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Generate the Verilog code corresponding to this FIRRTL code module BreakpointUnit_2 :
input clock : Clock
input reset : Reset
output io : { flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[0], flip pc : UInt<39>, flip ea : UInt<39>, flip mcontext : UInt<0>, flip scontext : UInt<0>, xcpt_if : UInt<1>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, debug_if : UInt<1>, debug_ld : UInt<1>, debug_st : UInt<1>, bpwatch : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[0]}
connect io.xcpt_if, UInt<1>(0h0)
connect io.xcpt_ld, UInt<1>(0h0)
connect io.xcpt_st, UInt<1>(0h0)
connect io.debug_if, UInt<1>(0h0)
connect io.debug_ld, UInt<1>(0h0)
connect io.debug_st, UInt<1>(0h0) | module BreakpointUnit_2( // @[Breakpoint.scala:79:7]
input clock, // @[Breakpoint.scala:79:7]
input reset, // @[Breakpoint.scala:79:7]
input io_status_debug, // @[Breakpoint.scala:80:14]
input io_status_cease, // @[Breakpoint.scala:80:14]
input io_status_wfi, // @[Breakpoint.scala:80:14]
input [1:0] io_status_dprv, // @[Breakpoint.scala:80:14]
input io_status_dv, // @[Breakpoint.scala:80:14]
input [1:0] io_status_prv, // @[Breakpoint.scala:80:14]
input io_status_v, // @[Breakpoint.scala:80:14]
input io_status_sd, // @[Breakpoint.scala:80:14]
input io_status_mpv, // @[Breakpoint.scala:80:14]
input io_status_gva, // @[Breakpoint.scala:80:14]
input io_status_tsr, // @[Breakpoint.scala:80:14]
input io_status_tw, // @[Breakpoint.scala:80:14]
input io_status_tvm, // @[Breakpoint.scala:80:14]
input io_status_mxr, // @[Breakpoint.scala:80:14]
input io_status_sum, // @[Breakpoint.scala:80:14]
input io_status_mprv, // @[Breakpoint.scala:80:14]
input [1:0] io_status_fs, // @[Breakpoint.scala:80:14]
input [1:0] io_status_mpp, // @[Breakpoint.scala:80:14]
input io_status_spp, // @[Breakpoint.scala:80:14]
input io_status_mpie, // @[Breakpoint.scala:80:14]
input io_status_spie, // @[Breakpoint.scala:80:14]
input io_status_mie, // @[Breakpoint.scala:80:14]
input io_status_sie, // @[Breakpoint.scala:80:14]
input [38:0] io_pc // @[Breakpoint.scala:80:14]
);
wire io_status_debug_0 = io_status_debug; // @[Breakpoint.scala:79:7]
wire io_status_cease_0 = io_status_cease; // @[Breakpoint.scala:79:7]
wire io_status_wfi_0 = io_status_wfi; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_dprv_0 = io_status_dprv; // @[Breakpoint.scala:79:7]
wire io_status_dv_0 = io_status_dv; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_prv_0 = io_status_prv; // @[Breakpoint.scala:79:7]
wire io_status_v_0 = io_status_v; // @[Breakpoint.scala:79:7]
wire io_status_sd_0 = io_status_sd; // @[Breakpoint.scala:79:7]
wire io_status_mpv_0 = io_status_mpv; // @[Breakpoint.scala:79:7]
wire io_status_gva_0 = io_status_gva; // @[Breakpoint.scala:79:7]
wire io_status_tsr_0 = io_status_tsr; // @[Breakpoint.scala:79:7]
wire io_status_tw_0 = io_status_tw; // @[Breakpoint.scala:79:7]
wire io_status_tvm_0 = io_status_tvm; // @[Breakpoint.scala:79:7]
wire io_status_mxr_0 = io_status_mxr; // @[Breakpoint.scala:79:7]
wire io_status_sum_0 = io_status_sum; // @[Breakpoint.scala:79:7]
wire io_status_mprv_0 = io_status_mprv; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_fs_0 = io_status_fs; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_mpp_0 = io_status_mpp; // @[Breakpoint.scala:79:7]
wire io_status_spp_0 = io_status_spp; // @[Breakpoint.scala:79:7]
wire io_status_mpie_0 = io_status_mpie; // @[Breakpoint.scala:79:7]
wire io_status_spie_0 = io_status_spie; // @[Breakpoint.scala:79:7]
wire io_status_mie_0 = io_status_mie; // @[Breakpoint.scala:79:7]
wire io_status_sie_0 = io_status_sie; // @[Breakpoint.scala:79:7]
wire [38:0] io_pc_0 = io_pc; // @[Breakpoint.scala:79:7]
wire [38:0] io_ea = 39'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_sxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_uxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_xs = 2'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_vs = 2'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [7:0] io_status_zero1 = 8'h0; // @[Breakpoint.scala:79:7, :80:14]
wire io_status_mbe = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sbe = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sd_rv32 = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_ube = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_upie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_hie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_uie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_if = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_ld = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_st = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_if = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_ld = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_st = 1'h0; // @[Breakpoint.scala:79:7]
wire [22:0] io_status_zero2 = 23'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [31:0] io_status_isa = 32'h14112D; // @[Breakpoint.scala:79:7, :80:14]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_14 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0hfc)))
node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0)
node sAdjustedExp = cvt(_sAdjustedExp_T_1)
node adjustedSig = shl(io.in.sig, 25)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _common_expOut_T = bits(sAdjustedExp, 8, 0)
node _common_expOut_T_1 = add(_common_expOut_T, UInt<1>(0h0))
node _common_expOut_T_2 = tail(_common_expOut_T_1, 1)
connect common_expOut, _common_expOut_T_2
node _common_fractOut_T = bits(adjustedSig, 25, 3)
node _common_fractOut_T_1 = bits(adjustedSig, 24, 2)
node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
connect common_overflow, UInt<1>(0h0)
connect common_totalUnderflow, UInt<1>(0h0)
connect common_underflow, UInt<1>(0h0)
connect common_inexact, UInt<1>(0h0)
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_14(); // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22]
wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28]
wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23]
wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23]
wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23]
wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23]
wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23]
wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53]
wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]
wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]
wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]
wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34]
wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49]
wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32]
wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32]
wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43]
wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28]
wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45]
wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32]
wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22]
wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32]
wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22]
wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_47 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0)
node _source_ok_T = shr(io.in.a.bits.source, 11)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits = bits(_uncommonBits_T, 10, 0)
node _T_4 = shr(io.in.a.bits.source, 11)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<11>(0h40f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0)
node _T_24 = shr(io.in.a.bits.source, 11)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0)
node _T_86 = shr(io.in.a.bits.source, 11)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0)
node _T_152 = shr(io.in.a.bits.source, 11)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0)
node _T_199 = shr(io.in.a.bits.source, 11)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0)
node _T_240 = shr(io.in.a.bits.source, 11)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0)
node _T_283 = shr(io.in.a.bits.source, 11)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0)
node _T_321 = shr(io.in.a.bits.source, 11)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0)
node _T_359 = shr(io.in.a.bits.source, 11)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 11)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<21>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<21>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1040>
connect a_set, UInt<1040>(0h0)
wire a_set_wo_ready : UInt<1040>
connect a_set_wo_ready, UInt<1040>(0h0)
wire a_opcodes_set : UInt<4160>
connect a_opcodes_set, UInt<4160>(0h0)
wire a_sizes_set : UInt<4160>
connect a_sizes_set, UInt<4160>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1040>
connect d_clr, UInt<1040>(0h0)
wire d_clr_wo_ready : UInt<1040>
connect d_clr_wo_ready, UInt<1040>(0h0)
wire d_opcodes_clr : UInt<4160>
connect d_opcodes_clr, UInt<4160>(0h0)
wire d_sizes_clr : UInt<4160>
connect d_sizes_clr, UInt<4160>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_96
node _T_656 = orr(inflight)
node _T_657 = eq(_T_656, UInt<1>(0h0))
node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_659 = or(_T_657, _T_658)
node _T_660 = lt(watchdog, plusarg_reader.out)
node _T_661 = or(_T_659, _T_660)
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_661, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_665 = and(io.in.a.ready, io.in.a.valid)
node _T_666 = and(io.in.d.ready, io.in.d.valid)
node _T_667 = or(_T_665, _T_666)
when _T_667 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<21>(0h0)
connect _c_first_WIRE.bits.source, UInt<11>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1040>
connect c_set, UInt<1040>(0h0)
wire c_set_wo_ready : UInt<1040>
connect c_set_wo_ready, UInt<1040>(0h0)
wire c_opcodes_set : UInt<4160>
connect c_opcodes_set, UInt<4160>(0h0)
wire c_sizes_set : UInt<4160>
connect c_sizes_set, UInt<4160>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<21>(0h0)
connect _WIRE_6.bits.source, UInt<11>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_668 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<21>(0h0)
connect _WIRE_8.bits.source, UInt<11>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_671 = and(_T_669, _T_670)
node _T_672 = and(_T_668, _T_671)
when _T_672 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<21>(0h0)
connect _WIRE_10.bits.source, UInt<11>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_674 = and(_T_673, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<21>(0h0)
connect _WIRE_12.bits.source, UInt<11>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_677 = and(_T_675, _T_676)
node _T_678 = and(_T_674, _T_677)
when _T_678 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<21>(0h0)
connect _WIRE_14.bits.source, UInt<11>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_679 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_680 = bits(_T_679, 0, 0)
node _T_681 = eq(_T_680, UInt<1>(0h0))
node _T_682 = asUInt(reset)
node _T_683 = eq(_T_682, UInt<1>(0h0))
when _T_683 :
node _T_684 = eq(_T_681, UInt<1>(0h0))
when _T_684 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_681, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1040>
connect d_clr_1, UInt<1040>(0h0)
wire d_clr_wo_ready_1 : UInt<1040>
connect d_clr_wo_ready_1, UInt<1040>(0h0)
wire d_opcodes_clr_1 : UInt<4160>
connect d_opcodes_clr_1, UInt<4160>(0h0)
wire d_sizes_clr_1 : UInt<4160>
connect d_sizes_clr_1, UInt<4160>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_685 = and(io.in.d.valid, d_first_2)
node _T_686 = and(_T_685, UInt<1>(0h1))
node _T_687 = and(_T_686, d_release_ack_1)
when _T_687 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_688 = and(io.in.d.ready, io.in.d.valid)
node _T_689 = and(_T_688, d_first_2)
node _T_690 = and(_T_689, UInt<1>(0h1))
node _T_691 = and(_T_690, d_release_ack_1)
when _T_691 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_695 = dshr(inflight_1, io.in.d.bits.source)
node _T_696 = bits(_T_695, 0, 0)
node _T_697 = or(_T_696, same_cycle_resp_1)
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_697, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<21>(0h0)
connect _WIRE_16.bits.source, UInt<11>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_702 = asUInt(reset)
node _T_703 = eq(_T_702, UInt<1>(0h0))
when _T_703 :
node _T_704 = eq(_T_701, UInt<1>(0h0))
when _T_704 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_701, UInt<1>(0h1), "") : assert_108
else :
node _T_705 = eq(io.in.d.bits.size, c_size_lookup)
node _T_706 = asUInt(reset)
node _T_707 = eq(_T_706, UInt<1>(0h0))
when _T_707 :
node _T_708 = eq(_T_705, UInt<1>(0h0))
when _T_708 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_705, UInt<1>(0h1), "") : assert_109
node _T_709 = and(io.in.d.valid, d_first_2)
node _T_710 = and(_T_709, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<21>(0h0)
connect _WIRE_18.bits.source, UInt<11>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_711 = and(_T_710, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<21>(0h0)
connect _WIRE_20.bits.source, UInt<11>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_713 = and(_T_711, _T_712)
node _T_714 = and(_T_713, d_release_ack_1)
node _T_715 = eq(c_probe_ack, UInt<1>(0h0))
node _T_716 = and(_T_714, _T_715)
when _T_716 :
node _T_717 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<21>(0h0)
connect _WIRE_22.bits.source, UInt<11>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_718 = or(_T_717, _WIRE_23.ready)
node _T_719 = asUInt(reset)
node _T_720 = eq(_T_719, UInt<1>(0h0))
when _T_720 :
node _T_721 = eq(_T_718, UInt<1>(0h0))
when _T_721 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_718, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_97
node _T_722 = orr(inflight_1)
node _T_723 = eq(_T_722, UInt<1>(0h0))
node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_725 = or(_T_723, _T_724)
node _T_726 = lt(watchdog_1, plusarg_reader_1.out)
node _T_727 = or(_T_725, _T_726)
node _T_728 = asUInt(reset)
node _T_729 = eq(_T_728, UInt<1>(0h0))
when _T_729 :
node _T_730 = eq(_T_727, UInt<1>(0h0))
when _T_730 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_727, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<21>(0h0)
connect _WIRE_24.bits.source, UInt<11>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_732 = and(io.in.d.ready, io.in.d.valid)
node _T_733 = or(_T_731, _T_732)
when _T_733 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_47( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52]
wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79]
wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77]
wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35]
wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35]
wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34]
wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34]
wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34]
wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_665; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_733; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [1039:0] a_set; // @[Monitor.scala:626:34]
wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [1039:0] d_clr; // @[Monitor.scala:664:34]
wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [1039:0] d_clr_1; // @[Monitor.scala:774:34]
wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113]
wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_34 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node adjustedSig = shl(io.in.sig, 0)
node doShiftSigDown1 = bits(adjustedSig, 26, 26)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _roundMask_T = bits(io.in.sExp, 8, 0)
node _roundMask_T_1 = not(_roundMask_T)
node roundMask_msb = bits(_roundMask_T_1, 8, 8)
node roundMask_lsbs = bits(_roundMask_T_1, 7, 0)
node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7)
node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0)
node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2)
node _roundMask_T_2 = bits(roundMask_shift, 63, 42)
node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0)
node _roundMask_T_4 = shl(UInt<8>(0hff), 8)
node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4)
node _roundMask_T_6 = shr(_roundMask_T_3, 8)
node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5)
node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0)
node _roundMask_T_9 = shl(_roundMask_T_8, 8)
node _roundMask_T_10 = not(_roundMask_T_5)
node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10)
node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11)
node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0)
node _roundMask_T_14 = shl(_roundMask_T_13, 4)
node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14)
node _roundMask_T_16 = shr(_roundMask_T_12, 4)
node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15)
node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0)
node _roundMask_T_19 = shl(_roundMask_T_18, 4)
node _roundMask_T_20 = not(_roundMask_T_15)
node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20)
node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21)
node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0)
node _roundMask_T_24 = shl(_roundMask_T_23, 2)
node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24)
node _roundMask_T_26 = shr(_roundMask_T_22, 2)
node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25)
node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0)
node _roundMask_T_29 = shl(_roundMask_T_28, 2)
node _roundMask_T_30 = not(_roundMask_T_25)
node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30)
node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31)
node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0)
node _roundMask_T_34 = shl(_roundMask_T_33, 1)
node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34)
node _roundMask_T_36 = shr(_roundMask_T_32, 1)
node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35)
node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0)
node _roundMask_T_39 = shl(_roundMask_T_38, 1)
node _roundMask_T_40 = not(_roundMask_T_35)
node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40)
node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41)
node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16)
node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0)
node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0)
node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0)
node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1)
node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47)
node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2)
node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0)
node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1)
node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51)
node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52)
node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4)
node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0)
node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1)
node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56)
node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57)
node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58)
node _roundMask_T_60 = not(_roundMask_T_59)
node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60)
node _roundMask_T_62 = not(_roundMask_T_61)
node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7))
node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3)
node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0)
node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0)
node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0)
node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1)
node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67)
node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2)
node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69)
node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0))
node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71)
node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0))
node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1)
node roundMask = cat(_roundMask_T_74, UInt<2>(0h3))
node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask)
node shiftedRoundMask = shr(_shiftedRoundMask_T, 1)
node _roundPosMask_T = not(shiftedRoundMask)
node roundPosMask = and(_roundPosMask_T, roundMask)
node _roundPosBit_T = and(adjustedSig, roundPosMask)
node roundPosBit = orr(_roundPosBit_T)
node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask)
node anyRoundExtra = orr(_anyRoundExtra_T)
node anyRound = or(roundPosBit, anyRoundExtra)
node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit)
node _roundIncr_T_2 = and(roundMagUp, anyRound)
node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2)
node _roundedSig_T = or(adjustedSig, roundMask)
node _roundedSig_T_1 = shr(_roundedSig_T, 2)
node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1))
node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit)
node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0))
node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4)
node _roundedSig_T_6 = shr(roundMask, 1)
node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0))
node _roundedSig_T_8 = not(_roundedSig_T_7)
node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8)
node _roundedSig_T_10 = not(roundMask)
node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10)
node _roundedSig_T_12 = shr(_roundedSig_T_11, 2)
node _roundedSig_T_13 = and(roundingMode_odd, anyRound)
node _roundedSig_T_14 = shr(roundPosMask, 1)
node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0))
node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15)
node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16)
node _sRoundedExp_T = shr(roundedSig, 24)
node _sRoundedExp_T_1 = cvt(_sRoundedExp_T)
node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1)
node _common_expOut_T = bits(sRoundedExp, 8, 0)
connect common_expOut, _common_expOut_T
node _common_fractOut_T = bits(roundedSig, 23, 1)
node _common_fractOut_T_1 = bits(roundedSig, 22, 0)
node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
node _common_overflow_T = shr(sRoundedExp, 7)
node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3)))
connect common_overflow, _common_overflow_T_1
node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b)))
connect common_totalUnderflow, _common_totalUnderflow_T
node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2)
node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1)
node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1)
node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2)
node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T)
node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0)
node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2)
node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3)
node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit)
node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound)
node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2)
node _roundCarry_T = bits(roundedSig, 25, 25)
node _roundCarry_T_1 = bits(roundedSig, 24, 24)
node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1)
node _common_underflow_T = shr(io.in.sExp, 8)
node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0)))
node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1)
node _common_underflow_T_3 = bits(roundMask, 3, 3)
node _common_underflow_T_4 = bits(roundMask, 2, 2)
node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4)
node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5)
node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1))
node _common_underflow_T_8 = bits(roundMask, 4, 4)
node _common_underflow_T_9 = bits(roundMask, 3, 3)
node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9)
node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0))
node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11)
node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry)
node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit)
node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr)
node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0))
node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16)
node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17)
connect common_underflow, _common_underflow_T_18
node _common_inexact_T = or(common_totalUnderflow, anyRound)
connect common_inexact, _common_inexact_T
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_34( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20]
wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53]
wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38]
wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29]
wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42]
wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25]
wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26]
wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56]
wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22]
wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22]
wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20]
wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20]
wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20]
wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20]
wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20]
wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20]
wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}]
wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}]
wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17]
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56]
wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22]
wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20]
wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20]
wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20]
wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58]
wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24]
wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24]
wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67]
wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49]
wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31]
wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}]
wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46]
wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]
wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]
wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]
wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]
wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s1k3z4u :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_67
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a32d64s1k3z4u
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a32d64s1k3z4u
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits.sink, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_10.bits.sink, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLBuffer_a32d64s1k3z4u( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_a_bits_source = 1'h0; // @[Decoupled.scala:362:21]
wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_bits_source = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire [2:0] auto_in_a_bits_param = 3'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_a_bits_param = 3'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
TLMonitor_67 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d64s1k3z4u nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d64s1k3z4u nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MSHR_3 :
input clock : Clock
input reset : Reset
output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<8>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<8>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<8>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}}
regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock
regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<8>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock
when meta_valid :
node _T = eq(meta.state, UInt<2>(0h0))
when _T :
node _T_1 = orr(meta.clients)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _T_6 = eq(meta.dirty, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = eq(meta.state, UInt<2>(0h1))
when _T_10 :
node _T_11 = eq(meta.dirty, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = eq(meta.state, UInt<2>(0h2))
when _T_15 :
node _T_16 = orr(meta.clients)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = sub(meta.clients, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = and(meta.clients, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4
assert(clock, _T_23, UInt<1>(0h1), "") : assert_4
node _T_27 = eq(meta.state, UInt<2>(0h3))
when _T_27 :
skip
regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1)
reg sink : UInt<3>, clock
reg gotT : UInt<1>, clock
reg bad_grant : UInt<1>, clock
reg probes_done : UInt<8>, clock
reg probes_toN : UInt<8>, clock
reg probes_noT : UInt<1>, clock
node _T_28 = neq(meta.state, UInt<2>(0h0))
node _T_29 = and(meta_valid, _T_28)
node _T_30 = eq(io.nestedwb.set, request.set)
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.nestedwb.tag, meta.tag)
node _T_33 = and(_T_31, _T_32)
when _T_33 :
when io.nestedwb.b_clr_dirty :
connect meta.dirty, UInt<1>(0h0)
when io.nestedwb.c_set_dirty :
connect meta.dirty, UInt<1>(0h1)
when io.nestedwb.b_toB :
connect meta.state, UInt<2>(0h1)
when io.nestedwb.b_toN :
connect meta.hit, UInt<1>(0h0)
connect io.status.valid, request_valid
connect io.status.bits.set, request.set
connect io.status.bits.tag, request.tag
connect io.status.bits.way, meta.way
node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0))
node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0))
node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2)
node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4)
node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6)
node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7)
connect io.status.bits.blockB, _io_status_bits_blockB_T_8
node _io_status_bits_nestB_T = and(meta_valid, w_releaseack)
node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast)
node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast)
node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3)
connect io.status.bits.nestB, _io_status_bits_nestB_T_4
node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0))
connect io.status.bits.blockC, _io_status_bits_blockC_T
node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1)
node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3)
node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4)
connect io.status.bits.nestC, _io_status_bits_nestC_T_5
node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0))
node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5
assert(clock, _T_36, UInt<1>(0h1), "") : assert_5
node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0))
node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6
assert(clock, _T_42, UInt<1>(0h1), "") : assert_6
node _no_wait_T = and(w_rprobeacklast, w_releaseack)
node _no_wait_T_1 = and(_no_wait_T, w_grantlast)
node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast)
node no_wait = and(_no_wait_T_2, w_grantack)
node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0))
node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release)
node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe)
connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2
node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1)
connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2
node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst)
node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst)
node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3)
connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4
node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0))
node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack)
node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant)
connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2
node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0))
node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst)
connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1
node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0))
node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack)
connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1
node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst)
node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait)
node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3)
connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4
connect io.schedule.bits.reload, no_wait
node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid)
node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid)
node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid)
node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid)
node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid)
node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid)
connect io.schedule.valid, _io_schedule_valid_T_5
when io.schedule.ready :
connect s_rprobe, UInt<1>(0h1)
when w_rprobeackfirst :
connect s_release, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
node _T_46 = and(s_release, s_pprobe)
when _T_46 :
connect s_acquire, UInt<1>(0h1)
when w_releaseack :
connect s_flush, UInt<1>(0h1)
when w_pprobeackfirst :
connect s_probeack, UInt<1>(0h1)
when w_grantfirst :
connect s_grantack, UInt<1>(0h1)
node _T_47 = and(w_pprobeack, w_grant)
when _T_47 :
connect s_execute, UInt<1>(0h1)
when no_wait :
connect s_writeback, UInt<1>(0h1)
when no_wait :
connect request_valid, UInt<1>(0h0)
connect meta_valid, UInt<1>(0h0)
wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<8>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}
connect final_meta_writeback, meta
node _req_clientBit_T = eq(request.source, UInt<6>(0h3c))
node _req_clientBit_T_1 = eq(request.source, UInt<6>(0h38))
node _req_clientBit_T_2 = eq(request.source, UInt<6>(0h34))
node _req_clientBit_T_3 = eq(request.source, UInt<6>(0h30))
node _req_clientBit_T_4 = eq(request.source, UInt<6>(0h2c))
node _req_clientBit_T_5 = eq(request.source, UInt<6>(0h28))
node _req_clientBit_T_6 = eq(request.source, UInt<6>(0h24))
node _req_clientBit_T_7 = eq(request.source, UInt<6>(0h20))
node req_clientBit_lo_lo = cat(_req_clientBit_T_1, _req_clientBit_T)
node req_clientBit_lo_hi = cat(_req_clientBit_T_3, _req_clientBit_T_2)
node req_clientBit_lo = cat(req_clientBit_lo_hi, req_clientBit_lo_lo)
node req_clientBit_hi_lo = cat(_req_clientBit_T_5, _req_clientBit_T_4)
node req_clientBit_hi_hi = cat(_req_clientBit_T_7, _req_clientBit_T_6)
node req_clientBit_hi = cat(req_clientBit_hi_hi, req_clientBit_hi_lo)
node req_clientBit = cat(req_clientBit_hi, req_clientBit_lo)
node _req_needT_T = bits(request.opcode, 2, 2)
node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0))
node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5))
node _req_needT_T_3 = eq(request.param, UInt<1>(0h1))
node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3)
node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4)
node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6))
node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7))
node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7)
node _req_needT_T_9 = neq(request.param, UInt<2>(0h0))
node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9)
node req_needT = or(_req_needT_T_5, _req_needT_T_10)
node _req_acquire_T = eq(request.opcode, UInt<3>(0h6))
node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7))
node req_acquire = or(_req_acquire_T, _req_acquire_T_1)
node _meta_no_clients_T = orr(meta.clients)
node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0))
node _req_promoteT_T = eq(meta.state, UInt<2>(0h3))
node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T)
node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT)
node req_promoteT = and(req_acquire, _req_promoteT_T_2)
node _T_48 = and(request.prio[2], UInt<1>(0h1))
when _T_48 :
node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0)
node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1
node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3))
node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2))
node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1)
node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state)
connect final_meta_writeback.state, _final_meta_writeback_state_T_3
node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1))
node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2))
node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1)
node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5))
node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3)
node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5)
node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7
connect final_meta_writeback.hit, UInt<1>(0h1)
else :
node _T_49 = and(request.control, UInt<1>(0h1))
when _T_49 :
when meta.hit :
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
node _final_meta_writeback_clients_T_8 = not(probes_toN)
node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9
connect final_meta_writeback.hit, UInt<1>(0h0)
else :
node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty)
node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2)
node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0))
node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5
node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0))
node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1))
node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire)
node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state)
node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1))
node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state)
node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11)
node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state)
node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13)
node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15)
node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16)
connect final_meta_writeback.state, _final_meta_writeback_state_T_17
node _final_meta_writeback_clients_T_10 = not(probes_toN)
node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10)
node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0))
node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14
connect final_meta_writeback.tag, request.tag
connect final_meta_writeback.hit, UInt<1>(0h1)
when bad_grant :
when meta.hit :
node _T_50 = eq(meta_valid, UInt<1>(0h0))
node _T_51 = eq(meta.state, UInt<2>(0h1))
node _T_52 = or(_T_50, _T_51)
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7
assert(clock, _T_52, UInt<1>(0h1), "") : assert_7
connect final_meta_writeback.hit, UInt<1>(0h1)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h1)
node _final_meta_writeback_clients_T_15 = not(probes_toN)
node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16
else :
connect final_meta_writeback.hit, UInt<1>(0h0)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
connect final_meta_writeback.clients, UInt<1>(0h0)
wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<8>, tag : UInt<13>}
connect invalid.dirty, UInt<1>(0h0)
connect invalid.state, UInt<2>(0h0)
connect invalid.clients, UInt<1>(0h0)
connect invalid.tag, UInt<1>(0h0)
node _honour_BtoT_T = and(meta.clients, req_clientBit)
node _honour_BtoT_T_1 = orr(_honour_BtoT_T)
node honour_BtoT = and(meta.hit, _honour_BtoT_T_1)
node _excluded_client_T = and(meta.hit, request.prio[0])
node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6))
node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7))
node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2)
node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4))
node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4)
node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5))
node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0))
node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7)
node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8)
node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0))
connect io.schedule.bits.a.bits.tag, request.tag
connect io.schedule.bits.a.bits.set, request.set
node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0))
connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1
node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6))
node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7))
node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2)
node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4)
connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5
connect io.schedule.bits.a.bits.source, UInt<1>(0h0)
node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1)
node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2)
connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3
node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag)
connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1
connect io.schedule.bits.b.bits.set, request.set
node _io_schedule_bits_b_bits_clients_T = not(excluded_client)
node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T)
connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1
node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6))
connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T
node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1))
node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1))
connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1
connect io.schedule.bits.c.bits.source, UInt<1>(0h0)
connect io.schedule.bits.c.bits.tag, meta.tag
connect io.schedule.bits.c.bits.set, request.set
connect io.schedule.bits.c.bits.way, meta.way
connect io.schedule.bits.c.bits.dirty, meta.dirty
connect io.schedule.bits.d.bits.set, request.set
connect io.schedule.bits.d.bits.put, request.put
connect io.schedule.bits.d.bits.offset, request.offset
connect io.schedule.bits.d.bits.tag, request.tag
connect io.schedule.bits.d.bits.source, request.source
connect io.schedule.bits.d.bits.size, request.size
connect io.schedule.bits.d.bits.param, request.param
connect io.schedule.bits.d.bits.opcode, request.opcode
connect io.schedule.bits.d.bits.control, request.control
connect io.schedule.bits.d.bits.prio, request.prio
node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0))
node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0))
node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param)
node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param)
node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param)
node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4)
node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param)
node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6)
node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8)
connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9
connect io.schedule.bits.d.bits.sink, UInt<1>(0h0)
connect io.schedule.bits.d.bits.way, meta.way
connect io.schedule.bits.d.bits.bad, bad_grant
connect io.schedule.bits.e.bits.sink, sink
connect io.schedule.bits.x.bits.fail, UInt<1>(0h0)
connect io.schedule.bits.dir.bits.set, request.set
connect io.schedule.bits.dir.bits.way, meta.way
node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0))
wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<8>, tag : UInt<13>}
connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag
connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients
connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state
connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty
node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE)
connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1
node _evict_T = eq(meta.hit, UInt<1>(0h0))
wire evict : UInt
connect evict, UInt<1>(0h0)
node evict_c = orr(meta.clients)
node _evict_T_1 = eq(UInt<2>(0h1), meta.state)
when _evict_T_1 :
node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1))
connect evict, _evict_out_T
else :
node _evict_T_2 = eq(UInt<2>(0h2), meta.state)
when _evict_T_2 :
node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect evict, _evict_out_T_1
else :
node _evict_T_3 = eq(UInt<2>(0h3), meta.state)
when _evict_T_3 :
node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3)
connect evict, _evict_out_T_4
else :
node _evict_T_4 = eq(UInt<2>(0h0), meta.state)
when _evict_T_4 :
connect evict, UInt<4>(0h8)
node _evict_T_5 = eq(_evict_T, UInt<1>(0h0))
when _evict_T_5 :
connect evict, UInt<4>(0h8)
wire before : UInt
connect before, UInt<1>(0h0)
node before_c = orr(meta.clients)
node _before_T = eq(UInt<2>(0h1), meta.state)
when _before_T :
node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1))
connect before, _before_out_T
else :
node _before_T_1 = eq(UInt<2>(0h2), meta.state)
when _before_T_1 :
node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect before, _before_out_T_1
else :
node _before_T_2 = eq(UInt<2>(0h3), meta.state)
when _before_T_2 :
node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3)
connect before, _before_out_T_4
else :
node _before_T_3 = eq(UInt<2>(0h0), meta.state)
when _before_T_3 :
connect before, UInt<4>(0h8)
node _before_T_4 = eq(meta.hit, UInt<1>(0h0))
when _before_T_4 :
connect before, UInt<4>(0h8)
wire after : UInt
connect after, UInt<1>(0h0)
node after_c = orr(final_meta_writeback.clients)
node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _after_T :
node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1))
connect after, _after_out_T
else :
node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _after_T_1 :
node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect after, _after_out_T_1
else :
node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _after_T_2 :
node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3)
connect after, _after_out_T_4
else :
node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _after_T_3 :
connect after, UInt<4>(0h8)
node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _after_T_4 :
connect after, UInt<4>(0h8)
node _T_56 = eq(s_release, UInt<1>(0h0))
node _T_57 = and(_T_56, w_rprobeackfirst)
node _T_58 = and(_T_57, io.schedule.ready)
when _T_58 :
node _T_59 = eq(evict, UInt<1>(0h1))
node _T_60 = eq(_T_59, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8
assert(clock, _T_60, UInt<1>(0h1), "") : assert_8
node _T_64 = eq(before, UInt<1>(0h1))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(evict, UInt<1>(0h0))
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10
assert(clock, _T_70, UInt<1>(0h1), "") : assert_10
node _T_74 = eq(before, UInt<1>(0h0))
node _T_75 = eq(_T_74, UInt<1>(0h0))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11
assert(clock, _T_75, UInt<1>(0h1), "") : assert_11
node _T_79 = eq(evict, UInt<3>(0h7))
node _T_80 = eq(before, UInt<3>(0h7))
node _T_81 = eq(evict, UInt<3>(0h5))
node _T_82 = eq(before, UInt<3>(0h5))
node _T_83 = eq(evict, UInt<3>(0h4))
node _T_84 = eq(before, UInt<3>(0h4))
node _T_85 = eq(evict, UInt<3>(0h6))
node _T_86 = eq(before, UInt<3>(0h6))
node _T_87 = eq(evict, UInt<2>(0h3))
node _T_88 = eq(before, UInt<2>(0h3))
node _T_89 = eq(evict, UInt<2>(0h2))
node _T_90 = eq(before, UInt<2>(0h2))
node _T_91 = eq(s_writeback, UInt<1>(0h0))
node _T_92 = and(_T_91, no_wait)
node _T_93 = and(_T_92, io.schedule.ready)
when _T_93 :
node _T_94 = eq(before, UInt<4>(0h8))
node _T_95 = eq(after, UInt<1>(0h1))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12
assert(clock, _T_97, UInt<1>(0h1), "") : assert_12
node _T_101 = eq(before, UInt<4>(0h8))
node _T_102 = eq(after, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13
assert(clock, _T_104, UInt<1>(0h1), "") : assert_13
node _T_108 = eq(before, UInt<4>(0h8))
node _T_109 = eq(after, UInt<3>(0h7))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(before, UInt<4>(0h8))
node _T_112 = eq(after, UInt<3>(0h5))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(_T_113, UInt<1>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14
assert(clock, _T_114, UInt<1>(0h1), "") : assert_14
node _T_118 = eq(before, UInt<4>(0h8))
node _T_119 = eq(after, UInt<3>(0h4))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15
assert(clock, _T_121, UInt<1>(0h1), "") : assert_15
node _T_125 = eq(before, UInt<4>(0h8))
node _T_126 = eq(after, UInt<3>(0h6))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(before, UInt<4>(0h8))
node _T_129 = eq(after, UInt<2>(0h3))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(before, UInt<4>(0h8))
node _T_132 = eq(after, UInt<2>(0h2))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16
assert(clock, _T_134, UInt<1>(0h1), "") : assert_16
node _T_138 = eq(before, UInt<1>(0h1))
node _T_139 = eq(after, UInt<4>(0h8))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(_T_140, UInt<1>(0h0))
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17
assert(clock, _T_141, UInt<1>(0h1), "") : assert_17
node _T_145 = eq(before, UInt<1>(0h1))
node _T_146 = eq(after, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(_T_147, UInt<1>(0h0))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18
assert(clock, _T_148, UInt<1>(0h1), "") : assert_18
node _T_152 = eq(before, UInt<1>(0h1))
node _T_153 = eq(after, UInt<3>(0h7))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(_T_154, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19
assert(clock, _T_155, UInt<1>(0h1), "") : assert_19
node _T_159 = eq(before, UInt<1>(0h1))
node _T_160 = eq(after, UInt<3>(0h5))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(_T_161, UInt<1>(0h0))
node _T_163 = asUInt(reset)
node _T_164 = eq(_T_163, UInt<1>(0h0))
when _T_164 :
node _T_165 = eq(_T_162, UInt<1>(0h0))
when _T_165 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20
assert(clock, _T_162, UInt<1>(0h1), "") : assert_20
node _T_166 = eq(before, UInt<1>(0h1))
node _T_167 = eq(after, UInt<3>(0h4))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21
assert(clock, _T_169, UInt<1>(0h1), "") : assert_21
node _T_173 = eq(before, UInt<1>(0h1))
node _T_174 = eq(after, UInt<3>(0h6))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(_T_175, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22
assert(clock, _T_176, UInt<1>(0h1), "") : assert_22
node _T_180 = eq(before, UInt<1>(0h1))
node _T_181 = eq(after, UInt<2>(0h3))
node _T_182 = and(_T_180, _T_181)
node _T_183 = eq(_T_182, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(before, UInt<1>(0h1))
node _T_188 = eq(after, UInt<2>(0h2))
node _T_189 = and(_T_187, _T_188)
node _T_190 = eq(_T_189, UInt<1>(0h0))
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(_T_190, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24
assert(clock, _T_190, UInt<1>(0h1), "") : assert_24
node _T_194 = eq(before, UInt<1>(0h0))
node _T_195 = eq(after, UInt<4>(0h8))
node _T_196 = and(_T_194, _T_195)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25
assert(clock, _T_197, UInt<1>(0h1), "") : assert_25
node _T_201 = eq(before, UInt<1>(0h0))
node _T_202 = eq(after, UInt<1>(0h1))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26
assert(clock, _T_204, UInt<1>(0h1), "") : assert_26
node _T_208 = eq(before, UInt<1>(0h0))
node _T_209 = eq(after, UInt<3>(0h7))
node _T_210 = and(_T_208, _T_209)
node _T_211 = eq(_T_210, UInt<1>(0h0))
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27
assert(clock, _T_211, UInt<1>(0h1), "") : assert_27
node _T_215 = eq(before, UInt<1>(0h0))
node _T_216 = eq(after, UInt<3>(0h5))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(_T_217, UInt<1>(0h0))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28
assert(clock, _T_218, UInt<1>(0h1), "") : assert_28
node _T_222 = eq(before, UInt<1>(0h0))
node _T_223 = eq(after, UInt<3>(0h6))
node _T_224 = and(_T_222, _T_223)
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29
assert(clock, _T_225, UInt<1>(0h1), "") : assert_29
node _T_229 = eq(before, UInt<1>(0h0))
node _T_230 = eq(after, UInt<3>(0h4))
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(before, UInt<1>(0h0))
node _T_237 = eq(after, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31
assert(clock, _T_239, UInt<1>(0h1), "") : assert_31
node _T_243 = eq(before, UInt<1>(0h0))
node _T_244 = eq(after, UInt<2>(0h2))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(_T_245, UInt<1>(0h0))
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32
assert(clock, _T_246, UInt<1>(0h1), "") : assert_32
node _T_250 = eq(before, UInt<3>(0h7))
node _T_251 = eq(after, UInt<4>(0h8))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33
assert(clock, _T_253, UInt<1>(0h1), "") : assert_33
node _T_257 = eq(before, UInt<3>(0h7))
node _T_258 = eq(after, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(_T_259, UInt<1>(0h0))
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34
assert(clock, _T_260, UInt<1>(0h1), "") : assert_34
node _T_264 = eq(before, UInt<3>(0h7))
node _T_265 = eq(after, UInt<1>(0h0))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35
assert(clock, _T_267, UInt<1>(0h1), "") : assert_35
node _T_271 = eq(before, UInt<3>(0h7))
node _T_272 = eq(after, UInt<3>(0h5))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(_T_273, UInt<1>(0h0))
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36
assert(clock, _T_274, UInt<1>(0h1), "") : assert_36
node _T_278 = eq(before, UInt<3>(0h7))
node _T_279 = eq(after, UInt<3>(0h6))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(before, UInt<3>(0h7))
node _T_282 = eq(after, UInt<3>(0h4))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37
assert(clock, _T_284, UInt<1>(0h1), "") : assert_37
node _T_288 = eq(before, UInt<3>(0h7))
node _T_289 = eq(after, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(before, UInt<3>(0h7))
node _T_292 = eq(after, UInt<2>(0h2))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(_T_293, UInt<1>(0h0))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38
assert(clock, _T_294, UInt<1>(0h1), "") : assert_38
node _T_298 = eq(before, UInt<3>(0h5))
node _T_299 = eq(after, UInt<4>(0h8))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(_T_300, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39
assert(clock, _T_301, UInt<1>(0h1), "") : assert_39
node _T_305 = eq(before, UInt<3>(0h5))
node _T_306 = eq(after, UInt<1>(0h1))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(_T_307, UInt<1>(0h0))
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40
assert(clock, _T_308, UInt<1>(0h1), "") : assert_40
node _T_312 = eq(before, UInt<3>(0h5))
node _T_313 = eq(after, UInt<1>(0h0))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(_T_314, UInt<1>(0h0))
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(_T_315, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41
assert(clock, _T_315, UInt<1>(0h1), "") : assert_41
node _T_319 = eq(before, UInt<3>(0h5))
node _T_320 = eq(after, UInt<3>(0h7))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(before, UInt<3>(0h5))
node _T_323 = eq(after, UInt<3>(0h6))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(before, UInt<3>(0h5))
node _T_326 = eq(after, UInt<3>(0h4))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(_T_327, UInt<1>(0h0))
node _T_329 = asUInt(reset)
node _T_330 = eq(_T_329, UInt<1>(0h0))
when _T_330 :
node _T_331 = eq(_T_328, UInt<1>(0h0))
when _T_331 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42
assert(clock, _T_328, UInt<1>(0h1), "") : assert_42
node _T_332 = eq(before, UInt<3>(0h5))
node _T_333 = eq(after, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(before, UInt<3>(0h5))
node _T_336 = eq(after, UInt<2>(0h2))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(_T_337, UInt<1>(0h0))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43
assert(clock, _T_338, UInt<1>(0h1), "") : assert_43
node _T_342 = eq(before, UInt<3>(0h6))
node _T_343 = eq(after, UInt<4>(0h8))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(_T_344, UInt<1>(0h0))
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44
assert(clock, _T_345, UInt<1>(0h1), "") : assert_44
node _T_349 = eq(before, UInt<3>(0h6))
node _T_350 = eq(after, UInt<1>(0h1))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(_T_351, UInt<1>(0h0))
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(_T_352, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45
assert(clock, _T_352, UInt<1>(0h1), "") : assert_45
node _T_356 = eq(before, UInt<3>(0h6))
node _T_357 = eq(after, UInt<1>(0h0))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(_T_358, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46
assert(clock, _T_359, UInt<1>(0h1), "") : assert_46
node _T_363 = eq(before, UInt<3>(0h6))
node _T_364 = eq(after, UInt<3>(0h7))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47
assert(clock, _T_366, UInt<1>(0h1), "") : assert_47
node _T_370 = eq(before, UInt<3>(0h6))
node _T_371 = eq(after, UInt<3>(0h5))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(_T_372, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48
assert(clock, _T_373, UInt<1>(0h1), "") : assert_48
node _T_377 = eq(before, UInt<3>(0h6))
node _T_378 = eq(after, UInt<3>(0h4))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(_T_379, UInt<1>(0h0))
node _T_381 = asUInt(reset)
node _T_382 = eq(_T_381, UInt<1>(0h0))
when _T_382 :
node _T_383 = eq(_T_380, UInt<1>(0h0))
when _T_383 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49
assert(clock, _T_380, UInt<1>(0h1), "") : assert_49
node _T_384 = eq(before, UInt<3>(0h6))
node _T_385 = eq(after, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(_T_386, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50
assert(clock, _T_387, UInt<1>(0h1), "") : assert_50
node _T_391 = eq(before, UInt<3>(0h6))
node _T_392 = eq(after, UInt<2>(0h2))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(before, UInt<3>(0h4))
node _T_395 = eq(after, UInt<4>(0h8))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51
assert(clock, _T_397, UInt<1>(0h1), "") : assert_51
node _T_401 = eq(before, UInt<3>(0h4))
node _T_402 = eq(after, UInt<1>(0h1))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(_T_403, UInt<1>(0h0))
node _T_405 = asUInt(reset)
node _T_406 = eq(_T_405, UInt<1>(0h0))
when _T_406 :
node _T_407 = eq(_T_404, UInt<1>(0h0))
when _T_407 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52
assert(clock, _T_404, UInt<1>(0h1), "") : assert_52
node _T_408 = eq(before, UInt<3>(0h4))
node _T_409 = eq(after, UInt<1>(0h0))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(_T_410, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53
assert(clock, _T_411, UInt<1>(0h1), "") : assert_53
node _T_415 = eq(before, UInt<3>(0h4))
node _T_416 = eq(after, UInt<3>(0h7))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(_T_417, UInt<1>(0h0))
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54
assert(clock, _T_418, UInt<1>(0h1), "") : assert_54
node _T_422 = eq(before, UInt<3>(0h4))
node _T_423 = eq(after, UInt<3>(0h5))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = asUInt(reset)
node _T_427 = eq(_T_426, UInt<1>(0h0))
when _T_427 :
node _T_428 = eq(_T_425, UInt<1>(0h0))
when _T_428 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55
assert(clock, _T_425, UInt<1>(0h1), "") : assert_55
node _T_429 = eq(before, UInt<3>(0h4))
node _T_430 = eq(after, UInt<3>(0h6))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(before, UInt<3>(0h4))
node _T_433 = eq(after, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(_T_434, UInt<1>(0h0))
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56
assert(clock, _T_435, UInt<1>(0h1), "") : assert_56
node _T_439 = eq(before, UInt<3>(0h4))
node _T_440 = eq(after, UInt<2>(0h2))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(before, UInt<2>(0h3))
node _T_443 = eq(after, UInt<4>(0h8))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(_T_444, UInt<1>(0h0))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57
assert(clock, _T_445, UInt<1>(0h1), "") : assert_57
node _T_449 = eq(before, UInt<2>(0h3))
node _T_450 = eq(after, UInt<1>(0h1))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(_T_451, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58
assert(clock, _T_452, UInt<1>(0h1), "") : assert_58
node _T_456 = eq(before, UInt<2>(0h3))
node _T_457 = eq(after, UInt<1>(0h0))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59
assert(clock, _T_459, UInt<1>(0h1), "") : assert_59
node _T_463 = eq(before, UInt<2>(0h3))
node _T_464 = eq(after, UInt<3>(0h7))
node _T_465 = and(_T_463, _T_464)
node _T_466 = eq(before, UInt<2>(0h3))
node _T_467 = eq(after, UInt<3>(0h5))
node _T_468 = and(_T_466, _T_467)
node _T_469 = eq(before, UInt<2>(0h3))
node _T_470 = eq(after, UInt<3>(0h6))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(before, UInt<2>(0h3))
node _T_473 = eq(after, UInt<3>(0h4))
node _T_474 = and(_T_472, _T_473)
node _T_475 = eq(before, UInt<2>(0h3))
node _T_476 = eq(after, UInt<2>(0h2))
node _T_477 = and(_T_475, _T_476)
node _T_478 = eq(before, UInt<2>(0h2))
node _T_479 = eq(after, UInt<4>(0h8))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60
assert(clock, _T_481, UInt<1>(0h1), "") : assert_60
node _T_485 = eq(before, UInt<2>(0h2))
node _T_486 = eq(after, UInt<1>(0h1))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(_T_487, UInt<1>(0h0))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61
assert(clock, _T_488, UInt<1>(0h1), "") : assert_61
node _T_492 = eq(before, UInt<2>(0h2))
node _T_493 = eq(after, UInt<1>(0h0))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62
assert(clock, _T_495, UInt<1>(0h1), "") : assert_62
node _T_499 = eq(before, UInt<2>(0h2))
node _T_500 = eq(after, UInt<3>(0h7))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(_T_501, UInt<1>(0h0))
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63
assert(clock, _T_502, UInt<1>(0h1), "") : assert_63
node _T_506 = eq(before, UInt<2>(0h2))
node _T_507 = eq(after, UInt<3>(0h5))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(_T_508, UInt<1>(0h0))
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64
assert(clock, _T_509, UInt<1>(0h1), "") : assert_64
node _T_513 = eq(before, UInt<2>(0h2))
node _T_514 = eq(after, UInt<3>(0h6))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(before, UInt<2>(0h2))
node _T_517 = eq(after, UInt<3>(0h4))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(before, UInt<2>(0h2))
node _T_520 = eq(after, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(_T_521, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65
assert(clock, _T_522, UInt<1>(0h1), "") : assert_65
node _probe_bit_T = eq(io.sinkc.bits.source, UInt<6>(0h3c))
node _probe_bit_T_1 = eq(io.sinkc.bits.source, UInt<6>(0h38))
node _probe_bit_T_2 = eq(io.sinkc.bits.source, UInt<6>(0h34))
node _probe_bit_T_3 = eq(io.sinkc.bits.source, UInt<6>(0h30))
node _probe_bit_T_4 = eq(io.sinkc.bits.source, UInt<6>(0h2c))
node _probe_bit_T_5 = eq(io.sinkc.bits.source, UInt<6>(0h28))
node _probe_bit_T_6 = eq(io.sinkc.bits.source, UInt<6>(0h24))
node _probe_bit_T_7 = eq(io.sinkc.bits.source, UInt<6>(0h20))
node probe_bit_lo_lo = cat(_probe_bit_T_1, _probe_bit_T)
node probe_bit_lo_hi = cat(_probe_bit_T_3, _probe_bit_T_2)
node probe_bit_lo = cat(probe_bit_lo_hi, probe_bit_lo_lo)
node probe_bit_hi_lo = cat(_probe_bit_T_5, _probe_bit_T_4)
node probe_bit_hi_hi = cat(_probe_bit_T_7, _probe_bit_T_6)
node probe_bit_hi = cat(probe_bit_hi_hi, probe_bit_hi_lo)
node probe_bit = cat(probe_bit_hi, probe_bit_lo)
node _last_probe_T = or(probes_done, probe_bit)
node _last_probe_T_1 = not(excluded_client)
node _last_probe_T_2 = and(meta.clients, _last_probe_T_1)
node last_probe = eq(_last_probe_T, _last_probe_T_2)
node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1))
node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2))
node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1)
node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5))
node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3)
when io.sinkc.valid :
node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_527 = and(probe_toN, _T_526)
node _T_528 = eq(probe_toN, UInt<1>(0h0))
node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_530 = and(_T_528, _T_529)
node _probes_done_T = or(probes_done, probe_bit)
connect probes_done, _probes_done_T
node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0))
node _probes_toN_T_1 = or(probes_toN, _probes_toN_T)
connect probes_toN, _probes_toN_T_1
node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3))
node _probes_noT_T_1 = or(probes_noT, _probes_noT_T)
connect probes_noT, _probes_noT_T_1
node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe)
connect w_rprobeackfirst, _w_rprobeackfirst_T
node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T)
connect w_rprobeacklast, _w_rprobeacklast_T_1
node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe)
connect w_pprobeackfirst, _w_pprobeackfirst_T
node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T)
connect w_pprobeacklast, _w_pprobeacklast_T_1
node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0))
node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T)
node set_pprobeack = and(last_probe, _set_pprobeack_T_1)
node _w_pprobeack_T = or(w_pprobeack, set_pprobeack)
connect w_pprobeack, _w_pprobeack_T
node _T_531 = eq(set_pprobeack, UInt<1>(0h0))
node _T_532 = and(_T_531, w_rprobeackfirst)
node _T_533 = and(set_pprobeack, w_rprobeackfirst)
node _T_534 = neq(meta.state, UInt<2>(0h0))
node _T_535 = eq(io.sinkc.bits.tag, meta.tag)
node _T_536 = and(_T_534, _T_535)
node _T_537 = and(_T_536, io.sinkc.bits.data)
when _T_537 :
connect meta.dirty, UInt<1>(0h1)
when io.sinkd.valid :
node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4))
node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_540 = or(_T_538, _T_539)
when _T_540 :
connect sink, io.sinkd.bits.sink
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, io.sinkd.bits.last
connect bad_grant, io.sinkd.bits.denied
node _w_grant_T = eq(request.offset, UInt<1>(0h0))
node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last)
connect w_grant, _w_grant_T_1
node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_542 = eq(request.offset, UInt<1>(0h0))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_545 = neq(request.offset, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0))
connect gotT, _gotT_T
else :
node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6))
when _T_547 :
connect w_releaseack, UInt<1>(0h1)
when io.sinke.valid :
connect w_grantack, UInt<1>(0h1)
wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}
connect allocate_as_full.set, io.allocate.bits.set
connect allocate_as_full.put, io.allocate.bits.put
connect allocate_as_full.offset, io.allocate.bits.offset
connect allocate_as_full.tag, io.allocate.bits.tag
connect allocate_as_full.source, io.allocate.bits.source
connect allocate_as_full.size, io.allocate.bits.size
connect allocate_as_full.param, io.allocate.bits.param
connect allocate_as_full.opcode, io.allocate.bits.opcode
connect allocate_as_full.control, io.allocate.bits.control
connect allocate_as_full.prio, io.allocate.bits.prio
node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat)
node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits)
node new_request = mux(io.allocate.valid, allocate_as_full, request)
node _new_needT_T = bits(new_request.opcode, 2, 2)
node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0))
node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5))
node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1))
node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3)
node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4)
node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6))
node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7))
node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7)
node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0))
node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9)
node new_needT = or(_new_needT_T_5, _new_needT_T_10)
node _new_clientBit_T = eq(new_request.source, UInt<6>(0h3c))
node _new_clientBit_T_1 = eq(new_request.source, UInt<6>(0h38))
node _new_clientBit_T_2 = eq(new_request.source, UInt<6>(0h34))
node _new_clientBit_T_3 = eq(new_request.source, UInt<6>(0h30))
node _new_clientBit_T_4 = eq(new_request.source, UInt<6>(0h2c))
node _new_clientBit_T_5 = eq(new_request.source, UInt<6>(0h28))
node _new_clientBit_T_6 = eq(new_request.source, UInt<6>(0h24))
node _new_clientBit_T_7 = eq(new_request.source, UInt<6>(0h20))
node new_clientBit_lo_lo = cat(_new_clientBit_T_1, _new_clientBit_T)
node new_clientBit_lo_hi = cat(_new_clientBit_T_3, _new_clientBit_T_2)
node new_clientBit_lo = cat(new_clientBit_lo_hi, new_clientBit_lo_lo)
node new_clientBit_hi_lo = cat(_new_clientBit_T_5, _new_clientBit_T_4)
node new_clientBit_hi_hi = cat(_new_clientBit_T_7, _new_clientBit_T_6)
node new_clientBit_hi = cat(new_clientBit_hi_hi, new_clientBit_hi_lo)
node new_clientBit = cat(new_clientBit_hi, new_clientBit_lo)
node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6))
node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7))
node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1)
node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4))
node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3)
node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5))
node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0))
node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6)
node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0))
wire prior : UInt
connect prior, UInt<1>(0h0)
node prior_c = orr(final_meta_writeback.clients)
node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _prior_T :
node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1))
connect prior, _prior_out_T
else :
node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _prior_T_1 :
node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect prior, _prior_out_T_1
else :
node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _prior_T_2 :
node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3)
connect prior, _prior_out_T_4
else :
node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _prior_T_3 :
connect prior, UInt<4>(0h8)
node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _prior_T_4 :
connect prior, UInt<4>(0h8)
node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat)
when _T_548 :
node _T_549 = eq(prior, UInt<4>(0h8))
node _T_550 = eq(prior, UInt<1>(0h1))
node _T_551 = eq(_T_550, UInt<1>(0h0))
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66
assert(clock, _T_551, UInt<1>(0h1), "") : assert_66
node _T_555 = eq(prior, UInt<1>(0h0))
node _T_556 = eq(_T_555, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67
assert(clock, _T_556, UInt<1>(0h1), "") : assert_67
node _T_560 = eq(prior, UInt<3>(0h7))
node _T_561 = eq(prior, UInt<3>(0h5))
node _T_562 = eq(prior, UInt<3>(0h4))
node _T_563 = eq(prior, UInt<3>(0h6))
node _T_564 = eq(prior, UInt<2>(0h3))
node _T_565 = eq(prior, UInt<2>(0h2))
when io.allocate.valid :
node _T_566 = eq(request_valid, UInt<1>(0h0))
node _T_567 = and(io.schedule.ready, io.schedule.valid)
node _T_568 = and(no_wait, _T_567)
node _T_569 = or(_T_566, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68
assert(clock, _T_569, UInt<1>(0h1), "") : assert_68
connect request_valid, UInt<1>(0h1)
connect request.set, io.allocate.bits.set
connect request.put, io.allocate.bits.put
connect request.offset, io.allocate.bits.offset
connect request.tag, io.allocate.bits.tag
connect request.source, io.allocate.bits.source
connect request.size, io.allocate.bits.size
connect request.param, io.allocate.bits.param
connect request.opcode, io.allocate.bits.opcode
connect request.control, io.allocate.bits.control
connect request.prio, io.allocate.bits.prio
node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat)
node _T_574 = or(io.directory.valid, _T_573)
when _T_574 :
connect meta_valid, UInt<1>(0h1)
connect meta, new_meta
connect probes_done, UInt<1>(0h0)
connect probes_toN, UInt<1>(0h0)
connect probes_noT, UInt<1>(0h0)
connect gotT, UInt<1>(0h0)
connect bad_grant, UInt<1>(0h0)
connect s_rprobe, UInt<1>(0h1)
connect w_rprobeackfirst, UInt<1>(0h1)
connect w_rprobeacklast, UInt<1>(0h1)
connect s_release, UInt<1>(0h1)
connect w_releaseack, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
connect s_acquire, UInt<1>(0h1)
connect s_flush, UInt<1>(0h1)
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, UInt<1>(0h1)
connect w_grant, UInt<1>(0h1)
connect w_pprobeackfirst, UInt<1>(0h1)
connect w_pprobeacklast, UInt<1>(0h1)
connect w_pprobeack, UInt<1>(0h1)
connect s_probeack, UInt<1>(0h1)
connect s_grantack, UInt<1>(0h1)
connect s_execute, UInt<1>(0h1)
connect w_grantack, UInt<1>(0h1)
connect s_writeback, UInt<1>(0h1)
node _T_575 = and(new_request.prio[2], UInt<1>(0h1))
when _T_575 :
connect s_execute, UInt<1>(0h0)
node _T_576 = bits(new_request.opcode, 0, 0)
node _T_577 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_578 = and(_T_576, _T_577)
when _T_578 :
connect s_writeback, UInt<1>(0h0)
node _T_579 = eq(new_request.param, UInt<3>(0h0))
node _T_580 = eq(new_request.param, UInt<3>(0h4))
node _T_581 = or(_T_579, _T_580)
node _T_582 = eq(new_meta.state, UInt<2>(0h2))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
connect s_writeback, UInt<1>(0h0)
node _T_584 = eq(new_request.param, UInt<3>(0h1))
node _T_585 = eq(new_request.param, UInt<3>(0h2))
node _T_586 = or(_T_584, _T_585)
node _T_587 = eq(new_request.param, UInt<3>(0h5))
node _T_588 = or(_T_586, _T_587)
node _T_589 = and(new_meta.clients, new_clientBit)
node _T_590 = neq(_T_589, UInt<1>(0h0))
node _T_591 = and(_T_588, _T_590)
when _T_591 :
connect s_writeback, UInt<1>(0h0)
node _T_592 = asUInt(reset)
node _T_593 = eq(_T_592, UInt<1>(0h0))
when _T_593 :
node _T_594 = eq(new_meta.hit, UInt<1>(0h0))
when _T_594 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69
assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69
else :
node _T_595 = and(new_request.control, UInt<1>(0h1))
when _T_595 :
connect s_flush, UInt<1>(0h0)
when new_meta.hit :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_596 = neq(new_meta.clients, UInt<1>(0h0))
node _T_597 = and(UInt<1>(0h1), _T_596)
when _T_597 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
else :
connect s_execute, UInt<1>(0h0)
node _T_598 = eq(new_meta.hit, UInt<1>(0h0))
node _T_599 = neq(new_meta.state, UInt<2>(0h0))
node _T_600 = and(_T_598, _T_599)
when _T_600 :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_601 = neq(new_meta.clients, UInt<1>(0h0))
node _T_602 = and(UInt<1>(0h1), _T_601)
when _T_602 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
node _T_603 = eq(new_meta.hit, UInt<1>(0h0))
node _T_604 = eq(new_meta.state, UInt<2>(0h1))
node _T_605 = and(_T_604, new_needT)
node _T_606 = or(_T_603, _T_605)
when _T_606 :
connect s_acquire, UInt<1>(0h0)
connect w_grantfirst, UInt<1>(0h0)
connect w_grantlast, UInt<1>(0h0)
connect w_grant, UInt<1>(0h0)
connect s_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_607 = eq(new_meta.state, UInt<2>(0h2))
node _T_608 = or(new_needT, _T_607)
node _T_609 = and(new_meta.hit, _T_608)
node _T_610 = not(new_skipProbe)
node _T_611 = and(new_meta.clients, _T_610)
node _T_612 = neq(_T_611, UInt<1>(0h0))
node _T_613 = and(_T_609, _T_612)
node _T_614 = and(UInt<1>(0h1), _T_613)
when _T_614 :
connect s_pprobe, UInt<1>(0h0)
connect w_pprobeackfirst, UInt<1>(0h0)
connect w_pprobeacklast, UInt<1>(0h0)
connect w_pprobeack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_615 = eq(new_request.opcode, UInt<3>(0h6))
node _T_616 = eq(new_request.opcode, UInt<3>(0h7))
node _T_617 = or(_T_615, _T_616)
when _T_617 :
connect w_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_618 = bits(new_request.opcode, 2, 2)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = and(_T_619, new_meta.hit)
node _T_621 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_622 = and(_T_620, _T_621)
when _T_622 :
connect s_writeback, UInt<1>(0h0) | module MSHR_3( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input [7:0] io_directory_bits_clients, // @[MSHR.scala:86:14]
input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [9:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [2:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output [7:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output [7:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire [7:0] final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire [7:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21]
wire [7:0] invalid_clients = 8'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire [7:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire [7:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire [7:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire [7:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [12:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [9:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg [7:0] meta_clients; // @[MSHR.scala:100:17]
reg [12:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [2:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg [7:0] probes_done; // @[MSHR.scala:150:24]
reg [7:0] probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire [7:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire _req_clientBit_T = request_source == 6'h3C; // @[Parameters.scala:46:9]
wire _req_clientBit_T_1 = request_source == 6'h38; // @[Parameters.scala:46:9]
wire _req_clientBit_T_2 = request_source == 6'h34; // @[Parameters.scala:46:9]
wire _req_clientBit_T_3 = request_source == 6'h30; // @[Parameters.scala:46:9]
wire _req_clientBit_T_4 = request_source == 6'h2C; // @[Parameters.scala:46:9]
wire _req_clientBit_T_5 = request_source == 6'h28; // @[Parameters.scala:46:9]
wire _req_clientBit_T_6 = request_source == 6'h24; // @[Parameters.scala:46:9]
wire _req_clientBit_T_7 = request_source == 6'h20; // @[Parameters.scala:46:9]
wire [1:0] req_clientBit_lo_lo = {_req_clientBit_T_1, _req_clientBit_T}; // @[Parameters.scala:46:9]
wire [1:0] req_clientBit_lo_hi = {_req_clientBit_T_3, _req_clientBit_T_2}; // @[Parameters.scala:46:9]
wire [3:0] req_clientBit_lo = {req_clientBit_lo_hi, req_clientBit_lo_lo}; // @[Parameters.scala:201:10]
wire [1:0] req_clientBit_hi_lo = {_req_clientBit_T_5, _req_clientBit_T_4}; // @[Parameters.scala:46:9]
wire [1:0] req_clientBit_hi_hi = {_req_clientBit_T_7, _req_clientBit_T_6}; // @[Parameters.scala:46:9]
wire [3:0] req_clientBit_hi = {req_clientBit_hi_hi, req_clientBit_hi_lo}; // @[Parameters.scala:201:10]
wire [7:0] req_clientBit = {req_clientBit_hi, req_clientBit_lo}; // @[Parameters.scala:201:10]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire _meta_no_clients_T = |meta_clients; // @[MSHR.scala:100:17, :220:39]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire [7:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 8'h0; // @[Parameters.scala:201:10, :282:66]
wire [7:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire [7:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire [7:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire [7:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire [7:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire [7:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire [7:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 8'h0; // @[MSHR.scala:100:17, :245:{40,64}]
wire [7:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 8'h0; // @[Parameters.scala:201:10]
wire [7:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire [7:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire [7:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 8'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire [7:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10]
wire _honour_BtoT_T_1 = |_honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire [7:0] excluded_client = _excluded_client_T_9 ? req_clientBit : 8'h0; // @[Parameters.scala:201:10]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire [7:0] _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 8'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire evict_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire before_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire after_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _probe_bit_T = io_sinkc_bits_source_0 == 6'h3C; // @[Parameters.scala:46:9]
wire _probe_bit_T_1 = io_sinkc_bits_source_0 == 6'h38; // @[Parameters.scala:46:9]
wire _probe_bit_T_2 = io_sinkc_bits_source_0 == 6'h34; // @[Parameters.scala:46:9]
wire _probe_bit_T_3 = io_sinkc_bits_source_0 == 6'h30; // @[Parameters.scala:46:9]
wire _probe_bit_T_4 = io_sinkc_bits_source_0 == 6'h2C; // @[Parameters.scala:46:9]
wire _probe_bit_T_5 = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9]
wire _probe_bit_T_6 = io_sinkc_bits_source_0 == 6'h24; // @[Parameters.scala:46:9]
wire _probe_bit_T_7 = io_sinkc_bits_source_0 == 6'h20; // @[Parameters.scala:46:9]
wire [1:0] probe_bit_lo_lo = {_probe_bit_T_1, _probe_bit_T}; // @[Parameters.scala:46:9]
wire [1:0] probe_bit_lo_hi = {_probe_bit_T_3, _probe_bit_T_2}; // @[Parameters.scala:46:9]
wire [3:0] probe_bit_lo = {probe_bit_lo_hi, probe_bit_lo_lo}; // @[Parameters.scala:201:10]
wire [1:0] probe_bit_hi_lo = {_probe_bit_T_5, _probe_bit_T_4}; // @[Parameters.scala:46:9]
wire [1:0] probe_bit_hi_hi = {_probe_bit_T_7, _probe_bit_T_6}; // @[Parameters.scala:46:9]
wire [3:0] probe_bit_hi = {probe_bit_hi_hi, probe_bit_hi_lo}; // @[Parameters.scala:201:10]
wire [7:0] probe_bit = {probe_bit_hi, probe_bit_lo}; // @[Parameters.scala:201:10]
wire [7:0] _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:201:10]
wire [7:0] _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire [7:0] _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire [7:0] _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire [7:0] _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire [7:0] _probes_toN_T = probe_toN ? probe_bit : 8'h0; // @[Parameters.scala:201:10, :282:66]
wire [7:0] _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [7:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _new_clientBit_T = new_request_source == 6'h3C; // @[Parameters.scala:46:9]
wire _new_clientBit_T_1 = new_request_source == 6'h38; // @[Parameters.scala:46:9]
wire _new_clientBit_T_2 = new_request_source == 6'h34; // @[Parameters.scala:46:9]
wire _new_clientBit_T_3 = new_request_source == 6'h30; // @[Parameters.scala:46:9]
wire _new_clientBit_T_4 = new_request_source == 6'h2C; // @[Parameters.scala:46:9]
wire _new_clientBit_T_5 = new_request_source == 6'h28; // @[Parameters.scala:46:9]
wire _new_clientBit_T_6 = new_request_source == 6'h24; // @[Parameters.scala:46:9]
wire _new_clientBit_T_7 = new_request_source == 6'h20; // @[Parameters.scala:46:9]
wire [1:0] new_clientBit_lo_lo = {_new_clientBit_T_1, _new_clientBit_T}; // @[Parameters.scala:46:9]
wire [1:0] new_clientBit_lo_hi = {_new_clientBit_T_3, _new_clientBit_T_2}; // @[Parameters.scala:46:9]
wire [3:0] new_clientBit_lo = {new_clientBit_lo_hi, new_clientBit_lo_lo}; // @[Parameters.scala:201:10]
wire [1:0] new_clientBit_hi_lo = {_new_clientBit_T_5, _new_clientBit_T_4}; // @[Parameters.scala:46:9]
wire [1:0] new_clientBit_hi_hi = {_new_clientBit_T_7, _new_clientBit_T_6}; // @[Parameters.scala:46:9]
wire [3:0] new_clientBit_hi = {new_clientBit_hi_hi, new_clientBit_hi_lo}; // @[Parameters.scala:201:10]
wire [7:0] new_clientBit = {new_clientBit_hi, new_clientBit_lo}; // @[Parameters.scala:201:10]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire [7:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 8'h0; // @[Parameters.scala:201:10, :279:106]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire prior_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_10 :
output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}}
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags)
node _sigSum_T = bits(io.mulAddResult, 48, 48)
node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1))
node _sigSum_T_2 = tail(_sigSum_T_1, 1)
node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC)
node _sigSum_T_4 = bits(io.mulAddResult, 47, 0)
node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4)
node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC)
node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags)
node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T)
node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1)
node CDom_sExp = asSInt(_CDom_sExp_T_2)
node _CDom_absSigSum_T = bits(sigSum, 74, 25)
node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T)
node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24)
node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2)
node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26)
node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4)
node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5)
node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1)
node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T)
node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1)
node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1)
node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3)
node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4)
node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist)
node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21)
node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0)
node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3)
wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0)
node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T)
connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1
node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4)
node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T)
connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1
node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8)
node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T)
connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1
node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12)
node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T)
connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1
node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16)
node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T)
connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1
node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20)
node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T)
connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1
node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24)
node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T)
connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1
node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1])
node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0])
node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3])
node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5])
node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo)
node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo)
node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2)
node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3)
node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4)
node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1)
node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0)
node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0)
node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0)
node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1)
node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9)
node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2)
node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0)
node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1)
node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13)
node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14)
node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4)
node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0)
node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1)
node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18)
node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19)
node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20)
node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21)
node _CDom_sig_T = shr(CDom_mainSig, 3)
node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0)
node _CDom_sig_T_2 = orr(_CDom_sig_T_1)
node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra)
node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra)
node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4)
node notCDom_signSigSum = bits(sigSum, 51, 51)
node _notCDom_absSigSum_T = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T)
node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags)
node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1)
node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4)
wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26]
node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0)
node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T)
connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2)
node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T)
connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4)
node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T)
connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6)
node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T)
connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8)
node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T)
connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10)
node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T)
connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12)
node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T)
connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14)
node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T)
connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16)
node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T)
connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18)
node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T)
connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20)
node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T)
connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22)
node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T)
connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24)
node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T)
connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26)
node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T)
connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28)
node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T)
connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30)
node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T)
connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32)
node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T)
connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34)
node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T)
connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36)
node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T)
connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38)
node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T)
connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40)
node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T)
connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42)
node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T)
connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44)
node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T)
connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46)
node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T)
connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48)
node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T)
connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50)
node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T)
connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1
node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1])
node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0])
node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4])
node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3])
node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo)
node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7])
node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6])
node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9])
node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11])
node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo)
node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo)
node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo)
node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14])
node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13])
node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17])
node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16])
node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo)
node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20])
node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19])
node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22])
node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24])
node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo)
node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo)
node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0)
node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1)
node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2)
node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3)
node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4)
node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5)
node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6)
node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7)
node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8)
node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9)
node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10)
node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11)
node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12)
node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13)
node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14)
node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15)
node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16)
node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17)
node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18)
node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19)
node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20)
node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21)
node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22)
node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23)
node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24)
node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25)
node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19))
node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26)
node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27)
node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28)
node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29)
node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30)
node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31)
node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32)
node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33)
node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34)
node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35)
node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36)
node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37)
node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38)
node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39)
node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40)
node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41)
node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42)
node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43)
node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44)
node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45)
node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46)
node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47)
node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48)
node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49)
node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1)
node _notCDom_sExp_T = cvt(notCDom_nearNormDist)
node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T)
node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1)
node notCDom_sExp = asSInt(_notCDom_sExp_T_2)
node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist)
node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23)
node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0)
node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0)
wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0)
node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T)
connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1
node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2)
node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T)
connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1
node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4)
node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T)
connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1
node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6)
node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T)
connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1
node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8)
node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T)
connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1
node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10)
node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T)
connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1
node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12)
node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T)
connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1
node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1])
node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0])
node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3])
node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5])
node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo)
node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo)
node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1)
node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3)
node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4)
node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1)
node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0)
node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0)
node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0)
node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1)
node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9)
node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2)
node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0)
node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1)
node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13)
node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14)
node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4)
node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0)
node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1)
node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18)
node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19)
node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20)
node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21)
node _notCDom_sig_T = shr(notCDom_mainSig, 3)
node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0)
node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1)
node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra)
node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3)
node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25)
node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0))
node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum)
node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T)
node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC)
node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB)
node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC)
node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB)
node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T)
node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB)
node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2)
node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0))
node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5)
node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC)
node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags)
node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8)
connect io.invalidExc, _io_invalidExc_T_9
node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC)
connect io.rawOut.isNaN, _io_rawOut_isNaN_T
connect io.rawOut.isInf, notNaN_isInfOut
node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0))
node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation)
node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1)
connect io.rawOut.isZero, _io_rawOut_isZero_T_2
node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd)
node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC)
node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1)
node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0))
node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3)
node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd)
node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC)
node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6)
node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min)
node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC)
node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9)
node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10)
node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0))
node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0))
node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13)
node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign)
node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15)
node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16)
connect io.rawOut.sign, _io_rawOut_sign_T_17
node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
connect io.rawOut.sExp, _io_rawOut_sExp_T
node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
connect io.rawOut.sig, _io_rawOut_sig_T | module MulAddRecFNToRaw_postMul_e8_s24_10( // @[MulAddRecFN.scala:169:7]
input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16]
input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16]
input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16]
input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16]
input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16]
output io_invalidExc, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16]
output io_rawOut_sign, // @[MulAddRecFN.scala:172:16]
output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16]
output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16]
);
wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7]
wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7]
wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7]
wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16]
wire io_fromPreMul_isZeroC = 1'h1; // @[MulAddRecFN.scala:169:7]
wire _io_rawOut_isZero_T = 1'h1; // @[MulAddRecFN.scala:283:14]
wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29]
wire io_fromPreMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfC = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:169:7]
wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45]
wire _io_invalidExc_T_7 = 1'h0; // @[MulAddRecFN.scala:275:61]
wire _io_invalidExc_T_8 = 1'h0; // @[MulAddRecFN.scala:276:35]
wire _io_rawOut_sign_T_1 = 1'h0; // @[MulAddRecFN.scala:286:31]
wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26]
wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46]
wire _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :278:48]
wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57]
wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44]
wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25]
wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50]
wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26]
wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25]
wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42]
wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32]
wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47]
wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47]
wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47]
wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28]
wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28]
wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12]
wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69]
wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43]
wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}]
wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43]
wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43]
wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20]
wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}]
wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46]
wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46]
wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23]
wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23]
wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71]
wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21]
wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}]
wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}]
wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19]
wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}]
wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37]
wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24]
wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}]
wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36]
wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}]
wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15]
assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20]
wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51]
wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20]
wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73]
wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25]
wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25]
wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}]
wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}]
wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}]
wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61]
wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36]
wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20]
wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19]
wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}]
wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}]
wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41]
wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41]
wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15]
assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20]
wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20]
wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20]
wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70]
wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70]
wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70]
wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76]
wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}]
wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46]
wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46]
assign _io_rawOut_sExp_T = notCDom_sExp; // @[MulAddRecFN.scala:241:46, :293:26]
wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27]
wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}]
wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20]
wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}]
wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15]
assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20]
wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70]
wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20]
wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11]
wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28]
wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28]
wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}]
wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}]
wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39]
assign _io_rawOut_sig_T = notCDom_sig; // @[MulAddRecFN.scala:251:12, :294:25]
wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21]
wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54]
wire _io_rawOut_isZero_T_1 = notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:42]
wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36]
wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36]
wire _io_rawOut_sign_T_15 = notCDom_sign; // @[MulAddRecFN.scala:257:12, :292:17]
wire _GEN_0 = io_fromPreMul_isInfA_0 | io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49]
wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49]
assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49]
wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36]
assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36]
assign notNaN_isInfOut = notNaN_isInfProd; // @[MulAddRecFN.scala:264:49, :265:44]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44]
wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 | io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32]
wire notNaN_addZeros = _notNaN_addZeros_T; // @[MulAddRecFN.scala:267:{32,58}]
wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26]
wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31]
wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 | _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31]
wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32]
wire _io_invalidExc_T_3 = _io_invalidExc_T_1 | _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32]
assign _io_invalidExc_T_9 = _io_invalidExc_T_3; // @[MulAddRecFN.scala:272:57, :273:57]
wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10]
wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36]
assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48]
assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42]
assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25]
wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27]
wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T; // @[MulAddRecFN.scala:285:{27,54}]
wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}]
wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36]
wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36]
wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48]
wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37]
wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10]
wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31]
wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}]
wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17]
assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49]
assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50]
assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26]
assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25]
assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x1_13 :
input clock : Clock
input reset : Reset
output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}}
wire nodeIn : UInt<1>[1]
invalidate nodeIn[0]
wire nodeOut : { sync : UInt<1>[1]}
invalidate nodeOut.sync[0]
connect auto.out, nodeOut
connect nodeIn, auto.in
inst reg of AsyncResetRegVec_w1_i0_13
connect reg.clock, clock
connect reg.reset, reset
connect reg.io.d, nodeIn[0]
connect reg.io.en, UInt<1>(0h1)
node _T = bits(reg.io.q, 0, 0)
connect nodeOut.sync[0], _T | module IntSyncCrossingSource_n1x1_13( // @[Crossing.scala:41:9]
input clock, // @[Crossing.scala:41:9]
input reset, // @[Crossing.scala:41:9]
input auto_in_0, // @[LazyModuleImp.scala:107:25]
output auto_out_sync_0 // @[LazyModuleImp.scala:107:25]
);
wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9]
wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9]
wire nodeOut_sync_0; // @[MixedNode.scala:542:17]
wire auto_out_sync_0_0; // @[Crossing.scala:41:9]
assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9]
AsyncResetRegVec_w1_i0_13 reg_0 ( // @[AsyncResetReg.scala:86:21]
.clock (clock),
.reset (reset),
.io_d (nodeIn_0), // @[MixedNode.scala:551:17]
.io_q (nodeOut_sync_0)
); // @[AsyncResetReg.scala:86:21]
assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_131 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_131( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_cbus_to_plic :
input clock : Clock
input reset : Reset
output auto : { fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
inst fragmenter of TLFragmenter_PLIC
connect fragmenter.clock, clock
connect fragmenter.reset, reset
wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlOut.d.bits.corrupt
invalidate tlOut.d.bits.data
invalidate tlOut.d.bits.denied
invalidate tlOut.d.bits.sink
invalidate tlOut.d.bits.source
invalidate tlOut.d.bits.size
invalidate tlOut.d.bits.param
invalidate tlOut.d.bits.opcode
invalidate tlOut.d.valid
invalidate tlOut.d.ready
invalidate tlOut.a.bits.corrupt
invalidate tlOut.a.bits.data
invalidate tlOut.a.bits.mask
invalidate tlOut.a.bits.address
invalidate tlOut.a.bits.source
invalidate tlOut.a.bits.size
invalidate tlOut.a.bits.param
invalidate tlOut.a.bits.opcode
invalidate tlOut.a.valid
invalidate tlOut.a.ready
wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlIn.d.bits.corrupt
invalidate tlIn.d.bits.data
invalidate tlIn.d.bits.denied
invalidate tlIn.d.bits.sink
invalidate tlIn.d.bits.source
invalidate tlIn.d.bits.size
invalidate tlIn.d.bits.param
invalidate tlIn.d.bits.opcode
invalidate tlIn.d.valid
invalidate tlIn.d.ready
invalidate tlIn.a.bits.corrupt
invalidate tlIn.a.bits.data
invalidate tlIn.a.bits.mask
invalidate tlIn.a.bits.address
invalidate tlIn.a.bits.source
invalidate tlIn.a.bits.size
invalidate tlIn.a.bits.param
invalidate tlIn.a.bits.opcode
invalidate tlIn.a.valid
invalidate tlIn.a.ready
connect tlOut, tlIn
connect fragmenter.auto.anon_in, tlOut
connect tlIn, auto.tl_in
connect fragmenter.auto.anon_out.d, auto.fragmenter_anon_out.d
connect auto.fragmenter_anon_out.a.bits, fragmenter.auto.anon_out.a.bits
connect auto.fragmenter_anon_out.a.valid, fragmenter.auto.anon_out.a.valid
connect fragmenter.auto.anon_out.a.ready, auto.fragmenter_anon_out.a.ready
extmodule plusarg_reader_56 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_57 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLInterconnectCoupler_cbus_to_plic( // @[LazyModuleImp.scala:138:7]
input clock, // @[LazyModuleImp.scala:138:7]
input reset, // @[LazyModuleImp.scala:138:7]
input auto_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [12:0] auto_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [27:0] auto_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [12:0] auto_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [8:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [27:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [8:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire tlOut_d_valid; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_d_bits_data; // @[MixedNode.scala:542:17]
wire [8:0] tlOut_d_bits_source; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_d_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_d_bits_opcode; // @[MixedNode.scala:542:17]
wire tlOut_a_ready; // @[MixedNode.scala:542:17]
wire auto_fragmenter_anon_out_a_ready_0 = auto_fragmenter_anon_out_a_ready; // @[LazyModuleImp.scala:138:7]
wire auto_fragmenter_anon_out_d_valid_0 = auto_fragmenter_anon_out_d_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_fragmenter_anon_out_d_bits_opcode_0 = auto_fragmenter_anon_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_fragmenter_anon_out_d_bits_size_0 = auto_fragmenter_anon_out_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [12:0] auto_fragmenter_anon_out_d_bits_source_0 = auto_fragmenter_anon_out_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_fragmenter_anon_out_d_bits_data_0 = auto_fragmenter_anon_out_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [8:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [27:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire auto_fragmenter_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_fragmenter_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_tl_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_tl_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_tl_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire tlOut_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire tlOut_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire tlOut_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire tlIn_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire tlIn_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire tlIn_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire [1:0] auto_fragmenter_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire [1:0] tlOut_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire [1:0] tlIn_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire tlIn_a_ready; // @[MixedNode.scala:551:17]
wire tlIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17]
wire [8:0] tlIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17]
wire [27:0] tlIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17]
wire [7:0] tlIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17]
wire [63:0] tlIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17]
wire tlIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17]
wire tlIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17]
wire tlIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [8:0] tlIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] tlIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [2:0] auto_fragmenter_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_fragmenter_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_fragmenter_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [12:0] auto_fragmenter_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [27:0] auto_fragmenter_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_fragmenter_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_fragmenter_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_fragmenter_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_fragmenter_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
wire auto_fragmenter_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [8:0] auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign tlIn_a_ready = tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_valid = tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_opcode = tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_size = tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_source = tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_data = tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [8:0] tlOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [27:0] tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlOut_a_valid; // @[MixedNode.scala:542:17]
wire tlOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_tl_in_a_ready_0 = tlIn_a_ready; // @[MixedNode.scala:551:17]
assign tlOut_a_valid = tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_opcode = tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_param = tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_size = tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_source = tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_address = tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_mask = tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_data = tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_corrupt = tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_d_ready = tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_tl_in_d_valid_0 = tlIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_opcode_0 = tlIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_size_0 = tlIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_source_0 = tlIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_data_0 = tlIn_d_bits_data; // @[MixedNode.scala:551:17]
TLFragmenter_PLIC fragmenter ( // @[Fragmenter.scala:345:34]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (tlOut_a_ready),
.auto_anon_in_a_valid (tlOut_a_valid), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_opcode (tlOut_a_bits_opcode), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_param (tlOut_a_bits_param), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_size (tlOut_a_bits_size), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_source (tlOut_a_bits_source), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_address (tlOut_a_bits_address), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_mask (tlOut_a_bits_mask), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_data (tlOut_a_bits_data), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_corrupt (tlOut_a_bits_corrupt), // @[MixedNode.scala:542:17]
.auto_anon_in_d_ready (tlOut_d_ready), // @[MixedNode.scala:542:17]
.auto_anon_in_d_valid (tlOut_d_valid),
.auto_anon_in_d_bits_opcode (tlOut_d_bits_opcode),
.auto_anon_in_d_bits_size (tlOut_d_bits_size),
.auto_anon_in_d_bits_source (tlOut_d_bits_source),
.auto_anon_in_d_bits_data (tlOut_d_bits_data),
.auto_anon_out_a_ready (auto_fragmenter_anon_out_a_ready_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_a_valid (auto_fragmenter_anon_out_a_valid_0),
.auto_anon_out_a_bits_opcode (auto_fragmenter_anon_out_a_bits_opcode_0),
.auto_anon_out_a_bits_param (auto_fragmenter_anon_out_a_bits_param_0),
.auto_anon_out_a_bits_size (auto_fragmenter_anon_out_a_bits_size_0),
.auto_anon_out_a_bits_source (auto_fragmenter_anon_out_a_bits_source_0),
.auto_anon_out_a_bits_address (auto_fragmenter_anon_out_a_bits_address_0),
.auto_anon_out_a_bits_mask (auto_fragmenter_anon_out_a_bits_mask_0),
.auto_anon_out_a_bits_data (auto_fragmenter_anon_out_a_bits_data_0),
.auto_anon_out_a_bits_corrupt (auto_fragmenter_anon_out_a_bits_corrupt_0),
.auto_anon_out_d_ready (auto_fragmenter_anon_out_d_ready_0),
.auto_anon_out_d_valid (auto_fragmenter_anon_out_d_valid_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_opcode (auto_fragmenter_anon_out_d_bits_opcode_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_size (auto_fragmenter_anon_out_d_bits_size_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_source (auto_fragmenter_anon_out_d_bits_source_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_data (auto_fragmenter_anon_out_d_bits_data_0) // @[LazyModuleImp.scala:138:7]
); // @[Fragmenter.scala:345:34]
assign auto_fragmenter_anon_out_a_valid = auto_fragmenter_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_opcode = auto_fragmenter_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_param = auto_fragmenter_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_size = auto_fragmenter_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_source = auto_fragmenter_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_address = auto_fragmenter_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_mask = auto_fragmenter_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_data = auto_fragmenter_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_corrupt = auto_fragmenter_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_d_ready = auto_fragmenter_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_data = auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_123 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_203
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_123( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_203 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_sbus_from_bus_named_fbus :
input clock : Clock
input reset : Reset
output auto : { widget_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, flip bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
inst widget of TLWidthWidget8
connect widget.clock, clock
connect widget.reset, reset
wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate bus_xingOut.d.bits.corrupt
invalidate bus_xingOut.d.bits.data
invalidate bus_xingOut.d.bits.denied
invalidate bus_xingOut.d.bits.sink
invalidate bus_xingOut.d.bits.source
invalidate bus_xingOut.d.bits.size
invalidate bus_xingOut.d.bits.param
invalidate bus_xingOut.d.bits.opcode
invalidate bus_xingOut.d.valid
invalidate bus_xingOut.d.ready
invalidate bus_xingOut.a.bits.corrupt
invalidate bus_xingOut.a.bits.data
invalidate bus_xingOut.a.bits.mask
invalidate bus_xingOut.a.bits.address
invalidate bus_xingOut.a.bits.source
invalidate bus_xingOut.a.bits.size
invalidate bus_xingOut.a.bits.param
invalidate bus_xingOut.a.bits.opcode
invalidate bus_xingOut.a.valid
invalidate bus_xingOut.a.ready
wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate bus_xingIn.d.bits.corrupt
invalidate bus_xingIn.d.bits.data
invalidate bus_xingIn.d.bits.denied
invalidate bus_xingIn.d.bits.sink
invalidate bus_xingIn.d.bits.source
invalidate bus_xingIn.d.bits.size
invalidate bus_xingIn.d.bits.param
invalidate bus_xingIn.d.bits.opcode
invalidate bus_xingIn.d.valid
invalidate bus_xingIn.d.ready
invalidate bus_xingIn.a.bits.corrupt
invalidate bus_xingIn.a.bits.data
invalidate bus_xingIn.a.bits.mask
invalidate bus_xingIn.a.bits.address
invalidate bus_xingIn.a.bits.source
invalidate bus_xingIn.a.bits.size
invalidate bus_xingIn.a.bits.param
invalidate bus_xingIn.a.bits.opcode
invalidate bus_xingIn.a.valid
invalidate bus_xingIn.a.ready
connect bus_xingOut, bus_xingIn
connect widget.auto.anon_in, bus_xingOut
connect bus_xingIn, auto.bus_xing_in
connect widget.auto.anon_out.d, auto.widget_anon_out.d
connect auto.widget_anon_out.a.bits, widget.auto.anon_out.a.bits
connect auto.widget_anon_out.a.valid, widget.auto.anon_out.a.valid
connect widget.auto.anon_out.a.ready, auto.widget_anon_out.a.ready | module TLInterconnectCoupler_sbus_from_bus_named_fbus( // @[LazyModuleImp.scala:138:7]
input clock, // @[LazyModuleImp.scala:138:7]
input reset, // @[LazyModuleImp.scala:138:7]
input auto_widget_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_widget_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_widget_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_widget_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_widget_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_widget_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_widget_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_widget_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_widget_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_widget_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_widget_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_widget_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_widget_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_widget_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_widget_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_widget_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_widget_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_widget_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_widget_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_widget_anon_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire bus_xingOut_d_valid; // @[MixedNode.scala:542:17]
wire bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire [63:0] bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17]
wire bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17]
wire [3:0] bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17]
wire [5:0] bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17]
wire bus_xingOut_a_ready; // @[MixedNode.scala:542:17]
wire auto_widget_anon_out_a_ready_0 = auto_widget_anon_out_a_ready; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_out_d_valid_0 = auto_widget_anon_out_d_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_widget_anon_out_d_bits_opcode_0 = auto_widget_anon_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_widget_anon_out_d_bits_param_0 = auto_widget_anon_out_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_widget_anon_out_d_bits_size_0 = auto_widget_anon_out_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [5:0] auto_widget_anon_out_d_bits_source_0 = auto_widget_anon_out_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_widget_anon_out_d_bits_sink_0 = auto_widget_anon_out_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_out_d_bits_denied_0 = auto_widget_anon_out_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [127:0] auto_widget_anon_out_d_bits_data_0 = auto_widget_anon_out_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_out_d_bits_corrupt_0 = auto_widget_anon_out_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire auto_bus_xing_in_a_valid_0 = auto_bus_xing_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_bus_xing_in_a_bits_opcode_0 = auto_bus_xing_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_bus_xing_in_a_bits_param_0 = auto_bus_xing_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_bus_xing_in_a_bits_size_0 = auto_bus_xing_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [5:0] auto_bus_xing_in_a_bits_source_0 = auto_bus_xing_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [31:0] auto_bus_xing_in_a_bits_address_0 = auto_bus_xing_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_bus_xing_in_a_bits_mask_0 = auto_bus_xing_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_bus_xing_in_a_bits_data_0 = auto_bus_xing_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_bus_xing_in_a_bits_corrupt_0 = auto_bus_xing_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire auto_bus_xing_in_d_ready_0 = auto_bus_xing_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire bus_xingIn_a_ready; // @[MixedNode.scala:551:17]
wire bus_xingIn_a_valid = auto_bus_xing_in_a_valid_0; // @[MixedNode.scala:551:17]
wire [2:0] bus_xingIn_a_bits_opcode = auto_bus_xing_in_a_bits_opcode_0; // @[MixedNode.scala:551:17]
wire [2:0] bus_xingIn_a_bits_param = auto_bus_xing_in_a_bits_param_0; // @[MixedNode.scala:551:17]
wire [3:0] bus_xingIn_a_bits_size = auto_bus_xing_in_a_bits_size_0; // @[MixedNode.scala:551:17]
wire [5:0] bus_xingIn_a_bits_source = auto_bus_xing_in_a_bits_source_0; // @[MixedNode.scala:551:17]
wire [31:0] bus_xingIn_a_bits_address = auto_bus_xing_in_a_bits_address_0; // @[MixedNode.scala:551:17]
wire [7:0] bus_xingIn_a_bits_mask = auto_bus_xing_in_a_bits_mask_0; // @[MixedNode.scala:551:17]
wire [63:0] bus_xingIn_a_bits_data = auto_bus_xing_in_a_bits_data_0; // @[MixedNode.scala:551:17]
wire bus_xingIn_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17]
wire bus_xingIn_d_ready = auto_bus_xing_in_d_ready_0; // @[MixedNode.scala:551:17]
wire bus_xingIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [5:0] bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17]
wire bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [2:0] auto_widget_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_widget_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_widget_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [5:0] auto_widget_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [31:0] auto_widget_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
wire [15:0] auto_widget_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
wire [127:0] auto_widget_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
wire auto_bus_xing_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_bus_xing_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_bus_xing_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_bus_xing_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [5:0] auto_bus_xing_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_bus_xing_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7]
wire auto_bus_xing_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_bus_xing_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_bus_xing_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_bus_xing_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign bus_xingIn_a_ready = bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_valid = bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_opcode = bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_param = bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_size = bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_source = bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_sink = bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_denied = bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_data = bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [5:0] bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17]
wire bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign bus_xingIn_d_bits_corrupt = bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire bus_xingOut_a_valid; // @[MixedNode.scala:542:17]
wire bus_xingOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_bus_xing_in_a_ready_0 = bus_xingIn_a_ready; // @[MixedNode.scala:551:17]
assign bus_xingOut_a_valid = bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_opcode = bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_param = bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_size = bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_source = bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_address = bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_mask = bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_data = bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_corrupt = bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_d_ready = bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_bus_xing_in_d_valid_0 = bus_xingIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_bus_xing_in_d_bits_opcode_0 = bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_bus_xing_in_d_bits_param_0 = bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17]
assign auto_bus_xing_in_d_bits_size_0 = bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_bus_xing_in_d_bits_source_0 = bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_bus_xing_in_d_bits_sink_0 = bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign auto_bus_xing_in_d_bits_denied_0 = bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign auto_bus_xing_in_d_bits_data_0 = bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17]
assign auto_bus_xing_in_d_bits_corrupt_0 = bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
TLWidthWidget8 widget ( // @[WidthWidget.scala:230:28]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (bus_xingOut_a_ready),
.auto_anon_in_a_valid (bus_xingOut_a_valid), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_opcode (bus_xingOut_a_bits_opcode), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_param (bus_xingOut_a_bits_param), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_size (bus_xingOut_a_bits_size), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_source (bus_xingOut_a_bits_source), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_address (bus_xingOut_a_bits_address), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_mask (bus_xingOut_a_bits_mask), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_data (bus_xingOut_a_bits_data), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_corrupt (bus_xingOut_a_bits_corrupt), // @[MixedNode.scala:542:17]
.auto_anon_in_d_ready (bus_xingOut_d_ready), // @[MixedNode.scala:542:17]
.auto_anon_in_d_valid (bus_xingOut_d_valid),
.auto_anon_in_d_bits_opcode (bus_xingOut_d_bits_opcode),
.auto_anon_in_d_bits_param (bus_xingOut_d_bits_param),
.auto_anon_in_d_bits_size (bus_xingOut_d_bits_size),
.auto_anon_in_d_bits_source (bus_xingOut_d_bits_source),
.auto_anon_in_d_bits_sink (bus_xingOut_d_bits_sink),
.auto_anon_in_d_bits_denied (bus_xingOut_d_bits_denied),
.auto_anon_in_d_bits_data (bus_xingOut_d_bits_data),
.auto_anon_in_d_bits_corrupt (bus_xingOut_d_bits_corrupt),
.auto_anon_out_a_ready (auto_widget_anon_out_a_ready_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_a_valid (auto_widget_anon_out_a_valid_0),
.auto_anon_out_a_bits_opcode (auto_widget_anon_out_a_bits_opcode_0),
.auto_anon_out_a_bits_param (auto_widget_anon_out_a_bits_param_0),
.auto_anon_out_a_bits_size (auto_widget_anon_out_a_bits_size_0),
.auto_anon_out_a_bits_source (auto_widget_anon_out_a_bits_source_0),
.auto_anon_out_a_bits_address (auto_widget_anon_out_a_bits_address_0),
.auto_anon_out_a_bits_mask (auto_widget_anon_out_a_bits_mask_0),
.auto_anon_out_a_bits_data (auto_widget_anon_out_a_bits_data_0),
.auto_anon_out_a_bits_corrupt (auto_widget_anon_out_a_bits_corrupt_0),
.auto_anon_out_d_ready (auto_widget_anon_out_d_ready_0),
.auto_anon_out_d_valid (auto_widget_anon_out_d_valid_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_opcode (auto_widget_anon_out_d_bits_opcode_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_param (auto_widget_anon_out_d_bits_param_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_size (auto_widget_anon_out_d_bits_size_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_source (auto_widget_anon_out_d_bits_source_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_sink (auto_widget_anon_out_d_bits_sink_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_denied (auto_widget_anon_out_d_bits_denied_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_data (auto_widget_anon_out_d_bits_data_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_corrupt (auto_widget_anon_out_d_bits_corrupt_0) // @[LazyModuleImp.scala:138:7]
); // @[WidthWidget.scala:230:28]
assign auto_widget_anon_out_a_valid = auto_widget_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_out_a_bits_opcode = auto_widget_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_out_a_bits_param = auto_widget_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_out_a_bits_size = auto_widget_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_out_a_bits_source = auto_widget_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_out_a_bits_address = auto_widget_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_out_a_bits_mask = auto_widget_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_out_a_bits_data = auto_widget_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_out_a_bits_corrupt = auto_widget_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_out_d_ready = auto_widget_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_bus_xing_in_a_ready = auto_bus_xing_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_bus_xing_in_d_valid = auto_bus_xing_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_bus_xing_in_d_bits_opcode = auto_bus_xing_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_bus_xing_in_d_bits_param = auto_bus_xing_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_bus_xing_in_d_bits_size = auto_bus_xing_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_bus_xing_in_d_bits_source = auto_bus_xing_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_bus_xing_in_d_bits_sink = auto_bus_xing_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7]
assign auto_bus_xing_in_d_bits_denied = auto_bus_xing_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
assign auto_bus_xing_in_d_bits_data = auto_bus_xing_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_bus_xing_in_d_bits_corrupt = auto_bus_xing_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module SwitchArbiter_71 :
input clock : Clock
input reset : Reset
output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[4], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], chosen_oh : UInt<4>[1]}
regreset lock_0 : UInt<4>, clock, reset, UInt<4>(0h0)
node unassigned_lo = cat(io.in[1].valid, io.in[0].valid)
node unassigned_hi = cat(io.in[3].valid, io.in[2].valid)
node _unassigned_T = cat(unassigned_hi, unassigned_lo)
node _unassigned_T_1 = not(lock_0)
node unassigned = and(_unassigned_T, _unassigned_T_1)
regreset mask : UInt<4>, clock, reset, UInt<4>(0h0)
wire choices : UInt<4>[1]
node _sel_T = not(mask)
node _sel_T_1 = and(unassigned, _sel_T)
node _sel_T_2 = cat(unassigned, _sel_T_1)
node _sel_T_3 = bits(_sel_T_2, 0, 0)
node _sel_T_4 = bits(_sel_T_2, 1, 1)
node _sel_T_5 = bits(_sel_T_2, 2, 2)
node _sel_T_6 = bits(_sel_T_2, 3, 3)
node _sel_T_7 = bits(_sel_T_2, 4, 4)
node _sel_T_8 = bits(_sel_T_2, 5, 5)
node _sel_T_9 = bits(_sel_T_2, 6, 6)
node _sel_T_10 = bits(_sel_T_2, 7, 7)
node _sel_T_11 = mux(_sel_T_10, UInt<8>(0h80), UInt<8>(0h0))
node _sel_T_12 = mux(_sel_T_9, UInt<8>(0h40), _sel_T_11)
node _sel_T_13 = mux(_sel_T_8, UInt<8>(0h20), _sel_T_12)
node _sel_T_14 = mux(_sel_T_7, UInt<8>(0h10), _sel_T_13)
node _sel_T_15 = mux(_sel_T_6, UInt<8>(0h8), _sel_T_14)
node _sel_T_16 = mux(_sel_T_5, UInt<8>(0h4), _sel_T_15)
node _sel_T_17 = mux(_sel_T_4, UInt<8>(0h2), _sel_T_16)
node sel = mux(_sel_T_3, UInt<8>(0h1), _sel_T_17)
node _choices_0_T = shr(sel, 4)
node _choices_0_T_1 = or(sel, _choices_0_T)
connect choices[0], _choices_0_T_1
node _T = not(choices[0])
node _T_1 = and(unassigned, _T)
node _T_2 = bits(_T_1, 0, 0)
node _T_3 = bits(_T_1, 1, 1)
node _T_4 = bits(_T_1, 2, 2)
node _T_5 = bits(_T_1, 3, 3)
node _T_6 = mux(_T_5, UInt<4>(0h8), UInt<4>(0h0))
node _T_7 = mux(_T_4, UInt<4>(0h4), _T_6)
node _T_8 = mux(_T_3, UInt<4>(0h2), _T_7)
node _T_9 = mux(_T_2, UInt<4>(0h1), _T_8)
connect io.in[0].ready, UInt<1>(0h0)
connect io.in[1].ready, UInt<1>(0h0)
connect io.in[2].ready, UInt<1>(0h0)
connect io.in[3].ready, UInt<1>(0h0)
node in_tails_lo = cat(io.in[1].bits.tail, io.in[0].bits.tail)
node in_tails_hi = cat(io.in[3].bits.tail, io.in[2].bits.tail)
node in_tails = cat(in_tails_hi, in_tails_lo)
node _in_valids_T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _in_valids_T_1 = and(io.in[0].valid, _in_valids_T)
node _in_valids_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _in_valids_T_3 = and(io.in[1].valid, _in_valids_T_2)
node _in_valids_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _in_valids_T_5 = and(io.in[2].valid, _in_valids_T_4)
node _in_valids_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _in_valids_T_7 = and(io.in[3].valid, _in_valids_T_6)
node in_valids_lo = cat(_in_valids_T_3, _in_valids_T_1)
node in_valids_hi = cat(_in_valids_T_7, _in_valids_T_5)
node in_valids = cat(in_valids_hi, in_valids_lo)
node _chosen_T = and(in_valids, lock_0)
node _chosen_T_1 = not(UInt<4>(0h0))
node _chosen_T_2 = and(_chosen_T, _chosen_T_1)
node _chosen_T_3 = orr(_chosen_T_2)
node chosen = mux(_chosen_T_3, lock_0, choices[0])
connect io.chosen_oh[0], chosen
node _io_out_0_valid_T = and(in_valids, chosen)
node _io_out_0_valid_T_1 = orr(_io_out_0_valid_T)
connect io.out[0].valid, _io_out_0_valid_T_1
node _io_out_0_bits_T = bits(chosen, 0, 0)
node _io_out_0_bits_T_1 = bits(chosen, 1, 1)
node _io_out_0_bits_T_2 = bits(chosen, 2, 2)
node _io_out_0_bits_T_3 = bits(chosen, 3, 3)
wire _io_out_0_bits_WIRE : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}
node _io_out_0_bits_T_4 = mux(_io_out_0_bits_T, io.in[0].bits.tail, UInt<1>(0h0))
node _io_out_0_bits_T_5 = mux(_io_out_0_bits_T_1, io.in[1].bits.tail, UInt<1>(0h0))
node _io_out_0_bits_T_6 = mux(_io_out_0_bits_T_2, io.in[2].bits.tail, UInt<1>(0h0))
node _io_out_0_bits_T_7 = mux(_io_out_0_bits_T_3, io.in[3].bits.tail, UInt<1>(0h0))
node _io_out_0_bits_T_8 = or(_io_out_0_bits_T_4, _io_out_0_bits_T_5)
node _io_out_0_bits_T_9 = or(_io_out_0_bits_T_8, _io_out_0_bits_T_6)
node _io_out_0_bits_T_10 = or(_io_out_0_bits_T_9, _io_out_0_bits_T_7)
wire _io_out_0_bits_WIRE_1 : UInt<1>
connect _io_out_0_bits_WIRE_1, _io_out_0_bits_T_10
connect _io_out_0_bits_WIRE.tail, _io_out_0_bits_WIRE_1
wire _io_out_0_bits_WIRE_2 : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}
wire _io_out_0_bits_WIRE_3 : UInt<1>[8]
node _io_out_0_bits_T_11 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[0], UInt<1>(0h0))
node _io_out_0_bits_T_12 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[0], UInt<1>(0h0))
node _io_out_0_bits_T_13 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[0], UInt<1>(0h0))
node _io_out_0_bits_T_14 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[0], UInt<1>(0h0))
node _io_out_0_bits_T_15 = or(_io_out_0_bits_T_11, _io_out_0_bits_T_12)
node _io_out_0_bits_T_16 = or(_io_out_0_bits_T_15, _io_out_0_bits_T_13)
node _io_out_0_bits_T_17 = or(_io_out_0_bits_T_16, _io_out_0_bits_T_14)
wire _io_out_0_bits_WIRE_4 : UInt<1>
connect _io_out_0_bits_WIRE_4, _io_out_0_bits_T_17
connect _io_out_0_bits_WIRE_3[0], _io_out_0_bits_WIRE_4
node _io_out_0_bits_T_18 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[1], UInt<1>(0h0))
node _io_out_0_bits_T_19 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[1], UInt<1>(0h0))
node _io_out_0_bits_T_20 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[1], UInt<1>(0h0))
node _io_out_0_bits_T_21 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[1], UInt<1>(0h0))
node _io_out_0_bits_T_22 = or(_io_out_0_bits_T_18, _io_out_0_bits_T_19)
node _io_out_0_bits_T_23 = or(_io_out_0_bits_T_22, _io_out_0_bits_T_20)
node _io_out_0_bits_T_24 = or(_io_out_0_bits_T_23, _io_out_0_bits_T_21)
wire _io_out_0_bits_WIRE_5 : UInt<1>
connect _io_out_0_bits_WIRE_5, _io_out_0_bits_T_24
connect _io_out_0_bits_WIRE_3[1], _io_out_0_bits_WIRE_5
node _io_out_0_bits_T_25 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[2], UInt<1>(0h0))
node _io_out_0_bits_T_26 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[2], UInt<1>(0h0))
node _io_out_0_bits_T_27 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[2], UInt<1>(0h0))
node _io_out_0_bits_T_28 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[2], UInt<1>(0h0))
node _io_out_0_bits_T_29 = or(_io_out_0_bits_T_25, _io_out_0_bits_T_26)
node _io_out_0_bits_T_30 = or(_io_out_0_bits_T_29, _io_out_0_bits_T_27)
node _io_out_0_bits_T_31 = or(_io_out_0_bits_T_30, _io_out_0_bits_T_28)
wire _io_out_0_bits_WIRE_6 : UInt<1>
connect _io_out_0_bits_WIRE_6, _io_out_0_bits_T_31
connect _io_out_0_bits_WIRE_3[2], _io_out_0_bits_WIRE_6
node _io_out_0_bits_T_32 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[3], UInt<1>(0h0))
node _io_out_0_bits_T_33 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[3], UInt<1>(0h0))
node _io_out_0_bits_T_34 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[3], UInt<1>(0h0))
node _io_out_0_bits_T_35 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[3], UInt<1>(0h0))
node _io_out_0_bits_T_36 = or(_io_out_0_bits_T_32, _io_out_0_bits_T_33)
node _io_out_0_bits_T_37 = or(_io_out_0_bits_T_36, _io_out_0_bits_T_34)
node _io_out_0_bits_T_38 = or(_io_out_0_bits_T_37, _io_out_0_bits_T_35)
wire _io_out_0_bits_WIRE_7 : UInt<1>
connect _io_out_0_bits_WIRE_7, _io_out_0_bits_T_38
connect _io_out_0_bits_WIRE_3[3], _io_out_0_bits_WIRE_7
node _io_out_0_bits_T_39 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[4], UInt<1>(0h0))
node _io_out_0_bits_T_40 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[4], UInt<1>(0h0))
node _io_out_0_bits_T_41 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[4], UInt<1>(0h0))
node _io_out_0_bits_T_42 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[4], UInt<1>(0h0))
node _io_out_0_bits_T_43 = or(_io_out_0_bits_T_39, _io_out_0_bits_T_40)
node _io_out_0_bits_T_44 = or(_io_out_0_bits_T_43, _io_out_0_bits_T_41)
node _io_out_0_bits_T_45 = or(_io_out_0_bits_T_44, _io_out_0_bits_T_42)
wire _io_out_0_bits_WIRE_8 : UInt<1>
connect _io_out_0_bits_WIRE_8, _io_out_0_bits_T_45
connect _io_out_0_bits_WIRE_3[4], _io_out_0_bits_WIRE_8
node _io_out_0_bits_T_46 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[5], UInt<1>(0h0))
node _io_out_0_bits_T_47 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[5], UInt<1>(0h0))
node _io_out_0_bits_T_48 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[5], UInt<1>(0h0))
node _io_out_0_bits_T_49 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[5], UInt<1>(0h0))
node _io_out_0_bits_T_50 = or(_io_out_0_bits_T_46, _io_out_0_bits_T_47)
node _io_out_0_bits_T_51 = or(_io_out_0_bits_T_50, _io_out_0_bits_T_48)
node _io_out_0_bits_T_52 = or(_io_out_0_bits_T_51, _io_out_0_bits_T_49)
wire _io_out_0_bits_WIRE_9 : UInt<1>
connect _io_out_0_bits_WIRE_9, _io_out_0_bits_T_52
connect _io_out_0_bits_WIRE_3[5], _io_out_0_bits_WIRE_9
node _io_out_0_bits_T_53 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[6], UInt<1>(0h0))
node _io_out_0_bits_T_54 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[6], UInt<1>(0h0))
node _io_out_0_bits_T_55 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[6], UInt<1>(0h0))
node _io_out_0_bits_T_56 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[6], UInt<1>(0h0))
node _io_out_0_bits_T_57 = or(_io_out_0_bits_T_53, _io_out_0_bits_T_54)
node _io_out_0_bits_T_58 = or(_io_out_0_bits_T_57, _io_out_0_bits_T_55)
node _io_out_0_bits_T_59 = or(_io_out_0_bits_T_58, _io_out_0_bits_T_56)
wire _io_out_0_bits_WIRE_10 : UInt<1>
connect _io_out_0_bits_WIRE_10, _io_out_0_bits_T_59
connect _io_out_0_bits_WIRE_3[6], _io_out_0_bits_WIRE_10
node _io_out_0_bits_T_60 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[7], UInt<1>(0h0))
node _io_out_0_bits_T_61 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[7], UInt<1>(0h0))
node _io_out_0_bits_T_62 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[7], UInt<1>(0h0))
node _io_out_0_bits_T_63 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[7], UInt<1>(0h0))
node _io_out_0_bits_T_64 = or(_io_out_0_bits_T_60, _io_out_0_bits_T_61)
node _io_out_0_bits_T_65 = or(_io_out_0_bits_T_64, _io_out_0_bits_T_62)
node _io_out_0_bits_T_66 = or(_io_out_0_bits_T_65, _io_out_0_bits_T_63)
wire _io_out_0_bits_WIRE_11 : UInt<1>
connect _io_out_0_bits_WIRE_11, _io_out_0_bits_T_66
connect _io_out_0_bits_WIRE_3[7], _io_out_0_bits_WIRE_11
connect _io_out_0_bits_WIRE_2.`0`, _io_out_0_bits_WIRE_3
wire _io_out_0_bits_WIRE_12 : UInt<1>[8]
node _io_out_0_bits_T_67 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[0], UInt<1>(0h0))
node _io_out_0_bits_T_68 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[0], UInt<1>(0h0))
node _io_out_0_bits_T_69 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[0], UInt<1>(0h0))
node _io_out_0_bits_T_70 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[0], UInt<1>(0h0))
node _io_out_0_bits_T_71 = or(_io_out_0_bits_T_67, _io_out_0_bits_T_68)
node _io_out_0_bits_T_72 = or(_io_out_0_bits_T_71, _io_out_0_bits_T_69)
node _io_out_0_bits_T_73 = or(_io_out_0_bits_T_72, _io_out_0_bits_T_70)
wire _io_out_0_bits_WIRE_13 : UInt<1>
connect _io_out_0_bits_WIRE_13, _io_out_0_bits_T_73
connect _io_out_0_bits_WIRE_12[0], _io_out_0_bits_WIRE_13
node _io_out_0_bits_T_74 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[1], UInt<1>(0h0))
node _io_out_0_bits_T_75 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[1], UInt<1>(0h0))
node _io_out_0_bits_T_76 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[1], UInt<1>(0h0))
node _io_out_0_bits_T_77 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[1], UInt<1>(0h0))
node _io_out_0_bits_T_78 = or(_io_out_0_bits_T_74, _io_out_0_bits_T_75)
node _io_out_0_bits_T_79 = or(_io_out_0_bits_T_78, _io_out_0_bits_T_76)
node _io_out_0_bits_T_80 = or(_io_out_0_bits_T_79, _io_out_0_bits_T_77)
wire _io_out_0_bits_WIRE_14 : UInt<1>
connect _io_out_0_bits_WIRE_14, _io_out_0_bits_T_80
connect _io_out_0_bits_WIRE_12[1], _io_out_0_bits_WIRE_14
node _io_out_0_bits_T_81 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[2], UInt<1>(0h0))
node _io_out_0_bits_T_82 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[2], UInt<1>(0h0))
node _io_out_0_bits_T_83 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[2], UInt<1>(0h0))
node _io_out_0_bits_T_84 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[2], UInt<1>(0h0))
node _io_out_0_bits_T_85 = or(_io_out_0_bits_T_81, _io_out_0_bits_T_82)
node _io_out_0_bits_T_86 = or(_io_out_0_bits_T_85, _io_out_0_bits_T_83)
node _io_out_0_bits_T_87 = or(_io_out_0_bits_T_86, _io_out_0_bits_T_84)
wire _io_out_0_bits_WIRE_15 : UInt<1>
connect _io_out_0_bits_WIRE_15, _io_out_0_bits_T_87
connect _io_out_0_bits_WIRE_12[2], _io_out_0_bits_WIRE_15
node _io_out_0_bits_T_88 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[3], UInt<1>(0h0))
node _io_out_0_bits_T_89 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[3], UInt<1>(0h0))
node _io_out_0_bits_T_90 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[3], UInt<1>(0h0))
node _io_out_0_bits_T_91 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[3], UInt<1>(0h0))
node _io_out_0_bits_T_92 = or(_io_out_0_bits_T_88, _io_out_0_bits_T_89)
node _io_out_0_bits_T_93 = or(_io_out_0_bits_T_92, _io_out_0_bits_T_90)
node _io_out_0_bits_T_94 = or(_io_out_0_bits_T_93, _io_out_0_bits_T_91)
wire _io_out_0_bits_WIRE_16 : UInt<1>
connect _io_out_0_bits_WIRE_16, _io_out_0_bits_T_94
connect _io_out_0_bits_WIRE_12[3], _io_out_0_bits_WIRE_16
node _io_out_0_bits_T_95 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[4], UInt<1>(0h0))
node _io_out_0_bits_T_96 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[4], UInt<1>(0h0))
node _io_out_0_bits_T_97 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[4], UInt<1>(0h0))
node _io_out_0_bits_T_98 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[4], UInt<1>(0h0))
node _io_out_0_bits_T_99 = or(_io_out_0_bits_T_95, _io_out_0_bits_T_96)
node _io_out_0_bits_T_100 = or(_io_out_0_bits_T_99, _io_out_0_bits_T_97)
node _io_out_0_bits_T_101 = or(_io_out_0_bits_T_100, _io_out_0_bits_T_98)
wire _io_out_0_bits_WIRE_17 : UInt<1>
connect _io_out_0_bits_WIRE_17, _io_out_0_bits_T_101
connect _io_out_0_bits_WIRE_12[4], _io_out_0_bits_WIRE_17
node _io_out_0_bits_T_102 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[5], UInt<1>(0h0))
node _io_out_0_bits_T_103 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[5], UInt<1>(0h0))
node _io_out_0_bits_T_104 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[5], UInt<1>(0h0))
node _io_out_0_bits_T_105 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[5], UInt<1>(0h0))
node _io_out_0_bits_T_106 = or(_io_out_0_bits_T_102, _io_out_0_bits_T_103)
node _io_out_0_bits_T_107 = or(_io_out_0_bits_T_106, _io_out_0_bits_T_104)
node _io_out_0_bits_T_108 = or(_io_out_0_bits_T_107, _io_out_0_bits_T_105)
wire _io_out_0_bits_WIRE_18 : UInt<1>
connect _io_out_0_bits_WIRE_18, _io_out_0_bits_T_108
connect _io_out_0_bits_WIRE_12[5], _io_out_0_bits_WIRE_18
node _io_out_0_bits_T_109 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[6], UInt<1>(0h0))
node _io_out_0_bits_T_110 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[6], UInt<1>(0h0))
node _io_out_0_bits_T_111 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[6], UInt<1>(0h0))
node _io_out_0_bits_T_112 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[6], UInt<1>(0h0))
node _io_out_0_bits_T_113 = or(_io_out_0_bits_T_109, _io_out_0_bits_T_110)
node _io_out_0_bits_T_114 = or(_io_out_0_bits_T_113, _io_out_0_bits_T_111)
node _io_out_0_bits_T_115 = or(_io_out_0_bits_T_114, _io_out_0_bits_T_112)
wire _io_out_0_bits_WIRE_19 : UInt<1>
connect _io_out_0_bits_WIRE_19, _io_out_0_bits_T_115
connect _io_out_0_bits_WIRE_12[6], _io_out_0_bits_WIRE_19
node _io_out_0_bits_T_116 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[7], UInt<1>(0h0))
node _io_out_0_bits_T_117 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[7], UInt<1>(0h0))
node _io_out_0_bits_T_118 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[7], UInt<1>(0h0))
node _io_out_0_bits_T_119 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[7], UInt<1>(0h0))
node _io_out_0_bits_T_120 = or(_io_out_0_bits_T_116, _io_out_0_bits_T_117)
node _io_out_0_bits_T_121 = or(_io_out_0_bits_T_120, _io_out_0_bits_T_118)
node _io_out_0_bits_T_122 = or(_io_out_0_bits_T_121, _io_out_0_bits_T_119)
wire _io_out_0_bits_WIRE_20 : UInt<1>
connect _io_out_0_bits_WIRE_20, _io_out_0_bits_T_122
connect _io_out_0_bits_WIRE_12[7], _io_out_0_bits_WIRE_20
connect _io_out_0_bits_WIRE_2.`1`, _io_out_0_bits_WIRE_12
wire _io_out_0_bits_WIRE_21 : UInt<1>[8]
node _io_out_0_bits_T_123 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[0], UInt<1>(0h0))
node _io_out_0_bits_T_124 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[0], UInt<1>(0h0))
node _io_out_0_bits_T_125 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[0], UInt<1>(0h0))
node _io_out_0_bits_T_126 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[0], UInt<1>(0h0))
node _io_out_0_bits_T_127 = or(_io_out_0_bits_T_123, _io_out_0_bits_T_124)
node _io_out_0_bits_T_128 = or(_io_out_0_bits_T_127, _io_out_0_bits_T_125)
node _io_out_0_bits_T_129 = or(_io_out_0_bits_T_128, _io_out_0_bits_T_126)
wire _io_out_0_bits_WIRE_22 : UInt<1>
connect _io_out_0_bits_WIRE_22, _io_out_0_bits_T_129
connect _io_out_0_bits_WIRE_21[0], _io_out_0_bits_WIRE_22
node _io_out_0_bits_T_130 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[1], UInt<1>(0h0))
node _io_out_0_bits_T_131 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[1], UInt<1>(0h0))
node _io_out_0_bits_T_132 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[1], UInt<1>(0h0))
node _io_out_0_bits_T_133 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[1], UInt<1>(0h0))
node _io_out_0_bits_T_134 = or(_io_out_0_bits_T_130, _io_out_0_bits_T_131)
node _io_out_0_bits_T_135 = or(_io_out_0_bits_T_134, _io_out_0_bits_T_132)
node _io_out_0_bits_T_136 = or(_io_out_0_bits_T_135, _io_out_0_bits_T_133)
wire _io_out_0_bits_WIRE_23 : UInt<1>
connect _io_out_0_bits_WIRE_23, _io_out_0_bits_T_136
connect _io_out_0_bits_WIRE_21[1], _io_out_0_bits_WIRE_23
node _io_out_0_bits_T_137 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[2], UInt<1>(0h0))
node _io_out_0_bits_T_138 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[2], UInt<1>(0h0))
node _io_out_0_bits_T_139 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[2], UInt<1>(0h0))
node _io_out_0_bits_T_140 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[2], UInt<1>(0h0))
node _io_out_0_bits_T_141 = or(_io_out_0_bits_T_137, _io_out_0_bits_T_138)
node _io_out_0_bits_T_142 = or(_io_out_0_bits_T_141, _io_out_0_bits_T_139)
node _io_out_0_bits_T_143 = or(_io_out_0_bits_T_142, _io_out_0_bits_T_140)
wire _io_out_0_bits_WIRE_24 : UInt<1>
connect _io_out_0_bits_WIRE_24, _io_out_0_bits_T_143
connect _io_out_0_bits_WIRE_21[2], _io_out_0_bits_WIRE_24
node _io_out_0_bits_T_144 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[3], UInt<1>(0h0))
node _io_out_0_bits_T_145 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[3], UInt<1>(0h0))
node _io_out_0_bits_T_146 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[3], UInt<1>(0h0))
node _io_out_0_bits_T_147 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[3], UInt<1>(0h0))
node _io_out_0_bits_T_148 = or(_io_out_0_bits_T_144, _io_out_0_bits_T_145)
node _io_out_0_bits_T_149 = or(_io_out_0_bits_T_148, _io_out_0_bits_T_146)
node _io_out_0_bits_T_150 = or(_io_out_0_bits_T_149, _io_out_0_bits_T_147)
wire _io_out_0_bits_WIRE_25 : UInt<1>
connect _io_out_0_bits_WIRE_25, _io_out_0_bits_T_150
connect _io_out_0_bits_WIRE_21[3], _io_out_0_bits_WIRE_25
node _io_out_0_bits_T_151 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[4], UInt<1>(0h0))
node _io_out_0_bits_T_152 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[4], UInt<1>(0h0))
node _io_out_0_bits_T_153 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[4], UInt<1>(0h0))
node _io_out_0_bits_T_154 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[4], UInt<1>(0h0))
node _io_out_0_bits_T_155 = or(_io_out_0_bits_T_151, _io_out_0_bits_T_152)
node _io_out_0_bits_T_156 = or(_io_out_0_bits_T_155, _io_out_0_bits_T_153)
node _io_out_0_bits_T_157 = or(_io_out_0_bits_T_156, _io_out_0_bits_T_154)
wire _io_out_0_bits_WIRE_26 : UInt<1>
connect _io_out_0_bits_WIRE_26, _io_out_0_bits_T_157
connect _io_out_0_bits_WIRE_21[4], _io_out_0_bits_WIRE_26
node _io_out_0_bits_T_158 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[5], UInt<1>(0h0))
node _io_out_0_bits_T_159 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[5], UInt<1>(0h0))
node _io_out_0_bits_T_160 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[5], UInt<1>(0h0))
node _io_out_0_bits_T_161 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[5], UInt<1>(0h0))
node _io_out_0_bits_T_162 = or(_io_out_0_bits_T_158, _io_out_0_bits_T_159)
node _io_out_0_bits_T_163 = or(_io_out_0_bits_T_162, _io_out_0_bits_T_160)
node _io_out_0_bits_T_164 = or(_io_out_0_bits_T_163, _io_out_0_bits_T_161)
wire _io_out_0_bits_WIRE_27 : UInt<1>
connect _io_out_0_bits_WIRE_27, _io_out_0_bits_T_164
connect _io_out_0_bits_WIRE_21[5], _io_out_0_bits_WIRE_27
node _io_out_0_bits_T_165 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[6], UInt<1>(0h0))
node _io_out_0_bits_T_166 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[6], UInt<1>(0h0))
node _io_out_0_bits_T_167 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[6], UInt<1>(0h0))
node _io_out_0_bits_T_168 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[6], UInt<1>(0h0))
node _io_out_0_bits_T_169 = or(_io_out_0_bits_T_165, _io_out_0_bits_T_166)
node _io_out_0_bits_T_170 = or(_io_out_0_bits_T_169, _io_out_0_bits_T_167)
node _io_out_0_bits_T_171 = or(_io_out_0_bits_T_170, _io_out_0_bits_T_168)
wire _io_out_0_bits_WIRE_28 : UInt<1>
connect _io_out_0_bits_WIRE_28, _io_out_0_bits_T_171
connect _io_out_0_bits_WIRE_21[6], _io_out_0_bits_WIRE_28
node _io_out_0_bits_T_172 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[7], UInt<1>(0h0))
node _io_out_0_bits_T_173 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[7], UInt<1>(0h0))
node _io_out_0_bits_T_174 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[7], UInt<1>(0h0))
node _io_out_0_bits_T_175 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[7], UInt<1>(0h0))
node _io_out_0_bits_T_176 = or(_io_out_0_bits_T_172, _io_out_0_bits_T_173)
node _io_out_0_bits_T_177 = or(_io_out_0_bits_T_176, _io_out_0_bits_T_174)
node _io_out_0_bits_T_178 = or(_io_out_0_bits_T_177, _io_out_0_bits_T_175)
wire _io_out_0_bits_WIRE_29 : UInt<1>
connect _io_out_0_bits_WIRE_29, _io_out_0_bits_T_178
connect _io_out_0_bits_WIRE_21[7], _io_out_0_bits_WIRE_29
connect _io_out_0_bits_WIRE_2.`2`, _io_out_0_bits_WIRE_21
wire _io_out_0_bits_WIRE_30 : UInt<1>[8]
node _io_out_0_bits_T_179 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[0], UInt<1>(0h0))
node _io_out_0_bits_T_180 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[0], UInt<1>(0h0))
node _io_out_0_bits_T_181 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[0], UInt<1>(0h0))
node _io_out_0_bits_T_182 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`3`[0], UInt<1>(0h0))
node _io_out_0_bits_T_183 = or(_io_out_0_bits_T_179, _io_out_0_bits_T_180)
node _io_out_0_bits_T_184 = or(_io_out_0_bits_T_183, _io_out_0_bits_T_181)
node _io_out_0_bits_T_185 = or(_io_out_0_bits_T_184, _io_out_0_bits_T_182)
wire _io_out_0_bits_WIRE_31 : UInt<1>
connect _io_out_0_bits_WIRE_31, _io_out_0_bits_T_185
connect _io_out_0_bits_WIRE_30[0], _io_out_0_bits_WIRE_31
node _io_out_0_bits_T_186 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[1], UInt<1>(0h0))
node _io_out_0_bits_T_187 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[1], UInt<1>(0h0))
node _io_out_0_bits_T_188 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[1], UInt<1>(0h0))
node _io_out_0_bits_T_189 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`3`[1], UInt<1>(0h0))
node _io_out_0_bits_T_190 = or(_io_out_0_bits_T_186, _io_out_0_bits_T_187)
node _io_out_0_bits_T_191 = or(_io_out_0_bits_T_190, _io_out_0_bits_T_188)
node _io_out_0_bits_T_192 = or(_io_out_0_bits_T_191, _io_out_0_bits_T_189)
wire _io_out_0_bits_WIRE_32 : UInt<1>
connect _io_out_0_bits_WIRE_32, _io_out_0_bits_T_192
connect _io_out_0_bits_WIRE_30[1], _io_out_0_bits_WIRE_32
node _io_out_0_bits_T_193 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[2], UInt<1>(0h0))
node _io_out_0_bits_T_194 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[2], UInt<1>(0h0))
node _io_out_0_bits_T_195 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[2], UInt<1>(0h0))
node _io_out_0_bits_T_196 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`3`[2], UInt<1>(0h0))
node _io_out_0_bits_T_197 = or(_io_out_0_bits_T_193, _io_out_0_bits_T_194)
node _io_out_0_bits_T_198 = or(_io_out_0_bits_T_197, _io_out_0_bits_T_195)
node _io_out_0_bits_T_199 = or(_io_out_0_bits_T_198, _io_out_0_bits_T_196)
wire _io_out_0_bits_WIRE_33 : UInt<1>
connect _io_out_0_bits_WIRE_33, _io_out_0_bits_T_199
connect _io_out_0_bits_WIRE_30[2], _io_out_0_bits_WIRE_33
node _io_out_0_bits_T_200 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[3], UInt<1>(0h0))
node _io_out_0_bits_T_201 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[3], UInt<1>(0h0))
node _io_out_0_bits_T_202 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[3], UInt<1>(0h0))
node _io_out_0_bits_T_203 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`3`[3], UInt<1>(0h0))
node _io_out_0_bits_T_204 = or(_io_out_0_bits_T_200, _io_out_0_bits_T_201)
node _io_out_0_bits_T_205 = or(_io_out_0_bits_T_204, _io_out_0_bits_T_202)
node _io_out_0_bits_T_206 = or(_io_out_0_bits_T_205, _io_out_0_bits_T_203)
wire _io_out_0_bits_WIRE_34 : UInt<1>
connect _io_out_0_bits_WIRE_34, _io_out_0_bits_T_206
connect _io_out_0_bits_WIRE_30[3], _io_out_0_bits_WIRE_34
node _io_out_0_bits_T_207 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[4], UInt<1>(0h0))
node _io_out_0_bits_T_208 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[4], UInt<1>(0h0))
node _io_out_0_bits_T_209 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[4], UInt<1>(0h0))
node _io_out_0_bits_T_210 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`3`[4], UInt<1>(0h0))
node _io_out_0_bits_T_211 = or(_io_out_0_bits_T_207, _io_out_0_bits_T_208)
node _io_out_0_bits_T_212 = or(_io_out_0_bits_T_211, _io_out_0_bits_T_209)
node _io_out_0_bits_T_213 = or(_io_out_0_bits_T_212, _io_out_0_bits_T_210)
wire _io_out_0_bits_WIRE_35 : UInt<1>
connect _io_out_0_bits_WIRE_35, _io_out_0_bits_T_213
connect _io_out_0_bits_WIRE_30[4], _io_out_0_bits_WIRE_35
node _io_out_0_bits_T_214 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[5], UInt<1>(0h0))
node _io_out_0_bits_T_215 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[5], UInt<1>(0h0))
node _io_out_0_bits_T_216 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[5], UInt<1>(0h0))
node _io_out_0_bits_T_217 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`3`[5], UInt<1>(0h0))
node _io_out_0_bits_T_218 = or(_io_out_0_bits_T_214, _io_out_0_bits_T_215)
node _io_out_0_bits_T_219 = or(_io_out_0_bits_T_218, _io_out_0_bits_T_216)
node _io_out_0_bits_T_220 = or(_io_out_0_bits_T_219, _io_out_0_bits_T_217)
wire _io_out_0_bits_WIRE_36 : UInt<1>
connect _io_out_0_bits_WIRE_36, _io_out_0_bits_T_220
connect _io_out_0_bits_WIRE_30[5], _io_out_0_bits_WIRE_36
node _io_out_0_bits_T_221 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[6], UInt<1>(0h0))
node _io_out_0_bits_T_222 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[6], UInt<1>(0h0))
node _io_out_0_bits_T_223 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[6], UInt<1>(0h0))
node _io_out_0_bits_T_224 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`3`[6], UInt<1>(0h0))
node _io_out_0_bits_T_225 = or(_io_out_0_bits_T_221, _io_out_0_bits_T_222)
node _io_out_0_bits_T_226 = or(_io_out_0_bits_T_225, _io_out_0_bits_T_223)
node _io_out_0_bits_T_227 = or(_io_out_0_bits_T_226, _io_out_0_bits_T_224)
wire _io_out_0_bits_WIRE_37 : UInt<1>
connect _io_out_0_bits_WIRE_37, _io_out_0_bits_T_227
connect _io_out_0_bits_WIRE_30[6], _io_out_0_bits_WIRE_37
node _io_out_0_bits_T_228 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[7], UInt<1>(0h0))
node _io_out_0_bits_T_229 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[7], UInt<1>(0h0))
node _io_out_0_bits_T_230 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[7], UInt<1>(0h0))
node _io_out_0_bits_T_231 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`3`[7], UInt<1>(0h0))
node _io_out_0_bits_T_232 = or(_io_out_0_bits_T_228, _io_out_0_bits_T_229)
node _io_out_0_bits_T_233 = or(_io_out_0_bits_T_232, _io_out_0_bits_T_230)
node _io_out_0_bits_T_234 = or(_io_out_0_bits_T_233, _io_out_0_bits_T_231)
wire _io_out_0_bits_WIRE_38 : UInt<1>
connect _io_out_0_bits_WIRE_38, _io_out_0_bits_T_234
connect _io_out_0_bits_WIRE_30[7], _io_out_0_bits_WIRE_38
connect _io_out_0_bits_WIRE_2.`3`, _io_out_0_bits_WIRE_30
connect _io_out_0_bits_WIRE.vc_sel, _io_out_0_bits_WIRE_2
connect io.out[0].bits, _io_out_0_bits_WIRE
node _T_10 = bits(chosen, 0, 0)
node _T_11 = and(_T_10, io.out[0].ready)
when _T_11 :
connect io.in[0].ready, UInt<1>(0h1)
node _T_12 = bits(chosen, 1, 1)
node _T_13 = and(_T_12, io.out[0].ready)
when _T_13 :
connect io.in[1].ready, UInt<1>(0h1)
node _T_14 = bits(chosen, 2, 2)
node _T_15 = and(_T_14, io.out[0].ready)
when _T_15 :
connect io.in[2].ready, UInt<1>(0h1)
node _T_16 = bits(chosen, 3, 3)
node _T_17 = and(_T_16, io.out[0].ready)
when _T_17 :
connect io.in[3].ready, UInt<1>(0h1)
node _T_18 = or(UInt<4>(0h0), chosen)
node _T_19 = and(io.out[0].ready, io.out[0].valid)
when _T_19 :
node _lock_0_T = not(in_tails)
node _lock_0_T_1 = and(chosen, _lock_0_T)
connect lock_0, _lock_0_T_1
node _T_20 = and(io.out[0].ready, io.out[0].valid)
when _T_20 :
node _mask_T = shr(io.chosen_oh[0], 0)
node _mask_T_1 = shr(io.chosen_oh[0], 1)
node _mask_T_2 = shr(io.chosen_oh[0], 2)
node _mask_T_3 = shr(io.chosen_oh[0], 3)
node _mask_T_4 = or(_mask_T, _mask_T_1)
node _mask_T_5 = or(_mask_T_4, _mask_T_2)
node _mask_T_6 = or(_mask_T_5, _mask_T_3)
connect mask, _mask_T_6
else :
node _mask_T_7 = not(mask)
node _mask_T_8 = eq(_mask_T_7, UInt<1>(0h0))
node _mask_T_9 = shl(mask, 1)
node _mask_T_10 = or(_mask_T_9, UInt<1>(0h1))
node _mask_T_11 = mux(_mask_T_8, UInt<1>(0h0), _mask_T_10)
connect mask, _mask_T_11 | module SwitchArbiter_71( // @[SwitchAllocator.scala:17:7]
input clock, // @[SwitchAllocator.scala:17:7]
input reset, // @[SwitchAllocator.scala:17:7]
output io_in_0_ready, // @[SwitchAllocator.scala:18:14]
input io_in_0_valid, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_3_2, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_3_3, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_3_4, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_3_5, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_3_6, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_3_7, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_2_3, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_2_4, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_2_5, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_2_6, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_2_7, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_in_1_ready, // @[SwitchAllocator.scala:18:14]
input io_in_1_valid, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_3_2, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_3_3, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_3_4, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_3_5, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_3_6, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_3_7, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_2_3, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_2_4, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_2_5, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_2_6, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_2_7, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_in_2_ready, // @[SwitchAllocator.scala:18:14]
input io_in_2_valid, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_3_2, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_3_3, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_3_4, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_3_5, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_3_6, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_3_7, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_2_3, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_2_4, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_2_5, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_2_6, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_2_7, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_in_3_ready, // @[SwitchAllocator.scala:18:14]
input io_in_3_valid, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_3_2, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_3_3, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_3_4, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_3_5, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_3_6, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_3_7, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_2_3, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_2_4, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_2_5, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_2_6, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_2_7, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_out_0_valid, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_3_2, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_3_3, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_3_4, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_3_5, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_3_6, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_3_7, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_2_3, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_2_4, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_2_5, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_2_6, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_2_7, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14]
output [3:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14]
);
reg [3:0] lock_0; // @[SwitchAllocator.scala:24:38]
wire [3:0] unassigned = {io_in_3_valid, io_in_2_valid, io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}]
reg [3:0] mask; // @[SwitchAllocator.scala:27:21]
wire [3:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}]
wire [7:0] sel = _sel_T_1[0] ? 8'h1 : _sel_T_1[1] ? 8'h2 : _sel_T_1[2] ? 8'h4 : _sel_T_1[3] ? 8'h8 : unassigned[0] ? 8'h10 : unassigned[1] ? 8'h20 : unassigned[2] ? 8'h40 : {unassigned[3], 7'h0}; // @[OneHot.scala:85:71]
wire [3:0] in_valids = {io_in_3_valid, io_in_2_valid, io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24]
wire [3:0] chosen = (|(in_valids & lock_0)) ? lock_0 : sel[3:0] | sel[7:4]; // @[Mux.scala:50:70]
wire [3:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35]
wire [2:0] _GEN = chosen[2:0] | chosen[3:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
wire [1:0] _GEN_0 = _GEN[1:0] | chosen[3:2]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
always @(posedge clock) begin // @[SwitchAllocator.scala:17:7]
if (reset) begin // @[SwitchAllocator.scala:17:7]
lock_0 <= 4'h0; // @[SwitchAllocator.scala:24:38]
mask <= 4'h0; // @[SwitchAllocator.scala:27:21]
end
else begin // @[SwitchAllocator.scala:17:7]
if (|_io_out_0_valid_T) // @[SwitchAllocator.scala:44:{35,45}]
lock_0 <= chosen & ~{io_in_3_bits_tail, io_in_2_bits_tail, io_in_1_bits_tail, io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}]
mask <= (|_io_out_0_valid_T) ? {chosen[3], _GEN[2], _GEN_0[1], _GEN_0[0] | chosen[3]} : (&mask) ? 4'h0 : {mask[2:0], 1'h1}; // @[SwitchAllocator.scala:17:7, :27:21, :42:21, :44:{35,45}, :57:25, :58:{10,55,71}, :60:{10,16,23,49}]
end
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_64 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_132
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_64( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_132 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_8 :
input clock : Clock
input reset : Reset
output io : { flip inR : { bits : UInt<32>}, flip inD : { bits : UInt<32>}, outL : { bits : UInt<32>}, outU : { bits : UInt<32>}, flip dir : UInt<1>, flip en : UInt<1>}
node _reg_T = eq(io.dir, UInt<1>(0h0))
node _reg_T_1 = mux(_reg_T, io.inR, io.inD)
reg reg : { bits : UInt<32>}, clock
when io.en :
connect reg.bits, _reg_T_1.bits
connect io.outU, reg
connect io.outL, reg | module PE_8( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [31:0] io_inR_bits, // @[Transposer.scala:101:16]
input [31:0] io_inD_bits, // @[Transposer.scala:101:16]
output [31:0] io_outL_bits, // @[Transposer.scala:101:16]
output [31:0] io_outU_bits, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [31:0] io_inR_bits_0 = io_inR_bits; // @[Transposer.scala:100:9]
wire [31:0] io_inD_bits_0 = io_inD_bits; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [31:0] io_outL_bits_0; // @[Transposer.scala:100:9]
wire [31:0] io_outU_bits_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [31:0] _reg_T_1_bits = _reg_T ? io_inR_bits_0 : io_inD_bits_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [31:0] reg_bits; // @[Transposer.scala:110:24]
assign io_outL_bits_0 = reg_bits; // @[Transposer.scala:100:9, :110:24]
assign io_outU_bits_0 = reg_bits; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_bits <= _reg_T_1_bits; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL_bits = io_outL_bits_0; // @[Transposer.scala:100:9]
assign io_outU_bits = io_outU_bits_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_45 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_57
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_45( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_57 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IntXbar_i5_o2_5 :
output auto : { flip anon_in_4 : UInt<1>[1], flip anon_in_3 : UInt<1>[1], flip anon_in_2 : UInt<1>[1], flip anon_in_1 : UInt<1>[1], flip anon_in_0 : UInt<1>[1], anon_out_1 : UInt<1>[5], anon_out_0 : UInt<1>[5]}
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
wire anonIn : UInt<1>[1]
invalidate anonIn[0]
wire anonIn_1 : UInt<1>[1]
invalidate anonIn_1[0]
wire anonIn_2 : UInt<1>[1]
invalidate anonIn_2[0]
wire anonIn_3 : UInt<1>[1]
invalidate anonIn_3[0]
wire anonIn_4 : UInt<1>[1]
invalidate anonIn_4[0]
wire anonOut : UInt<1>[5]
invalidate anonOut[0]
invalidate anonOut[1]
invalidate anonOut[2]
invalidate anonOut[3]
invalidate anonOut[4]
wire x1_anonOut : UInt<1>[5]
invalidate x1_anonOut[0]
invalidate x1_anonOut[1]
invalidate x1_anonOut[2]
invalidate x1_anonOut[3]
invalidate x1_anonOut[4]
connect auto.anon_out_0, anonOut
connect auto.anon_out_1, x1_anonOut
connect anonIn, auto.anon_in_0
connect anonIn_1, auto.anon_in_1
connect anonIn_2, auto.anon_in_2
connect anonIn_3, auto.anon_in_3
connect anonIn_4, auto.anon_in_4
connect anonOut[0], anonIn[0]
connect anonOut[1], anonIn_1[0]
connect anonOut[2], anonIn_2[0]
connect anonOut[3], anonIn_3[0]
connect anonOut[4], anonIn_4[0]
connect x1_anonOut[0], anonIn[0]
connect x1_anonOut[1], anonIn_1[0]
connect x1_anonOut[2], anonIn_2[0]
connect x1_anonOut[3], anonIn_3[0]
connect x1_anonOut[4], anonIn_4[0] | module IntXbar_i5_o2_5(); // @[Xbar.scala:22:9]
wire auto_anon_in_4_0 = 1'h0; // @[Xbar.scala:22:9]
wire auto_anon_in_3_0 = 1'h0; // @[Xbar.scala:22:9]
wire auto_anon_in_2_0 = 1'h0; // @[Xbar.scala:22:9]
wire auto_anon_in_1_0 = 1'h0; // @[Xbar.scala:22:9]
wire auto_anon_in_0_0 = 1'h0; // @[Xbar.scala:22:9]
wire auto_anon_out_1_0 = 1'h0; // @[Xbar.scala:22:9]
wire auto_anon_out_1_1 = 1'h0; // @[Xbar.scala:22:9]
wire auto_anon_out_1_2 = 1'h0; // @[Xbar.scala:22:9]
wire auto_anon_out_1_3 = 1'h0; // @[Xbar.scala:22:9]
wire auto_anon_out_1_4 = 1'h0; // @[Xbar.scala:22:9]
wire auto_anon_out_0_0 = 1'h0; // @[Xbar.scala:22:9]
wire auto_anon_out_0_1 = 1'h0; // @[Xbar.scala:22:9]
wire auto_anon_out_0_2 = 1'h0; // @[Xbar.scala:22:9]
wire auto_anon_out_0_3 = 1'h0; // @[Xbar.scala:22:9]
wire auto_anon_out_0_4 = 1'h0; // @[Xbar.scala:22:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire anonIn_0 = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_1_0 = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_2_0 = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_3_0 = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_4_0 = 1'h0; // @[MixedNode.scala:551:17]
wire anonOut_0 = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_1 = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_2 = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_3 = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_4 = 1'h0; // @[MixedNode.scala:542:17]
wire x1_anonOut_0 = 1'h0; // @[MixedNode.scala:542:17]
wire x1_anonOut_1 = 1'h0; // @[MixedNode.scala:542:17]
wire x1_anonOut_2 = 1'h0; // @[MixedNode.scala:542:17]
wire x1_anonOut_3 = 1'h0; // @[MixedNode.scala:542:17]
wire x1_anonOut_4 = 1'h0; // @[MixedNode.scala:542:17]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_29 :
output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}}
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags)
node _sigSum_T = bits(io.mulAddResult, 48, 48)
node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1))
node _sigSum_T_2 = tail(_sigSum_T_1, 1)
node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC)
node _sigSum_T_4 = bits(io.mulAddResult, 47, 0)
node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4)
node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC)
node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags)
node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T)
node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1)
node CDom_sExp = asSInt(_CDom_sExp_T_2)
node _CDom_absSigSum_T = bits(sigSum, 74, 25)
node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T)
node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24)
node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2)
node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26)
node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4)
node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5)
node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1)
node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T)
node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1)
node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1)
node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3)
node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4)
node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist)
node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21)
node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0)
node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3)
wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0)
node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T)
connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1
node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4)
node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T)
connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1
node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8)
node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T)
connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1
node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12)
node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T)
connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1
node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16)
node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T)
connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1
node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20)
node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T)
connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1
node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24)
node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T)
connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1
node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1])
node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0])
node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3])
node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5])
node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo)
node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo)
node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2)
node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3)
node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4)
node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1)
node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0)
node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0)
node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0)
node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1)
node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9)
node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2)
node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0)
node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1)
node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13)
node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14)
node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4)
node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0)
node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1)
node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18)
node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19)
node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20)
node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21)
node _CDom_sig_T = shr(CDom_mainSig, 3)
node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0)
node _CDom_sig_T_2 = orr(_CDom_sig_T_1)
node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra)
node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra)
node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4)
node notCDom_signSigSum = bits(sigSum, 51, 51)
node _notCDom_absSigSum_T = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T)
node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags)
node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1)
node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4)
wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26]
node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0)
node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T)
connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2)
node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T)
connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4)
node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T)
connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6)
node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T)
connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8)
node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T)
connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10)
node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T)
connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12)
node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T)
connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14)
node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T)
connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16)
node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T)
connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18)
node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T)
connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20)
node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T)
connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22)
node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T)
connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24)
node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T)
connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26)
node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T)
connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28)
node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T)
connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30)
node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T)
connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32)
node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T)
connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34)
node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T)
connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36)
node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T)
connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38)
node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T)
connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40)
node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T)
connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42)
node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T)
connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44)
node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T)
connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46)
node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T)
connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48)
node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T)
connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50)
node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T)
connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1
node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1])
node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0])
node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4])
node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3])
node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo)
node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7])
node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6])
node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9])
node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11])
node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo)
node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo)
node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo)
node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14])
node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13])
node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17])
node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16])
node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo)
node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20])
node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19])
node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22])
node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24])
node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo)
node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo)
node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0)
node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1)
node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2)
node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3)
node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4)
node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5)
node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6)
node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7)
node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8)
node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9)
node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10)
node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11)
node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12)
node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13)
node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14)
node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15)
node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16)
node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17)
node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18)
node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19)
node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20)
node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21)
node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22)
node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23)
node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24)
node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25)
node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19))
node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26)
node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27)
node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28)
node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29)
node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30)
node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31)
node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32)
node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33)
node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34)
node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35)
node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36)
node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37)
node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38)
node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39)
node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40)
node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41)
node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42)
node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43)
node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44)
node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45)
node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46)
node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47)
node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48)
node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49)
node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1)
node _notCDom_sExp_T = cvt(notCDom_nearNormDist)
node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T)
node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1)
node notCDom_sExp = asSInt(_notCDom_sExp_T_2)
node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist)
node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23)
node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0)
node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0)
wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0)
node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T)
connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1
node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2)
node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T)
connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1
node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4)
node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T)
connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1
node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6)
node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T)
connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1
node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8)
node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T)
connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1
node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10)
node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T)
connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1
node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12)
node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T)
connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1
node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1])
node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0])
node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3])
node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5])
node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo)
node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo)
node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1)
node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3)
node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4)
node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1)
node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0)
node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0)
node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0)
node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1)
node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9)
node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2)
node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0)
node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1)
node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13)
node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14)
node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4)
node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0)
node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1)
node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18)
node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19)
node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20)
node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21)
node _notCDom_sig_T = shr(notCDom_mainSig, 3)
node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0)
node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1)
node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra)
node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3)
node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25)
node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0))
node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum)
node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T)
node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC)
node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB)
node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC)
node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB)
node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T)
node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB)
node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2)
node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0))
node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5)
node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC)
node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags)
node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8)
connect io.invalidExc, _io_invalidExc_T_9
node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC)
connect io.rawOut.isNaN, _io_rawOut_isNaN_T
connect io.rawOut.isInf, notNaN_isInfOut
node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0))
node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation)
node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1)
connect io.rawOut.isZero, _io_rawOut_isZero_T_2
node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd)
node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC)
node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1)
node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0))
node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3)
node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd)
node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC)
node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6)
node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min)
node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC)
node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9)
node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10)
node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0))
node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0))
node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13)
node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign)
node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15)
node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16)
connect io.rawOut.sign, _io_rawOut_sign_T_17
node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
connect io.rawOut.sExp, _io_rawOut_sExp_T
node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
connect io.rawOut.sig, _io_rawOut_sig_T | module MulAddRecFNToRaw_postMul_e8_s24_29( // @[MulAddRecFN.scala:169:7]
input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16]
input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16]
input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16]
input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16]
input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16]
output io_invalidExc, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16]
output io_rawOut_sign, // @[MulAddRecFN.scala:172:16]
output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16]
output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16]
);
wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7]
wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7]
wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7]
wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7]
wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29]
wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45]
wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26]
wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16]
wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57]
wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48]
wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44]
wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25]
wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50]
wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26]
wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25]
wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42]
wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32]
wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47]
wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47]
wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47]
wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28]
wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28]
wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12]
wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69]
wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43]
wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}]
wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43]
wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43]
wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20]
wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}]
wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46]
wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46]
wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23]
wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23]
wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71]
wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21]
wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}]
wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}]
wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19]
wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}]
wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37]
wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24]
wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}]
wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36]
wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}]
wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15]
assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20]
wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51]
wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20]
wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73]
wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25]
wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25]
wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}]
wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}]
wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}]
wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61]
wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36]
wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20]
wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19]
wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}]
wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}]
wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41]
wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41]
wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15]
assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20]
wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20]
wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20]
wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70]
wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70]
wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70]
wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76]
wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}]
wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46]
wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46]
wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27]
wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}]
wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20]
wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}]
wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15]
assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20]
wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70]
wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20]
wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11]
wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28]
wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28]
wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}]
wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}]
wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39]
wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21]
wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54]
wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36]
wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36]
wire _GEN_0 = io_fromPreMul_isInfA_0 | io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49]
wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49]
assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49]
wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36]
assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36]
assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44]
wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 | io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32]
wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}]
wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26]
wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31]
wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 | _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31]
wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32]
wire _io_invalidExc_T_3 = _io_invalidExc_T_1 | _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32]
wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10]
wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36]
wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61]
wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35]
assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35]
assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57]
assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48]
wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14]
wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}]
assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42]
assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25]
wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27]
wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31]
wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31]
wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}]
wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36]
wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36]
wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48]
wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37]
wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10]
wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31]
wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}]
wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17]
wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17]
assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49]
assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50]
assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26]
assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26]
assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25]
assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25]
assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_403 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_147
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<8>, clock
reg c2 : SInt<8>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h0), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node _c1_T = bits(io.in_d, 7, 0)
node _c1_T_1 = asSInt(_c1_T)
connect c1, _c1_T_1
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node _c2_T = bits(io.in_d, 7, 0)
node _c2_T_1 = asSInt(_c2_T)
connect c2, _c2_T_1
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h0), _T_4)
node _T_6 = or(UInt<1>(0h1), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_403( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_147 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_15 :
input clock : Clock
input reset : Reset
output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1)
reg flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, clock
inst q of Queue3_EgressFlit_15
connect q.clock, clock
connect q.reset, reset
connect q.io.enq.valid, io.in[0].valid
connect q.io.enq.bits.head, io.in[0].bits.head
connect q.io.enq.bits.tail, io.in[0].bits.tail
node _q_io_enq_bits_ingress_id_T = eq(UInt<4>(0h8), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1)
node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<4>(0he), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4)
node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7)
node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<3>(0h7), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10)
node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<4>(0hd), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13)
node _q_io_enq_bits_ingress_id_T_15 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_16 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_17 = and(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16)
node _q_io_enq_bits_ingress_id_T_18 = eq(UInt<4>(0hb), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_19 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_20 = and(_q_io_enq_bits_ingress_id_T_18, _q_io_enq_bits_ingress_id_T_19)
node _q_io_enq_bits_ingress_id_T_21 = eq(UInt<2>(0h2), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_22 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_23 = and(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_22)
node _q_io_enq_bits_ingress_id_T_24 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<6>(0h10), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_25 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<6>(0h19), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_26 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<6>(0ha), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_27 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<6>(0hd), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_28 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<6>(0h16), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_29 = mux(_q_io_enq_bits_ingress_id_T_17, UInt<6>(0h4), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_30 = mux(_q_io_enq_bits_ingress_id_T_20, UInt<6>(0h13), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_31 = mux(_q_io_enq_bits_ingress_id_T_23, UInt<6>(0h7), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_32 = or(_q_io_enq_bits_ingress_id_T_24, _q_io_enq_bits_ingress_id_T_25)
node _q_io_enq_bits_ingress_id_T_33 = or(_q_io_enq_bits_ingress_id_T_32, _q_io_enq_bits_ingress_id_T_26)
node _q_io_enq_bits_ingress_id_T_34 = or(_q_io_enq_bits_ingress_id_T_33, _q_io_enq_bits_ingress_id_T_27)
node _q_io_enq_bits_ingress_id_T_35 = or(_q_io_enq_bits_ingress_id_T_34, _q_io_enq_bits_ingress_id_T_28)
node _q_io_enq_bits_ingress_id_T_36 = or(_q_io_enq_bits_ingress_id_T_35, _q_io_enq_bits_ingress_id_T_29)
node _q_io_enq_bits_ingress_id_T_37 = or(_q_io_enq_bits_ingress_id_T_36, _q_io_enq_bits_ingress_id_T_30)
node _q_io_enq_bits_ingress_id_T_38 = or(_q_io_enq_bits_ingress_id_T_37, _q_io_enq_bits_ingress_id_T_31)
wire _q_io_enq_bits_ingress_id_WIRE : UInt<6>
connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_38
connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE
connect q.io.enq.bits.payload, io.in[0].bits.payload
connect io.out.bits, q.io.deq.bits
connect io.out.valid, q.io.deq.valid
connect q.io.deq.ready, io.out.ready
node _T = eq(q.io.enq.ready, UInt<1>(0h0))
node _T_1 = and(q.io.enq.valid, _T)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0))
connect io.credit_available[0], _io_credit_available_0_T
node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0))
connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T
connect io.channel_status[0].flow, flow
node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail)
when _T_6 :
connect channel_empty, UInt<1>(0h1)
when io.allocs[0].alloc :
connect channel_empty, UInt<1>(0h0)
connect flow, io.allocs[0].flow | module EgressUnit_15( // @[EgressUnit.scala:12:7]
input clock, // @[EgressUnit.scala:12:7]
input reset, // @[EgressUnit.scala:12:7]
input io_in_0_valid, // @[EgressUnit.scala:18:14]
input io_in_0_bits_head, // @[EgressUnit.scala:18:14]
input io_in_0_bits_tail, // @[EgressUnit.scala:18:14]
input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14]
input [4:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14]
input [1:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14]
output io_credit_available_0, // @[EgressUnit.scala:18:14]
output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14]
input io_allocs_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14]
input io_out_ready, // @[EgressUnit.scala:18:14]
output io_out_valid, // @[EgressUnit.scala:18:14]
output io_out_bits_head, // @[EgressUnit.scala:18:14]
output io_out_bits_tail, // @[EgressUnit.scala:18:14]
output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14]
);
wire _q_io_enq_ready; // @[EgressUnit.scala:22:17]
wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17]
reg channel_empty; // @[EgressUnit.scala:20:30]
wire _q_io_enq_bits_ingress_id_T_22 = io_in_0_bits_flow_ingress_node_id == 2'h1; // @[EgressUnit.scala:32:27] |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNPipe_l2_e8_s24_7 :
input clock : Clock
input reset : Reset
output io : { flip validin : UInt<1>, flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>, validout : UInt<1>}
inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e8_s24_7
inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e8_s24_7
connect mulAddRecFNToRaw_preMul.io.op, io.op
connect mulAddRecFNToRaw_preMul.io.a, io.a
connect mulAddRecFNToRaw_preMul.io.b, io.b
connect mulAddRecFNToRaw_preMul.io.c, io.c
node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB)
node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC)
wire valid_stage0 : UInt<1>
wire roundingMode_stage0 : UInt<3>
wire detectTininess_stage0 : UInt<1>
regreset mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v, io.validin
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, clock
when io.validin :
connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b, mulAddRecFNToRaw_preMul.io.toPostMul
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out : { valid : UInt<1>, bits : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}}
connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.valid, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v
connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b
connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.bit0AlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.highAlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CDom_CAlignDist
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CIsDominant
connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.doSubMags
connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.sExpSum
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.signProd
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNAOrB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isSigNaNAny
regreset mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v, io.validin
reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b : UInt<49>, clock
when io.validin :
connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b, mulAddResult
wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out : { valid : UInt<1>, bits : UInt<49>}
connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.valid, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v
connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b
connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits
regreset mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v, io.validin
reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b : UInt<3>, clock
when io.validin :
connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b, io.roundingMode
wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>}
connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.valid, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v
connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b
connect mulAddRecFNToRaw_postMul.io.roundingMode, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits
regreset roundingMode_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect roundingMode_stage0_pipe_v, io.validin
reg roundingMode_stage0_pipe_b : UInt<3>, clock
when io.validin :
connect roundingMode_stage0_pipe_b, io.roundingMode
wire roundingMode_stage0_pipe_out : { valid : UInt<1>, bits : UInt<3>}
connect roundingMode_stage0_pipe_out.valid, roundingMode_stage0_pipe_v
connect roundingMode_stage0_pipe_out.bits, roundingMode_stage0_pipe_b
connect roundingMode_stage0, roundingMode_stage0_pipe_out.bits
regreset detectTininess_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect detectTininess_stage0_pipe_v, io.validin
reg detectTininess_stage0_pipe_b : UInt<1>, clock
when io.validin :
connect detectTininess_stage0_pipe_b, io.detectTininess
wire detectTininess_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>}
connect detectTininess_stage0_pipe_out.valid, detectTininess_stage0_pipe_v
connect detectTininess_stage0_pipe_out.bits, detectTininess_stage0_pipe_b
connect detectTininess_stage0, detectTininess_stage0_pipe_out.bits
regreset valid_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect valid_stage0_pipe_v, io.validin
reg valid_stage0_pipe_b : UInt<1>, clock
when io.validin :
connect valid_stage0_pipe_b, UInt<1>(0h0)
wire valid_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>}
connect valid_stage0_pipe_out.valid, valid_stage0_pipe_v
connect valid_stage0_pipe_out.bits, valid_stage0_pipe_b
connect valid_stage0, valid_stage0_pipe_out.valid
inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_14
regreset roundRawFNToRecFN_io_invalidExc_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect roundRawFNToRecFN_io_invalidExc_pipe_v, valid_stage0
reg roundRawFNToRecFN_io_invalidExc_pipe_b : UInt<1>, clock
when valid_stage0 :
connect roundRawFNToRecFN_io_invalidExc_pipe_b, mulAddRecFNToRaw_postMul.io.invalidExc
wire roundRawFNToRecFN_io_invalidExc_pipe_out : { valid : UInt<1>, bits : UInt<1>}
connect roundRawFNToRecFN_io_invalidExc_pipe_out.valid, roundRawFNToRecFN_io_invalidExc_pipe_v
connect roundRawFNToRecFN_io_invalidExc_pipe_out.bits, roundRawFNToRecFN_io_invalidExc_pipe_b
connect roundRawFNToRecFN.io.invalidExc, roundRawFNToRecFN_io_invalidExc_pipe_out.bits
regreset roundRawFNToRecFN_io_in_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect roundRawFNToRecFN_io_in_pipe_v, valid_stage0
reg roundRawFNToRecFN_io_in_pipe_b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, clock
when valid_stage0 :
connect roundRawFNToRecFN_io_in_pipe_b, mulAddRecFNToRaw_postMul.io.rawOut
wire roundRawFNToRecFN_io_in_pipe_out : { valid : UInt<1>, bits : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}}
connect roundRawFNToRecFN_io_in_pipe_out.valid, roundRawFNToRecFN_io_in_pipe_v
connect roundRawFNToRecFN_io_in_pipe_out.bits, roundRawFNToRecFN_io_in_pipe_b
connect roundRawFNToRecFN.io.in.sig, roundRawFNToRecFN_io_in_pipe_out.bits.sig
connect roundRawFNToRecFN.io.in.sExp, roundRawFNToRecFN_io_in_pipe_out.bits.sExp
connect roundRawFNToRecFN.io.in.sign, roundRawFNToRecFN_io_in_pipe_out.bits.sign
connect roundRawFNToRecFN.io.in.isZero, roundRawFNToRecFN_io_in_pipe_out.bits.isZero
connect roundRawFNToRecFN.io.in.isInf, roundRawFNToRecFN_io_in_pipe_out.bits.isInf
connect roundRawFNToRecFN.io.in.isNaN, roundRawFNToRecFN_io_in_pipe_out.bits.isNaN
regreset roundRawFNToRecFN_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect roundRawFNToRecFN_io_roundingMode_pipe_v, valid_stage0
reg roundRawFNToRecFN_io_roundingMode_pipe_b : UInt<3>, clock
when valid_stage0 :
connect roundRawFNToRecFN_io_roundingMode_pipe_b, roundingMode_stage0
wire roundRawFNToRecFN_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>}
connect roundRawFNToRecFN_io_roundingMode_pipe_out.valid, roundRawFNToRecFN_io_roundingMode_pipe_v
connect roundRawFNToRecFN_io_roundingMode_pipe_out.bits, roundRawFNToRecFN_io_roundingMode_pipe_b
connect roundRawFNToRecFN.io.roundingMode, roundRawFNToRecFN_io_roundingMode_pipe_out.bits
regreset roundRawFNToRecFN_io_detectTininess_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect roundRawFNToRecFN_io_detectTininess_pipe_v, valid_stage0
reg roundRawFNToRecFN_io_detectTininess_pipe_b : UInt<1>, clock
when valid_stage0 :
connect roundRawFNToRecFN_io_detectTininess_pipe_b, detectTininess_stage0
wire roundRawFNToRecFN_io_detectTininess_pipe_out : { valid : UInt<1>, bits : UInt<1>}
connect roundRawFNToRecFN_io_detectTininess_pipe_out.valid, roundRawFNToRecFN_io_detectTininess_pipe_v
connect roundRawFNToRecFN_io_detectTininess_pipe_out.bits, roundRawFNToRecFN_io_detectTininess_pipe_b
connect roundRawFNToRecFN.io.detectTininess, roundRawFNToRecFN_io_detectTininess_pipe_out.bits
regreset io_validout_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect io_validout_pipe_v, valid_stage0
reg io_validout_pipe_b : UInt<1>, clock
when valid_stage0 :
connect io_validout_pipe_b, UInt<1>(0h0)
wire io_validout_pipe_out : { valid : UInt<1>, bits : UInt<1>}
connect io_validout_pipe_out.valid, io_validout_pipe_v
connect io_validout_pipe_out.bits, io_validout_pipe_b
connect io.validout, io_validout_pipe_out.valid
connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect io.out, roundRawFNToRecFN.io.out
connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags | module MulAddRecFNPipe_l2_e8_s24_7( // @[FPU.scala:633:7]
input clock, // @[FPU.scala:633:7]
input reset, // @[FPU.scala:633:7]
input io_validin, // @[FPU.scala:638:16]
input [1:0] io_op, // @[FPU.scala:638:16]
input [32:0] io_a, // @[FPU.scala:638:16]
input [32:0] io_b, // @[FPU.scala:638:16]
input [32:0] io_c, // @[FPU.scala:638:16]
input [2:0] io_roundingMode, // @[FPU.scala:638:16]
output [32:0] io_out, // @[FPU.scala:638:16]
output [4:0] io_exceptionFlags, // @[FPU.scala:638:16]
output io_validout // @[FPU.scala:638:16]
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[FPU.scala:655:42]
wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[FPU.scala:655:42]
wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[FPU.scala:655:42]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[FPU.scala:654:41]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[FPU.scala:654:41]
wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[FPU.scala:654:41]
wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[FPU.scala:654:41]
wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[FPU.scala:654:41]
wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[FPU.scala:654:41]
wire io_validin_0 = io_validin; // @[FPU.scala:633:7]
wire [1:0] io_op_0 = io_op; // @[FPU.scala:633:7]
wire [32:0] io_a_0 = io_a; // @[FPU.scala:633:7]
wire [32:0] io_b_0 = io_b; // @[FPU.scala:633:7]
wire [32:0] io_c_0 = io_c; // @[FPU.scala:633:7]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[FPU.scala:633:7]
wire io_detectTininess = 1'h1; // @[FPU.scala:633:7]
wire detectTininess_stage0 = 1'h1; // @[FPU.scala:669:37]
wire detectTininess_stage0_pipe_out_bits = 1'h1; // @[Valid.scala:135:21]
wire valid_stage0_pipe_out_bits = 1'h0; // @[Valid.scala:135:21]
wire io_validout_pipe_out_bits = 1'h0; // @[Valid.scala:135:21]
wire io_validout_pipe_out_valid; // @[Valid.scala:135:21]
wire [32:0] io_out_0; // @[FPU.scala:633:7]
wire [4:0] io_exceptionFlags_0; // @[FPU.scala:633:7]
wire io_validout_0; // @[FPU.scala:633:7]
wire [47:0] _mulAddResult_T = {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[FPU.scala:654:41, :663:45]
wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[FPU.scala:654:41, :663:45, :664:50]
wire valid_stage0_pipe_out_valid; // @[Valid.scala:135:21]
wire valid_stage0; // @[FPU.scala:667:28]
wire [2:0] roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21]
wire [2:0] roundingMode_stage0; // @[FPU.scala:668:35]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:141:24]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_valid = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:135:21, :141:24]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:135:21, :142:26]
reg [9:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:142:26]
wire [9:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:135:21, :142:26]
reg [4:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:142:26]
wire [4:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:135:21, :142:26]
reg [25:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:142:26]
wire [25:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:141:24]
wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_valid = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [48:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:142:26]
wire [48:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:141:24]
wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_valid = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:142:26]
wire [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26]
reg roundingMode_stage0_pipe_v; // @[Valid.scala:141:24]
wire roundingMode_stage0_pipe_out_valid = roundingMode_stage0_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [2:0] roundingMode_stage0_pipe_b; // @[Valid.scala:142:26]
assign roundingMode_stage0_pipe_out_bits = roundingMode_stage0_pipe_b; // @[Valid.scala:135:21, :142:26]
assign roundingMode_stage0 = roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21]
reg detectTininess_stage0_pipe_v; // @[Valid.scala:141:24]
wire detectTininess_stage0_pipe_out_valid = detectTininess_stage0_pipe_v; // @[Valid.scala:135:21, :141:24]
reg valid_stage0_pipe_v; // @[Valid.scala:141:24]
assign valid_stage0_pipe_out_valid = valid_stage0_pipe_v; // @[Valid.scala:135:21, :141:24]
assign valid_stage0 = valid_stage0_pipe_out_valid; // @[Valid.scala:135:21]
reg roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_invalidExc_pipe_out_valid = roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:135:21, :141:24]
reg roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_invalidExc_pipe_out_bits = roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_in_pipe_out_valid = roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:135:21, :141:24]
reg roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_isNaN = roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_isInf = roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_isZero = roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_sign = roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:135:21, :142:26]
reg [9:0] roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:142:26]
wire [9:0] roundRawFNToRecFN_io_in_pipe_out_bits_sExp = roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:135:21, :142:26]
reg [26:0] roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:142:26]
wire [26:0] roundRawFNToRecFN_io_in_pipe_out_bits_sig = roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_roundingMode_pipe_out_valid = roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:142:26]
wire [2:0] roundRawFNToRecFN_io_roundingMode_pipe_out_bits = roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_detectTininess_pipe_out_valid = roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:135:21, :141:24]
reg roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_detectTininess_pipe_out_bits = roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:135:21, :142:26]
reg io_validout_pipe_v; // @[Valid.scala:141:24]
assign io_validout_pipe_out_valid = io_validout_pipe_v; // @[Valid.scala:135:21, :141:24]
assign io_validout_0 = io_validout_pipe_out_valid; // @[Valid.scala:135:21]
always @(posedge clock) begin // @[FPU.scala:633:7]
if (reset) begin // @[FPU.scala:633:7]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= 1'h0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= 1'h0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundingMode_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24]
detectTininess_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24]
valid_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_invalidExc_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_in_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_detectTininess_pipe_v <= 1'h0; // @[Valid.scala:141:24]
io_validout_pipe_v <= 1'h0; // @[Valid.scala:141:24]
end
else begin // @[FPU.scala:633:7]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
roundingMode_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
detectTininess_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
valid_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_invalidExc_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_in_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_roundingMode_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_detectTininess_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
io_validout_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
end
if (io_validin_0) begin // @[FPU.scala:633:7]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= mulAddResult; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26]
roundingMode_stage0_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26]
end
if (valid_stage0) begin // @[FPU.scala:667:28]
roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0; // @[Valid.scala:142:26]
end
roundRawFNToRecFN_io_detectTininess_pipe_b <= valid_stage0 | roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26]
always @(posedge)
MulAddRecFNToRaw_preMul_e8_s24_7 mulAddRecFNToRaw_preMul ( // @[FPU.scala:654:41]
.io_op (io_op_0), // @[FPU.scala:633:7]
.io_a (io_a_0), // @[FPU.scala:633:7]
.io_b (io_b_0), // @[FPU.scala:633:7]
.io_c (io_c_0), // @[FPU.scala:633:7]
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),
.io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),
.io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),
.io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
); // @[FPU.scala:654:41]
MulAddRecFNToRaw_postMul_e8_s24_7 mulAddRecFNToRaw_postMul ( // @[FPU.scala:655:42]
.io_fromPreMul_isSigNaNAny (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny), // @[Valid.scala:135:21]
.io_fromPreMul_isNaNAOrB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB), // @[Valid.scala:135:21]
.io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA), // @[Valid.scala:135:21]
.io_fromPreMul_isZeroA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA), // @[Valid.scala:135:21]
.io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB), // @[Valid.scala:135:21]
.io_fromPreMul_isZeroB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB), // @[Valid.scala:135:21]
.io_fromPreMul_signProd (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd), // @[Valid.scala:135:21]
.io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC), // @[Valid.scala:135:21]
.io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC), // @[Valid.scala:135:21]
.io_fromPreMul_isZeroC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC), // @[Valid.scala:135:21]
.io_fromPreMul_sExpSum (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum), // @[Valid.scala:135:21]
.io_fromPreMul_doSubMags (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags), // @[Valid.scala:135:21]
.io_fromPreMul_CIsDominant (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant), // @[Valid.scala:135:21]
.io_fromPreMul_CDom_CAlignDist (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist), // @[Valid.scala:135:21]
.io_fromPreMul_highAlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC), // @[Valid.scala:135:21]
.io_fromPreMul_bit0AlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC), // @[Valid.scala:135:21]
.io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits), // @[Valid.scala:135:21]
.io_roundingMode (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
); // @[FPU.scala:655:42]
RoundRawFNToRecFN_e8_s24_14 roundRawFNToRecFN ( // @[FPU.scala:682:35]
.io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_out_bits), // @[Valid.scala:135:21]
.io_in_isNaN (roundRawFNToRecFN_io_in_pipe_out_bits_isNaN), // @[Valid.scala:135:21]
.io_in_isInf (roundRawFNToRecFN_io_in_pipe_out_bits_isInf), // @[Valid.scala:135:21]
.io_in_isZero (roundRawFNToRecFN_io_in_pipe_out_bits_isZero), // @[Valid.scala:135:21]
.io_in_sign (roundRawFNToRecFN_io_in_pipe_out_bits_sign), // @[Valid.scala:135:21]
.io_in_sExp (roundRawFNToRecFN_io_in_pipe_out_bits_sExp), // @[Valid.scala:135:21]
.io_in_sig (roundRawFNToRecFN_io_in_pipe_out_bits_sig), // @[Valid.scala:135:21]
.io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21]
.io_detectTininess (roundRawFNToRecFN_io_detectTininess_pipe_out_bits), // @[Valid.scala:135:21]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[FPU.scala:682:35]
assign io_out = io_out_0; // @[FPU.scala:633:7]
assign io_exceptionFlags = io_exceptionFlags_0; // @[FPU.scala:633:7]
assign io_validout = io_validout_0; // @[FPU.scala:633:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_15 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_24
connect io_out_source_valid.clock, clock
connect io_out_source_valid.reset, reset
connect io_out_source_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_15( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_24 io_out_source_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_9 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_265
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_9( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_265 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_6 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node adjustedSig = shl(io.in.sig, 0)
node doShiftSigDown1 = bits(adjustedSig, 26, 26)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _roundMask_T = bits(io.in.sExp, 8, 0)
node _roundMask_T_1 = not(_roundMask_T)
node roundMask_msb = bits(_roundMask_T_1, 8, 8)
node roundMask_lsbs = bits(_roundMask_T_1, 7, 0)
node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7)
node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0)
node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2)
node _roundMask_T_2 = bits(roundMask_shift, 63, 42)
node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0)
node _roundMask_T_4 = shl(UInt<8>(0hff), 8)
node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4)
node _roundMask_T_6 = shr(_roundMask_T_3, 8)
node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5)
node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0)
node _roundMask_T_9 = shl(_roundMask_T_8, 8)
node _roundMask_T_10 = not(_roundMask_T_5)
node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10)
node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11)
node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0)
node _roundMask_T_14 = shl(_roundMask_T_13, 4)
node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14)
node _roundMask_T_16 = shr(_roundMask_T_12, 4)
node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15)
node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0)
node _roundMask_T_19 = shl(_roundMask_T_18, 4)
node _roundMask_T_20 = not(_roundMask_T_15)
node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20)
node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21)
node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0)
node _roundMask_T_24 = shl(_roundMask_T_23, 2)
node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24)
node _roundMask_T_26 = shr(_roundMask_T_22, 2)
node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25)
node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0)
node _roundMask_T_29 = shl(_roundMask_T_28, 2)
node _roundMask_T_30 = not(_roundMask_T_25)
node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30)
node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31)
node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0)
node _roundMask_T_34 = shl(_roundMask_T_33, 1)
node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34)
node _roundMask_T_36 = shr(_roundMask_T_32, 1)
node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35)
node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0)
node _roundMask_T_39 = shl(_roundMask_T_38, 1)
node _roundMask_T_40 = not(_roundMask_T_35)
node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40)
node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41)
node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16)
node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0)
node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0)
node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0)
node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1)
node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47)
node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2)
node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0)
node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1)
node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51)
node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52)
node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4)
node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0)
node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1)
node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56)
node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57)
node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58)
node _roundMask_T_60 = not(_roundMask_T_59)
node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60)
node _roundMask_T_62 = not(_roundMask_T_61)
node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7))
node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3)
node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0)
node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0)
node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0)
node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1)
node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67)
node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2)
node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69)
node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0))
node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71)
node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0))
node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1)
node roundMask = cat(_roundMask_T_74, UInt<2>(0h3))
node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask)
node shiftedRoundMask = shr(_shiftedRoundMask_T, 1)
node _roundPosMask_T = not(shiftedRoundMask)
node roundPosMask = and(_roundPosMask_T, roundMask)
node _roundPosBit_T = and(adjustedSig, roundPosMask)
node roundPosBit = orr(_roundPosBit_T)
node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask)
node anyRoundExtra = orr(_anyRoundExtra_T)
node anyRound = or(roundPosBit, anyRoundExtra)
node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit)
node _roundIncr_T_2 = and(roundMagUp, anyRound)
node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2)
node _roundedSig_T = or(adjustedSig, roundMask)
node _roundedSig_T_1 = shr(_roundedSig_T, 2)
node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1))
node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit)
node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0))
node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4)
node _roundedSig_T_6 = shr(roundMask, 1)
node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0))
node _roundedSig_T_8 = not(_roundedSig_T_7)
node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8)
node _roundedSig_T_10 = not(roundMask)
node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10)
node _roundedSig_T_12 = shr(_roundedSig_T_11, 2)
node _roundedSig_T_13 = and(roundingMode_odd, anyRound)
node _roundedSig_T_14 = shr(roundPosMask, 1)
node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0))
node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15)
node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16)
node _sRoundedExp_T = shr(roundedSig, 24)
node _sRoundedExp_T_1 = cvt(_sRoundedExp_T)
node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1)
node _common_expOut_T = bits(sRoundedExp, 8, 0)
connect common_expOut, _common_expOut_T
node _common_fractOut_T = bits(roundedSig, 23, 1)
node _common_fractOut_T_1 = bits(roundedSig, 22, 0)
node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
node _common_overflow_T = shr(sRoundedExp, 7)
node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3)))
connect common_overflow, _common_overflow_T_1
node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b)))
connect common_totalUnderflow, _common_totalUnderflow_T
node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2)
node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1)
node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1)
node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2)
node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T)
node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0)
node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2)
node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3)
node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit)
node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound)
node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2)
node _roundCarry_T = bits(roundedSig, 25, 25)
node _roundCarry_T_1 = bits(roundedSig, 24, 24)
node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1)
node _common_underflow_T = shr(io.in.sExp, 8)
node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0)))
node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1)
node _common_underflow_T_3 = bits(roundMask, 3, 3)
node _common_underflow_T_4 = bits(roundMask, 2, 2)
node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4)
node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5)
node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1))
node _common_underflow_T_8 = bits(roundMask, 4, 4)
node _common_underflow_T_9 = bits(roundMask, 3, 3)
node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9)
node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0))
node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11)
node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry)
node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit)
node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr)
node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0))
node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16)
node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17)
connect common_underflow, _common_underflow_T_18
node _common_inexact_T = or(common_totalUnderflow, anyRound)
connect common_inexact, _common_inexact_T
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_6( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20]
wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53]
wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38]
wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29]
wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42]
wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25]
wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26]
wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56]
wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22]
wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22]
wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20]
wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20]
wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20]
wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20]
wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20]
wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20]
wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}]
wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}]
wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17]
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56]
wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22]
wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20]
wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20]
wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20]
wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58]
wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24]
wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24]
wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67]
wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49]
wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31]
wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}]
wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46]
wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]
wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]
wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]
wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]
wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_95 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_351
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_95( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_351 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_83 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_83
connect io_out_sink_valid.clock, clock
connect io_out_sink_valid.reset, reset
connect io_out_sink_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_83( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_83 io_out_sink_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_76 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_332
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_76( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_332 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_90 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_90( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_27 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_26 = shr(io.in.a.bits.source, 2)
node _source_ok_T_27 = eq(_source_ok_T_26, UInt<4>(0h8))
node _source_ok_T_28 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28)
node _source_ok_T_30 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30)
node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[9]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_31
connect _source_ok_WIRE[7], _source_ok_T_32
connect _source_ok_WIRE[8], _source_ok_T_33
node _source_ok_T_34 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[2])
node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[3])
node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[4])
node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[5])
node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[6])
node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[7])
node source_ok = or(_source_ok_T_40, _source_ok_WIRE[8])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_72 = shr(io.in.a.bits.source, 2)
node _T_73 = eq(_T_72, UInt<4>(0h8))
node _T_74 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_75 = and(_T_73, _T_74)
node _T_76 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_77 = and(_T_75, _T_76)
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_80 = cvt(_T_79)
node _T_81 = and(_T_80, asSInt(UInt<1>(0h0)))
node _T_82 = asSInt(_T_81)
node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0)))
node _T_84 = or(_T_78, _T_83)
node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_88 = cvt(_T_87)
node _T_89 = and(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = asSInt(_T_89)
node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0)))
node _T_92 = or(_T_86, _T_91)
node _T_93 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_94 = eq(_T_93, UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<1>(0h0)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = or(_T_94, _T_99)
node _T_101 = and(_T_11, _T_24)
node _T_102 = and(_T_101, _T_37)
node _T_103 = and(_T_102, _T_50)
node _T_104 = and(_T_103, _T_63)
node _T_105 = and(_T_104, _T_71)
node _T_106 = and(_T_105, _T_84)
node _T_107 = and(_T_106, _T_92)
node _T_108 = and(_T_107, _T_100)
node _T_109 = asUInt(reset)
node _T_110 = eq(_T_109, UInt<1>(0h0))
when _T_110 :
node _T_111 = eq(_T_108, UInt<1>(0h0))
when _T_111 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_108, UInt<1>(0h1), "") : assert_1
node _T_112 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_112 :
node _T_113 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_114 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_115 = and(_T_113, _T_114)
node _T_116 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_117 = shr(io.in.a.bits.source, 2)
node _T_118 = eq(_T_117, UInt<1>(0h0))
node _T_119 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_120 = and(_T_118, _T_119)
node _T_121 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_122 = and(_T_120, _T_121)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_123 = shr(io.in.a.bits.source, 2)
node _T_124 = eq(_T_123, UInt<1>(0h1))
node _T_125 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_126 = and(_T_124, _T_125)
node _T_127 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_128 = and(_T_126, _T_127)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_129 = shr(io.in.a.bits.source, 2)
node _T_130 = eq(_T_129, UInt<2>(0h2))
node _T_131 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_132 = and(_T_130, _T_131)
node _T_133 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_134 = and(_T_132, _T_133)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_135 = shr(io.in.a.bits.source, 2)
node _T_136 = eq(_T_135, UInt<2>(0h3))
node _T_137 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_138 = and(_T_136, _T_137)
node _T_139 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_142 = shr(io.in.a.bits.source, 2)
node _T_143 = eq(_T_142, UInt<4>(0h8))
node _T_144 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_145 = and(_T_143, _T_144)
node _T_146 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_150 = or(_T_116, _T_122)
node _T_151 = or(_T_150, _T_128)
node _T_152 = or(_T_151, _T_134)
node _T_153 = or(_T_152, _T_140)
node _T_154 = or(_T_153, _T_141)
node _T_155 = or(_T_154, _T_147)
node _T_156 = or(_T_155, _T_148)
node _T_157 = or(_T_156, _T_149)
node _T_158 = and(_T_115, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_161 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_162 = cvt(_T_161)
node _T_163 = and(_T_162, asSInt(UInt<18>(0h2f000)))
node _T_164 = asSInt(_T_163)
node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0)))
node _T_166 = and(_T_160, _T_165)
node _T_167 = or(UInt<1>(0h0), _T_166)
node _T_168 = and(_T_159, _T_167)
node _T_169 = asUInt(reset)
node _T_170 = eq(_T_169, UInt<1>(0h0))
when _T_170 :
node _T_171 = eq(_T_168, UInt<1>(0h0))
when _T_171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_168, UInt<1>(0h1), "") : assert_2
node _T_172 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_173 = shr(io.in.a.bits.source, 2)
node _T_174 = eq(_T_173, UInt<1>(0h0))
node _T_175 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_176 = and(_T_174, _T_175)
node _T_177 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_178 = and(_T_176, _T_177)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_179 = shr(io.in.a.bits.source, 2)
node _T_180 = eq(_T_179, UInt<1>(0h1))
node _T_181 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_182 = and(_T_180, _T_181)
node _T_183 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_184 = and(_T_182, _T_183)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_185 = shr(io.in.a.bits.source, 2)
node _T_186 = eq(_T_185, UInt<2>(0h2))
node _T_187 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_188 = and(_T_186, _T_187)
node _T_189 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_190 = and(_T_188, _T_189)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_191 = shr(io.in.a.bits.source, 2)
node _T_192 = eq(_T_191, UInt<2>(0h3))
node _T_193 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_194 = and(_T_192, _T_193)
node _T_195 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_196 = and(_T_194, _T_195)
node _T_197 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_198 = shr(io.in.a.bits.source, 2)
node _T_199 = eq(_T_198, UInt<4>(0h8))
node _T_200 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_201 = and(_T_199, _T_200)
node _T_202 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_205 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[9]
connect _WIRE[0], _T_172
connect _WIRE[1], _T_178
connect _WIRE[2], _T_184
connect _WIRE[3], _T_190
connect _WIRE[4], _T_196
connect _WIRE[5], _T_197
connect _WIRE[6], _T_203
connect _WIRE[7], _T_204
connect _WIRE[8], _T_205
node _T_206 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_207 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_208 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_209 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_210 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_211 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_212 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_213 = mux(_WIRE[6], _T_206, UInt<1>(0h0))
node _T_214 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_215 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_216 = or(_T_207, _T_208)
node _T_217 = or(_T_216, _T_209)
node _T_218 = or(_T_217, _T_210)
node _T_219 = or(_T_218, _T_211)
node _T_220 = or(_T_219, _T_212)
node _T_221 = or(_T_220, _T_213)
node _T_222 = or(_T_221, _T_214)
node _T_223 = or(_T_222, _T_215)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_223
node _T_224 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_225 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_226 = and(_T_224, _T_225)
node _T_227 = or(UInt<1>(0h0), _T_226)
node _T_228 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_229 = cvt(_T_228)
node _T_230 = and(_T_229, asSInt(UInt<18>(0h2f000)))
node _T_231 = asSInt(_T_230)
node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0)))
node _T_233 = and(_T_227, _T_232)
node _T_234 = or(UInt<1>(0h0), _T_233)
node _T_235 = and(_WIRE_1, _T_234)
node _T_236 = asUInt(reset)
node _T_237 = eq(_T_236, UInt<1>(0h0))
when _T_237 :
node _T_238 = eq(_T_235, UInt<1>(0h0))
when _T_238 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_235, UInt<1>(0h1), "") : assert_3
node _T_239 = asUInt(reset)
node _T_240 = eq(_T_239, UInt<1>(0h0))
when _T_240 :
node _T_241 = eq(source_ok, UInt<1>(0h0))
when _T_241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_242 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_243 = asUInt(reset)
node _T_244 = eq(_T_243, UInt<1>(0h0))
when _T_244 :
node _T_245 = eq(_T_242, UInt<1>(0h0))
when _T_245 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_242, UInt<1>(0h1), "") : assert_5
node _T_246 = asUInt(reset)
node _T_247 = eq(_T_246, UInt<1>(0h0))
when _T_247 :
node _T_248 = eq(is_aligned, UInt<1>(0h0))
when _T_248 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_249 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_250 = asUInt(reset)
node _T_251 = eq(_T_250, UInt<1>(0h0))
when _T_251 :
node _T_252 = eq(_T_249, UInt<1>(0h0))
when _T_252 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_249, UInt<1>(0h1), "") : assert_7
node _T_253 = not(io.in.a.bits.mask)
node _T_254 = eq(_T_253, UInt<1>(0h0))
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_254, UInt<1>(0h1), "") : assert_8
node _T_258 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_259 = asUInt(reset)
node _T_260 = eq(_T_259, UInt<1>(0h0))
when _T_260 :
node _T_261 = eq(_T_258, UInt<1>(0h0))
when _T_261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_258, UInt<1>(0h1), "") : assert_9
node _T_262 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_262 :
node _T_263 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_264 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_265 = and(_T_263, _T_264)
node _T_266 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_267 = shr(io.in.a.bits.source, 2)
node _T_268 = eq(_T_267, UInt<1>(0h0))
node _T_269 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_270 = and(_T_268, _T_269)
node _T_271 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_272 = and(_T_270, _T_271)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_273 = shr(io.in.a.bits.source, 2)
node _T_274 = eq(_T_273, UInt<1>(0h1))
node _T_275 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_276 = and(_T_274, _T_275)
node _T_277 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_278 = and(_T_276, _T_277)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_279 = shr(io.in.a.bits.source, 2)
node _T_280 = eq(_T_279, UInt<2>(0h2))
node _T_281 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_282 = and(_T_280, _T_281)
node _T_283 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_284 = and(_T_282, _T_283)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_285 = shr(io.in.a.bits.source, 2)
node _T_286 = eq(_T_285, UInt<2>(0h3))
node _T_287 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_288 = and(_T_286, _T_287)
node _T_289 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_292 = shr(io.in.a.bits.source, 2)
node _T_293 = eq(_T_292, UInt<4>(0h8))
node _T_294 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_295 = and(_T_293, _T_294)
node _T_296 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_297 = and(_T_295, _T_296)
node _T_298 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_299 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_300 = or(_T_266, _T_272)
node _T_301 = or(_T_300, _T_278)
node _T_302 = or(_T_301, _T_284)
node _T_303 = or(_T_302, _T_290)
node _T_304 = or(_T_303, _T_291)
node _T_305 = or(_T_304, _T_297)
node _T_306 = or(_T_305, _T_298)
node _T_307 = or(_T_306, _T_299)
node _T_308 = and(_T_265, _T_307)
node _T_309 = or(UInt<1>(0h0), _T_308)
node _T_310 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_311 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_312 = cvt(_T_311)
node _T_313 = and(_T_312, asSInt(UInt<18>(0h2f000)))
node _T_314 = asSInt(_T_313)
node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0)))
node _T_316 = and(_T_310, _T_315)
node _T_317 = or(UInt<1>(0h0), _T_316)
node _T_318 = and(_T_309, _T_317)
node _T_319 = asUInt(reset)
node _T_320 = eq(_T_319, UInt<1>(0h0))
when _T_320 :
node _T_321 = eq(_T_318, UInt<1>(0h0))
when _T_321 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_318, UInt<1>(0h1), "") : assert_10
node _T_322 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_323 = shr(io.in.a.bits.source, 2)
node _T_324 = eq(_T_323, UInt<1>(0h0))
node _T_325 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_326 = and(_T_324, _T_325)
node _T_327 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_328 = and(_T_326, _T_327)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_329 = shr(io.in.a.bits.source, 2)
node _T_330 = eq(_T_329, UInt<1>(0h1))
node _T_331 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_332 = and(_T_330, _T_331)
node _T_333 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_335 = shr(io.in.a.bits.source, 2)
node _T_336 = eq(_T_335, UInt<2>(0h2))
node _T_337 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_338 = and(_T_336, _T_337)
node _T_339 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_340 = and(_T_338, _T_339)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_341 = shr(io.in.a.bits.source, 2)
node _T_342 = eq(_T_341, UInt<2>(0h3))
node _T_343 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_344 = and(_T_342, _T_343)
node _T_345 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_346 = and(_T_344, _T_345)
node _T_347 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_348 = shr(io.in.a.bits.source, 2)
node _T_349 = eq(_T_348, UInt<4>(0h8))
node _T_350 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_351 = and(_T_349, _T_350)
node _T_352 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_353 = and(_T_351, _T_352)
node _T_354 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_355 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[9]
connect _WIRE_2[0], _T_322
connect _WIRE_2[1], _T_328
connect _WIRE_2[2], _T_334
connect _WIRE_2[3], _T_340
connect _WIRE_2[4], _T_346
connect _WIRE_2[5], _T_347
connect _WIRE_2[6], _T_353
connect _WIRE_2[7], _T_354
connect _WIRE_2[8], _T_355
node _T_356 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_357 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_358 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_359 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_360 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_361 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_362 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_363 = mux(_WIRE_2[6], _T_356, UInt<1>(0h0))
node _T_364 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_365 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_366 = or(_T_357, _T_358)
node _T_367 = or(_T_366, _T_359)
node _T_368 = or(_T_367, _T_360)
node _T_369 = or(_T_368, _T_361)
node _T_370 = or(_T_369, _T_362)
node _T_371 = or(_T_370, _T_363)
node _T_372 = or(_T_371, _T_364)
node _T_373 = or(_T_372, _T_365)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_373
node _T_374 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_375 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_376 = and(_T_374, _T_375)
node _T_377 = or(UInt<1>(0h0), _T_376)
node _T_378 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_379 = cvt(_T_378)
node _T_380 = and(_T_379, asSInt(UInt<18>(0h2f000)))
node _T_381 = asSInt(_T_380)
node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0)))
node _T_383 = and(_T_377, _T_382)
node _T_384 = or(UInt<1>(0h0), _T_383)
node _T_385 = and(_WIRE_3, _T_384)
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_385, UInt<1>(0h1), "") : assert_11
node _T_389 = asUInt(reset)
node _T_390 = eq(_T_389, UInt<1>(0h0))
when _T_390 :
node _T_391 = eq(source_ok, UInt<1>(0h0))
when _T_391 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_392 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_393 = asUInt(reset)
node _T_394 = eq(_T_393, UInt<1>(0h0))
when _T_394 :
node _T_395 = eq(_T_392, UInt<1>(0h0))
when _T_395 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_392, UInt<1>(0h1), "") : assert_13
node _T_396 = asUInt(reset)
node _T_397 = eq(_T_396, UInt<1>(0h0))
when _T_397 :
node _T_398 = eq(is_aligned, UInt<1>(0h0))
when _T_398 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_399 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_400 = asUInt(reset)
node _T_401 = eq(_T_400, UInt<1>(0h0))
when _T_401 :
node _T_402 = eq(_T_399, UInt<1>(0h0))
when _T_402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_399, UInt<1>(0h1), "") : assert_15
node _T_403 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_404 = asUInt(reset)
node _T_405 = eq(_T_404, UInt<1>(0h0))
when _T_405 :
node _T_406 = eq(_T_403, UInt<1>(0h0))
when _T_406 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_403, UInt<1>(0h1), "") : assert_16
node _T_407 = not(io.in.a.bits.mask)
node _T_408 = eq(_T_407, UInt<1>(0h0))
node _T_409 = asUInt(reset)
node _T_410 = eq(_T_409, UInt<1>(0h0))
when _T_410 :
node _T_411 = eq(_T_408, UInt<1>(0h0))
when _T_411 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_408, UInt<1>(0h1), "") : assert_17
node _T_412 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_413 = asUInt(reset)
node _T_414 = eq(_T_413, UInt<1>(0h0))
when _T_414 :
node _T_415 = eq(_T_412, UInt<1>(0h0))
when _T_415 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_412, UInt<1>(0h1), "") : assert_18
node _T_416 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_416 :
node _T_417 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_418 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_419 = and(_T_417, _T_418)
node _T_420 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_421 = shr(io.in.a.bits.source, 2)
node _T_422 = eq(_T_421, UInt<1>(0h0))
node _T_423 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_424 = and(_T_422, _T_423)
node _T_425 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_426 = and(_T_424, _T_425)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_427 = shr(io.in.a.bits.source, 2)
node _T_428 = eq(_T_427, UInt<1>(0h1))
node _T_429 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_430 = and(_T_428, _T_429)
node _T_431 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_432 = and(_T_430, _T_431)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_433 = shr(io.in.a.bits.source, 2)
node _T_434 = eq(_T_433, UInt<2>(0h2))
node _T_435 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_436 = and(_T_434, _T_435)
node _T_437 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_438 = and(_T_436, _T_437)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_439 = shr(io.in.a.bits.source, 2)
node _T_440 = eq(_T_439, UInt<2>(0h3))
node _T_441 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_442 = and(_T_440, _T_441)
node _T_443 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_446 = shr(io.in.a.bits.source, 2)
node _T_447 = eq(_T_446, UInt<4>(0h8))
node _T_448 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_449 = and(_T_447, _T_448)
node _T_450 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_453 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_454 = or(_T_420, _T_426)
node _T_455 = or(_T_454, _T_432)
node _T_456 = or(_T_455, _T_438)
node _T_457 = or(_T_456, _T_444)
node _T_458 = or(_T_457, _T_445)
node _T_459 = or(_T_458, _T_451)
node _T_460 = or(_T_459, _T_452)
node _T_461 = or(_T_460, _T_453)
node _T_462 = and(_T_419, _T_461)
node _T_463 = or(UInt<1>(0h0), _T_462)
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_463, UInt<1>(0h1), "") : assert_19
node _T_467 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_468 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_469 = and(_T_467, _T_468)
node _T_470 = or(UInt<1>(0h0), _T_469)
node _T_471 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_472 = cvt(_T_471)
node _T_473 = and(_T_472, asSInt(UInt<18>(0h2f000)))
node _T_474 = asSInt(_T_473)
node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0)))
node _T_476 = and(_T_470, _T_475)
node _T_477 = or(UInt<1>(0h0), _T_476)
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_477, UInt<1>(0h1), "") : assert_20
node _T_481 = asUInt(reset)
node _T_482 = eq(_T_481, UInt<1>(0h0))
when _T_482 :
node _T_483 = eq(source_ok, UInt<1>(0h0))
when _T_483 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_484 = asUInt(reset)
node _T_485 = eq(_T_484, UInt<1>(0h0))
when _T_485 :
node _T_486 = eq(is_aligned, UInt<1>(0h0))
when _T_486 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_487 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_488 = asUInt(reset)
node _T_489 = eq(_T_488, UInt<1>(0h0))
when _T_489 :
node _T_490 = eq(_T_487, UInt<1>(0h0))
when _T_490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_487, UInt<1>(0h1), "") : assert_23
node _T_491 = eq(io.in.a.bits.mask, mask)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_491, UInt<1>(0h1), "") : assert_24
node _T_495 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_495, UInt<1>(0h1), "") : assert_25
node _T_499 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_499 :
node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_501 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_502 = and(_T_500, _T_501)
node _T_503 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_504 = shr(io.in.a.bits.source, 2)
node _T_505 = eq(_T_504, UInt<1>(0h0))
node _T_506 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_507 = and(_T_505, _T_506)
node _T_508 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_509 = and(_T_507, _T_508)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_510 = shr(io.in.a.bits.source, 2)
node _T_511 = eq(_T_510, UInt<1>(0h1))
node _T_512 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_513 = and(_T_511, _T_512)
node _T_514 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_515 = and(_T_513, _T_514)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_516 = shr(io.in.a.bits.source, 2)
node _T_517 = eq(_T_516, UInt<2>(0h2))
node _T_518 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_519 = and(_T_517, _T_518)
node _T_520 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_522 = shr(io.in.a.bits.source, 2)
node _T_523 = eq(_T_522, UInt<2>(0h3))
node _T_524 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_525 = and(_T_523, _T_524)
node _T_526 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_527 = and(_T_525, _T_526)
node _T_528 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_529 = shr(io.in.a.bits.source, 2)
node _T_530 = eq(_T_529, UInt<4>(0h8))
node _T_531 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_532 = and(_T_530, _T_531)
node _T_533 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_534 = and(_T_532, _T_533)
node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_536 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_537 = or(_T_503, _T_509)
node _T_538 = or(_T_537, _T_515)
node _T_539 = or(_T_538, _T_521)
node _T_540 = or(_T_539, _T_527)
node _T_541 = or(_T_540, _T_528)
node _T_542 = or(_T_541, _T_534)
node _T_543 = or(_T_542, _T_535)
node _T_544 = or(_T_543, _T_536)
node _T_545 = and(_T_502, _T_544)
node _T_546 = or(UInt<1>(0h0), _T_545)
node _T_547 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_548 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_549 = and(_T_547, _T_548)
node _T_550 = or(UInt<1>(0h0), _T_549)
node _T_551 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_552 = cvt(_T_551)
node _T_553 = and(_T_552, asSInt(UInt<18>(0h2f000)))
node _T_554 = asSInt(_T_553)
node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0)))
node _T_556 = and(_T_550, _T_555)
node _T_557 = or(UInt<1>(0h0), _T_556)
node _T_558 = and(_T_546, _T_557)
node _T_559 = asUInt(reset)
node _T_560 = eq(_T_559, UInt<1>(0h0))
when _T_560 :
node _T_561 = eq(_T_558, UInt<1>(0h0))
when _T_561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_558, UInt<1>(0h1), "") : assert_26
node _T_562 = asUInt(reset)
node _T_563 = eq(_T_562, UInt<1>(0h0))
when _T_563 :
node _T_564 = eq(source_ok, UInt<1>(0h0))
when _T_564 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_565 = asUInt(reset)
node _T_566 = eq(_T_565, UInt<1>(0h0))
when _T_566 :
node _T_567 = eq(is_aligned, UInt<1>(0h0))
when _T_567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_568 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_568, UInt<1>(0h1), "") : assert_29
node _T_572 = eq(io.in.a.bits.mask, mask)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_572, UInt<1>(0h1), "") : assert_30
node _T_576 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_576 :
node _T_577 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_578 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_579 = and(_T_577, _T_578)
node _T_580 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_581 = shr(io.in.a.bits.source, 2)
node _T_582 = eq(_T_581, UInt<1>(0h0))
node _T_583 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_584 = and(_T_582, _T_583)
node _T_585 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_586 = and(_T_584, _T_585)
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_587 = shr(io.in.a.bits.source, 2)
node _T_588 = eq(_T_587, UInt<1>(0h1))
node _T_589 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_590 = and(_T_588, _T_589)
node _T_591 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_592 = and(_T_590, _T_591)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_593 = shr(io.in.a.bits.source, 2)
node _T_594 = eq(_T_593, UInt<2>(0h2))
node _T_595 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_596 = and(_T_594, _T_595)
node _T_597 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_598 = and(_T_596, _T_597)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_599 = shr(io.in.a.bits.source, 2)
node _T_600 = eq(_T_599, UInt<2>(0h3))
node _T_601 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_602 = and(_T_600, _T_601)
node _T_603 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_604 = and(_T_602, _T_603)
node _T_605 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_606 = shr(io.in.a.bits.source, 2)
node _T_607 = eq(_T_606, UInt<4>(0h8))
node _T_608 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_609 = and(_T_607, _T_608)
node _T_610 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_611 = and(_T_609, _T_610)
node _T_612 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_613 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_614 = or(_T_580, _T_586)
node _T_615 = or(_T_614, _T_592)
node _T_616 = or(_T_615, _T_598)
node _T_617 = or(_T_616, _T_604)
node _T_618 = or(_T_617, _T_605)
node _T_619 = or(_T_618, _T_611)
node _T_620 = or(_T_619, _T_612)
node _T_621 = or(_T_620, _T_613)
node _T_622 = and(_T_579, _T_621)
node _T_623 = or(UInt<1>(0h0), _T_622)
node _T_624 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_625 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_626 = and(_T_624, _T_625)
node _T_627 = or(UInt<1>(0h0), _T_626)
node _T_628 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_629 = cvt(_T_628)
node _T_630 = and(_T_629, asSInt(UInt<18>(0h2f000)))
node _T_631 = asSInt(_T_630)
node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0)))
node _T_633 = and(_T_627, _T_632)
node _T_634 = or(UInt<1>(0h0), _T_633)
node _T_635 = and(_T_623, _T_634)
node _T_636 = asUInt(reset)
node _T_637 = eq(_T_636, UInt<1>(0h0))
when _T_637 :
node _T_638 = eq(_T_635, UInt<1>(0h0))
when _T_638 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_635, UInt<1>(0h1), "") : assert_31
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(source_ok, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_642 = asUInt(reset)
node _T_643 = eq(_T_642, UInt<1>(0h0))
when _T_643 :
node _T_644 = eq(is_aligned, UInt<1>(0h0))
when _T_644 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_645 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_646 = asUInt(reset)
node _T_647 = eq(_T_646, UInt<1>(0h0))
when _T_647 :
node _T_648 = eq(_T_645, UInt<1>(0h0))
when _T_648 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_645, UInt<1>(0h1), "") : assert_34
node _T_649 = not(mask)
node _T_650 = and(io.in.a.bits.mask, _T_649)
node _T_651 = eq(_T_650, UInt<1>(0h0))
node _T_652 = asUInt(reset)
node _T_653 = eq(_T_652, UInt<1>(0h0))
when _T_653 :
node _T_654 = eq(_T_651, UInt<1>(0h0))
when _T_654 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_651, UInt<1>(0h1), "") : assert_35
node _T_655 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_655 :
node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_657 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_658 = and(_T_656, _T_657)
node _T_659 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_660 = shr(io.in.a.bits.source, 2)
node _T_661 = eq(_T_660, UInt<1>(0h0))
node _T_662 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_663 = and(_T_661, _T_662)
node _T_664 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_665 = and(_T_663, _T_664)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_666 = shr(io.in.a.bits.source, 2)
node _T_667 = eq(_T_666, UInt<1>(0h1))
node _T_668 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_669 = and(_T_667, _T_668)
node _T_670 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_671 = and(_T_669, _T_670)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_672 = shr(io.in.a.bits.source, 2)
node _T_673 = eq(_T_672, UInt<2>(0h2))
node _T_674 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_675 = and(_T_673, _T_674)
node _T_676 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_677 = and(_T_675, _T_676)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_678 = shr(io.in.a.bits.source, 2)
node _T_679 = eq(_T_678, UInt<2>(0h3))
node _T_680 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_681 = and(_T_679, _T_680)
node _T_682 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_683 = and(_T_681, _T_682)
node _T_684 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_685 = shr(io.in.a.bits.source, 2)
node _T_686 = eq(_T_685, UInt<4>(0h8))
node _T_687 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_688 = and(_T_686, _T_687)
node _T_689 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_690 = and(_T_688, _T_689)
node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_692 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_693 = or(_T_659, _T_665)
node _T_694 = or(_T_693, _T_671)
node _T_695 = or(_T_694, _T_677)
node _T_696 = or(_T_695, _T_683)
node _T_697 = or(_T_696, _T_684)
node _T_698 = or(_T_697, _T_690)
node _T_699 = or(_T_698, _T_691)
node _T_700 = or(_T_699, _T_692)
node _T_701 = and(_T_658, _T_700)
node _T_702 = or(UInt<1>(0h0), _T_701)
node _T_703 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_704 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_705 = cvt(_T_704)
node _T_706 = and(_T_705, asSInt(UInt<18>(0h2f000)))
node _T_707 = asSInt(_T_706)
node _T_708 = eq(_T_707, asSInt(UInt<1>(0h0)))
node _T_709 = and(_T_703, _T_708)
node _T_710 = or(UInt<1>(0h0), _T_709)
node _T_711 = and(_T_702, _T_710)
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(_T_711, UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_711, UInt<1>(0h1), "") : assert_36
node _T_715 = asUInt(reset)
node _T_716 = eq(_T_715, UInt<1>(0h0))
when _T_716 :
node _T_717 = eq(source_ok, UInt<1>(0h0))
when _T_717 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_718 = asUInt(reset)
node _T_719 = eq(_T_718, UInt<1>(0h0))
when _T_719 :
node _T_720 = eq(is_aligned, UInt<1>(0h0))
when _T_720 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_721 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_722 = asUInt(reset)
node _T_723 = eq(_T_722, UInt<1>(0h0))
when _T_723 :
node _T_724 = eq(_T_721, UInt<1>(0h0))
when _T_724 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_721, UInt<1>(0h1), "") : assert_39
node _T_725 = eq(io.in.a.bits.mask, mask)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_725, UInt<1>(0h1), "") : assert_40
node _T_729 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_729 :
node _T_730 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_731 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_732 = and(_T_730, _T_731)
node _T_733 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_734 = shr(io.in.a.bits.source, 2)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_737 = and(_T_735, _T_736)
node _T_738 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_739 = and(_T_737, _T_738)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0)
node _T_740 = shr(io.in.a.bits.source, 2)
node _T_741 = eq(_T_740, UInt<1>(0h1))
node _T_742 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_743 = and(_T_741, _T_742)
node _T_744 = leq(uncommonBits_46, UInt<2>(0h3))
node _T_745 = and(_T_743, _T_744)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0)
node _T_746 = shr(io.in.a.bits.source, 2)
node _T_747 = eq(_T_746, UInt<2>(0h2))
node _T_748 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_749 = and(_T_747, _T_748)
node _T_750 = leq(uncommonBits_47, UInt<2>(0h3))
node _T_751 = and(_T_749, _T_750)
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_752 = shr(io.in.a.bits.source, 2)
node _T_753 = eq(_T_752, UInt<2>(0h3))
node _T_754 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_755 = and(_T_753, _T_754)
node _T_756 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_757 = and(_T_755, _T_756)
node _T_758 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_759 = shr(io.in.a.bits.source, 2)
node _T_760 = eq(_T_759, UInt<4>(0h8))
node _T_761 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_762 = and(_T_760, _T_761)
node _T_763 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_764 = and(_T_762, _T_763)
node _T_765 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_766 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_767 = or(_T_733, _T_739)
node _T_768 = or(_T_767, _T_745)
node _T_769 = or(_T_768, _T_751)
node _T_770 = or(_T_769, _T_757)
node _T_771 = or(_T_770, _T_758)
node _T_772 = or(_T_771, _T_764)
node _T_773 = or(_T_772, _T_765)
node _T_774 = or(_T_773, _T_766)
node _T_775 = and(_T_732, _T_774)
node _T_776 = or(UInt<1>(0h0), _T_775)
node _T_777 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_778 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_779 = cvt(_T_778)
node _T_780 = and(_T_779, asSInt(UInt<18>(0h2f000)))
node _T_781 = asSInt(_T_780)
node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0)))
node _T_783 = and(_T_777, _T_782)
node _T_784 = or(UInt<1>(0h0), _T_783)
node _T_785 = and(_T_776, _T_784)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_785, UInt<1>(0h1), "") : assert_41
node _T_789 = asUInt(reset)
node _T_790 = eq(_T_789, UInt<1>(0h0))
when _T_790 :
node _T_791 = eq(source_ok, UInt<1>(0h0))
when _T_791 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_792 = asUInt(reset)
node _T_793 = eq(_T_792, UInt<1>(0h0))
when _T_793 :
node _T_794 = eq(is_aligned, UInt<1>(0h0))
when _T_794 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_795 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_796 = asUInt(reset)
node _T_797 = eq(_T_796, UInt<1>(0h0))
when _T_797 :
node _T_798 = eq(_T_795, UInt<1>(0h0))
when _T_798 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_795, UInt<1>(0h1), "") : assert_44
node _T_799 = eq(io.in.a.bits.mask, mask)
node _T_800 = asUInt(reset)
node _T_801 = eq(_T_800, UInt<1>(0h0))
when _T_801 :
node _T_802 = eq(_T_799, UInt<1>(0h0))
when _T_802 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_799, UInt<1>(0h1), "") : assert_45
node _T_803 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_803 :
node _T_804 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_805 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_806 = and(_T_804, _T_805)
node _T_807 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_808 = shr(io.in.a.bits.source, 2)
node _T_809 = eq(_T_808, UInt<1>(0h0))
node _T_810 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_811 = and(_T_809, _T_810)
node _T_812 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_813 = and(_T_811, _T_812)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_814 = shr(io.in.a.bits.source, 2)
node _T_815 = eq(_T_814, UInt<1>(0h1))
node _T_816 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_817 = and(_T_815, _T_816)
node _T_818 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_819 = and(_T_817, _T_818)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0)
node _T_820 = shr(io.in.a.bits.source, 2)
node _T_821 = eq(_T_820, UInt<2>(0h2))
node _T_822 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_823 = and(_T_821, _T_822)
node _T_824 = leq(uncommonBits_52, UInt<2>(0h3))
node _T_825 = and(_T_823, _T_824)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0)
node _T_826 = shr(io.in.a.bits.source, 2)
node _T_827 = eq(_T_826, UInt<2>(0h3))
node _T_828 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_829 = and(_T_827, _T_828)
node _T_830 = leq(uncommonBits_53, UInt<2>(0h3))
node _T_831 = and(_T_829, _T_830)
node _T_832 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0)
node _T_833 = shr(io.in.a.bits.source, 2)
node _T_834 = eq(_T_833, UInt<4>(0h8))
node _T_835 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_836 = and(_T_834, _T_835)
node _T_837 = leq(uncommonBits_54, UInt<2>(0h3))
node _T_838 = and(_T_836, _T_837)
node _T_839 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_840 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_841 = or(_T_807, _T_813)
node _T_842 = or(_T_841, _T_819)
node _T_843 = or(_T_842, _T_825)
node _T_844 = or(_T_843, _T_831)
node _T_845 = or(_T_844, _T_832)
node _T_846 = or(_T_845, _T_838)
node _T_847 = or(_T_846, _T_839)
node _T_848 = or(_T_847, _T_840)
node _T_849 = and(_T_806, _T_848)
node _T_850 = or(UInt<1>(0h0), _T_849)
node _T_851 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_852 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_853 = cvt(_T_852)
node _T_854 = and(_T_853, asSInt(UInt<18>(0h2f000)))
node _T_855 = asSInt(_T_854)
node _T_856 = eq(_T_855, asSInt(UInt<1>(0h0)))
node _T_857 = and(_T_851, _T_856)
node _T_858 = or(UInt<1>(0h0), _T_857)
node _T_859 = and(_T_850, _T_858)
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(_T_859, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_859, UInt<1>(0h1), "") : assert_46
node _T_863 = asUInt(reset)
node _T_864 = eq(_T_863, UInt<1>(0h0))
when _T_864 :
node _T_865 = eq(source_ok, UInt<1>(0h0))
when _T_865 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_866 = asUInt(reset)
node _T_867 = eq(_T_866, UInt<1>(0h0))
when _T_867 :
node _T_868 = eq(is_aligned, UInt<1>(0h0))
when _T_868 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_869 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_869, UInt<1>(0h1), "") : assert_49
node _T_873 = eq(io.in.a.bits.mask, mask)
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(_T_873, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_873, UInt<1>(0h1), "") : assert_50
node _T_877 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_878 = asUInt(reset)
node _T_879 = eq(_T_878, UInt<1>(0h0))
when _T_879 :
node _T_880 = eq(_T_877, UInt<1>(0h0))
when _T_880 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_877, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_881 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_882 = asUInt(reset)
node _T_883 = eq(_T_882, UInt<1>(0h0))
when _T_883 :
node _T_884 = eq(_T_881, UInt<1>(0h0))
when _T_884 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_881, UInt<1>(0h1), "") : assert_52
node _source_ok_T_41 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_42 = shr(io.in.d.bits.source, 2)
node _source_ok_T_43 = eq(_source_ok_T_42, UInt<1>(0h0))
node _source_ok_T_44 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44)
node _source_ok_T_46 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_48 = shr(io.in.d.bits.source, 2)
node _source_ok_T_49 = eq(_source_ok_T_48, UInt<1>(0h1))
node _source_ok_T_50 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50)
node _source_ok_T_52 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_53 = and(_source_ok_T_51, _source_ok_T_52)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_54 = shr(io.in.d.bits.source, 2)
node _source_ok_T_55 = eq(_source_ok_T_54, UInt<2>(0h2))
node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56)
node _source_ok_T_58 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_60 = shr(io.in.d.bits.source, 2)
node _source_ok_T_61 = eq(_source_ok_T_60, UInt<2>(0h3))
node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62)
node _source_ok_T_64 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64)
node _source_ok_T_66 = eq(io.in.d.bits.source, UInt<6>(0h28))
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_67 = shr(io.in.d.bits.source, 2)
node _source_ok_T_68 = eq(_source_ok_T_67, UInt<4>(0h8))
node _source_ok_T_69 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69)
node _source_ok_T_71 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71)
node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<6>(0h24))
node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[9]
connect _source_ok_WIRE_1[0], _source_ok_T_41
connect _source_ok_WIRE_1[1], _source_ok_T_47
connect _source_ok_WIRE_1[2], _source_ok_T_53
connect _source_ok_WIRE_1[3], _source_ok_T_59
connect _source_ok_WIRE_1[4], _source_ok_T_65
connect _source_ok_WIRE_1[5], _source_ok_T_66
connect _source_ok_WIRE_1[6], _source_ok_T_72
connect _source_ok_WIRE_1[7], _source_ok_T_73
connect _source_ok_WIRE_1[8], _source_ok_T_74
node _source_ok_T_75 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[2])
node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[3])
node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[4])
node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[5])
node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[6])
node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[7])
node source_ok_1 = or(_source_ok_T_81, _source_ok_WIRE_1[8])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_885 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_885 :
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(source_ok_1, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_889 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_890 = asUInt(reset)
node _T_891 = eq(_T_890, UInt<1>(0h0))
when _T_891 :
node _T_892 = eq(_T_889, UInt<1>(0h0))
when _T_892 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_889, UInt<1>(0h1), "") : assert_54
node _T_893 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_894 = asUInt(reset)
node _T_895 = eq(_T_894, UInt<1>(0h0))
when _T_895 :
node _T_896 = eq(_T_893, UInt<1>(0h0))
when _T_896 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_893, UInt<1>(0h1), "") : assert_55
node _T_897 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_898 = asUInt(reset)
node _T_899 = eq(_T_898, UInt<1>(0h0))
when _T_899 :
node _T_900 = eq(_T_897, UInt<1>(0h0))
when _T_900 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_897, UInt<1>(0h1), "") : assert_56
node _T_901 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_902 = asUInt(reset)
node _T_903 = eq(_T_902, UInt<1>(0h0))
when _T_903 :
node _T_904 = eq(_T_901, UInt<1>(0h0))
when _T_904 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_901, UInt<1>(0h1), "") : assert_57
node _T_905 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_905 :
node _T_906 = asUInt(reset)
node _T_907 = eq(_T_906, UInt<1>(0h0))
when _T_907 :
node _T_908 = eq(source_ok_1, UInt<1>(0h0))
when _T_908 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_909 = asUInt(reset)
node _T_910 = eq(_T_909, UInt<1>(0h0))
when _T_910 :
node _T_911 = eq(sink_ok, UInt<1>(0h0))
when _T_911 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_912 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_913 = asUInt(reset)
node _T_914 = eq(_T_913, UInt<1>(0h0))
when _T_914 :
node _T_915 = eq(_T_912, UInt<1>(0h0))
when _T_915 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_912, UInt<1>(0h1), "") : assert_60
node _T_916 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_917 = asUInt(reset)
node _T_918 = eq(_T_917, UInt<1>(0h0))
when _T_918 :
node _T_919 = eq(_T_916, UInt<1>(0h0))
when _T_919 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_916, UInt<1>(0h1), "") : assert_61
node _T_920 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_921 = asUInt(reset)
node _T_922 = eq(_T_921, UInt<1>(0h0))
when _T_922 :
node _T_923 = eq(_T_920, UInt<1>(0h0))
when _T_923 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_920, UInt<1>(0h1), "") : assert_62
node _T_924 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_925 = asUInt(reset)
node _T_926 = eq(_T_925, UInt<1>(0h0))
when _T_926 :
node _T_927 = eq(_T_924, UInt<1>(0h0))
when _T_927 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_924, UInt<1>(0h1), "") : assert_63
node _T_928 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_929 = or(UInt<1>(0h0), _T_928)
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_929, UInt<1>(0h1), "") : assert_64
node _T_933 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_933 :
node _T_934 = asUInt(reset)
node _T_935 = eq(_T_934, UInt<1>(0h0))
when _T_935 :
node _T_936 = eq(source_ok_1, UInt<1>(0h0))
when _T_936 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_937 = asUInt(reset)
node _T_938 = eq(_T_937, UInt<1>(0h0))
when _T_938 :
node _T_939 = eq(sink_ok, UInt<1>(0h0))
when _T_939 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_940 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_941 = asUInt(reset)
node _T_942 = eq(_T_941, UInt<1>(0h0))
when _T_942 :
node _T_943 = eq(_T_940, UInt<1>(0h0))
when _T_943 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_940, UInt<1>(0h1), "") : assert_67
node _T_944 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_945 = asUInt(reset)
node _T_946 = eq(_T_945, UInt<1>(0h0))
when _T_946 :
node _T_947 = eq(_T_944, UInt<1>(0h0))
when _T_947 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_944, UInt<1>(0h1), "") : assert_68
node _T_948 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_949 = asUInt(reset)
node _T_950 = eq(_T_949, UInt<1>(0h0))
when _T_950 :
node _T_951 = eq(_T_948, UInt<1>(0h0))
when _T_951 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_948, UInt<1>(0h1), "") : assert_69
node _T_952 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_953 = or(_T_952, io.in.d.bits.corrupt)
node _T_954 = asUInt(reset)
node _T_955 = eq(_T_954, UInt<1>(0h0))
when _T_955 :
node _T_956 = eq(_T_953, UInt<1>(0h0))
when _T_956 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_953, UInt<1>(0h1), "") : assert_70
node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_958 = or(UInt<1>(0h0), _T_957)
node _T_959 = asUInt(reset)
node _T_960 = eq(_T_959, UInt<1>(0h0))
when _T_960 :
node _T_961 = eq(_T_958, UInt<1>(0h0))
when _T_961 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_958, UInt<1>(0h1), "") : assert_71
node _T_962 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_962 :
node _T_963 = asUInt(reset)
node _T_964 = eq(_T_963, UInt<1>(0h0))
when _T_964 :
node _T_965 = eq(source_ok_1, UInt<1>(0h0))
when _T_965 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_966 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_967 = asUInt(reset)
node _T_968 = eq(_T_967, UInt<1>(0h0))
when _T_968 :
node _T_969 = eq(_T_966, UInt<1>(0h0))
when _T_969 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_966, UInt<1>(0h1), "") : assert_73
node _T_970 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_971 = asUInt(reset)
node _T_972 = eq(_T_971, UInt<1>(0h0))
when _T_972 :
node _T_973 = eq(_T_970, UInt<1>(0h0))
when _T_973 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_970, UInt<1>(0h1), "") : assert_74
node _T_974 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_975 = or(UInt<1>(0h0), _T_974)
node _T_976 = asUInt(reset)
node _T_977 = eq(_T_976, UInt<1>(0h0))
when _T_977 :
node _T_978 = eq(_T_975, UInt<1>(0h0))
when _T_978 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_975, UInt<1>(0h1), "") : assert_75
node _T_979 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_979 :
node _T_980 = asUInt(reset)
node _T_981 = eq(_T_980, UInt<1>(0h0))
when _T_981 :
node _T_982 = eq(source_ok_1, UInt<1>(0h0))
when _T_982 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_983 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_984 = asUInt(reset)
node _T_985 = eq(_T_984, UInt<1>(0h0))
when _T_985 :
node _T_986 = eq(_T_983, UInt<1>(0h0))
when _T_986 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_983, UInt<1>(0h1), "") : assert_77
node _T_987 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_988 = or(_T_987, io.in.d.bits.corrupt)
node _T_989 = asUInt(reset)
node _T_990 = eq(_T_989, UInt<1>(0h0))
when _T_990 :
node _T_991 = eq(_T_988, UInt<1>(0h0))
when _T_991 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_988, UInt<1>(0h1), "") : assert_78
node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_993 = or(UInt<1>(0h0), _T_992)
node _T_994 = asUInt(reset)
node _T_995 = eq(_T_994, UInt<1>(0h0))
when _T_995 :
node _T_996 = eq(_T_993, UInt<1>(0h0))
when _T_996 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_993, UInt<1>(0h1), "") : assert_79
node _T_997 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_997 :
node _T_998 = asUInt(reset)
node _T_999 = eq(_T_998, UInt<1>(0h0))
when _T_999 :
node _T_1000 = eq(source_ok_1, UInt<1>(0h0))
when _T_1000 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1001 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1002 = asUInt(reset)
node _T_1003 = eq(_T_1002, UInt<1>(0h0))
when _T_1003 :
node _T_1004 = eq(_T_1001, UInt<1>(0h0))
when _T_1004 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1001, UInt<1>(0h1), "") : assert_81
node _T_1005 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1006 = asUInt(reset)
node _T_1007 = eq(_T_1006, UInt<1>(0h0))
when _T_1007 :
node _T_1008 = eq(_T_1005, UInt<1>(0h0))
when _T_1008 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1005, UInt<1>(0h1), "") : assert_82
node _T_1009 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1010 = or(UInt<1>(0h0), _T_1009)
node _T_1011 = asUInt(reset)
node _T_1012 = eq(_T_1011, UInt<1>(0h0))
when _T_1012 :
node _T_1013 = eq(_T_1010, UInt<1>(0h0))
when _T_1013 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1010, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<21>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1014 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1015 = asUInt(reset)
node _T_1016 = eq(_T_1015, UInt<1>(0h0))
when _T_1016 :
node _T_1017 = eq(_T_1014, UInt<1>(0h0))
when _T_1017 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1014, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<21>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1018 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1019 = asUInt(reset)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
node _T_1021 = eq(_T_1018, UInt<1>(0h0))
when _T_1021 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1018, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1022 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1023 = asUInt(reset)
node _T_1024 = eq(_T_1023, UInt<1>(0h0))
when _T_1024 :
node _T_1025 = eq(_T_1022, UInt<1>(0h0))
when _T_1025 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1022, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1026 = eq(a_first, UInt<1>(0h0))
node _T_1027 = and(io.in.a.valid, _T_1026)
when _T_1027 :
node _T_1028 = eq(io.in.a.bits.opcode, opcode)
node _T_1029 = asUInt(reset)
node _T_1030 = eq(_T_1029, UInt<1>(0h0))
when _T_1030 :
node _T_1031 = eq(_T_1028, UInt<1>(0h0))
when _T_1031 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1028, UInt<1>(0h1), "") : assert_87
node _T_1032 = eq(io.in.a.bits.param, param)
node _T_1033 = asUInt(reset)
node _T_1034 = eq(_T_1033, UInt<1>(0h0))
when _T_1034 :
node _T_1035 = eq(_T_1032, UInt<1>(0h0))
when _T_1035 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1032, UInt<1>(0h1), "") : assert_88
node _T_1036 = eq(io.in.a.bits.size, size)
node _T_1037 = asUInt(reset)
node _T_1038 = eq(_T_1037, UInt<1>(0h0))
when _T_1038 :
node _T_1039 = eq(_T_1036, UInt<1>(0h0))
when _T_1039 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1036, UInt<1>(0h1), "") : assert_89
node _T_1040 = eq(io.in.a.bits.source, source)
node _T_1041 = asUInt(reset)
node _T_1042 = eq(_T_1041, UInt<1>(0h0))
when _T_1042 :
node _T_1043 = eq(_T_1040, UInt<1>(0h0))
when _T_1043 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1040, UInt<1>(0h1), "") : assert_90
node _T_1044 = eq(io.in.a.bits.address, address)
node _T_1045 = asUInt(reset)
node _T_1046 = eq(_T_1045, UInt<1>(0h0))
when _T_1046 :
node _T_1047 = eq(_T_1044, UInt<1>(0h0))
when _T_1047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1044, UInt<1>(0h1), "") : assert_91
node _T_1048 = and(io.in.a.ready, io.in.a.valid)
node _T_1049 = and(_T_1048, a_first)
when _T_1049 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1050 = eq(d_first, UInt<1>(0h0))
node _T_1051 = and(io.in.d.valid, _T_1050)
when _T_1051 :
node _T_1052 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1053 = asUInt(reset)
node _T_1054 = eq(_T_1053, UInt<1>(0h0))
when _T_1054 :
node _T_1055 = eq(_T_1052, UInt<1>(0h0))
when _T_1055 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1052, UInt<1>(0h1), "") : assert_92
node _T_1056 = eq(io.in.d.bits.param, param_1)
node _T_1057 = asUInt(reset)
node _T_1058 = eq(_T_1057, UInt<1>(0h0))
when _T_1058 :
node _T_1059 = eq(_T_1056, UInt<1>(0h0))
when _T_1059 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1056, UInt<1>(0h1), "") : assert_93
node _T_1060 = eq(io.in.d.bits.size, size_1)
node _T_1061 = asUInt(reset)
node _T_1062 = eq(_T_1061, UInt<1>(0h0))
when _T_1062 :
node _T_1063 = eq(_T_1060, UInt<1>(0h0))
when _T_1063 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1060, UInt<1>(0h1), "") : assert_94
node _T_1064 = eq(io.in.d.bits.source, source_1)
node _T_1065 = asUInt(reset)
node _T_1066 = eq(_T_1065, UInt<1>(0h0))
when _T_1066 :
node _T_1067 = eq(_T_1064, UInt<1>(0h0))
when _T_1067 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1064, UInt<1>(0h1), "") : assert_95
node _T_1068 = eq(io.in.d.bits.sink, sink)
node _T_1069 = asUInt(reset)
node _T_1070 = eq(_T_1069, UInt<1>(0h0))
when _T_1070 :
node _T_1071 = eq(_T_1068, UInt<1>(0h0))
when _T_1071 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1068, UInt<1>(0h1), "") : assert_96
node _T_1072 = eq(io.in.d.bits.denied, denied)
node _T_1073 = asUInt(reset)
node _T_1074 = eq(_T_1073, UInt<1>(0h0))
when _T_1074 :
node _T_1075 = eq(_T_1072, UInt<1>(0h0))
when _T_1075 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1072, UInt<1>(0h1), "") : assert_97
node _T_1076 = and(io.in.d.ready, io.in.d.valid)
node _T_1077 = and(_T_1076, d_first)
when _T_1077 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1078 = and(io.in.a.valid, a_first_1)
node _T_1079 = and(_T_1078, UInt<1>(0h1))
when _T_1079 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1080 = and(io.in.a.ready, io.in.a.valid)
node _T_1081 = and(_T_1080, a_first_1)
node _T_1082 = and(_T_1081, UInt<1>(0h1))
when _T_1082 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1083 = dshr(inflight, io.in.a.bits.source)
node _T_1084 = bits(_T_1083, 0, 0)
node _T_1085 = eq(_T_1084, UInt<1>(0h0))
node _T_1086 = asUInt(reset)
node _T_1087 = eq(_T_1086, UInt<1>(0h0))
when _T_1087 :
node _T_1088 = eq(_T_1085, UInt<1>(0h0))
when _T_1088 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1085, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1089 = and(io.in.d.valid, d_first_1)
node _T_1090 = and(_T_1089, UInt<1>(0h1))
node _T_1091 = eq(d_release_ack, UInt<1>(0h0))
node _T_1092 = and(_T_1090, _T_1091)
when _T_1092 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1093 = and(io.in.d.ready, io.in.d.valid)
node _T_1094 = and(_T_1093, d_first_1)
node _T_1095 = and(_T_1094, UInt<1>(0h1))
node _T_1096 = eq(d_release_ack, UInt<1>(0h0))
node _T_1097 = and(_T_1095, _T_1096)
when _T_1097 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1098 = and(io.in.d.valid, d_first_1)
node _T_1099 = and(_T_1098, UInt<1>(0h1))
node _T_1100 = eq(d_release_ack, UInt<1>(0h0))
node _T_1101 = and(_T_1099, _T_1100)
when _T_1101 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1102 = dshr(inflight, io.in.d.bits.source)
node _T_1103 = bits(_T_1102, 0, 0)
node _T_1104 = or(_T_1103, same_cycle_resp)
node _T_1105 = asUInt(reset)
node _T_1106 = eq(_T_1105, UInt<1>(0h0))
when _T_1106 :
node _T_1107 = eq(_T_1104, UInt<1>(0h0))
when _T_1107 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1104, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1108 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1109 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1110 = or(_T_1108, _T_1109)
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(_T_1110, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1110, UInt<1>(0h1), "") : assert_100
node _T_1114 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(_T_1114, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1114, UInt<1>(0h1), "") : assert_101
else :
node _T_1118 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1119 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1120 = or(_T_1118, _T_1119)
node _T_1121 = asUInt(reset)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = eq(_T_1120, UInt<1>(0h0))
when _T_1123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1120, UInt<1>(0h1), "") : assert_102
node _T_1124 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1125 = asUInt(reset)
node _T_1126 = eq(_T_1125, UInt<1>(0h0))
when _T_1126 :
node _T_1127 = eq(_T_1124, UInt<1>(0h0))
when _T_1127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1124, UInt<1>(0h1), "") : assert_103
node _T_1128 = and(io.in.d.valid, d_first_1)
node _T_1129 = and(_T_1128, a_first_1)
node _T_1130 = and(_T_1129, io.in.a.valid)
node _T_1131 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1132 = and(_T_1130, _T_1131)
node _T_1133 = eq(d_release_ack, UInt<1>(0h0))
node _T_1134 = and(_T_1132, _T_1133)
when _T_1134 :
node _T_1135 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1136 = or(_T_1135, io.in.a.ready)
node _T_1137 = asUInt(reset)
node _T_1138 = eq(_T_1137, UInt<1>(0h0))
when _T_1138 :
node _T_1139 = eq(_T_1136, UInt<1>(0h0))
when _T_1139 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1136, UInt<1>(0h1), "") : assert_104
node _T_1140 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1141 = orr(a_set_wo_ready)
node _T_1142 = eq(_T_1141, UInt<1>(0h0))
node _T_1143 = or(_T_1140, _T_1142)
node _T_1144 = asUInt(reset)
node _T_1145 = eq(_T_1144, UInt<1>(0h0))
when _T_1145 :
node _T_1146 = eq(_T_1143, UInt<1>(0h0))
when _T_1146 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1143, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_54
node _T_1147 = orr(inflight)
node _T_1148 = eq(_T_1147, UInt<1>(0h0))
node _T_1149 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1150 = or(_T_1148, _T_1149)
node _T_1151 = lt(watchdog, plusarg_reader.out)
node _T_1152 = or(_T_1150, _T_1151)
node _T_1153 = asUInt(reset)
node _T_1154 = eq(_T_1153, UInt<1>(0h0))
when _T_1154 :
node _T_1155 = eq(_T_1152, UInt<1>(0h0))
when _T_1155 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1152, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1156 = and(io.in.a.ready, io.in.a.valid)
node _T_1157 = and(io.in.d.ready, io.in.d.valid)
node _T_1158 = or(_T_1156, _T_1157)
when _T_1158 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<21>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<21>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1159 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<21>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1160 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1161 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1162 = and(_T_1160, _T_1161)
node _T_1163 = and(_T_1159, _T_1162)
when _T_1163 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<21>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1164 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1165 = and(_T_1164, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<21>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1166 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1167 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1168 = and(_T_1166, _T_1167)
node _T_1169 = and(_T_1165, _T_1168)
when _T_1169 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<21>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1170 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1171 = bits(_T_1170, 0, 0)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
node _T_1173 = asUInt(reset)
node _T_1174 = eq(_T_1173, UInt<1>(0h0))
when _T_1174 :
node _T_1175 = eq(_T_1172, UInt<1>(0h0))
when _T_1175 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1172, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1176 = and(io.in.d.valid, d_first_2)
node _T_1177 = and(_T_1176, UInt<1>(0h1))
node _T_1178 = and(_T_1177, d_release_ack_1)
when _T_1178 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1179 = and(io.in.d.ready, io.in.d.valid)
node _T_1180 = and(_T_1179, d_first_2)
node _T_1181 = and(_T_1180, UInt<1>(0h1))
node _T_1182 = and(_T_1181, d_release_ack_1)
when _T_1182 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1183 = and(io.in.d.valid, d_first_2)
node _T_1184 = and(_T_1183, UInt<1>(0h1))
node _T_1185 = and(_T_1184, d_release_ack_1)
when _T_1185 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1186 = dshr(inflight_1, io.in.d.bits.source)
node _T_1187 = bits(_T_1186, 0, 0)
node _T_1188 = or(_T_1187, same_cycle_resp_1)
node _T_1189 = asUInt(reset)
node _T_1190 = eq(_T_1189, UInt<1>(0h0))
when _T_1190 :
node _T_1191 = eq(_T_1188, UInt<1>(0h0))
when _T_1191 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1188, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<21>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1192 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1193 = asUInt(reset)
node _T_1194 = eq(_T_1193, UInt<1>(0h0))
when _T_1194 :
node _T_1195 = eq(_T_1192, UInt<1>(0h0))
when _T_1195 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1192, UInt<1>(0h1), "") : assert_109
else :
node _T_1196 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1197 = asUInt(reset)
node _T_1198 = eq(_T_1197, UInt<1>(0h0))
when _T_1198 :
node _T_1199 = eq(_T_1196, UInt<1>(0h0))
when _T_1199 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1196, UInt<1>(0h1), "") : assert_110
node _T_1200 = and(io.in.d.valid, d_first_2)
node _T_1201 = and(_T_1200, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<21>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1202 = and(_T_1201, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<21>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1203 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1204 = and(_T_1202, _T_1203)
node _T_1205 = and(_T_1204, d_release_ack_1)
node _T_1206 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1207 = and(_T_1205, _T_1206)
when _T_1207 :
node _T_1208 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<21>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1209 = or(_T_1208, _WIRE_27.ready)
node _T_1210 = asUInt(reset)
node _T_1211 = eq(_T_1210, UInt<1>(0h0))
when _T_1211 :
node _T_1212 = eq(_T_1209, UInt<1>(0h0))
when _T_1212 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1209, UInt<1>(0h1), "") : assert_111
node _T_1213 = orr(c_set_wo_ready)
when _T_1213 :
node _T_1214 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1215 = asUInt(reset)
node _T_1216 = eq(_T_1215, UInt<1>(0h0))
when _T_1216 :
node _T_1217 = eq(_T_1214, UInt<1>(0h0))
when _T_1217 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1214, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_55
node _T_1218 = orr(inflight_1)
node _T_1219 = eq(_T_1218, UInt<1>(0h0))
node _T_1220 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1221 = or(_T_1219, _T_1220)
node _T_1222 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1223 = or(_T_1221, _T_1222)
node _T_1224 = asUInt(reset)
node _T_1225 = eq(_T_1224, UInt<1>(0h0))
when _T_1225 :
node _T_1226 = eq(_T_1223, UInt<1>(0h0))
when _T_1226 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1223, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<21>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1227 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1228 = and(io.in.d.ready, io.in.d.valid)
node _T_1229 = or(_T_1227, _T_1228)
when _T_1229 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_27( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_28 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_30 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_26 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_27 = _source_ok_T_26 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_29 = _source_ok_T_27; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_31 = _source_ok_T_29; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31]
wire _source_ok_T_34 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_40 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_67 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31]
wire _source_ok_T_66 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_66; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_68 = _source_ok_T_67 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31]
wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31]
wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire _source_ok_T_75 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_81 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1156 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1156; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1156; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
wire _T_1229 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1229; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1229; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1229; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1082 = _T_1156 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1082 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1082 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1082 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1082 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1082 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1128 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1128 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1097 = _T_1229 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1097 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1097 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1097 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1200 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1200 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1182 = _T_1229 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1182 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1182 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1182 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLCacheCork :
input clock : Clock
input reset : Reset
output auto : { flip in_7 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip in_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip in_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip in_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip in_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip in_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out_7 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeIn.e.bits.sink
invalidate nodeIn.e.valid
invalidate nodeIn.e.ready
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.c.bits.corrupt
invalidate nodeIn.c.bits.data
invalidate nodeIn.c.bits.address
invalidate nodeIn.c.bits.source
invalidate nodeIn.c.bits.size
invalidate nodeIn.c.bits.param
invalidate nodeIn.c.bits.opcode
invalidate nodeIn.c.valid
invalidate nodeIn.c.ready
invalidate nodeIn.b.bits.corrupt
invalidate nodeIn.b.bits.data
invalidate nodeIn.b.bits.mask
invalidate nodeIn.b.bits.address
invalidate nodeIn.b.bits.source
invalidate nodeIn.b.bits.size
invalidate nodeIn.b.bits.param
invalidate nodeIn.b.bits.opcode
invalidate nodeIn.b.valid
invalidate nodeIn.b.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
wire nodeIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeIn_1.e.bits.sink
invalidate nodeIn_1.e.valid
invalidate nodeIn_1.e.ready
invalidate nodeIn_1.d.bits.corrupt
invalidate nodeIn_1.d.bits.data
invalidate nodeIn_1.d.bits.denied
invalidate nodeIn_1.d.bits.sink
invalidate nodeIn_1.d.bits.source
invalidate nodeIn_1.d.bits.size
invalidate nodeIn_1.d.bits.param
invalidate nodeIn_1.d.bits.opcode
invalidate nodeIn_1.d.valid
invalidate nodeIn_1.d.ready
invalidate nodeIn_1.c.bits.corrupt
invalidate nodeIn_1.c.bits.data
invalidate nodeIn_1.c.bits.address
invalidate nodeIn_1.c.bits.source
invalidate nodeIn_1.c.bits.size
invalidate nodeIn_1.c.bits.param
invalidate nodeIn_1.c.bits.opcode
invalidate nodeIn_1.c.valid
invalidate nodeIn_1.c.ready
invalidate nodeIn_1.b.bits.corrupt
invalidate nodeIn_1.b.bits.data
invalidate nodeIn_1.b.bits.mask
invalidate nodeIn_1.b.bits.address
invalidate nodeIn_1.b.bits.source
invalidate nodeIn_1.b.bits.size
invalidate nodeIn_1.b.bits.param
invalidate nodeIn_1.b.bits.opcode
invalidate nodeIn_1.b.valid
invalidate nodeIn_1.b.ready
invalidate nodeIn_1.a.bits.corrupt
invalidate nodeIn_1.a.bits.data
invalidate nodeIn_1.a.bits.mask
invalidate nodeIn_1.a.bits.address
invalidate nodeIn_1.a.bits.source
invalidate nodeIn_1.a.bits.size
invalidate nodeIn_1.a.bits.param
invalidate nodeIn_1.a.bits.opcode
invalidate nodeIn_1.a.valid
invalidate nodeIn_1.a.ready
wire nodeIn_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeIn_2.e.bits.sink
invalidate nodeIn_2.e.valid
invalidate nodeIn_2.e.ready
invalidate nodeIn_2.d.bits.corrupt
invalidate nodeIn_2.d.bits.data
invalidate nodeIn_2.d.bits.denied
invalidate nodeIn_2.d.bits.sink
invalidate nodeIn_2.d.bits.source
invalidate nodeIn_2.d.bits.size
invalidate nodeIn_2.d.bits.param
invalidate nodeIn_2.d.bits.opcode
invalidate nodeIn_2.d.valid
invalidate nodeIn_2.d.ready
invalidate nodeIn_2.c.bits.corrupt
invalidate nodeIn_2.c.bits.data
invalidate nodeIn_2.c.bits.address
invalidate nodeIn_2.c.bits.source
invalidate nodeIn_2.c.bits.size
invalidate nodeIn_2.c.bits.param
invalidate nodeIn_2.c.bits.opcode
invalidate nodeIn_2.c.valid
invalidate nodeIn_2.c.ready
invalidate nodeIn_2.b.bits.corrupt
invalidate nodeIn_2.b.bits.data
invalidate nodeIn_2.b.bits.mask
invalidate nodeIn_2.b.bits.address
invalidate nodeIn_2.b.bits.source
invalidate nodeIn_2.b.bits.size
invalidate nodeIn_2.b.bits.param
invalidate nodeIn_2.b.bits.opcode
invalidate nodeIn_2.b.valid
invalidate nodeIn_2.b.ready
invalidate nodeIn_2.a.bits.corrupt
invalidate nodeIn_2.a.bits.data
invalidate nodeIn_2.a.bits.mask
invalidate nodeIn_2.a.bits.address
invalidate nodeIn_2.a.bits.source
invalidate nodeIn_2.a.bits.size
invalidate nodeIn_2.a.bits.param
invalidate nodeIn_2.a.bits.opcode
invalidate nodeIn_2.a.valid
invalidate nodeIn_2.a.ready
wire nodeIn_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeIn_3.e.bits.sink
invalidate nodeIn_3.e.valid
invalidate nodeIn_3.e.ready
invalidate nodeIn_3.d.bits.corrupt
invalidate nodeIn_3.d.bits.data
invalidate nodeIn_3.d.bits.denied
invalidate nodeIn_3.d.bits.sink
invalidate nodeIn_3.d.bits.source
invalidate nodeIn_3.d.bits.size
invalidate nodeIn_3.d.bits.param
invalidate nodeIn_3.d.bits.opcode
invalidate nodeIn_3.d.valid
invalidate nodeIn_3.d.ready
invalidate nodeIn_3.c.bits.corrupt
invalidate nodeIn_3.c.bits.data
invalidate nodeIn_3.c.bits.address
invalidate nodeIn_3.c.bits.source
invalidate nodeIn_3.c.bits.size
invalidate nodeIn_3.c.bits.param
invalidate nodeIn_3.c.bits.opcode
invalidate nodeIn_3.c.valid
invalidate nodeIn_3.c.ready
invalidate nodeIn_3.b.bits.corrupt
invalidate nodeIn_3.b.bits.data
invalidate nodeIn_3.b.bits.mask
invalidate nodeIn_3.b.bits.address
invalidate nodeIn_3.b.bits.source
invalidate nodeIn_3.b.bits.size
invalidate nodeIn_3.b.bits.param
invalidate nodeIn_3.b.bits.opcode
invalidate nodeIn_3.b.valid
invalidate nodeIn_3.b.ready
invalidate nodeIn_3.a.bits.corrupt
invalidate nodeIn_3.a.bits.data
invalidate nodeIn_3.a.bits.mask
invalidate nodeIn_3.a.bits.address
invalidate nodeIn_3.a.bits.source
invalidate nodeIn_3.a.bits.size
invalidate nodeIn_3.a.bits.param
invalidate nodeIn_3.a.bits.opcode
invalidate nodeIn_3.a.valid
invalidate nodeIn_3.a.ready
wire nodeIn_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeIn_4.e.bits.sink
invalidate nodeIn_4.e.valid
invalidate nodeIn_4.e.ready
invalidate nodeIn_4.d.bits.corrupt
invalidate nodeIn_4.d.bits.data
invalidate nodeIn_4.d.bits.denied
invalidate nodeIn_4.d.bits.sink
invalidate nodeIn_4.d.bits.source
invalidate nodeIn_4.d.bits.size
invalidate nodeIn_4.d.bits.param
invalidate nodeIn_4.d.bits.opcode
invalidate nodeIn_4.d.valid
invalidate nodeIn_4.d.ready
invalidate nodeIn_4.c.bits.corrupt
invalidate nodeIn_4.c.bits.data
invalidate nodeIn_4.c.bits.address
invalidate nodeIn_4.c.bits.source
invalidate nodeIn_4.c.bits.size
invalidate nodeIn_4.c.bits.param
invalidate nodeIn_4.c.bits.opcode
invalidate nodeIn_4.c.valid
invalidate nodeIn_4.c.ready
invalidate nodeIn_4.b.bits.corrupt
invalidate nodeIn_4.b.bits.data
invalidate nodeIn_4.b.bits.mask
invalidate nodeIn_4.b.bits.address
invalidate nodeIn_4.b.bits.source
invalidate nodeIn_4.b.bits.size
invalidate nodeIn_4.b.bits.param
invalidate nodeIn_4.b.bits.opcode
invalidate nodeIn_4.b.valid
invalidate nodeIn_4.b.ready
invalidate nodeIn_4.a.bits.corrupt
invalidate nodeIn_4.a.bits.data
invalidate nodeIn_4.a.bits.mask
invalidate nodeIn_4.a.bits.address
invalidate nodeIn_4.a.bits.source
invalidate nodeIn_4.a.bits.size
invalidate nodeIn_4.a.bits.param
invalidate nodeIn_4.a.bits.opcode
invalidate nodeIn_4.a.valid
invalidate nodeIn_4.a.ready
wire nodeIn_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeIn_5.e.bits.sink
invalidate nodeIn_5.e.valid
invalidate nodeIn_5.e.ready
invalidate nodeIn_5.d.bits.corrupt
invalidate nodeIn_5.d.bits.data
invalidate nodeIn_5.d.bits.denied
invalidate nodeIn_5.d.bits.sink
invalidate nodeIn_5.d.bits.source
invalidate nodeIn_5.d.bits.size
invalidate nodeIn_5.d.bits.param
invalidate nodeIn_5.d.bits.opcode
invalidate nodeIn_5.d.valid
invalidate nodeIn_5.d.ready
invalidate nodeIn_5.c.bits.corrupt
invalidate nodeIn_5.c.bits.data
invalidate nodeIn_5.c.bits.address
invalidate nodeIn_5.c.bits.source
invalidate nodeIn_5.c.bits.size
invalidate nodeIn_5.c.bits.param
invalidate nodeIn_5.c.bits.opcode
invalidate nodeIn_5.c.valid
invalidate nodeIn_5.c.ready
invalidate nodeIn_5.b.bits.corrupt
invalidate nodeIn_5.b.bits.data
invalidate nodeIn_5.b.bits.mask
invalidate nodeIn_5.b.bits.address
invalidate nodeIn_5.b.bits.source
invalidate nodeIn_5.b.bits.size
invalidate nodeIn_5.b.bits.param
invalidate nodeIn_5.b.bits.opcode
invalidate nodeIn_5.b.valid
invalidate nodeIn_5.b.ready
invalidate nodeIn_5.a.bits.corrupt
invalidate nodeIn_5.a.bits.data
invalidate nodeIn_5.a.bits.mask
invalidate nodeIn_5.a.bits.address
invalidate nodeIn_5.a.bits.source
invalidate nodeIn_5.a.bits.size
invalidate nodeIn_5.a.bits.param
invalidate nodeIn_5.a.bits.opcode
invalidate nodeIn_5.a.valid
invalidate nodeIn_5.a.ready
wire nodeIn_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeIn_6.e.bits.sink
invalidate nodeIn_6.e.valid
invalidate nodeIn_6.e.ready
invalidate nodeIn_6.d.bits.corrupt
invalidate nodeIn_6.d.bits.data
invalidate nodeIn_6.d.bits.denied
invalidate nodeIn_6.d.bits.sink
invalidate nodeIn_6.d.bits.source
invalidate nodeIn_6.d.bits.size
invalidate nodeIn_6.d.bits.param
invalidate nodeIn_6.d.bits.opcode
invalidate nodeIn_6.d.valid
invalidate nodeIn_6.d.ready
invalidate nodeIn_6.c.bits.corrupt
invalidate nodeIn_6.c.bits.data
invalidate nodeIn_6.c.bits.address
invalidate nodeIn_6.c.bits.source
invalidate nodeIn_6.c.bits.size
invalidate nodeIn_6.c.bits.param
invalidate nodeIn_6.c.bits.opcode
invalidate nodeIn_6.c.valid
invalidate nodeIn_6.c.ready
invalidate nodeIn_6.b.bits.corrupt
invalidate nodeIn_6.b.bits.data
invalidate nodeIn_6.b.bits.mask
invalidate nodeIn_6.b.bits.address
invalidate nodeIn_6.b.bits.source
invalidate nodeIn_6.b.bits.size
invalidate nodeIn_6.b.bits.param
invalidate nodeIn_6.b.bits.opcode
invalidate nodeIn_6.b.valid
invalidate nodeIn_6.b.ready
invalidate nodeIn_6.a.bits.corrupt
invalidate nodeIn_6.a.bits.data
invalidate nodeIn_6.a.bits.mask
invalidate nodeIn_6.a.bits.address
invalidate nodeIn_6.a.bits.source
invalidate nodeIn_6.a.bits.size
invalidate nodeIn_6.a.bits.param
invalidate nodeIn_6.a.bits.opcode
invalidate nodeIn_6.a.valid
invalidate nodeIn_6.a.ready
wire nodeIn_7 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeIn_7.e.bits.sink
invalidate nodeIn_7.e.valid
invalidate nodeIn_7.e.ready
invalidate nodeIn_7.d.bits.corrupt
invalidate nodeIn_7.d.bits.data
invalidate nodeIn_7.d.bits.denied
invalidate nodeIn_7.d.bits.sink
invalidate nodeIn_7.d.bits.source
invalidate nodeIn_7.d.bits.size
invalidate nodeIn_7.d.bits.param
invalidate nodeIn_7.d.bits.opcode
invalidate nodeIn_7.d.valid
invalidate nodeIn_7.d.ready
invalidate nodeIn_7.c.bits.corrupt
invalidate nodeIn_7.c.bits.data
invalidate nodeIn_7.c.bits.address
invalidate nodeIn_7.c.bits.source
invalidate nodeIn_7.c.bits.size
invalidate nodeIn_7.c.bits.param
invalidate nodeIn_7.c.bits.opcode
invalidate nodeIn_7.c.valid
invalidate nodeIn_7.c.ready
invalidate nodeIn_7.b.bits.corrupt
invalidate nodeIn_7.b.bits.data
invalidate nodeIn_7.b.bits.mask
invalidate nodeIn_7.b.bits.address
invalidate nodeIn_7.b.bits.source
invalidate nodeIn_7.b.bits.size
invalidate nodeIn_7.b.bits.param
invalidate nodeIn_7.b.bits.opcode
invalidate nodeIn_7.b.valid
invalidate nodeIn_7.b.ready
invalidate nodeIn_7.a.bits.corrupt
invalidate nodeIn_7.a.bits.data
invalidate nodeIn_7.a.bits.mask
invalidate nodeIn_7.a.bits.address
invalidate nodeIn_7.a.bits.source
invalidate nodeIn_7.a.bits.size
invalidate nodeIn_7.a.bits.param
invalidate nodeIn_7.a.bits.opcode
invalidate nodeIn_7.a.valid
invalidate nodeIn_7.a.ready
inst monitor of TLMonitor_66
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink
connect monitor.io.in.e.valid, nodeIn.e.valid
connect monitor.io.in.e.ready, nodeIn.e.ready
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt
connect monitor.io.in.c.bits.data, nodeIn.c.bits.data
connect monitor.io.in.c.bits.address, nodeIn.c.bits.address
connect monitor.io.in.c.bits.source, nodeIn.c.bits.source
connect monitor.io.in.c.bits.size, nodeIn.c.bits.size
connect monitor.io.in.c.bits.param, nodeIn.c.bits.param
connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode
connect monitor.io.in.c.valid, nodeIn.c.valid
connect monitor.io.in.c.ready, nodeIn.c.ready
connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt
connect monitor.io.in.b.bits.data, nodeIn.b.bits.data
connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask
connect monitor.io.in.b.bits.address, nodeIn.b.bits.address
connect monitor.io.in.b.bits.source, nodeIn.b.bits.source
connect monitor.io.in.b.bits.size, nodeIn.b.bits.size
connect monitor.io.in.b.bits.param, nodeIn.b.bits.param
connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode
connect monitor.io.in.b.valid, nodeIn.b.valid
connect monitor.io.in.b.ready, nodeIn.b.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
inst monitor_1 of TLMonitor_67
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.e.bits.sink, nodeIn_1.e.bits.sink
connect monitor_1.io.in.e.valid, nodeIn_1.e.valid
connect monitor_1.io.in.e.ready, nodeIn_1.e.ready
connect monitor_1.io.in.d.bits.corrupt, nodeIn_1.d.bits.corrupt
connect monitor_1.io.in.d.bits.data, nodeIn_1.d.bits.data
connect monitor_1.io.in.d.bits.denied, nodeIn_1.d.bits.denied
connect monitor_1.io.in.d.bits.sink, nodeIn_1.d.bits.sink
connect monitor_1.io.in.d.bits.source, nodeIn_1.d.bits.source
connect monitor_1.io.in.d.bits.size, nodeIn_1.d.bits.size
connect monitor_1.io.in.d.bits.param, nodeIn_1.d.bits.param
connect monitor_1.io.in.d.bits.opcode, nodeIn_1.d.bits.opcode
connect monitor_1.io.in.d.valid, nodeIn_1.d.valid
connect monitor_1.io.in.d.ready, nodeIn_1.d.ready
connect monitor_1.io.in.c.bits.corrupt, nodeIn_1.c.bits.corrupt
connect monitor_1.io.in.c.bits.data, nodeIn_1.c.bits.data
connect monitor_1.io.in.c.bits.address, nodeIn_1.c.bits.address
connect monitor_1.io.in.c.bits.source, nodeIn_1.c.bits.source
connect monitor_1.io.in.c.bits.size, nodeIn_1.c.bits.size
connect monitor_1.io.in.c.bits.param, nodeIn_1.c.bits.param
connect monitor_1.io.in.c.bits.opcode, nodeIn_1.c.bits.opcode
connect monitor_1.io.in.c.valid, nodeIn_1.c.valid
connect monitor_1.io.in.c.ready, nodeIn_1.c.ready
connect monitor_1.io.in.b.bits.corrupt, nodeIn_1.b.bits.corrupt
connect monitor_1.io.in.b.bits.data, nodeIn_1.b.bits.data
connect monitor_1.io.in.b.bits.mask, nodeIn_1.b.bits.mask
connect monitor_1.io.in.b.bits.address, nodeIn_1.b.bits.address
connect monitor_1.io.in.b.bits.source, nodeIn_1.b.bits.source
connect monitor_1.io.in.b.bits.size, nodeIn_1.b.bits.size
connect monitor_1.io.in.b.bits.param, nodeIn_1.b.bits.param
connect monitor_1.io.in.b.bits.opcode, nodeIn_1.b.bits.opcode
connect monitor_1.io.in.b.valid, nodeIn_1.b.valid
connect monitor_1.io.in.b.ready, nodeIn_1.b.ready
connect monitor_1.io.in.a.bits.corrupt, nodeIn_1.a.bits.corrupt
connect monitor_1.io.in.a.bits.data, nodeIn_1.a.bits.data
connect monitor_1.io.in.a.bits.mask, nodeIn_1.a.bits.mask
connect monitor_1.io.in.a.bits.address, nodeIn_1.a.bits.address
connect monitor_1.io.in.a.bits.source, nodeIn_1.a.bits.source
connect monitor_1.io.in.a.bits.size, nodeIn_1.a.bits.size
connect monitor_1.io.in.a.bits.param, nodeIn_1.a.bits.param
connect monitor_1.io.in.a.bits.opcode, nodeIn_1.a.bits.opcode
connect monitor_1.io.in.a.valid, nodeIn_1.a.valid
connect monitor_1.io.in.a.ready, nodeIn_1.a.ready
inst monitor_2 of TLMonitor_68
connect monitor_2.clock, clock
connect monitor_2.reset, reset
connect monitor_2.io.in.e.bits.sink, nodeIn_2.e.bits.sink
connect monitor_2.io.in.e.valid, nodeIn_2.e.valid
connect monitor_2.io.in.e.ready, nodeIn_2.e.ready
connect monitor_2.io.in.d.bits.corrupt, nodeIn_2.d.bits.corrupt
connect monitor_2.io.in.d.bits.data, nodeIn_2.d.bits.data
connect monitor_2.io.in.d.bits.denied, nodeIn_2.d.bits.denied
connect monitor_2.io.in.d.bits.sink, nodeIn_2.d.bits.sink
connect monitor_2.io.in.d.bits.source, nodeIn_2.d.bits.source
connect monitor_2.io.in.d.bits.size, nodeIn_2.d.bits.size
connect monitor_2.io.in.d.bits.param, nodeIn_2.d.bits.param
connect monitor_2.io.in.d.bits.opcode, nodeIn_2.d.bits.opcode
connect monitor_2.io.in.d.valid, nodeIn_2.d.valid
connect monitor_2.io.in.d.ready, nodeIn_2.d.ready
connect monitor_2.io.in.c.bits.corrupt, nodeIn_2.c.bits.corrupt
connect monitor_2.io.in.c.bits.data, nodeIn_2.c.bits.data
connect monitor_2.io.in.c.bits.address, nodeIn_2.c.bits.address
connect monitor_2.io.in.c.bits.source, nodeIn_2.c.bits.source
connect monitor_2.io.in.c.bits.size, nodeIn_2.c.bits.size
connect monitor_2.io.in.c.bits.param, nodeIn_2.c.bits.param
connect monitor_2.io.in.c.bits.opcode, nodeIn_2.c.bits.opcode
connect monitor_2.io.in.c.valid, nodeIn_2.c.valid
connect monitor_2.io.in.c.ready, nodeIn_2.c.ready
connect monitor_2.io.in.b.bits.corrupt, nodeIn_2.b.bits.corrupt
connect monitor_2.io.in.b.bits.data, nodeIn_2.b.bits.data
connect monitor_2.io.in.b.bits.mask, nodeIn_2.b.bits.mask
connect monitor_2.io.in.b.bits.address, nodeIn_2.b.bits.address
connect monitor_2.io.in.b.bits.source, nodeIn_2.b.bits.source
connect monitor_2.io.in.b.bits.size, nodeIn_2.b.bits.size
connect monitor_2.io.in.b.bits.param, nodeIn_2.b.bits.param
connect monitor_2.io.in.b.bits.opcode, nodeIn_2.b.bits.opcode
connect monitor_2.io.in.b.valid, nodeIn_2.b.valid
connect monitor_2.io.in.b.ready, nodeIn_2.b.ready
connect monitor_2.io.in.a.bits.corrupt, nodeIn_2.a.bits.corrupt
connect monitor_2.io.in.a.bits.data, nodeIn_2.a.bits.data
connect monitor_2.io.in.a.bits.mask, nodeIn_2.a.bits.mask
connect monitor_2.io.in.a.bits.address, nodeIn_2.a.bits.address
connect monitor_2.io.in.a.bits.source, nodeIn_2.a.bits.source
connect monitor_2.io.in.a.bits.size, nodeIn_2.a.bits.size
connect monitor_2.io.in.a.bits.param, nodeIn_2.a.bits.param
connect monitor_2.io.in.a.bits.opcode, nodeIn_2.a.bits.opcode
connect monitor_2.io.in.a.valid, nodeIn_2.a.valid
connect monitor_2.io.in.a.ready, nodeIn_2.a.ready
inst monitor_3 of TLMonitor_69
connect monitor_3.clock, clock
connect monitor_3.reset, reset
connect monitor_3.io.in.e.bits.sink, nodeIn_3.e.bits.sink
connect monitor_3.io.in.e.valid, nodeIn_3.e.valid
connect monitor_3.io.in.e.ready, nodeIn_3.e.ready
connect monitor_3.io.in.d.bits.corrupt, nodeIn_3.d.bits.corrupt
connect monitor_3.io.in.d.bits.data, nodeIn_3.d.bits.data
connect monitor_3.io.in.d.bits.denied, nodeIn_3.d.bits.denied
connect monitor_3.io.in.d.bits.sink, nodeIn_3.d.bits.sink
connect monitor_3.io.in.d.bits.source, nodeIn_3.d.bits.source
connect monitor_3.io.in.d.bits.size, nodeIn_3.d.bits.size
connect monitor_3.io.in.d.bits.param, nodeIn_3.d.bits.param
connect monitor_3.io.in.d.bits.opcode, nodeIn_3.d.bits.opcode
connect monitor_3.io.in.d.valid, nodeIn_3.d.valid
connect monitor_3.io.in.d.ready, nodeIn_3.d.ready
connect monitor_3.io.in.c.bits.corrupt, nodeIn_3.c.bits.corrupt
connect monitor_3.io.in.c.bits.data, nodeIn_3.c.bits.data
connect monitor_3.io.in.c.bits.address, nodeIn_3.c.bits.address
connect monitor_3.io.in.c.bits.source, nodeIn_3.c.bits.source
connect monitor_3.io.in.c.bits.size, nodeIn_3.c.bits.size
connect monitor_3.io.in.c.bits.param, nodeIn_3.c.bits.param
connect monitor_3.io.in.c.bits.opcode, nodeIn_3.c.bits.opcode
connect monitor_3.io.in.c.valid, nodeIn_3.c.valid
connect monitor_3.io.in.c.ready, nodeIn_3.c.ready
connect monitor_3.io.in.b.bits.corrupt, nodeIn_3.b.bits.corrupt
connect monitor_3.io.in.b.bits.data, nodeIn_3.b.bits.data
connect monitor_3.io.in.b.bits.mask, nodeIn_3.b.bits.mask
connect monitor_3.io.in.b.bits.address, nodeIn_3.b.bits.address
connect monitor_3.io.in.b.bits.source, nodeIn_3.b.bits.source
connect monitor_3.io.in.b.bits.size, nodeIn_3.b.bits.size
connect monitor_3.io.in.b.bits.param, nodeIn_3.b.bits.param
connect monitor_3.io.in.b.bits.opcode, nodeIn_3.b.bits.opcode
connect monitor_3.io.in.b.valid, nodeIn_3.b.valid
connect monitor_3.io.in.b.ready, nodeIn_3.b.ready
connect monitor_3.io.in.a.bits.corrupt, nodeIn_3.a.bits.corrupt
connect monitor_3.io.in.a.bits.data, nodeIn_3.a.bits.data
connect monitor_3.io.in.a.bits.mask, nodeIn_3.a.bits.mask
connect monitor_3.io.in.a.bits.address, nodeIn_3.a.bits.address
connect monitor_3.io.in.a.bits.source, nodeIn_3.a.bits.source
connect monitor_3.io.in.a.bits.size, nodeIn_3.a.bits.size
connect monitor_3.io.in.a.bits.param, nodeIn_3.a.bits.param
connect monitor_3.io.in.a.bits.opcode, nodeIn_3.a.bits.opcode
connect monitor_3.io.in.a.valid, nodeIn_3.a.valid
connect monitor_3.io.in.a.ready, nodeIn_3.a.ready
inst monitor_4 of TLMonitor_70
connect monitor_4.clock, clock
connect monitor_4.reset, reset
connect monitor_4.io.in.e.bits.sink, nodeIn_4.e.bits.sink
connect monitor_4.io.in.e.valid, nodeIn_4.e.valid
connect monitor_4.io.in.e.ready, nodeIn_4.e.ready
connect monitor_4.io.in.d.bits.corrupt, nodeIn_4.d.bits.corrupt
connect monitor_4.io.in.d.bits.data, nodeIn_4.d.bits.data
connect monitor_4.io.in.d.bits.denied, nodeIn_4.d.bits.denied
connect monitor_4.io.in.d.bits.sink, nodeIn_4.d.bits.sink
connect monitor_4.io.in.d.bits.source, nodeIn_4.d.bits.source
connect monitor_4.io.in.d.bits.size, nodeIn_4.d.bits.size
connect monitor_4.io.in.d.bits.param, nodeIn_4.d.bits.param
connect monitor_4.io.in.d.bits.opcode, nodeIn_4.d.bits.opcode
connect monitor_4.io.in.d.valid, nodeIn_4.d.valid
connect monitor_4.io.in.d.ready, nodeIn_4.d.ready
connect monitor_4.io.in.c.bits.corrupt, nodeIn_4.c.bits.corrupt
connect monitor_4.io.in.c.bits.data, nodeIn_4.c.bits.data
connect monitor_4.io.in.c.bits.address, nodeIn_4.c.bits.address
connect monitor_4.io.in.c.bits.source, nodeIn_4.c.bits.source
connect monitor_4.io.in.c.bits.size, nodeIn_4.c.bits.size
connect monitor_4.io.in.c.bits.param, nodeIn_4.c.bits.param
connect monitor_4.io.in.c.bits.opcode, nodeIn_4.c.bits.opcode
connect monitor_4.io.in.c.valid, nodeIn_4.c.valid
connect monitor_4.io.in.c.ready, nodeIn_4.c.ready
connect monitor_4.io.in.b.bits.corrupt, nodeIn_4.b.bits.corrupt
connect monitor_4.io.in.b.bits.data, nodeIn_4.b.bits.data
connect monitor_4.io.in.b.bits.mask, nodeIn_4.b.bits.mask
connect monitor_4.io.in.b.bits.address, nodeIn_4.b.bits.address
connect monitor_4.io.in.b.bits.source, nodeIn_4.b.bits.source
connect monitor_4.io.in.b.bits.size, nodeIn_4.b.bits.size
connect monitor_4.io.in.b.bits.param, nodeIn_4.b.bits.param
connect monitor_4.io.in.b.bits.opcode, nodeIn_4.b.bits.opcode
connect monitor_4.io.in.b.valid, nodeIn_4.b.valid
connect monitor_4.io.in.b.ready, nodeIn_4.b.ready
connect monitor_4.io.in.a.bits.corrupt, nodeIn_4.a.bits.corrupt
connect monitor_4.io.in.a.bits.data, nodeIn_4.a.bits.data
connect monitor_4.io.in.a.bits.mask, nodeIn_4.a.bits.mask
connect monitor_4.io.in.a.bits.address, nodeIn_4.a.bits.address
connect monitor_4.io.in.a.bits.source, nodeIn_4.a.bits.source
connect monitor_4.io.in.a.bits.size, nodeIn_4.a.bits.size
connect monitor_4.io.in.a.bits.param, nodeIn_4.a.bits.param
connect monitor_4.io.in.a.bits.opcode, nodeIn_4.a.bits.opcode
connect monitor_4.io.in.a.valid, nodeIn_4.a.valid
connect monitor_4.io.in.a.ready, nodeIn_4.a.ready
inst monitor_5 of TLMonitor_71
connect monitor_5.clock, clock
connect monitor_5.reset, reset
connect monitor_5.io.in.e.bits.sink, nodeIn_5.e.bits.sink
connect monitor_5.io.in.e.valid, nodeIn_5.e.valid
connect monitor_5.io.in.e.ready, nodeIn_5.e.ready
connect monitor_5.io.in.d.bits.corrupt, nodeIn_5.d.bits.corrupt
connect monitor_5.io.in.d.bits.data, nodeIn_5.d.bits.data
connect monitor_5.io.in.d.bits.denied, nodeIn_5.d.bits.denied
connect monitor_5.io.in.d.bits.sink, nodeIn_5.d.bits.sink
connect monitor_5.io.in.d.bits.source, nodeIn_5.d.bits.source
connect monitor_5.io.in.d.bits.size, nodeIn_5.d.bits.size
connect monitor_5.io.in.d.bits.param, nodeIn_5.d.bits.param
connect monitor_5.io.in.d.bits.opcode, nodeIn_5.d.bits.opcode
connect monitor_5.io.in.d.valid, nodeIn_5.d.valid
connect monitor_5.io.in.d.ready, nodeIn_5.d.ready
connect monitor_5.io.in.c.bits.corrupt, nodeIn_5.c.bits.corrupt
connect monitor_5.io.in.c.bits.data, nodeIn_5.c.bits.data
connect monitor_5.io.in.c.bits.address, nodeIn_5.c.bits.address
connect monitor_5.io.in.c.bits.source, nodeIn_5.c.bits.source
connect monitor_5.io.in.c.bits.size, nodeIn_5.c.bits.size
connect monitor_5.io.in.c.bits.param, nodeIn_5.c.bits.param
connect monitor_5.io.in.c.bits.opcode, nodeIn_5.c.bits.opcode
connect monitor_5.io.in.c.valid, nodeIn_5.c.valid
connect monitor_5.io.in.c.ready, nodeIn_5.c.ready
connect monitor_5.io.in.b.bits.corrupt, nodeIn_5.b.bits.corrupt
connect monitor_5.io.in.b.bits.data, nodeIn_5.b.bits.data
connect monitor_5.io.in.b.bits.mask, nodeIn_5.b.bits.mask
connect monitor_5.io.in.b.bits.address, nodeIn_5.b.bits.address
connect monitor_5.io.in.b.bits.source, nodeIn_5.b.bits.source
connect monitor_5.io.in.b.bits.size, nodeIn_5.b.bits.size
connect monitor_5.io.in.b.bits.param, nodeIn_5.b.bits.param
connect monitor_5.io.in.b.bits.opcode, nodeIn_5.b.bits.opcode
connect monitor_5.io.in.b.valid, nodeIn_5.b.valid
connect monitor_5.io.in.b.ready, nodeIn_5.b.ready
connect monitor_5.io.in.a.bits.corrupt, nodeIn_5.a.bits.corrupt
connect monitor_5.io.in.a.bits.data, nodeIn_5.a.bits.data
connect monitor_5.io.in.a.bits.mask, nodeIn_5.a.bits.mask
connect monitor_5.io.in.a.bits.address, nodeIn_5.a.bits.address
connect monitor_5.io.in.a.bits.source, nodeIn_5.a.bits.source
connect monitor_5.io.in.a.bits.size, nodeIn_5.a.bits.size
connect monitor_5.io.in.a.bits.param, nodeIn_5.a.bits.param
connect monitor_5.io.in.a.bits.opcode, nodeIn_5.a.bits.opcode
connect monitor_5.io.in.a.valid, nodeIn_5.a.valid
connect monitor_5.io.in.a.ready, nodeIn_5.a.ready
inst monitor_6 of TLMonitor_72
connect monitor_6.clock, clock
connect monitor_6.reset, reset
connect monitor_6.io.in.e.bits.sink, nodeIn_6.e.bits.sink
connect monitor_6.io.in.e.valid, nodeIn_6.e.valid
connect monitor_6.io.in.e.ready, nodeIn_6.e.ready
connect monitor_6.io.in.d.bits.corrupt, nodeIn_6.d.bits.corrupt
connect monitor_6.io.in.d.bits.data, nodeIn_6.d.bits.data
connect monitor_6.io.in.d.bits.denied, nodeIn_6.d.bits.denied
connect monitor_6.io.in.d.bits.sink, nodeIn_6.d.bits.sink
connect monitor_6.io.in.d.bits.source, nodeIn_6.d.bits.source
connect monitor_6.io.in.d.bits.size, nodeIn_6.d.bits.size
connect monitor_6.io.in.d.bits.param, nodeIn_6.d.bits.param
connect monitor_6.io.in.d.bits.opcode, nodeIn_6.d.bits.opcode
connect monitor_6.io.in.d.valid, nodeIn_6.d.valid
connect monitor_6.io.in.d.ready, nodeIn_6.d.ready
connect monitor_6.io.in.c.bits.corrupt, nodeIn_6.c.bits.corrupt
connect monitor_6.io.in.c.bits.data, nodeIn_6.c.bits.data
connect monitor_6.io.in.c.bits.address, nodeIn_6.c.bits.address
connect monitor_6.io.in.c.bits.source, nodeIn_6.c.bits.source
connect monitor_6.io.in.c.bits.size, nodeIn_6.c.bits.size
connect monitor_6.io.in.c.bits.param, nodeIn_6.c.bits.param
connect monitor_6.io.in.c.bits.opcode, nodeIn_6.c.bits.opcode
connect monitor_6.io.in.c.valid, nodeIn_6.c.valid
connect monitor_6.io.in.c.ready, nodeIn_6.c.ready
connect monitor_6.io.in.b.bits.corrupt, nodeIn_6.b.bits.corrupt
connect monitor_6.io.in.b.bits.data, nodeIn_6.b.bits.data
connect monitor_6.io.in.b.bits.mask, nodeIn_6.b.bits.mask
connect monitor_6.io.in.b.bits.address, nodeIn_6.b.bits.address
connect monitor_6.io.in.b.bits.source, nodeIn_6.b.bits.source
connect monitor_6.io.in.b.bits.size, nodeIn_6.b.bits.size
connect monitor_6.io.in.b.bits.param, nodeIn_6.b.bits.param
connect monitor_6.io.in.b.bits.opcode, nodeIn_6.b.bits.opcode
connect monitor_6.io.in.b.valid, nodeIn_6.b.valid
connect monitor_6.io.in.b.ready, nodeIn_6.b.ready
connect monitor_6.io.in.a.bits.corrupt, nodeIn_6.a.bits.corrupt
connect monitor_6.io.in.a.bits.data, nodeIn_6.a.bits.data
connect monitor_6.io.in.a.bits.mask, nodeIn_6.a.bits.mask
connect monitor_6.io.in.a.bits.address, nodeIn_6.a.bits.address
connect monitor_6.io.in.a.bits.source, nodeIn_6.a.bits.source
connect monitor_6.io.in.a.bits.size, nodeIn_6.a.bits.size
connect monitor_6.io.in.a.bits.param, nodeIn_6.a.bits.param
connect monitor_6.io.in.a.bits.opcode, nodeIn_6.a.bits.opcode
connect monitor_6.io.in.a.valid, nodeIn_6.a.valid
connect monitor_6.io.in.a.ready, nodeIn_6.a.ready
inst monitor_7 of TLMonitor_73
connect monitor_7.clock, clock
connect monitor_7.reset, reset
connect monitor_7.io.in.e.bits.sink, nodeIn_7.e.bits.sink
connect monitor_7.io.in.e.valid, nodeIn_7.e.valid
connect monitor_7.io.in.e.ready, nodeIn_7.e.ready
connect monitor_7.io.in.d.bits.corrupt, nodeIn_7.d.bits.corrupt
connect monitor_7.io.in.d.bits.data, nodeIn_7.d.bits.data
connect monitor_7.io.in.d.bits.denied, nodeIn_7.d.bits.denied
connect monitor_7.io.in.d.bits.sink, nodeIn_7.d.bits.sink
connect monitor_7.io.in.d.bits.source, nodeIn_7.d.bits.source
connect monitor_7.io.in.d.bits.size, nodeIn_7.d.bits.size
connect monitor_7.io.in.d.bits.param, nodeIn_7.d.bits.param
connect monitor_7.io.in.d.bits.opcode, nodeIn_7.d.bits.opcode
connect monitor_7.io.in.d.valid, nodeIn_7.d.valid
connect monitor_7.io.in.d.ready, nodeIn_7.d.ready
connect monitor_7.io.in.c.bits.corrupt, nodeIn_7.c.bits.corrupt
connect monitor_7.io.in.c.bits.data, nodeIn_7.c.bits.data
connect monitor_7.io.in.c.bits.address, nodeIn_7.c.bits.address
connect monitor_7.io.in.c.bits.source, nodeIn_7.c.bits.source
connect monitor_7.io.in.c.bits.size, nodeIn_7.c.bits.size
connect monitor_7.io.in.c.bits.param, nodeIn_7.c.bits.param
connect monitor_7.io.in.c.bits.opcode, nodeIn_7.c.bits.opcode
connect monitor_7.io.in.c.valid, nodeIn_7.c.valid
connect monitor_7.io.in.c.ready, nodeIn_7.c.ready
connect monitor_7.io.in.b.bits.corrupt, nodeIn_7.b.bits.corrupt
connect monitor_7.io.in.b.bits.data, nodeIn_7.b.bits.data
connect monitor_7.io.in.b.bits.mask, nodeIn_7.b.bits.mask
connect monitor_7.io.in.b.bits.address, nodeIn_7.b.bits.address
connect monitor_7.io.in.b.bits.source, nodeIn_7.b.bits.source
connect monitor_7.io.in.b.bits.size, nodeIn_7.b.bits.size
connect monitor_7.io.in.b.bits.param, nodeIn_7.b.bits.param
connect monitor_7.io.in.b.bits.opcode, nodeIn_7.b.bits.opcode
connect monitor_7.io.in.b.valid, nodeIn_7.b.valid
connect monitor_7.io.in.b.ready, nodeIn_7.b.ready
connect monitor_7.io.in.a.bits.corrupt, nodeIn_7.a.bits.corrupt
connect monitor_7.io.in.a.bits.data, nodeIn_7.a.bits.data
connect monitor_7.io.in.a.bits.mask, nodeIn_7.a.bits.mask
connect monitor_7.io.in.a.bits.address, nodeIn_7.a.bits.address
connect monitor_7.io.in.a.bits.source, nodeIn_7.a.bits.source
connect monitor_7.io.in.a.bits.size, nodeIn_7.a.bits.size
connect monitor_7.io.in.a.bits.param, nodeIn_7.a.bits.param
connect monitor_7.io.in.a.bits.opcode, nodeIn_7.a.bits.opcode
connect monitor_7.io.in.a.valid, nodeIn_7.a.valid
connect monitor_7.io.in.a.ready, nodeIn_7.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_nodeOut.d.bits.corrupt
invalidate x1_nodeOut.d.bits.data
invalidate x1_nodeOut.d.bits.denied
invalidate x1_nodeOut.d.bits.sink
invalidate x1_nodeOut.d.bits.source
invalidate x1_nodeOut.d.bits.size
invalidate x1_nodeOut.d.bits.param
invalidate x1_nodeOut.d.bits.opcode
invalidate x1_nodeOut.d.valid
invalidate x1_nodeOut.d.ready
invalidate x1_nodeOut.a.bits.corrupt
invalidate x1_nodeOut.a.bits.data
invalidate x1_nodeOut.a.bits.mask
invalidate x1_nodeOut.a.bits.address
invalidate x1_nodeOut.a.bits.source
invalidate x1_nodeOut.a.bits.size
invalidate x1_nodeOut.a.bits.param
invalidate x1_nodeOut.a.bits.opcode
invalidate x1_nodeOut.a.valid
invalidate x1_nodeOut.a.ready
wire x1_nodeOut_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_nodeOut_1.d.bits.corrupt
invalidate x1_nodeOut_1.d.bits.data
invalidate x1_nodeOut_1.d.bits.denied
invalidate x1_nodeOut_1.d.bits.sink
invalidate x1_nodeOut_1.d.bits.source
invalidate x1_nodeOut_1.d.bits.size
invalidate x1_nodeOut_1.d.bits.param
invalidate x1_nodeOut_1.d.bits.opcode
invalidate x1_nodeOut_1.d.valid
invalidate x1_nodeOut_1.d.ready
invalidate x1_nodeOut_1.a.bits.corrupt
invalidate x1_nodeOut_1.a.bits.data
invalidate x1_nodeOut_1.a.bits.mask
invalidate x1_nodeOut_1.a.bits.address
invalidate x1_nodeOut_1.a.bits.source
invalidate x1_nodeOut_1.a.bits.size
invalidate x1_nodeOut_1.a.bits.param
invalidate x1_nodeOut_1.a.bits.opcode
invalidate x1_nodeOut_1.a.valid
invalidate x1_nodeOut_1.a.ready
wire x1_nodeOut_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_nodeOut_2.d.bits.corrupt
invalidate x1_nodeOut_2.d.bits.data
invalidate x1_nodeOut_2.d.bits.denied
invalidate x1_nodeOut_2.d.bits.sink
invalidate x1_nodeOut_2.d.bits.source
invalidate x1_nodeOut_2.d.bits.size
invalidate x1_nodeOut_2.d.bits.param
invalidate x1_nodeOut_2.d.bits.opcode
invalidate x1_nodeOut_2.d.valid
invalidate x1_nodeOut_2.d.ready
invalidate x1_nodeOut_2.a.bits.corrupt
invalidate x1_nodeOut_2.a.bits.data
invalidate x1_nodeOut_2.a.bits.mask
invalidate x1_nodeOut_2.a.bits.address
invalidate x1_nodeOut_2.a.bits.source
invalidate x1_nodeOut_2.a.bits.size
invalidate x1_nodeOut_2.a.bits.param
invalidate x1_nodeOut_2.a.bits.opcode
invalidate x1_nodeOut_2.a.valid
invalidate x1_nodeOut_2.a.ready
wire x1_nodeOut_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_nodeOut_3.d.bits.corrupt
invalidate x1_nodeOut_3.d.bits.data
invalidate x1_nodeOut_3.d.bits.denied
invalidate x1_nodeOut_3.d.bits.sink
invalidate x1_nodeOut_3.d.bits.source
invalidate x1_nodeOut_3.d.bits.size
invalidate x1_nodeOut_3.d.bits.param
invalidate x1_nodeOut_3.d.bits.opcode
invalidate x1_nodeOut_3.d.valid
invalidate x1_nodeOut_3.d.ready
invalidate x1_nodeOut_3.a.bits.corrupt
invalidate x1_nodeOut_3.a.bits.data
invalidate x1_nodeOut_3.a.bits.mask
invalidate x1_nodeOut_3.a.bits.address
invalidate x1_nodeOut_3.a.bits.source
invalidate x1_nodeOut_3.a.bits.size
invalidate x1_nodeOut_3.a.bits.param
invalidate x1_nodeOut_3.a.bits.opcode
invalidate x1_nodeOut_3.a.valid
invalidate x1_nodeOut_3.a.ready
wire x1_nodeOut_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_nodeOut_4.d.bits.corrupt
invalidate x1_nodeOut_4.d.bits.data
invalidate x1_nodeOut_4.d.bits.denied
invalidate x1_nodeOut_4.d.bits.sink
invalidate x1_nodeOut_4.d.bits.source
invalidate x1_nodeOut_4.d.bits.size
invalidate x1_nodeOut_4.d.bits.param
invalidate x1_nodeOut_4.d.bits.opcode
invalidate x1_nodeOut_4.d.valid
invalidate x1_nodeOut_4.d.ready
invalidate x1_nodeOut_4.a.bits.corrupt
invalidate x1_nodeOut_4.a.bits.data
invalidate x1_nodeOut_4.a.bits.mask
invalidate x1_nodeOut_4.a.bits.address
invalidate x1_nodeOut_4.a.bits.source
invalidate x1_nodeOut_4.a.bits.size
invalidate x1_nodeOut_4.a.bits.param
invalidate x1_nodeOut_4.a.bits.opcode
invalidate x1_nodeOut_4.a.valid
invalidate x1_nodeOut_4.a.ready
wire x1_nodeOut_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_nodeOut_5.d.bits.corrupt
invalidate x1_nodeOut_5.d.bits.data
invalidate x1_nodeOut_5.d.bits.denied
invalidate x1_nodeOut_5.d.bits.sink
invalidate x1_nodeOut_5.d.bits.source
invalidate x1_nodeOut_5.d.bits.size
invalidate x1_nodeOut_5.d.bits.param
invalidate x1_nodeOut_5.d.bits.opcode
invalidate x1_nodeOut_5.d.valid
invalidate x1_nodeOut_5.d.ready
invalidate x1_nodeOut_5.a.bits.corrupt
invalidate x1_nodeOut_5.a.bits.data
invalidate x1_nodeOut_5.a.bits.mask
invalidate x1_nodeOut_5.a.bits.address
invalidate x1_nodeOut_5.a.bits.source
invalidate x1_nodeOut_5.a.bits.size
invalidate x1_nodeOut_5.a.bits.param
invalidate x1_nodeOut_5.a.bits.opcode
invalidate x1_nodeOut_5.a.valid
invalidate x1_nodeOut_5.a.ready
wire x1_nodeOut_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_nodeOut_6.d.bits.corrupt
invalidate x1_nodeOut_6.d.bits.data
invalidate x1_nodeOut_6.d.bits.denied
invalidate x1_nodeOut_6.d.bits.sink
invalidate x1_nodeOut_6.d.bits.source
invalidate x1_nodeOut_6.d.bits.size
invalidate x1_nodeOut_6.d.bits.param
invalidate x1_nodeOut_6.d.bits.opcode
invalidate x1_nodeOut_6.d.valid
invalidate x1_nodeOut_6.d.ready
invalidate x1_nodeOut_6.a.bits.corrupt
invalidate x1_nodeOut_6.a.bits.data
invalidate x1_nodeOut_6.a.bits.mask
invalidate x1_nodeOut_6.a.bits.address
invalidate x1_nodeOut_6.a.bits.source
invalidate x1_nodeOut_6.a.bits.size
invalidate x1_nodeOut_6.a.bits.param
invalidate x1_nodeOut_6.a.bits.opcode
invalidate x1_nodeOut_6.a.valid
invalidate x1_nodeOut_6.a.ready
connect auto.out_0, nodeOut
connect auto.out_1, x1_nodeOut
connect auto.out_2, x1_nodeOut_1
connect auto.out_3, x1_nodeOut_2
connect auto.out_4, x1_nodeOut_3
connect auto.out_5, x1_nodeOut_4
connect auto.out_6, x1_nodeOut_5
connect auto.out_7, x1_nodeOut_6
connect nodeIn, auto.in_0
connect nodeIn_1, auto.in_1
connect nodeIn_2, auto.in_2
connect nodeIn_3, auto.in_3
connect nodeIn_4, auto.in_4
connect nodeIn_5, auto.in_5
connect nodeIn_6, auto.in_6
connect nodeIn_7, auto.in_7
wire a_a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
wire a_d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _isPut_T = eq(nodeIn.a.bits.opcode, UInt<1>(0h0))
node _isPut_T_1 = eq(nodeIn.a.bits.opcode, UInt<1>(0h1))
node isPut = or(_isPut_T, _isPut_T_1)
node _toD_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h6))
node _toD_T_1 = eq(nodeIn.a.bits.param, UInt<2>(0h2))
node _toD_T_2 = and(_toD_T, _toD_T_1)
node _toD_T_3 = eq(nodeIn.a.bits.opcode, UInt<3>(0h7))
node toD = or(_toD_T_2, _toD_T_3)
node _nodeIn_a_ready_T = mux(toD, a_d.ready, a_a.ready)
connect nodeIn.a.ready, _nodeIn_a_ready_T
node _a_a_valid_T = eq(toD, UInt<1>(0h0))
node _a_a_valid_T_1 = and(nodeIn.a.valid, _a_a_valid_T)
connect a_a.valid, _a_a_valid_T_1
connect a_a.bits, nodeIn.a.bits
node _a_a_bits_source_T = shl(nodeIn.a.bits.source, 1)
node _a_a_bits_source_T_1 = mux(isPut, UInt<1>(0h1), UInt<1>(0h0))
node _a_a_bits_source_T_2 = or(_a_a_bits_source_T, _a_a_bits_source_T_1)
connect a_a.bits.source, _a_a_bits_source_T_2
node _T = eq(nodeIn.a.bits.opcode, UInt<3>(0h6))
node _T_1 = eq(nodeIn.a.bits.opcode, UInt<3>(0h7))
node _T_2 = or(_T, _T_1)
when _T_2 :
connect a_a.bits.opcode, UInt<3>(0h4)
connect a_a.bits.param, UInt<1>(0h0)
node _a_a_bits_source_T_3 = shl(nodeIn.a.bits.source, 1)
node _a_a_bits_source_T_4 = or(_a_a_bits_source_T_3, UInt<1>(0h1))
connect a_a.bits.source, _a_a_bits_source_T_4
node _a_d_valid_T = and(nodeIn.a.valid, toD)
connect a_d.valid, _a_d_valid_T
wire a_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect a_d_bits_d.opcode, UInt<3>(0h4)
connect a_d_bits_d.param, UInt<2>(0h0)
connect a_d_bits_d.size, nodeIn.a.bits.size
connect a_d_bits_d.source, nodeIn.a.bits.source
connect a_d_bits_d.sink, UInt<1>(0h0)
connect a_d_bits_d.denied, UInt<1>(0h0)
invalidate a_d_bits_d.data
connect a_d_bits_d.corrupt, UInt<1>(0h0)
connect a_d.bits.corrupt, a_d_bits_d.corrupt
connect a_d.bits.data, a_d_bits_d.data
connect a_d.bits.denied, a_d_bits_d.denied
connect a_d.bits.sink, a_d_bits_d.sink
connect a_d.bits.source, a_d_bits_d.source
connect a_d.bits.size, a_d_bits_d.size
connect a_d.bits.param, a_d_bits_d.param
connect a_d.bits.opcode, a_d_bits_d.opcode
wire c_a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
node _c_a_valid_T = eq(nodeIn.c.bits.opcode, UInt<3>(0h7))
node _c_a_valid_T_1 = and(nodeIn.c.valid, _c_a_valid_T)
connect c_a.valid, _c_a_valid_T_1
node _c_a_bits_T = shl(nodeIn.c.bits.source, 1)
node _c_a_bits_legal_T = leq(UInt<1>(0h0), nodeIn.c.bits.size)
node _c_a_bits_legal_T_1 = leq(nodeIn.c.bits.size, UInt<3>(0h6))
node _c_a_bits_legal_T_2 = and(_c_a_bits_legal_T, _c_a_bits_legal_T_1)
node _c_a_bits_legal_T_3 = or(UInt<1>(0h0), _c_a_bits_legal_T_2)
node _c_a_bits_legal_T_4 = xor(nodeIn.c.bits.address, UInt<1>(0h0))
node _c_a_bits_legal_T_5 = cvt(_c_a_bits_legal_T_4)
node _c_a_bits_legal_T_6 = and(_c_a_bits_legal_T_5, asSInt(UInt<1>(0h0)))
node _c_a_bits_legal_T_7 = asSInt(_c_a_bits_legal_T_6)
node _c_a_bits_legal_T_8 = eq(_c_a_bits_legal_T_7, asSInt(UInt<1>(0h0)))
node _c_a_bits_legal_T_9 = and(_c_a_bits_legal_T_3, _c_a_bits_legal_T_8)
node c_a_bits_legal = or(UInt<1>(0h0), _c_a_bits_legal_T_9)
wire c_a_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect c_a_bits_a.opcode, UInt<1>(0h0)
connect c_a_bits_a.param, UInt<1>(0h0)
connect c_a_bits_a.size, nodeIn.c.bits.size
connect c_a_bits_a.source, _c_a_bits_T
connect c_a_bits_a.address, nodeIn.c.bits.address
node _c_a_bits_a_mask_sizeOH_T = or(nodeIn.c.bits.size, UInt<3>(0h0))
node c_a_bits_a_mask_sizeOH_shiftAmount = bits(_c_a_bits_a_mask_sizeOH_T, 1, 0)
node _c_a_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), c_a_bits_a_mask_sizeOH_shiftAmount)
node _c_a_bits_a_mask_sizeOH_T_2 = bits(_c_a_bits_a_mask_sizeOH_T_1, 2, 0)
node c_a_bits_a_mask_sizeOH = or(_c_a_bits_a_mask_sizeOH_T_2, UInt<1>(0h1))
node c_a_bits_a_mask_sub_sub_sub_0_1 = geq(nodeIn.c.bits.size, UInt<2>(0h3))
node c_a_bits_a_mask_sub_sub_size = bits(c_a_bits_a_mask_sizeOH, 2, 2)
node c_a_bits_a_mask_sub_sub_bit = bits(nodeIn.c.bits.address, 2, 2)
node c_a_bits_a_mask_sub_sub_nbit = eq(c_a_bits_a_mask_sub_sub_bit, UInt<1>(0h0))
node c_a_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_nbit)
node _c_a_bits_a_mask_sub_sub_acc_T = and(c_a_bits_a_mask_sub_sub_size, c_a_bits_a_mask_sub_sub_0_2)
node c_a_bits_a_mask_sub_sub_0_1 = or(c_a_bits_a_mask_sub_sub_sub_0_1, _c_a_bits_a_mask_sub_sub_acc_T)
node c_a_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_bit)
node _c_a_bits_a_mask_sub_sub_acc_T_1 = and(c_a_bits_a_mask_sub_sub_size, c_a_bits_a_mask_sub_sub_1_2)
node c_a_bits_a_mask_sub_sub_1_1 = or(c_a_bits_a_mask_sub_sub_sub_0_1, _c_a_bits_a_mask_sub_sub_acc_T_1)
node c_a_bits_a_mask_sub_size = bits(c_a_bits_a_mask_sizeOH, 1, 1)
node c_a_bits_a_mask_sub_bit = bits(nodeIn.c.bits.address, 1, 1)
node c_a_bits_a_mask_sub_nbit = eq(c_a_bits_a_mask_sub_bit, UInt<1>(0h0))
node c_a_bits_a_mask_sub_0_2 = and(c_a_bits_a_mask_sub_sub_0_2, c_a_bits_a_mask_sub_nbit)
node _c_a_bits_a_mask_sub_acc_T = and(c_a_bits_a_mask_sub_size, c_a_bits_a_mask_sub_0_2)
node c_a_bits_a_mask_sub_0_1 = or(c_a_bits_a_mask_sub_sub_0_1, _c_a_bits_a_mask_sub_acc_T)
node c_a_bits_a_mask_sub_1_2 = and(c_a_bits_a_mask_sub_sub_0_2, c_a_bits_a_mask_sub_bit)
node _c_a_bits_a_mask_sub_acc_T_1 = and(c_a_bits_a_mask_sub_size, c_a_bits_a_mask_sub_1_2)
node c_a_bits_a_mask_sub_1_1 = or(c_a_bits_a_mask_sub_sub_0_1, _c_a_bits_a_mask_sub_acc_T_1)
node c_a_bits_a_mask_sub_2_2 = and(c_a_bits_a_mask_sub_sub_1_2, c_a_bits_a_mask_sub_nbit)
node _c_a_bits_a_mask_sub_acc_T_2 = and(c_a_bits_a_mask_sub_size, c_a_bits_a_mask_sub_2_2)
node c_a_bits_a_mask_sub_2_1 = or(c_a_bits_a_mask_sub_sub_1_1, _c_a_bits_a_mask_sub_acc_T_2)
node c_a_bits_a_mask_sub_3_2 = and(c_a_bits_a_mask_sub_sub_1_2, c_a_bits_a_mask_sub_bit)
node _c_a_bits_a_mask_sub_acc_T_3 = and(c_a_bits_a_mask_sub_size, c_a_bits_a_mask_sub_3_2)
node c_a_bits_a_mask_sub_3_1 = or(c_a_bits_a_mask_sub_sub_1_1, _c_a_bits_a_mask_sub_acc_T_3)
node c_a_bits_a_mask_size = bits(c_a_bits_a_mask_sizeOH, 0, 0)
node c_a_bits_a_mask_bit = bits(nodeIn.c.bits.address, 0, 0)
node c_a_bits_a_mask_nbit = eq(c_a_bits_a_mask_bit, UInt<1>(0h0))
node c_a_bits_a_mask_eq = and(c_a_bits_a_mask_sub_0_2, c_a_bits_a_mask_nbit)
node _c_a_bits_a_mask_acc_T = and(c_a_bits_a_mask_size, c_a_bits_a_mask_eq)
node c_a_bits_a_mask_acc = or(c_a_bits_a_mask_sub_0_1, _c_a_bits_a_mask_acc_T)
node c_a_bits_a_mask_eq_1 = and(c_a_bits_a_mask_sub_0_2, c_a_bits_a_mask_bit)
node _c_a_bits_a_mask_acc_T_1 = and(c_a_bits_a_mask_size, c_a_bits_a_mask_eq_1)
node c_a_bits_a_mask_acc_1 = or(c_a_bits_a_mask_sub_0_1, _c_a_bits_a_mask_acc_T_1)
node c_a_bits_a_mask_eq_2 = and(c_a_bits_a_mask_sub_1_2, c_a_bits_a_mask_nbit)
node _c_a_bits_a_mask_acc_T_2 = and(c_a_bits_a_mask_size, c_a_bits_a_mask_eq_2)
node c_a_bits_a_mask_acc_2 = or(c_a_bits_a_mask_sub_1_1, _c_a_bits_a_mask_acc_T_2)
node c_a_bits_a_mask_eq_3 = and(c_a_bits_a_mask_sub_1_2, c_a_bits_a_mask_bit)
node _c_a_bits_a_mask_acc_T_3 = and(c_a_bits_a_mask_size, c_a_bits_a_mask_eq_3)
node c_a_bits_a_mask_acc_3 = or(c_a_bits_a_mask_sub_1_1, _c_a_bits_a_mask_acc_T_3)
node c_a_bits_a_mask_eq_4 = and(c_a_bits_a_mask_sub_2_2, c_a_bits_a_mask_nbit)
node _c_a_bits_a_mask_acc_T_4 = and(c_a_bits_a_mask_size, c_a_bits_a_mask_eq_4)
node c_a_bits_a_mask_acc_4 = or(c_a_bits_a_mask_sub_2_1, _c_a_bits_a_mask_acc_T_4)
node c_a_bits_a_mask_eq_5 = and(c_a_bits_a_mask_sub_2_2, c_a_bits_a_mask_bit)
node _c_a_bits_a_mask_acc_T_5 = and(c_a_bits_a_mask_size, c_a_bits_a_mask_eq_5)
node c_a_bits_a_mask_acc_5 = or(c_a_bits_a_mask_sub_2_1, _c_a_bits_a_mask_acc_T_5)
node c_a_bits_a_mask_eq_6 = and(c_a_bits_a_mask_sub_3_2, c_a_bits_a_mask_nbit)
node _c_a_bits_a_mask_acc_T_6 = and(c_a_bits_a_mask_size, c_a_bits_a_mask_eq_6)
node c_a_bits_a_mask_acc_6 = or(c_a_bits_a_mask_sub_3_1, _c_a_bits_a_mask_acc_T_6)
node c_a_bits_a_mask_eq_7 = and(c_a_bits_a_mask_sub_3_2, c_a_bits_a_mask_bit)
node _c_a_bits_a_mask_acc_T_7 = and(c_a_bits_a_mask_size, c_a_bits_a_mask_eq_7)
node c_a_bits_a_mask_acc_7 = or(c_a_bits_a_mask_sub_3_1, _c_a_bits_a_mask_acc_T_7)
node c_a_bits_a_mask_lo_lo = cat(c_a_bits_a_mask_acc_1, c_a_bits_a_mask_acc)
node c_a_bits_a_mask_lo_hi = cat(c_a_bits_a_mask_acc_3, c_a_bits_a_mask_acc_2)
node c_a_bits_a_mask_lo = cat(c_a_bits_a_mask_lo_hi, c_a_bits_a_mask_lo_lo)
node c_a_bits_a_mask_hi_lo = cat(c_a_bits_a_mask_acc_5, c_a_bits_a_mask_acc_4)
node c_a_bits_a_mask_hi_hi = cat(c_a_bits_a_mask_acc_7, c_a_bits_a_mask_acc_6)
node c_a_bits_a_mask_hi = cat(c_a_bits_a_mask_hi_hi, c_a_bits_a_mask_hi_lo)
node _c_a_bits_a_mask_T = cat(c_a_bits_a_mask_hi, c_a_bits_a_mask_lo)
connect c_a_bits_a.mask, _c_a_bits_a_mask_T
connect c_a_bits_a.data, nodeIn.c.bits.data
connect c_a_bits_a.corrupt, nodeIn.c.bits.corrupt
connect c_a.bits, c_a_bits_a
wire c_d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _c_d_valid_T = eq(nodeIn.c.bits.opcode, UInt<3>(0h6))
node _c_d_valid_T_1 = and(nodeIn.c.valid, _c_d_valid_T)
connect c_d.valid, _c_d_valid_T_1
wire c_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect c_d_bits_d.opcode, UInt<3>(0h6)
connect c_d_bits_d.param, UInt<1>(0h0)
connect c_d_bits_d.size, nodeIn.c.bits.size
connect c_d_bits_d.source, nodeIn.c.bits.source
connect c_d_bits_d.sink, UInt<1>(0h0)
connect c_d_bits_d.denied, UInt<1>(0h0)
invalidate c_d_bits_d.data
connect c_d_bits_d.corrupt, UInt<1>(0h0)
connect c_d.bits.corrupt, c_d_bits_d.corrupt
connect c_d.bits.data, c_d_bits_d.data
connect c_d.bits.denied, c_d_bits_d.denied
connect c_d.bits.sink, c_d_bits_d.sink
connect c_d.bits.source, c_d_bits_d.source
connect c_d.bits.size, c_d_bits_d.size
connect c_d.bits.param, c_d_bits_d.param
connect c_d.bits.opcode, c_d_bits_d.opcode
node _T_3 = eq(nodeIn.c.valid, UInt<1>(0h0))
node _T_4 = eq(nodeIn.c.bits.opcode, UInt<3>(0h6))
node _T_5 = or(_T_3, _T_4)
node _T_6 = eq(nodeIn.c.bits.opcode, UInt<3>(0h7))
node _T_7 = or(_T_5, _T_6)
node _T_8 = asUInt(reset)
node _T_9 = eq(_T_8, UInt<1>(0h0))
when _T_9 :
node _T_10 = eq(_T_7, UInt<1>(0h0))
when _T_10 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:116 assert (!in.c.valid || in.c.bits.opcode === Release || in.c.bits.opcode === ReleaseData)\n") : printf
assert(clock, _T_7, UInt<1>(0h1), "") : assert
node _nodeIn_c_ready_T = eq(nodeIn.c.bits.opcode, UInt<3>(0h6))
node _nodeIn_c_ready_T_1 = mux(_nodeIn_c_ready_T, c_d.ready, c_a.ready)
connect nodeIn.c.ready, _nodeIn_c_ready_T_1
connect nodeIn.e.ready, UInt<1>(0h1)
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.ready, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.mask, UInt<8>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<2>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_11 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:124 assert (!out.b.valid)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
inst pool of IDPool
connect pool.clock, clock
connect pool.reset, reset
node _pool_io_free_valid_T = and(nodeIn.e.ready, nodeIn.e.valid)
connect pool.io.free.valid, _pool_io_free_valid_T
connect pool.io.free.bits, nodeIn.e.bits.sink
wire in_d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _d_first_T = and(in_d.ready, in_d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), in_d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(in_d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
node _d_grant_T = eq(in_d.bits.opcode, UInt<3>(0h5))
node _d_grant_T_1 = eq(in_d.bits.opcode, UInt<3>(0h4))
node d_grant = or(_d_grant_T, _d_grant_T_1)
node _pool_io_alloc_ready_T = and(nodeIn.d.ready, nodeIn.d.valid)
node _pool_io_alloc_ready_T_1 = and(_pool_io_alloc_ready_T, d_first)
node _pool_io_alloc_ready_T_2 = and(_pool_io_alloc_ready_T_1, d_grant)
connect pool.io.alloc.ready, _pool_io_alloc_ready_T_2
node _nodeIn_d_valid_T = eq(d_first, UInt<1>(0h0))
node _nodeIn_d_valid_T_1 = or(pool.io.alloc.valid, _nodeIn_d_valid_T)
node _nodeIn_d_valid_T_2 = eq(d_grant, UInt<1>(0h0))
node _nodeIn_d_valid_T_3 = or(_nodeIn_d_valid_T_1, _nodeIn_d_valid_T_2)
node _nodeIn_d_valid_T_4 = and(in_d.valid, _nodeIn_d_valid_T_3)
connect nodeIn.d.valid, _nodeIn_d_valid_T_4
node _in_d_ready_T = eq(d_first, UInt<1>(0h0))
node _in_d_ready_T_1 = or(pool.io.alloc.valid, _in_d_ready_T)
node _in_d_ready_T_2 = eq(d_grant, UInt<1>(0h0))
node _in_d_ready_T_3 = or(_in_d_ready_T_1, _in_d_ready_T_2)
node _in_d_ready_T_4 = and(nodeIn.d.ready, _in_d_ready_T_3)
connect in_d.ready, _in_d_ready_T_4
connect nodeIn.d.bits.corrupt, in_d.bits.corrupt
connect nodeIn.d.bits.data, in_d.bits.data
connect nodeIn.d.bits.denied, in_d.bits.denied
connect nodeIn.d.bits.sink, in_d.bits.sink
connect nodeIn.d.bits.source, in_d.bits.source
connect nodeIn.d.bits.size, in_d.bits.size
connect nodeIn.d.bits.param, in_d.bits.param
connect nodeIn.d.bits.opcode, in_d.bits.opcode
reg nodeIn_d_bits_sink_r : UInt<3>, clock
when d_first :
connect nodeIn_d_bits_sink_r, pool.io.alloc.bits
node _nodeIn_d_bits_sink_T = mux(d_first, pool.io.alloc.bits, nodeIn_d_bits_sink_r)
connect nodeIn.d.bits.sink, _nodeIn_d_bits_sink_T
wire d_d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect d_d, nodeOut.d
node _d_d_bits_source_T = shr(nodeOut.d.bits.source, 1)
connect d_d.bits.source, _d_d_bits_source_T
reg wSourceVec : UInt<1>[10], clock
node _aWOk_T = xor(nodeIn.a.bits.address, UInt<1>(0h0))
node _aWOk_T_1 = cvt(_aWOk_T)
node _aWOk_T_2 = and(_aWOk_T_1, asSInt(UInt<1>(0h0)))
node _aWOk_T_3 = asSInt(_aWOk_T_2)
node _aWOk_T_4 = eq(_aWOk_T_3, asSInt(UInt<1>(0h0)))
node _bypass_T = and(UInt<1>(0h0), nodeIn.a.valid)
node _bypass_T_1 = eq(nodeIn.a.bits.source, d_d.bits.source)
node bypass = and(_bypass_T, _bypass_T_1)
node _dWHeld_T = mux(bypass, UInt<1>(0h1), wSourceVec[d_d.bits.source])
reg dWHeld_r : UInt<1>, clock
when d_first :
connect dWHeld_r, _dWHeld_T
node dWHeld = mux(d_first, _dWHeld_T, dWHeld_r)
node _T_15 = and(nodeIn.a.ready, nodeIn.a.valid)
when _T_15 :
connect wSourceVec[nodeIn.a.bits.source], UInt<1>(0h1)
node _T_16 = eq(nodeOut.d.bits.opcode, UInt<1>(0h1))
node _T_17 = bits(nodeOut.d.bits.source, 0, 0)
node _T_18 = and(_T_16, _T_17)
when _T_18 :
connect d_d.bits.opcode, UInt<3>(0h5)
node _d_d_bits_param_T = mux(dWHeld, UInt<2>(0h0), UInt<2>(0h1))
connect d_d.bits.param, _d_d_bits_param_T
node _T_19 = eq(nodeOut.d.bits.opcode, UInt<1>(0h0))
node _T_20 = bits(nodeOut.d.bits.source, 0, 0)
node _T_21 = eq(_T_20, UInt<1>(0h0))
node _T_22 = and(_T_19, _T_21)
when _T_22 :
connect d_d.bits.opcode, UInt<3>(0h6)
node _decode_T = dshl(UInt<6>(0h3f), c_a.bits.size)
node _decode_T_1 = bits(_decode_T, 5, 0)
node _decode_T_2 = not(_decode_T_1)
node decode = shr(_decode_T_2, 3)
node _opdata_T = bits(c_a.bits.opcode, 2, 2)
node opdata = eq(_opdata_T, UInt<1>(0h0))
node _T_23 = mux(opdata, decode, UInt<1>(0h0))
node _decode_T_3 = dshl(UInt<6>(0h3f), a_a.bits.size)
node _decode_T_4 = bits(_decode_T_3, 5, 0)
node _decode_T_5 = not(_decode_T_4)
node decode_1 = shr(_decode_T_5, 3)
node _opdata_T_1 = bits(a_a.bits.opcode, 2, 2)
node opdata_1 = eq(_opdata_T_1, UInt<1>(0h0))
node _T_24 = mux(opdata_1, decode_1, UInt<1>(0h0))
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, nodeOut.a.ready)
node _readys_T = cat(a_a.valid, c_a.valid)
node _readys_T_1 = shl(_readys_T, 1)
node _readys_T_2 = bits(_readys_T_1, 1, 0)
node _readys_T_3 = or(_readys_T, _readys_T_2)
node _readys_T_4 = bits(_readys_T_3, 1, 0)
node _readys_T_5 = shl(_readys_T_4, 1)
node _readys_T_6 = bits(_readys_T_5, 1, 0)
node _readys_T_7 = not(_readys_T_6)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
wire readys : UInt<1>[2]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
node _winner_T = and(readys[0], c_a.valid)
node _winner_T_1 = and(readys[1], a_a.valid)
wire winner : UInt<1>[2]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node _prefixOR_T = or(prefixOR_1, winner[1])
node _T_25 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_26 = eq(winner[0], UInt<1>(0h0))
node _T_27 = or(_T_25, _T_26)
node _T_28 = eq(prefixOR_1, UInt<1>(0h0))
node _T_29 = eq(winner[1], UInt<1>(0h0))
node _T_30 = or(_T_28, _T_29)
node _T_31 = and(_T_27, _T_30)
node _T_32 = asUInt(reset)
node _T_33 = eq(_T_32, UInt<1>(0h0))
when _T_33 :
node _T_34 = eq(_T_31, UInt<1>(0h0))
when _T_34 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_2
assert(clock, _T_31, UInt<1>(0h1), "") : assert_2
node _T_35 = or(c_a.valid, a_a.valid)
node _T_36 = eq(_T_35, UInt<1>(0h0))
node _T_37 = or(winner[0], winner[1])
node _T_38 = or(_T_36, _T_37)
node _T_39 = asUInt(reset)
node _T_40 = eq(_T_39, UInt<1>(0h0))
when _T_40 :
node _T_41 = eq(_T_38, UInt<1>(0h0))
when _T_41 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_3
assert(clock, _T_38, UInt<1>(0h1), "") : assert_3
node maskedBeats_0 = mux(winner[0], _T_23, UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], _T_24, UInt<1>(0h0))
node initBeats = or(maskedBeats_0, maskedBeats_1)
node _beatsLeft_T = and(nodeOut.a.ready, nodeOut.a.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[2]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
regreset state : UInt<1>[2], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _c_a_ready_T = and(nodeOut.a.ready, allowed[0])
connect c_a.ready, _c_a_ready_T
node _a_a_ready_T = and(nodeOut.a.ready, allowed[1])
connect a_a.ready, _a_a_ready_T
node _nodeOut_a_valid_T = or(c_a.valid, a_a.valid)
node _nodeOut_a_valid_T_1 = mux(state[0], c_a.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_2 = mux(state[1], a_a.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_3 = or(_nodeOut_a_valid_T_1, _nodeOut_a_valid_T_2)
wire _nodeOut_a_valid_WIRE : UInt<1>
connect _nodeOut_a_valid_WIRE, _nodeOut_a_valid_T_3
node _nodeOut_a_valid_T_4 = mux(idle, _nodeOut_a_valid_T, _nodeOut_a_valid_WIRE)
connect nodeOut.a.valid, _nodeOut_a_valid_T_4
wire _nodeOut_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _nodeOut_a_bits_T = mux(muxState[0], c_a.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_1 = mux(muxState[1], a_a.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_2 = or(_nodeOut_a_bits_T, _nodeOut_a_bits_T_1)
wire _nodeOut_a_bits_WIRE_1 : UInt<1>
connect _nodeOut_a_bits_WIRE_1, _nodeOut_a_bits_T_2
connect _nodeOut_a_bits_WIRE.corrupt, _nodeOut_a_bits_WIRE_1
node _nodeOut_a_bits_T_3 = mux(muxState[0], c_a.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_4 = mux(muxState[1], a_a.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_5 = or(_nodeOut_a_bits_T_3, _nodeOut_a_bits_T_4)
wire _nodeOut_a_bits_WIRE_2 : UInt<64>
connect _nodeOut_a_bits_WIRE_2, _nodeOut_a_bits_T_5
connect _nodeOut_a_bits_WIRE.data, _nodeOut_a_bits_WIRE_2
node _nodeOut_a_bits_T_6 = mux(muxState[0], c_a.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_7 = mux(muxState[1], a_a.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_8 = or(_nodeOut_a_bits_T_6, _nodeOut_a_bits_T_7)
wire _nodeOut_a_bits_WIRE_3 : UInt<8>
connect _nodeOut_a_bits_WIRE_3, _nodeOut_a_bits_T_8
connect _nodeOut_a_bits_WIRE.mask, _nodeOut_a_bits_WIRE_3
wire _nodeOut_a_bits_WIRE_4 : { }
connect _nodeOut_a_bits_WIRE.echo, _nodeOut_a_bits_WIRE_4
wire _nodeOut_a_bits_WIRE_5 : { }
connect _nodeOut_a_bits_WIRE.user, _nodeOut_a_bits_WIRE_5
node _nodeOut_a_bits_T_9 = mux(muxState[0], c_a.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_10 = mux(muxState[1], a_a.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_11 = or(_nodeOut_a_bits_T_9, _nodeOut_a_bits_T_10)
wire _nodeOut_a_bits_WIRE_6 : UInt<32>
connect _nodeOut_a_bits_WIRE_6, _nodeOut_a_bits_T_11
connect _nodeOut_a_bits_WIRE.address, _nodeOut_a_bits_WIRE_6
node _nodeOut_a_bits_T_12 = mux(muxState[0], c_a.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_13 = mux(muxState[1], a_a.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_14 = or(_nodeOut_a_bits_T_12, _nodeOut_a_bits_T_13)
wire _nodeOut_a_bits_WIRE_7 : UInt<5>
connect _nodeOut_a_bits_WIRE_7, _nodeOut_a_bits_T_14
connect _nodeOut_a_bits_WIRE.source, _nodeOut_a_bits_WIRE_7
node _nodeOut_a_bits_T_15 = mux(muxState[0], c_a.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_16 = mux(muxState[1], a_a.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_17 = or(_nodeOut_a_bits_T_15, _nodeOut_a_bits_T_16)
wire _nodeOut_a_bits_WIRE_8 : UInt<3>
connect _nodeOut_a_bits_WIRE_8, _nodeOut_a_bits_T_17
connect _nodeOut_a_bits_WIRE.size, _nodeOut_a_bits_WIRE_8
node _nodeOut_a_bits_T_18 = mux(muxState[0], c_a.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_19 = mux(muxState[1], a_a.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_20 = or(_nodeOut_a_bits_T_18, _nodeOut_a_bits_T_19)
wire _nodeOut_a_bits_WIRE_9 : UInt<3>
connect _nodeOut_a_bits_WIRE_9, _nodeOut_a_bits_T_20
connect _nodeOut_a_bits_WIRE.param, _nodeOut_a_bits_WIRE_9
node _nodeOut_a_bits_T_21 = mux(muxState[0], c_a.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_22 = mux(muxState[1], a_a.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_23 = or(_nodeOut_a_bits_T_21, _nodeOut_a_bits_T_22)
wire _nodeOut_a_bits_WIRE_10 : UInt<3>
connect _nodeOut_a_bits_WIRE_10, _nodeOut_a_bits_T_23
connect _nodeOut_a_bits_WIRE.opcode, _nodeOut_a_bits_WIRE_10
connect nodeOut.a.bits.corrupt, _nodeOut_a_bits_WIRE.corrupt
connect nodeOut.a.bits.data, _nodeOut_a_bits_WIRE.data
connect nodeOut.a.bits.mask, _nodeOut_a_bits_WIRE.mask
connect nodeOut.a.bits.address, _nodeOut_a_bits_WIRE.address
connect nodeOut.a.bits.source, _nodeOut_a_bits_WIRE.source
connect nodeOut.a.bits.size, _nodeOut_a_bits_WIRE.size
connect nodeOut.a.bits.param, _nodeOut_a_bits_WIRE.param
connect nodeOut.a.bits.opcode, _nodeOut_a_bits_WIRE.opcode
node _decode_T_6 = dshl(UInt<6>(0h3f), d_d.bits.size)
node _decode_T_7 = bits(_decode_T_6, 5, 0)
node _decode_T_8 = not(_decode_T_7)
node decode_2 = shr(_decode_T_8, 3)
node opdata_2 = bits(d_d.bits.opcode, 0, 0)
node _T_42 = mux(opdata_2, decode_2, UInt<1>(0h0))
inst q of Queue2_TLBundleD_a32d64s4k3z3c_8
connect q.clock, clock
connect q.reset, reset
connect q.io.enq.valid, c_d.valid
connect q.io.enq.bits.corrupt, c_d.bits.corrupt
connect q.io.enq.bits.data, c_d.bits.data
connect q.io.enq.bits.denied, c_d.bits.denied
connect q.io.enq.bits.sink, c_d.bits.sink
connect q.io.enq.bits.source, c_d.bits.source
connect q.io.enq.bits.size, c_d.bits.size
connect q.io.enq.bits.param, c_d.bits.param
connect q.io.enq.bits.opcode, c_d.bits.opcode
connect c_d.ready, q.io.enq.ready
inst q_1 of Queue2_TLBundleD_a32d64s4k3z3c_9
connect q_1.clock, clock
connect q_1.reset, reset
connect q_1.io.enq.valid, a_d.valid
connect q_1.io.enq.bits.corrupt, a_d.bits.corrupt
connect q_1.io.enq.bits.data, a_d.bits.data
connect q_1.io.enq.bits.denied, a_d.bits.denied
connect q_1.io.enq.bits.sink, a_d.bits.sink
connect q_1.io.enq.bits.source, a_d.bits.source
connect q_1.io.enq.bits.size, a_d.bits.size
connect q_1.io.enq.bits.param, a_d.bits.param
connect q_1.io.enq.bits.opcode, a_d.bits.opcode
connect a_d.ready, q_1.io.enq.ready
regreset beatsLeft_1 : UInt, clock, reset, UInt<1>(0h0)
node idle_1 = eq(beatsLeft_1, UInt<1>(0h0))
node latch_1 = and(idle_1, in_d.ready)
node readys_hi = cat(q_1.io.deq.valid, q.io.deq.valid)
node _readys_T_10 = cat(readys_hi, d_d.valid)
node _readys_T_11 = shl(_readys_T_10, 1)
node _readys_T_12 = bits(_readys_T_11, 2, 0)
node _readys_T_13 = or(_readys_T_10, _readys_T_12)
node _readys_T_14 = shl(_readys_T_13, 2)
node _readys_T_15 = bits(_readys_T_14, 2, 0)
node _readys_T_16 = or(_readys_T_13, _readys_T_15)
node _readys_T_17 = bits(_readys_T_16, 2, 0)
node _readys_T_18 = shl(_readys_T_17, 1)
node _readys_T_19 = bits(_readys_T_18, 2, 0)
node _readys_T_20 = not(_readys_T_19)
node _readys_T_21 = bits(_readys_T_20, 0, 0)
node _readys_T_22 = bits(_readys_T_20, 1, 1)
node _readys_T_23 = bits(_readys_T_20, 2, 2)
wire readys_1 : UInt<1>[3]
connect readys_1[0], _readys_T_21
connect readys_1[1], _readys_T_22
connect readys_1[2], _readys_T_23
node _winner_T_2 = and(readys_1[0], d_d.valid)
node _winner_T_3 = and(readys_1[1], q.io.deq.valid)
node _winner_T_4 = and(readys_1[2], q_1.io.deq.valid)
wire winner_1 : UInt<1>[3]
connect winner_1[0], _winner_T_2
connect winner_1[1], _winner_T_3
connect winner_1[2], _winner_T_4
node prefixOR_1_1 = or(UInt<1>(0h0), winner_1[0])
node prefixOR_2 = or(prefixOR_1_1, winner_1[1])
node _prefixOR_T_1 = or(prefixOR_2, winner_1[2])
node _T_43 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_44 = eq(winner_1[0], UInt<1>(0h0))
node _T_45 = or(_T_43, _T_44)
node _T_46 = eq(prefixOR_1_1, UInt<1>(0h0))
node _T_47 = eq(winner_1[1], UInt<1>(0h0))
node _T_48 = or(_T_46, _T_47)
node _T_49 = eq(prefixOR_2, UInt<1>(0h0))
node _T_50 = eq(winner_1[2], UInt<1>(0h0))
node _T_51 = or(_T_49, _T_50)
node _T_52 = and(_T_45, _T_48)
node _T_53 = and(_T_52, _T_51)
node _T_54 = asUInt(reset)
node _T_55 = eq(_T_54, UInt<1>(0h0))
when _T_55 :
node _T_56 = eq(_T_53, UInt<1>(0h0))
when _T_56 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_4
assert(clock, _T_53, UInt<1>(0h1), "") : assert_4
node _T_57 = or(d_d.valid, q.io.deq.valid)
node _T_58 = or(_T_57, q_1.io.deq.valid)
node _T_59 = eq(_T_58, UInt<1>(0h0))
node _T_60 = or(winner_1[0], winner_1[1])
node _T_61 = or(_T_60, winner_1[2])
node _T_62 = or(_T_59, _T_61)
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node maskedBeats_0_1 = mux(winner_1[0], _T_42, UInt<1>(0h0))
node maskedBeats_1_1 = mux(winner_1[1], UInt<1>(0h0), UInt<1>(0h0))
node maskedBeats_2 = mux(winner_1[2], UInt<1>(0h0), UInt<1>(0h0))
node _initBeats_T = or(maskedBeats_0_1, maskedBeats_1_1)
node initBeats_1 = or(_initBeats_T, maskedBeats_2)
node _beatsLeft_T_4 = and(in_d.ready, in_d.valid)
node _beatsLeft_T_5 = sub(beatsLeft_1, _beatsLeft_T_4)
node _beatsLeft_T_6 = tail(_beatsLeft_T_5, 1)
node _beatsLeft_T_7 = mux(latch_1, initBeats_1, _beatsLeft_T_6)
connect beatsLeft_1, _beatsLeft_T_7
wire _state_WIRE_1 : UInt<1>[3]
connect _state_WIRE_1[0], UInt<1>(0h0)
connect _state_WIRE_1[1], UInt<1>(0h0)
connect _state_WIRE_1[2], UInt<1>(0h0)
regreset state_1 : UInt<1>[3], clock, reset, _state_WIRE_1
node muxState_1 = mux(idle_1, winner_1, state_1)
connect state_1, muxState_1
node allowed_1 = mux(idle_1, readys_1, state_1)
node _d_d_ready_T = and(in_d.ready, allowed_1[0])
connect d_d.ready, _d_d_ready_T
node _q_io_deq_ready_T = and(in_d.ready, allowed_1[1])
connect q.io.deq.ready, _q_io_deq_ready_T
node _q_io_deq_ready_T_1 = and(in_d.ready, allowed_1[2])
connect q_1.io.deq.ready, _q_io_deq_ready_T_1
node _in_d_valid_T = or(d_d.valid, q.io.deq.valid)
node _in_d_valid_T_1 = or(_in_d_valid_T, q_1.io.deq.valid)
node _in_d_valid_T_2 = mux(state_1[0], d_d.valid, UInt<1>(0h0))
node _in_d_valid_T_3 = mux(state_1[1], q.io.deq.valid, UInt<1>(0h0))
node _in_d_valid_T_4 = mux(state_1[2], q_1.io.deq.valid, UInt<1>(0h0))
node _in_d_valid_T_5 = or(_in_d_valid_T_2, _in_d_valid_T_3)
node _in_d_valid_T_6 = or(_in_d_valid_T_5, _in_d_valid_T_4)
wire _in_d_valid_WIRE : UInt<1>
connect _in_d_valid_WIRE, _in_d_valid_T_6
node _in_d_valid_T_7 = mux(idle_1, _in_d_valid_T_1, _in_d_valid_WIRE)
connect in_d.valid, _in_d_valid_T_7
wire _in_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_d_bits_T = mux(muxState_1[0], d_d.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_1 = mux(muxState_1[1], q.io.deq.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_2 = mux(muxState_1[2], q_1.io.deq.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_3 = or(_in_d_bits_T, _in_d_bits_T_1)
node _in_d_bits_T_4 = or(_in_d_bits_T_3, _in_d_bits_T_2)
wire _in_d_bits_WIRE_1 : UInt<1>
connect _in_d_bits_WIRE_1, _in_d_bits_T_4
connect _in_d_bits_WIRE.corrupt, _in_d_bits_WIRE_1
node _in_d_bits_T_5 = mux(muxState_1[0], d_d.bits.data, UInt<1>(0h0))
node _in_d_bits_T_6 = mux(muxState_1[1], q.io.deq.bits.data, UInt<1>(0h0))
node _in_d_bits_T_7 = mux(muxState_1[2], q_1.io.deq.bits.data, UInt<1>(0h0))
node _in_d_bits_T_8 = or(_in_d_bits_T_5, _in_d_bits_T_6)
node _in_d_bits_T_9 = or(_in_d_bits_T_8, _in_d_bits_T_7)
wire _in_d_bits_WIRE_2 : UInt<64>
connect _in_d_bits_WIRE_2, _in_d_bits_T_9
connect _in_d_bits_WIRE.data, _in_d_bits_WIRE_2
wire _in_d_bits_WIRE_3 : { }
connect _in_d_bits_WIRE.echo, _in_d_bits_WIRE_3
wire _in_d_bits_WIRE_4 : { }
connect _in_d_bits_WIRE.user, _in_d_bits_WIRE_4
node _in_d_bits_T_10 = mux(muxState_1[0], d_d.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_11 = mux(muxState_1[1], q.io.deq.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_12 = mux(muxState_1[2], q_1.io.deq.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_13 = or(_in_d_bits_T_10, _in_d_bits_T_11)
node _in_d_bits_T_14 = or(_in_d_bits_T_13, _in_d_bits_T_12)
wire _in_d_bits_WIRE_5 : UInt<1>
connect _in_d_bits_WIRE_5, _in_d_bits_T_14
connect _in_d_bits_WIRE.denied, _in_d_bits_WIRE_5
node _in_d_bits_T_15 = mux(muxState_1[0], d_d.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_16 = mux(muxState_1[1], q.io.deq.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_17 = mux(muxState_1[2], q_1.io.deq.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_18 = or(_in_d_bits_T_15, _in_d_bits_T_16)
node _in_d_bits_T_19 = or(_in_d_bits_T_18, _in_d_bits_T_17)
wire _in_d_bits_WIRE_6 : UInt<3>
connect _in_d_bits_WIRE_6, _in_d_bits_T_19
connect _in_d_bits_WIRE.sink, _in_d_bits_WIRE_6
node _in_d_bits_T_20 = mux(muxState_1[0], d_d.bits.source, UInt<1>(0h0))
node _in_d_bits_T_21 = mux(muxState_1[1], q.io.deq.bits.source, UInt<1>(0h0))
node _in_d_bits_T_22 = mux(muxState_1[2], q_1.io.deq.bits.source, UInt<1>(0h0))
node _in_d_bits_T_23 = or(_in_d_bits_T_20, _in_d_bits_T_21)
node _in_d_bits_T_24 = or(_in_d_bits_T_23, _in_d_bits_T_22)
wire _in_d_bits_WIRE_7 : UInt<4>
connect _in_d_bits_WIRE_7, _in_d_bits_T_24
connect _in_d_bits_WIRE.source, _in_d_bits_WIRE_7
node _in_d_bits_T_25 = mux(muxState_1[0], d_d.bits.size, UInt<1>(0h0))
node _in_d_bits_T_26 = mux(muxState_1[1], q.io.deq.bits.size, UInt<1>(0h0))
node _in_d_bits_T_27 = mux(muxState_1[2], q_1.io.deq.bits.size, UInt<1>(0h0))
node _in_d_bits_T_28 = or(_in_d_bits_T_25, _in_d_bits_T_26)
node _in_d_bits_T_29 = or(_in_d_bits_T_28, _in_d_bits_T_27)
wire _in_d_bits_WIRE_8 : UInt<3>
connect _in_d_bits_WIRE_8, _in_d_bits_T_29
connect _in_d_bits_WIRE.size, _in_d_bits_WIRE_8
node _in_d_bits_T_30 = mux(muxState_1[0], d_d.bits.param, UInt<1>(0h0))
node _in_d_bits_T_31 = mux(muxState_1[1], q.io.deq.bits.param, UInt<1>(0h0))
node _in_d_bits_T_32 = mux(muxState_1[2], q_1.io.deq.bits.param, UInt<1>(0h0))
node _in_d_bits_T_33 = or(_in_d_bits_T_30, _in_d_bits_T_31)
node _in_d_bits_T_34 = or(_in_d_bits_T_33, _in_d_bits_T_32)
wire _in_d_bits_WIRE_9 : UInt<2>
connect _in_d_bits_WIRE_9, _in_d_bits_T_34
connect _in_d_bits_WIRE.param, _in_d_bits_WIRE_9
node _in_d_bits_T_35 = mux(muxState_1[0], d_d.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_36 = mux(muxState_1[1], q.io.deq.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_37 = mux(muxState_1[2], q_1.io.deq.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_38 = or(_in_d_bits_T_35, _in_d_bits_T_36)
node _in_d_bits_T_39 = or(_in_d_bits_T_38, _in_d_bits_T_37)
wire _in_d_bits_WIRE_10 : UInt<3>
connect _in_d_bits_WIRE_10, _in_d_bits_T_39
connect _in_d_bits_WIRE.opcode, _in_d_bits_WIRE_10
connect in_d.bits.corrupt, _in_d_bits_WIRE.corrupt
connect in_d.bits.data, _in_d_bits_WIRE.data
connect in_d.bits.denied, _in_d_bits_WIRE.denied
connect in_d.bits.sink, _in_d_bits_WIRE.sink
connect in_d.bits.source, _in_d_bits_WIRE.source
connect in_d.bits.size, _in_d_bits_WIRE.size
connect in_d.bits.param, _in_d_bits_WIRE.param
connect in_d.bits.opcode, _in_d_bits_WIRE.opcode
connect nodeIn.b.valid, UInt<1>(0h0)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.address, UInt<32>(0h0)
connect _WIRE_4.bits.source, UInt<5>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<3>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.valid, UInt<1>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_6.bits.sink, UInt<1>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.valid, UInt<1>(0h0)
wire a_a_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
wire a_d_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _isPut_T_2 = eq(nodeIn_1.a.bits.opcode, UInt<1>(0h0))
node _isPut_T_3 = eq(nodeIn_1.a.bits.opcode, UInt<1>(0h1))
node isPut_1 = or(_isPut_T_2, _isPut_T_3)
node _toD_T_4 = eq(nodeIn_1.a.bits.opcode, UInt<3>(0h6))
node _toD_T_5 = eq(nodeIn_1.a.bits.param, UInt<2>(0h2))
node _toD_T_6 = and(_toD_T_4, _toD_T_5)
node _toD_T_7 = eq(nodeIn_1.a.bits.opcode, UInt<3>(0h7))
node toD_1 = or(_toD_T_6, _toD_T_7)
node _nodeIn_a_ready_T_1 = mux(toD_1, a_d_1.ready, a_a_1.ready)
connect nodeIn_1.a.ready, _nodeIn_a_ready_T_1
node _a_a_valid_T_2 = eq(toD_1, UInt<1>(0h0))
node _a_a_valid_T_3 = and(nodeIn_1.a.valid, _a_a_valid_T_2)
connect a_a_1.valid, _a_a_valid_T_3
connect a_a_1.bits, nodeIn_1.a.bits
node _a_a_bits_source_T_5 = shl(nodeIn_1.a.bits.source, 1)
node _a_a_bits_source_T_6 = mux(isPut_1, UInt<1>(0h1), UInt<1>(0h0))
node _a_a_bits_source_T_7 = or(_a_a_bits_source_T_5, _a_a_bits_source_T_6)
connect a_a_1.bits.source, _a_a_bits_source_T_7
node _T_66 = eq(nodeIn_1.a.bits.opcode, UInt<3>(0h6))
node _T_67 = eq(nodeIn_1.a.bits.opcode, UInt<3>(0h7))
node _T_68 = or(_T_66, _T_67)
when _T_68 :
connect a_a_1.bits.opcode, UInt<3>(0h4)
connect a_a_1.bits.param, UInt<1>(0h0)
node _a_a_bits_source_T_8 = shl(nodeIn_1.a.bits.source, 1)
node _a_a_bits_source_T_9 = or(_a_a_bits_source_T_8, UInt<1>(0h1))
connect a_a_1.bits.source, _a_a_bits_source_T_9
node _a_d_valid_T_1 = and(nodeIn_1.a.valid, toD_1)
connect a_d_1.valid, _a_d_valid_T_1
wire a_d_bits_d_1 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect a_d_bits_d_1.opcode, UInt<3>(0h4)
connect a_d_bits_d_1.param, UInt<2>(0h0)
connect a_d_bits_d_1.size, nodeIn_1.a.bits.size
connect a_d_bits_d_1.source, nodeIn_1.a.bits.source
connect a_d_bits_d_1.sink, UInt<1>(0h0)
connect a_d_bits_d_1.denied, UInt<1>(0h0)
invalidate a_d_bits_d_1.data
connect a_d_bits_d_1.corrupt, UInt<1>(0h0)
connect a_d_1.bits.corrupt, a_d_bits_d_1.corrupt
connect a_d_1.bits.data, a_d_bits_d_1.data
connect a_d_1.bits.denied, a_d_bits_d_1.denied
connect a_d_1.bits.sink, a_d_bits_d_1.sink
connect a_d_1.bits.source, a_d_bits_d_1.source
connect a_d_1.bits.size, a_d_bits_d_1.size
connect a_d_1.bits.param, a_d_bits_d_1.param
connect a_d_1.bits.opcode, a_d_bits_d_1.opcode
wire c_a_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
node _c_a_valid_T_2 = eq(nodeIn_1.c.bits.opcode, UInt<3>(0h7))
node _c_a_valid_T_3 = and(nodeIn_1.c.valid, _c_a_valid_T_2)
connect c_a_1.valid, _c_a_valid_T_3
node _c_a_bits_T_1 = shl(nodeIn_1.c.bits.source, 1)
node _c_a_bits_legal_T_10 = leq(UInt<1>(0h0), nodeIn_1.c.bits.size)
node _c_a_bits_legal_T_11 = leq(nodeIn_1.c.bits.size, UInt<3>(0h6))
node _c_a_bits_legal_T_12 = and(_c_a_bits_legal_T_10, _c_a_bits_legal_T_11)
node _c_a_bits_legal_T_13 = or(UInt<1>(0h0), _c_a_bits_legal_T_12)
node _c_a_bits_legal_T_14 = xor(nodeIn_1.c.bits.address, UInt<1>(0h0))
node _c_a_bits_legal_T_15 = cvt(_c_a_bits_legal_T_14)
node _c_a_bits_legal_T_16 = and(_c_a_bits_legal_T_15, asSInt(UInt<1>(0h0)))
node _c_a_bits_legal_T_17 = asSInt(_c_a_bits_legal_T_16)
node _c_a_bits_legal_T_18 = eq(_c_a_bits_legal_T_17, asSInt(UInt<1>(0h0)))
node _c_a_bits_legal_T_19 = and(_c_a_bits_legal_T_13, _c_a_bits_legal_T_18)
node c_a_bits_legal_1 = or(UInt<1>(0h0), _c_a_bits_legal_T_19)
wire c_a_bits_a_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect c_a_bits_a_1.opcode, UInt<1>(0h0)
connect c_a_bits_a_1.param, UInt<1>(0h0)
connect c_a_bits_a_1.size, nodeIn_1.c.bits.size
connect c_a_bits_a_1.source, _c_a_bits_T_1
connect c_a_bits_a_1.address, nodeIn_1.c.bits.address
node _c_a_bits_a_mask_sizeOH_T_3 = or(nodeIn_1.c.bits.size, UInt<3>(0h0))
node c_a_bits_a_mask_sizeOH_shiftAmount_1 = bits(_c_a_bits_a_mask_sizeOH_T_3, 1, 0)
node _c_a_bits_a_mask_sizeOH_T_4 = dshl(UInt<1>(0h1), c_a_bits_a_mask_sizeOH_shiftAmount_1)
node _c_a_bits_a_mask_sizeOH_T_5 = bits(_c_a_bits_a_mask_sizeOH_T_4, 2, 0)
node c_a_bits_a_mask_sizeOH_1 = or(_c_a_bits_a_mask_sizeOH_T_5, UInt<1>(0h1))
node c_a_bits_a_mask_sub_sub_sub_0_1_1 = geq(nodeIn_1.c.bits.size, UInt<2>(0h3))
node c_a_bits_a_mask_sub_sub_size_1 = bits(c_a_bits_a_mask_sizeOH_1, 2, 2)
node c_a_bits_a_mask_sub_sub_bit_1 = bits(nodeIn_1.c.bits.address, 2, 2)
node c_a_bits_a_mask_sub_sub_nbit_1 = eq(c_a_bits_a_mask_sub_sub_bit_1, UInt<1>(0h0))
node c_a_bits_a_mask_sub_sub_0_2_1 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_nbit_1)
node _c_a_bits_a_mask_sub_sub_acc_T_2 = and(c_a_bits_a_mask_sub_sub_size_1, c_a_bits_a_mask_sub_sub_0_2_1)
node c_a_bits_a_mask_sub_sub_0_1_1 = or(c_a_bits_a_mask_sub_sub_sub_0_1_1, _c_a_bits_a_mask_sub_sub_acc_T_2)
node c_a_bits_a_mask_sub_sub_1_2_1 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_bit_1)
node _c_a_bits_a_mask_sub_sub_acc_T_3 = and(c_a_bits_a_mask_sub_sub_size_1, c_a_bits_a_mask_sub_sub_1_2_1)
node c_a_bits_a_mask_sub_sub_1_1_1 = or(c_a_bits_a_mask_sub_sub_sub_0_1_1, _c_a_bits_a_mask_sub_sub_acc_T_3)
node c_a_bits_a_mask_sub_size_1 = bits(c_a_bits_a_mask_sizeOH_1, 1, 1)
node c_a_bits_a_mask_sub_bit_1 = bits(nodeIn_1.c.bits.address, 1, 1)
node c_a_bits_a_mask_sub_nbit_1 = eq(c_a_bits_a_mask_sub_bit_1, UInt<1>(0h0))
node c_a_bits_a_mask_sub_0_2_1 = and(c_a_bits_a_mask_sub_sub_0_2_1, c_a_bits_a_mask_sub_nbit_1)
node _c_a_bits_a_mask_sub_acc_T_4 = and(c_a_bits_a_mask_sub_size_1, c_a_bits_a_mask_sub_0_2_1)
node c_a_bits_a_mask_sub_0_1_1 = or(c_a_bits_a_mask_sub_sub_0_1_1, _c_a_bits_a_mask_sub_acc_T_4)
node c_a_bits_a_mask_sub_1_2_1 = and(c_a_bits_a_mask_sub_sub_0_2_1, c_a_bits_a_mask_sub_bit_1)
node _c_a_bits_a_mask_sub_acc_T_5 = and(c_a_bits_a_mask_sub_size_1, c_a_bits_a_mask_sub_1_2_1)
node c_a_bits_a_mask_sub_1_1_1 = or(c_a_bits_a_mask_sub_sub_0_1_1, _c_a_bits_a_mask_sub_acc_T_5)
node c_a_bits_a_mask_sub_2_2_1 = and(c_a_bits_a_mask_sub_sub_1_2_1, c_a_bits_a_mask_sub_nbit_1)
node _c_a_bits_a_mask_sub_acc_T_6 = and(c_a_bits_a_mask_sub_size_1, c_a_bits_a_mask_sub_2_2_1)
node c_a_bits_a_mask_sub_2_1_1 = or(c_a_bits_a_mask_sub_sub_1_1_1, _c_a_bits_a_mask_sub_acc_T_6)
node c_a_bits_a_mask_sub_3_2_1 = and(c_a_bits_a_mask_sub_sub_1_2_1, c_a_bits_a_mask_sub_bit_1)
node _c_a_bits_a_mask_sub_acc_T_7 = and(c_a_bits_a_mask_sub_size_1, c_a_bits_a_mask_sub_3_2_1)
node c_a_bits_a_mask_sub_3_1_1 = or(c_a_bits_a_mask_sub_sub_1_1_1, _c_a_bits_a_mask_sub_acc_T_7)
node c_a_bits_a_mask_size_1 = bits(c_a_bits_a_mask_sizeOH_1, 0, 0)
node c_a_bits_a_mask_bit_1 = bits(nodeIn_1.c.bits.address, 0, 0)
node c_a_bits_a_mask_nbit_1 = eq(c_a_bits_a_mask_bit_1, UInt<1>(0h0))
node c_a_bits_a_mask_eq_8 = and(c_a_bits_a_mask_sub_0_2_1, c_a_bits_a_mask_nbit_1)
node _c_a_bits_a_mask_acc_T_8 = and(c_a_bits_a_mask_size_1, c_a_bits_a_mask_eq_8)
node c_a_bits_a_mask_acc_8 = or(c_a_bits_a_mask_sub_0_1_1, _c_a_bits_a_mask_acc_T_8)
node c_a_bits_a_mask_eq_9 = and(c_a_bits_a_mask_sub_0_2_1, c_a_bits_a_mask_bit_1)
node _c_a_bits_a_mask_acc_T_9 = and(c_a_bits_a_mask_size_1, c_a_bits_a_mask_eq_9)
node c_a_bits_a_mask_acc_9 = or(c_a_bits_a_mask_sub_0_1_1, _c_a_bits_a_mask_acc_T_9)
node c_a_bits_a_mask_eq_10 = and(c_a_bits_a_mask_sub_1_2_1, c_a_bits_a_mask_nbit_1)
node _c_a_bits_a_mask_acc_T_10 = and(c_a_bits_a_mask_size_1, c_a_bits_a_mask_eq_10)
node c_a_bits_a_mask_acc_10 = or(c_a_bits_a_mask_sub_1_1_1, _c_a_bits_a_mask_acc_T_10)
node c_a_bits_a_mask_eq_11 = and(c_a_bits_a_mask_sub_1_2_1, c_a_bits_a_mask_bit_1)
node _c_a_bits_a_mask_acc_T_11 = and(c_a_bits_a_mask_size_1, c_a_bits_a_mask_eq_11)
node c_a_bits_a_mask_acc_11 = or(c_a_bits_a_mask_sub_1_1_1, _c_a_bits_a_mask_acc_T_11)
node c_a_bits_a_mask_eq_12 = and(c_a_bits_a_mask_sub_2_2_1, c_a_bits_a_mask_nbit_1)
node _c_a_bits_a_mask_acc_T_12 = and(c_a_bits_a_mask_size_1, c_a_bits_a_mask_eq_12)
node c_a_bits_a_mask_acc_12 = or(c_a_bits_a_mask_sub_2_1_1, _c_a_bits_a_mask_acc_T_12)
node c_a_bits_a_mask_eq_13 = and(c_a_bits_a_mask_sub_2_2_1, c_a_bits_a_mask_bit_1)
node _c_a_bits_a_mask_acc_T_13 = and(c_a_bits_a_mask_size_1, c_a_bits_a_mask_eq_13)
node c_a_bits_a_mask_acc_13 = or(c_a_bits_a_mask_sub_2_1_1, _c_a_bits_a_mask_acc_T_13)
node c_a_bits_a_mask_eq_14 = and(c_a_bits_a_mask_sub_3_2_1, c_a_bits_a_mask_nbit_1)
node _c_a_bits_a_mask_acc_T_14 = and(c_a_bits_a_mask_size_1, c_a_bits_a_mask_eq_14)
node c_a_bits_a_mask_acc_14 = or(c_a_bits_a_mask_sub_3_1_1, _c_a_bits_a_mask_acc_T_14)
node c_a_bits_a_mask_eq_15 = and(c_a_bits_a_mask_sub_3_2_1, c_a_bits_a_mask_bit_1)
node _c_a_bits_a_mask_acc_T_15 = and(c_a_bits_a_mask_size_1, c_a_bits_a_mask_eq_15)
node c_a_bits_a_mask_acc_15 = or(c_a_bits_a_mask_sub_3_1_1, _c_a_bits_a_mask_acc_T_15)
node c_a_bits_a_mask_lo_lo_1 = cat(c_a_bits_a_mask_acc_9, c_a_bits_a_mask_acc_8)
node c_a_bits_a_mask_lo_hi_1 = cat(c_a_bits_a_mask_acc_11, c_a_bits_a_mask_acc_10)
node c_a_bits_a_mask_lo_1 = cat(c_a_bits_a_mask_lo_hi_1, c_a_bits_a_mask_lo_lo_1)
node c_a_bits_a_mask_hi_lo_1 = cat(c_a_bits_a_mask_acc_13, c_a_bits_a_mask_acc_12)
node c_a_bits_a_mask_hi_hi_1 = cat(c_a_bits_a_mask_acc_15, c_a_bits_a_mask_acc_14)
node c_a_bits_a_mask_hi_1 = cat(c_a_bits_a_mask_hi_hi_1, c_a_bits_a_mask_hi_lo_1)
node _c_a_bits_a_mask_T_1 = cat(c_a_bits_a_mask_hi_1, c_a_bits_a_mask_lo_1)
connect c_a_bits_a_1.mask, _c_a_bits_a_mask_T_1
connect c_a_bits_a_1.data, nodeIn_1.c.bits.data
connect c_a_bits_a_1.corrupt, nodeIn_1.c.bits.corrupt
connect c_a_1.bits, c_a_bits_a_1
wire c_d_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _c_d_valid_T_2 = eq(nodeIn_1.c.bits.opcode, UInt<3>(0h6))
node _c_d_valid_T_3 = and(nodeIn_1.c.valid, _c_d_valid_T_2)
connect c_d_1.valid, _c_d_valid_T_3
wire c_d_bits_d_1 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect c_d_bits_d_1.opcode, UInt<3>(0h6)
connect c_d_bits_d_1.param, UInt<1>(0h0)
connect c_d_bits_d_1.size, nodeIn_1.c.bits.size
connect c_d_bits_d_1.source, nodeIn_1.c.bits.source
connect c_d_bits_d_1.sink, UInt<1>(0h0)
connect c_d_bits_d_1.denied, UInt<1>(0h0)
invalidate c_d_bits_d_1.data
connect c_d_bits_d_1.corrupt, UInt<1>(0h0)
connect c_d_1.bits.corrupt, c_d_bits_d_1.corrupt
connect c_d_1.bits.data, c_d_bits_d_1.data
connect c_d_1.bits.denied, c_d_bits_d_1.denied
connect c_d_1.bits.sink, c_d_bits_d_1.sink
connect c_d_1.bits.source, c_d_bits_d_1.source
connect c_d_1.bits.size, c_d_bits_d_1.size
connect c_d_1.bits.param, c_d_bits_d_1.param
connect c_d_1.bits.opcode, c_d_bits_d_1.opcode
node _T_69 = eq(nodeIn_1.c.valid, UInt<1>(0h0))
node _T_70 = eq(nodeIn_1.c.bits.opcode, UInt<3>(0h6))
node _T_71 = or(_T_69, _T_70)
node _T_72 = eq(nodeIn_1.c.bits.opcode, UInt<3>(0h7))
node _T_73 = or(_T_71, _T_72)
node _T_74 = asUInt(reset)
node _T_75 = eq(_T_74, UInt<1>(0h0))
when _T_75 :
node _T_76 = eq(_T_73, UInt<1>(0h0))
when _T_76 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:116 assert (!in.c.valid || in.c.bits.opcode === Release || in.c.bits.opcode === ReleaseData)\n") : printf_6
assert(clock, _T_73, UInt<1>(0h1), "") : assert_6
node _nodeIn_c_ready_T_2 = eq(nodeIn_1.c.bits.opcode, UInt<3>(0h6))
node _nodeIn_c_ready_T_3 = mux(_nodeIn_c_ready_T_2, c_d_1.ready, c_a_1.ready)
connect nodeIn_1.c.ready, _nodeIn_c_ready_T_3
connect nodeIn_1.e.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.mask, UInt<8>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<2>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.ready, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.mask, UInt<8>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<5>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<2>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_77 = eq(_WIRE_11.valid, UInt<1>(0h0))
node _T_78 = asUInt(reset)
node _T_79 = eq(_T_78, UInt<1>(0h0))
when _T_79 :
node _T_80 = eq(_T_77, UInt<1>(0h0))
when _T_80 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:124 assert (!out.b.valid)\n") : printf_7
assert(clock, _T_77, UInt<1>(0h1), "") : assert_7
inst pool_1 of IDPool_1
connect pool_1.clock, clock
connect pool_1.reset, reset
node _pool_io_free_valid_T_1 = and(nodeIn_1.e.ready, nodeIn_1.e.valid)
connect pool_1.io.free.valid, _pool_io_free_valid_T_1
connect pool_1.io.free.bits, nodeIn_1.e.bits.sink
wire in_d_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _d_first_T_1 = and(in_d_1.ready, in_d_1.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), in_d_1.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(in_d_1.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
node _d_grant_T_2 = eq(in_d_1.bits.opcode, UInt<3>(0h5))
node _d_grant_T_3 = eq(in_d_1.bits.opcode, UInt<3>(0h4))
node d_grant_1 = or(_d_grant_T_2, _d_grant_T_3)
node _pool_io_alloc_ready_T_3 = and(nodeIn_1.d.ready, nodeIn_1.d.valid)
node _pool_io_alloc_ready_T_4 = and(_pool_io_alloc_ready_T_3, d_first_1)
node _pool_io_alloc_ready_T_5 = and(_pool_io_alloc_ready_T_4, d_grant_1)
connect pool_1.io.alloc.ready, _pool_io_alloc_ready_T_5
node _nodeIn_d_valid_T_5 = eq(d_first_1, UInt<1>(0h0))
node _nodeIn_d_valid_T_6 = or(pool_1.io.alloc.valid, _nodeIn_d_valid_T_5)
node _nodeIn_d_valid_T_7 = eq(d_grant_1, UInt<1>(0h0))
node _nodeIn_d_valid_T_8 = or(_nodeIn_d_valid_T_6, _nodeIn_d_valid_T_7)
node _nodeIn_d_valid_T_9 = and(in_d_1.valid, _nodeIn_d_valid_T_8)
connect nodeIn_1.d.valid, _nodeIn_d_valid_T_9
node _in_d_ready_T_5 = eq(d_first_1, UInt<1>(0h0))
node _in_d_ready_T_6 = or(pool_1.io.alloc.valid, _in_d_ready_T_5)
node _in_d_ready_T_7 = eq(d_grant_1, UInt<1>(0h0))
node _in_d_ready_T_8 = or(_in_d_ready_T_6, _in_d_ready_T_7)
node _in_d_ready_T_9 = and(nodeIn_1.d.ready, _in_d_ready_T_8)
connect in_d_1.ready, _in_d_ready_T_9
connect nodeIn_1.d.bits.corrupt, in_d_1.bits.corrupt
connect nodeIn_1.d.bits.data, in_d_1.bits.data
connect nodeIn_1.d.bits.denied, in_d_1.bits.denied
connect nodeIn_1.d.bits.sink, in_d_1.bits.sink
connect nodeIn_1.d.bits.source, in_d_1.bits.source
connect nodeIn_1.d.bits.size, in_d_1.bits.size
connect nodeIn_1.d.bits.param, in_d_1.bits.param
connect nodeIn_1.d.bits.opcode, in_d_1.bits.opcode
reg nodeIn_d_bits_sink_r_1 : UInt<3>, clock
when d_first_1 :
connect nodeIn_d_bits_sink_r_1, pool_1.io.alloc.bits
node _nodeIn_d_bits_sink_T_1 = mux(d_first_1, pool_1.io.alloc.bits, nodeIn_d_bits_sink_r_1)
connect nodeIn_1.d.bits.sink, _nodeIn_d_bits_sink_T_1
wire d_d_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect d_d_1, x1_nodeOut.d
node _d_d_bits_source_T_1 = shr(x1_nodeOut.d.bits.source, 1)
connect d_d_1.bits.source, _d_d_bits_source_T_1
reg wSourceVec_1 : UInt<1>[10], clock
node _aWOk_T_5 = xor(nodeIn_1.a.bits.address, UInt<1>(0h0))
node _aWOk_T_6 = cvt(_aWOk_T_5)
node _aWOk_T_7 = and(_aWOk_T_6, asSInt(UInt<1>(0h0)))
node _aWOk_T_8 = asSInt(_aWOk_T_7)
node _aWOk_T_9 = eq(_aWOk_T_8, asSInt(UInt<1>(0h0)))
node _bypass_T_2 = and(UInt<1>(0h0), nodeIn_1.a.valid)
node _bypass_T_3 = eq(nodeIn_1.a.bits.source, d_d_1.bits.source)
node bypass_1 = and(_bypass_T_2, _bypass_T_3)
node _dWHeld_T_1 = mux(bypass_1, UInt<1>(0h1), wSourceVec_1[d_d_1.bits.source])
reg dWHeld_r_1 : UInt<1>, clock
when d_first_1 :
connect dWHeld_r_1, _dWHeld_T_1
node dWHeld_1 = mux(d_first_1, _dWHeld_T_1, dWHeld_r_1)
node _T_81 = and(nodeIn_1.a.ready, nodeIn_1.a.valid)
when _T_81 :
connect wSourceVec_1[nodeIn_1.a.bits.source], UInt<1>(0h1)
node _T_82 = eq(x1_nodeOut.d.bits.opcode, UInt<1>(0h1))
node _T_83 = bits(x1_nodeOut.d.bits.source, 0, 0)
node _T_84 = and(_T_82, _T_83)
when _T_84 :
connect d_d_1.bits.opcode, UInt<3>(0h5)
node _d_d_bits_param_T_1 = mux(dWHeld_1, UInt<2>(0h0), UInt<2>(0h1))
connect d_d_1.bits.param, _d_d_bits_param_T_1
node _T_85 = eq(x1_nodeOut.d.bits.opcode, UInt<1>(0h0))
node _T_86 = bits(x1_nodeOut.d.bits.source, 0, 0)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = and(_T_85, _T_87)
when _T_88 :
connect d_d_1.bits.opcode, UInt<3>(0h6)
node _decode_T_9 = dshl(UInt<6>(0h3f), c_a_1.bits.size)
node _decode_T_10 = bits(_decode_T_9, 5, 0)
node _decode_T_11 = not(_decode_T_10)
node decode_3 = shr(_decode_T_11, 3)
node _opdata_T_2 = bits(c_a_1.bits.opcode, 2, 2)
node opdata_3 = eq(_opdata_T_2, UInt<1>(0h0))
node _T_89 = mux(opdata_3, decode_3, UInt<1>(0h0))
node _decode_T_12 = dshl(UInt<6>(0h3f), a_a_1.bits.size)
node _decode_T_13 = bits(_decode_T_12, 5, 0)
node _decode_T_14 = not(_decode_T_13)
node decode_4 = shr(_decode_T_14, 3)
node _opdata_T_3 = bits(a_a_1.bits.opcode, 2, 2)
node opdata_4 = eq(_opdata_T_3, UInt<1>(0h0))
node _T_90 = mux(opdata_4, decode_4, UInt<1>(0h0))
regreset beatsLeft_2 : UInt, clock, reset, UInt<1>(0h0)
node idle_2 = eq(beatsLeft_2, UInt<1>(0h0))
node latch_2 = and(idle_2, x1_nodeOut.a.ready)
node _readys_T_24 = cat(a_a_1.valid, c_a_1.valid)
node _readys_T_25 = shl(_readys_T_24, 1)
node _readys_T_26 = bits(_readys_T_25, 1, 0)
node _readys_T_27 = or(_readys_T_24, _readys_T_26)
node _readys_T_28 = bits(_readys_T_27, 1, 0)
node _readys_T_29 = shl(_readys_T_28, 1)
node _readys_T_30 = bits(_readys_T_29, 1, 0)
node _readys_T_31 = not(_readys_T_30)
node _readys_T_32 = bits(_readys_T_31, 0, 0)
node _readys_T_33 = bits(_readys_T_31, 1, 1)
wire readys_2 : UInt<1>[2]
connect readys_2[0], _readys_T_32
connect readys_2[1], _readys_T_33
node _winner_T_5 = and(readys_2[0], c_a_1.valid)
node _winner_T_6 = and(readys_2[1], a_a_1.valid)
wire winner_2 : UInt<1>[2]
connect winner_2[0], _winner_T_5
connect winner_2[1], _winner_T_6
node prefixOR_1_2 = or(UInt<1>(0h0), winner_2[0])
node _prefixOR_T_2 = or(prefixOR_1_2, winner_2[1])
node _T_91 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_92 = eq(winner_2[0], UInt<1>(0h0))
node _T_93 = or(_T_91, _T_92)
node _T_94 = eq(prefixOR_1_2, UInt<1>(0h0))
node _T_95 = eq(winner_2[1], UInt<1>(0h0))
node _T_96 = or(_T_94, _T_95)
node _T_97 = and(_T_93, _T_96)
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_8
assert(clock, _T_97, UInt<1>(0h1), "") : assert_8
node _T_101 = or(c_a_1.valid, a_a_1.valid)
node _T_102 = eq(_T_101, UInt<1>(0h0))
node _T_103 = or(winner_2[0], winner_2[1])
node _T_104 = or(_T_102, _T_103)
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_9
assert(clock, _T_104, UInt<1>(0h1), "") : assert_9
node maskedBeats_0_2 = mux(winner_2[0], _T_89, UInt<1>(0h0))
node maskedBeats_1_2 = mux(winner_2[1], _T_90, UInt<1>(0h0))
node initBeats_2 = or(maskedBeats_0_2, maskedBeats_1_2)
node _beatsLeft_T_8 = and(x1_nodeOut.a.ready, x1_nodeOut.a.valid)
node _beatsLeft_T_9 = sub(beatsLeft_2, _beatsLeft_T_8)
node _beatsLeft_T_10 = tail(_beatsLeft_T_9, 1)
node _beatsLeft_T_11 = mux(latch_2, initBeats_2, _beatsLeft_T_10)
connect beatsLeft_2, _beatsLeft_T_11
wire _state_WIRE_2 : UInt<1>[2]
connect _state_WIRE_2[0], UInt<1>(0h0)
connect _state_WIRE_2[1], UInt<1>(0h0)
regreset state_2 : UInt<1>[2], clock, reset, _state_WIRE_2
node muxState_2 = mux(idle_2, winner_2, state_2)
connect state_2, muxState_2
node allowed_2 = mux(idle_2, readys_2, state_2)
node _c_a_ready_T_1 = and(x1_nodeOut.a.ready, allowed_2[0])
connect c_a_1.ready, _c_a_ready_T_1
node _a_a_ready_T_1 = and(x1_nodeOut.a.ready, allowed_2[1])
connect a_a_1.ready, _a_a_ready_T_1
node _nodeOut_a_valid_T_5 = or(c_a_1.valid, a_a_1.valid)
node _nodeOut_a_valid_T_6 = mux(state_2[0], c_a_1.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_7 = mux(state_2[1], a_a_1.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_8 = or(_nodeOut_a_valid_T_6, _nodeOut_a_valid_T_7)
wire _nodeOut_a_valid_WIRE_1 : UInt<1>
connect _nodeOut_a_valid_WIRE_1, _nodeOut_a_valid_T_8
node _nodeOut_a_valid_T_9 = mux(idle_2, _nodeOut_a_valid_T_5, _nodeOut_a_valid_WIRE_1)
connect x1_nodeOut.a.valid, _nodeOut_a_valid_T_9
wire _nodeOut_a_bits_WIRE_11 : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _nodeOut_a_bits_T_24 = mux(muxState_2[0], c_a_1.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_25 = mux(muxState_2[1], a_a_1.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_26 = or(_nodeOut_a_bits_T_24, _nodeOut_a_bits_T_25)
wire _nodeOut_a_bits_WIRE_12 : UInt<1>
connect _nodeOut_a_bits_WIRE_12, _nodeOut_a_bits_T_26
connect _nodeOut_a_bits_WIRE_11.corrupt, _nodeOut_a_bits_WIRE_12
node _nodeOut_a_bits_T_27 = mux(muxState_2[0], c_a_1.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_28 = mux(muxState_2[1], a_a_1.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_29 = or(_nodeOut_a_bits_T_27, _nodeOut_a_bits_T_28)
wire _nodeOut_a_bits_WIRE_13 : UInt<64>
connect _nodeOut_a_bits_WIRE_13, _nodeOut_a_bits_T_29
connect _nodeOut_a_bits_WIRE_11.data, _nodeOut_a_bits_WIRE_13
node _nodeOut_a_bits_T_30 = mux(muxState_2[0], c_a_1.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_31 = mux(muxState_2[1], a_a_1.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_32 = or(_nodeOut_a_bits_T_30, _nodeOut_a_bits_T_31)
wire _nodeOut_a_bits_WIRE_14 : UInt<8>
connect _nodeOut_a_bits_WIRE_14, _nodeOut_a_bits_T_32
connect _nodeOut_a_bits_WIRE_11.mask, _nodeOut_a_bits_WIRE_14
wire _nodeOut_a_bits_WIRE_15 : { }
connect _nodeOut_a_bits_WIRE_11.echo, _nodeOut_a_bits_WIRE_15
wire _nodeOut_a_bits_WIRE_16 : { }
connect _nodeOut_a_bits_WIRE_11.user, _nodeOut_a_bits_WIRE_16
node _nodeOut_a_bits_T_33 = mux(muxState_2[0], c_a_1.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_34 = mux(muxState_2[1], a_a_1.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_35 = or(_nodeOut_a_bits_T_33, _nodeOut_a_bits_T_34)
wire _nodeOut_a_bits_WIRE_17 : UInt<32>
connect _nodeOut_a_bits_WIRE_17, _nodeOut_a_bits_T_35
connect _nodeOut_a_bits_WIRE_11.address, _nodeOut_a_bits_WIRE_17
node _nodeOut_a_bits_T_36 = mux(muxState_2[0], c_a_1.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_37 = mux(muxState_2[1], a_a_1.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_38 = or(_nodeOut_a_bits_T_36, _nodeOut_a_bits_T_37)
wire _nodeOut_a_bits_WIRE_18 : UInt<5>
connect _nodeOut_a_bits_WIRE_18, _nodeOut_a_bits_T_38
connect _nodeOut_a_bits_WIRE_11.source, _nodeOut_a_bits_WIRE_18
node _nodeOut_a_bits_T_39 = mux(muxState_2[0], c_a_1.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_40 = mux(muxState_2[1], a_a_1.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_41 = or(_nodeOut_a_bits_T_39, _nodeOut_a_bits_T_40)
wire _nodeOut_a_bits_WIRE_19 : UInt<3>
connect _nodeOut_a_bits_WIRE_19, _nodeOut_a_bits_T_41
connect _nodeOut_a_bits_WIRE_11.size, _nodeOut_a_bits_WIRE_19
node _nodeOut_a_bits_T_42 = mux(muxState_2[0], c_a_1.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_43 = mux(muxState_2[1], a_a_1.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_44 = or(_nodeOut_a_bits_T_42, _nodeOut_a_bits_T_43)
wire _nodeOut_a_bits_WIRE_20 : UInt<3>
connect _nodeOut_a_bits_WIRE_20, _nodeOut_a_bits_T_44
connect _nodeOut_a_bits_WIRE_11.param, _nodeOut_a_bits_WIRE_20
node _nodeOut_a_bits_T_45 = mux(muxState_2[0], c_a_1.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_46 = mux(muxState_2[1], a_a_1.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_47 = or(_nodeOut_a_bits_T_45, _nodeOut_a_bits_T_46)
wire _nodeOut_a_bits_WIRE_21 : UInt<3>
connect _nodeOut_a_bits_WIRE_21, _nodeOut_a_bits_T_47
connect _nodeOut_a_bits_WIRE_11.opcode, _nodeOut_a_bits_WIRE_21
connect x1_nodeOut.a.bits.corrupt, _nodeOut_a_bits_WIRE_11.corrupt
connect x1_nodeOut.a.bits.data, _nodeOut_a_bits_WIRE_11.data
connect x1_nodeOut.a.bits.mask, _nodeOut_a_bits_WIRE_11.mask
connect x1_nodeOut.a.bits.address, _nodeOut_a_bits_WIRE_11.address
connect x1_nodeOut.a.bits.source, _nodeOut_a_bits_WIRE_11.source
connect x1_nodeOut.a.bits.size, _nodeOut_a_bits_WIRE_11.size
connect x1_nodeOut.a.bits.param, _nodeOut_a_bits_WIRE_11.param
connect x1_nodeOut.a.bits.opcode, _nodeOut_a_bits_WIRE_11.opcode
node _decode_T_15 = dshl(UInt<6>(0h3f), d_d_1.bits.size)
node _decode_T_16 = bits(_decode_T_15, 5, 0)
node _decode_T_17 = not(_decode_T_16)
node decode_5 = shr(_decode_T_17, 3)
node opdata_5 = bits(d_d_1.bits.opcode, 0, 0)
node _T_108 = mux(opdata_5, decode_5, UInt<1>(0h0))
inst q_2 of Queue2_TLBundleD_a32d64s4k3z3c_10
connect q_2.clock, clock
connect q_2.reset, reset
connect q_2.io.enq.valid, c_d_1.valid
connect q_2.io.enq.bits.corrupt, c_d_1.bits.corrupt
connect q_2.io.enq.bits.data, c_d_1.bits.data
connect q_2.io.enq.bits.denied, c_d_1.bits.denied
connect q_2.io.enq.bits.sink, c_d_1.bits.sink
connect q_2.io.enq.bits.source, c_d_1.bits.source
connect q_2.io.enq.bits.size, c_d_1.bits.size
connect q_2.io.enq.bits.param, c_d_1.bits.param
connect q_2.io.enq.bits.opcode, c_d_1.bits.opcode
connect c_d_1.ready, q_2.io.enq.ready
inst q_3 of Queue2_TLBundleD_a32d64s4k3z3c_11
connect q_3.clock, clock
connect q_3.reset, reset
connect q_3.io.enq.valid, a_d_1.valid
connect q_3.io.enq.bits.corrupt, a_d_1.bits.corrupt
connect q_3.io.enq.bits.data, a_d_1.bits.data
connect q_3.io.enq.bits.denied, a_d_1.bits.denied
connect q_3.io.enq.bits.sink, a_d_1.bits.sink
connect q_3.io.enq.bits.source, a_d_1.bits.source
connect q_3.io.enq.bits.size, a_d_1.bits.size
connect q_3.io.enq.bits.param, a_d_1.bits.param
connect q_3.io.enq.bits.opcode, a_d_1.bits.opcode
connect a_d_1.ready, q_3.io.enq.ready
regreset beatsLeft_3 : UInt, clock, reset, UInt<1>(0h0)
node idle_3 = eq(beatsLeft_3, UInt<1>(0h0))
node latch_3 = and(idle_3, in_d_1.ready)
node readys_hi_1 = cat(q_3.io.deq.valid, q_2.io.deq.valid)
node _readys_T_34 = cat(readys_hi_1, d_d_1.valid)
node _readys_T_35 = shl(_readys_T_34, 1)
node _readys_T_36 = bits(_readys_T_35, 2, 0)
node _readys_T_37 = or(_readys_T_34, _readys_T_36)
node _readys_T_38 = shl(_readys_T_37, 2)
node _readys_T_39 = bits(_readys_T_38, 2, 0)
node _readys_T_40 = or(_readys_T_37, _readys_T_39)
node _readys_T_41 = bits(_readys_T_40, 2, 0)
node _readys_T_42 = shl(_readys_T_41, 1)
node _readys_T_43 = bits(_readys_T_42, 2, 0)
node _readys_T_44 = not(_readys_T_43)
node _readys_T_45 = bits(_readys_T_44, 0, 0)
node _readys_T_46 = bits(_readys_T_44, 1, 1)
node _readys_T_47 = bits(_readys_T_44, 2, 2)
wire readys_3 : UInt<1>[3]
connect readys_3[0], _readys_T_45
connect readys_3[1], _readys_T_46
connect readys_3[2], _readys_T_47
node _winner_T_7 = and(readys_3[0], d_d_1.valid)
node _winner_T_8 = and(readys_3[1], q_2.io.deq.valid)
node _winner_T_9 = and(readys_3[2], q_3.io.deq.valid)
wire winner_3 : UInt<1>[3]
connect winner_3[0], _winner_T_7
connect winner_3[1], _winner_T_8
connect winner_3[2], _winner_T_9
node prefixOR_1_3 = or(UInt<1>(0h0), winner_3[0])
node prefixOR_2_1 = or(prefixOR_1_3, winner_3[1])
node _prefixOR_T_3 = or(prefixOR_2_1, winner_3[2])
node _T_109 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_110 = eq(winner_3[0], UInt<1>(0h0))
node _T_111 = or(_T_109, _T_110)
node _T_112 = eq(prefixOR_1_3, UInt<1>(0h0))
node _T_113 = eq(winner_3[1], UInt<1>(0h0))
node _T_114 = or(_T_112, _T_113)
node _T_115 = eq(prefixOR_2_1, UInt<1>(0h0))
node _T_116 = eq(winner_3[2], UInt<1>(0h0))
node _T_117 = or(_T_115, _T_116)
node _T_118 = and(_T_111, _T_114)
node _T_119 = and(_T_118, _T_117)
node _T_120 = asUInt(reset)
node _T_121 = eq(_T_120, UInt<1>(0h0))
when _T_121 :
node _T_122 = eq(_T_119, UInt<1>(0h0))
when _T_122 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_10
assert(clock, _T_119, UInt<1>(0h1), "") : assert_10
node _T_123 = or(d_d_1.valid, q_2.io.deq.valid)
node _T_124 = or(_T_123, q_3.io.deq.valid)
node _T_125 = eq(_T_124, UInt<1>(0h0))
node _T_126 = or(winner_3[0], winner_3[1])
node _T_127 = or(_T_126, winner_3[2])
node _T_128 = or(_T_125, _T_127)
node _T_129 = asUInt(reset)
node _T_130 = eq(_T_129, UInt<1>(0h0))
when _T_130 :
node _T_131 = eq(_T_128, UInt<1>(0h0))
when _T_131 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_11
assert(clock, _T_128, UInt<1>(0h1), "") : assert_11
node maskedBeats_0_3 = mux(winner_3[0], _T_108, UInt<1>(0h0))
node maskedBeats_1_3 = mux(winner_3[1], UInt<1>(0h0), UInt<1>(0h0))
node maskedBeats_2_1 = mux(winner_3[2], UInt<1>(0h0), UInt<1>(0h0))
node _initBeats_T_1 = or(maskedBeats_0_3, maskedBeats_1_3)
node initBeats_3 = or(_initBeats_T_1, maskedBeats_2_1)
node _beatsLeft_T_12 = and(in_d_1.ready, in_d_1.valid)
node _beatsLeft_T_13 = sub(beatsLeft_3, _beatsLeft_T_12)
node _beatsLeft_T_14 = tail(_beatsLeft_T_13, 1)
node _beatsLeft_T_15 = mux(latch_3, initBeats_3, _beatsLeft_T_14)
connect beatsLeft_3, _beatsLeft_T_15
wire _state_WIRE_3 : UInt<1>[3]
connect _state_WIRE_3[0], UInt<1>(0h0)
connect _state_WIRE_3[1], UInt<1>(0h0)
connect _state_WIRE_3[2], UInt<1>(0h0)
regreset state_3 : UInt<1>[3], clock, reset, _state_WIRE_3
node muxState_3 = mux(idle_3, winner_3, state_3)
connect state_3, muxState_3
node allowed_3 = mux(idle_3, readys_3, state_3)
node _d_d_ready_T_1 = and(in_d_1.ready, allowed_3[0])
connect d_d_1.ready, _d_d_ready_T_1
node _q_io_deq_ready_T_2 = and(in_d_1.ready, allowed_3[1])
connect q_2.io.deq.ready, _q_io_deq_ready_T_2
node _q_io_deq_ready_T_3 = and(in_d_1.ready, allowed_3[2])
connect q_3.io.deq.ready, _q_io_deq_ready_T_3
node _in_d_valid_T_8 = or(d_d_1.valid, q_2.io.deq.valid)
node _in_d_valid_T_9 = or(_in_d_valid_T_8, q_3.io.deq.valid)
node _in_d_valid_T_10 = mux(state_3[0], d_d_1.valid, UInt<1>(0h0))
node _in_d_valid_T_11 = mux(state_3[1], q_2.io.deq.valid, UInt<1>(0h0))
node _in_d_valid_T_12 = mux(state_3[2], q_3.io.deq.valid, UInt<1>(0h0))
node _in_d_valid_T_13 = or(_in_d_valid_T_10, _in_d_valid_T_11)
node _in_d_valid_T_14 = or(_in_d_valid_T_13, _in_d_valid_T_12)
wire _in_d_valid_WIRE_1 : UInt<1>
connect _in_d_valid_WIRE_1, _in_d_valid_T_14
node _in_d_valid_T_15 = mux(idle_3, _in_d_valid_T_9, _in_d_valid_WIRE_1)
connect in_d_1.valid, _in_d_valid_T_15
wire _in_d_bits_WIRE_11 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_d_bits_T_40 = mux(muxState_3[0], d_d_1.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_41 = mux(muxState_3[1], q_2.io.deq.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_42 = mux(muxState_3[2], q_3.io.deq.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_43 = or(_in_d_bits_T_40, _in_d_bits_T_41)
node _in_d_bits_T_44 = or(_in_d_bits_T_43, _in_d_bits_T_42)
wire _in_d_bits_WIRE_12 : UInt<1>
connect _in_d_bits_WIRE_12, _in_d_bits_T_44
connect _in_d_bits_WIRE_11.corrupt, _in_d_bits_WIRE_12
node _in_d_bits_T_45 = mux(muxState_3[0], d_d_1.bits.data, UInt<1>(0h0))
node _in_d_bits_T_46 = mux(muxState_3[1], q_2.io.deq.bits.data, UInt<1>(0h0))
node _in_d_bits_T_47 = mux(muxState_3[2], q_3.io.deq.bits.data, UInt<1>(0h0))
node _in_d_bits_T_48 = or(_in_d_bits_T_45, _in_d_bits_T_46)
node _in_d_bits_T_49 = or(_in_d_bits_T_48, _in_d_bits_T_47)
wire _in_d_bits_WIRE_13 : UInt<64>
connect _in_d_bits_WIRE_13, _in_d_bits_T_49
connect _in_d_bits_WIRE_11.data, _in_d_bits_WIRE_13
wire _in_d_bits_WIRE_14 : { }
connect _in_d_bits_WIRE_11.echo, _in_d_bits_WIRE_14
wire _in_d_bits_WIRE_15 : { }
connect _in_d_bits_WIRE_11.user, _in_d_bits_WIRE_15
node _in_d_bits_T_50 = mux(muxState_3[0], d_d_1.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_51 = mux(muxState_3[1], q_2.io.deq.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_52 = mux(muxState_3[2], q_3.io.deq.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_53 = or(_in_d_bits_T_50, _in_d_bits_T_51)
node _in_d_bits_T_54 = or(_in_d_bits_T_53, _in_d_bits_T_52)
wire _in_d_bits_WIRE_16 : UInt<1>
connect _in_d_bits_WIRE_16, _in_d_bits_T_54
connect _in_d_bits_WIRE_11.denied, _in_d_bits_WIRE_16
node _in_d_bits_T_55 = mux(muxState_3[0], d_d_1.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_56 = mux(muxState_3[1], q_2.io.deq.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_57 = mux(muxState_3[2], q_3.io.deq.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_58 = or(_in_d_bits_T_55, _in_d_bits_T_56)
node _in_d_bits_T_59 = or(_in_d_bits_T_58, _in_d_bits_T_57)
wire _in_d_bits_WIRE_17 : UInt<3>
connect _in_d_bits_WIRE_17, _in_d_bits_T_59
connect _in_d_bits_WIRE_11.sink, _in_d_bits_WIRE_17
node _in_d_bits_T_60 = mux(muxState_3[0], d_d_1.bits.source, UInt<1>(0h0))
node _in_d_bits_T_61 = mux(muxState_3[1], q_2.io.deq.bits.source, UInt<1>(0h0))
node _in_d_bits_T_62 = mux(muxState_3[2], q_3.io.deq.bits.source, UInt<1>(0h0))
node _in_d_bits_T_63 = or(_in_d_bits_T_60, _in_d_bits_T_61)
node _in_d_bits_T_64 = or(_in_d_bits_T_63, _in_d_bits_T_62)
wire _in_d_bits_WIRE_18 : UInt<4>
connect _in_d_bits_WIRE_18, _in_d_bits_T_64
connect _in_d_bits_WIRE_11.source, _in_d_bits_WIRE_18
node _in_d_bits_T_65 = mux(muxState_3[0], d_d_1.bits.size, UInt<1>(0h0))
node _in_d_bits_T_66 = mux(muxState_3[1], q_2.io.deq.bits.size, UInt<1>(0h0))
node _in_d_bits_T_67 = mux(muxState_3[2], q_3.io.deq.bits.size, UInt<1>(0h0))
node _in_d_bits_T_68 = or(_in_d_bits_T_65, _in_d_bits_T_66)
node _in_d_bits_T_69 = or(_in_d_bits_T_68, _in_d_bits_T_67)
wire _in_d_bits_WIRE_19 : UInt<3>
connect _in_d_bits_WIRE_19, _in_d_bits_T_69
connect _in_d_bits_WIRE_11.size, _in_d_bits_WIRE_19
node _in_d_bits_T_70 = mux(muxState_3[0], d_d_1.bits.param, UInt<1>(0h0))
node _in_d_bits_T_71 = mux(muxState_3[1], q_2.io.deq.bits.param, UInt<1>(0h0))
node _in_d_bits_T_72 = mux(muxState_3[2], q_3.io.deq.bits.param, UInt<1>(0h0))
node _in_d_bits_T_73 = or(_in_d_bits_T_70, _in_d_bits_T_71)
node _in_d_bits_T_74 = or(_in_d_bits_T_73, _in_d_bits_T_72)
wire _in_d_bits_WIRE_20 : UInt<2>
connect _in_d_bits_WIRE_20, _in_d_bits_T_74
connect _in_d_bits_WIRE_11.param, _in_d_bits_WIRE_20
node _in_d_bits_T_75 = mux(muxState_3[0], d_d_1.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_76 = mux(muxState_3[1], q_2.io.deq.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_77 = mux(muxState_3[2], q_3.io.deq.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_78 = or(_in_d_bits_T_75, _in_d_bits_T_76)
node _in_d_bits_T_79 = or(_in_d_bits_T_78, _in_d_bits_T_77)
wire _in_d_bits_WIRE_21 : UInt<3>
connect _in_d_bits_WIRE_21, _in_d_bits_T_79
connect _in_d_bits_WIRE_11.opcode, _in_d_bits_WIRE_21
connect in_d_1.bits.corrupt, _in_d_bits_WIRE_11.corrupt
connect in_d_1.bits.data, _in_d_bits_WIRE_11.data
connect in_d_1.bits.denied, _in_d_bits_WIRE_11.denied
connect in_d_1.bits.sink, _in_d_bits_WIRE_11.sink
connect in_d_1.bits.source, _in_d_bits_WIRE_11.source
connect in_d_1.bits.size, _in_d_bits_WIRE_11.size
connect in_d_1.bits.param, _in_d_bits_WIRE_11.param
connect in_d_1.bits.opcode, _in_d_bits_WIRE_11.opcode
connect nodeIn_1.b.valid, UInt<1>(0h0)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<5>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
connect _WIRE_13.valid, UInt<1>(0h0)
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_14.bits.sink, UInt<1>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
connect _WIRE_15.valid, UInt<1>(0h0)
wire a_a_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
wire a_d_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _isPut_T_4 = eq(nodeIn_2.a.bits.opcode, UInt<1>(0h0))
node _isPut_T_5 = eq(nodeIn_2.a.bits.opcode, UInt<1>(0h1))
node isPut_2 = or(_isPut_T_4, _isPut_T_5)
node _toD_T_8 = eq(nodeIn_2.a.bits.opcode, UInt<3>(0h6))
node _toD_T_9 = eq(nodeIn_2.a.bits.param, UInt<2>(0h2))
node _toD_T_10 = and(_toD_T_8, _toD_T_9)
node _toD_T_11 = eq(nodeIn_2.a.bits.opcode, UInt<3>(0h7))
node toD_2 = or(_toD_T_10, _toD_T_11)
node _nodeIn_a_ready_T_2 = mux(toD_2, a_d_2.ready, a_a_2.ready)
connect nodeIn_2.a.ready, _nodeIn_a_ready_T_2
node _a_a_valid_T_4 = eq(toD_2, UInt<1>(0h0))
node _a_a_valid_T_5 = and(nodeIn_2.a.valid, _a_a_valid_T_4)
connect a_a_2.valid, _a_a_valid_T_5
connect a_a_2.bits, nodeIn_2.a.bits
node _a_a_bits_source_T_10 = shl(nodeIn_2.a.bits.source, 1)
node _a_a_bits_source_T_11 = mux(isPut_2, UInt<1>(0h1), UInt<1>(0h0))
node _a_a_bits_source_T_12 = or(_a_a_bits_source_T_10, _a_a_bits_source_T_11)
connect a_a_2.bits.source, _a_a_bits_source_T_12
node _T_132 = eq(nodeIn_2.a.bits.opcode, UInt<3>(0h6))
node _T_133 = eq(nodeIn_2.a.bits.opcode, UInt<3>(0h7))
node _T_134 = or(_T_132, _T_133)
when _T_134 :
connect a_a_2.bits.opcode, UInt<3>(0h4)
connect a_a_2.bits.param, UInt<1>(0h0)
node _a_a_bits_source_T_13 = shl(nodeIn_2.a.bits.source, 1)
node _a_a_bits_source_T_14 = or(_a_a_bits_source_T_13, UInt<1>(0h1))
connect a_a_2.bits.source, _a_a_bits_source_T_14
node _a_d_valid_T_2 = and(nodeIn_2.a.valid, toD_2)
connect a_d_2.valid, _a_d_valid_T_2
wire a_d_bits_d_2 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect a_d_bits_d_2.opcode, UInt<3>(0h4)
connect a_d_bits_d_2.param, UInt<2>(0h0)
connect a_d_bits_d_2.size, nodeIn_2.a.bits.size
connect a_d_bits_d_2.source, nodeIn_2.a.bits.source
connect a_d_bits_d_2.sink, UInt<1>(0h0)
connect a_d_bits_d_2.denied, UInt<1>(0h0)
invalidate a_d_bits_d_2.data
connect a_d_bits_d_2.corrupt, UInt<1>(0h0)
connect a_d_2.bits.corrupt, a_d_bits_d_2.corrupt
connect a_d_2.bits.data, a_d_bits_d_2.data
connect a_d_2.bits.denied, a_d_bits_d_2.denied
connect a_d_2.bits.sink, a_d_bits_d_2.sink
connect a_d_2.bits.source, a_d_bits_d_2.source
connect a_d_2.bits.size, a_d_bits_d_2.size
connect a_d_2.bits.param, a_d_bits_d_2.param
connect a_d_2.bits.opcode, a_d_bits_d_2.opcode
wire c_a_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
node _c_a_valid_T_4 = eq(nodeIn_2.c.bits.opcode, UInt<3>(0h7))
node _c_a_valid_T_5 = and(nodeIn_2.c.valid, _c_a_valid_T_4)
connect c_a_2.valid, _c_a_valid_T_5
node _c_a_bits_T_2 = shl(nodeIn_2.c.bits.source, 1)
node _c_a_bits_legal_T_20 = leq(UInt<1>(0h0), nodeIn_2.c.bits.size)
node _c_a_bits_legal_T_21 = leq(nodeIn_2.c.bits.size, UInt<3>(0h6))
node _c_a_bits_legal_T_22 = and(_c_a_bits_legal_T_20, _c_a_bits_legal_T_21)
node _c_a_bits_legal_T_23 = or(UInt<1>(0h0), _c_a_bits_legal_T_22)
node _c_a_bits_legal_T_24 = xor(nodeIn_2.c.bits.address, UInt<1>(0h0))
node _c_a_bits_legal_T_25 = cvt(_c_a_bits_legal_T_24)
node _c_a_bits_legal_T_26 = and(_c_a_bits_legal_T_25, asSInt(UInt<1>(0h0)))
node _c_a_bits_legal_T_27 = asSInt(_c_a_bits_legal_T_26)
node _c_a_bits_legal_T_28 = eq(_c_a_bits_legal_T_27, asSInt(UInt<1>(0h0)))
node _c_a_bits_legal_T_29 = and(_c_a_bits_legal_T_23, _c_a_bits_legal_T_28)
node c_a_bits_legal_2 = or(UInt<1>(0h0), _c_a_bits_legal_T_29)
wire c_a_bits_a_2 : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect c_a_bits_a_2.opcode, UInt<1>(0h0)
connect c_a_bits_a_2.param, UInt<1>(0h0)
connect c_a_bits_a_2.size, nodeIn_2.c.bits.size
connect c_a_bits_a_2.source, _c_a_bits_T_2
connect c_a_bits_a_2.address, nodeIn_2.c.bits.address
node _c_a_bits_a_mask_sizeOH_T_6 = or(nodeIn_2.c.bits.size, UInt<3>(0h0))
node c_a_bits_a_mask_sizeOH_shiftAmount_2 = bits(_c_a_bits_a_mask_sizeOH_T_6, 1, 0)
node _c_a_bits_a_mask_sizeOH_T_7 = dshl(UInt<1>(0h1), c_a_bits_a_mask_sizeOH_shiftAmount_2)
node _c_a_bits_a_mask_sizeOH_T_8 = bits(_c_a_bits_a_mask_sizeOH_T_7, 2, 0)
node c_a_bits_a_mask_sizeOH_2 = or(_c_a_bits_a_mask_sizeOH_T_8, UInt<1>(0h1))
node c_a_bits_a_mask_sub_sub_sub_0_1_2 = geq(nodeIn_2.c.bits.size, UInt<2>(0h3))
node c_a_bits_a_mask_sub_sub_size_2 = bits(c_a_bits_a_mask_sizeOH_2, 2, 2)
node c_a_bits_a_mask_sub_sub_bit_2 = bits(nodeIn_2.c.bits.address, 2, 2)
node c_a_bits_a_mask_sub_sub_nbit_2 = eq(c_a_bits_a_mask_sub_sub_bit_2, UInt<1>(0h0))
node c_a_bits_a_mask_sub_sub_0_2_2 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_nbit_2)
node _c_a_bits_a_mask_sub_sub_acc_T_4 = and(c_a_bits_a_mask_sub_sub_size_2, c_a_bits_a_mask_sub_sub_0_2_2)
node c_a_bits_a_mask_sub_sub_0_1_2 = or(c_a_bits_a_mask_sub_sub_sub_0_1_2, _c_a_bits_a_mask_sub_sub_acc_T_4)
node c_a_bits_a_mask_sub_sub_1_2_2 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_bit_2)
node _c_a_bits_a_mask_sub_sub_acc_T_5 = and(c_a_bits_a_mask_sub_sub_size_2, c_a_bits_a_mask_sub_sub_1_2_2)
node c_a_bits_a_mask_sub_sub_1_1_2 = or(c_a_bits_a_mask_sub_sub_sub_0_1_2, _c_a_bits_a_mask_sub_sub_acc_T_5)
node c_a_bits_a_mask_sub_size_2 = bits(c_a_bits_a_mask_sizeOH_2, 1, 1)
node c_a_bits_a_mask_sub_bit_2 = bits(nodeIn_2.c.bits.address, 1, 1)
node c_a_bits_a_mask_sub_nbit_2 = eq(c_a_bits_a_mask_sub_bit_2, UInt<1>(0h0))
node c_a_bits_a_mask_sub_0_2_2 = and(c_a_bits_a_mask_sub_sub_0_2_2, c_a_bits_a_mask_sub_nbit_2)
node _c_a_bits_a_mask_sub_acc_T_8 = and(c_a_bits_a_mask_sub_size_2, c_a_bits_a_mask_sub_0_2_2)
node c_a_bits_a_mask_sub_0_1_2 = or(c_a_bits_a_mask_sub_sub_0_1_2, _c_a_bits_a_mask_sub_acc_T_8)
node c_a_bits_a_mask_sub_1_2_2 = and(c_a_bits_a_mask_sub_sub_0_2_2, c_a_bits_a_mask_sub_bit_2)
node _c_a_bits_a_mask_sub_acc_T_9 = and(c_a_bits_a_mask_sub_size_2, c_a_bits_a_mask_sub_1_2_2)
node c_a_bits_a_mask_sub_1_1_2 = or(c_a_bits_a_mask_sub_sub_0_1_2, _c_a_bits_a_mask_sub_acc_T_9)
node c_a_bits_a_mask_sub_2_2_2 = and(c_a_bits_a_mask_sub_sub_1_2_2, c_a_bits_a_mask_sub_nbit_2)
node _c_a_bits_a_mask_sub_acc_T_10 = and(c_a_bits_a_mask_sub_size_2, c_a_bits_a_mask_sub_2_2_2)
node c_a_bits_a_mask_sub_2_1_2 = or(c_a_bits_a_mask_sub_sub_1_1_2, _c_a_bits_a_mask_sub_acc_T_10)
node c_a_bits_a_mask_sub_3_2_2 = and(c_a_bits_a_mask_sub_sub_1_2_2, c_a_bits_a_mask_sub_bit_2)
node _c_a_bits_a_mask_sub_acc_T_11 = and(c_a_bits_a_mask_sub_size_2, c_a_bits_a_mask_sub_3_2_2)
node c_a_bits_a_mask_sub_3_1_2 = or(c_a_bits_a_mask_sub_sub_1_1_2, _c_a_bits_a_mask_sub_acc_T_11)
node c_a_bits_a_mask_size_2 = bits(c_a_bits_a_mask_sizeOH_2, 0, 0)
node c_a_bits_a_mask_bit_2 = bits(nodeIn_2.c.bits.address, 0, 0)
node c_a_bits_a_mask_nbit_2 = eq(c_a_bits_a_mask_bit_2, UInt<1>(0h0))
node c_a_bits_a_mask_eq_16 = and(c_a_bits_a_mask_sub_0_2_2, c_a_bits_a_mask_nbit_2)
node _c_a_bits_a_mask_acc_T_16 = and(c_a_bits_a_mask_size_2, c_a_bits_a_mask_eq_16)
node c_a_bits_a_mask_acc_16 = or(c_a_bits_a_mask_sub_0_1_2, _c_a_bits_a_mask_acc_T_16)
node c_a_bits_a_mask_eq_17 = and(c_a_bits_a_mask_sub_0_2_2, c_a_bits_a_mask_bit_2)
node _c_a_bits_a_mask_acc_T_17 = and(c_a_bits_a_mask_size_2, c_a_bits_a_mask_eq_17)
node c_a_bits_a_mask_acc_17 = or(c_a_bits_a_mask_sub_0_1_2, _c_a_bits_a_mask_acc_T_17)
node c_a_bits_a_mask_eq_18 = and(c_a_bits_a_mask_sub_1_2_2, c_a_bits_a_mask_nbit_2)
node _c_a_bits_a_mask_acc_T_18 = and(c_a_bits_a_mask_size_2, c_a_bits_a_mask_eq_18)
node c_a_bits_a_mask_acc_18 = or(c_a_bits_a_mask_sub_1_1_2, _c_a_bits_a_mask_acc_T_18)
node c_a_bits_a_mask_eq_19 = and(c_a_bits_a_mask_sub_1_2_2, c_a_bits_a_mask_bit_2)
node _c_a_bits_a_mask_acc_T_19 = and(c_a_bits_a_mask_size_2, c_a_bits_a_mask_eq_19)
node c_a_bits_a_mask_acc_19 = or(c_a_bits_a_mask_sub_1_1_2, _c_a_bits_a_mask_acc_T_19)
node c_a_bits_a_mask_eq_20 = and(c_a_bits_a_mask_sub_2_2_2, c_a_bits_a_mask_nbit_2)
node _c_a_bits_a_mask_acc_T_20 = and(c_a_bits_a_mask_size_2, c_a_bits_a_mask_eq_20)
node c_a_bits_a_mask_acc_20 = or(c_a_bits_a_mask_sub_2_1_2, _c_a_bits_a_mask_acc_T_20)
node c_a_bits_a_mask_eq_21 = and(c_a_bits_a_mask_sub_2_2_2, c_a_bits_a_mask_bit_2)
node _c_a_bits_a_mask_acc_T_21 = and(c_a_bits_a_mask_size_2, c_a_bits_a_mask_eq_21)
node c_a_bits_a_mask_acc_21 = or(c_a_bits_a_mask_sub_2_1_2, _c_a_bits_a_mask_acc_T_21)
node c_a_bits_a_mask_eq_22 = and(c_a_bits_a_mask_sub_3_2_2, c_a_bits_a_mask_nbit_2)
node _c_a_bits_a_mask_acc_T_22 = and(c_a_bits_a_mask_size_2, c_a_bits_a_mask_eq_22)
node c_a_bits_a_mask_acc_22 = or(c_a_bits_a_mask_sub_3_1_2, _c_a_bits_a_mask_acc_T_22)
node c_a_bits_a_mask_eq_23 = and(c_a_bits_a_mask_sub_3_2_2, c_a_bits_a_mask_bit_2)
node _c_a_bits_a_mask_acc_T_23 = and(c_a_bits_a_mask_size_2, c_a_bits_a_mask_eq_23)
node c_a_bits_a_mask_acc_23 = or(c_a_bits_a_mask_sub_3_1_2, _c_a_bits_a_mask_acc_T_23)
node c_a_bits_a_mask_lo_lo_2 = cat(c_a_bits_a_mask_acc_17, c_a_bits_a_mask_acc_16)
node c_a_bits_a_mask_lo_hi_2 = cat(c_a_bits_a_mask_acc_19, c_a_bits_a_mask_acc_18)
node c_a_bits_a_mask_lo_2 = cat(c_a_bits_a_mask_lo_hi_2, c_a_bits_a_mask_lo_lo_2)
node c_a_bits_a_mask_hi_lo_2 = cat(c_a_bits_a_mask_acc_21, c_a_bits_a_mask_acc_20)
node c_a_bits_a_mask_hi_hi_2 = cat(c_a_bits_a_mask_acc_23, c_a_bits_a_mask_acc_22)
node c_a_bits_a_mask_hi_2 = cat(c_a_bits_a_mask_hi_hi_2, c_a_bits_a_mask_hi_lo_2)
node _c_a_bits_a_mask_T_2 = cat(c_a_bits_a_mask_hi_2, c_a_bits_a_mask_lo_2)
connect c_a_bits_a_2.mask, _c_a_bits_a_mask_T_2
connect c_a_bits_a_2.data, nodeIn_2.c.bits.data
connect c_a_bits_a_2.corrupt, nodeIn_2.c.bits.corrupt
connect c_a_2.bits, c_a_bits_a_2
wire c_d_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _c_d_valid_T_4 = eq(nodeIn_2.c.bits.opcode, UInt<3>(0h6))
node _c_d_valid_T_5 = and(nodeIn_2.c.valid, _c_d_valid_T_4)
connect c_d_2.valid, _c_d_valid_T_5
wire c_d_bits_d_2 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect c_d_bits_d_2.opcode, UInt<3>(0h6)
connect c_d_bits_d_2.param, UInt<1>(0h0)
connect c_d_bits_d_2.size, nodeIn_2.c.bits.size
connect c_d_bits_d_2.source, nodeIn_2.c.bits.source
connect c_d_bits_d_2.sink, UInt<1>(0h0)
connect c_d_bits_d_2.denied, UInt<1>(0h0)
invalidate c_d_bits_d_2.data
connect c_d_bits_d_2.corrupt, UInt<1>(0h0)
connect c_d_2.bits.corrupt, c_d_bits_d_2.corrupt
connect c_d_2.bits.data, c_d_bits_d_2.data
connect c_d_2.bits.denied, c_d_bits_d_2.denied
connect c_d_2.bits.sink, c_d_bits_d_2.sink
connect c_d_2.bits.source, c_d_bits_d_2.source
connect c_d_2.bits.size, c_d_bits_d_2.size
connect c_d_2.bits.param, c_d_bits_d_2.param
connect c_d_2.bits.opcode, c_d_bits_d_2.opcode
node _T_135 = eq(nodeIn_2.c.valid, UInt<1>(0h0))
node _T_136 = eq(nodeIn_2.c.bits.opcode, UInt<3>(0h6))
node _T_137 = or(_T_135, _T_136)
node _T_138 = eq(nodeIn_2.c.bits.opcode, UInt<3>(0h7))
node _T_139 = or(_T_137, _T_138)
node _T_140 = asUInt(reset)
node _T_141 = eq(_T_140, UInt<1>(0h0))
when _T_141 :
node _T_142 = eq(_T_139, UInt<1>(0h0))
when _T_142 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:116 assert (!in.c.valid || in.c.bits.opcode === Release || in.c.bits.opcode === ReleaseData)\n") : printf_12
assert(clock, _T_139, UInt<1>(0h1), "") : assert_12
node _nodeIn_c_ready_T_4 = eq(nodeIn_2.c.bits.opcode, UInt<3>(0h6))
node _nodeIn_c_ready_T_5 = mux(_nodeIn_c_ready_T_4, c_d_2.ready, c_a_2.ready)
connect nodeIn_2.c.ready, _nodeIn_c_ready_T_5
connect nodeIn_2.e.ready, UInt<1>(0h1)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.mask, UInt<8>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<5>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<2>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
connect _WIRE_17.ready, UInt<1>(0h0)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.mask, UInt<8>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<5>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<2>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_143 = eq(_WIRE_19.valid, UInt<1>(0h0))
node _T_144 = asUInt(reset)
node _T_145 = eq(_T_144, UInt<1>(0h0))
when _T_145 :
node _T_146 = eq(_T_143, UInt<1>(0h0))
when _T_146 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:124 assert (!out.b.valid)\n") : printf_13
assert(clock, _T_143, UInt<1>(0h1), "") : assert_13
inst pool_2 of IDPool_2
connect pool_2.clock, clock
connect pool_2.reset, reset
node _pool_io_free_valid_T_2 = and(nodeIn_2.e.ready, nodeIn_2.e.valid)
connect pool_2.io.free.valid, _pool_io_free_valid_T_2
connect pool_2.io.free.bits, nodeIn_2.e.bits.sink
wire in_d_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _d_first_T_2 = and(in_d_2.ready, in_d_2.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), in_d_2.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(in_d_2.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
node _d_grant_T_4 = eq(in_d_2.bits.opcode, UInt<3>(0h5))
node _d_grant_T_5 = eq(in_d_2.bits.opcode, UInt<3>(0h4))
node d_grant_2 = or(_d_grant_T_4, _d_grant_T_5)
node _pool_io_alloc_ready_T_6 = and(nodeIn_2.d.ready, nodeIn_2.d.valid)
node _pool_io_alloc_ready_T_7 = and(_pool_io_alloc_ready_T_6, d_first_2)
node _pool_io_alloc_ready_T_8 = and(_pool_io_alloc_ready_T_7, d_grant_2)
connect pool_2.io.alloc.ready, _pool_io_alloc_ready_T_8
node _nodeIn_d_valid_T_10 = eq(d_first_2, UInt<1>(0h0))
node _nodeIn_d_valid_T_11 = or(pool_2.io.alloc.valid, _nodeIn_d_valid_T_10)
node _nodeIn_d_valid_T_12 = eq(d_grant_2, UInt<1>(0h0))
node _nodeIn_d_valid_T_13 = or(_nodeIn_d_valid_T_11, _nodeIn_d_valid_T_12)
node _nodeIn_d_valid_T_14 = and(in_d_2.valid, _nodeIn_d_valid_T_13)
connect nodeIn_2.d.valid, _nodeIn_d_valid_T_14
node _in_d_ready_T_10 = eq(d_first_2, UInt<1>(0h0))
node _in_d_ready_T_11 = or(pool_2.io.alloc.valid, _in_d_ready_T_10)
node _in_d_ready_T_12 = eq(d_grant_2, UInt<1>(0h0))
node _in_d_ready_T_13 = or(_in_d_ready_T_11, _in_d_ready_T_12)
node _in_d_ready_T_14 = and(nodeIn_2.d.ready, _in_d_ready_T_13)
connect in_d_2.ready, _in_d_ready_T_14
connect nodeIn_2.d.bits.corrupt, in_d_2.bits.corrupt
connect nodeIn_2.d.bits.data, in_d_2.bits.data
connect nodeIn_2.d.bits.denied, in_d_2.bits.denied
connect nodeIn_2.d.bits.sink, in_d_2.bits.sink
connect nodeIn_2.d.bits.source, in_d_2.bits.source
connect nodeIn_2.d.bits.size, in_d_2.bits.size
connect nodeIn_2.d.bits.param, in_d_2.bits.param
connect nodeIn_2.d.bits.opcode, in_d_2.bits.opcode
reg nodeIn_d_bits_sink_r_2 : UInt<3>, clock
when d_first_2 :
connect nodeIn_d_bits_sink_r_2, pool_2.io.alloc.bits
node _nodeIn_d_bits_sink_T_2 = mux(d_first_2, pool_2.io.alloc.bits, nodeIn_d_bits_sink_r_2)
connect nodeIn_2.d.bits.sink, _nodeIn_d_bits_sink_T_2
wire d_d_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect d_d_2, x1_nodeOut_1.d
node _d_d_bits_source_T_2 = shr(x1_nodeOut_1.d.bits.source, 1)
connect d_d_2.bits.source, _d_d_bits_source_T_2
reg wSourceVec_2 : UInt<1>[10], clock
node _aWOk_T_10 = xor(nodeIn_2.a.bits.address, UInt<1>(0h0))
node _aWOk_T_11 = cvt(_aWOk_T_10)
node _aWOk_T_12 = and(_aWOk_T_11, asSInt(UInt<1>(0h0)))
node _aWOk_T_13 = asSInt(_aWOk_T_12)
node _aWOk_T_14 = eq(_aWOk_T_13, asSInt(UInt<1>(0h0)))
node _bypass_T_4 = and(UInt<1>(0h0), nodeIn_2.a.valid)
node _bypass_T_5 = eq(nodeIn_2.a.bits.source, d_d_2.bits.source)
node bypass_2 = and(_bypass_T_4, _bypass_T_5)
node _dWHeld_T_2 = mux(bypass_2, UInt<1>(0h1), wSourceVec_2[d_d_2.bits.source])
reg dWHeld_r_2 : UInt<1>, clock
when d_first_2 :
connect dWHeld_r_2, _dWHeld_T_2
node dWHeld_2 = mux(d_first_2, _dWHeld_T_2, dWHeld_r_2)
node _T_147 = and(nodeIn_2.a.ready, nodeIn_2.a.valid)
when _T_147 :
connect wSourceVec_2[nodeIn_2.a.bits.source], UInt<1>(0h1)
node _T_148 = eq(x1_nodeOut_1.d.bits.opcode, UInt<1>(0h1))
node _T_149 = bits(x1_nodeOut_1.d.bits.source, 0, 0)
node _T_150 = and(_T_148, _T_149)
when _T_150 :
connect d_d_2.bits.opcode, UInt<3>(0h5)
node _d_d_bits_param_T_2 = mux(dWHeld_2, UInt<2>(0h0), UInt<2>(0h1))
connect d_d_2.bits.param, _d_d_bits_param_T_2
node _T_151 = eq(x1_nodeOut_1.d.bits.opcode, UInt<1>(0h0))
node _T_152 = bits(x1_nodeOut_1.d.bits.source, 0, 0)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = and(_T_151, _T_153)
when _T_154 :
connect d_d_2.bits.opcode, UInt<3>(0h6)
node _decode_T_18 = dshl(UInt<6>(0h3f), c_a_2.bits.size)
node _decode_T_19 = bits(_decode_T_18, 5, 0)
node _decode_T_20 = not(_decode_T_19)
node decode_6 = shr(_decode_T_20, 3)
node _opdata_T_4 = bits(c_a_2.bits.opcode, 2, 2)
node opdata_6 = eq(_opdata_T_4, UInt<1>(0h0))
node _T_155 = mux(opdata_6, decode_6, UInt<1>(0h0))
node _decode_T_21 = dshl(UInt<6>(0h3f), a_a_2.bits.size)
node _decode_T_22 = bits(_decode_T_21, 5, 0)
node _decode_T_23 = not(_decode_T_22)
node decode_7 = shr(_decode_T_23, 3)
node _opdata_T_5 = bits(a_a_2.bits.opcode, 2, 2)
node opdata_7 = eq(_opdata_T_5, UInt<1>(0h0))
node _T_156 = mux(opdata_7, decode_7, UInt<1>(0h0))
regreset beatsLeft_4 : UInt, clock, reset, UInt<1>(0h0)
node idle_4 = eq(beatsLeft_4, UInt<1>(0h0))
node latch_4 = and(idle_4, x1_nodeOut_1.a.ready)
node _readys_T_48 = cat(a_a_2.valid, c_a_2.valid)
node _readys_T_49 = shl(_readys_T_48, 1)
node _readys_T_50 = bits(_readys_T_49, 1, 0)
node _readys_T_51 = or(_readys_T_48, _readys_T_50)
node _readys_T_52 = bits(_readys_T_51, 1, 0)
node _readys_T_53 = shl(_readys_T_52, 1)
node _readys_T_54 = bits(_readys_T_53, 1, 0)
node _readys_T_55 = not(_readys_T_54)
node _readys_T_56 = bits(_readys_T_55, 0, 0)
node _readys_T_57 = bits(_readys_T_55, 1, 1)
wire readys_4 : UInt<1>[2]
connect readys_4[0], _readys_T_56
connect readys_4[1], _readys_T_57
node _winner_T_10 = and(readys_4[0], c_a_2.valid)
node _winner_T_11 = and(readys_4[1], a_a_2.valid)
wire winner_4 : UInt<1>[2]
connect winner_4[0], _winner_T_10
connect winner_4[1], _winner_T_11
node prefixOR_1_4 = or(UInt<1>(0h0), winner_4[0])
node _prefixOR_T_4 = or(prefixOR_1_4, winner_4[1])
node _T_157 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_158 = eq(winner_4[0], UInt<1>(0h0))
node _T_159 = or(_T_157, _T_158)
node _T_160 = eq(prefixOR_1_4, UInt<1>(0h0))
node _T_161 = eq(winner_4[1], UInt<1>(0h0))
node _T_162 = or(_T_160, _T_161)
node _T_163 = and(_T_159, _T_162)
node _T_164 = asUInt(reset)
node _T_165 = eq(_T_164, UInt<1>(0h0))
when _T_165 :
node _T_166 = eq(_T_163, UInt<1>(0h0))
when _T_166 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_14
assert(clock, _T_163, UInt<1>(0h1), "") : assert_14
node _T_167 = or(c_a_2.valid, a_a_2.valid)
node _T_168 = eq(_T_167, UInt<1>(0h0))
node _T_169 = or(winner_4[0], winner_4[1])
node _T_170 = or(_T_168, _T_169)
node _T_171 = asUInt(reset)
node _T_172 = eq(_T_171, UInt<1>(0h0))
when _T_172 :
node _T_173 = eq(_T_170, UInt<1>(0h0))
when _T_173 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_15
assert(clock, _T_170, UInt<1>(0h1), "") : assert_15
node maskedBeats_0_4 = mux(winner_4[0], _T_155, UInt<1>(0h0))
node maskedBeats_1_4 = mux(winner_4[1], _T_156, UInt<1>(0h0))
node initBeats_4 = or(maskedBeats_0_4, maskedBeats_1_4)
node _beatsLeft_T_16 = and(x1_nodeOut_1.a.ready, x1_nodeOut_1.a.valid)
node _beatsLeft_T_17 = sub(beatsLeft_4, _beatsLeft_T_16)
node _beatsLeft_T_18 = tail(_beatsLeft_T_17, 1)
node _beatsLeft_T_19 = mux(latch_4, initBeats_4, _beatsLeft_T_18)
connect beatsLeft_4, _beatsLeft_T_19
wire _state_WIRE_4 : UInt<1>[2]
connect _state_WIRE_4[0], UInt<1>(0h0)
connect _state_WIRE_4[1], UInt<1>(0h0)
regreset state_4 : UInt<1>[2], clock, reset, _state_WIRE_4
node muxState_4 = mux(idle_4, winner_4, state_4)
connect state_4, muxState_4
node allowed_4 = mux(idle_4, readys_4, state_4)
node _c_a_ready_T_2 = and(x1_nodeOut_1.a.ready, allowed_4[0])
connect c_a_2.ready, _c_a_ready_T_2
node _a_a_ready_T_2 = and(x1_nodeOut_1.a.ready, allowed_4[1])
connect a_a_2.ready, _a_a_ready_T_2
node _nodeOut_a_valid_T_10 = or(c_a_2.valid, a_a_2.valid)
node _nodeOut_a_valid_T_11 = mux(state_4[0], c_a_2.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_12 = mux(state_4[1], a_a_2.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_13 = or(_nodeOut_a_valid_T_11, _nodeOut_a_valid_T_12)
wire _nodeOut_a_valid_WIRE_2 : UInt<1>
connect _nodeOut_a_valid_WIRE_2, _nodeOut_a_valid_T_13
node _nodeOut_a_valid_T_14 = mux(idle_4, _nodeOut_a_valid_T_10, _nodeOut_a_valid_WIRE_2)
connect x1_nodeOut_1.a.valid, _nodeOut_a_valid_T_14
wire _nodeOut_a_bits_WIRE_22 : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _nodeOut_a_bits_T_48 = mux(muxState_4[0], c_a_2.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_49 = mux(muxState_4[1], a_a_2.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_50 = or(_nodeOut_a_bits_T_48, _nodeOut_a_bits_T_49)
wire _nodeOut_a_bits_WIRE_23 : UInt<1>
connect _nodeOut_a_bits_WIRE_23, _nodeOut_a_bits_T_50
connect _nodeOut_a_bits_WIRE_22.corrupt, _nodeOut_a_bits_WIRE_23
node _nodeOut_a_bits_T_51 = mux(muxState_4[0], c_a_2.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_52 = mux(muxState_4[1], a_a_2.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_53 = or(_nodeOut_a_bits_T_51, _nodeOut_a_bits_T_52)
wire _nodeOut_a_bits_WIRE_24 : UInt<64>
connect _nodeOut_a_bits_WIRE_24, _nodeOut_a_bits_T_53
connect _nodeOut_a_bits_WIRE_22.data, _nodeOut_a_bits_WIRE_24
node _nodeOut_a_bits_T_54 = mux(muxState_4[0], c_a_2.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_55 = mux(muxState_4[1], a_a_2.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_56 = or(_nodeOut_a_bits_T_54, _nodeOut_a_bits_T_55)
wire _nodeOut_a_bits_WIRE_25 : UInt<8>
connect _nodeOut_a_bits_WIRE_25, _nodeOut_a_bits_T_56
connect _nodeOut_a_bits_WIRE_22.mask, _nodeOut_a_bits_WIRE_25
wire _nodeOut_a_bits_WIRE_26 : { }
connect _nodeOut_a_bits_WIRE_22.echo, _nodeOut_a_bits_WIRE_26
wire _nodeOut_a_bits_WIRE_27 : { }
connect _nodeOut_a_bits_WIRE_22.user, _nodeOut_a_bits_WIRE_27
node _nodeOut_a_bits_T_57 = mux(muxState_4[0], c_a_2.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_58 = mux(muxState_4[1], a_a_2.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_59 = or(_nodeOut_a_bits_T_57, _nodeOut_a_bits_T_58)
wire _nodeOut_a_bits_WIRE_28 : UInt<32>
connect _nodeOut_a_bits_WIRE_28, _nodeOut_a_bits_T_59
connect _nodeOut_a_bits_WIRE_22.address, _nodeOut_a_bits_WIRE_28
node _nodeOut_a_bits_T_60 = mux(muxState_4[0], c_a_2.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_61 = mux(muxState_4[1], a_a_2.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_62 = or(_nodeOut_a_bits_T_60, _nodeOut_a_bits_T_61)
wire _nodeOut_a_bits_WIRE_29 : UInt<5>
connect _nodeOut_a_bits_WIRE_29, _nodeOut_a_bits_T_62
connect _nodeOut_a_bits_WIRE_22.source, _nodeOut_a_bits_WIRE_29
node _nodeOut_a_bits_T_63 = mux(muxState_4[0], c_a_2.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_64 = mux(muxState_4[1], a_a_2.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_65 = or(_nodeOut_a_bits_T_63, _nodeOut_a_bits_T_64)
wire _nodeOut_a_bits_WIRE_30 : UInt<3>
connect _nodeOut_a_bits_WIRE_30, _nodeOut_a_bits_T_65
connect _nodeOut_a_bits_WIRE_22.size, _nodeOut_a_bits_WIRE_30
node _nodeOut_a_bits_T_66 = mux(muxState_4[0], c_a_2.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_67 = mux(muxState_4[1], a_a_2.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_68 = or(_nodeOut_a_bits_T_66, _nodeOut_a_bits_T_67)
wire _nodeOut_a_bits_WIRE_31 : UInt<3>
connect _nodeOut_a_bits_WIRE_31, _nodeOut_a_bits_T_68
connect _nodeOut_a_bits_WIRE_22.param, _nodeOut_a_bits_WIRE_31
node _nodeOut_a_bits_T_69 = mux(muxState_4[0], c_a_2.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_70 = mux(muxState_4[1], a_a_2.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_71 = or(_nodeOut_a_bits_T_69, _nodeOut_a_bits_T_70)
wire _nodeOut_a_bits_WIRE_32 : UInt<3>
connect _nodeOut_a_bits_WIRE_32, _nodeOut_a_bits_T_71
connect _nodeOut_a_bits_WIRE_22.opcode, _nodeOut_a_bits_WIRE_32
connect x1_nodeOut_1.a.bits.corrupt, _nodeOut_a_bits_WIRE_22.corrupt
connect x1_nodeOut_1.a.bits.data, _nodeOut_a_bits_WIRE_22.data
connect x1_nodeOut_1.a.bits.mask, _nodeOut_a_bits_WIRE_22.mask
connect x1_nodeOut_1.a.bits.address, _nodeOut_a_bits_WIRE_22.address
connect x1_nodeOut_1.a.bits.source, _nodeOut_a_bits_WIRE_22.source
connect x1_nodeOut_1.a.bits.size, _nodeOut_a_bits_WIRE_22.size
connect x1_nodeOut_1.a.bits.param, _nodeOut_a_bits_WIRE_22.param
connect x1_nodeOut_1.a.bits.opcode, _nodeOut_a_bits_WIRE_22.opcode
node _decode_T_24 = dshl(UInt<6>(0h3f), d_d_2.bits.size)
node _decode_T_25 = bits(_decode_T_24, 5, 0)
node _decode_T_26 = not(_decode_T_25)
node decode_8 = shr(_decode_T_26, 3)
node opdata_8 = bits(d_d_2.bits.opcode, 0, 0)
node _T_174 = mux(opdata_8, decode_8, UInt<1>(0h0))
inst q_4 of Queue2_TLBundleD_a32d64s4k3z3c_12
connect q_4.clock, clock
connect q_4.reset, reset
connect q_4.io.enq.valid, c_d_2.valid
connect q_4.io.enq.bits.corrupt, c_d_2.bits.corrupt
connect q_4.io.enq.bits.data, c_d_2.bits.data
connect q_4.io.enq.bits.denied, c_d_2.bits.denied
connect q_4.io.enq.bits.sink, c_d_2.bits.sink
connect q_4.io.enq.bits.source, c_d_2.bits.source
connect q_4.io.enq.bits.size, c_d_2.bits.size
connect q_4.io.enq.bits.param, c_d_2.bits.param
connect q_4.io.enq.bits.opcode, c_d_2.bits.opcode
connect c_d_2.ready, q_4.io.enq.ready
inst q_5 of Queue2_TLBundleD_a32d64s4k3z3c_13
connect q_5.clock, clock
connect q_5.reset, reset
connect q_5.io.enq.valid, a_d_2.valid
connect q_5.io.enq.bits.corrupt, a_d_2.bits.corrupt
connect q_5.io.enq.bits.data, a_d_2.bits.data
connect q_5.io.enq.bits.denied, a_d_2.bits.denied
connect q_5.io.enq.bits.sink, a_d_2.bits.sink
connect q_5.io.enq.bits.source, a_d_2.bits.source
connect q_5.io.enq.bits.size, a_d_2.bits.size
connect q_5.io.enq.bits.param, a_d_2.bits.param
connect q_5.io.enq.bits.opcode, a_d_2.bits.opcode
connect a_d_2.ready, q_5.io.enq.ready
regreset beatsLeft_5 : UInt, clock, reset, UInt<1>(0h0)
node idle_5 = eq(beatsLeft_5, UInt<1>(0h0))
node latch_5 = and(idle_5, in_d_2.ready)
node readys_hi_2 = cat(q_5.io.deq.valid, q_4.io.deq.valid)
node _readys_T_58 = cat(readys_hi_2, d_d_2.valid)
node _readys_T_59 = shl(_readys_T_58, 1)
node _readys_T_60 = bits(_readys_T_59, 2, 0)
node _readys_T_61 = or(_readys_T_58, _readys_T_60)
node _readys_T_62 = shl(_readys_T_61, 2)
node _readys_T_63 = bits(_readys_T_62, 2, 0)
node _readys_T_64 = or(_readys_T_61, _readys_T_63)
node _readys_T_65 = bits(_readys_T_64, 2, 0)
node _readys_T_66 = shl(_readys_T_65, 1)
node _readys_T_67 = bits(_readys_T_66, 2, 0)
node _readys_T_68 = not(_readys_T_67)
node _readys_T_69 = bits(_readys_T_68, 0, 0)
node _readys_T_70 = bits(_readys_T_68, 1, 1)
node _readys_T_71 = bits(_readys_T_68, 2, 2)
wire readys_5 : UInt<1>[3]
connect readys_5[0], _readys_T_69
connect readys_5[1], _readys_T_70
connect readys_5[2], _readys_T_71
node _winner_T_12 = and(readys_5[0], d_d_2.valid)
node _winner_T_13 = and(readys_5[1], q_4.io.deq.valid)
node _winner_T_14 = and(readys_5[2], q_5.io.deq.valid)
wire winner_5 : UInt<1>[3]
connect winner_5[0], _winner_T_12
connect winner_5[1], _winner_T_13
connect winner_5[2], _winner_T_14
node prefixOR_1_5 = or(UInt<1>(0h0), winner_5[0])
node prefixOR_2_2 = or(prefixOR_1_5, winner_5[1])
node _prefixOR_T_5 = or(prefixOR_2_2, winner_5[2])
node _T_175 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_176 = eq(winner_5[0], UInt<1>(0h0))
node _T_177 = or(_T_175, _T_176)
node _T_178 = eq(prefixOR_1_5, UInt<1>(0h0))
node _T_179 = eq(winner_5[1], UInt<1>(0h0))
node _T_180 = or(_T_178, _T_179)
node _T_181 = eq(prefixOR_2_2, UInt<1>(0h0))
node _T_182 = eq(winner_5[2], UInt<1>(0h0))
node _T_183 = or(_T_181, _T_182)
node _T_184 = and(_T_177, _T_180)
node _T_185 = and(_T_184, _T_183)
node _T_186 = asUInt(reset)
node _T_187 = eq(_T_186, UInt<1>(0h0))
when _T_187 :
node _T_188 = eq(_T_185, UInt<1>(0h0))
when _T_188 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_16
assert(clock, _T_185, UInt<1>(0h1), "") : assert_16
node _T_189 = or(d_d_2.valid, q_4.io.deq.valid)
node _T_190 = or(_T_189, q_5.io.deq.valid)
node _T_191 = eq(_T_190, UInt<1>(0h0))
node _T_192 = or(winner_5[0], winner_5[1])
node _T_193 = or(_T_192, winner_5[2])
node _T_194 = or(_T_191, _T_193)
node _T_195 = asUInt(reset)
node _T_196 = eq(_T_195, UInt<1>(0h0))
when _T_196 :
node _T_197 = eq(_T_194, UInt<1>(0h0))
when _T_197 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_17
assert(clock, _T_194, UInt<1>(0h1), "") : assert_17
node maskedBeats_0_5 = mux(winner_5[0], _T_174, UInt<1>(0h0))
node maskedBeats_1_5 = mux(winner_5[1], UInt<1>(0h0), UInt<1>(0h0))
node maskedBeats_2_2 = mux(winner_5[2], UInt<1>(0h0), UInt<1>(0h0))
node _initBeats_T_2 = or(maskedBeats_0_5, maskedBeats_1_5)
node initBeats_5 = or(_initBeats_T_2, maskedBeats_2_2)
node _beatsLeft_T_20 = and(in_d_2.ready, in_d_2.valid)
node _beatsLeft_T_21 = sub(beatsLeft_5, _beatsLeft_T_20)
node _beatsLeft_T_22 = tail(_beatsLeft_T_21, 1)
node _beatsLeft_T_23 = mux(latch_5, initBeats_5, _beatsLeft_T_22)
connect beatsLeft_5, _beatsLeft_T_23
wire _state_WIRE_5 : UInt<1>[3]
connect _state_WIRE_5[0], UInt<1>(0h0)
connect _state_WIRE_5[1], UInt<1>(0h0)
connect _state_WIRE_5[2], UInt<1>(0h0)
regreset state_5 : UInt<1>[3], clock, reset, _state_WIRE_5
node muxState_5 = mux(idle_5, winner_5, state_5)
connect state_5, muxState_5
node allowed_5 = mux(idle_5, readys_5, state_5)
node _d_d_ready_T_2 = and(in_d_2.ready, allowed_5[0])
connect d_d_2.ready, _d_d_ready_T_2
node _q_io_deq_ready_T_4 = and(in_d_2.ready, allowed_5[1])
connect q_4.io.deq.ready, _q_io_deq_ready_T_4
node _q_io_deq_ready_T_5 = and(in_d_2.ready, allowed_5[2])
connect q_5.io.deq.ready, _q_io_deq_ready_T_5
node _in_d_valid_T_16 = or(d_d_2.valid, q_4.io.deq.valid)
node _in_d_valid_T_17 = or(_in_d_valid_T_16, q_5.io.deq.valid)
node _in_d_valid_T_18 = mux(state_5[0], d_d_2.valid, UInt<1>(0h0))
node _in_d_valid_T_19 = mux(state_5[1], q_4.io.deq.valid, UInt<1>(0h0))
node _in_d_valid_T_20 = mux(state_5[2], q_5.io.deq.valid, UInt<1>(0h0))
node _in_d_valid_T_21 = or(_in_d_valid_T_18, _in_d_valid_T_19)
node _in_d_valid_T_22 = or(_in_d_valid_T_21, _in_d_valid_T_20)
wire _in_d_valid_WIRE_2 : UInt<1>
connect _in_d_valid_WIRE_2, _in_d_valid_T_22
node _in_d_valid_T_23 = mux(idle_5, _in_d_valid_T_17, _in_d_valid_WIRE_2)
connect in_d_2.valid, _in_d_valid_T_23
wire _in_d_bits_WIRE_22 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_d_bits_T_80 = mux(muxState_5[0], d_d_2.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_81 = mux(muxState_5[1], q_4.io.deq.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_82 = mux(muxState_5[2], q_5.io.deq.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_83 = or(_in_d_bits_T_80, _in_d_bits_T_81)
node _in_d_bits_T_84 = or(_in_d_bits_T_83, _in_d_bits_T_82)
wire _in_d_bits_WIRE_23 : UInt<1>
connect _in_d_bits_WIRE_23, _in_d_bits_T_84
connect _in_d_bits_WIRE_22.corrupt, _in_d_bits_WIRE_23
node _in_d_bits_T_85 = mux(muxState_5[0], d_d_2.bits.data, UInt<1>(0h0))
node _in_d_bits_T_86 = mux(muxState_5[1], q_4.io.deq.bits.data, UInt<1>(0h0))
node _in_d_bits_T_87 = mux(muxState_5[2], q_5.io.deq.bits.data, UInt<1>(0h0))
node _in_d_bits_T_88 = or(_in_d_bits_T_85, _in_d_bits_T_86)
node _in_d_bits_T_89 = or(_in_d_bits_T_88, _in_d_bits_T_87)
wire _in_d_bits_WIRE_24 : UInt<64>
connect _in_d_bits_WIRE_24, _in_d_bits_T_89
connect _in_d_bits_WIRE_22.data, _in_d_bits_WIRE_24
wire _in_d_bits_WIRE_25 : { }
connect _in_d_bits_WIRE_22.echo, _in_d_bits_WIRE_25
wire _in_d_bits_WIRE_26 : { }
connect _in_d_bits_WIRE_22.user, _in_d_bits_WIRE_26
node _in_d_bits_T_90 = mux(muxState_5[0], d_d_2.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_91 = mux(muxState_5[1], q_4.io.deq.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_92 = mux(muxState_5[2], q_5.io.deq.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_93 = or(_in_d_bits_T_90, _in_d_bits_T_91)
node _in_d_bits_T_94 = or(_in_d_bits_T_93, _in_d_bits_T_92)
wire _in_d_bits_WIRE_27 : UInt<1>
connect _in_d_bits_WIRE_27, _in_d_bits_T_94
connect _in_d_bits_WIRE_22.denied, _in_d_bits_WIRE_27
node _in_d_bits_T_95 = mux(muxState_5[0], d_d_2.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_96 = mux(muxState_5[1], q_4.io.deq.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_97 = mux(muxState_5[2], q_5.io.deq.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_98 = or(_in_d_bits_T_95, _in_d_bits_T_96)
node _in_d_bits_T_99 = or(_in_d_bits_T_98, _in_d_bits_T_97)
wire _in_d_bits_WIRE_28 : UInt<3>
connect _in_d_bits_WIRE_28, _in_d_bits_T_99
connect _in_d_bits_WIRE_22.sink, _in_d_bits_WIRE_28
node _in_d_bits_T_100 = mux(muxState_5[0], d_d_2.bits.source, UInt<1>(0h0))
node _in_d_bits_T_101 = mux(muxState_5[1], q_4.io.deq.bits.source, UInt<1>(0h0))
node _in_d_bits_T_102 = mux(muxState_5[2], q_5.io.deq.bits.source, UInt<1>(0h0))
node _in_d_bits_T_103 = or(_in_d_bits_T_100, _in_d_bits_T_101)
node _in_d_bits_T_104 = or(_in_d_bits_T_103, _in_d_bits_T_102)
wire _in_d_bits_WIRE_29 : UInt<4>
connect _in_d_bits_WIRE_29, _in_d_bits_T_104
connect _in_d_bits_WIRE_22.source, _in_d_bits_WIRE_29
node _in_d_bits_T_105 = mux(muxState_5[0], d_d_2.bits.size, UInt<1>(0h0))
node _in_d_bits_T_106 = mux(muxState_5[1], q_4.io.deq.bits.size, UInt<1>(0h0))
node _in_d_bits_T_107 = mux(muxState_5[2], q_5.io.deq.bits.size, UInt<1>(0h0))
node _in_d_bits_T_108 = or(_in_d_bits_T_105, _in_d_bits_T_106)
node _in_d_bits_T_109 = or(_in_d_bits_T_108, _in_d_bits_T_107)
wire _in_d_bits_WIRE_30 : UInt<3>
connect _in_d_bits_WIRE_30, _in_d_bits_T_109
connect _in_d_bits_WIRE_22.size, _in_d_bits_WIRE_30
node _in_d_bits_T_110 = mux(muxState_5[0], d_d_2.bits.param, UInt<1>(0h0))
node _in_d_bits_T_111 = mux(muxState_5[1], q_4.io.deq.bits.param, UInt<1>(0h0))
node _in_d_bits_T_112 = mux(muxState_5[2], q_5.io.deq.bits.param, UInt<1>(0h0))
node _in_d_bits_T_113 = or(_in_d_bits_T_110, _in_d_bits_T_111)
node _in_d_bits_T_114 = or(_in_d_bits_T_113, _in_d_bits_T_112)
wire _in_d_bits_WIRE_31 : UInt<2>
connect _in_d_bits_WIRE_31, _in_d_bits_T_114
connect _in_d_bits_WIRE_22.param, _in_d_bits_WIRE_31
node _in_d_bits_T_115 = mux(muxState_5[0], d_d_2.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_116 = mux(muxState_5[1], q_4.io.deq.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_117 = mux(muxState_5[2], q_5.io.deq.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_118 = or(_in_d_bits_T_115, _in_d_bits_T_116)
node _in_d_bits_T_119 = or(_in_d_bits_T_118, _in_d_bits_T_117)
wire _in_d_bits_WIRE_32 : UInt<3>
connect _in_d_bits_WIRE_32, _in_d_bits_T_119
connect _in_d_bits_WIRE_22.opcode, _in_d_bits_WIRE_32
connect in_d_2.bits.corrupt, _in_d_bits_WIRE_22.corrupt
connect in_d_2.bits.data, _in_d_bits_WIRE_22.data
connect in_d_2.bits.denied, _in_d_bits_WIRE_22.denied
connect in_d_2.bits.sink, _in_d_bits_WIRE_22.sink
connect in_d_2.bits.source, _in_d_bits_WIRE_22.source
connect in_d_2.bits.size, _in_d_bits_WIRE_22.size
connect in_d_2.bits.param, _in_d_bits_WIRE_22.param
connect in_d_2.bits.opcode, _in_d_bits_WIRE_22.opcode
connect nodeIn_2.b.valid, UInt<1>(0h0)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<5>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
connect _WIRE_21.valid, UInt<1>(0h0)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_22.bits.sink, UInt<1>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
connect _WIRE_23.valid, UInt<1>(0h0)
wire a_a_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
wire a_d_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _isPut_T_6 = eq(nodeIn_3.a.bits.opcode, UInt<1>(0h0))
node _isPut_T_7 = eq(nodeIn_3.a.bits.opcode, UInt<1>(0h1))
node isPut_3 = or(_isPut_T_6, _isPut_T_7)
node _toD_T_12 = eq(nodeIn_3.a.bits.opcode, UInt<3>(0h6))
node _toD_T_13 = eq(nodeIn_3.a.bits.param, UInt<2>(0h2))
node _toD_T_14 = and(_toD_T_12, _toD_T_13)
node _toD_T_15 = eq(nodeIn_3.a.bits.opcode, UInt<3>(0h7))
node toD_3 = or(_toD_T_14, _toD_T_15)
node _nodeIn_a_ready_T_3 = mux(toD_3, a_d_3.ready, a_a_3.ready)
connect nodeIn_3.a.ready, _nodeIn_a_ready_T_3
node _a_a_valid_T_6 = eq(toD_3, UInt<1>(0h0))
node _a_a_valid_T_7 = and(nodeIn_3.a.valid, _a_a_valid_T_6)
connect a_a_3.valid, _a_a_valid_T_7
connect a_a_3.bits, nodeIn_3.a.bits
node _a_a_bits_source_T_15 = shl(nodeIn_3.a.bits.source, 1)
node _a_a_bits_source_T_16 = mux(isPut_3, UInt<1>(0h1), UInt<1>(0h0))
node _a_a_bits_source_T_17 = or(_a_a_bits_source_T_15, _a_a_bits_source_T_16)
connect a_a_3.bits.source, _a_a_bits_source_T_17
node _T_198 = eq(nodeIn_3.a.bits.opcode, UInt<3>(0h6))
node _T_199 = eq(nodeIn_3.a.bits.opcode, UInt<3>(0h7))
node _T_200 = or(_T_198, _T_199)
when _T_200 :
connect a_a_3.bits.opcode, UInt<3>(0h4)
connect a_a_3.bits.param, UInt<1>(0h0)
node _a_a_bits_source_T_18 = shl(nodeIn_3.a.bits.source, 1)
node _a_a_bits_source_T_19 = or(_a_a_bits_source_T_18, UInt<1>(0h1))
connect a_a_3.bits.source, _a_a_bits_source_T_19
node _a_d_valid_T_3 = and(nodeIn_3.a.valid, toD_3)
connect a_d_3.valid, _a_d_valid_T_3
wire a_d_bits_d_3 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect a_d_bits_d_3.opcode, UInt<3>(0h4)
connect a_d_bits_d_3.param, UInt<2>(0h0)
connect a_d_bits_d_3.size, nodeIn_3.a.bits.size
connect a_d_bits_d_3.source, nodeIn_3.a.bits.source
connect a_d_bits_d_3.sink, UInt<1>(0h0)
connect a_d_bits_d_3.denied, UInt<1>(0h0)
invalidate a_d_bits_d_3.data
connect a_d_bits_d_3.corrupt, UInt<1>(0h0)
connect a_d_3.bits.corrupt, a_d_bits_d_3.corrupt
connect a_d_3.bits.data, a_d_bits_d_3.data
connect a_d_3.bits.denied, a_d_bits_d_3.denied
connect a_d_3.bits.sink, a_d_bits_d_3.sink
connect a_d_3.bits.source, a_d_bits_d_3.source
connect a_d_3.bits.size, a_d_bits_d_3.size
connect a_d_3.bits.param, a_d_bits_d_3.param
connect a_d_3.bits.opcode, a_d_bits_d_3.opcode
wire c_a_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
node _c_a_valid_T_6 = eq(nodeIn_3.c.bits.opcode, UInt<3>(0h7))
node _c_a_valid_T_7 = and(nodeIn_3.c.valid, _c_a_valid_T_6)
connect c_a_3.valid, _c_a_valid_T_7
node _c_a_bits_T_3 = shl(nodeIn_3.c.bits.source, 1)
node _c_a_bits_legal_T_30 = leq(UInt<1>(0h0), nodeIn_3.c.bits.size)
node _c_a_bits_legal_T_31 = leq(nodeIn_3.c.bits.size, UInt<3>(0h6))
node _c_a_bits_legal_T_32 = and(_c_a_bits_legal_T_30, _c_a_bits_legal_T_31)
node _c_a_bits_legal_T_33 = or(UInt<1>(0h0), _c_a_bits_legal_T_32)
node _c_a_bits_legal_T_34 = xor(nodeIn_3.c.bits.address, UInt<1>(0h0))
node _c_a_bits_legal_T_35 = cvt(_c_a_bits_legal_T_34)
node _c_a_bits_legal_T_36 = and(_c_a_bits_legal_T_35, asSInt(UInt<1>(0h0)))
node _c_a_bits_legal_T_37 = asSInt(_c_a_bits_legal_T_36)
node _c_a_bits_legal_T_38 = eq(_c_a_bits_legal_T_37, asSInt(UInt<1>(0h0)))
node _c_a_bits_legal_T_39 = and(_c_a_bits_legal_T_33, _c_a_bits_legal_T_38)
node c_a_bits_legal_3 = or(UInt<1>(0h0), _c_a_bits_legal_T_39)
wire c_a_bits_a_3 : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect c_a_bits_a_3.opcode, UInt<1>(0h0)
connect c_a_bits_a_3.param, UInt<1>(0h0)
connect c_a_bits_a_3.size, nodeIn_3.c.bits.size
connect c_a_bits_a_3.source, _c_a_bits_T_3
connect c_a_bits_a_3.address, nodeIn_3.c.bits.address
node _c_a_bits_a_mask_sizeOH_T_9 = or(nodeIn_3.c.bits.size, UInt<3>(0h0))
node c_a_bits_a_mask_sizeOH_shiftAmount_3 = bits(_c_a_bits_a_mask_sizeOH_T_9, 1, 0)
node _c_a_bits_a_mask_sizeOH_T_10 = dshl(UInt<1>(0h1), c_a_bits_a_mask_sizeOH_shiftAmount_3)
node _c_a_bits_a_mask_sizeOH_T_11 = bits(_c_a_bits_a_mask_sizeOH_T_10, 2, 0)
node c_a_bits_a_mask_sizeOH_3 = or(_c_a_bits_a_mask_sizeOH_T_11, UInt<1>(0h1))
node c_a_bits_a_mask_sub_sub_sub_0_1_3 = geq(nodeIn_3.c.bits.size, UInt<2>(0h3))
node c_a_bits_a_mask_sub_sub_size_3 = bits(c_a_bits_a_mask_sizeOH_3, 2, 2)
node c_a_bits_a_mask_sub_sub_bit_3 = bits(nodeIn_3.c.bits.address, 2, 2)
node c_a_bits_a_mask_sub_sub_nbit_3 = eq(c_a_bits_a_mask_sub_sub_bit_3, UInt<1>(0h0))
node c_a_bits_a_mask_sub_sub_0_2_3 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_nbit_3)
node _c_a_bits_a_mask_sub_sub_acc_T_6 = and(c_a_bits_a_mask_sub_sub_size_3, c_a_bits_a_mask_sub_sub_0_2_3)
node c_a_bits_a_mask_sub_sub_0_1_3 = or(c_a_bits_a_mask_sub_sub_sub_0_1_3, _c_a_bits_a_mask_sub_sub_acc_T_6)
node c_a_bits_a_mask_sub_sub_1_2_3 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_bit_3)
node _c_a_bits_a_mask_sub_sub_acc_T_7 = and(c_a_bits_a_mask_sub_sub_size_3, c_a_bits_a_mask_sub_sub_1_2_3)
node c_a_bits_a_mask_sub_sub_1_1_3 = or(c_a_bits_a_mask_sub_sub_sub_0_1_3, _c_a_bits_a_mask_sub_sub_acc_T_7)
node c_a_bits_a_mask_sub_size_3 = bits(c_a_bits_a_mask_sizeOH_3, 1, 1)
node c_a_bits_a_mask_sub_bit_3 = bits(nodeIn_3.c.bits.address, 1, 1)
node c_a_bits_a_mask_sub_nbit_3 = eq(c_a_bits_a_mask_sub_bit_3, UInt<1>(0h0))
node c_a_bits_a_mask_sub_0_2_3 = and(c_a_bits_a_mask_sub_sub_0_2_3, c_a_bits_a_mask_sub_nbit_3)
node _c_a_bits_a_mask_sub_acc_T_12 = and(c_a_bits_a_mask_sub_size_3, c_a_bits_a_mask_sub_0_2_3)
node c_a_bits_a_mask_sub_0_1_3 = or(c_a_bits_a_mask_sub_sub_0_1_3, _c_a_bits_a_mask_sub_acc_T_12)
node c_a_bits_a_mask_sub_1_2_3 = and(c_a_bits_a_mask_sub_sub_0_2_3, c_a_bits_a_mask_sub_bit_3)
node _c_a_bits_a_mask_sub_acc_T_13 = and(c_a_bits_a_mask_sub_size_3, c_a_bits_a_mask_sub_1_2_3)
node c_a_bits_a_mask_sub_1_1_3 = or(c_a_bits_a_mask_sub_sub_0_1_3, _c_a_bits_a_mask_sub_acc_T_13)
node c_a_bits_a_mask_sub_2_2_3 = and(c_a_bits_a_mask_sub_sub_1_2_3, c_a_bits_a_mask_sub_nbit_3)
node _c_a_bits_a_mask_sub_acc_T_14 = and(c_a_bits_a_mask_sub_size_3, c_a_bits_a_mask_sub_2_2_3)
node c_a_bits_a_mask_sub_2_1_3 = or(c_a_bits_a_mask_sub_sub_1_1_3, _c_a_bits_a_mask_sub_acc_T_14)
node c_a_bits_a_mask_sub_3_2_3 = and(c_a_bits_a_mask_sub_sub_1_2_3, c_a_bits_a_mask_sub_bit_3)
node _c_a_bits_a_mask_sub_acc_T_15 = and(c_a_bits_a_mask_sub_size_3, c_a_bits_a_mask_sub_3_2_3)
node c_a_bits_a_mask_sub_3_1_3 = or(c_a_bits_a_mask_sub_sub_1_1_3, _c_a_bits_a_mask_sub_acc_T_15)
node c_a_bits_a_mask_size_3 = bits(c_a_bits_a_mask_sizeOH_3, 0, 0)
node c_a_bits_a_mask_bit_3 = bits(nodeIn_3.c.bits.address, 0, 0)
node c_a_bits_a_mask_nbit_3 = eq(c_a_bits_a_mask_bit_3, UInt<1>(0h0))
node c_a_bits_a_mask_eq_24 = and(c_a_bits_a_mask_sub_0_2_3, c_a_bits_a_mask_nbit_3)
node _c_a_bits_a_mask_acc_T_24 = and(c_a_bits_a_mask_size_3, c_a_bits_a_mask_eq_24)
node c_a_bits_a_mask_acc_24 = or(c_a_bits_a_mask_sub_0_1_3, _c_a_bits_a_mask_acc_T_24)
node c_a_bits_a_mask_eq_25 = and(c_a_bits_a_mask_sub_0_2_3, c_a_bits_a_mask_bit_3)
node _c_a_bits_a_mask_acc_T_25 = and(c_a_bits_a_mask_size_3, c_a_bits_a_mask_eq_25)
node c_a_bits_a_mask_acc_25 = or(c_a_bits_a_mask_sub_0_1_3, _c_a_bits_a_mask_acc_T_25)
node c_a_bits_a_mask_eq_26 = and(c_a_bits_a_mask_sub_1_2_3, c_a_bits_a_mask_nbit_3)
node _c_a_bits_a_mask_acc_T_26 = and(c_a_bits_a_mask_size_3, c_a_bits_a_mask_eq_26)
node c_a_bits_a_mask_acc_26 = or(c_a_bits_a_mask_sub_1_1_3, _c_a_bits_a_mask_acc_T_26)
node c_a_bits_a_mask_eq_27 = and(c_a_bits_a_mask_sub_1_2_3, c_a_bits_a_mask_bit_3)
node _c_a_bits_a_mask_acc_T_27 = and(c_a_bits_a_mask_size_3, c_a_bits_a_mask_eq_27)
node c_a_bits_a_mask_acc_27 = or(c_a_bits_a_mask_sub_1_1_3, _c_a_bits_a_mask_acc_T_27)
node c_a_bits_a_mask_eq_28 = and(c_a_bits_a_mask_sub_2_2_3, c_a_bits_a_mask_nbit_3)
node _c_a_bits_a_mask_acc_T_28 = and(c_a_bits_a_mask_size_3, c_a_bits_a_mask_eq_28)
node c_a_bits_a_mask_acc_28 = or(c_a_bits_a_mask_sub_2_1_3, _c_a_bits_a_mask_acc_T_28)
node c_a_bits_a_mask_eq_29 = and(c_a_bits_a_mask_sub_2_2_3, c_a_bits_a_mask_bit_3)
node _c_a_bits_a_mask_acc_T_29 = and(c_a_bits_a_mask_size_3, c_a_bits_a_mask_eq_29)
node c_a_bits_a_mask_acc_29 = or(c_a_bits_a_mask_sub_2_1_3, _c_a_bits_a_mask_acc_T_29)
node c_a_bits_a_mask_eq_30 = and(c_a_bits_a_mask_sub_3_2_3, c_a_bits_a_mask_nbit_3)
node _c_a_bits_a_mask_acc_T_30 = and(c_a_bits_a_mask_size_3, c_a_bits_a_mask_eq_30)
node c_a_bits_a_mask_acc_30 = or(c_a_bits_a_mask_sub_3_1_3, _c_a_bits_a_mask_acc_T_30)
node c_a_bits_a_mask_eq_31 = and(c_a_bits_a_mask_sub_3_2_3, c_a_bits_a_mask_bit_3)
node _c_a_bits_a_mask_acc_T_31 = and(c_a_bits_a_mask_size_3, c_a_bits_a_mask_eq_31)
node c_a_bits_a_mask_acc_31 = or(c_a_bits_a_mask_sub_3_1_3, _c_a_bits_a_mask_acc_T_31)
node c_a_bits_a_mask_lo_lo_3 = cat(c_a_bits_a_mask_acc_25, c_a_bits_a_mask_acc_24)
node c_a_bits_a_mask_lo_hi_3 = cat(c_a_bits_a_mask_acc_27, c_a_bits_a_mask_acc_26)
node c_a_bits_a_mask_lo_3 = cat(c_a_bits_a_mask_lo_hi_3, c_a_bits_a_mask_lo_lo_3)
node c_a_bits_a_mask_hi_lo_3 = cat(c_a_bits_a_mask_acc_29, c_a_bits_a_mask_acc_28)
node c_a_bits_a_mask_hi_hi_3 = cat(c_a_bits_a_mask_acc_31, c_a_bits_a_mask_acc_30)
node c_a_bits_a_mask_hi_3 = cat(c_a_bits_a_mask_hi_hi_3, c_a_bits_a_mask_hi_lo_3)
node _c_a_bits_a_mask_T_3 = cat(c_a_bits_a_mask_hi_3, c_a_bits_a_mask_lo_3)
connect c_a_bits_a_3.mask, _c_a_bits_a_mask_T_3
connect c_a_bits_a_3.data, nodeIn_3.c.bits.data
connect c_a_bits_a_3.corrupt, nodeIn_3.c.bits.corrupt
connect c_a_3.bits, c_a_bits_a_3
wire c_d_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _c_d_valid_T_6 = eq(nodeIn_3.c.bits.opcode, UInt<3>(0h6))
node _c_d_valid_T_7 = and(nodeIn_3.c.valid, _c_d_valid_T_6)
connect c_d_3.valid, _c_d_valid_T_7
wire c_d_bits_d_3 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect c_d_bits_d_3.opcode, UInt<3>(0h6)
connect c_d_bits_d_3.param, UInt<1>(0h0)
connect c_d_bits_d_3.size, nodeIn_3.c.bits.size
connect c_d_bits_d_3.source, nodeIn_3.c.bits.source
connect c_d_bits_d_3.sink, UInt<1>(0h0)
connect c_d_bits_d_3.denied, UInt<1>(0h0)
invalidate c_d_bits_d_3.data
connect c_d_bits_d_3.corrupt, UInt<1>(0h0)
connect c_d_3.bits.corrupt, c_d_bits_d_3.corrupt
connect c_d_3.bits.data, c_d_bits_d_3.data
connect c_d_3.bits.denied, c_d_bits_d_3.denied
connect c_d_3.bits.sink, c_d_bits_d_3.sink
connect c_d_3.bits.source, c_d_bits_d_3.source
connect c_d_3.bits.size, c_d_bits_d_3.size
connect c_d_3.bits.param, c_d_bits_d_3.param
connect c_d_3.bits.opcode, c_d_bits_d_3.opcode
node _T_201 = eq(nodeIn_3.c.valid, UInt<1>(0h0))
node _T_202 = eq(nodeIn_3.c.bits.opcode, UInt<3>(0h6))
node _T_203 = or(_T_201, _T_202)
node _T_204 = eq(nodeIn_3.c.bits.opcode, UInt<3>(0h7))
node _T_205 = or(_T_203, _T_204)
node _T_206 = asUInt(reset)
node _T_207 = eq(_T_206, UInt<1>(0h0))
when _T_207 :
node _T_208 = eq(_T_205, UInt<1>(0h0))
when _T_208 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:116 assert (!in.c.valid || in.c.bits.opcode === Release || in.c.bits.opcode === ReleaseData)\n") : printf_18
assert(clock, _T_205, UInt<1>(0h1), "") : assert_18
node _nodeIn_c_ready_T_6 = eq(nodeIn_3.c.bits.opcode, UInt<3>(0h6))
node _nodeIn_c_ready_T_7 = mux(_nodeIn_c_ready_T_6, c_d_3.ready, c_a_3.ready)
connect nodeIn_3.c.ready, _nodeIn_c_ready_T_7
connect nodeIn_3.e.ready, UInt<1>(0h1)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.mask, UInt<8>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<5>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<2>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
connect _WIRE_25.ready, UInt<1>(0h0)
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.mask, UInt<8>(0h0)
connect _WIRE_26.bits.address, UInt<32>(0h0)
connect _WIRE_26.bits.source, UInt<5>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<2>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_209 = eq(_WIRE_27.valid, UInt<1>(0h0))
node _T_210 = asUInt(reset)
node _T_211 = eq(_T_210, UInt<1>(0h0))
when _T_211 :
node _T_212 = eq(_T_209, UInt<1>(0h0))
when _T_212 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:124 assert (!out.b.valid)\n") : printf_19
assert(clock, _T_209, UInt<1>(0h1), "") : assert_19
inst pool_3 of IDPool_3
connect pool_3.clock, clock
connect pool_3.reset, reset
node _pool_io_free_valid_T_3 = and(nodeIn_3.e.ready, nodeIn_3.e.valid)
connect pool_3.io.free.valid, _pool_io_free_valid_T_3
connect pool_3.io.free.bits, nodeIn_3.e.bits.sink
wire in_d_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _d_first_T_3 = and(in_d_3.ready, in_d_3.valid)
node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), in_d_3.bits.size)
node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0)
node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10)
node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3)
node d_first_beats1_opdata_3 = bits(in_d_3.bits.opcode, 0, 0)
node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0))
regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1))
node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1)
node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0))
node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1))
node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0))
node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7)
node d_first_done_3 = and(d_first_last_3, _d_first_T_3)
node _d_first_count_T_3 = not(d_first_counter1_3)
node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3)
when _d_first_T_3 :
node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3)
connect d_first_counter_3, _d_first_counter_T_3
node _d_grant_T_6 = eq(in_d_3.bits.opcode, UInt<3>(0h5))
node _d_grant_T_7 = eq(in_d_3.bits.opcode, UInt<3>(0h4))
node d_grant_3 = or(_d_grant_T_6, _d_grant_T_7)
node _pool_io_alloc_ready_T_9 = and(nodeIn_3.d.ready, nodeIn_3.d.valid)
node _pool_io_alloc_ready_T_10 = and(_pool_io_alloc_ready_T_9, d_first_3)
node _pool_io_alloc_ready_T_11 = and(_pool_io_alloc_ready_T_10, d_grant_3)
connect pool_3.io.alloc.ready, _pool_io_alloc_ready_T_11
node _nodeIn_d_valid_T_15 = eq(d_first_3, UInt<1>(0h0))
node _nodeIn_d_valid_T_16 = or(pool_3.io.alloc.valid, _nodeIn_d_valid_T_15)
node _nodeIn_d_valid_T_17 = eq(d_grant_3, UInt<1>(0h0))
node _nodeIn_d_valid_T_18 = or(_nodeIn_d_valid_T_16, _nodeIn_d_valid_T_17)
node _nodeIn_d_valid_T_19 = and(in_d_3.valid, _nodeIn_d_valid_T_18)
connect nodeIn_3.d.valid, _nodeIn_d_valid_T_19
node _in_d_ready_T_15 = eq(d_first_3, UInt<1>(0h0))
node _in_d_ready_T_16 = or(pool_3.io.alloc.valid, _in_d_ready_T_15)
node _in_d_ready_T_17 = eq(d_grant_3, UInt<1>(0h0))
node _in_d_ready_T_18 = or(_in_d_ready_T_16, _in_d_ready_T_17)
node _in_d_ready_T_19 = and(nodeIn_3.d.ready, _in_d_ready_T_18)
connect in_d_3.ready, _in_d_ready_T_19
connect nodeIn_3.d.bits.corrupt, in_d_3.bits.corrupt
connect nodeIn_3.d.bits.data, in_d_3.bits.data
connect nodeIn_3.d.bits.denied, in_d_3.bits.denied
connect nodeIn_3.d.bits.sink, in_d_3.bits.sink
connect nodeIn_3.d.bits.source, in_d_3.bits.source
connect nodeIn_3.d.bits.size, in_d_3.bits.size
connect nodeIn_3.d.bits.param, in_d_3.bits.param
connect nodeIn_3.d.bits.opcode, in_d_3.bits.opcode
reg nodeIn_d_bits_sink_r_3 : UInt<3>, clock
when d_first_3 :
connect nodeIn_d_bits_sink_r_3, pool_3.io.alloc.bits
node _nodeIn_d_bits_sink_T_3 = mux(d_first_3, pool_3.io.alloc.bits, nodeIn_d_bits_sink_r_3)
connect nodeIn_3.d.bits.sink, _nodeIn_d_bits_sink_T_3
wire d_d_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect d_d_3, x1_nodeOut_2.d
node _d_d_bits_source_T_3 = shr(x1_nodeOut_2.d.bits.source, 1)
connect d_d_3.bits.source, _d_d_bits_source_T_3
reg wSourceVec_3 : UInt<1>[10], clock
node _aWOk_T_15 = xor(nodeIn_3.a.bits.address, UInt<1>(0h0))
node _aWOk_T_16 = cvt(_aWOk_T_15)
node _aWOk_T_17 = and(_aWOk_T_16, asSInt(UInt<1>(0h0)))
node _aWOk_T_18 = asSInt(_aWOk_T_17)
node _aWOk_T_19 = eq(_aWOk_T_18, asSInt(UInt<1>(0h0)))
node _bypass_T_6 = and(UInt<1>(0h0), nodeIn_3.a.valid)
node _bypass_T_7 = eq(nodeIn_3.a.bits.source, d_d_3.bits.source)
node bypass_3 = and(_bypass_T_6, _bypass_T_7)
node _dWHeld_T_3 = mux(bypass_3, UInt<1>(0h1), wSourceVec_3[d_d_3.bits.source])
reg dWHeld_r_3 : UInt<1>, clock
when d_first_3 :
connect dWHeld_r_3, _dWHeld_T_3
node dWHeld_3 = mux(d_first_3, _dWHeld_T_3, dWHeld_r_3)
node _T_213 = and(nodeIn_3.a.ready, nodeIn_3.a.valid)
when _T_213 :
connect wSourceVec_3[nodeIn_3.a.bits.source], UInt<1>(0h1)
node _T_214 = eq(x1_nodeOut_2.d.bits.opcode, UInt<1>(0h1))
node _T_215 = bits(x1_nodeOut_2.d.bits.source, 0, 0)
node _T_216 = and(_T_214, _T_215)
when _T_216 :
connect d_d_3.bits.opcode, UInt<3>(0h5)
node _d_d_bits_param_T_3 = mux(dWHeld_3, UInt<2>(0h0), UInt<2>(0h1))
connect d_d_3.bits.param, _d_d_bits_param_T_3
node _T_217 = eq(x1_nodeOut_2.d.bits.opcode, UInt<1>(0h0))
node _T_218 = bits(x1_nodeOut_2.d.bits.source, 0, 0)
node _T_219 = eq(_T_218, UInt<1>(0h0))
node _T_220 = and(_T_217, _T_219)
when _T_220 :
connect d_d_3.bits.opcode, UInt<3>(0h6)
node _decode_T_27 = dshl(UInt<6>(0h3f), c_a_3.bits.size)
node _decode_T_28 = bits(_decode_T_27, 5, 0)
node _decode_T_29 = not(_decode_T_28)
node decode_9 = shr(_decode_T_29, 3)
node _opdata_T_6 = bits(c_a_3.bits.opcode, 2, 2)
node opdata_9 = eq(_opdata_T_6, UInt<1>(0h0))
node _T_221 = mux(opdata_9, decode_9, UInt<1>(0h0))
node _decode_T_30 = dshl(UInt<6>(0h3f), a_a_3.bits.size)
node _decode_T_31 = bits(_decode_T_30, 5, 0)
node _decode_T_32 = not(_decode_T_31)
node decode_10 = shr(_decode_T_32, 3)
node _opdata_T_7 = bits(a_a_3.bits.opcode, 2, 2)
node opdata_10 = eq(_opdata_T_7, UInt<1>(0h0))
node _T_222 = mux(opdata_10, decode_10, UInt<1>(0h0))
regreset beatsLeft_6 : UInt, clock, reset, UInt<1>(0h0)
node idle_6 = eq(beatsLeft_6, UInt<1>(0h0))
node latch_6 = and(idle_6, x1_nodeOut_2.a.ready)
node _readys_T_72 = cat(a_a_3.valid, c_a_3.valid)
node _readys_T_73 = shl(_readys_T_72, 1)
node _readys_T_74 = bits(_readys_T_73, 1, 0)
node _readys_T_75 = or(_readys_T_72, _readys_T_74)
node _readys_T_76 = bits(_readys_T_75, 1, 0)
node _readys_T_77 = shl(_readys_T_76, 1)
node _readys_T_78 = bits(_readys_T_77, 1, 0)
node _readys_T_79 = not(_readys_T_78)
node _readys_T_80 = bits(_readys_T_79, 0, 0)
node _readys_T_81 = bits(_readys_T_79, 1, 1)
wire readys_6 : UInt<1>[2]
connect readys_6[0], _readys_T_80
connect readys_6[1], _readys_T_81
node _winner_T_15 = and(readys_6[0], c_a_3.valid)
node _winner_T_16 = and(readys_6[1], a_a_3.valid)
wire winner_6 : UInt<1>[2]
connect winner_6[0], _winner_T_15
connect winner_6[1], _winner_T_16
node prefixOR_1_6 = or(UInt<1>(0h0), winner_6[0])
node _prefixOR_T_6 = or(prefixOR_1_6, winner_6[1])
node _T_223 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_224 = eq(winner_6[0], UInt<1>(0h0))
node _T_225 = or(_T_223, _T_224)
node _T_226 = eq(prefixOR_1_6, UInt<1>(0h0))
node _T_227 = eq(winner_6[1], UInt<1>(0h0))
node _T_228 = or(_T_226, _T_227)
node _T_229 = and(_T_225, _T_228)
node _T_230 = asUInt(reset)
node _T_231 = eq(_T_230, UInt<1>(0h0))
when _T_231 :
node _T_232 = eq(_T_229, UInt<1>(0h0))
when _T_232 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_20
assert(clock, _T_229, UInt<1>(0h1), "") : assert_20
node _T_233 = or(c_a_3.valid, a_a_3.valid)
node _T_234 = eq(_T_233, UInt<1>(0h0))
node _T_235 = or(winner_6[0], winner_6[1])
node _T_236 = or(_T_234, _T_235)
node _T_237 = asUInt(reset)
node _T_238 = eq(_T_237, UInt<1>(0h0))
when _T_238 :
node _T_239 = eq(_T_236, UInt<1>(0h0))
when _T_239 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_21
assert(clock, _T_236, UInt<1>(0h1), "") : assert_21
node maskedBeats_0_6 = mux(winner_6[0], _T_221, UInt<1>(0h0))
node maskedBeats_1_6 = mux(winner_6[1], _T_222, UInt<1>(0h0))
node initBeats_6 = or(maskedBeats_0_6, maskedBeats_1_6)
node _beatsLeft_T_24 = and(x1_nodeOut_2.a.ready, x1_nodeOut_2.a.valid)
node _beatsLeft_T_25 = sub(beatsLeft_6, _beatsLeft_T_24)
node _beatsLeft_T_26 = tail(_beatsLeft_T_25, 1)
node _beatsLeft_T_27 = mux(latch_6, initBeats_6, _beatsLeft_T_26)
connect beatsLeft_6, _beatsLeft_T_27
wire _state_WIRE_6 : UInt<1>[2]
connect _state_WIRE_6[0], UInt<1>(0h0)
connect _state_WIRE_6[1], UInt<1>(0h0)
regreset state_6 : UInt<1>[2], clock, reset, _state_WIRE_6
node muxState_6 = mux(idle_6, winner_6, state_6)
connect state_6, muxState_6
node allowed_6 = mux(idle_6, readys_6, state_6)
node _c_a_ready_T_3 = and(x1_nodeOut_2.a.ready, allowed_6[0])
connect c_a_3.ready, _c_a_ready_T_3
node _a_a_ready_T_3 = and(x1_nodeOut_2.a.ready, allowed_6[1])
connect a_a_3.ready, _a_a_ready_T_3
node _nodeOut_a_valid_T_15 = or(c_a_3.valid, a_a_3.valid)
node _nodeOut_a_valid_T_16 = mux(state_6[0], c_a_3.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_17 = mux(state_6[1], a_a_3.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_18 = or(_nodeOut_a_valid_T_16, _nodeOut_a_valid_T_17)
wire _nodeOut_a_valid_WIRE_3 : UInt<1>
connect _nodeOut_a_valid_WIRE_3, _nodeOut_a_valid_T_18
node _nodeOut_a_valid_T_19 = mux(idle_6, _nodeOut_a_valid_T_15, _nodeOut_a_valid_WIRE_3)
connect x1_nodeOut_2.a.valid, _nodeOut_a_valid_T_19
wire _nodeOut_a_bits_WIRE_33 : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _nodeOut_a_bits_T_72 = mux(muxState_6[0], c_a_3.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_73 = mux(muxState_6[1], a_a_3.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_74 = or(_nodeOut_a_bits_T_72, _nodeOut_a_bits_T_73)
wire _nodeOut_a_bits_WIRE_34 : UInt<1>
connect _nodeOut_a_bits_WIRE_34, _nodeOut_a_bits_T_74
connect _nodeOut_a_bits_WIRE_33.corrupt, _nodeOut_a_bits_WIRE_34
node _nodeOut_a_bits_T_75 = mux(muxState_6[0], c_a_3.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_76 = mux(muxState_6[1], a_a_3.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_77 = or(_nodeOut_a_bits_T_75, _nodeOut_a_bits_T_76)
wire _nodeOut_a_bits_WIRE_35 : UInt<64>
connect _nodeOut_a_bits_WIRE_35, _nodeOut_a_bits_T_77
connect _nodeOut_a_bits_WIRE_33.data, _nodeOut_a_bits_WIRE_35
node _nodeOut_a_bits_T_78 = mux(muxState_6[0], c_a_3.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_79 = mux(muxState_6[1], a_a_3.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_80 = or(_nodeOut_a_bits_T_78, _nodeOut_a_bits_T_79)
wire _nodeOut_a_bits_WIRE_36 : UInt<8>
connect _nodeOut_a_bits_WIRE_36, _nodeOut_a_bits_T_80
connect _nodeOut_a_bits_WIRE_33.mask, _nodeOut_a_bits_WIRE_36
wire _nodeOut_a_bits_WIRE_37 : { }
connect _nodeOut_a_bits_WIRE_33.echo, _nodeOut_a_bits_WIRE_37
wire _nodeOut_a_bits_WIRE_38 : { }
connect _nodeOut_a_bits_WIRE_33.user, _nodeOut_a_bits_WIRE_38
node _nodeOut_a_bits_T_81 = mux(muxState_6[0], c_a_3.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_82 = mux(muxState_6[1], a_a_3.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_83 = or(_nodeOut_a_bits_T_81, _nodeOut_a_bits_T_82)
wire _nodeOut_a_bits_WIRE_39 : UInt<32>
connect _nodeOut_a_bits_WIRE_39, _nodeOut_a_bits_T_83
connect _nodeOut_a_bits_WIRE_33.address, _nodeOut_a_bits_WIRE_39
node _nodeOut_a_bits_T_84 = mux(muxState_6[0], c_a_3.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_85 = mux(muxState_6[1], a_a_3.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_86 = or(_nodeOut_a_bits_T_84, _nodeOut_a_bits_T_85)
wire _nodeOut_a_bits_WIRE_40 : UInt<5>
connect _nodeOut_a_bits_WIRE_40, _nodeOut_a_bits_T_86
connect _nodeOut_a_bits_WIRE_33.source, _nodeOut_a_bits_WIRE_40
node _nodeOut_a_bits_T_87 = mux(muxState_6[0], c_a_3.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_88 = mux(muxState_6[1], a_a_3.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_89 = or(_nodeOut_a_bits_T_87, _nodeOut_a_bits_T_88)
wire _nodeOut_a_bits_WIRE_41 : UInt<3>
connect _nodeOut_a_bits_WIRE_41, _nodeOut_a_bits_T_89
connect _nodeOut_a_bits_WIRE_33.size, _nodeOut_a_bits_WIRE_41
node _nodeOut_a_bits_T_90 = mux(muxState_6[0], c_a_3.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_91 = mux(muxState_6[1], a_a_3.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_92 = or(_nodeOut_a_bits_T_90, _nodeOut_a_bits_T_91)
wire _nodeOut_a_bits_WIRE_42 : UInt<3>
connect _nodeOut_a_bits_WIRE_42, _nodeOut_a_bits_T_92
connect _nodeOut_a_bits_WIRE_33.param, _nodeOut_a_bits_WIRE_42
node _nodeOut_a_bits_T_93 = mux(muxState_6[0], c_a_3.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_94 = mux(muxState_6[1], a_a_3.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_95 = or(_nodeOut_a_bits_T_93, _nodeOut_a_bits_T_94)
wire _nodeOut_a_bits_WIRE_43 : UInt<3>
connect _nodeOut_a_bits_WIRE_43, _nodeOut_a_bits_T_95
connect _nodeOut_a_bits_WIRE_33.opcode, _nodeOut_a_bits_WIRE_43
connect x1_nodeOut_2.a.bits.corrupt, _nodeOut_a_bits_WIRE_33.corrupt
connect x1_nodeOut_2.a.bits.data, _nodeOut_a_bits_WIRE_33.data
connect x1_nodeOut_2.a.bits.mask, _nodeOut_a_bits_WIRE_33.mask
connect x1_nodeOut_2.a.bits.address, _nodeOut_a_bits_WIRE_33.address
connect x1_nodeOut_2.a.bits.source, _nodeOut_a_bits_WIRE_33.source
connect x1_nodeOut_2.a.bits.size, _nodeOut_a_bits_WIRE_33.size
connect x1_nodeOut_2.a.bits.param, _nodeOut_a_bits_WIRE_33.param
connect x1_nodeOut_2.a.bits.opcode, _nodeOut_a_bits_WIRE_33.opcode
node _decode_T_33 = dshl(UInt<6>(0h3f), d_d_3.bits.size)
node _decode_T_34 = bits(_decode_T_33, 5, 0)
node _decode_T_35 = not(_decode_T_34)
node decode_11 = shr(_decode_T_35, 3)
node opdata_11 = bits(d_d_3.bits.opcode, 0, 0)
node _T_240 = mux(opdata_11, decode_11, UInt<1>(0h0))
inst q_6 of Queue2_TLBundleD_a32d64s4k3z3c_14
connect q_6.clock, clock
connect q_6.reset, reset
connect q_6.io.enq.valid, c_d_3.valid
connect q_6.io.enq.bits.corrupt, c_d_3.bits.corrupt
connect q_6.io.enq.bits.data, c_d_3.bits.data
connect q_6.io.enq.bits.denied, c_d_3.bits.denied
connect q_6.io.enq.bits.sink, c_d_3.bits.sink
connect q_6.io.enq.bits.source, c_d_3.bits.source
connect q_6.io.enq.bits.size, c_d_3.bits.size
connect q_6.io.enq.bits.param, c_d_3.bits.param
connect q_6.io.enq.bits.opcode, c_d_3.bits.opcode
connect c_d_3.ready, q_6.io.enq.ready
inst q_7 of Queue2_TLBundleD_a32d64s4k3z3c_15
connect q_7.clock, clock
connect q_7.reset, reset
connect q_7.io.enq.valid, a_d_3.valid
connect q_7.io.enq.bits.corrupt, a_d_3.bits.corrupt
connect q_7.io.enq.bits.data, a_d_3.bits.data
connect q_7.io.enq.bits.denied, a_d_3.bits.denied
connect q_7.io.enq.bits.sink, a_d_3.bits.sink
connect q_7.io.enq.bits.source, a_d_3.bits.source
connect q_7.io.enq.bits.size, a_d_3.bits.size
connect q_7.io.enq.bits.param, a_d_3.bits.param
connect q_7.io.enq.bits.opcode, a_d_3.bits.opcode
connect a_d_3.ready, q_7.io.enq.ready
regreset beatsLeft_7 : UInt, clock, reset, UInt<1>(0h0)
node idle_7 = eq(beatsLeft_7, UInt<1>(0h0))
node latch_7 = and(idle_7, in_d_3.ready)
node readys_hi_3 = cat(q_7.io.deq.valid, q_6.io.deq.valid)
node _readys_T_82 = cat(readys_hi_3, d_d_3.valid)
node _readys_T_83 = shl(_readys_T_82, 1)
node _readys_T_84 = bits(_readys_T_83, 2, 0)
node _readys_T_85 = or(_readys_T_82, _readys_T_84)
node _readys_T_86 = shl(_readys_T_85, 2)
node _readys_T_87 = bits(_readys_T_86, 2, 0)
node _readys_T_88 = or(_readys_T_85, _readys_T_87)
node _readys_T_89 = bits(_readys_T_88, 2, 0)
node _readys_T_90 = shl(_readys_T_89, 1)
node _readys_T_91 = bits(_readys_T_90, 2, 0)
node _readys_T_92 = not(_readys_T_91)
node _readys_T_93 = bits(_readys_T_92, 0, 0)
node _readys_T_94 = bits(_readys_T_92, 1, 1)
node _readys_T_95 = bits(_readys_T_92, 2, 2)
wire readys_7 : UInt<1>[3]
connect readys_7[0], _readys_T_93
connect readys_7[1], _readys_T_94
connect readys_7[2], _readys_T_95
node _winner_T_17 = and(readys_7[0], d_d_3.valid)
node _winner_T_18 = and(readys_7[1], q_6.io.deq.valid)
node _winner_T_19 = and(readys_7[2], q_7.io.deq.valid)
wire winner_7 : UInt<1>[3]
connect winner_7[0], _winner_T_17
connect winner_7[1], _winner_T_18
connect winner_7[2], _winner_T_19
node prefixOR_1_7 = or(UInt<1>(0h0), winner_7[0])
node prefixOR_2_3 = or(prefixOR_1_7, winner_7[1])
node _prefixOR_T_7 = or(prefixOR_2_3, winner_7[2])
node _T_241 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_242 = eq(winner_7[0], UInt<1>(0h0))
node _T_243 = or(_T_241, _T_242)
node _T_244 = eq(prefixOR_1_7, UInt<1>(0h0))
node _T_245 = eq(winner_7[1], UInt<1>(0h0))
node _T_246 = or(_T_244, _T_245)
node _T_247 = eq(prefixOR_2_3, UInt<1>(0h0))
node _T_248 = eq(winner_7[2], UInt<1>(0h0))
node _T_249 = or(_T_247, _T_248)
node _T_250 = and(_T_243, _T_246)
node _T_251 = and(_T_250, _T_249)
node _T_252 = asUInt(reset)
node _T_253 = eq(_T_252, UInt<1>(0h0))
when _T_253 :
node _T_254 = eq(_T_251, UInt<1>(0h0))
when _T_254 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_22
assert(clock, _T_251, UInt<1>(0h1), "") : assert_22
node _T_255 = or(d_d_3.valid, q_6.io.deq.valid)
node _T_256 = or(_T_255, q_7.io.deq.valid)
node _T_257 = eq(_T_256, UInt<1>(0h0))
node _T_258 = or(winner_7[0], winner_7[1])
node _T_259 = or(_T_258, winner_7[2])
node _T_260 = or(_T_257, _T_259)
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_23
assert(clock, _T_260, UInt<1>(0h1), "") : assert_23
node maskedBeats_0_7 = mux(winner_7[0], _T_240, UInt<1>(0h0))
node maskedBeats_1_7 = mux(winner_7[1], UInt<1>(0h0), UInt<1>(0h0))
node maskedBeats_2_3 = mux(winner_7[2], UInt<1>(0h0), UInt<1>(0h0))
node _initBeats_T_3 = or(maskedBeats_0_7, maskedBeats_1_7)
node initBeats_7 = or(_initBeats_T_3, maskedBeats_2_3)
node _beatsLeft_T_28 = and(in_d_3.ready, in_d_3.valid)
node _beatsLeft_T_29 = sub(beatsLeft_7, _beatsLeft_T_28)
node _beatsLeft_T_30 = tail(_beatsLeft_T_29, 1)
node _beatsLeft_T_31 = mux(latch_7, initBeats_7, _beatsLeft_T_30)
connect beatsLeft_7, _beatsLeft_T_31
wire _state_WIRE_7 : UInt<1>[3]
connect _state_WIRE_7[0], UInt<1>(0h0)
connect _state_WIRE_7[1], UInt<1>(0h0)
connect _state_WIRE_7[2], UInt<1>(0h0)
regreset state_7 : UInt<1>[3], clock, reset, _state_WIRE_7
node muxState_7 = mux(idle_7, winner_7, state_7)
connect state_7, muxState_7
node allowed_7 = mux(idle_7, readys_7, state_7)
node _d_d_ready_T_3 = and(in_d_3.ready, allowed_7[0])
connect d_d_3.ready, _d_d_ready_T_3
node _q_io_deq_ready_T_6 = and(in_d_3.ready, allowed_7[1])
connect q_6.io.deq.ready, _q_io_deq_ready_T_6
node _q_io_deq_ready_T_7 = and(in_d_3.ready, allowed_7[2])
connect q_7.io.deq.ready, _q_io_deq_ready_T_7
node _in_d_valid_T_24 = or(d_d_3.valid, q_6.io.deq.valid)
node _in_d_valid_T_25 = or(_in_d_valid_T_24, q_7.io.deq.valid)
node _in_d_valid_T_26 = mux(state_7[0], d_d_3.valid, UInt<1>(0h0))
node _in_d_valid_T_27 = mux(state_7[1], q_6.io.deq.valid, UInt<1>(0h0))
node _in_d_valid_T_28 = mux(state_7[2], q_7.io.deq.valid, UInt<1>(0h0))
node _in_d_valid_T_29 = or(_in_d_valid_T_26, _in_d_valid_T_27)
node _in_d_valid_T_30 = or(_in_d_valid_T_29, _in_d_valid_T_28)
wire _in_d_valid_WIRE_3 : UInt<1>
connect _in_d_valid_WIRE_3, _in_d_valid_T_30
node _in_d_valid_T_31 = mux(idle_7, _in_d_valid_T_25, _in_d_valid_WIRE_3)
connect in_d_3.valid, _in_d_valid_T_31
wire _in_d_bits_WIRE_33 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_d_bits_T_120 = mux(muxState_7[0], d_d_3.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_121 = mux(muxState_7[1], q_6.io.deq.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_122 = mux(muxState_7[2], q_7.io.deq.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_123 = or(_in_d_bits_T_120, _in_d_bits_T_121)
node _in_d_bits_T_124 = or(_in_d_bits_T_123, _in_d_bits_T_122)
wire _in_d_bits_WIRE_34 : UInt<1>
connect _in_d_bits_WIRE_34, _in_d_bits_T_124
connect _in_d_bits_WIRE_33.corrupt, _in_d_bits_WIRE_34
node _in_d_bits_T_125 = mux(muxState_7[0], d_d_3.bits.data, UInt<1>(0h0))
node _in_d_bits_T_126 = mux(muxState_7[1], q_6.io.deq.bits.data, UInt<1>(0h0))
node _in_d_bits_T_127 = mux(muxState_7[2], q_7.io.deq.bits.data, UInt<1>(0h0))
node _in_d_bits_T_128 = or(_in_d_bits_T_125, _in_d_bits_T_126)
node _in_d_bits_T_129 = or(_in_d_bits_T_128, _in_d_bits_T_127)
wire _in_d_bits_WIRE_35 : UInt<64>
connect _in_d_bits_WIRE_35, _in_d_bits_T_129
connect _in_d_bits_WIRE_33.data, _in_d_bits_WIRE_35
wire _in_d_bits_WIRE_36 : { }
connect _in_d_bits_WIRE_33.echo, _in_d_bits_WIRE_36
wire _in_d_bits_WIRE_37 : { }
connect _in_d_bits_WIRE_33.user, _in_d_bits_WIRE_37
node _in_d_bits_T_130 = mux(muxState_7[0], d_d_3.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_131 = mux(muxState_7[1], q_6.io.deq.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_132 = mux(muxState_7[2], q_7.io.deq.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_133 = or(_in_d_bits_T_130, _in_d_bits_T_131)
node _in_d_bits_T_134 = or(_in_d_bits_T_133, _in_d_bits_T_132)
wire _in_d_bits_WIRE_38 : UInt<1>
connect _in_d_bits_WIRE_38, _in_d_bits_T_134
connect _in_d_bits_WIRE_33.denied, _in_d_bits_WIRE_38
node _in_d_bits_T_135 = mux(muxState_7[0], d_d_3.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_136 = mux(muxState_7[1], q_6.io.deq.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_137 = mux(muxState_7[2], q_7.io.deq.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_138 = or(_in_d_bits_T_135, _in_d_bits_T_136)
node _in_d_bits_T_139 = or(_in_d_bits_T_138, _in_d_bits_T_137)
wire _in_d_bits_WIRE_39 : UInt<3>
connect _in_d_bits_WIRE_39, _in_d_bits_T_139
connect _in_d_bits_WIRE_33.sink, _in_d_bits_WIRE_39
node _in_d_bits_T_140 = mux(muxState_7[0], d_d_3.bits.source, UInt<1>(0h0))
node _in_d_bits_T_141 = mux(muxState_7[1], q_6.io.deq.bits.source, UInt<1>(0h0))
node _in_d_bits_T_142 = mux(muxState_7[2], q_7.io.deq.bits.source, UInt<1>(0h0))
node _in_d_bits_T_143 = or(_in_d_bits_T_140, _in_d_bits_T_141)
node _in_d_bits_T_144 = or(_in_d_bits_T_143, _in_d_bits_T_142)
wire _in_d_bits_WIRE_40 : UInt<4>
connect _in_d_bits_WIRE_40, _in_d_bits_T_144
connect _in_d_bits_WIRE_33.source, _in_d_bits_WIRE_40
node _in_d_bits_T_145 = mux(muxState_7[0], d_d_3.bits.size, UInt<1>(0h0))
node _in_d_bits_T_146 = mux(muxState_7[1], q_6.io.deq.bits.size, UInt<1>(0h0))
node _in_d_bits_T_147 = mux(muxState_7[2], q_7.io.deq.bits.size, UInt<1>(0h0))
node _in_d_bits_T_148 = or(_in_d_bits_T_145, _in_d_bits_T_146)
node _in_d_bits_T_149 = or(_in_d_bits_T_148, _in_d_bits_T_147)
wire _in_d_bits_WIRE_41 : UInt<3>
connect _in_d_bits_WIRE_41, _in_d_bits_T_149
connect _in_d_bits_WIRE_33.size, _in_d_bits_WIRE_41
node _in_d_bits_T_150 = mux(muxState_7[0], d_d_3.bits.param, UInt<1>(0h0))
node _in_d_bits_T_151 = mux(muxState_7[1], q_6.io.deq.bits.param, UInt<1>(0h0))
node _in_d_bits_T_152 = mux(muxState_7[2], q_7.io.deq.bits.param, UInt<1>(0h0))
node _in_d_bits_T_153 = or(_in_d_bits_T_150, _in_d_bits_T_151)
node _in_d_bits_T_154 = or(_in_d_bits_T_153, _in_d_bits_T_152)
wire _in_d_bits_WIRE_42 : UInt<2>
connect _in_d_bits_WIRE_42, _in_d_bits_T_154
connect _in_d_bits_WIRE_33.param, _in_d_bits_WIRE_42
node _in_d_bits_T_155 = mux(muxState_7[0], d_d_3.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_156 = mux(muxState_7[1], q_6.io.deq.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_157 = mux(muxState_7[2], q_7.io.deq.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_158 = or(_in_d_bits_T_155, _in_d_bits_T_156)
node _in_d_bits_T_159 = or(_in_d_bits_T_158, _in_d_bits_T_157)
wire _in_d_bits_WIRE_43 : UInt<3>
connect _in_d_bits_WIRE_43, _in_d_bits_T_159
connect _in_d_bits_WIRE_33.opcode, _in_d_bits_WIRE_43
connect in_d_3.bits.corrupt, _in_d_bits_WIRE_33.corrupt
connect in_d_3.bits.data, _in_d_bits_WIRE_33.data
connect in_d_3.bits.denied, _in_d_bits_WIRE_33.denied
connect in_d_3.bits.sink, _in_d_bits_WIRE_33.sink
connect in_d_3.bits.source, _in_d_bits_WIRE_33.source
connect in_d_3.bits.size, _in_d_bits_WIRE_33.size
connect in_d_3.bits.param, _in_d_bits_WIRE_33.param
connect in_d_3.bits.opcode, _in_d_bits_WIRE_33.opcode
connect nodeIn_3.b.valid, UInt<1>(0h0)
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<32>(0h0)
connect _WIRE_28.bits.source, UInt<5>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
connect _WIRE_29.valid, UInt<1>(0h0)
wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_30.bits.sink, UInt<1>(0h0)
connect _WIRE_30.valid, UInt<1>(0h0)
connect _WIRE_30.ready, UInt<1>(0h0)
wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_31.bits, _WIRE_30.bits
connect _WIRE_31.valid, _WIRE_30.valid
connect _WIRE_31.ready, _WIRE_30.ready
connect _WIRE_31.valid, UInt<1>(0h0)
wire a_a_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
wire a_d_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _isPut_T_8 = eq(nodeIn_4.a.bits.opcode, UInt<1>(0h0))
node _isPut_T_9 = eq(nodeIn_4.a.bits.opcode, UInt<1>(0h1))
node isPut_4 = or(_isPut_T_8, _isPut_T_9)
node _toD_T_16 = eq(nodeIn_4.a.bits.opcode, UInt<3>(0h6))
node _toD_T_17 = eq(nodeIn_4.a.bits.param, UInt<2>(0h2))
node _toD_T_18 = and(_toD_T_16, _toD_T_17)
node _toD_T_19 = eq(nodeIn_4.a.bits.opcode, UInt<3>(0h7))
node toD_4 = or(_toD_T_18, _toD_T_19)
node _nodeIn_a_ready_T_4 = mux(toD_4, a_d_4.ready, a_a_4.ready)
connect nodeIn_4.a.ready, _nodeIn_a_ready_T_4
node _a_a_valid_T_8 = eq(toD_4, UInt<1>(0h0))
node _a_a_valid_T_9 = and(nodeIn_4.a.valid, _a_a_valid_T_8)
connect a_a_4.valid, _a_a_valid_T_9
connect a_a_4.bits, nodeIn_4.a.bits
node _a_a_bits_source_T_20 = shl(nodeIn_4.a.bits.source, 1)
node _a_a_bits_source_T_21 = mux(isPut_4, UInt<1>(0h1), UInt<1>(0h0))
node _a_a_bits_source_T_22 = or(_a_a_bits_source_T_20, _a_a_bits_source_T_21)
connect a_a_4.bits.source, _a_a_bits_source_T_22
node _T_264 = eq(nodeIn_4.a.bits.opcode, UInt<3>(0h6))
node _T_265 = eq(nodeIn_4.a.bits.opcode, UInt<3>(0h7))
node _T_266 = or(_T_264, _T_265)
when _T_266 :
connect a_a_4.bits.opcode, UInt<3>(0h4)
connect a_a_4.bits.param, UInt<1>(0h0)
node _a_a_bits_source_T_23 = shl(nodeIn_4.a.bits.source, 1)
node _a_a_bits_source_T_24 = or(_a_a_bits_source_T_23, UInt<1>(0h1))
connect a_a_4.bits.source, _a_a_bits_source_T_24
node _a_d_valid_T_4 = and(nodeIn_4.a.valid, toD_4)
connect a_d_4.valid, _a_d_valid_T_4
wire a_d_bits_d_4 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect a_d_bits_d_4.opcode, UInt<3>(0h4)
connect a_d_bits_d_4.param, UInt<2>(0h0)
connect a_d_bits_d_4.size, nodeIn_4.a.bits.size
connect a_d_bits_d_4.source, nodeIn_4.a.bits.source
connect a_d_bits_d_4.sink, UInt<1>(0h0)
connect a_d_bits_d_4.denied, UInt<1>(0h0)
invalidate a_d_bits_d_4.data
connect a_d_bits_d_4.corrupt, UInt<1>(0h0)
connect a_d_4.bits.corrupt, a_d_bits_d_4.corrupt
connect a_d_4.bits.data, a_d_bits_d_4.data
connect a_d_4.bits.denied, a_d_bits_d_4.denied
connect a_d_4.bits.sink, a_d_bits_d_4.sink
connect a_d_4.bits.source, a_d_bits_d_4.source
connect a_d_4.bits.size, a_d_bits_d_4.size
connect a_d_4.bits.param, a_d_bits_d_4.param
connect a_d_4.bits.opcode, a_d_bits_d_4.opcode
wire c_a_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
node _c_a_valid_T_8 = eq(nodeIn_4.c.bits.opcode, UInt<3>(0h7))
node _c_a_valid_T_9 = and(nodeIn_4.c.valid, _c_a_valid_T_8)
connect c_a_4.valid, _c_a_valid_T_9
node _c_a_bits_T_4 = shl(nodeIn_4.c.bits.source, 1)
node _c_a_bits_legal_T_40 = leq(UInt<1>(0h0), nodeIn_4.c.bits.size)
node _c_a_bits_legal_T_41 = leq(nodeIn_4.c.bits.size, UInt<3>(0h6))
node _c_a_bits_legal_T_42 = and(_c_a_bits_legal_T_40, _c_a_bits_legal_T_41)
node _c_a_bits_legal_T_43 = or(UInt<1>(0h0), _c_a_bits_legal_T_42)
node _c_a_bits_legal_T_44 = xor(nodeIn_4.c.bits.address, UInt<1>(0h0))
node _c_a_bits_legal_T_45 = cvt(_c_a_bits_legal_T_44)
node _c_a_bits_legal_T_46 = and(_c_a_bits_legal_T_45, asSInt(UInt<1>(0h0)))
node _c_a_bits_legal_T_47 = asSInt(_c_a_bits_legal_T_46)
node _c_a_bits_legal_T_48 = eq(_c_a_bits_legal_T_47, asSInt(UInt<1>(0h0)))
node _c_a_bits_legal_T_49 = and(_c_a_bits_legal_T_43, _c_a_bits_legal_T_48)
node c_a_bits_legal_4 = or(UInt<1>(0h0), _c_a_bits_legal_T_49)
wire c_a_bits_a_4 : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect c_a_bits_a_4.opcode, UInt<1>(0h0)
connect c_a_bits_a_4.param, UInt<1>(0h0)
connect c_a_bits_a_4.size, nodeIn_4.c.bits.size
connect c_a_bits_a_4.source, _c_a_bits_T_4
connect c_a_bits_a_4.address, nodeIn_4.c.bits.address
node _c_a_bits_a_mask_sizeOH_T_12 = or(nodeIn_4.c.bits.size, UInt<3>(0h0))
node c_a_bits_a_mask_sizeOH_shiftAmount_4 = bits(_c_a_bits_a_mask_sizeOH_T_12, 1, 0)
node _c_a_bits_a_mask_sizeOH_T_13 = dshl(UInt<1>(0h1), c_a_bits_a_mask_sizeOH_shiftAmount_4)
node _c_a_bits_a_mask_sizeOH_T_14 = bits(_c_a_bits_a_mask_sizeOH_T_13, 2, 0)
node c_a_bits_a_mask_sizeOH_4 = or(_c_a_bits_a_mask_sizeOH_T_14, UInt<1>(0h1))
node c_a_bits_a_mask_sub_sub_sub_0_1_4 = geq(nodeIn_4.c.bits.size, UInt<2>(0h3))
node c_a_bits_a_mask_sub_sub_size_4 = bits(c_a_bits_a_mask_sizeOH_4, 2, 2)
node c_a_bits_a_mask_sub_sub_bit_4 = bits(nodeIn_4.c.bits.address, 2, 2)
node c_a_bits_a_mask_sub_sub_nbit_4 = eq(c_a_bits_a_mask_sub_sub_bit_4, UInt<1>(0h0))
node c_a_bits_a_mask_sub_sub_0_2_4 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_nbit_4)
node _c_a_bits_a_mask_sub_sub_acc_T_8 = and(c_a_bits_a_mask_sub_sub_size_4, c_a_bits_a_mask_sub_sub_0_2_4)
node c_a_bits_a_mask_sub_sub_0_1_4 = or(c_a_bits_a_mask_sub_sub_sub_0_1_4, _c_a_bits_a_mask_sub_sub_acc_T_8)
node c_a_bits_a_mask_sub_sub_1_2_4 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_bit_4)
node _c_a_bits_a_mask_sub_sub_acc_T_9 = and(c_a_bits_a_mask_sub_sub_size_4, c_a_bits_a_mask_sub_sub_1_2_4)
node c_a_bits_a_mask_sub_sub_1_1_4 = or(c_a_bits_a_mask_sub_sub_sub_0_1_4, _c_a_bits_a_mask_sub_sub_acc_T_9)
node c_a_bits_a_mask_sub_size_4 = bits(c_a_bits_a_mask_sizeOH_4, 1, 1)
node c_a_bits_a_mask_sub_bit_4 = bits(nodeIn_4.c.bits.address, 1, 1)
node c_a_bits_a_mask_sub_nbit_4 = eq(c_a_bits_a_mask_sub_bit_4, UInt<1>(0h0))
node c_a_bits_a_mask_sub_0_2_4 = and(c_a_bits_a_mask_sub_sub_0_2_4, c_a_bits_a_mask_sub_nbit_4)
node _c_a_bits_a_mask_sub_acc_T_16 = and(c_a_bits_a_mask_sub_size_4, c_a_bits_a_mask_sub_0_2_4)
node c_a_bits_a_mask_sub_0_1_4 = or(c_a_bits_a_mask_sub_sub_0_1_4, _c_a_bits_a_mask_sub_acc_T_16)
node c_a_bits_a_mask_sub_1_2_4 = and(c_a_bits_a_mask_sub_sub_0_2_4, c_a_bits_a_mask_sub_bit_4)
node _c_a_bits_a_mask_sub_acc_T_17 = and(c_a_bits_a_mask_sub_size_4, c_a_bits_a_mask_sub_1_2_4)
node c_a_bits_a_mask_sub_1_1_4 = or(c_a_bits_a_mask_sub_sub_0_1_4, _c_a_bits_a_mask_sub_acc_T_17)
node c_a_bits_a_mask_sub_2_2_4 = and(c_a_bits_a_mask_sub_sub_1_2_4, c_a_bits_a_mask_sub_nbit_4)
node _c_a_bits_a_mask_sub_acc_T_18 = and(c_a_bits_a_mask_sub_size_4, c_a_bits_a_mask_sub_2_2_4)
node c_a_bits_a_mask_sub_2_1_4 = or(c_a_bits_a_mask_sub_sub_1_1_4, _c_a_bits_a_mask_sub_acc_T_18)
node c_a_bits_a_mask_sub_3_2_4 = and(c_a_bits_a_mask_sub_sub_1_2_4, c_a_bits_a_mask_sub_bit_4)
node _c_a_bits_a_mask_sub_acc_T_19 = and(c_a_bits_a_mask_sub_size_4, c_a_bits_a_mask_sub_3_2_4)
node c_a_bits_a_mask_sub_3_1_4 = or(c_a_bits_a_mask_sub_sub_1_1_4, _c_a_bits_a_mask_sub_acc_T_19)
node c_a_bits_a_mask_size_4 = bits(c_a_bits_a_mask_sizeOH_4, 0, 0)
node c_a_bits_a_mask_bit_4 = bits(nodeIn_4.c.bits.address, 0, 0)
node c_a_bits_a_mask_nbit_4 = eq(c_a_bits_a_mask_bit_4, UInt<1>(0h0))
node c_a_bits_a_mask_eq_32 = and(c_a_bits_a_mask_sub_0_2_4, c_a_bits_a_mask_nbit_4)
node _c_a_bits_a_mask_acc_T_32 = and(c_a_bits_a_mask_size_4, c_a_bits_a_mask_eq_32)
node c_a_bits_a_mask_acc_32 = or(c_a_bits_a_mask_sub_0_1_4, _c_a_bits_a_mask_acc_T_32)
node c_a_bits_a_mask_eq_33 = and(c_a_bits_a_mask_sub_0_2_4, c_a_bits_a_mask_bit_4)
node _c_a_bits_a_mask_acc_T_33 = and(c_a_bits_a_mask_size_4, c_a_bits_a_mask_eq_33)
node c_a_bits_a_mask_acc_33 = or(c_a_bits_a_mask_sub_0_1_4, _c_a_bits_a_mask_acc_T_33)
node c_a_bits_a_mask_eq_34 = and(c_a_bits_a_mask_sub_1_2_4, c_a_bits_a_mask_nbit_4)
node _c_a_bits_a_mask_acc_T_34 = and(c_a_bits_a_mask_size_4, c_a_bits_a_mask_eq_34)
node c_a_bits_a_mask_acc_34 = or(c_a_bits_a_mask_sub_1_1_4, _c_a_bits_a_mask_acc_T_34)
node c_a_bits_a_mask_eq_35 = and(c_a_bits_a_mask_sub_1_2_4, c_a_bits_a_mask_bit_4)
node _c_a_bits_a_mask_acc_T_35 = and(c_a_bits_a_mask_size_4, c_a_bits_a_mask_eq_35)
node c_a_bits_a_mask_acc_35 = or(c_a_bits_a_mask_sub_1_1_4, _c_a_bits_a_mask_acc_T_35)
node c_a_bits_a_mask_eq_36 = and(c_a_bits_a_mask_sub_2_2_4, c_a_bits_a_mask_nbit_4)
node _c_a_bits_a_mask_acc_T_36 = and(c_a_bits_a_mask_size_4, c_a_bits_a_mask_eq_36)
node c_a_bits_a_mask_acc_36 = or(c_a_bits_a_mask_sub_2_1_4, _c_a_bits_a_mask_acc_T_36)
node c_a_bits_a_mask_eq_37 = and(c_a_bits_a_mask_sub_2_2_4, c_a_bits_a_mask_bit_4)
node _c_a_bits_a_mask_acc_T_37 = and(c_a_bits_a_mask_size_4, c_a_bits_a_mask_eq_37)
node c_a_bits_a_mask_acc_37 = or(c_a_bits_a_mask_sub_2_1_4, _c_a_bits_a_mask_acc_T_37)
node c_a_bits_a_mask_eq_38 = and(c_a_bits_a_mask_sub_3_2_4, c_a_bits_a_mask_nbit_4)
node _c_a_bits_a_mask_acc_T_38 = and(c_a_bits_a_mask_size_4, c_a_bits_a_mask_eq_38)
node c_a_bits_a_mask_acc_38 = or(c_a_bits_a_mask_sub_3_1_4, _c_a_bits_a_mask_acc_T_38)
node c_a_bits_a_mask_eq_39 = and(c_a_bits_a_mask_sub_3_2_4, c_a_bits_a_mask_bit_4)
node _c_a_bits_a_mask_acc_T_39 = and(c_a_bits_a_mask_size_4, c_a_bits_a_mask_eq_39)
node c_a_bits_a_mask_acc_39 = or(c_a_bits_a_mask_sub_3_1_4, _c_a_bits_a_mask_acc_T_39)
node c_a_bits_a_mask_lo_lo_4 = cat(c_a_bits_a_mask_acc_33, c_a_bits_a_mask_acc_32)
node c_a_bits_a_mask_lo_hi_4 = cat(c_a_bits_a_mask_acc_35, c_a_bits_a_mask_acc_34)
node c_a_bits_a_mask_lo_4 = cat(c_a_bits_a_mask_lo_hi_4, c_a_bits_a_mask_lo_lo_4)
node c_a_bits_a_mask_hi_lo_4 = cat(c_a_bits_a_mask_acc_37, c_a_bits_a_mask_acc_36)
node c_a_bits_a_mask_hi_hi_4 = cat(c_a_bits_a_mask_acc_39, c_a_bits_a_mask_acc_38)
node c_a_bits_a_mask_hi_4 = cat(c_a_bits_a_mask_hi_hi_4, c_a_bits_a_mask_hi_lo_4)
node _c_a_bits_a_mask_T_4 = cat(c_a_bits_a_mask_hi_4, c_a_bits_a_mask_lo_4)
connect c_a_bits_a_4.mask, _c_a_bits_a_mask_T_4
connect c_a_bits_a_4.data, nodeIn_4.c.bits.data
connect c_a_bits_a_4.corrupt, nodeIn_4.c.bits.corrupt
connect c_a_4.bits, c_a_bits_a_4
wire c_d_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _c_d_valid_T_8 = eq(nodeIn_4.c.bits.opcode, UInt<3>(0h6))
node _c_d_valid_T_9 = and(nodeIn_4.c.valid, _c_d_valid_T_8)
connect c_d_4.valid, _c_d_valid_T_9
wire c_d_bits_d_4 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect c_d_bits_d_4.opcode, UInt<3>(0h6)
connect c_d_bits_d_4.param, UInt<1>(0h0)
connect c_d_bits_d_4.size, nodeIn_4.c.bits.size
connect c_d_bits_d_4.source, nodeIn_4.c.bits.source
connect c_d_bits_d_4.sink, UInt<1>(0h0)
connect c_d_bits_d_4.denied, UInt<1>(0h0)
invalidate c_d_bits_d_4.data
connect c_d_bits_d_4.corrupt, UInt<1>(0h0)
connect c_d_4.bits.corrupt, c_d_bits_d_4.corrupt
connect c_d_4.bits.data, c_d_bits_d_4.data
connect c_d_4.bits.denied, c_d_bits_d_4.denied
connect c_d_4.bits.sink, c_d_bits_d_4.sink
connect c_d_4.bits.source, c_d_bits_d_4.source
connect c_d_4.bits.size, c_d_bits_d_4.size
connect c_d_4.bits.param, c_d_bits_d_4.param
connect c_d_4.bits.opcode, c_d_bits_d_4.opcode
node _T_267 = eq(nodeIn_4.c.valid, UInt<1>(0h0))
node _T_268 = eq(nodeIn_4.c.bits.opcode, UInt<3>(0h6))
node _T_269 = or(_T_267, _T_268)
node _T_270 = eq(nodeIn_4.c.bits.opcode, UInt<3>(0h7))
node _T_271 = or(_T_269, _T_270)
node _T_272 = asUInt(reset)
node _T_273 = eq(_T_272, UInt<1>(0h0))
when _T_273 :
node _T_274 = eq(_T_271, UInt<1>(0h0))
when _T_274 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:116 assert (!in.c.valid || in.c.bits.opcode === Release || in.c.bits.opcode === ReleaseData)\n") : printf_24
assert(clock, _T_271, UInt<1>(0h1), "") : assert_24
node _nodeIn_c_ready_T_8 = eq(nodeIn_4.c.bits.opcode, UInt<3>(0h6))
node _nodeIn_c_ready_T_9 = mux(_nodeIn_c_ready_T_8, c_d_4.ready, c_a_4.ready)
connect nodeIn_4.c.ready, _nodeIn_c_ready_T_9
connect nodeIn_4.e.ready, UInt<1>(0h1)
wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_32.bits.corrupt, UInt<1>(0h0)
connect _WIRE_32.bits.data, UInt<64>(0h0)
connect _WIRE_32.bits.mask, UInt<8>(0h0)
connect _WIRE_32.bits.address, UInt<32>(0h0)
connect _WIRE_32.bits.source, UInt<5>(0h0)
connect _WIRE_32.bits.size, UInt<3>(0h0)
connect _WIRE_32.bits.param, UInt<2>(0h0)
connect _WIRE_32.bits.opcode, UInt<3>(0h0)
connect _WIRE_32.valid, UInt<1>(0h0)
connect _WIRE_32.ready, UInt<1>(0h0)
wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_33.bits, _WIRE_32.bits
connect _WIRE_33.valid, _WIRE_32.valid
connect _WIRE_33.ready, _WIRE_32.ready
connect _WIRE_33.ready, UInt<1>(0h0)
wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_34.bits.corrupt, UInt<1>(0h0)
connect _WIRE_34.bits.data, UInt<64>(0h0)
connect _WIRE_34.bits.mask, UInt<8>(0h0)
connect _WIRE_34.bits.address, UInt<32>(0h0)
connect _WIRE_34.bits.source, UInt<5>(0h0)
connect _WIRE_34.bits.size, UInt<3>(0h0)
connect _WIRE_34.bits.param, UInt<2>(0h0)
connect _WIRE_34.bits.opcode, UInt<3>(0h0)
connect _WIRE_34.valid, UInt<1>(0h0)
connect _WIRE_34.ready, UInt<1>(0h0)
wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_35.bits, _WIRE_34.bits
connect _WIRE_35.valid, _WIRE_34.valid
connect _WIRE_35.ready, _WIRE_34.ready
node _T_275 = eq(_WIRE_35.valid, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:124 assert (!out.b.valid)\n") : printf_25
assert(clock, _T_275, UInt<1>(0h1), "") : assert_25
inst pool_4 of IDPool_4
connect pool_4.clock, clock
connect pool_4.reset, reset
node _pool_io_free_valid_T_4 = and(nodeIn_4.e.ready, nodeIn_4.e.valid)
connect pool_4.io.free.valid, _pool_io_free_valid_T_4
connect pool_4.io.free.bits, nodeIn_4.e.bits.sink
wire in_d_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _d_first_T_4 = and(in_d_4.ready, in_d_4.valid)
node _d_first_beats1_decode_T_12 = dshl(UInt<6>(0h3f), in_d_4.bits.size)
node _d_first_beats1_decode_T_13 = bits(_d_first_beats1_decode_T_12, 5, 0)
node _d_first_beats1_decode_T_14 = not(_d_first_beats1_decode_T_13)
node d_first_beats1_decode_4 = shr(_d_first_beats1_decode_T_14, 3)
node d_first_beats1_opdata_4 = bits(in_d_4.bits.opcode, 0, 0)
node d_first_beats1_4 = mux(d_first_beats1_opdata_4, d_first_beats1_decode_4, UInt<1>(0h0))
regreset d_first_counter_4 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_4 = sub(d_first_counter_4, UInt<1>(0h1))
node d_first_counter1_4 = tail(_d_first_counter1_T_4, 1)
node d_first_4 = eq(d_first_counter_4, UInt<1>(0h0))
node _d_first_last_T_8 = eq(d_first_counter_4, UInt<1>(0h1))
node _d_first_last_T_9 = eq(d_first_beats1_4, UInt<1>(0h0))
node d_first_last_4 = or(_d_first_last_T_8, _d_first_last_T_9)
node d_first_done_4 = and(d_first_last_4, _d_first_T_4)
node _d_first_count_T_4 = not(d_first_counter1_4)
node d_first_count_4 = and(d_first_beats1_4, _d_first_count_T_4)
when _d_first_T_4 :
node _d_first_counter_T_4 = mux(d_first_4, d_first_beats1_4, d_first_counter1_4)
connect d_first_counter_4, _d_first_counter_T_4
node _d_grant_T_8 = eq(in_d_4.bits.opcode, UInt<3>(0h5))
node _d_grant_T_9 = eq(in_d_4.bits.opcode, UInt<3>(0h4))
node d_grant_4 = or(_d_grant_T_8, _d_grant_T_9)
node _pool_io_alloc_ready_T_12 = and(nodeIn_4.d.ready, nodeIn_4.d.valid)
node _pool_io_alloc_ready_T_13 = and(_pool_io_alloc_ready_T_12, d_first_4)
node _pool_io_alloc_ready_T_14 = and(_pool_io_alloc_ready_T_13, d_grant_4)
connect pool_4.io.alloc.ready, _pool_io_alloc_ready_T_14
node _nodeIn_d_valid_T_20 = eq(d_first_4, UInt<1>(0h0))
node _nodeIn_d_valid_T_21 = or(pool_4.io.alloc.valid, _nodeIn_d_valid_T_20)
node _nodeIn_d_valid_T_22 = eq(d_grant_4, UInt<1>(0h0))
node _nodeIn_d_valid_T_23 = or(_nodeIn_d_valid_T_21, _nodeIn_d_valid_T_22)
node _nodeIn_d_valid_T_24 = and(in_d_4.valid, _nodeIn_d_valid_T_23)
connect nodeIn_4.d.valid, _nodeIn_d_valid_T_24
node _in_d_ready_T_20 = eq(d_first_4, UInt<1>(0h0))
node _in_d_ready_T_21 = or(pool_4.io.alloc.valid, _in_d_ready_T_20)
node _in_d_ready_T_22 = eq(d_grant_4, UInt<1>(0h0))
node _in_d_ready_T_23 = or(_in_d_ready_T_21, _in_d_ready_T_22)
node _in_d_ready_T_24 = and(nodeIn_4.d.ready, _in_d_ready_T_23)
connect in_d_4.ready, _in_d_ready_T_24
connect nodeIn_4.d.bits.corrupt, in_d_4.bits.corrupt
connect nodeIn_4.d.bits.data, in_d_4.bits.data
connect nodeIn_4.d.bits.denied, in_d_4.bits.denied
connect nodeIn_4.d.bits.sink, in_d_4.bits.sink
connect nodeIn_4.d.bits.source, in_d_4.bits.source
connect nodeIn_4.d.bits.size, in_d_4.bits.size
connect nodeIn_4.d.bits.param, in_d_4.bits.param
connect nodeIn_4.d.bits.opcode, in_d_4.bits.opcode
reg nodeIn_d_bits_sink_r_4 : UInt<3>, clock
when d_first_4 :
connect nodeIn_d_bits_sink_r_4, pool_4.io.alloc.bits
node _nodeIn_d_bits_sink_T_4 = mux(d_first_4, pool_4.io.alloc.bits, nodeIn_d_bits_sink_r_4)
connect nodeIn_4.d.bits.sink, _nodeIn_d_bits_sink_T_4
wire d_d_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect d_d_4, x1_nodeOut_3.d
node _d_d_bits_source_T_4 = shr(x1_nodeOut_3.d.bits.source, 1)
connect d_d_4.bits.source, _d_d_bits_source_T_4
reg wSourceVec_4 : UInt<1>[10], clock
node _aWOk_T_20 = xor(nodeIn_4.a.bits.address, UInt<1>(0h0))
node _aWOk_T_21 = cvt(_aWOk_T_20)
node _aWOk_T_22 = and(_aWOk_T_21, asSInt(UInt<1>(0h0)))
node _aWOk_T_23 = asSInt(_aWOk_T_22)
node _aWOk_T_24 = eq(_aWOk_T_23, asSInt(UInt<1>(0h0)))
node _bypass_T_8 = and(UInt<1>(0h0), nodeIn_4.a.valid)
node _bypass_T_9 = eq(nodeIn_4.a.bits.source, d_d_4.bits.source)
node bypass_4 = and(_bypass_T_8, _bypass_T_9)
node _dWHeld_T_4 = mux(bypass_4, UInt<1>(0h1), wSourceVec_4[d_d_4.bits.source])
reg dWHeld_r_4 : UInt<1>, clock
when d_first_4 :
connect dWHeld_r_4, _dWHeld_T_4
node dWHeld_4 = mux(d_first_4, _dWHeld_T_4, dWHeld_r_4)
node _T_279 = and(nodeIn_4.a.ready, nodeIn_4.a.valid)
when _T_279 :
connect wSourceVec_4[nodeIn_4.a.bits.source], UInt<1>(0h1)
node _T_280 = eq(x1_nodeOut_3.d.bits.opcode, UInt<1>(0h1))
node _T_281 = bits(x1_nodeOut_3.d.bits.source, 0, 0)
node _T_282 = and(_T_280, _T_281)
when _T_282 :
connect d_d_4.bits.opcode, UInt<3>(0h5)
node _d_d_bits_param_T_4 = mux(dWHeld_4, UInt<2>(0h0), UInt<2>(0h1))
connect d_d_4.bits.param, _d_d_bits_param_T_4
node _T_283 = eq(x1_nodeOut_3.d.bits.opcode, UInt<1>(0h0))
node _T_284 = bits(x1_nodeOut_3.d.bits.source, 0, 0)
node _T_285 = eq(_T_284, UInt<1>(0h0))
node _T_286 = and(_T_283, _T_285)
when _T_286 :
connect d_d_4.bits.opcode, UInt<3>(0h6)
node _decode_T_36 = dshl(UInt<6>(0h3f), c_a_4.bits.size)
node _decode_T_37 = bits(_decode_T_36, 5, 0)
node _decode_T_38 = not(_decode_T_37)
node decode_12 = shr(_decode_T_38, 3)
node _opdata_T_8 = bits(c_a_4.bits.opcode, 2, 2)
node opdata_12 = eq(_opdata_T_8, UInt<1>(0h0))
node _T_287 = mux(opdata_12, decode_12, UInt<1>(0h0))
node _decode_T_39 = dshl(UInt<6>(0h3f), a_a_4.bits.size)
node _decode_T_40 = bits(_decode_T_39, 5, 0)
node _decode_T_41 = not(_decode_T_40)
node decode_13 = shr(_decode_T_41, 3)
node _opdata_T_9 = bits(a_a_4.bits.opcode, 2, 2)
node opdata_13 = eq(_opdata_T_9, UInt<1>(0h0))
node _T_288 = mux(opdata_13, decode_13, UInt<1>(0h0))
regreset beatsLeft_8 : UInt, clock, reset, UInt<1>(0h0)
node idle_8 = eq(beatsLeft_8, UInt<1>(0h0))
node latch_8 = and(idle_8, x1_nodeOut_3.a.ready)
node _readys_T_96 = cat(a_a_4.valid, c_a_4.valid)
node _readys_T_97 = shl(_readys_T_96, 1)
node _readys_T_98 = bits(_readys_T_97, 1, 0)
node _readys_T_99 = or(_readys_T_96, _readys_T_98)
node _readys_T_100 = bits(_readys_T_99, 1, 0)
node _readys_T_101 = shl(_readys_T_100, 1)
node _readys_T_102 = bits(_readys_T_101, 1, 0)
node _readys_T_103 = not(_readys_T_102)
node _readys_T_104 = bits(_readys_T_103, 0, 0)
node _readys_T_105 = bits(_readys_T_103, 1, 1)
wire readys_8 : UInt<1>[2]
connect readys_8[0], _readys_T_104
connect readys_8[1], _readys_T_105
node _winner_T_20 = and(readys_8[0], c_a_4.valid)
node _winner_T_21 = and(readys_8[1], a_a_4.valid)
wire winner_8 : UInt<1>[2]
connect winner_8[0], _winner_T_20
connect winner_8[1], _winner_T_21
node prefixOR_1_8 = or(UInt<1>(0h0), winner_8[0])
node _prefixOR_T_8 = or(prefixOR_1_8, winner_8[1])
node _T_289 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_290 = eq(winner_8[0], UInt<1>(0h0))
node _T_291 = or(_T_289, _T_290)
node _T_292 = eq(prefixOR_1_8, UInt<1>(0h0))
node _T_293 = eq(winner_8[1], UInt<1>(0h0))
node _T_294 = or(_T_292, _T_293)
node _T_295 = and(_T_291, _T_294)
node _T_296 = asUInt(reset)
node _T_297 = eq(_T_296, UInt<1>(0h0))
when _T_297 :
node _T_298 = eq(_T_295, UInt<1>(0h0))
when _T_298 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_26
assert(clock, _T_295, UInt<1>(0h1), "") : assert_26
node _T_299 = or(c_a_4.valid, a_a_4.valid)
node _T_300 = eq(_T_299, UInt<1>(0h0))
node _T_301 = or(winner_8[0], winner_8[1])
node _T_302 = or(_T_300, _T_301)
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_T_302, UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_27
assert(clock, _T_302, UInt<1>(0h1), "") : assert_27
node maskedBeats_0_8 = mux(winner_8[0], _T_287, UInt<1>(0h0))
node maskedBeats_1_8 = mux(winner_8[1], _T_288, UInt<1>(0h0))
node initBeats_8 = or(maskedBeats_0_8, maskedBeats_1_8)
node _beatsLeft_T_32 = and(x1_nodeOut_3.a.ready, x1_nodeOut_3.a.valid)
node _beatsLeft_T_33 = sub(beatsLeft_8, _beatsLeft_T_32)
node _beatsLeft_T_34 = tail(_beatsLeft_T_33, 1)
node _beatsLeft_T_35 = mux(latch_8, initBeats_8, _beatsLeft_T_34)
connect beatsLeft_8, _beatsLeft_T_35
wire _state_WIRE_8 : UInt<1>[2]
connect _state_WIRE_8[0], UInt<1>(0h0)
connect _state_WIRE_8[1], UInt<1>(0h0)
regreset state_8 : UInt<1>[2], clock, reset, _state_WIRE_8
node muxState_8 = mux(idle_8, winner_8, state_8)
connect state_8, muxState_8
node allowed_8 = mux(idle_8, readys_8, state_8)
node _c_a_ready_T_4 = and(x1_nodeOut_3.a.ready, allowed_8[0])
connect c_a_4.ready, _c_a_ready_T_4
node _a_a_ready_T_4 = and(x1_nodeOut_3.a.ready, allowed_8[1])
connect a_a_4.ready, _a_a_ready_T_4
node _nodeOut_a_valid_T_20 = or(c_a_4.valid, a_a_4.valid)
node _nodeOut_a_valid_T_21 = mux(state_8[0], c_a_4.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_22 = mux(state_8[1], a_a_4.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_23 = or(_nodeOut_a_valid_T_21, _nodeOut_a_valid_T_22)
wire _nodeOut_a_valid_WIRE_4 : UInt<1>
connect _nodeOut_a_valid_WIRE_4, _nodeOut_a_valid_T_23
node _nodeOut_a_valid_T_24 = mux(idle_8, _nodeOut_a_valid_T_20, _nodeOut_a_valid_WIRE_4)
connect x1_nodeOut_3.a.valid, _nodeOut_a_valid_T_24
wire _nodeOut_a_bits_WIRE_44 : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _nodeOut_a_bits_T_96 = mux(muxState_8[0], c_a_4.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_97 = mux(muxState_8[1], a_a_4.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_98 = or(_nodeOut_a_bits_T_96, _nodeOut_a_bits_T_97)
wire _nodeOut_a_bits_WIRE_45 : UInt<1>
connect _nodeOut_a_bits_WIRE_45, _nodeOut_a_bits_T_98
connect _nodeOut_a_bits_WIRE_44.corrupt, _nodeOut_a_bits_WIRE_45
node _nodeOut_a_bits_T_99 = mux(muxState_8[0], c_a_4.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_100 = mux(muxState_8[1], a_a_4.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_101 = or(_nodeOut_a_bits_T_99, _nodeOut_a_bits_T_100)
wire _nodeOut_a_bits_WIRE_46 : UInt<64>
connect _nodeOut_a_bits_WIRE_46, _nodeOut_a_bits_T_101
connect _nodeOut_a_bits_WIRE_44.data, _nodeOut_a_bits_WIRE_46
node _nodeOut_a_bits_T_102 = mux(muxState_8[0], c_a_4.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_103 = mux(muxState_8[1], a_a_4.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_104 = or(_nodeOut_a_bits_T_102, _nodeOut_a_bits_T_103)
wire _nodeOut_a_bits_WIRE_47 : UInt<8>
connect _nodeOut_a_bits_WIRE_47, _nodeOut_a_bits_T_104
connect _nodeOut_a_bits_WIRE_44.mask, _nodeOut_a_bits_WIRE_47
wire _nodeOut_a_bits_WIRE_48 : { }
connect _nodeOut_a_bits_WIRE_44.echo, _nodeOut_a_bits_WIRE_48
wire _nodeOut_a_bits_WIRE_49 : { }
connect _nodeOut_a_bits_WIRE_44.user, _nodeOut_a_bits_WIRE_49
node _nodeOut_a_bits_T_105 = mux(muxState_8[0], c_a_4.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_106 = mux(muxState_8[1], a_a_4.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_107 = or(_nodeOut_a_bits_T_105, _nodeOut_a_bits_T_106)
wire _nodeOut_a_bits_WIRE_50 : UInt<32>
connect _nodeOut_a_bits_WIRE_50, _nodeOut_a_bits_T_107
connect _nodeOut_a_bits_WIRE_44.address, _nodeOut_a_bits_WIRE_50
node _nodeOut_a_bits_T_108 = mux(muxState_8[0], c_a_4.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_109 = mux(muxState_8[1], a_a_4.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_110 = or(_nodeOut_a_bits_T_108, _nodeOut_a_bits_T_109)
wire _nodeOut_a_bits_WIRE_51 : UInt<5>
connect _nodeOut_a_bits_WIRE_51, _nodeOut_a_bits_T_110
connect _nodeOut_a_bits_WIRE_44.source, _nodeOut_a_bits_WIRE_51
node _nodeOut_a_bits_T_111 = mux(muxState_8[0], c_a_4.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_112 = mux(muxState_8[1], a_a_4.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_113 = or(_nodeOut_a_bits_T_111, _nodeOut_a_bits_T_112)
wire _nodeOut_a_bits_WIRE_52 : UInt<3>
connect _nodeOut_a_bits_WIRE_52, _nodeOut_a_bits_T_113
connect _nodeOut_a_bits_WIRE_44.size, _nodeOut_a_bits_WIRE_52
node _nodeOut_a_bits_T_114 = mux(muxState_8[0], c_a_4.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_115 = mux(muxState_8[1], a_a_4.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_116 = or(_nodeOut_a_bits_T_114, _nodeOut_a_bits_T_115)
wire _nodeOut_a_bits_WIRE_53 : UInt<3>
connect _nodeOut_a_bits_WIRE_53, _nodeOut_a_bits_T_116
connect _nodeOut_a_bits_WIRE_44.param, _nodeOut_a_bits_WIRE_53
node _nodeOut_a_bits_T_117 = mux(muxState_8[0], c_a_4.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_118 = mux(muxState_8[1], a_a_4.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_119 = or(_nodeOut_a_bits_T_117, _nodeOut_a_bits_T_118)
wire _nodeOut_a_bits_WIRE_54 : UInt<3>
connect _nodeOut_a_bits_WIRE_54, _nodeOut_a_bits_T_119
connect _nodeOut_a_bits_WIRE_44.opcode, _nodeOut_a_bits_WIRE_54
connect x1_nodeOut_3.a.bits.corrupt, _nodeOut_a_bits_WIRE_44.corrupt
connect x1_nodeOut_3.a.bits.data, _nodeOut_a_bits_WIRE_44.data
connect x1_nodeOut_3.a.bits.mask, _nodeOut_a_bits_WIRE_44.mask
connect x1_nodeOut_3.a.bits.address, _nodeOut_a_bits_WIRE_44.address
connect x1_nodeOut_3.a.bits.source, _nodeOut_a_bits_WIRE_44.source
connect x1_nodeOut_3.a.bits.size, _nodeOut_a_bits_WIRE_44.size
connect x1_nodeOut_3.a.bits.param, _nodeOut_a_bits_WIRE_44.param
connect x1_nodeOut_3.a.bits.opcode, _nodeOut_a_bits_WIRE_44.opcode
node _decode_T_42 = dshl(UInt<6>(0h3f), d_d_4.bits.size)
node _decode_T_43 = bits(_decode_T_42, 5, 0)
node _decode_T_44 = not(_decode_T_43)
node decode_14 = shr(_decode_T_44, 3)
node opdata_14 = bits(d_d_4.bits.opcode, 0, 0)
node _T_306 = mux(opdata_14, decode_14, UInt<1>(0h0))
inst q_8 of Queue2_TLBundleD_a32d64s4k3z3c_16
connect q_8.clock, clock
connect q_8.reset, reset
connect q_8.io.enq.valid, c_d_4.valid
connect q_8.io.enq.bits.corrupt, c_d_4.bits.corrupt
connect q_8.io.enq.bits.data, c_d_4.bits.data
connect q_8.io.enq.bits.denied, c_d_4.bits.denied
connect q_8.io.enq.bits.sink, c_d_4.bits.sink
connect q_8.io.enq.bits.source, c_d_4.bits.source
connect q_8.io.enq.bits.size, c_d_4.bits.size
connect q_8.io.enq.bits.param, c_d_4.bits.param
connect q_8.io.enq.bits.opcode, c_d_4.bits.opcode
connect c_d_4.ready, q_8.io.enq.ready
inst q_9 of Queue2_TLBundleD_a32d64s4k3z3c_17
connect q_9.clock, clock
connect q_9.reset, reset
connect q_9.io.enq.valid, a_d_4.valid
connect q_9.io.enq.bits.corrupt, a_d_4.bits.corrupt
connect q_9.io.enq.bits.data, a_d_4.bits.data
connect q_9.io.enq.bits.denied, a_d_4.bits.denied
connect q_9.io.enq.bits.sink, a_d_4.bits.sink
connect q_9.io.enq.bits.source, a_d_4.bits.source
connect q_9.io.enq.bits.size, a_d_4.bits.size
connect q_9.io.enq.bits.param, a_d_4.bits.param
connect q_9.io.enq.bits.opcode, a_d_4.bits.opcode
connect a_d_4.ready, q_9.io.enq.ready
regreset beatsLeft_9 : UInt, clock, reset, UInt<1>(0h0)
node idle_9 = eq(beatsLeft_9, UInt<1>(0h0))
node latch_9 = and(idle_9, in_d_4.ready)
node readys_hi_4 = cat(q_9.io.deq.valid, q_8.io.deq.valid)
node _readys_T_106 = cat(readys_hi_4, d_d_4.valid)
node _readys_T_107 = shl(_readys_T_106, 1)
node _readys_T_108 = bits(_readys_T_107, 2, 0)
node _readys_T_109 = or(_readys_T_106, _readys_T_108)
node _readys_T_110 = shl(_readys_T_109, 2)
node _readys_T_111 = bits(_readys_T_110, 2, 0)
node _readys_T_112 = or(_readys_T_109, _readys_T_111)
node _readys_T_113 = bits(_readys_T_112, 2, 0)
node _readys_T_114 = shl(_readys_T_113, 1)
node _readys_T_115 = bits(_readys_T_114, 2, 0)
node _readys_T_116 = not(_readys_T_115)
node _readys_T_117 = bits(_readys_T_116, 0, 0)
node _readys_T_118 = bits(_readys_T_116, 1, 1)
node _readys_T_119 = bits(_readys_T_116, 2, 2)
wire readys_9 : UInt<1>[3]
connect readys_9[0], _readys_T_117
connect readys_9[1], _readys_T_118
connect readys_9[2], _readys_T_119
node _winner_T_22 = and(readys_9[0], d_d_4.valid)
node _winner_T_23 = and(readys_9[1], q_8.io.deq.valid)
node _winner_T_24 = and(readys_9[2], q_9.io.deq.valid)
wire winner_9 : UInt<1>[3]
connect winner_9[0], _winner_T_22
connect winner_9[1], _winner_T_23
connect winner_9[2], _winner_T_24
node prefixOR_1_9 = or(UInt<1>(0h0), winner_9[0])
node prefixOR_2_4 = or(prefixOR_1_9, winner_9[1])
node _prefixOR_T_9 = or(prefixOR_2_4, winner_9[2])
node _T_307 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_308 = eq(winner_9[0], UInt<1>(0h0))
node _T_309 = or(_T_307, _T_308)
node _T_310 = eq(prefixOR_1_9, UInt<1>(0h0))
node _T_311 = eq(winner_9[1], UInt<1>(0h0))
node _T_312 = or(_T_310, _T_311)
node _T_313 = eq(prefixOR_2_4, UInt<1>(0h0))
node _T_314 = eq(winner_9[2], UInt<1>(0h0))
node _T_315 = or(_T_313, _T_314)
node _T_316 = and(_T_309, _T_312)
node _T_317 = and(_T_316, _T_315)
node _T_318 = asUInt(reset)
node _T_319 = eq(_T_318, UInt<1>(0h0))
when _T_319 :
node _T_320 = eq(_T_317, UInt<1>(0h0))
when _T_320 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_28
assert(clock, _T_317, UInt<1>(0h1), "") : assert_28
node _T_321 = or(d_d_4.valid, q_8.io.deq.valid)
node _T_322 = or(_T_321, q_9.io.deq.valid)
node _T_323 = eq(_T_322, UInt<1>(0h0))
node _T_324 = or(winner_9[0], winner_9[1])
node _T_325 = or(_T_324, winner_9[2])
node _T_326 = or(_T_323, _T_325)
node _T_327 = asUInt(reset)
node _T_328 = eq(_T_327, UInt<1>(0h0))
when _T_328 :
node _T_329 = eq(_T_326, UInt<1>(0h0))
when _T_329 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_29
assert(clock, _T_326, UInt<1>(0h1), "") : assert_29
node maskedBeats_0_9 = mux(winner_9[0], _T_306, UInt<1>(0h0))
node maskedBeats_1_9 = mux(winner_9[1], UInt<1>(0h0), UInt<1>(0h0))
node maskedBeats_2_4 = mux(winner_9[2], UInt<1>(0h0), UInt<1>(0h0))
node _initBeats_T_4 = or(maskedBeats_0_9, maskedBeats_1_9)
node initBeats_9 = or(_initBeats_T_4, maskedBeats_2_4)
node _beatsLeft_T_36 = and(in_d_4.ready, in_d_4.valid)
node _beatsLeft_T_37 = sub(beatsLeft_9, _beatsLeft_T_36)
node _beatsLeft_T_38 = tail(_beatsLeft_T_37, 1)
node _beatsLeft_T_39 = mux(latch_9, initBeats_9, _beatsLeft_T_38)
connect beatsLeft_9, _beatsLeft_T_39
wire _state_WIRE_9 : UInt<1>[3]
connect _state_WIRE_9[0], UInt<1>(0h0)
connect _state_WIRE_9[1], UInt<1>(0h0)
connect _state_WIRE_9[2], UInt<1>(0h0)
regreset state_9 : UInt<1>[3], clock, reset, _state_WIRE_9
node muxState_9 = mux(idle_9, winner_9, state_9)
connect state_9, muxState_9
node allowed_9 = mux(idle_9, readys_9, state_9)
node _d_d_ready_T_4 = and(in_d_4.ready, allowed_9[0])
connect d_d_4.ready, _d_d_ready_T_4
node _q_io_deq_ready_T_8 = and(in_d_4.ready, allowed_9[1])
connect q_8.io.deq.ready, _q_io_deq_ready_T_8
node _q_io_deq_ready_T_9 = and(in_d_4.ready, allowed_9[2])
connect q_9.io.deq.ready, _q_io_deq_ready_T_9
node _in_d_valid_T_32 = or(d_d_4.valid, q_8.io.deq.valid)
node _in_d_valid_T_33 = or(_in_d_valid_T_32, q_9.io.deq.valid)
node _in_d_valid_T_34 = mux(state_9[0], d_d_4.valid, UInt<1>(0h0))
node _in_d_valid_T_35 = mux(state_9[1], q_8.io.deq.valid, UInt<1>(0h0))
node _in_d_valid_T_36 = mux(state_9[2], q_9.io.deq.valid, UInt<1>(0h0))
node _in_d_valid_T_37 = or(_in_d_valid_T_34, _in_d_valid_T_35)
node _in_d_valid_T_38 = or(_in_d_valid_T_37, _in_d_valid_T_36)
wire _in_d_valid_WIRE_4 : UInt<1>
connect _in_d_valid_WIRE_4, _in_d_valid_T_38
node _in_d_valid_T_39 = mux(idle_9, _in_d_valid_T_33, _in_d_valid_WIRE_4)
connect in_d_4.valid, _in_d_valid_T_39
wire _in_d_bits_WIRE_44 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_d_bits_T_160 = mux(muxState_9[0], d_d_4.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_161 = mux(muxState_9[1], q_8.io.deq.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_162 = mux(muxState_9[2], q_9.io.deq.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_163 = or(_in_d_bits_T_160, _in_d_bits_T_161)
node _in_d_bits_T_164 = or(_in_d_bits_T_163, _in_d_bits_T_162)
wire _in_d_bits_WIRE_45 : UInt<1>
connect _in_d_bits_WIRE_45, _in_d_bits_T_164
connect _in_d_bits_WIRE_44.corrupt, _in_d_bits_WIRE_45
node _in_d_bits_T_165 = mux(muxState_9[0], d_d_4.bits.data, UInt<1>(0h0))
node _in_d_bits_T_166 = mux(muxState_9[1], q_8.io.deq.bits.data, UInt<1>(0h0))
node _in_d_bits_T_167 = mux(muxState_9[2], q_9.io.deq.bits.data, UInt<1>(0h0))
node _in_d_bits_T_168 = or(_in_d_bits_T_165, _in_d_bits_T_166)
node _in_d_bits_T_169 = or(_in_d_bits_T_168, _in_d_bits_T_167)
wire _in_d_bits_WIRE_46 : UInt<64>
connect _in_d_bits_WIRE_46, _in_d_bits_T_169
connect _in_d_bits_WIRE_44.data, _in_d_bits_WIRE_46
wire _in_d_bits_WIRE_47 : { }
connect _in_d_bits_WIRE_44.echo, _in_d_bits_WIRE_47
wire _in_d_bits_WIRE_48 : { }
connect _in_d_bits_WIRE_44.user, _in_d_bits_WIRE_48
node _in_d_bits_T_170 = mux(muxState_9[0], d_d_4.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_171 = mux(muxState_9[1], q_8.io.deq.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_172 = mux(muxState_9[2], q_9.io.deq.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_173 = or(_in_d_bits_T_170, _in_d_bits_T_171)
node _in_d_bits_T_174 = or(_in_d_bits_T_173, _in_d_bits_T_172)
wire _in_d_bits_WIRE_49 : UInt<1>
connect _in_d_bits_WIRE_49, _in_d_bits_T_174
connect _in_d_bits_WIRE_44.denied, _in_d_bits_WIRE_49
node _in_d_bits_T_175 = mux(muxState_9[0], d_d_4.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_176 = mux(muxState_9[1], q_8.io.deq.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_177 = mux(muxState_9[2], q_9.io.deq.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_178 = or(_in_d_bits_T_175, _in_d_bits_T_176)
node _in_d_bits_T_179 = or(_in_d_bits_T_178, _in_d_bits_T_177)
wire _in_d_bits_WIRE_50 : UInt<3>
connect _in_d_bits_WIRE_50, _in_d_bits_T_179
connect _in_d_bits_WIRE_44.sink, _in_d_bits_WIRE_50
node _in_d_bits_T_180 = mux(muxState_9[0], d_d_4.bits.source, UInt<1>(0h0))
node _in_d_bits_T_181 = mux(muxState_9[1], q_8.io.deq.bits.source, UInt<1>(0h0))
node _in_d_bits_T_182 = mux(muxState_9[2], q_9.io.deq.bits.source, UInt<1>(0h0))
node _in_d_bits_T_183 = or(_in_d_bits_T_180, _in_d_bits_T_181)
node _in_d_bits_T_184 = or(_in_d_bits_T_183, _in_d_bits_T_182)
wire _in_d_bits_WIRE_51 : UInt<4>
connect _in_d_bits_WIRE_51, _in_d_bits_T_184
connect _in_d_bits_WIRE_44.source, _in_d_bits_WIRE_51
node _in_d_bits_T_185 = mux(muxState_9[0], d_d_4.bits.size, UInt<1>(0h0))
node _in_d_bits_T_186 = mux(muxState_9[1], q_8.io.deq.bits.size, UInt<1>(0h0))
node _in_d_bits_T_187 = mux(muxState_9[2], q_9.io.deq.bits.size, UInt<1>(0h0))
node _in_d_bits_T_188 = or(_in_d_bits_T_185, _in_d_bits_T_186)
node _in_d_bits_T_189 = or(_in_d_bits_T_188, _in_d_bits_T_187)
wire _in_d_bits_WIRE_52 : UInt<3>
connect _in_d_bits_WIRE_52, _in_d_bits_T_189
connect _in_d_bits_WIRE_44.size, _in_d_bits_WIRE_52
node _in_d_bits_T_190 = mux(muxState_9[0], d_d_4.bits.param, UInt<1>(0h0))
node _in_d_bits_T_191 = mux(muxState_9[1], q_8.io.deq.bits.param, UInt<1>(0h0))
node _in_d_bits_T_192 = mux(muxState_9[2], q_9.io.deq.bits.param, UInt<1>(0h0))
node _in_d_bits_T_193 = or(_in_d_bits_T_190, _in_d_bits_T_191)
node _in_d_bits_T_194 = or(_in_d_bits_T_193, _in_d_bits_T_192)
wire _in_d_bits_WIRE_53 : UInt<2>
connect _in_d_bits_WIRE_53, _in_d_bits_T_194
connect _in_d_bits_WIRE_44.param, _in_d_bits_WIRE_53
node _in_d_bits_T_195 = mux(muxState_9[0], d_d_4.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_196 = mux(muxState_9[1], q_8.io.deq.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_197 = mux(muxState_9[2], q_9.io.deq.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_198 = or(_in_d_bits_T_195, _in_d_bits_T_196)
node _in_d_bits_T_199 = or(_in_d_bits_T_198, _in_d_bits_T_197)
wire _in_d_bits_WIRE_54 : UInt<3>
connect _in_d_bits_WIRE_54, _in_d_bits_T_199
connect _in_d_bits_WIRE_44.opcode, _in_d_bits_WIRE_54
connect in_d_4.bits.corrupt, _in_d_bits_WIRE_44.corrupt
connect in_d_4.bits.data, _in_d_bits_WIRE_44.data
connect in_d_4.bits.denied, _in_d_bits_WIRE_44.denied
connect in_d_4.bits.sink, _in_d_bits_WIRE_44.sink
connect in_d_4.bits.source, _in_d_bits_WIRE_44.source
connect in_d_4.bits.size, _in_d_bits_WIRE_44.size
connect in_d_4.bits.param, _in_d_bits_WIRE_44.param
connect in_d_4.bits.opcode, _in_d_bits_WIRE_44.opcode
connect nodeIn_4.b.valid, UInt<1>(0h0)
wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_36.bits.corrupt, UInt<1>(0h0)
connect _WIRE_36.bits.data, UInt<64>(0h0)
connect _WIRE_36.bits.address, UInt<32>(0h0)
connect _WIRE_36.bits.source, UInt<5>(0h0)
connect _WIRE_36.bits.size, UInt<3>(0h0)
connect _WIRE_36.bits.param, UInt<3>(0h0)
connect _WIRE_36.bits.opcode, UInt<3>(0h0)
connect _WIRE_36.valid, UInt<1>(0h0)
connect _WIRE_36.ready, UInt<1>(0h0)
wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_37.bits, _WIRE_36.bits
connect _WIRE_37.valid, _WIRE_36.valid
connect _WIRE_37.ready, _WIRE_36.ready
connect _WIRE_37.valid, UInt<1>(0h0)
wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_38.bits.sink, UInt<1>(0h0)
connect _WIRE_38.valid, UInt<1>(0h0)
connect _WIRE_38.ready, UInt<1>(0h0)
wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_39.bits, _WIRE_38.bits
connect _WIRE_39.valid, _WIRE_38.valid
connect _WIRE_39.ready, _WIRE_38.ready
connect _WIRE_39.valid, UInt<1>(0h0)
wire a_a_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
wire a_d_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _isPut_T_10 = eq(nodeIn_5.a.bits.opcode, UInt<1>(0h0))
node _isPut_T_11 = eq(nodeIn_5.a.bits.opcode, UInt<1>(0h1))
node isPut_5 = or(_isPut_T_10, _isPut_T_11)
node _toD_T_20 = eq(nodeIn_5.a.bits.opcode, UInt<3>(0h6))
node _toD_T_21 = eq(nodeIn_5.a.bits.param, UInt<2>(0h2))
node _toD_T_22 = and(_toD_T_20, _toD_T_21)
node _toD_T_23 = eq(nodeIn_5.a.bits.opcode, UInt<3>(0h7))
node toD_5 = or(_toD_T_22, _toD_T_23)
node _nodeIn_a_ready_T_5 = mux(toD_5, a_d_5.ready, a_a_5.ready)
connect nodeIn_5.a.ready, _nodeIn_a_ready_T_5
node _a_a_valid_T_10 = eq(toD_5, UInt<1>(0h0))
node _a_a_valid_T_11 = and(nodeIn_5.a.valid, _a_a_valid_T_10)
connect a_a_5.valid, _a_a_valid_T_11
connect a_a_5.bits, nodeIn_5.a.bits
node _a_a_bits_source_T_25 = shl(nodeIn_5.a.bits.source, 1)
node _a_a_bits_source_T_26 = mux(isPut_5, UInt<1>(0h1), UInt<1>(0h0))
node _a_a_bits_source_T_27 = or(_a_a_bits_source_T_25, _a_a_bits_source_T_26)
connect a_a_5.bits.source, _a_a_bits_source_T_27
node _T_330 = eq(nodeIn_5.a.bits.opcode, UInt<3>(0h6))
node _T_331 = eq(nodeIn_5.a.bits.opcode, UInt<3>(0h7))
node _T_332 = or(_T_330, _T_331)
when _T_332 :
connect a_a_5.bits.opcode, UInt<3>(0h4)
connect a_a_5.bits.param, UInt<1>(0h0)
node _a_a_bits_source_T_28 = shl(nodeIn_5.a.bits.source, 1)
node _a_a_bits_source_T_29 = or(_a_a_bits_source_T_28, UInt<1>(0h1))
connect a_a_5.bits.source, _a_a_bits_source_T_29
node _a_d_valid_T_5 = and(nodeIn_5.a.valid, toD_5)
connect a_d_5.valid, _a_d_valid_T_5
wire a_d_bits_d_5 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect a_d_bits_d_5.opcode, UInt<3>(0h4)
connect a_d_bits_d_5.param, UInt<2>(0h0)
connect a_d_bits_d_5.size, nodeIn_5.a.bits.size
connect a_d_bits_d_5.source, nodeIn_5.a.bits.source
connect a_d_bits_d_5.sink, UInt<1>(0h0)
connect a_d_bits_d_5.denied, UInt<1>(0h0)
invalidate a_d_bits_d_5.data
connect a_d_bits_d_5.corrupt, UInt<1>(0h0)
connect a_d_5.bits.corrupt, a_d_bits_d_5.corrupt
connect a_d_5.bits.data, a_d_bits_d_5.data
connect a_d_5.bits.denied, a_d_bits_d_5.denied
connect a_d_5.bits.sink, a_d_bits_d_5.sink
connect a_d_5.bits.source, a_d_bits_d_5.source
connect a_d_5.bits.size, a_d_bits_d_5.size
connect a_d_5.bits.param, a_d_bits_d_5.param
connect a_d_5.bits.opcode, a_d_bits_d_5.opcode
wire c_a_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
node _c_a_valid_T_10 = eq(nodeIn_5.c.bits.opcode, UInt<3>(0h7))
node _c_a_valid_T_11 = and(nodeIn_5.c.valid, _c_a_valid_T_10)
connect c_a_5.valid, _c_a_valid_T_11
node _c_a_bits_T_5 = shl(nodeIn_5.c.bits.source, 1)
node _c_a_bits_legal_T_50 = leq(UInt<1>(0h0), nodeIn_5.c.bits.size)
node _c_a_bits_legal_T_51 = leq(nodeIn_5.c.bits.size, UInt<3>(0h6))
node _c_a_bits_legal_T_52 = and(_c_a_bits_legal_T_50, _c_a_bits_legal_T_51)
node _c_a_bits_legal_T_53 = or(UInt<1>(0h0), _c_a_bits_legal_T_52)
node _c_a_bits_legal_T_54 = xor(nodeIn_5.c.bits.address, UInt<1>(0h0))
node _c_a_bits_legal_T_55 = cvt(_c_a_bits_legal_T_54)
node _c_a_bits_legal_T_56 = and(_c_a_bits_legal_T_55, asSInt(UInt<1>(0h0)))
node _c_a_bits_legal_T_57 = asSInt(_c_a_bits_legal_T_56)
node _c_a_bits_legal_T_58 = eq(_c_a_bits_legal_T_57, asSInt(UInt<1>(0h0)))
node _c_a_bits_legal_T_59 = and(_c_a_bits_legal_T_53, _c_a_bits_legal_T_58)
node c_a_bits_legal_5 = or(UInt<1>(0h0), _c_a_bits_legal_T_59)
wire c_a_bits_a_5 : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect c_a_bits_a_5.opcode, UInt<1>(0h0)
connect c_a_bits_a_5.param, UInt<1>(0h0)
connect c_a_bits_a_5.size, nodeIn_5.c.bits.size
connect c_a_bits_a_5.source, _c_a_bits_T_5
connect c_a_bits_a_5.address, nodeIn_5.c.bits.address
node _c_a_bits_a_mask_sizeOH_T_15 = or(nodeIn_5.c.bits.size, UInt<3>(0h0))
node c_a_bits_a_mask_sizeOH_shiftAmount_5 = bits(_c_a_bits_a_mask_sizeOH_T_15, 1, 0)
node _c_a_bits_a_mask_sizeOH_T_16 = dshl(UInt<1>(0h1), c_a_bits_a_mask_sizeOH_shiftAmount_5)
node _c_a_bits_a_mask_sizeOH_T_17 = bits(_c_a_bits_a_mask_sizeOH_T_16, 2, 0)
node c_a_bits_a_mask_sizeOH_5 = or(_c_a_bits_a_mask_sizeOH_T_17, UInt<1>(0h1))
node c_a_bits_a_mask_sub_sub_sub_0_1_5 = geq(nodeIn_5.c.bits.size, UInt<2>(0h3))
node c_a_bits_a_mask_sub_sub_size_5 = bits(c_a_bits_a_mask_sizeOH_5, 2, 2)
node c_a_bits_a_mask_sub_sub_bit_5 = bits(nodeIn_5.c.bits.address, 2, 2)
node c_a_bits_a_mask_sub_sub_nbit_5 = eq(c_a_bits_a_mask_sub_sub_bit_5, UInt<1>(0h0))
node c_a_bits_a_mask_sub_sub_0_2_5 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_nbit_5)
node _c_a_bits_a_mask_sub_sub_acc_T_10 = and(c_a_bits_a_mask_sub_sub_size_5, c_a_bits_a_mask_sub_sub_0_2_5)
node c_a_bits_a_mask_sub_sub_0_1_5 = or(c_a_bits_a_mask_sub_sub_sub_0_1_5, _c_a_bits_a_mask_sub_sub_acc_T_10)
node c_a_bits_a_mask_sub_sub_1_2_5 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_bit_5)
node _c_a_bits_a_mask_sub_sub_acc_T_11 = and(c_a_bits_a_mask_sub_sub_size_5, c_a_bits_a_mask_sub_sub_1_2_5)
node c_a_bits_a_mask_sub_sub_1_1_5 = or(c_a_bits_a_mask_sub_sub_sub_0_1_5, _c_a_bits_a_mask_sub_sub_acc_T_11)
node c_a_bits_a_mask_sub_size_5 = bits(c_a_bits_a_mask_sizeOH_5, 1, 1)
node c_a_bits_a_mask_sub_bit_5 = bits(nodeIn_5.c.bits.address, 1, 1)
node c_a_bits_a_mask_sub_nbit_5 = eq(c_a_bits_a_mask_sub_bit_5, UInt<1>(0h0))
node c_a_bits_a_mask_sub_0_2_5 = and(c_a_bits_a_mask_sub_sub_0_2_5, c_a_bits_a_mask_sub_nbit_5)
node _c_a_bits_a_mask_sub_acc_T_20 = and(c_a_bits_a_mask_sub_size_5, c_a_bits_a_mask_sub_0_2_5)
node c_a_bits_a_mask_sub_0_1_5 = or(c_a_bits_a_mask_sub_sub_0_1_5, _c_a_bits_a_mask_sub_acc_T_20)
node c_a_bits_a_mask_sub_1_2_5 = and(c_a_bits_a_mask_sub_sub_0_2_5, c_a_bits_a_mask_sub_bit_5)
node _c_a_bits_a_mask_sub_acc_T_21 = and(c_a_bits_a_mask_sub_size_5, c_a_bits_a_mask_sub_1_2_5)
node c_a_bits_a_mask_sub_1_1_5 = or(c_a_bits_a_mask_sub_sub_0_1_5, _c_a_bits_a_mask_sub_acc_T_21)
node c_a_bits_a_mask_sub_2_2_5 = and(c_a_bits_a_mask_sub_sub_1_2_5, c_a_bits_a_mask_sub_nbit_5)
node _c_a_bits_a_mask_sub_acc_T_22 = and(c_a_bits_a_mask_sub_size_5, c_a_bits_a_mask_sub_2_2_5)
node c_a_bits_a_mask_sub_2_1_5 = or(c_a_bits_a_mask_sub_sub_1_1_5, _c_a_bits_a_mask_sub_acc_T_22)
node c_a_bits_a_mask_sub_3_2_5 = and(c_a_bits_a_mask_sub_sub_1_2_5, c_a_bits_a_mask_sub_bit_5)
node _c_a_bits_a_mask_sub_acc_T_23 = and(c_a_bits_a_mask_sub_size_5, c_a_bits_a_mask_sub_3_2_5)
node c_a_bits_a_mask_sub_3_1_5 = or(c_a_bits_a_mask_sub_sub_1_1_5, _c_a_bits_a_mask_sub_acc_T_23)
node c_a_bits_a_mask_size_5 = bits(c_a_bits_a_mask_sizeOH_5, 0, 0)
node c_a_bits_a_mask_bit_5 = bits(nodeIn_5.c.bits.address, 0, 0)
node c_a_bits_a_mask_nbit_5 = eq(c_a_bits_a_mask_bit_5, UInt<1>(0h0))
node c_a_bits_a_mask_eq_40 = and(c_a_bits_a_mask_sub_0_2_5, c_a_bits_a_mask_nbit_5)
node _c_a_bits_a_mask_acc_T_40 = and(c_a_bits_a_mask_size_5, c_a_bits_a_mask_eq_40)
node c_a_bits_a_mask_acc_40 = or(c_a_bits_a_mask_sub_0_1_5, _c_a_bits_a_mask_acc_T_40)
node c_a_bits_a_mask_eq_41 = and(c_a_bits_a_mask_sub_0_2_5, c_a_bits_a_mask_bit_5)
node _c_a_bits_a_mask_acc_T_41 = and(c_a_bits_a_mask_size_5, c_a_bits_a_mask_eq_41)
node c_a_bits_a_mask_acc_41 = or(c_a_bits_a_mask_sub_0_1_5, _c_a_bits_a_mask_acc_T_41)
node c_a_bits_a_mask_eq_42 = and(c_a_bits_a_mask_sub_1_2_5, c_a_bits_a_mask_nbit_5)
node _c_a_bits_a_mask_acc_T_42 = and(c_a_bits_a_mask_size_5, c_a_bits_a_mask_eq_42)
node c_a_bits_a_mask_acc_42 = or(c_a_bits_a_mask_sub_1_1_5, _c_a_bits_a_mask_acc_T_42)
node c_a_bits_a_mask_eq_43 = and(c_a_bits_a_mask_sub_1_2_5, c_a_bits_a_mask_bit_5)
node _c_a_bits_a_mask_acc_T_43 = and(c_a_bits_a_mask_size_5, c_a_bits_a_mask_eq_43)
node c_a_bits_a_mask_acc_43 = or(c_a_bits_a_mask_sub_1_1_5, _c_a_bits_a_mask_acc_T_43)
node c_a_bits_a_mask_eq_44 = and(c_a_bits_a_mask_sub_2_2_5, c_a_bits_a_mask_nbit_5)
node _c_a_bits_a_mask_acc_T_44 = and(c_a_bits_a_mask_size_5, c_a_bits_a_mask_eq_44)
node c_a_bits_a_mask_acc_44 = or(c_a_bits_a_mask_sub_2_1_5, _c_a_bits_a_mask_acc_T_44)
node c_a_bits_a_mask_eq_45 = and(c_a_bits_a_mask_sub_2_2_5, c_a_bits_a_mask_bit_5)
node _c_a_bits_a_mask_acc_T_45 = and(c_a_bits_a_mask_size_5, c_a_bits_a_mask_eq_45)
node c_a_bits_a_mask_acc_45 = or(c_a_bits_a_mask_sub_2_1_5, _c_a_bits_a_mask_acc_T_45)
node c_a_bits_a_mask_eq_46 = and(c_a_bits_a_mask_sub_3_2_5, c_a_bits_a_mask_nbit_5)
node _c_a_bits_a_mask_acc_T_46 = and(c_a_bits_a_mask_size_5, c_a_bits_a_mask_eq_46)
node c_a_bits_a_mask_acc_46 = or(c_a_bits_a_mask_sub_3_1_5, _c_a_bits_a_mask_acc_T_46)
node c_a_bits_a_mask_eq_47 = and(c_a_bits_a_mask_sub_3_2_5, c_a_bits_a_mask_bit_5)
node _c_a_bits_a_mask_acc_T_47 = and(c_a_bits_a_mask_size_5, c_a_bits_a_mask_eq_47)
node c_a_bits_a_mask_acc_47 = or(c_a_bits_a_mask_sub_3_1_5, _c_a_bits_a_mask_acc_T_47)
node c_a_bits_a_mask_lo_lo_5 = cat(c_a_bits_a_mask_acc_41, c_a_bits_a_mask_acc_40)
node c_a_bits_a_mask_lo_hi_5 = cat(c_a_bits_a_mask_acc_43, c_a_bits_a_mask_acc_42)
node c_a_bits_a_mask_lo_5 = cat(c_a_bits_a_mask_lo_hi_5, c_a_bits_a_mask_lo_lo_5)
node c_a_bits_a_mask_hi_lo_5 = cat(c_a_bits_a_mask_acc_45, c_a_bits_a_mask_acc_44)
node c_a_bits_a_mask_hi_hi_5 = cat(c_a_bits_a_mask_acc_47, c_a_bits_a_mask_acc_46)
node c_a_bits_a_mask_hi_5 = cat(c_a_bits_a_mask_hi_hi_5, c_a_bits_a_mask_hi_lo_5)
node _c_a_bits_a_mask_T_5 = cat(c_a_bits_a_mask_hi_5, c_a_bits_a_mask_lo_5)
connect c_a_bits_a_5.mask, _c_a_bits_a_mask_T_5
connect c_a_bits_a_5.data, nodeIn_5.c.bits.data
connect c_a_bits_a_5.corrupt, nodeIn_5.c.bits.corrupt
connect c_a_5.bits, c_a_bits_a_5
wire c_d_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _c_d_valid_T_10 = eq(nodeIn_5.c.bits.opcode, UInt<3>(0h6))
node _c_d_valid_T_11 = and(nodeIn_5.c.valid, _c_d_valid_T_10)
connect c_d_5.valid, _c_d_valid_T_11
wire c_d_bits_d_5 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect c_d_bits_d_5.opcode, UInt<3>(0h6)
connect c_d_bits_d_5.param, UInt<1>(0h0)
connect c_d_bits_d_5.size, nodeIn_5.c.bits.size
connect c_d_bits_d_5.source, nodeIn_5.c.bits.source
connect c_d_bits_d_5.sink, UInt<1>(0h0)
connect c_d_bits_d_5.denied, UInt<1>(0h0)
invalidate c_d_bits_d_5.data
connect c_d_bits_d_5.corrupt, UInt<1>(0h0)
connect c_d_5.bits.corrupt, c_d_bits_d_5.corrupt
connect c_d_5.bits.data, c_d_bits_d_5.data
connect c_d_5.bits.denied, c_d_bits_d_5.denied
connect c_d_5.bits.sink, c_d_bits_d_5.sink
connect c_d_5.bits.source, c_d_bits_d_5.source
connect c_d_5.bits.size, c_d_bits_d_5.size
connect c_d_5.bits.param, c_d_bits_d_5.param
connect c_d_5.bits.opcode, c_d_bits_d_5.opcode
node _T_333 = eq(nodeIn_5.c.valid, UInt<1>(0h0))
node _T_334 = eq(nodeIn_5.c.bits.opcode, UInt<3>(0h6))
node _T_335 = or(_T_333, _T_334)
node _T_336 = eq(nodeIn_5.c.bits.opcode, UInt<3>(0h7))
node _T_337 = or(_T_335, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:116 assert (!in.c.valid || in.c.bits.opcode === Release || in.c.bits.opcode === ReleaseData)\n") : printf_30
assert(clock, _T_337, UInt<1>(0h1), "") : assert_30
node _nodeIn_c_ready_T_10 = eq(nodeIn_5.c.bits.opcode, UInt<3>(0h6))
node _nodeIn_c_ready_T_11 = mux(_nodeIn_c_ready_T_10, c_d_5.ready, c_a_5.ready)
connect nodeIn_5.c.ready, _nodeIn_c_ready_T_11
connect nodeIn_5.e.ready, UInt<1>(0h1)
wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_40.bits.corrupt, UInt<1>(0h0)
connect _WIRE_40.bits.data, UInt<64>(0h0)
connect _WIRE_40.bits.mask, UInt<8>(0h0)
connect _WIRE_40.bits.address, UInt<32>(0h0)
connect _WIRE_40.bits.source, UInt<5>(0h0)
connect _WIRE_40.bits.size, UInt<3>(0h0)
connect _WIRE_40.bits.param, UInt<2>(0h0)
connect _WIRE_40.bits.opcode, UInt<3>(0h0)
connect _WIRE_40.valid, UInt<1>(0h0)
connect _WIRE_40.ready, UInt<1>(0h0)
wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_41.bits, _WIRE_40.bits
connect _WIRE_41.valid, _WIRE_40.valid
connect _WIRE_41.ready, _WIRE_40.ready
connect _WIRE_41.ready, UInt<1>(0h0)
wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_42.bits.corrupt, UInt<1>(0h0)
connect _WIRE_42.bits.data, UInt<64>(0h0)
connect _WIRE_42.bits.mask, UInt<8>(0h0)
connect _WIRE_42.bits.address, UInt<32>(0h0)
connect _WIRE_42.bits.source, UInt<5>(0h0)
connect _WIRE_42.bits.size, UInt<3>(0h0)
connect _WIRE_42.bits.param, UInt<2>(0h0)
connect _WIRE_42.bits.opcode, UInt<3>(0h0)
connect _WIRE_42.valid, UInt<1>(0h0)
connect _WIRE_42.ready, UInt<1>(0h0)
wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_43.bits, _WIRE_42.bits
connect _WIRE_43.valid, _WIRE_42.valid
connect _WIRE_43.ready, _WIRE_42.ready
node _T_341 = eq(_WIRE_43.valid, UInt<1>(0h0))
node _T_342 = asUInt(reset)
node _T_343 = eq(_T_342, UInt<1>(0h0))
when _T_343 :
node _T_344 = eq(_T_341, UInt<1>(0h0))
when _T_344 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:124 assert (!out.b.valid)\n") : printf_31
assert(clock, _T_341, UInt<1>(0h1), "") : assert_31
inst pool_5 of IDPool_5
connect pool_5.clock, clock
connect pool_5.reset, reset
node _pool_io_free_valid_T_5 = and(nodeIn_5.e.ready, nodeIn_5.e.valid)
connect pool_5.io.free.valid, _pool_io_free_valid_T_5
connect pool_5.io.free.bits, nodeIn_5.e.bits.sink
wire in_d_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _d_first_T_5 = and(in_d_5.ready, in_d_5.valid)
node _d_first_beats1_decode_T_15 = dshl(UInt<6>(0h3f), in_d_5.bits.size)
node _d_first_beats1_decode_T_16 = bits(_d_first_beats1_decode_T_15, 5, 0)
node _d_first_beats1_decode_T_17 = not(_d_first_beats1_decode_T_16)
node d_first_beats1_decode_5 = shr(_d_first_beats1_decode_T_17, 3)
node d_first_beats1_opdata_5 = bits(in_d_5.bits.opcode, 0, 0)
node d_first_beats1_5 = mux(d_first_beats1_opdata_5, d_first_beats1_decode_5, UInt<1>(0h0))
regreset d_first_counter_5 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_5 = sub(d_first_counter_5, UInt<1>(0h1))
node d_first_counter1_5 = tail(_d_first_counter1_T_5, 1)
node d_first_5 = eq(d_first_counter_5, UInt<1>(0h0))
node _d_first_last_T_10 = eq(d_first_counter_5, UInt<1>(0h1))
node _d_first_last_T_11 = eq(d_first_beats1_5, UInt<1>(0h0))
node d_first_last_5 = or(_d_first_last_T_10, _d_first_last_T_11)
node d_first_done_5 = and(d_first_last_5, _d_first_T_5)
node _d_first_count_T_5 = not(d_first_counter1_5)
node d_first_count_5 = and(d_first_beats1_5, _d_first_count_T_5)
when _d_first_T_5 :
node _d_first_counter_T_5 = mux(d_first_5, d_first_beats1_5, d_first_counter1_5)
connect d_first_counter_5, _d_first_counter_T_5
node _d_grant_T_10 = eq(in_d_5.bits.opcode, UInt<3>(0h5))
node _d_grant_T_11 = eq(in_d_5.bits.opcode, UInt<3>(0h4))
node d_grant_5 = or(_d_grant_T_10, _d_grant_T_11)
node _pool_io_alloc_ready_T_15 = and(nodeIn_5.d.ready, nodeIn_5.d.valid)
node _pool_io_alloc_ready_T_16 = and(_pool_io_alloc_ready_T_15, d_first_5)
node _pool_io_alloc_ready_T_17 = and(_pool_io_alloc_ready_T_16, d_grant_5)
connect pool_5.io.alloc.ready, _pool_io_alloc_ready_T_17
node _nodeIn_d_valid_T_25 = eq(d_first_5, UInt<1>(0h0))
node _nodeIn_d_valid_T_26 = or(pool_5.io.alloc.valid, _nodeIn_d_valid_T_25)
node _nodeIn_d_valid_T_27 = eq(d_grant_5, UInt<1>(0h0))
node _nodeIn_d_valid_T_28 = or(_nodeIn_d_valid_T_26, _nodeIn_d_valid_T_27)
node _nodeIn_d_valid_T_29 = and(in_d_5.valid, _nodeIn_d_valid_T_28)
connect nodeIn_5.d.valid, _nodeIn_d_valid_T_29
node _in_d_ready_T_25 = eq(d_first_5, UInt<1>(0h0))
node _in_d_ready_T_26 = or(pool_5.io.alloc.valid, _in_d_ready_T_25)
node _in_d_ready_T_27 = eq(d_grant_5, UInt<1>(0h0))
node _in_d_ready_T_28 = or(_in_d_ready_T_26, _in_d_ready_T_27)
node _in_d_ready_T_29 = and(nodeIn_5.d.ready, _in_d_ready_T_28)
connect in_d_5.ready, _in_d_ready_T_29
connect nodeIn_5.d.bits.corrupt, in_d_5.bits.corrupt
connect nodeIn_5.d.bits.data, in_d_5.bits.data
connect nodeIn_5.d.bits.denied, in_d_5.bits.denied
connect nodeIn_5.d.bits.sink, in_d_5.bits.sink
connect nodeIn_5.d.bits.source, in_d_5.bits.source
connect nodeIn_5.d.bits.size, in_d_5.bits.size
connect nodeIn_5.d.bits.param, in_d_5.bits.param
connect nodeIn_5.d.bits.opcode, in_d_5.bits.opcode
reg nodeIn_d_bits_sink_r_5 : UInt<3>, clock
when d_first_5 :
connect nodeIn_d_bits_sink_r_5, pool_5.io.alloc.bits
node _nodeIn_d_bits_sink_T_5 = mux(d_first_5, pool_5.io.alloc.bits, nodeIn_d_bits_sink_r_5)
connect nodeIn_5.d.bits.sink, _nodeIn_d_bits_sink_T_5
wire d_d_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect d_d_5, x1_nodeOut_4.d
node _d_d_bits_source_T_5 = shr(x1_nodeOut_4.d.bits.source, 1)
connect d_d_5.bits.source, _d_d_bits_source_T_5
reg wSourceVec_5 : UInt<1>[10], clock
node _aWOk_T_25 = xor(nodeIn_5.a.bits.address, UInt<1>(0h0))
node _aWOk_T_26 = cvt(_aWOk_T_25)
node _aWOk_T_27 = and(_aWOk_T_26, asSInt(UInt<1>(0h0)))
node _aWOk_T_28 = asSInt(_aWOk_T_27)
node _aWOk_T_29 = eq(_aWOk_T_28, asSInt(UInt<1>(0h0)))
node _bypass_T_10 = and(UInt<1>(0h0), nodeIn_5.a.valid)
node _bypass_T_11 = eq(nodeIn_5.a.bits.source, d_d_5.bits.source)
node bypass_5 = and(_bypass_T_10, _bypass_T_11)
node _dWHeld_T_5 = mux(bypass_5, UInt<1>(0h1), wSourceVec_5[d_d_5.bits.source])
reg dWHeld_r_5 : UInt<1>, clock
when d_first_5 :
connect dWHeld_r_5, _dWHeld_T_5
node dWHeld_5 = mux(d_first_5, _dWHeld_T_5, dWHeld_r_5)
node _T_345 = and(nodeIn_5.a.ready, nodeIn_5.a.valid)
when _T_345 :
connect wSourceVec_5[nodeIn_5.a.bits.source], UInt<1>(0h1)
node _T_346 = eq(x1_nodeOut_4.d.bits.opcode, UInt<1>(0h1))
node _T_347 = bits(x1_nodeOut_4.d.bits.source, 0, 0)
node _T_348 = and(_T_346, _T_347)
when _T_348 :
connect d_d_5.bits.opcode, UInt<3>(0h5)
node _d_d_bits_param_T_5 = mux(dWHeld_5, UInt<2>(0h0), UInt<2>(0h1))
connect d_d_5.bits.param, _d_d_bits_param_T_5
node _T_349 = eq(x1_nodeOut_4.d.bits.opcode, UInt<1>(0h0))
node _T_350 = bits(x1_nodeOut_4.d.bits.source, 0, 0)
node _T_351 = eq(_T_350, UInt<1>(0h0))
node _T_352 = and(_T_349, _T_351)
when _T_352 :
connect d_d_5.bits.opcode, UInt<3>(0h6)
node _decode_T_45 = dshl(UInt<6>(0h3f), c_a_5.bits.size)
node _decode_T_46 = bits(_decode_T_45, 5, 0)
node _decode_T_47 = not(_decode_T_46)
node decode_15 = shr(_decode_T_47, 3)
node _opdata_T_10 = bits(c_a_5.bits.opcode, 2, 2)
node opdata_15 = eq(_opdata_T_10, UInt<1>(0h0))
node _T_353 = mux(opdata_15, decode_15, UInt<1>(0h0))
node _decode_T_48 = dshl(UInt<6>(0h3f), a_a_5.bits.size)
node _decode_T_49 = bits(_decode_T_48, 5, 0)
node _decode_T_50 = not(_decode_T_49)
node decode_16 = shr(_decode_T_50, 3)
node _opdata_T_11 = bits(a_a_5.bits.opcode, 2, 2)
node opdata_16 = eq(_opdata_T_11, UInt<1>(0h0))
node _T_354 = mux(opdata_16, decode_16, UInt<1>(0h0))
regreset beatsLeft_10 : UInt, clock, reset, UInt<1>(0h0)
node idle_10 = eq(beatsLeft_10, UInt<1>(0h0))
node latch_10 = and(idle_10, x1_nodeOut_4.a.ready)
node _readys_T_120 = cat(a_a_5.valid, c_a_5.valid)
node _readys_T_121 = shl(_readys_T_120, 1)
node _readys_T_122 = bits(_readys_T_121, 1, 0)
node _readys_T_123 = or(_readys_T_120, _readys_T_122)
node _readys_T_124 = bits(_readys_T_123, 1, 0)
node _readys_T_125 = shl(_readys_T_124, 1)
node _readys_T_126 = bits(_readys_T_125, 1, 0)
node _readys_T_127 = not(_readys_T_126)
node _readys_T_128 = bits(_readys_T_127, 0, 0)
node _readys_T_129 = bits(_readys_T_127, 1, 1)
wire readys_10 : UInt<1>[2]
connect readys_10[0], _readys_T_128
connect readys_10[1], _readys_T_129
node _winner_T_25 = and(readys_10[0], c_a_5.valid)
node _winner_T_26 = and(readys_10[1], a_a_5.valid)
wire winner_10 : UInt<1>[2]
connect winner_10[0], _winner_T_25
connect winner_10[1], _winner_T_26
node prefixOR_1_10 = or(UInt<1>(0h0), winner_10[0])
node _prefixOR_T_10 = or(prefixOR_1_10, winner_10[1])
node _T_355 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_356 = eq(winner_10[0], UInt<1>(0h0))
node _T_357 = or(_T_355, _T_356)
node _T_358 = eq(prefixOR_1_10, UInt<1>(0h0))
node _T_359 = eq(winner_10[1], UInt<1>(0h0))
node _T_360 = or(_T_358, _T_359)
node _T_361 = and(_T_357, _T_360)
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_32
assert(clock, _T_361, UInt<1>(0h1), "") : assert_32
node _T_365 = or(c_a_5.valid, a_a_5.valid)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = or(winner_10[0], winner_10[1])
node _T_368 = or(_T_366, _T_367)
node _T_369 = asUInt(reset)
node _T_370 = eq(_T_369, UInt<1>(0h0))
when _T_370 :
node _T_371 = eq(_T_368, UInt<1>(0h0))
when _T_371 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_33
assert(clock, _T_368, UInt<1>(0h1), "") : assert_33
node maskedBeats_0_10 = mux(winner_10[0], _T_353, UInt<1>(0h0))
node maskedBeats_1_10 = mux(winner_10[1], _T_354, UInt<1>(0h0))
node initBeats_10 = or(maskedBeats_0_10, maskedBeats_1_10)
node _beatsLeft_T_40 = and(x1_nodeOut_4.a.ready, x1_nodeOut_4.a.valid)
node _beatsLeft_T_41 = sub(beatsLeft_10, _beatsLeft_T_40)
node _beatsLeft_T_42 = tail(_beatsLeft_T_41, 1)
node _beatsLeft_T_43 = mux(latch_10, initBeats_10, _beatsLeft_T_42)
connect beatsLeft_10, _beatsLeft_T_43
wire _state_WIRE_10 : UInt<1>[2]
connect _state_WIRE_10[0], UInt<1>(0h0)
connect _state_WIRE_10[1], UInt<1>(0h0)
regreset state_10 : UInt<1>[2], clock, reset, _state_WIRE_10
node muxState_10 = mux(idle_10, winner_10, state_10)
connect state_10, muxState_10
node allowed_10 = mux(idle_10, readys_10, state_10)
node _c_a_ready_T_5 = and(x1_nodeOut_4.a.ready, allowed_10[0])
connect c_a_5.ready, _c_a_ready_T_5
node _a_a_ready_T_5 = and(x1_nodeOut_4.a.ready, allowed_10[1])
connect a_a_5.ready, _a_a_ready_T_5
node _nodeOut_a_valid_T_25 = or(c_a_5.valid, a_a_5.valid)
node _nodeOut_a_valid_T_26 = mux(state_10[0], c_a_5.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_27 = mux(state_10[1], a_a_5.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_28 = or(_nodeOut_a_valid_T_26, _nodeOut_a_valid_T_27)
wire _nodeOut_a_valid_WIRE_5 : UInt<1>
connect _nodeOut_a_valid_WIRE_5, _nodeOut_a_valid_T_28
node _nodeOut_a_valid_T_29 = mux(idle_10, _nodeOut_a_valid_T_25, _nodeOut_a_valid_WIRE_5)
connect x1_nodeOut_4.a.valid, _nodeOut_a_valid_T_29
wire _nodeOut_a_bits_WIRE_55 : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _nodeOut_a_bits_T_120 = mux(muxState_10[0], c_a_5.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_121 = mux(muxState_10[1], a_a_5.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_122 = or(_nodeOut_a_bits_T_120, _nodeOut_a_bits_T_121)
wire _nodeOut_a_bits_WIRE_56 : UInt<1>
connect _nodeOut_a_bits_WIRE_56, _nodeOut_a_bits_T_122
connect _nodeOut_a_bits_WIRE_55.corrupt, _nodeOut_a_bits_WIRE_56
node _nodeOut_a_bits_T_123 = mux(muxState_10[0], c_a_5.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_124 = mux(muxState_10[1], a_a_5.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_125 = or(_nodeOut_a_bits_T_123, _nodeOut_a_bits_T_124)
wire _nodeOut_a_bits_WIRE_57 : UInt<64>
connect _nodeOut_a_bits_WIRE_57, _nodeOut_a_bits_T_125
connect _nodeOut_a_bits_WIRE_55.data, _nodeOut_a_bits_WIRE_57
node _nodeOut_a_bits_T_126 = mux(muxState_10[0], c_a_5.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_127 = mux(muxState_10[1], a_a_5.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_128 = or(_nodeOut_a_bits_T_126, _nodeOut_a_bits_T_127)
wire _nodeOut_a_bits_WIRE_58 : UInt<8>
connect _nodeOut_a_bits_WIRE_58, _nodeOut_a_bits_T_128
connect _nodeOut_a_bits_WIRE_55.mask, _nodeOut_a_bits_WIRE_58
wire _nodeOut_a_bits_WIRE_59 : { }
connect _nodeOut_a_bits_WIRE_55.echo, _nodeOut_a_bits_WIRE_59
wire _nodeOut_a_bits_WIRE_60 : { }
connect _nodeOut_a_bits_WIRE_55.user, _nodeOut_a_bits_WIRE_60
node _nodeOut_a_bits_T_129 = mux(muxState_10[0], c_a_5.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_130 = mux(muxState_10[1], a_a_5.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_131 = or(_nodeOut_a_bits_T_129, _nodeOut_a_bits_T_130)
wire _nodeOut_a_bits_WIRE_61 : UInt<32>
connect _nodeOut_a_bits_WIRE_61, _nodeOut_a_bits_T_131
connect _nodeOut_a_bits_WIRE_55.address, _nodeOut_a_bits_WIRE_61
node _nodeOut_a_bits_T_132 = mux(muxState_10[0], c_a_5.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_133 = mux(muxState_10[1], a_a_5.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_134 = or(_nodeOut_a_bits_T_132, _nodeOut_a_bits_T_133)
wire _nodeOut_a_bits_WIRE_62 : UInt<5>
connect _nodeOut_a_bits_WIRE_62, _nodeOut_a_bits_T_134
connect _nodeOut_a_bits_WIRE_55.source, _nodeOut_a_bits_WIRE_62
node _nodeOut_a_bits_T_135 = mux(muxState_10[0], c_a_5.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_136 = mux(muxState_10[1], a_a_5.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_137 = or(_nodeOut_a_bits_T_135, _nodeOut_a_bits_T_136)
wire _nodeOut_a_bits_WIRE_63 : UInt<3>
connect _nodeOut_a_bits_WIRE_63, _nodeOut_a_bits_T_137
connect _nodeOut_a_bits_WIRE_55.size, _nodeOut_a_bits_WIRE_63
node _nodeOut_a_bits_T_138 = mux(muxState_10[0], c_a_5.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_139 = mux(muxState_10[1], a_a_5.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_140 = or(_nodeOut_a_bits_T_138, _nodeOut_a_bits_T_139)
wire _nodeOut_a_bits_WIRE_64 : UInt<3>
connect _nodeOut_a_bits_WIRE_64, _nodeOut_a_bits_T_140
connect _nodeOut_a_bits_WIRE_55.param, _nodeOut_a_bits_WIRE_64
node _nodeOut_a_bits_T_141 = mux(muxState_10[0], c_a_5.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_142 = mux(muxState_10[1], a_a_5.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_143 = or(_nodeOut_a_bits_T_141, _nodeOut_a_bits_T_142)
wire _nodeOut_a_bits_WIRE_65 : UInt<3>
connect _nodeOut_a_bits_WIRE_65, _nodeOut_a_bits_T_143
connect _nodeOut_a_bits_WIRE_55.opcode, _nodeOut_a_bits_WIRE_65
connect x1_nodeOut_4.a.bits.corrupt, _nodeOut_a_bits_WIRE_55.corrupt
connect x1_nodeOut_4.a.bits.data, _nodeOut_a_bits_WIRE_55.data
connect x1_nodeOut_4.a.bits.mask, _nodeOut_a_bits_WIRE_55.mask
connect x1_nodeOut_4.a.bits.address, _nodeOut_a_bits_WIRE_55.address
connect x1_nodeOut_4.a.bits.source, _nodeOut_a_bits_WIRE_55.source
connect x1_nodeOut_4.a.bits.size, _nodeOut_a_bits_WIRE_55.size
connect x1_nodeOut_4.a.bits.param, _nodeOut_a_bits_WIRE_55.param
connect x1_nodeOut_4.a.bits.opcode, _nodeOut_a_bits_WIRE_55.opcode
node _decode_T_51 = dshl(UInt<6>(0h3f), d_d_5.bits.size)
node _decode_T_52 = bits(_decode_T_51, 5, 0)
node _decode_T_53 = not(_decode_T_52)
node decode_17 = shr(_decode_T_53, 3)
node opdata_17 = bits(d_d_5.bits.opcode, 0, 0)
node _T_372 = mux(opdata_17, decode_17, UInt<1>(0h0))
inst q_10 of Queue2_TLBundleD_a32d64s4k3z3c_18
connect q_10.clock, clock
connect q_10.reset, reset
connect q_10.io.enq.valid, c_d_5.valid
connect q_10.io.enq.bits.corrupt, c_d_5.bits.corrupt
connect q_10.io.enq.bits.data, c_d_5.bits.data
connect q_10.io.enq.bits.denied, c_d_5.bits.denied
connect q_10.io.enq.bits.sink, c_d_5.bits.sink
connect q_10.io.enq.bits.source, c_d_5.bits.source
connect q_10.io.enq.bits.size, c_d_5.bits.size
connect q_10.io.enq.bits.param, c_d_5.bits.param
connect q_10.io.enq.bits.opcode, c_d_5.bits.opcode
connect c_d_5.ready, q_10.io.enq.ready
inst q_11 of Queue2_TLBundleD_a32d64s4k3z3c_19
connect q_11.clock, clock
connect q_11.reset, reset
connect q_11.io.enq.valid, a_d_5.valid
connect q_11.io.enq.bits.corrupt, a_d_5.bits.corrupt
connect q_11.io.enq.bits.data, a_d_5.bits.data
connect q_11.io.enq.bits.denied, a_d_5.bits.denied
connect q_11.io.enq.bits.sink, a_d_5.bits.sink
connect q_11.io.enq.bits.source, a_d_5.bits.source
connect q_11.io.enq.bits.size, a_d_5.bits.size
connect q_11.io.enq.bits.param, a_d_5.bits.param
connect q_11.io.enq.bits.opcode, a_d_5.bits.opcode
connect a_d_5.ready, q_11.io.enq.ready
regreset beatsLeft_11 : UInt, clock, reset, UInt<1>(0h0)
node idle_11 = eq(beatsLeft_11, UInt<1>(0h0))
node latch_11 = and(idle_11, in_d_5.ready)
node readys_hi_5 = cat(q_11.io.deq.valid, q_10.io.deq.valid)
node _readys_T_130 = cat(readys_hi_5, d_d_5.valid)
node _readys_T_131 = shl(_readys_T_130, 1)
node _readys_T_132 = bits(_readys_T_131, 2, 0)
node _readys_T_133 = or(_readys_T_130, _readys_T_132)
node _readys_T_134 = shl(_readys_T_133, 2)
node _readys_T_135 = bits(_readys_T_134, 2, 0)
node _readys_T_136 = or(_readys_T_133, _readys_T_135)
node _readys_T_137 = bits(_readys_T_136, 2, 0)
node _readys_T_138 = shl(_readys_T_137, 1)
node _readys_T_139 = bits(_readys_T_138, 2, 0)
node _readys_T_140 = not(_readys_T_139)
node _readys_T_141 = bits(_readys_T_140, 0, 0)
node _readys_T_142 = bits(_readys_T_140, 1, 1)
node _readys_T_143 = bits(_readys_T_140, 2, 2)
wire readys_11 : UInt<1>[3]
connect readys_11[0], _readys_T_141
connect readys_11[1], _readys_T_142
connect readys_11[2], _readys_T_143
node _winner_T_27 = and(readys_11[0], d_d_5.valid)
node _winner_T_28 = and(readys_11[1], q_10.io.deq.valid)
node _winner_T_29 = and(readys_11[2], q_11.io.deq.valid)
wire winner_11 : UInt<1>[3]
connect winner_11[0], _winner_T_27
connect winner_11[1], _winner_T_28
connect winner_11[2], _winner_T_29
node prefixOR_1_11 = or(UInt<1>(0h0), winner_11[0])
node prefixOR_2_5 = or(prefixOR_1_11, winner_11[1])
node _prefixOR_T_11 = or(prefixOR_2_5, winner_11[2])
node _T_373 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_374 = eq(winner_11[0], UInt<1>(0h0))
node _T_375 = or(_T_373, _T_374)
node _T_376 = eq(prefixOR_1_11, UInt<1>(0h0))
node _T_377 = eq(winner_11[1], UInt<1>(0h0))
node _T_378 = or(_T_376, _T_377)
node _T_379 = eq(prefixOR_2_5, UInt<1>(0h0))
node _T_380 = eq(winner_11[2], UInt<1>(0h0))
node _T_381 = or(_T_379, _T_380)
node _T_382 = and(_T_375, _T_378)
node _T_383 = and(_T_382, _T_381)
node _T_384 = asUInt(reset)
node _T_385 = eq(_T_384, UInt<1>(0h0))
when _T_385 :
node _T_386 = eq(_T_383, UInt<1>(0h0))
when _T_386 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_34
assert(clock, _T_383, UInt<1>(0h1), "") : assert_34
node _T_387 = or(d_d_5.valid, q_10.io.deq.valid)
node _T_388 = or(_T_387, q_11.io.deq.valid)
node _T_389 = eq(_T_388, UInt<1>(0h0))
node _T_390 = or(winner_11[0], winner_11[1])
node _T_391 = or(_T_390, winner_11[2])
node _T_392 = or(_T_389, _T_391)
node _T_393 = asUInt(reset)
node _T_394 = eq(_T_393, UInt<1>(0h0))
when _T_394 :
node _T_395 = eq(_T_392, UInt<1>(0h0))
when _T_395 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_35
assert(clock, _T_392, UInt<1>(0h1), "") : assert_35
node maskedBeats_0_11 = mux(winner_11[0], _T_372, UInt<1>(0h0))
node maskedBeats_1_11 = mux(winner_11[1], UInt<1>(0h0), UInt<1>(0h0))
node maskedBeats_2_5 = mux(winner_11[2], UInt<1>(0h0), UInt<1>(0h0))
node _initBeats_T_5 = or(maskedBeats_0_11, maskedBeats_1_11)
node initBeats_11 = or(_initBeats_T_5, maskedBeats_2_5)
node _beatsLeft_T_44 = and(in_d_5.ready, in_d_5.valid)
node _beatsLeft_T_45 = sub(beatsLeft_11, _beatsLeft_T_44)
node _beatsLeft_T_46 = tail(_beatsLeft_T_45, 1)
node _beatsLeft_T_47 = mux(latch_11, initBeats_11, _beatsLeft_T_46)
connect beatsLeft_11, _beatsLeft_T_47
wire _state_WIRE_11 : UInt<1>[3]
connect _state_WIRE_11[0], UInt<1>(0h0)
connect _state_WIRE_11[1], UInt<1>(0h0)
connect _state_WIRE_11[2], UInt<1>(0h0)
regreset state_11 : UInt<1>[3], clock, reset, _state_WIRE_11
node muxState_11 = mux(idle_11, winner_11, state_11)
connect state_11, muxState_11
node allowed_11 = mux(idle_11, readys_11, state_11)
node _d_d_ready_T_5 = and(in_d_5.ready, allowed_11[0])
connect d_d_5.ready, _d_d_ready_T_5
node _q_io_deq_ready_T_10 = and(in_d_5.ready, allowed_11[1])
connect q_10.io.deq.ready, _q_io_deq_ready_T_10
node _q_io_deq_ready_T_11 = and(in_d_5.ready, allowed_11[2])
connect q_11.io.deq.ready, _q_io_deq_ready_T_11
node _in_d_valid_T_40 = or(d_d_5.valid, q_10.io.deq.valid)
node _in_d_valid_T_41 = or(_in_d_valid_T_40, q_11.io.deq.valid)
node _in_d_valid_T_42 = mux(state_11[0], d_d_5.valid, UInt<1>(0h0))
node _in_d_valid_T_43 = mux(state_11[1], q_10.io.deq.valid, UInt<1>(0h0))
node _in_d_valid_T_44 = mux(state_11[2], q_11.io.deq.valid, UInt<1>(0h0))
node _in_d_valid_T_45 = or(_in_d_valid_T_42, _in_d_valid_T_43)
node _in_d_valid_T_46 = or(_in_d_valid_T_45, _in_d_valid_T_44)
wire _in_d_valid_WIRE_5 : UInt<1>
connect _in_d_valid_WIRE_5, _in_d_valid_T_46
node _in_d_valid_T_47 = mux(idle_11, _in_d_valid_T_41, _in_d_valid_WIRE_5)
connect in_d_5.valid, _in_d_valid_T_47
wire _in_d_bits_WIRE_55 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_d_bits_T_200 = mux(muxState_11[0], d_d_5.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_201 = mux(muxState_11[1], q_10.io.deq.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_202 = mux(muxState_11[2], q_11.io.deq.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_203 = or(_in_d_bits_T_200, _in_d_bits_T_201)
node _in_d_bits_T_204 = or(_in_d_bits_T_203, _in_d_bits_T_202)
wire _in_d_bits_WIRE_56 : UInt<1>
connect _in_d_bits_WIRE_56, _in_d_bits_T_204
connect _in_d_bits_WIRE_55.corrupt, _in_d_bits_WIRE_56
node _in_d_bits_T_205 = mux(muxState_11[0], d_d_5.bits.data, UInt<1>(0h0))
node _in_d_bits_T_206 = mux(muxState_11[1], q_10.io.deq.bits.data, UInt<1>(0h0))
node _in_d_bits_T_207 = mux(muxState_11[2], q_11.io.deq.bits.data, UInt<1>(0h0))
node _in_d_bits_T_208 = or(_in_d_bits_T_205, _in_d_bits_T_206)
node _in_d_bits_T_209 = or(_in_d_bits_T_208, _in_d_bits_T_207)
wire _in_d_bits_WIRE_57 : UInt<64>
connect _in_d_bits_WIRE_57, _in_d_bits_T_209
connect _in_d_bits_WIRE_55.data, _in_d_bits_WIRE_57
wire _in_d_bits_WIRE_58 : { }
connect _in_d_bits_WIRE_55.echo, _in_d_bits_WIRE_58
wire _in_d_bits_WIRE_59 : { }
connect _in_d_bits_WIRE_55.user, _in_d_bits_WIRE_59
node _in_d_bits_T_210 = mux(muxState_11[0], d_d_5.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_211 = mux(muxState_11[1], q_10.io.deq.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_212 = mux(muxState_11[2], q_11.io.deq.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_213 = or(_in_d_bits_T_210, _in_d_bits_T_211)
node _in_d_bits_T_214 = or(_in_d_bits_T_213, _in_d_bits_T_212)
wire _in_d_bits_WIRE_60 : UInt<1>
connect _in_d_bits_WIRE_60, _in_d_bits_T_214
connect _in_d_bits_WIRE_55.denied, _in_d_bits_WIRE_60
node _in_d_bits_T_215 = mux(muxState_11[0], d_d_5.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_216 = mux(muxState_11[1], q_10.io.deq.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_217 = mux(muxState_11[2], q_11.io.deq.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_218 = or(_in_d_bits_T_215, _in_d_bits_T_216)
node _in_d_bits_T_219 = or(_in_d_bits_T_218, _in_d_bits_T_217)
wire _in_d_bits_WIRE_61 : UInt<3>
connect _in_d_bits_WIRE_61, _in_d_bits_T_219
connect _in_d_bits_WIRE_55.sink, _in_d_bits_WIRE_61
node _in_d_bits_T_220 = mux(muxState_11[0], d_d_5.bits.source, UInt<1>(0h0))
node _in_d_bits_T_221 = mux(muxState_11[1], q_10.io.deq.bits.source, UInt<1>(0h0))
node _in_d_bits_T_222 = mux(muxState_11[2], q_11.io.deq.bits.source, UInt<1>(0h0))
node _in_d_bits_T_223 = or(_in_d_bits_T_220, _in_d_bits_T_221)
node _in_d_bits_T_224 = or(_in_d_bits_T_223, _in_d_bits_T_222)
wire _in_d_bits_WIRE_62 : UInt<4>
connect _in_d_bits_WIRE_62, _in_d_bits_T_224
connect _in_d_bits_WIRE_55.source, _in_d_bits_WIRE_62
node _in_d_bits_T_225 = mux(muxState_11[0], d_d_5.bits.size, UInt<1>(0h0))
node _in_d_bits_T_226 = mux(muxState_11[1], q_10.io.deq.bits.size, UInt<1>(0h0))
node _in_d_bits_T_227 = mux(muxState_11[2], q_11.io.deq.bits.size, UInt<1>(0h0))
node _in_d_bits_T_228 = or(_in_d_bits_T_225, _in_d_bits_T_226)
node _in_d_bits_T_229 = or(_in_d_bits_T_228, _in_d_bits_T_227)
wire _in_d_bits_WIRE_63 : UInt<3>
connect _in_d_bits_WIRE_63, _in_d_bits_T_229
connect _in_d_bits_WIRE_55.size, _in_d_bits_WIRE_63
node _in_d_bits_T_230 = mux(muxState_11[0], d_d_5.bits.param, UInt<1>(0h0))
node _in_d_bits_T_231 = mux(muxState_11[1], q_10.io.deq.bits.param, UInt<1>(0h0))
node _in_d_bits_T_232 = mux(muxState_11[2], q_11.io.deq.bits.param, UInt<1>(0h0))
node _in_d_bits_T_233 = or(_in_d_bits_T_230, _in_d_bits_T_231)
node _in_d_bits_T_234 = or(_in_d_bits_T_233, _in_d_bits_T_232)
wire _in_d_bits_WIRE_64 : UInt<2>
connect _in_d_bits_WIRE_64, _in_d_bits_T_234
connect _in_d_bits_WIRE_55.param, _in_d_bits_WIRE_64
node _in_d_bits_T_235 = mux(muxState_11[0], d_d_5.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_236 = mux(muxState_11[1], q_10.io.deq.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_237 = mux(muxState_11[2], q_11.io.deq.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_238 = or(_in_d_bits_T_235, _in_d_bits_T_236)
node _in_d_bits_T_239 = or(_in_d_bits_T_238, _in_d_bits_T_237)
wire _in_d_bits_WIRE_65 : UInt<3>
connect _in_d_bits_WIRE_65, _in_d_bits_T_239
connect _in_d_bits_WIRE_55.opcode, _in_d_bits_WIRE_65
connect in_d_5.bits.corrupt, _in_d_bits_WIRE_55.corrupt
connect in_d_5.bits.data, _in_d_bits_WIRE_55.data
connect in_d_5.bits.denied, _in_d_bits_WIRE_55.denied
connect in_d_5.bits.sink, _in_d_bits_WIRE_55.sink
connect in_d_5.bits.source, _in_d_bits_WIRE_55.source
connect in_d_5.bits.size, _in_d_bits_WIRE_55.size
connect in_d_5.bits.param, _in_d_bits_WIRE_55.param
connect in_d_5.bits.opcode, _in_d_bits_WIRE_55.opcode
connect nodeIn_5.b.valid, UInt<1>(0h0)
wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_44.bits.corrupt, UInt<1>(0h0)
connect _WIRE_44.bits.data, UInt<64>(0h0)
connect _WIRE_44.bits.address, UInt<32>(0h0)
connect _WIRE_44.bits.source, UInt<5>(0h0)
connect _WIRE_44.bits.size, UInt<3>(0h0)
connect _WIRE_44.bits.param, UInt<3>(0h0)
connect _WIRE_44.bits.opcode, UInt<3>(0h0)
connect _WIRE_44.valid, UInt<1>(0h0)
connect _WIRE_44.ready, UInt<1>(0h0)
wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_45.bits, _WIRE_44.bits
connect _WIRE_45.valid, _WIRE_44.valid
connect _WIRE_45.ready, _WIRE_44.ready
connect _WIRE_45.valid, UInt<1>(0h0)
wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_46.bits.sink, UInt<1>(0h0)
connect _WIRE_46.valid, UInt<1>(0h0)
connect _WIRE_46.ready, UInt<1>(0h0)
wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_47.bits, _WIRE_46.bits
connect _WIRE_47.valid, _WIRE_46.valid
connect _WIRE_47.ready, _WIRE_46.ready
connect _WIRE_47.valid, UInt<1>(0h0)
wire a_a_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
wire a_d_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _isPut_T_12 = eq(nodeIn_6.a.bits.opcode, UInt<1>(0h0))
node _isPut_T_13 = eq(nodeIn_6.a.bits.opcode, UInt<1>(0h1))
node isPut_6 = or(_isPut_T_12, _isPut_T_13)
node _toD_T_24 = eq(nodeIn_6.a.bits.opcode, UInt<3>(0h6))
node _toD_T_25 = eq(nodeIn_6.a.bits.param, UInt<2>(0h2))
node _toD_T_26 = and(_toD_T_24, _toD_T_25)
node _toD_T_27 = eq(nodeIn_6.a.bits.opcode, UInt<3>(0h7))
node toD_6 = or(_toD_T_26, _toD_T_27)
node _nodeIn_a_ready_T_6 = mux(toD_6, a_d_6.ready, a_a_6.ready)
connect nodeIn_6.a.ready, _nodeIn_a_ready_T_6
node _a_a_valid_T_12 = eq(toD_6, UInt<1>(0h0))
node _a_a_valid_T_13 = and(nodeIn_6.a.valid, _a_a_valid_T_12)
connect a_a_6.valid, _a_a_valid_T_13
connect a_a_6.bits, nodeIn_6.a.bits
node _a_a_bits_source_T_30 = shl(nodeIn_6.a.bits.source, 1)
node _a_a_bits_source_T_31 = mux(isPut_6, UInt<1>(0h1), UInt<1>(0h0))
node _a_a_bits_source_T_32 = or(_a_a_bits_source_T_30, _a_a_bits_source_T_31)
connect a_a_6.bits.source, _a_a_bits_source_T_32
node _T_396 = eq(nodeIn_6.a.bits.opcode, UInt<3>(0h6))
node _T_397 = eq(nodeIn_6.a.bits.opcode, UInt<3>(0h7))
node _T_398 = or(_T_396, _T_397)
when _T_398 :
connect a_a_6.bits.opcode, UInt<3>(0h4)
connect a_a_6.bits.param, UInt<1>(0h0)
node _a_a_bits_source_T_33 = shl(nodeIn_6.a.bits.source, 1)
node _a_a_bits_source_T_34 = or(_a_a_bits_source_T_33, UInt<1>(0h1))
connect a_a_6.bits.source, _a_a_bits_source_T_34
node _a_d_valid_T_6 = and(nodeIn_6.a.valid, toD_6)
connect a_d_6.valid, _a_d_valid_T_6
wire a_d_bits_d_6 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect a_d_bits_d_6.opcode, UInt<3>(0h4)
connect a_d_bits_d_6.param, UInt<2>(0h0)
connect a_d_bits_d_6.size, nodeIn_6.a.bits.size
connect a_d_bits_d_6.source, nodeIn_6.a.bits.source
connect a_d_bits_d_6.sink, UInt<1>(0h0)
connect a_d_bits_d_6.denied, UInt<1>(0h0)
invalidate a_d_bits_d_6.data
connect a_d_bits_d_6.corrupt, UInt<1>(0h0)
connect a_d_6.bits.corrupt, a_d_bits_d_6.corrupt
connect a_d_6.bits.data, a_d_bits_d_6.data
connect a_d_6.bits.denied, a_d_bits_d_6.denied
connect a_d_6.bits.sink, a_d_bits_d_6.sink
connect a_d_6.bits.source, a_d_bits_d_6.source
connect a_d_6.bits.size, a_d_bits_d_6.size
connect a_d_6.bits.param, a_d_bits_d_6.param
connect a_d_6.bits.opcode, a_d_bits_d_6.opcode
wire c_a_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
node _c_a_valid_T_12 = eq(nodeIn_6.c.bits.opcode, UInt<3>(0h7))
node _c_a_valid_T_13 = and(nodeIn_6.c.valid, _c_a_valid_T_12)
connect c_a_6.valid, _c_a_valid_T_13
node _c_a_bits_T_6 = shl(nodeIn_6.c.bits.source, 1)
node _c_a_bits_legal_T_60 = leq(UInt<1>(0h0), nodeIn_6.c.bits.size)
node _c_a_bits_legal_T_61 = leq(nodeIn_6.c.bits.size, UInt<3>(0h6))
node _c_a_bits_legal_T_62 = and(_c_a_bits_legal_T_60, _c_a_bits_legal_T_61)
node _c_a_bits_legal_T_63 = or(UInt<1>(0h0), _c_a_bits_legal_T_62)
node _c_a_bits_legal_T_64 = xor(nodeIn_6.c.bits.address, UInt<1>(0h0))
node _c_a_bits_legal_T_65 = cvt(_c_a_bits_legal_T_64)
node _c_a_bits_legal_T_66 = and(_c_a_bits_legal_T_65, asSInt(UInt<1>(0h0)))
node _c_a_bits_legal_T_67 = asSInt(_c_a_bits_legal_T_66)
node _c_a_bits_legal_T_68 = eq(_c_a_bits_legal_T_67, asSInt(UInt<1>(0h0)))
node _c_a_bits_legal_T_69 = and(_c_a_bits_legal_T_63, _c_a_bits_legal_T_68)
node c_a_bits_legal_6 = or(UInt<1>(0h0), _c_a_bits_legal_T_69)
wire c_a_bits_a_6 : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect c_a_bits_a_6.opcode, UInt<1>(0h0)
connect c_a_bits_a_6.param, UInt<1>(0h0)
connect c_a_bits_a_6.size, nodeIn_6.c.bits.size
connect c_a_bits_a_6.source, _c_a_bits_T_6
connect c_a_bits_a_6.address, nodeIn_6.c.bits.address
node _c_a_bits_a_mask_sizeOH_T_18 = or(nodeIn_6.c.bits.size, UInt<3>(0h0))
node c_a_bits_a_mask_sizeOH_shiftAmount_6 = bits(_c_a_bits_a_mask_sizeOH_T_18, 1, 0)
node _c_a_bits_a_mask_sizeOH_T_19 = dshl(UInt<1>(0h1), c_a_bits_a_mask_sizeOH_shiftAmount_6)
node _c_a_bits_a_mask_sizeOH_T_20 = bits(_c_a_bits_a_mask_sizeOH_T_19, 2, 0)
node c_a_bits_a_mask_sizeOH_6 = or(_c_a_bits_a_mask_sizeOH_T_20, UInt<1>(0h1))
node c_a_bits_a_mask_sub_sub_sub_0_1_6 = geq(nodeIn_6.c.bits.size, UInt<2>(0h3))
node c_a_bits_a_mask_sub_sub_size_6 = bits(c_a_bits_a_mask_sizeOH_6, 2, 2)
node c_a_bits_a_mask_sub_sub_bit_6 = bits(nodeIn_6.c.bits.address, 2, 2)
node c_a_bits_a_mask_sub_sub_nbit_6 = eq(c_a_bits_a_mask_sub_sub_bit_6, UInt<1>(0h0))
node c_a_bits_a_mask_sub_sub_0_2_6 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_nbit_6)
node _c_a_bits_a_mask_sub_sub_acc_T_12 = and(c_a_bits_a_mask_sub_sub_size_6, c_a_bits_a_mask_sub_sub_0_2_6)
node c_a_bits_a_mask_sub_sub_0_1_6 = or(c_a_bits_a_mask_sub_sub_sub_0_1_6, _c_a_bits_a_mask_sub_sub_acc_T_12)
node c_a_bits_a_mask_sub_sub_1_2_6 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_bit_6)
node _c_a_bits_a_mask_sub_sub_acc_T_13 = and(c_a_bits_a_mask_sub_sub_size_6, c_a_bits_a_mask_sub_sub_1_2_6)
node c_a_bits_a_mask_sub_sub_1_1_6 = or(c_a_bits_a_mask_sub_sub_sub_0_1_6, _c_a_bits_a_mask_sub_sub_acc_T_13)
node c_a_bits_a_mask_sub_size_6 = bits(c_a_bits_a_mask_sizeOH_6, 1, 1)
node c_a_bits_a_mask_sub_bit_6 = bits(nodeIn_6.c.bits.address, 1, 1)
node c_a_bits_a_mask_sub_nbit_6 = eq(c_a_bits_a_mask_sub_bit_6, UInt<1>(0h0))
node c_a_bits_a_mask_sub_0_2_6 = and(c_a_bits_a_mask_sub_sub_0_2_6, c_a_bits_a_mask_sub_nbit_6)
node _c_a_bits_a_mask_sub_acc_T_24 = and(c_a_bits_a_mask_sub_size_6, c_a_bits_a_mask_sub_0_2_6)
node c_a_bits_a_mask_sub_0_1_6 = or(c_a_bits_a_mask_sub_sub_0_1_6, _c_a_bits_a_mask_sub_acc_T_24)
node c_a_bits_a_mask_sub_1_2_6 = and(c_a_bits_a_mask_sub_sub_0_2_6, c_a_bits_a_mask_sub_bit_6)
node _c_a_bits_a_mask_sub_acc_T_25 = and(c_a_bits_a_mask_sub_size_6, c_a_bits_a_mask_sub_1_2_6)
node c_a_bits_a_mask_sub_1_1_6 = or(c_a_bits_a_mask_sub_sub_0_1_6, _c_a_bits_a_mask_sub_acc_T_25)
node c_a_bits_a_mask_sub_2_2_6 = and(c_a_bits_a_mask_sub_sub_1_2_6, c_a_bits_a_mask_sub_nbit_6)
node _c_a_bits_a_mask_sub_acc_T_26 = and(c_a_bits_a_mask_sub_size_6, c_a_bits_a_mask_sub_2_2_6)
node c_a_bits_a_mask_sub_2_1_6 = or(c_a_bits_a_mask_sub_sub_1_1_6, _c_a_bits_a_mask_sub_acc_T_26)
node c_a_bits_a_mask_sub_3_2_6 = and(c_a_bits_a_mask_sub_sub_1_2_6, c_a_bits_a_mask_sub_bit_6)
node _c_a_bits_a_mask_sub_acc_T_27 = and(c_a_bits_a_mask_sub_size_6, c_a_bits_a_mask_sub_3_2_6)
node c_a_bits_a_mask_sub_3_1_6 = or(c_a_bits_a_mask_sub_sub_1_1_6, _c_a_bits_a_mask_sub_acc_T_27)
node c_a_bits_a_mask_size_6 = bits(c_a_bits_a_mask_sizeOH_6, 0, 0)
node c_a_bits_a_mask_bit_6 = bits(nodeIn_6.c.bits.address, 0, 0)
node c_a_bits_a_mask_nbit_6 = eq(c_a_bits_a_mask_bit_6, UInt<1>(0h0))
node c_a_bits_a_mask_eq_48 = and(c_a_bits_a_mask_sub_0_2_6, c_a_bits_a_mask_nbit_6)
node _c_a_bits_a_mask_acc_T_48 = and(c_a_bits_a_mask_size_6, c_a_bits_a_mask_eq_48)
node c_a_bits_a_mask_acc_48 = or(c_a_bits_a_mask_sub_0_1_6, _c_a_bits_a_mask_acc_T_48)
node c_a_bits_a_mask_eq_49 = and(c_a_bits_a_mask_sub_0_2_6, c_a_bits_a_mask_bit_6)
node _c_a_bits_a_mask_acc_T_49 = and(c_a_bits_a_mask_size_6, c_a_bits_a_mask_eq_49)
node c_a_bits_a_mask_acc_49 = or(c_a_bits_a_mask_sub_0_1_6, _c_a_bits_a_mask_acc_T_49)
node c_a_bits_a_mask_eq_50 = and(c_a_bits_a_mask_sub_1_2_6, c_a_bits_a_mask_nbit_6)
node _c_a_bits_a_mask_acc_T_50 = and(c_a_bits_a_mask_size_6, c_a_bits_a_mask_eq_50)
node c_a_bits_a_mask_acc_50 = or(c_a_bits_a_mask_sub_1_1_6, _c_a_bits_a_mask_acc_T_50)
node c_a_bits_a_mask_eq_51 = and(c_a_bits_a_mask_sub_1_2_6, c_a_bits_a_mask_bit_6)
node _c_a_bits_a_mask_acc_T_51 = and(c_a_bits_a_mask_size_6, c_a_bits_a_mask_eq_51)
node c_a_bits_a_mask_acc_51 = or(c_a_bits_a_mask_sub_1_1_6, _c_a_bits_a_mask_acc_T_51)
node c_a_bits_a_mask_eq_52 = and(c_a_bits_a_mask_sub_2_2_6, c_a_bits_a_mask_nbit_6)
node _c_a_bits_a_mask_acc_T_52 = and(c_a_bits_a_mask_size_6, c_a_bits_a_mask_eq_52)
node c_a_bits_a_mask_acc_52 = or(c_a_bits_a_mask_sub_2_1_6, _c_a_bits_a_mask_acc_T_52)
node c_a_bits_a_mask_eq_53 = and(c_a_bits_a_mask_sub_2_2_6, c_a_bits_a_mask_bit_6)
node _c_a_bits_a_mask_acc_T_53 = and(c_a_bits_a_mask_size_6, c_a_bits_a_mask_eq_53)
node c_a_bits_a_mask_acc_53 = or(c_a_bits_a_mask_sub_2_1_6, _c_a_bits_a_mask_acc_T_53)
node c_a_bits_a_mask_eq_54 = and(c_a_bits_a_mask_sub_3_2_6, c_a_bits_a_mask_nbit_6)
node _c_a_bits_a_mask_acc_T_54 = and(c_a_bits_a_mask_size_6, c_a_bits_a_mask_eq_54)
node c_a_bits_a_mask_acc_54 = or(c_a_bits_a_mask_sub_3_1_6, _c_a_bits_a_mask_acc_T_54)
node c_a_bits_a_mask_eq_55 = and(c_a_bits_a_mask_sub_3_2_6, c_a_bits_a_mask_bit_6)
node _c_a_bits_a_mask_acc_T_55 = and(c_a_bits_a_mask_size_6, c_a_bits_a_mask_eq_55)
node c_a_bits_a_mask_acc_55 = or(c_a_bits_a_mask_sub_3_1_6, _c_a_bits_a_mask_acc_T_55)
node c_a_bits_a_mask_lo_lo_6 = cat(c_a_bits_a_mask_acc_49, c_a_bits_a_mask_acc_48)
node c_a_bits_a_mask_lo_hi_6 = cat(c_a_bits_a_mask_acc_51, c_a_bits_a_mask_acc_50)
node c_a_bits_a_mask_lo_6 = cat(c_a_bits_a_mask_lo_hi_6, c_a_bits_a_mask_lo_lo_6)
node c_a_bits_a_mask_hi_lo_6 = cat(c_a_bits_a_mask_acc_53, c_a_bits_a_mask_acc_52)
node c_a_bits_a_mask_hi_hi_6 = cat(c_a_bits_a_mask_acc_55, c_a_bits_a_mask_acc_54)
node c_a_bits_a_mask_hi_6 = cat(c_a_bits_a_mask_hi_hi_6, c_a_bits_a_mask_hi_lo_6)
node _c_a_bits_a_mask_T_6 = cat(c_a_bits_a_mask_hi_6, c_a_bits_a_mask_lo_6)
connect c_a_bits_a_6.mask, _c_a_bits_a_mask_T_6
connect c_a_bits_a_6.data, nodeIn_6.c.bits.data
connect c_a_bits_a_6.corrupt, nodeIn_6.c.bits.corrupt
connect c_a_6.bits, c_a_bits_a_6
wire c_d_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _c_d_valid_T_12 = eq(nodeIn_6.c.bits.opcode, UInt<3>(0h6))
node _c_d_valid_T_13 = and(nodeIn_6.c.valid, _c_d_valid_T_12)
connect c_d_6.valid, _c_d_valid_T_13
wire c_d_bits_d_6 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect c_d_bits_d_6.opcode, UInt<3>(0h6)
connect c_d_bits_d_6.param, UInt<1>(0h0)
connect c_d_bits_d_6.size, nodeIn_6.c.bits.size
connect c_d_bits_d_6.source, nodeIn_6.c.bits.source
connect c_d_bits_d_6.sink, UInt<1>(0h0)
connect c_d_bits_d_6.denied, UInt<1>(0h0)
invalidate c_d_bits_d_6.data
connect c_d_bits_d_6.corrupt, UInt<1>(0h0)
connect c_d_6.bits.corrupt, c_d_bits_d_6.corrupt
connect c_d_6.bits.data, c_d_bits_d_6.data
connect c_d_6.bits.denied, c_d_bits_d_6.denied
connect c_d_6.bits.sink, c_d_bits_d_6.sink
connect c_d_6.bits.source, c_d_bits_d_6.source
connect c_d_6.bits.size, c_d_bits_d_6.size
connect c_d_6.bits.param, c_d_bits_d_6.param
connect c_d_6.bits.opcode, c_d_bits_d_6.opcode
node _T_399 = eq(nodeIn_6.c.valid, UInt<1>(0h0))
node _T_400 = eq(nodeIn_6.c.bits.opcode, UInt<3>(0h6))
node _T_401 = or(_T_399, _T_400)
node _T_402 = eq(nodeIn_6.c.bits.opcode, UInt<3>(0h7))
node _T_403 = or(_T_401, _T_402)
node _T_404 = asUInt(reset)
node _T_405 = eq(_T_404, UInt<1>(0h0))
when _T_405 :
node _T_406 = eq(_T_403, UInt<1>(0h0))
when _T_406 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:116 assert (!in.c.valid || in.c.bits.opcode === Release || in.c.bits.opcode === ReleaseData)\n") : printf_36
assert(clock, _T_403, UInt<1>(0h1), "") : assert_36
node _nodeIn_c_ready_T_12 = eq(nodeIn_6.c.bits.opcode, UInt<3>(0h6))
node _nodeIn_c_ready_T_13 = mux(_nodeIn_c_ready_T_12, c_d_6.ready, c_a_6.ready)
connect nodeIn_6.c.ready, _nodeIn_c_ready_T_13
connect nodeIn_6.e.ready, UInt<1>(0h1)
wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_48.bits.corrupt, UInt<1>(0h0)
connect _WIRE_48.bits.data, UInt<64>(0h0)
connect _WIRE_48.bits.mask, UInt<8>(0h0)
connect _WIRE_48.bits.address, UInt<32>(0h0)
connect _WIRE_48.bits.source, UInt<5>(0h0)
connect _WIRE_48.bits.size, UInt<3>(0h0)
connect _WIRE_48.bits.param, UInt<2>(0h0)
connect _WIRE_48.bits.opcode, UInt<3>(0h0)
connect _WIRE_48.valid, UInt<1>(0h0)
connect _WIRE_48.ready, UInt<1>(0h0)
wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_49.bits, _WIRE_48.bits
connect _WIRE_49.valid, _WIRE_48.valid
connect _WIRE_49.ready, _WIRE_48.ready
connect _WIRE_49.ready, UInt<1>(0h0)
wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_50.bits.corrupt, UInt<1>(0h0)
connect _WIRE_50.bits.data, UInt<64>(0h0)
connect _WIRE_50.bits.mask, UInt<8>(0h0)
connect _WIRE_50.bits.address, UInt<32>(0h0)
connect _WIRE_50.bits.source, UInt<5>(0h0)
connect _WIRE_50.bits.size, UInt<3>(0h0)
connect _WIRE_50.bits.param, UInt<2>(0h0)
connect _WIRE_50.bits.opcode, UInt<3>(0h0)
connect _WIRE_50.valid, UInt<1>(0h0)
connect _WIRE_50.ready, UInt<1>(0h0)
wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_51.bits, _WIRE_50.bits
connect _WIRE_51.valid, _WIRE_50.valid
connect _WIRE_51.ready, _WIRE_50.ready
node _T_407 = eq(_WIRE_51.valid, UInt<1>(0h0))
node _T_408 = asUInt(reset)
node _T_409 = eq(_T_408, UInt<1>(0h0))
when _T_409 :
node _T_410 = eq(_T_407, UInt<1>(0h0))
when _T_410 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:124 assert (!out.b.valid)\n") : printf_37
assert(clock, _T_407, UInt<1>(0h1), "") : assert_37
inst pool_6 of IDPool_6
connect pool_6.clock, clock
connect pool_6.reset, reset
node _pool_io_free_valid_T_6 = and(nodeIn_6.e.ready, nodeIn_6.e.valid)
connect pool_6.io.free.valid, _pool_io_free_valid_T_6
connect pool_6.io.free.bits, nodeIn_6.e.bits.sink
wire in_d_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _d_first_T_6 = and(in_d_6.ready, in_d_6.valid)
node _d_first_beats1_decode_T_18 = dshl(UInt<6>(0h3f), in_d_6.bits.size)
node _d_first_beats1_decode_T_19 = bits(_d_first_beats1_decode_T_18, 5, 0)
node _d_first_beats1_decode_T_20 = not(_d_first_beats1_decode_T_19)
node d_first_beats1_decode_6 = shr(_d_first_beats1_decode_T_20, 3)
node d_first_beats1_opdata_6 = bits(in_d_6.bits.opcode, 0, 0)
node d_first_beats1_6 = mux(d_first_beats1_opdata_6, d_first_beats1_decode_6, UInt<1>(0h0))
regreset d_first_counter_6 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_6 = sub(d_first_counter_6, UInt<1>(0h1))
node d_first_counter1_6 = tail(_d_first_counter1_T_6, 1)
node d_first_6 = eq(d_first_counter_6, UInt<1>(0h0))
node _d_first_last_T_12 = eq(d_first_counter_6, UInt<1>(0h1))
node _d_first_last_T_13 = eq(d_first_beats1_6, UInt<1>(0h0))
node d_first_last_6 = or(_d_first_last_T_12, _d_first_last_T_13)
node d_first_done_6 = and(d_first_last_6, _d_first_T_6)
node _d_first_count_T_6 = not(d_first_counter1_6)
node d_first_count_6 = and(d_first_beats1_6, _d_first_count_T_6)
when _d_first_T_6 :
node _d_first_counter_T_6 = mux(d_first_6, d_first_beats1_6, d_first_counter1_6)
connect d_first_counter_6, _d_first_counter_T_6
node _d_grant_T_12 = eq(in_d_6.bits.opcode, UInt<3>(0h5))
node _d_grant_T_13 = eq(in_d_6.bits.opcode, UInt<3>(0h4))
node d_grant_6 = or(_d_grant_T_12, _d_grant_T_13)
node _pool_io_alloc_ready_T_18 = and(nodeIn_6.d.ready, nodeIn_6.d.valid)
node _pool_io_alloc_ready_T_19 = and(_pool_io_alloc_ready_T_18, d_first_6)
node _pool_io_alloc_ready_T_20 = and(_pool_io_alloc_ready_T_19, d_grant_6)
connect pool_6.io.alloc.ready, _pool_io_alloc_ready_T_20
node _nodeIn_d_valid_T_30 = eq(d_first_6, UInt<1>(0h0))
node _nodeIn_d_valid_T_31 = or(pool_6.io.alloc.valid, _nodeIn_d_valid_T_30)
node _nodeIn_d_valid_T_32 = eq(d_grant_6, UInt<1>(0h0))
node _nodeIn_d_valid_T_33 = or(_nodeIn_d_valid_T_31, _nodeIn_d_valid_T_32)
node _nodeIn_d_valid_T_34 = and(in_d_6.valid, _nodeIn_d_valid_T_33)
connect nodeIn_6.d.valid, _nodeIn_d_valid_T_34
node _in_d_ready_T_30 = eq(d_first_6, UInt<1>(0h0))
node _in_d_ready_T_31 = or(pool_6.io.alloc.valid, _in_d_ready_T_30)
node _in_d_ready_T_32 = eq(d_grant_6, UInt<1>(0h0))
node _in_d_ready_T_33 = or(_in_d_ready_T_31, _in_d_ready_T_32)
node _in_d_ready_T_34 = and(nodeIn_6.d.ready, _in_d_ready_T_33)
connect in_d_6.ready, _in_d_ready_T_34
connect nodeIn_6.d.bits.corrupt, in_d_6.bits.corrupt
connect nodeIn_6.d.bits.data, in_d_6.bits.data
connect nodeIn_6.d.bits.denied, in_d_6.bits.denied
connect nodeIn_6.d.bits.sink, in_d_6.bits.sink
connect nodeIn_6.d.bits.source, in_d_6.bits.source
connect nodeIn_6.d.bits.size, in_d_6.bits.size
connect nodeIn_6.d.bits.param, in_d_6.bits.param
connect nodeIn_6.d.bits.opcode, in_d_6.bits.opcode
reg nodeIn_d_bits_sink_r_6 : UInt<3>, clock
when d_first_6 :
connect nodeIn_d_bits_sink_r_6, pool_6.io.alloc.bits
node _nodeIn_d_bits_sink_T_6 = mux(d_first_6, pool_6.io.alloc.bits, nodeIn_d_bits_sink_r_6)
connect nodeIn_6.d.bits.sink, _nodeIn_d_bits_sink_T_6
wire d_d_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect d_d_6, x1_nodeOut_5.d
node _d_d_bits_source_T_6 = shr(x1_nodeOut_5.d.bits.source, 1)
connect d_d_6.bits.source, _d_d_bits_source_T_6
reg wSourceVec_6 : UInt<1>[10], clock
node _aWOk_T_30 = xor(nodeIn_6.a.bits.address, UInt<1>(0h0))
node _aWOk_T_31 = cvt(_aWOk_T_30)
node _aWOk_T_32 = and(_aWOk_T_31, asSInt(UInt<1>(0h0)))
node _aWOk_T_33 = asSInt(_aWOk_T_32)
node _aWOk_T_34 = eq(_aWOk_T_33, asSInt(UInt<1>(0h0)))
node _bypass_T_12 = and(UInt<1>(0h0), nodeIn_6.a.valid)
node _bypass_T_13 = eq(nodeIn_6.a.bits.source, d_d_6.bits.source)
node bypass_6 = and(_bypass_T_12, _bypass_T_13)
node _dWHeld_T_6 = mux(bypass_6, UInt<1>(0h1), wSourceVec_6[d_d_6.bits.source])
reg dWHeld_r_6 : UInt<1>, clock
when d_first_6 :
connect dWHeld_r_6, _dWHeld_T_6
node dWHeld_6 = mux(d_first_6, _dWHeld_T_6, dWHeld_r_6)
node _T_411 = and(nodeIn_6.a.ready, nodeIn_6.a.valid)
when _T_411 :
connect wSourceVec_6[nodeIn_6.a.bits.source], UInt<1>(0h1)
node _T_412 = eq(x1_nodeOut_5.d.bits.opcode, UInt<1>(0h1))
node _T_413 = bits(x1_nodeOut_5.d.bits.source, 0, 0)
node _T_414 = and(_T_412, _T_413)
when _T_414 :
connect d_d_6.bits.opcode, UInt<3>(0h5)
node _d_d_bits_param_T_6 = mux(dWHeld_6, UInt<2>(0h0), UInt<2>(0h1))
connect d_d_6.bits.param, _d_d_bits_param_T_6
node _T_415 = eq(x1_nodeOut_5.d.bits.opcode, UInt<1>(0h0))
node _T_416 = bits(x1_nodeOut_5.d.bits.source, 0, 0)
node _T_417 = eq(_T_416, UInt<1>(0h0))
node _T_418 = and(_T_415, _T_417)
when _T_418 :
connect d_d_6.bits.opcode, UInt<3>(0h6)
node _decode_T_54 = dshl(UInt<6>(0h3f), c_a_6.bits.size)
node _decode_T_55 = bits(_decode_T_54, 5, 0)
node _decode_T_56 = not(_decode_T_55)
node decode_18 = shr(_decode_T_56, 3)
node _opdata_T_12 = bits(c_a_6.bits.opcode, 2, 2)
node opdata_18 = eq(_opdata_T_12, UInt<1>(0h0))
node _T_419 = mux(opdata_18, decode_18, UInt<1>(0h0))
node _decode_T_57 = dshl(UInt<6>(0h3f), a_a_6.bits.size)
node _decode_T_58 = bits(_decode_T_57, 5, 0)
node _decode_T_59 = not(_decode_T_58)
node decode_19 = shr(_decode_T_59, 3)
node _opdata_T_13 = bits(a_a_6.bits.opcode, 2, 2)
node opdata_19 = eq(_opdata_T_13, UInt<1>(0h0))
node _T_420 = mux(opdata_19, decode_19, UInt<1>(0h0))
regreset beatsLeft_12 : UInt, clock, reset, UInt<1>(0h0)
node idle_12 = eq(beatsLeft_12, UInt<1>(0h0))
node latch_12 = and(idle_12, x1_nodeOut_5.a.ready)
node _readys_T_144 = cat(a_a_6.valid, c_a_6.valid)
node _readys_T_145 = shl(_readys_T_144, 1)
node _readys_T_146 = bits(_readys_T_145, 1, 0)
node _readys_T_147 = or(_readys_T_144, _readys_T_146)
node _readys_T_148 = bits(_readys_T_147, 1, 0)
node _readys_T_149 = shl(_readys_T_148, 1)
node _readys_T_150 = bits(_readys_T_149, 1, 0)
node _readys_T_151 = not(_readys_T_150)
node _readys_T_152 = bits(_readys_T_151, 0, 0)
node _readys_T_153 = bits(_readys_T_151, 1, 1)
wire readys_12 : UInt<1>[2]
connect readys_12[0], _readys_T_152
connect readys_12[1], _readys_T_153
node _winner_T_30 = and(readys_12[0], c_a_6.valid)
node _winner_T_31 = and(readys_12[1], a_a_6.valid)
wire winner_12 : UInt<1>[2]
connect winner_12[0], _winner_T_30
connect winner_12[1], _winner_T_31
node prefixOR_1_12 = or(UInt<1>(0h0), winner_12[0])
node _prefixOR_T_12 = or(prefixOR_1_12, winner_12[1])
node _T_421 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_422 = eq(winner_12[0], UInt<1>(0h0))
node _T_423 = or(_T_421, _T_422)
node _T_424 = eq(prefixOR_1_12, UInt<1>(0h0))
node _T_425 = eq(winner_12[1], UInt<1>(0h0))
node _T_426 = or(_T_424, _T_425)
node _T_427 = and(_T_423, _T_426)
node _T_428 = asUInt(reset)
node _T_429 = eq(_T_428, UInt<1>(0h0))
when _T_429 :
node _T_430 = eq(_T_427, UInt<1>(0h0))
when _T_430 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_38
assert(clock, _T_427, UInt<1>(0h1), "") : assert_38
node _T_431 = or(c_a_6.valid, a_a_6.valid)
node _T_432 = eq(_T_431, UInt<1>(0h0))
node _T_433 = or(winner_12[0], winner_12[1])
node _T_434 = or(_T_432, _T_433)
node _T_435 = asUInt(reset)
node _T_436 = eq(_T_435, UInt<1>(0h0))
when _T_436 :
node _T_437 = eq(_T_434, UInt<1>(0h0))
when _T_437 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_39
assert(clock, _T_434, UInt<1>(0h1), "") : assert_39
node maskedBeats_0_12 = mux(winner_12[0], _T_419, UInt<1>(0h0))
node maskedBeats_1_12 = mux(winner_12[1], _T_420, UInt<1>(0h0))
node initBeats_12 = or(maskedBeats_0_12, maskedBeats_1_12)
node _beatsLeft_T_48 = and(x1_nodeOut_5.a.ready, x1_nodeOut_5.a.valid)
node _beatsLeft_T_49 = sub(beatsLeft_12, _beatsLeft_T_48)
node _beatsLeft_T_50 = tail(_beatsLeft_T_49, 1)
node _beatsLeft_T_51 = mux(latch_12, initBeats_12, _beatsLeft_T_50)
connect beatsLeft_12, _beatsLeft_T_51
wire _state_WIRE_12 : UInt<1>[2]
connect _state_WIRE_12[0], UInt<1>(0h0)
connect _state_WIRE_12[1], UInt<1>(0h0)
regreset state_12 : UInt<1>[2], clock, reset, _state_WIRE_12
node muxState_12 = mux(idle_12, winner_12, state_12)
connect state_12, muxState_12
node allowed_12 = mux(idle_12, readys_12, state_12)
node _c_a_ready_T_6 = and(x1_nodeOut_5.a.ready, allowed_12[0])
connect c_a_6.ready, _c_a_ready_T_6
node _a_a_ready_T_6 = and(x1_nodeOut_5.a.ready, allowed_12[1])
connect a_a_6.ready, _a_a_ready_T_6
node _nodeOut_a_valid_T_30 = or(c_a_6.valid, a_a_6.valid)
node _nodeOut_a_valid_T_31 = mux(state_12[0], c_a_6.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_32 = mux(state_12[1], a_a_6.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_33 = or(_nodeOut_a_valid_T_31, _nodeOut_a_valid_T_32)
wire _nodeOut_a_valid_WIRE_6 : UInt<1>
connect _nodeOut_a_valid_WIRE_6, _nodeOut_a_valid_T_33
node _nodeOut_a_valid_T_34 = mux(idle_12, _nodeOut_a_valid_T_30, _nodeOut_a_valid_WIRE_6)
connect x1_nodeOut_5.a.valid, _nodeOut_a_valid_T_34
wire _nodeOut_a_bits_WIRE_66 : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _nodeOut_a_bits_T_144 = mux(muxState_12[0], c_a_6.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_145 = mux(muxState_12[1], a_a_6.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_146 = or(_nodeOut_a_bits_T_144, _nodeOut_a_bits_T_145)
wire _nodeOut_a_bits_WIRE_67 : UInt<1>
connect _nodeOut_a_bits_WIRE_67, _nodeOut_a_bits_T_146
connect _nodeOut_a_bits_WIRE_66.corrupt, _nodeOut_a_bits_WIRE_67
node _nodeOut_a_bits_T_147 = mux(muxState_12[0], c_a_6.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_148 = mux(muxState_12[1], a_a_6.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_149 = or(_nodeOut_a_bits_T_147, _nodeOut_a_bits_T_148)
wire _nodeOut_a_bits_WIRE_68 : UInt<64>
connect _nodeOut_a_bits_WIRE_68, _nodeOut_a_bits_T_149
connect _nodeOut_a_bits_WIRE_66.data, _nodeOut_a_bits_WIRE_68
node _nodeOut_a_bits_T_150 = mux(muxState_12[0], c_a_6.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_151 = mux(muxState_12[1], a_a_6.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_152 = or(_nodeOut_a_bits_T_150, _nodeOut_a_bits_T_151)
wire _nodeOut_a_bits_WIRE_69 : UInt<8>
connect _nodeOut_a_bits_WIRE_69, _nodeOut_a_bits_T_152
connect _nodeOut_a_bits_WIRE_66.mask, _nodeOut_a_bits_WIRE_69
wire _nodeOut_a_bits_WIRE_70 : { }
connect _nodeOut_a_bits_WIRE_66.echo, _nodeOut_a_bits_WIRE_70
wire _nodeOut_a_bits_WIRE_71 : { }
connect _nodeOut_a_bits_WIRE_66.user, _nodeOut_a_bits_WIRE_71
node _nodeOut_a_bits_T_153 = mux(muxState_12[0], c_a_6.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_154 = mux(muxState_12[1], a_a_6.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_155 = or(_nodeOut_a_bits_T_153, _nodeOut_a_bits_T_154)
wire _nodeOut_a_bits_WIRE_72 : UInt<32>
connect _nodeOut_a_bits_WIRE_72, _nodeOut_a_bits_T_155
connect _nodeOut_a_bits_WIRE_66.address, _nodeOut_a_bits_WIRE_72
node _nodeOut_a_bits_T_156 = mux(muxState_12[0], c_a_6.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_157 = mux(muxState_12[1], a_a_6.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_158 = or(_nodeOut_a_bits_T_156, _nodeOut_a_bits_T_157)
wire _nodeOut_a_bits_WIRE_73 : UInt<5>
connect _nodeOut_a_bits_WIRE_73, _nodeOut_a_bits_T_158
connect _nodeOut_a_bits_WIRE_66.source, _nodeOut_a_bits_WIRE_73
node _nodeOut_a_bits_T_159 = mux(muxState_12[0], c_a_6.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_160 = mux(muxState_12[1], a_a_6.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_161 = or(_nodeOut_a_bits_T_159, _nodeOut_a_bits_T_160)
wire _nodeOut_a_bits_WIRE_74 : UInt<3>
connect _nodeOut_a_bits_WIRE_74, _nodeOut_a_bits_T_161
connect _nodeOut_a_bits_WIRE_66.size, _nodeOut_a_bits_WIRE_74
node _nodeOut_a_bits_T_162 = mux(muxState_12[0], c_a_6.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_163 = mux(muxState_12[1], a_a_6.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_164 = or(_nodeOut_a_bits_T_162, _nodeOut_a_bits_T_163)
wire _nodeOut_a_bits_WIRE_75 : UInt<3>
connect _nodeOut_a_bits_WIRE_75, _nodeOut_a_bits_T_164
connect _nodeOut_a_bits_WIRE_66.param, _nodeOut_a_bits_WIRE_75
node _nodeOut_a_bits_T_165 = mux(muxState_12[0], c_a_6.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_166 = mux(muxState_12[1], a_a_6.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_167 = or(_nodeOut_a_bits_T_165, _nodeOut_a_bits_T_166)
wire _nodeOut_a_bits_WIRE_76 : UInt<3>
connect _nodeOut_a_bits_WIRE_76, _nodeOut_a_bits_T_167
connect _nodeOut_a_bits_WIRE_66.opcode, _nodeOut_a_bits_WIRE_76
connect x1_nodeOut_5.a.bits.corrupt, _nodeOut_a_bits_WIRE_66.corrupt
connect x1_nodeOut_5.a.bits.data, _nodeOut_a_bits_WIRE_66.data
connect x1_nodeOut_5.a.bits.mask, _nodeOut_a_bits_WIRE_66.mask
connect x1_nodeOut_5.a.bits.address, _nodeOut_a_bits_WIRE_66.address
connect x1_nodeOut_5.a.bits.source, _nodeOut_a_bits_WIRE_66.source
connect x1_nodeOut_5.a.bits.size, _nodeOut_a_bits_WIRE_66.size
connect x1_nodeOut_5.a.bits.param, _nodeOut_a_bits_WIRE_66.param
connect x1_nodeOut_5.a.bits.opcode, _nodeOut_a_bits_WIRE_66.opcode
node _decode_T_60 = dshl(UInt<6>(0h3f), d_d_6.bits.size)
node _decode_T_61 = bits(_decode_T_60, 5, 0)
node _decode_T_62 = not(_decode_T_61)
node decode_20 = shr(_decode_T_62, 3)
node opdata_20 = bits(d_d_6.bits.opcode, 0, 0)
node _T_438 = mux(opdata_20, decode_20, UInt<1>(0h0))
inst q_12 of Queue2_TLBundleD_a32d64s4k3z3c_20
connect q_12.clock, clock
connect q_12.reset, reset
connect q_12.io.enq.valid, c_d_6.valid
connect q_12.io.enq.bits.corrupt, c_d_6.bits.corrupt
connect q_12.io.enq.bits.data, c_d_6.bits.data
connect q_12.io.enq.bits.denied, c_d_6.bits.denied
connect q_12.io.enq.bits.sink, c_d_6.bits.sink
connect q_12.io.enq.bits.source, c_d_6.bits.source
connect q_12.io.enq.bits.size, c_d_6.bits.size
connect q_12.io.enq.bits.param, c_d_6.bits.param
connect q_12.io.enq.bits.opcode, c_d_6.bits.opcode
connect c_d_6.ready, q_12.io.enq.ready
inst q_13 of Queue2_TLBundleD_a32d64s4k3z3c_21
connect q_13.clock, clock
connect q_13.reset, reset
connect q_13.io.enq.valid, a_d_6.valid
connect q_13.io.enq.bits.corrupt, a_d_6.bits.corrupt
connect q_13.io.enq.bits.data, a_d_6.bits.data
connect q_13.io.enq.bits.denied, a_d_6.bits.denied
connect q_13.io.enq.bits.sink, a_d_6.bits.sink
connect q_13.io.enq.bits.source, a_d_6.bits.source
connect q_13.io.enq.bits.size, a_d_6.bits.size
connect q_13.io.enq.bits.param, a_d_6.bits.param
connect q_13.io.enq.bits.opcode, a_d_6.bits.opcode
connect a_d_6.ready, q_13.io.enq.ready
regreset beatsLeft_13 : UInt, clock, reset, UInt<1>(0h0)
node idle_13 = eq(beatsLeft_13, UInt<1>(0h0))
node latch_13 = and(idle_13, in_d_6.ready)
node readys_hi_6 = cat(q_13.io.deq.valid, q_12.io.deq.valid)
node _readys_T_154 = cat(readys_hi_6, d_d_6.valid)
node _readys_T_155 = shl(_readys_T_154, 1)
node _readys_T_156 = bits(_readys_T_155, 2, 0)
node _readys_T_157 = or(_readys_T_154, _readys_T_156)
node _readys_T_158 = shl(_readys_T_157, 2)
node _readys_T_159 = bits(_readys_T_158, 2, 0)
node _readys_T_160 = or(_readys_T_157, _readys_T_159)
node _readys_T_161 = bits(_readys_T_160, 2, 0)
node _readys_T_162 = shl(_readys_T_161, 1)
node _readys_T_163 = bits(_readys_T_162, 2, 0)
node _readys_T_164 = not(_readys_T_163)
node _readys_T_165 = bits(_readys_T_164, 0, 0)
node _readys_T_166 = bits(_readys_T_164, 1, 1)
node _readys_T_167 = bits(_readys_T_164, 2, 2)
wire readys_13 : UInt<1>[3]
connect readys_13[0], _readys_T_165
connect readys_13[1], _readys_T_166
connect readys_13[2], _readys_T_167
node _winner_T_32 = and(readys_13[0], d_d_6.valid)
node _winner_T_33 = and(readys_13[1], q_12.io.deq.valid)
node _winner_T_34 = and(readys_13[2], q_13.io.deq.valid)
wire winner_13 : UInt<1>[3]
connect winner_13[0], _winner_T_32
connect winner_13[1], _winner_T_33
connect winner_13[2], _winner_T_34
node prefixOR_1_13 = or(UInt<1>(0h0), winner_13[0])
node prefixOR_2_6 = or(prefixOR_1_13, winner_13[1])
node _prefixOR_T_13 = or(prefixOR_2_6, winner_13[2])
node _T_439 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_440 = eq(winner_13[0], UInt<1>(0h0))
node _T_441 = or(_T_439, _T_440)
node _T_442 = eq(prefixOR_1_13, UInt<1>(0h0))
node _T_443 = eq(winner_13[1], UInt<1>(0h0))
node _T_444 = or(_T_442, _T_443)
node _T_445 = eq(prefixOR_2_6, UInt<1>(0h0))
node _T_446 = eq(winner_13[2], UInt<1>(0h0))
node _T_447 = or(_T_445, _T_446)
node _T_448 = and(_T_441, _T_444)
node _T_449 = and(_T_448, _T_447)
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_T_449, UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_40
assert(clock, _T_449, UInt<1>(0h1), "") : assert_40
node _T_453 = or(d_d_6.valid, q_12.io.deq.valid)
node _T_454 = or(_T_453, q_13.io.deq.valid)
node _T_455 = eq(_T_454, UInt<1>(0h0))
node _T_456 = or(winner_13[0], winner_13[1])
node _T_457 = or(_T_456, winner_13[2])
node _T_458 = or(_T_455, _T_457)
node _T_459 = asUInt(reset)
node _T_460 = eq(_T_459, UInt<1>(0h0))
when _T_460 :
node _T_461 = eq(_T_458, UInt<1>(0h0))
when _T_461 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_41
assert(clock, _T_458, UInt<1>(0h1), "") : assert_41
node maskedBeats_0_13 = mux(winner_13[0], _T_438, UInt<1>(0h0))
node maskedBeats_1_13 = mux(winner_13[1], UInt<1>(0h0), UInt<1>(0h0))
node maskedBeats_2_6 = mux(winner_13[2], UInt<1>(0h0), UInt<1>(0h0))
node _initBeats_T_6 = or(maskedBeats_0_13, maskedBeats_1_13)
node initBeats_13 = or(_initBeats_T_6, maskedBeats_2_6)
node _beatsLeft_T_52 = and(in_d_6.ready, in_d_6.valid)
node _beatsLeft_T_53 = sub(beatsLeft_13, _beatsLeft_T_52)
node _beatsLeft_T_54 = tail(_beatsLeft_T_53, 1)
node _beatsLeft_T_55 = mux(latch_13, initBeats_13, _beatsLeft_T_54)
connect beatsLeft_13, _beatsLeft_T_55
wire _state_WIRE_13 : UInt<1>[3]
connect _state_WIRE_13[0], UInt<1>(0h0)
connect _state_WIRE_13[1], UInt<1>(0h0)
connect _state_WIRE_13[2], UInt<1>(0h0)
regreset state_13 : UInt<1>[3], clock, reset, _state_WIRE_13
node muxState_13 = mux(idle_13, winner_13, state_13)
connect state_13, muxState_13
node allowed_13 = mux(idle_13, readys_13, state_13)
node _d_d_ready_T_6 = and(in_d_6.ready, allowed_13[0])
connect d_d_6.ready, _d_d_ready_T_6
node _q_io_deq_ready_T_12 = and(in_d_6.ready, allowed_13[1])
connect q_12.io.deq.ready, _q_io_deq_ready_T_12
node _q_io_deq_ready_T_13 = and(in_d_6.ready, allowed_13[2])
connect q_13.io.deq.ready, _q_io_deq_ready_T_13
node _in_d_valid_T_48 = or(d_d_6.valid, q_12.io.deq.valid)
node _in_d_valid_T_49 = or(_in_d_valid_T_48, q_13.io.deq.valid)
node _in_d_valid_T_50 = mux(state_13[0], d_d_6.valid, UInt<1>(0h0))
node _in_d_valid_T_51 = mux(state_13[1], q_12.io.deq.valid, UInt<1>(0h0))
node _in_d_valid_T_52 = mux(state_13[2], q_13.io.deq.valid, UInt<1>(0h0))
node _in_d_valid_T_53 = or(_in_d_valid_T_50, _in_d_valid_T_51)
node _in_d_valid_T_54 = or(_in_d_valid_T_53, _in_d_valid_T_52)
wire _in_d_valid_WIRE_6 : UInt<1>
connect _in_d_valid_WIRE_6, _in_d_valid_T_54
node _in_d_valid_T_55 = mux(idle_13, _in_d_valid_T_49, _in_d_valid_WIRE_6)
connect in_d_6.valid, _in_d_valid_T_55
wire _in_d_bits_WIRE_66 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_d_bits_T_240 = mux(muxState_13[0], d_d_6.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_241 = mux(muxState_13[1], q_12.io.deq.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_242 = mux(muxState_13[2], q_13.io.deq.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_243 = or(_in_d_bits_T_240, _in_d_bits_T_241)
node _in_d_bits_T_244 = or(_in_d_bits_T_243, _in_d_bits_T_242)
wire _in_d_bits_WIRE_67 : UInt<1>
connect _in_d_bits_WIRE_67, _in_d_bits_T_244
connect _in_d_bits_WIRE_66.corrupt, _in_d_bits_WIRE_67
node _in_d_bits_T_245 = mux(muxState_13[0], d_d_6.bits.data, UInt<1>(0h0))
node _in_d_bits_T_246 = mux(muxState_13[1], q_12.io.deq.bits.data, UInt<1>(0h0))
node _in_d_bits_T_247 = mux(muxState_13[2], q_13.io.deq.bits.data, UInt<1>(0h0))
node _in_d_bits_T_248 = or(_in_d_bits_T_245, _in_d_bits_T_246)
node _in_d_bits_T_249 = or(_in_d_bits_T_248, _in_d_bits_T_247)
wire _in_d_bits_WIRE_68 : UInt<64>
connect _in_d_bits_WIRE_68, _in_d_bits_T_249
connect _in_d_bits_WIRE_66.data, _in_d_bits_WIRE_68
wire _in_d_bits_WIRE_69 : { }
connect _in_d_bits_WIRE_66.echo, _in_d_bits_WIRE_69
wire _in_d_bits_WIRE_70 : { }
connect _in_d_bits_WIRE_66.user, _in_d_bits_WIRE_70
node _in_d_bits_T_250 = mux(muxState_13[0], d_d_6.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_251 = mux(muxState_13[1], q_12.io.deq.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_252 = mux(muxState_13[2], q_13.io.deq.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_253 = or(_in_d_bits_T_250, _in_d_bits_T_251)
node _in_d_bits_T_254 = or(_in_d_bits_T_253, _in_d_bits_T_252)
wire _in_d_bits_WIRE_71 : UInt<1>
connect _in_d_bits_WIRE_71, _in_d_bits_T_254
connect _in_d_bits_WIRE_66.denied, _in_d_bits_WIRE_71
node _in_d_bits_T_255 = mux(muxState_13[0], d_d_6.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_256 = mux(muxState_13[1], q_12.io.deq.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_257 = mux(muxState_13[2], q_13.io.deq.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_258 = or(_in_d_bits_T_255, _in_d_bits_T_256)
node _in_d_bits_T_259 = or(_in_d_bits_T_258, _in_d_bits_T_257)
wire _in_d_bits_WIRE_72 : UInt<3>
connect _in_d_bits_WIRE_72, _in_d_bits_T_259
connect _in_d_bits_WIRE_66.sink, _in_d_bits_WIRE_72
node _in_d_bits_T_260 = mux(muxState_13[0], d_d_6.bits.source, UInt<1>(0h0))
node _in_d_bits_T_261 = mux(muxState_13[1], q_12.io.deq.bits.source, UInt<1>(0h0))
node _in_d_bits_T_262 = mux(muxState_13[2], q_13.io.deq.bits.source, UInt<1>(0h0))
node _in_d_bits_T_263 = or(_in_d_bits_T_260, _in_d_bits_T_261)
node _in_d_bits_T_264 = or(_in_d_bits_T_263, _in_d_bits_T_262)
wire _in_d_bits_WIRE_73 : UInt<4>
connect _in_d_bits_WIRE_73, _in_d_bits_T_264
connect _in_d_bits_WIRE_66.source, _in_d_bits_WIRE_73
node _in_d_bits_T_265 = mux(muxState_13[0], d_d_6.bits.size, UInt<1>(0h0))
node _in_d_bits_T_266 = mux(muxState_13[1], q_12.io.deq.bits.size, UInt<1>(0h0))
node _in_d_bits_T_267 = mux(muxState_13[2], q_13.io.deq.bits.size, UInt<1>(0h0))
node _in_d_bits_T_268 = or(_in_d_bits_T_265, _in_d_bits_T_266)
node _in_d_bits_T_269 = or(_in_d_bits_T_268, _in_d_bits_T_267)
wire _in_d_bits_WIRE_74 : UInt<3>
connect _in_d_bits_WIRE_74, _in_d_bits_T_269
connect _in_d_bits_WIRE_66.size, _in_d_bits_WIRE_74
node _in_d_bits_T_270 = mux(muxState_13[0], d_d_6.bits.param, UInt<1>(0h0))
node _in_d_bits_T_271 = mux(muxState_13[1], q_12.io.deq.bits.param, UInt<1>(0h0))
node _in_d_bits_T_272 = mux(muxState_13[2], q_13.io.deq.bits.param, UInt<1>(0h0))
node _in_d_bits_T_273 = or(_in_d_bits_T_270, _in_d_bits_T_271)
node _in_d_bits_T_274 = or(_in_d_bits_T_273, _in_d_bits_T_272)
wire _in_d_bits_WIRE_75 : UInt<2>
connect _in_d_bits_WIRE_75, _in_d_bits_T_274
connect _in_d_bits_WIRE_66.param, _in_d_bits_WIRE_75
node _in_d_bits_T_275 = mux(muxState_13[0], d_d_6.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_276 = mux(muxState_13[1], q_12.io.deq.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_277 = mux(muxState_13[2], q_13.io.deq.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_278 = or(_in_d_bits_T_275, _in_d_bits_T_276)
node _in_d_bits_T_279 = or(_in_d_bits_T_278, _in_d_bits_T_277)
wire _in_d_bits_WIRE_76 : UInt<3>
connect _in_d_bits_WIRE_76, _in_d_bits_T_279
connect _in_d_bits_WIRE_66.opcode, _in_d_bits_WIRE_76
connect in_d_6.bits.corrupt, _in_d_bits_WIRE_66.corrupt
connect in_d_6.bits.data, _in_d_bits_WIRE_66.data
connect in_d_6.bits.denied, _in_d_bits_WIRE_66.denied
connect in_d_6.bits.sink, _in_d_bits_WIRE_66.sink
connect in_d_6.bits.source, _in_d_bits_WIRE_66.source
connect in_d_6.bits.size, _in_d_bits_WIRE_66.size
connect in_d_6.bits.param, _in_d_bits_WIRE_66.param
connect in_d_6.bits.opcode, _in_d_bits_WIRE_66.opcode
connect nodeIn_6.b.valid, UInt<1>(0h0)
wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_52.bits.corrupt, UInt<1>(0h0)
connect _WIRE_52.bits.data, UInt<64>(0h0)
connect _WIRE_52.bits.address, UInt<32>(0h0)
connect _WIRE_52.bits.source, UInt<5>(0h0)
connect _WIRE_52.bits.size, UInt<3>(0h0)
connect _WIRE_52.bits.param, UInt<3>(0h0)
connect _WIRE_52.bits.opcode, UInt<3>(0h0)
connect _WIRE_52.valid, UInt<1>(0h0)
connect _WIRE_52.ready, UInt<1>(0h0)
wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_53.bits, _WIRE_52.bits
connect _WIRE_53.valid, _WIRE_52.valid
connect _WIRE_53.ready, _WIRE_52.ready
connect _WIRE_53.valid, UInt<1>(0h0)
wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_54.bits.sink, UInt<1>(0h0)
connect _WIRE_54.valid, UInt<1>(0h0)
connect _WIRE_54.ready, UInt<1>(0h0)
wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_55.bits, _WIRE_54.bits
connect _WIRE_55.valid, _WIRE_54.valid
connect _WIRE_55.ready, _WIRE_54.ready
connect _WIRE_55.valid, UInt<1>(0h0)
wire a_a_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
wire a_d_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _isPut_T_14 = eq(nodeIn_7.a.bits.opcode, UInt<1>(0h0))
node _isPut_T_15 = eq(nodeIn_7.a.bits.opcode, UInt<1>(0h1))
node isPut_7 = or(_isPut_T_14, _isPut_T_15)
node _toD_T_28 = eq(nodeIn_7.a.bits.opcode, UInt<3>(0h6))
node _toD_T_29 = eq(nodeIn_7.a.bits.param, UInt<2>(0h2))
node _toD_T_30 = and(_toD_T_28, _toD_T_29)
node _toD_T_31 = eq(nodeIn_7.a.bits.opcode, UInt<3>(0h7))
node toD_7 = or(_toD_T_30, _toD_T_31)
node _nodeIn_a_ready_T_7 = mux(toD_7, a_d_7.ready, a_a_7.ready)
connect nodeIn_7.a.ready, _nodeIn_a_ready_T_7
node _a_a_valid_T_14 = eq(toD_7, UInt<1>(0h0))
node _a_a_valid_T_15 = and(nodeIn_7.a.valid, _a_a_valid_T_14)
connect a_a_7.valid, _a_a_valid_T_15
connect a_a_7.bits, nodeIn_7.a.bits
node _a_a_bits_source_T_35 = shl(nodeIn_7.a.bits.source, 1)
node _a_a_bits_source_T_36 = mux(isPut_7, UInt<1>(0h1), UInt<1>(0h0))
node _a_a_bits_source_T_37 = or(_a_a_bits_source_T_35, _a_a_bits_source_T_36)
connect a_a_7.bits.source, _a_a_bits_source_T_37
node _T_462 = eq(nodeIn_7.a.bits.opcode, UInt<3>(0h6))
node _T_463 = eq(nodeIn_7.a.bits.opcode, UInt<3>(0h7))
node _T_464 = or(_T_462, _T_463)
when _T_464 :
connect a_a_7.bits.opcode, UInt<3>(0h4)
connect a_a_7.bits.param, UInt<1>(0h0)
node _a_a_bits_source_T_38 = shl(nodeIn_7.a.bits.source, 1)
node _a_a_bits_source_T_39 = or(_a_a_bits_source_T_38, UInt<1>(0h1))
connect a_a_7.bits.source, _a_a_bits_source_T_39
node _a_d_valid_T_7 = and(nodeIn_7.a.valid, toD_7)
connect a_d_7.valid, _a_d_valid_T_7
wire a_d_bits_d_7 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect a_d_bits_d_7.opcode, UInt<3>(0h4)
connect a_d_bits_d_7.param, UInt<2>(0h0)
connect a_d_bits_d_7.size, nodeIn_7.a.bits.size
connect a_d_bits_d_7.source, nodeIn_7.a.bits.source
connect a_d_bits_d_7.sink, UInt<1>(0h0)
connect a_d_bits_d_7.denied, UInt<1>(0h0)
invalidate a_d_bits_d_7.data
connect a_d_bits_d_7.corrupt, UInt<1>(0h0)
connect a_d_7.bits.corrupt, a_d_bits_d_7.corrupt
connect a_d_7.bits.data, a_d_bits_d_7.data
connect a_d_7.bits.denied, a_d_bits_d_7.denied
connect a_d_7.bits.sink, a_d_bits_d_7.sink
connect a_d_7.bits.source, a_d_bits_d_7.source
connect a_d_7.bits.size, a_d_bits_d_7.size
connect a_d_7.bits.param, a_d_bits_d_7.param
connect a_d_7.bits.opcode, a_d_bits_d_7.opcode
wire c_a_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
node _c_a_valid_T_14 = eq(nodeIn_7.c.bits.opcode, UInt<3>(0h7))
node _c_a_valid_T_15 = and(nodeIn_7.c.valid, _c_a_valid_T_14)
connect c_a_7.valid, _c_a_valid_T_15
node _c_a_bits_T_7 = shl(nodeIn_7.c.bits.source, 1)
node _c_a_bits_legal_T_70 = leq(UInt<1>(0h0), nodeIn_7.c.bits.size)
node _c_a_bits_legal_T_71 = leq(nodeIn_7.c.bits.size, UInt<3>(0h6))
node _c_a_bits_legal_T_72 = and(_c_a_bits_legal_T_70, _c_a_bits_legal_T_71)
node _c_a_bits_legal_T_73 = or(UInt<1>(0h0), _c_a_bits_legal_T_72)
node _c_a_bits_legal_T_74 = xor(nodeIn_7.c.bits.address, UInt<1>(0h0))
node _c_a_bits_legal_T_75 = cvt(_c_a_bits_legal_T_74)
node _c_a_bits_legal_T_76 = and(_c_a_bits_legal_T_75, asSInt(UInt<1>(0h0)))
node _c_a_bits_legal_T_77 = asSInt(_c_a_bits_legal_T_76)
node _c_a_bits_legal_T_78 = eq(_c_a_bits_legal_T_77, asSInt(UInt<1>(0h0)))
node _c_a_bits_legal_T_79 = and(_c_a_bits_legal_T_73, _c_a_bits_legal_T_78)
node c_a_bits_legal_7 = or(UInt<1>(0h0), _c_a_bits_legal_T_79)
wire c_a_bits_a_7 : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect c_a_bits_a_7.opcode, UInt<1>(0h0)
connect c_a_bits_a_7.param, UInt<1>(0h0)
connect c_a_bits_a_7.size, nodeIn_7.c.bits.size
connect c_a_bits_a_7.source, _c_a_bits_T_7
connect c_a_bits_a_7.address, nodeIn_7.c.bits.address
node _c_a_bits_a_mask_sizeOH_T_21 = or(nodeIn_7.c.bits.size, UInt<3>(0h0))
node c_a_bits_a_mask_sizeOH_shiftAmount_7 = bits(_c_a_bits_a_mask_sizeOH_T_21, 1, 0)
node _c_a_bits_a_mask_sizeOH_T_22 = dshl(UInt<1>(0h1), c_a_bits_a_mask_sizeOH_shiftAmount_7)
node _c_a_bits_a_mask_sizeOH_T_23 = bits(_c_a_bits_a_mask_sizeOH_T_22, 2, 0)
node c_a_bits_a_mask_sizeOH_7 = or(_c_a_bits_a_mask_sizeOH_T_23, UInt<1>(0h1))
node c_a_bits_a_mask_sub_sub_sub_0_1_7 = geq(nodeIn_7.c.bits.size, UInt<2>(0h3))
node c_a_bits_a_mask_sub_sub_size_7 = bits(c_a_bits_a_mask_sizeOH_7, 2, 2)
node c_a_bits_a_mask_sub_sub_bit_7 = bits(nodeIn_7.c.bits.address, 2, 2)
node c_a_bits_a_mask_sub_sub_nbit_7 = eq(c_a_bits_a_mask_sub_sub_bit_7, UInt<1>(0h0))
node c_a_bits_a_mask_sub_sub_0_2_7 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_nbit_7)
node _c_a_bits_a_mask_sub_sub_acc_T_14 = and(c_a_bits_a_mask_sub_sub_size_7, c_a_bits_a_mask_sub_sub_0_2_7)
node c_a_bits_a_mask_sub_sub_0_1_7 = or(c_a_bits_a_mask_sub_sub_sub_0_1_7, _c_a_bits_a_mask_sub_sub_acc_T_14)
node c_a_bits_a_mask_sub_sub_1_2_7 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_bit_7)
node _c_a_bits_a_mask_sub_sub_acc_T_15 = and(c_a_bits_a_mask_sub_sub_size_7, c_a_bits_a_mask_sub_sub_1_2_7)
node c_a_bits_a_mask_sub_sub_1_1_7 = or(c_a_bits_a_mask_sub_sub_sub_0_1_7, _c_a_bits_a_mask_sub_sub_acc_T_15)
node c_a_bits_a_mask_sub_size_7 = bits(c_a_bits_a_mask_sizeOH_7, 1, 1)
node c_a_bits_a_mask_sub_bit_7 = bits(nodeIn_7.c.bits.address, 1, 1)
node c_a_bits_a_mask_sub_nbit_7 = eq(c_a_bits_a_mask_sub_bit_7, UInt<1>(0h0))
node c_a_bits_a_mask_sub_0_2_7 = and(c_a_bits_a_mask_sub_sub_0_2_7, c_a_bits_a_mask_sub_nbit_7)
node _c_a_bits_a_mask_sub_acc_T_28 = and(c_a_bits_a_mask_sub_size_7, c_a_bits_a_mask_sub_0_2_7)
node c_a_bits_a_mask_sub_0_1_7 = or(c_a_bits_a_mask_sub_sub_0_1_7, _c_a_bits_a_mask_sub_acc_T_28)
node c_a_bits_a_mask_sub_1_2_7 = and(c_a_bits_a_mask_sub_sub_0_2_7, c_a_bits_a_mask_sub_bit_7)
node _c_a_bits_a_mask_sub_acc_T_29 = and(c_a_bits_a_mask_sub_size_7, c_a_bits_a_mask_sub_1_2_7)
node c_a_bits_a_mask_sub_1_1_7 = or(c_a_bits_a_mask_sub_sub_0_1_7, _c_a_bits_a_mask_sub_acc_T_29)
node c_a_bits_a_mask_sub_2_2_7 = and(c_a_bits_a_mask_sub_sub_1_2_7, c_a_bits_a_mask_sub_nbit_7)
node _c_a_bits_a_mask_sub_acc_T_30 = and(c_a_bits_a_mask_sub_size_7, c_a_bits_a_mask_sub_2_2_7)
node c_a_bits_a_mask_sub_2_1_7 = or(c_a_bits_a_mask_sub_sub_1_1_7, _c_a_bits_a_mask_sub_acc_T_30)
node c_a_bits_a_mask_sub_3_2_7 = and(c_a_bits_a_mask_sub_sub_1_2_7, c_a_bits_a_mask_sub_bit_7)
node _c_a_bits_a_mask_sub_acc_T_31 = and(c_a_bits_a_mask_sub_size_7, c_a_bits_a_mask_sub_3_2_7)
node c_a_bits_a_mask_sub_3_1_7 = or(c_a_bits_a_mask_sub_sub_1_1_7, _c_a_bits_a_mask_sub_acc_T_31)
node c_a_bits_a_mask_size_7 = bits(c_a_bits_a_mask_sizeOH_7, 0, 0)
node c_a_bits_a_mask_bit_7 = bits(nodeIn_7.c.bits.address, 0, 0)
node c_a_bits_a_mask_nbit_7 = eq(c_a_bits_a_mask_bit_7, UInt<1>(0h0))
node c_a_bits_a_mask_eq_56 = and(c_a_bits_a_mask_sub_0_2_7, c_a_bits_a_mask_nbit_7)
node _c_a_bits_a_mask_acc_T_56 = and(c_a_bits_a_mask_size_7, c_a_bits_a_mask_eq_56)
node c_a_bits_a_mask_acc_56 = or(c_a_bits_a_mask_sub_0_1_7, _c_a_bits_a_mask_acc_T_56)
node c_a_bits_a_mask_eq_57 = and(c_a_bits_a_mask_sub_0_2_7, c_a_bits_a_mask_bit_7)
node _c_a_bits_a_mask_acc_T_57 = and(c_a_bits_a_mask_size_7, c_a_bits_a_mask_eq_57)
node c_a_bits_a_mask_acc_57 = or(c_a_bits_a_mask_sub_0_1_7, _c_a_bits_a_mask_acc_T_57)
node c_a_bits_a_mask_eq_58 = and(c_a_bits_a_mask_sub_1_2_7, c_a_bits_a_mask_nbit_7)
node _c_a_bits_a_mask_acc_T_58 = and(c_a_bits_a_mask_size_7, c_a_bits_a_mask_eq_58)
node c_a_bits_a_mask_acc_58 = or(c_a_bits_a_mask_sub_1_1_7, _c_a_bits_a_mask_acc_T_58)
node c_a_bits_a_mask_eq_59 = and(c_a_bits_a_mask_sub_1_2_7, c_a_bits_a_mask_bit_7)
node _c_a_bits_a_mask_acc_T_59 = and(c_a_bits_a_mask_size_7, c_a_bits_a_mask_eq_59)
node c_a_bits_a_mask_acc_59 = or(c_a_bits_a_mask_sub_1_1_7, _c_a_bits_a_mask_acc_T_59)
node c_a_bits_a_mask_eq_60 = and(c_a_bits_a_mask_sub_2_2_7, c_a_bits_a_mask_nbit_7)
node _c_a_bits_a_mask_acc_T_60 = and(c_a_bits_a_mask_size_7, c_a_bits_a_mask_eq_60)
node c_a_bits_a_mask_acc_60 = or(c_a_bits_a_mask_sub_2_1_7, _c_a_bits_a_mask_acc_T_60)
node c_a_bits_a_mask_eq_61 = and(c_a_bits_a_mask_sub_2_2_7, c_a_bits_a_mask_bit_7)
node _c_a_bits_a_mask_acc_T_61 = and(c_a_bits_a_mask_size_7, c_a_bits_a_mask_eq_61)
node c_a_bits_a_mask_acc_61 = or(c_a_bits_a_mask_sub_2_1_7, _c_a_bits_a_mask_acc_T_61)
node c_a_bits_a_mask_eq_62 = and(c_a_bits_a_mask_sub_3_2_7, c_a_bits_a_mask_nbit_7)
node _c_a_bits_a_mask_acc_T_62 = and(c_a_bits_a_mask_size_7, c_a_bits_a_mask_eq_62)
node c_a_bits_a_mask_acc_62 = or(c_a_bits_a_mask_sub_3_1_7, _c_a_bits_a_mask_acc_T_62)
node c_a_bits_a_mask_eq_63 = and(c_a_bits_a_mask_sub_3_2_7, c_a_bits_a_mask_bit_7)
node _c_a_bits_a_mask_acc_T_63 = and(c_a_bits_a_mask_size_7, c_a_bits_a_mask_eq_63)
node c_a_bits_a_mask_acc_63 = or(c_a_bits_a_mask_sub_3_1_7, _c_a_bits_a_mask_acc_T_63)
node c_a_bits_a_mask_lo_lo_7 = cat(c_a_bits_a_mask_acc_57, c_a_bits_a_mask_acc_56)
node c_a_bits_a_mask_lo_hi_7 = cat(c_a_bits_a_mask_acc_59, c_a_bits_a_mask_acc_58)
node c_a_bits_a_mask_lo_7 = cat(c_a_bits_a_mask_lo_hi_7, c_a_bits_a_mask_lo_lo_7)
node c_a_bits_a_mask_hi_lo_7 = cat(c_a_bits_a_mask_acc_61, c_a_bits_a_mask_acc_60)
node c_a_bits_a_mask_hi_hi_7 = cat(c_a_bits_a_mask_acc_63, c_a_bits_a_mask_acc_62)
node c_a_bits_a_mask_hi_7 = cat(c_a_bits_a_mask_hi_hi_7, c_a_bits_a_mask_hi_lo_7)
node _c_a_bits_a_mask_T_7 = cat(c_a_bits_a_mask_hi_7, c_a_bits_a_mask_lo_7)
connect c_a_bits_a_7.mask, _c_a_bits_a_mask_T_7
connect c_a_bits_a_7.data, nodeIn_7.c.bits.data
connect c_a_bits_a_7.corrupt, nodeIn_7.c.bits.corrupt
connect c_a_7.bits, c_a_bits_a_7
wire c_d_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _c_d_valid_T_14 = eq(nodeIn_7.c.bits.opcode, UInt<3>(0h6))
node _c_d_valid_T_15 = and(nodeIn_7.c.valid, _c_d_valid_T_14)
connect c_d_7.valid, _c_d_valid_T_15
wire c_d_bits_d_7 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect c_d_bits_d_7.opcode, UInt<3>(0h6)
connect c_d_bits_d_7.param, UInt<1>(0h0)
connect c_d_bits_d_7.size, nodeIn_7.c.bits.size
connect c_d_bits_d_7.source, nodeIn_7.c.bits.source
connect c_d_bits_d_7.sink, UInt<1>(0h0)
connect c_d_bits_d_7.denied, UInt<1>(0h0)
invalidate c_d_bits_d_7.data
connect c_d_bits_d_7.corrupt, UInt<1>(0h0)
connect c_d_7.bits.corrupt, c_d_bits_d_7.corrupt
connect c_d_7.bits.data, c_d_bits_d_7.data
connect c_d_7.bits.denied, c_d_bits_d_7.denied
connect c_d_7.bits.sink, c_d_bits_d_7.sink
connect c_d_7.bits.source, c_d_bits_d_7.source
connect c_d_7.bits.size, c_d_bits_d_7.size
connect c_d_7.bits.param, c_d_bits_d_7.param
connect c_d_7.bits.opcode, c_d_bits_d_7.opcode
node _T_465 = eq(nodeIn_7.c.valid, UInt<1>(0h0))
node _T_466 = eq(nodeIn_7.c.bits.opcode, UInt<3>(0h6))
node _T_467 = or(_T_465, _T_466)
node _T_468 = eq(nodeIn_7.c.bits.opcode, UInt<3>(0h7))
node _T_469 = or(_T_467, _T_468)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:116 assert (!in.c.valid || in.c.bits.opcode === Release || in.c.bits.opcode === ReleaseData)\n") : printf_42
assert(clock, _T_469, UInt<1>(0h1), "") : assert_42
node _nodeIn_c_ready_T_14 = eq(nodeIn_7.c.bits.opcode, UInt<3>(0h6))
node _nodeIn_c_ready_T_15 = mux(_nodeIn_c_ready_T_14, c_d_7.ready, c_a_7.ready)
connect nodeIn_7.c.ready, _nodeIn_c_ready_T_15
connect nodeIn_7.e.ready, UInt<1>(0h1)
wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_56.bits.corrupt, UInt<1>(0h0)
connect _WIRE_56.bits.data, UInt<64>(0h0)
connect _WIRE_56.bits.mask, UInt<8>(0h0)
connect _WIRE_56.bits.address, UInt<32>(0h0)
connect _WIRE_56.bits.source, UInt<5>(0h0)
connect _WIRE_56.bits.size, UInt<3>(0h0)
connect _WIRE_56.bits.param, UInt<2>(0h0)
connect _WIRE_56.bits.opcode, UInt<3>(0h0)
connect _WIRE_56.valid, UInt<1>(0h0)
connect _WIRE_56.ready, UInt<1>(0h0)
wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_57.bits, _WIRE_56.bits
connect _WIRE_57.valid, _WIRE_56.valid
connect _WIRE_57.ready, _WIRE_56.ready
connect _WIRE_57.ready, UInt<1>(0h0)
wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_58.bits.corrupt, UInt<1>(0h0)
connect _WIRE_58.bits.data, UInt<64>(0h0)
connect _WIRE_58.bits.mask, UInt<8>(0h0)
connect _WIRE_58.bits.address, UInt<32>(0h0)
connect _WIRE_58.bits.source, UInt<5>(0h0)
connect _WIRE_58.bits.size, UInt<3>(0h0)
connect _WIRE_58.bits.param, UInt<2>(0h0)
connect _WIRE_58.bits.opcode, UInt<3>(0h0)
connect _WIRE_58.valid, UInt<1>(0h0)
connect _WIRE_58.ready, UInt<1>(0h0)
wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_59.bits, _WIRE_58.bits
connect _WIRE_59.valid, _WIRE_58.valid
connect _WIRE_59.ready, _WIRE_58.ready
node _T_473 = eq(_WIRE_59.valid, UInt<1>(0h0))
node _T_474 = asUInt(reset)
node _T_475 = eq(_T_474, UInt<1>(0h0))
when _T_475 :
node _T_476 = eq(_T_473, UInt<1>(0h0))
when _T_476 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:124 assert (!out.b.valid)\n") : printf_43
assert(clock, _T_473, UInt<1>(0h1), "") : assert_43
inst pool_7 of IDPool_7
connect pool_7.clock, clock
connect pool_7.reset, reset
node _pool_io_free_valid_T_7 = and(nodeIn_7.e.ready, nodeIn_7.e.valid)
connect pool_7.io.free.valid, _pool_io_free_valid_T_7
connect pool_7.io.free.bits, nodeIn_7.e.bits.sink
wire in_d_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _d_first_T_7 = and(in_d_7.ready, in_d_7.valid)
node _d_first_beats1_decode_T_21 = dshl(UInt<6>(0h3f), in_d_7.bits.size)
node _d_first_beats1_decode_T_22 = bits(_d_first_beats1_decode_T_21, 5, 0)
node _d_first_beats1_decode_T_23 = not(_d_first_beats1_decode_T_22)
node d_first_beats1_decode_7 = shr(_d_first_beats1_decode_T_23, 3)
node d_first_beats1_opdata_7 = bits(in_d_7.bits.opcode, 0, 0)
node d_first_beats1_7 = mux(d_first_beats1_opdata_7, d_first_beats1_decode_7, UInt<1>(0h0))
regreset d_first_counter_7 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_7 = sub(d_first_counter_7, UInt<1>(0h1))
node d_first_counter1_7 = tail(_d_first_counter1_T_7, 1)
node d_first_7 = eq(d_first_counter_7, UInt<1>(0h0))
node _d_first_last_T_14 = eq(d_first_counter_7, UInt<1>(0h1))
node _d_first_last_T_15 = eq(d_first_beats1_7, UInt<1>(0h0))
node d_first_last_7 = or(_d_first_last_T_14, _d_first_last_T_15)
node d_first_done_7 = and(d_first_last_7, _d_first_T_7)
node _d_first_count_T_7 = not(d_first_counter1_7)
node d_first_count_7 = and(d_first_beats1_7, _d_first_count_T_7)
when _d_first_T_7 :
node _d_first_counter_T_7 = mux(d_first_7, d_first_beats1_7, d_first_counter1_7)
connect d_first_counter_7, _d_first_counter_T_7
node _d_grant_T_14 = eq(in_d_7.bits.opcode, UInt<3>(0h5))
node _d_grant_T_15 = eq(in_d_7.bits.opcode, UInt<3>(0h4))
node d_grant_7 = or(_d_grant_T_14, _d_grant_T_15)
node _pool_io_alloc_ready_T_21 = and(nodeIn_7.d.ready, nodeIn_7.d.valid)
node _pool_io_alloc_ready_T_22 = and(_pool_io_alloc_ready_T_21, d_first_7)
node _pool_io_alloc_ready_T_23 = and(_pool_io_alloc_ready_T_22, d_grant_7)
connect pool_7.io.alloc.ready, _pool_io_alloc_ready_T_23
node _nodeIn_d_valid_T_35 = eq(d_first_7, UInt<1>(0h0))
node _nodeIn_d_valid_T_36 = or(pool_7.io.alloc.valid, _nodeIn_d_valid_T_35)
node _nodeIn_d_valid_T_37 = eq(d_grant_7, UInt<1>(0h0))
node _nodeIn_d_valid_T_38 = or(_nodeIn_d_valid_T_36, _nodeIn_d_valid_T_37)
node _nodeIn_d_valid_T_39 = and(in_d_7.valid, _nodeIn_d_valid_T_38)
connect nodeIn_7.d.valid, _nodeIn_d_valid_T_39
node _in_d_ready_T_35 = eq(d_first_7, UInt<1>(0h0))
node _in_d_ready_T_36 = or(pool_7.io.alloc.valid, _in_d_ready_T_35)
node _in_d_ready_T_37 = eq(d_grant_7, UInt<1>(0h0))
node _in_d_ready_T_38 = or(_in_d_ready_T_36, _in_d_ready_T_37)
node _in_d_ready_T_39 = and(nodeIn_7.d.ready, _in_d_ready_T_38)
connect in_d_7.ready, _in_d_ready_T_39
connect nodeIn_7.d.bits.corrupt, in_d_7.bits.corrupt
connect nodeIn_7.d.bits.data, in_d_7.bits.data
connect nodeIn_7.d.bits.denied, in_d_7.bits.denied
connect nodeIn_7.d.bits.sink, in_d_7.bits.sink
connect nodeIn_7.d.bits.source, in_d_7.bits.source
connect nodeIn_7.d.bits.size, in_d_7.bits.size
connect nodeIn_7.d.bits.param, in_d_7.bits.param
connect nodeIn_7.d.bits.opcode, in_d_7.bits.opcode
reg nodeIn_d_bits_sink_r_7 : UInt<3>, clock
when d_first_7 :
connect nodeIn_d_bits_sink_r_7, pool_7.io.alloc.bits
node _nodeIn_d_bits_sink_T_7 = mux(d_first_7, pool_7.io.alloc.bits, nodeIn_d_bits_sink_r_7)
connect nodeIn_7.d.bits.sink, _nodeIn_d_bits_sink_T_7
wire d_d_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect d_d_7, x1_nodeOut_6.d
node _d_d_bits_source_T_7 = shr(x1_nodeOut_6.d.bits.source, 1)
connect d_d_7.bits.source, _d_d_bits_source_T_7
reg wSourceVec_7 : UInt<1>[10], clock
node _aWOk_T_35 = xor(nodeIn_7.a.bits.address, UInt<1>(0h0))
node _aWOk_T_36 = cvt(_aWOk_T_35)
node _aWOk_T_37 = and(_aWOk_T_36, asSInt(UInt<1>(0h0)))
node _aWOk_T_38 = asSInt(_aWOk_T_37)
node _aWOk_T_39 = eq(_aWOk_T_38, asSInt(UInt<1>(0h0)))
node _bypass_T_14 = and(UInt<1>(0h0), nodeIn_7.a.valid)
node _bypass_T_15 = eq(nodeIn_7.a.bits.source, d_d_7.bits.source)
node bypass_7 = and(_bypass_T_14, _bypass_T_15)
node _dWHeld_T_7 = mux(bypass_7, UInt<1>(0h1), wSourceVec_7[d_d_7.bits.source])
reg dWHeld_r_7 : UInt<1>, clock
when d_first_7 :
connect dWHeld_r_7, _dWHeld_T_7
node dWHeld_7 = mux(d_first_7, _dWHeld_T_7, dWHeld_r_7)
node _T_477 = and(nodeIn_7.a.ready, nodeIn_7.a.valid)
when _T_477 :
connect wSourceVec_7[nodeIn_7.a.bits.source], UInt<1>(0h1)
node _T_478 = eq(x1_nodeOut_6.d.bits.opcode, UInt<1>(0h1))
node _T_479 = bits(x1_nodeOut_6.d.bits.source, 0, 0)
node _T_480 = and(_T_478, _T_479)
when _T_480 :
connect d_d_7.bits.opcode, UInt<3>(0h5)
node _d_d_bits_param_T_7 = mux(dWHeld_7, UInt<2>(0h0), UInt<2>(0h1))
connect d_d_7.bits.param, _d_d_bits_param_T_7
node _T_481 = eq(x1_nodeOut_6.d.bits.opcode, UInt<1>(0h0))
node _T_482 = bits(x1_nodeOut_6.d.bits.source, 0, 0)
node _T_483 = eq(_T_482, UInt<1>(0h0))
node _T_484 = and(_T_481, _T_483)
when _T_484 :
connect d_d_7.bits.opcode, UInt<3>(0h6)
node _decode_T_63 = dshl(UInt<6>(0h3f), c_a_7.bits.size)
node _decode_T_64 = bits(_decode_T_63, 5, 0)
node _decode_T_65 = not(_decode_T_64)
node decode_21 = shr(_decode_T_65, 3)
node _opdata_T_14 = bits(c_a_7.bits.opcode, 2, 2)
node opdata_21 = eq(_opdata_T_14, UInt<1>(0h0))
node _T_485 = mux(opdata_21, decode_21, UInt<1>(0h0))
node _decode_T_66 = dshl(UInt<6>(0h3f), a_a_7.bits.size)
node _decode_T_67 = bits(_decode_T_66, 5, 0)
node _decode_T_68 = not(_decode_T_67)
node decode_22 = shr(_decode_T_68, 3)
node _opdata_T_15 = bits(a_a_7.bits.opcode, 2, 2)
node opdata_22 = eq(_opdata_T_15, UInt<1>(0h0))
node _T_486 = mux(opdata_22, decode_22, UInt<1>(0h0))
regreset beatsLeft_14 : UInt, clock, reset, UInt<1>(0h0)
node idle_14 = eq(beatsLeft_14, UInt<1>(0h0))
node latch_14 = and(idle_14, x1_nodeOut_6.a.ready)
node _readys_T_168 = cat(a_a_7.valid, c_a_7.valid)
node _readys_T_169 = shl(_readys_T_168, 1)
node _readys_T_170 = bits(_readys_T_169, 1, 0)
node _readys_T_171 = or(_readys_T_168, _readys_T_170)
node _readys_T_172 = bits(_readys_T_171, 1, 0)
node _readys_T_173 = shl(_readys_T_172, 1)
node _readys_T_174 = bits(_readys_T_173, 1, 0)
node _readys_T_175 = not(_readys_T_174)
node _readys_T_176 = bits(_readys_T_175, 0, 0)
node _readys_T_177 = bits(_readys_T_175, 1, 1)
wire readys_14 : UInt<1>[2]
connect readys_14[0], _readys_T_176
connect readys_14[1], _readys_T_177
node _winner_T_35 = and(readys_14[0], c_a_7.valid)
node _winner_T_36 = and(readys_14[1], a_a_7.valid)
wire winner_14 : UInt<1>[2]
connect winner_14[0], _winner_T_35
connect winner_14[1], _winner_T_36
node prefixOR_1_14 = or(UInt<1>(0h0), winner_14[0])
node _prefixOR_T_14 = or(prefixOR_1_14, winner_14[1])
node _T_487 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_488 = eq(winner_14[0], UInt<1>(0h0))
node _T_489 = or(_T_487, _T_488)
node _T_490 = eq(prefixOR_1_14, UInt<1>(0h0))
node _T_491 = eq(winner_14[1], UInt<1>(0h0))
node _T_492 = or(_T_490, _T_491)
node _T_493 = and(_T_489, _T_492)
node _T_494 = asUInt(reset)
node _T_495 = eq(_T_494, UInt<1>(0h0))
when _T_495 :
node _T_496 = eq(_T_493, UInt<1>(0h0))
when _T_496 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_44
assert(clock, _T_493, UInt<1>(0h1), "") : assert_44
node _T_497 = or(c_a_7.valid, a_a_7.valid)
node _T_498 = eq(_T_497, UInt<1>(0h0))
node _T_499 = or(winner_14[0], winner_14[1])
node _T_500 = or(_T_498, _T_499)
node _T_501 = asUInt(reset)
node _T_502 = eq(_T_501, UInt<1>(0h0))
when _T_502 :
node _T_503 = eq(_T_500, UInt<1>(0h0))
when _T_503 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_45
assert(clock, _T_500, UInt<1>(0h1), "") : assert_45
node maskedBeats_0_14 = mux(winner_14[0], _T_485, UInt<1>(0h0))
node maskedBeats_1_14 = mux(winner_14[1], _T_486, UInt<1>(0h0))
node initBeats_14 = or(maskedBeats_0_14, maskedBeats_1_14)
node _beatsLeft_T_56 = and(x1_nodeOut_6.a.ready, x1_nodeOut_6.a.valid)
node _beatsLeft_T_57 = sub(beatsLeft_14, _beatsLeft_T_56)
node _beatsLeft_T_58 = tail(_beatsLeft_T_57, 1)
node _beatsLeft_T_59 = mux(latch_14, initBeats_14, _beatsLeft_T_58)
connect beatsLeft_14, _beatsLeft_T_59
wire _state_WIRE_14 : UInt<1>[2]
connect _state_WIRE_14[0], UInt<1>(0h0)
connect _state_WIRE_14[1], UInt<1>(0h0)
regreset state_14 : UInt<1>[2], clock, reset, _state_WIRE_14
node muxState_14 = mux(idle_14, winner_14, state_14)
connect state_14, muxState_14
node allowed_14 = mux(idle_14, readys_14, state_14)
node _c_a_ready_T_7 = and(x1_nodeOut_6.a.ready, allowed_14[0])
connect c_a_7.ready, _c_a_ready_T_7
node _a_a_ready_T_7 = and(x1_nodeOut_6.a.ready, allowed_14[1])
connect a_a_7.ready, _a_a_ready_T_7
node _nodeOut_a_valid_T_35 = or(c_a_7.valid, a_a_7.valid)
node _nodeOut_a_valid_T_36 = mux(state_14[0], c_a_7.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_37 = mux(state_14[1], a_a_7.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_38 = or(_nodeOut_a_valid_T_36, _nodeOut_a_valid_T_37)
wire _nodeOut_a_valid_WIRE_7 : UInt<1>
connect _nodeOut_a_valid_WIRE_7, _nodeOut_a_valid_T_38
node _nodeOut_a_valid_T_39 = mux(idle_14, _nodeOut_a_valid_T_35, _nodeOut_a_valid_WIRE_7)
connect x1_nodeOut_6.a.valid, _nodeOut_a_valid_T_39
wire _nodeOut_a_bits_WIRE_77 : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _nodeOut_a_bits_T_168 = mux(muxState_14[0], c_a_7.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_169 = mux(muxState_14[1], a_a_7.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_170 = or(_nodeOut_a_bits_T_168, _nodeOut_a_bits_T_169)
wire _nodeOut_a_bits_WIRE_78 : UInt<1>
connect _nodeOut_a_bits_WIRE_78, _nodeOut_a_bits_T_170
connect _nodeOut_a_bits_WIRE_77.corrupt, _nodeOut_a_bits_WIRE_78
node _nodeOut_a_bits_T_171 = mux(muxState_14[0], c_a_7.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_172 = mux(muxState_14[1], a_a_7.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_173 = or(_nodeOut_a_bits_T_171, _nodeOut_a_bits_T_172)
wire _nodeOut_a_bits_WIRE_79 : UInt<64>
connect _nodeOut_a_bits_WIRE_79, _nodeOut_a_bits_T_173
connect _nodeOut_a_bits_WIRE_77.data, _nodeOut_a_bits_WIRE_79
node _nodeOut_a_bits_T_174 = mux(muxState_14[0], c_a_7.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_175 = mux(muxState_14[1], a_a_7.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_176 = or(_nodeOut_a_bits_T_174, _nodeOut_a_bits_T_175)
wire _nodeOut_a_bits_WIRE_80 : UInt<8>
connect _nodeOut_a_bits_WIRE_80, _nodeOut_a_bits_T_176
connect _nodeOut_a_bits_WIRE_77.mask, _nodeOut_a_bits_WIRE_80
wire _nodeOut_a_bits_WIRE_81 : { }
connect _nodeOut_a_bits_WIRE_77.echo, _nodeOut_a_bits_WIRE_81
wire _nodeOut_a_bits_WIRE_82 : { }
connect _nodeOut_a_bits_WIRE_77.user, _nodeOut_a_bits_WIRE_82
node _nodeOut_a_bits_T_177 = mux(muxState_14[0], c_a_7.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_178 = mux(muxState_14[1], a_a_7.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_179 = or(_nodeOut_a_bits_T_177, _nodeOut_a_bits_T_178)
wire _nodeOut_a_bits_WIRE_83 : UInt<32>
connect _nodeOut_a_bits_WIRE_83, _nodeOut_a_bits_T_179
connect _nodeOut_a_bits_WIRE_77.address, _nodeOut_a_bits_WIRE_83
node _nodeOut_a_bits_T_180 = mux(muxState_14[0], c_a_7.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_181 = mux(muxState_14[1], a_a_7.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_182 = or(_nodeOut_a_bits_T_180, _nodeOut_a_bits_T_181)
wire _nodeOut_a_bits_WIRE_84 : UInt<5>
connect _nodeOut_a_bits_WIRE_84, _nodeOut_a_bits_T_182
connect _nodeOut_a_bits_WIRE_77.source, _nodeOut_a_bits_WIRE_84
node _nodeOut_a_bits_T_183 = mux(muxState_14[0], c_a_7.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_184 = mux(muxState_14[1], a_a_7.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_185 = or(_nodeOut_a_bits_T_183, _nodeOut_a_bits_T_184)
wire _nodeOut_a_bits_WIRE_85 : UInt<3>
connect _nodeOut_a_bits_WIRE_85, _nodeOut_a_bits_T_185
connect _nodeOut_a_bits_WIRE_77.size, _nodeOut_a_bits_WIRE_85
node _nodeOut_a_bits_T_186 = mux(muxState_14[0], c_a_7.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_187 = mux(muxState_14[1], a_a_7.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_188 = or(_nodeOut_a_bits_T_186, _nodeOut_a_bits_T_187)
wire _nodeOut_a_bits_WIRE_86 : UInt<3>
connect _nodeOut_a_bits_WIRE_86, _nodeOut_a_bits_T_188
connect _nodeOut_a_bits_WIRE_77.param, _nodeOut_a_bits_WIRE_86
node _nodeOut_a_bits_T_189 = mux(muxState_14[0], c_a_7.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_190 = mux(muxState_14[1], a_a_7.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_191 = or(_nodeOut_a_bits_T_189, _nodeOut_a_bits_T_190)
wire _nodeOut_a_bits_WIRE_87 : UInt<3>
connect _nodeOut_a_bits_WIRE_87, _nodeOut_a_bits_T_191
connect _nodeOut_a_bits_WIRE_77.opcode, _nodeOut_a_bits_WIRE_87
connect x1_nodeOut_6.a.bits.corrupt, _nodeOut_a_bits_WIRE_77.corrupt
connect x1_nodeOut_6.a.bits.data, _nodeOut_a_bits_WIRE_77.data
connect x1_nodeOut_6.a.bits.mask, _nodeOut_a_bits_WIRE_77.mask
connect x1_nodeOut_6.a.bits.address, _nodeOut_a_bits_WIRE_77.address
connect x1_nodeOut_6.a.bits.source, _nodeOut_a_bits_WIRE_77.source
connect x1_nodeOut_6.a.bits.size, _nodeOut_a_bits_WIRE_77.size
connect x1_nodeOut_6.a.bits.param, _nodeOut_a_bits_WIRE_77.param
connect x1_nodeOut_6.a.bits.opcode, _nodeOut_a_bits_WIRE_77.opcode
node _decode_T_69 = dshl(UInt<6>(0h3f), d_d_7.bits.size)
node _decode_T_70 = bits(_decode_T_69, 5, 0)
node _decode_T_71 = not(_decode_T_70)
node decode_23 = shr(_decode_T_71, 3)
node opdata_23 = bits(d_d_7.bits.opcode, 0, 0)
node _T_504 = mux(opdata_23, decode_23, UInt<1>(0h0))
inst q_14 of Queue2_TLBundleD_a32d64s4k3z3c_22
connect q_14.clock, clock
connect q_14.reset, reset
connect q_14.io.enq.valid, c_d_7.valid
connect q_14.io.enq.bits.corrupt, c_d_7.bits.corrupt
connect q_14.io.enq.bits.data, c_d_7.bits.data
connect q_14.io.enq.bits.denied, c_d_7.bits.denied
connect q_14.io.enq.bits.sink, c_d_7.bits.sink
connect q_14.io.enq.bits.source, c_d_7.bits.source
connect q_14.io.enq.bits.size, c_d_7.bits.size
connect q_14.io.enq.bits.param, c_d_7.bits.param
connect q_14.io.enq.bits.opcode, c_d_7.bits.opcode
connect c_d_7.ready, q_14.io.enq.ready
inst q_15 of Queue2_TLBundleD_a32d64s4k3z3c_23
connect q_15.clock, clock
connect q_15.reset, reset
connect q_15.io.enq.valid, a_d_7.valid
connect q_15.io.enq.bits.corrupt, a_d_7.bits.corrupt
connect q_15.io.enq.bits.data, a_d_7.bits.data
connect q_15.io.enq.bits.denied, a_d_7.bits.denied
connect q_15.io.enq.bits.sink, a_d_7.bits.sink
connect q_15.io.enq.bits.source, a_d_7.bits.source
connect q_15.io.enq.bits.size, a_d_7.bits.size
connect q_15.io.enq.bits.param, a_d_7.bits.param
connect q_15.io.enq.bits.opcode, a_d_7.bits.opcode
connect a_d_7.ready, q_15.io.enq.ready
regreset beatsLeft_15 : UInt, clock, reset, UInt<1>(0h0)
node idle_15 = eq(beatsLeft_15, UInt<1>(0h0))
node latch_15 = and(idle_15, in_d_7.ready)
node readys_hi_7 = cat(q_15.io.deq.valid, q_14.io.deq.valid)
node _readys_T_178 = cat(readys_hi_7, d_d_7.valid)
node _readys_T_179 = shl(_readys_T_178, 1)
node _readys_T_180 = bits(_readys_T_179, 2, 0)
node _readys_T_181 = or(_readys_T_178, _readys_T_180)
node _readys_T_182 = shl(_readys_T_181, 2)
node _readys_T_183 = bits(_readys_T_182, 2, 0)
node _readys_T_184 = or(_readys_T_181, _readys_T_183)
node _readys_T_185 = bits(_readys_T_184, 2, 0)
node _readys_T_186 = shl(_readys_T_185, 1)
node _readys_T_187 = bits(_readys_T_186, 2, 0)
node _readys_T_188 = not(_readys_T_187)
node _readys_T_189 = bits(_readys_T_188, 0, 0)
node _readys_T_190 = bits(_readys_T_188, 1, 1)
node _readys_T_191 = bits(_readys_T_188, 2, 2)
wire readys_15 : UInt<1>[3]
connect readys_15[0], _readys_T_189
connect readys_15[1], _readys_T_190
connect readys_15[2], _readys_T_191
node _winner_T_37 = and(readys_15[0], d_d_7.valid)
node _winner_T_38 = and(readys_15[1], q_14.io.deq.valid)
node _winner_T_39 = and(readys_15[2], q_15.io.deq.valid)
wire winner_15 : UInt<1>[3]
connect winner_15[0], _winner_T_37
connect winner_15[1], _winner_T_38
connect winner_15[2], _winner_T_39
node prefixOR_1_15 = or(UInt<1>(0h0), winner_15[0])
node prefixOR_2_7 = or(prefixOR_1_15, winner_15[1])
node _prefixOR_T_15 = or(prefixOR_2_7, winner_15[2])
node _T_505 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_506 = eq(winner_15[0], UInt<1>(0h0))
node _T_507 = or(_T_505, _T_506)
node _T_508 = eq(prefixOR_1_15, UInt<1>(0h0))
node _T_509 = eq(winner_15[1], UInt<1>(0h0))
node _T_510 = or(_T_508, _T_509)
node _T_511 = eq(prefixOR_2_7, UInt<1>(0h0))
node _T_512 = eq(winner_15[2], UInt<1>(0h0))
node _T_513 = or(_T_511, _T_512)
node _T_514 = and(_T_507, _T_510)
node _T_515 = and(_T_514, _T_513)
node _T_516 = asUInt(reset)
node _T_517 = eq(_T_516, UInt<1>(0h0))
when _T_517 :
node _T_518 = eq(_T_515, UInt<1>(0h0))
when _T_518 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_46
assert(clock, _T_515, UInt<1>(0h1), "") : assert_46
node _T_519 = or(d_d_7.valid, q_14.io.deq.valid)
node _T_520 = or(_T_519, q_15.io.deq.valid)
node _T_521 = eq(_T_520, UInt<1>(0h0))
node _T_522 = or(winner_15[0], winner_15[1])
node _T_523 = or(_T_522, winner_15[2])
node _T_524 = or(_T_521, _T_523)
node _T_525 = asUInt(reset)
node _T_526 = eq(_T_525, UInt<1>(0h0))
when _T_526 :
node _T_527 = eq(_T_524, UInt<1>(0h0))
when _T_527 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_47
assert(clock, _T_524, UInt<1>(0h1), "") : assert_47
node maskedBeats_0_15 = mux(winner_15[0], _T_504, UInt<1>(0h0))
node maskedBeats_1_15 = mux(winner_15[1], UInt<1>(0h0), UInt<1>(0h0))
node maskedBeats_2_7 = mux(winner_15[2], UInt<1>(0h0), UInt<1>(0h0))
node _initBeats_T_7 = or(maskedBeats_0_15, maskedBeats_1_15)
node initBeats_15 = or(_initBeats_T_7, maskedBeats_2_7)
node _beatsLeft_T_60 = and(in_d_7.ready, in_d_7.valid)
node _beatsLeft_T_61 = sub(beatsLeft_15, _beatsLeft_T_60)
node _beatsLeft_T_62 = tail(_beatsLeft_T_61, 1)
node _beatsLeft_T_63 = mux(latch_15, initBeats_15, _beatsLeft_T_62)
connect beatsLeft_15, _beatsLeft_T_63
wire _state_WIRE_15 : UInt<1>[3]
connect _state_WIRE_15[0], UInt<1>(0h0)
connect _state_WIRE_15[1], UInt<1>(0h0)
connect _state_WIRE_15[2], UInt<1>(0h0)
regreset state_15 : UInt<1>[3], clock, reset, _state_WIRE_15
node muxState_15 = mux(idle_15, winner_15, state_15)
connect state_15, muxState_15
node allowed_15 = mux(idle_15, readys_15, state_15)
node _d_d_ready_T_7 = and(in_d_7.ready, allowed_15[0])
connect d_d_7.ready, _d_d_ready_T_7
node _q_io_deq_ready_T_14 = and(in_d_7.ready, allowed_15[1])
connect q_14.io.deq.ready, _q_io_deq_ready_T_14
node _q_io_deq_ready_T_15 = and(in_d_7.ready, allowed_15[2])
connect q_15.io.deq.ready, _q_io_deq_ready_T_15
node _in_d_valid_T_56 = or(d_d_7.valid, q_14.io.deq.valid)
node _in_d_valid_T_57 = or(_in_d_valid_T_56, q_15.io.deq.valid)
node _in_d_valid_T_58 = mux(state_15[0], d_d_7.valid, UInt<1>(0h0))
node _in_d_valid_T_59 = mux(state_15[1], q_14.io.deq.valid, UInt<1>(0h0))
node _in_d_valid_T_60 = mux(state_15[2], q_15.io.deq.valid, UInt<1>(0h0))
node _in_d_valid_T_61 = or(_in_d_valid_T_58, _in_d_valid_T_59)
node _in_d_valid_T_62 = or(_in_d_valid_T_61, _in_d_valid_T_60)
wire _in_d_valid_WIRE_7 : UInt<1>
connect _in_d_valid_WIRE_7, _in_d_valid_T_62
node _in_d_valid_T_63 = mux(idle_15, _in_d_valid_T_57, _in_d_valid_WIRE_7)
connect in_d_7.valid, _in_d_valid_T_63
wire _in_d_bits_WIRE_77 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_d_bits_T_280 = mux(muxState_15[0], d_d_7.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_281 = mux(muxState_15[1], q_14.io.deq.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_282 = mux(muxState_15[2], q_15.io.deq.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_283 = or(_in_d_bits_T_280, _in_d_bits_T_281)
node _in_d_bits_T_284 = or(_in_d_bits_T_283, _in_d_bits_T_282)
wire _in_d_bits_WIRE_78 : UInt<1>
connect _in_d_bits_WIRE_78, _in_d_bits_T_284
connect _in_d_bits_WIRE_77.corrupt, _in_d_bits_WIRE_78
node _in_d_bits_T_285 = mux(muxState_15[0], d_d_7.bits.data, UInt<1>(0h0))
node _in_d_bits_T_286 = mux(muxState_15[1], q_14.io.deq.bits.data, UInt<1>(0h0))
node _in_d_bits_T_287 = mux(muxState_15[2], q_15.io.deq.bits.data, UInt<1>(0h0))
node _in_d_bits_T_288 = or(_in_d_bits_T_285, _in_d_bits_T_286)
node _in_d_bits_T_289 = or(_in_d_bits_T_288, _in_d_bits_T_287)
wire _in_d_bits_WIRE_79 : UInt<64>
connect _in_d_bits_WIRE_79, _in_d_bits_T_289
connect _in_d_bits_WIRE_77.data, _in_d_bits_WIRE_79
wire _in_d_bits_WIRE_80 : { }
connect _in_d_bits_WIRE_77.echo, _in_d_bits_WIRE_80
wire _in_d_bits_WIRE_81 : { }
connect _in_d_bits_WIRE_77.user, _in_d_bits_WIRE_81
node _in_d_bits_T_290 = mux(muxState_15[0], d_d_7.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_291 = mux(muxState_15[1], q_14.io.deq.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_292 = mux(muxState_15[2], q_15.io.deq.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_293 = or(_in_d_bits_T_290, _in_d_bits_T_291)
node _in_d_bits_T_294 = or(_in_d_bits_T_293, _in_d_bits_T_292)
wire _in_d_bits_WIRE_82 : UInt<1>
connect _in_d_bits_WIRE_82, _in_d_bits_T_294
connect _in_d_bits_WIRE_77.denied, _in_d_bits_WIRE_82
node _in_d_bits_T_295 = mux(muxState_15[0], d_d_7.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_296 = mux(muxState_15[1], q_14.io.deq.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_297 = mux(muxState_15[2], q_15.io.deq.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_298 = or(_in_d_bits_T_295, _in_d_bits_T_296)
node _in_d_bits_T_299 = or(_in_d_bits_T_298, _in_d_bits_T_297)
wire _in_d_bits_WIRE_83 : UInt<3>
connect _in_d_bits_WIRE_83, _in_d_bits_T_299
connect _in_d_bits_WIRE_77.sink, _in_d_bits_WIRE_83
node _in_d_bits_T_300 = mux(muxState_15[0], d_d_7.bits.source, UInt<1>(0h0))
node _in_d_bits_T_301 = mux(muxState_15[1], q_14.io.deq.bits.source, UInt<1>(0h0))
node _in_d_bits_T_302 = mux(muxState_15[2], q_15.io.deq.bits.source, UInt<1>(0h0))
node _in_d_bits_T_303 = or(_in_d_bits_T_300, _in_d_bits_T_301)
node _in_d_bits_T_304 = or(_in_d_bits_T_303, _in_d_bits_T_302)
wire _in_d_bits_WIRE_84 : UInt<4>
connect _in_d_bits_WIRE_84, _in_d_bits_T_304
connect _in_d_bits_WIRE_77.source, _in_d_bits_WIRE_84
node _in_d_bits_T_305 = mux(muxState_15[0], d_d_7.bits.size, UInt<1>(0h0))
node _in_d_bits_T_306 = mux(muxState_15[1], q_14.io.deq.bits.size, UInt<1>(0h0))
node _in_d_bits_T_307 = mux(muxState_15[2], q_15.io.deq.bits.size, UInt<1>(0h0))
node _in_d_bits_T_308 = or(_in_d_bits_T_305, _in_d_bits_T_306)
node _in_d_bits_T_309 = or(_in_d_bits_T_308, _in_d_bits_T_307)
wire _in_d_bits_WIRE_85 : UInt<3>
connect _in_d_bits_WIRE_85, _in_d_bits_T_309
connect _in_d_bits_WIRE_77.size, _in_d_bits_WIRE_85
node _in_d_bits_T_310 = mux(muxState_15[0], d_d_7.bits.param, UInt<1>(0h0))
node _in_d_bits_T_311 = mux(muxState_15[1], q_14.io.deq.bits.param, UInt<1>(0h0))
node _in_d_bits_T_312 = mux(muxState_15[2], q_15.io.deq.bits.param, UInt<1>(0h0))
node _in_d_bits_T_313 = or(_in_d_bits_T_310, _in_d_bits_T_311)
node _in_d_bits_T_314 = or(_in_d_bits_T_313, _in_d_bits_T_312)
wire _in_d_bits_WIRE_86 : UInt<2>
connect _in_d_bits_WIRE_86, _in_d_bits_T_314
connect _in_d_bits_WIRE_77.param, _in_d_bits_WIRE_86
node _in_d_bits_T_315 = mux(muxState_15[0], d_d_7.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_316 = mux(muxState_15[1], q_14.io.deq.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_317 = mux(muxState_15[2], q_15.io.deq.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_318 = or(_in_d_bits_T_315, _in_d_bits_T_316)
node _in_d_bits_T_319 = or(_in_d_bits_T_318, _in_d_bits_T_317)
wire _in_d_bits_WIRE_87 : UInt<3>
connect _in_d_bits_WIRE_87, _in_d_bits_T_319
connect _in_d_bits_WIRE_77.opcode, _in_d_bits_WIRE_87
connect in_d_7.bits.corrupt, _in_d_bits_WIRE_77.corrupt
connect in_d_7.bits.data, _in_d_bits_WIRE_77.data
connect in_d_7.bits.denied, _in_d_bits_WIRE_77.denied
connect in_d_7.bits.sink, _in_d_bits_WIRE_77.sink
connect in_d_7.bits.source, _in_d_bits_WIRE_77.source
connect in_d_7.bits.size, _in_d_bits_WIRE_77.size
connect in_d_7.bits.param, _in_d_bits_WIRE_77.param
connect in_d_7.bits.opcode, _in_d_bits_WIRE_77.opcode
connect nodeIn_7.b.valid, UInt<1>(0h0)
wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_60.bits.corrupt, UInt<1>(0h0)
connect _WIRE_60.bits.data, UInt<64>(0h0)
connect _WIRE_60.bits.address, UInt<32>(0h0)
connect _WIRE_60.bits.source, UInt<5>(0h0)
connect _WIRE_60.bits.size, UInt<3>(0h0)
connect _WIRE_60.bits.param, UInt<3>(0h0)
connect _WIRE_60.bits.opcode, UInt<3>(0h0)
connect _WIRE_60.valid, UInt<1>(0h0)
connect _WIRE_60.ready, UInt<1>(0h0)
wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_61.bits, _WIRE_60.bits
connect _WIRE_61.valid, _WIRE_60.valid
connect _WIRE_61.ready, _WIRE_60.ready
connect _WIRE_61.valid, UInt<1>(0h0)
wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_62.bits.sink, UInt<1>(0h0)
connect _WIRE_62.valid, UInt<1>(0h0)
connect _WIRE_62.ready, UInt<1>(0h0)
wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_63.bits, _WIRE_62.bits
connect _WIRE_63.valid, _WIRE_62.valid
connect _WIRE_63.ready, _WIRE_62.ready
connect _WIRE_63.valid, UInt<1>(0h0) | module TLCacheCork( // @[CacheCork.scala:42:9]
input clock, // @[CacheCork.scala:42:9]
input reset, // @[CacheCork.scala:42:9]
output auto_in_7_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_7_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_7_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_7_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_7_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_7_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_7_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_7_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_7_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_7_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_7_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_7_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_7_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_7_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_7_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_7_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_7_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_7_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_7_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_7_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_7_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_7_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_7_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_7_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_7_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_7_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_7_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_7_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_7_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_7_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_7_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_6_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_6_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_6_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_6_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_6_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_6_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_6_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_6_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_6_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_6_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_6_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_6_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_6_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_6_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_6_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_6_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_6_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_6_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_6_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_6_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_6_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_6_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_6_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_6_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_6_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_6_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_6_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_6_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_6_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_6_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_6_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_5_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_5_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_5_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_5_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_5_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_5_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_5_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_5_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_5_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_5_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_5_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_5_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_5_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_5_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_5_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_5_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_5_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_5_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_5_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_5_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_5_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_5_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_5_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_5_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_5_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_5_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_5_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_5_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_5_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_5_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_5_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_4_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_4_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_4_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_4_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_4_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_4_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_4_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_4_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_4_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_4_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_4_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_4_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_4_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_4_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_4_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_4_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_4_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_4_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_4_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_4_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_4_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_4_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_4_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_4_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_4_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_4_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_4_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_4_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_4_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_4_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_4_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_3_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_3_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_3_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_3_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_3_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_3_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_3_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_3_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_3_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_3_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_3_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_3_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_3_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_3_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_3_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_3_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_3_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_3_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_3_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_3_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_3_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_2_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_2_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_2_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_2_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_2_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_2_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_2_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_2_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_2_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_2_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_2_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_2_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_1_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_1_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_1_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_1_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_1_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_1_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_0_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_0_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_0_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_0_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_0_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_0_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_0_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_7_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_7_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_7_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_7_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_7_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_7_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_7_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_7_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_7_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_7_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_7_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_7_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_7_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_7_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_7_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_7_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_7_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_7_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_7_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_7_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_6_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_6_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_6_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_6_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_6_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_6_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_6_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_6_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_6_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_6_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_6_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_6_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_6_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_6_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_6_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_6_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_6_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_6_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_6_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_6_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_5_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_5_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_5_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_5_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_5_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_5_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_5_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_5_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_5_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_5_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_5_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_5_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_5_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_5_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_5_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_5_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_5_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_5_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_5_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_5_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_4_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_4_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_4_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_4_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_4_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_4_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_4_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_4_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_4_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_4_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_4_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_4_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_4_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_4_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_4_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_4_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_4_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_4_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_4_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_4_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_3_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_3_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_3_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_3_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_3_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_3_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_3_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_3_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_3_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_3_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_3_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_3_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_3_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_3_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_2_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_2_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_2_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_2_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_2_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_2_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire _q_15_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _q_15_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _q_15_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _q_15_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _q_15_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [2:0] _q_15_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _q_15_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire [63:0] _q_15_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _q_15_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _q_14_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _q_14_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _q_14_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _q_14_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _q_14_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [2:0] _q_14_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _q_14_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire [63:0] _q_14_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _q_14_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _pool_7_io_alloc_valid; // @[CacheCork.scala:127:26]
wire [2:0] _pool_7_io_alloc_bits; // @[CacheCork.scala:127:26]
wire _q_13_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _q_13_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _q_13_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _q_13_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _q_13_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [2:0] _q_13_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _q_13_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire [63:0] _q_13_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _q_13_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _q_12_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _q_12_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _q_12_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _q_12_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _q_12_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [2:0] _q_12_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _q_12_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire [63:0] _q_12_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _q_12_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _pool_6_io_alloc_valid; // @[CacheCork.scala:127:26]
wire [2:0] _pool_6_io_alloc_bits; // @[CacheCork.scala:127:26]
wire _q_11_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _q_11_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _q_11_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _q_11_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _q_11_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [2:0] _q_11_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _q_11_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire [63:0] _q_11_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _q_11_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _q_10_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _q_10_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _q_10_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _q_10_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _q_10_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [2:0] _q_10_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _q_10_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire [63:0] _q_10_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _q_10_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _pool_5_io_alloc_valid; // @[CacheCork.scala:127:26]
wire [2:0] _pool_5_io_alloc_bits; // @[CacheCork.scala:127:26]
wire _q_9_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _q_9_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _q_9_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _q_9_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _q_9_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [2:0] _q_9_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _q_9_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire [63:0] _q_9_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _q_9_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _q_8_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _q_8_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _q_8_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _q_8_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _q_8_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [2:0] _q_8_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _q_8_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire [63:0] _q_8_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _q_8_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _pool_4_io_alloc_valid; // @[CacheCork.scala:127:26]
wire [2:0] _pool_4_io_alloc_bits; // @[CacheCork.scala:127:26]
wire _q_7_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _q_7_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _q_7_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _q_7_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _q_7_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [2:0] _q_7_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _q_7_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire [63:0] _q_7_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _q_7_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _q_6_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _q_6_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _q_6_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _q_6_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _q_6_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [2:0] _q_6_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _q_6_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire [63:0] _q_6_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _q_6_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _pool_3_io_alloc_valid; // @[CacheCork.scala:127:26]
wire [2:0] _pool_3_io_alloc_bits; // @[CacheCork.scala:127:26]
wire _q_5_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _q_5_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _q_5_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _q_5_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _q_5_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [2:0] _q_5_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _q_5_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire [63:0] _q_5_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _q_5_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _q_4_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _q_4_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _q_4_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _q_4_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _q_4_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [2:0] _q_4_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _q_4_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire [63:0] _q_4_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _q_4_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _pool_2_io_alloc_valid; // @[CacheCork.scala:127:26]
wire [2:0] _pool_2_io_alloc_bits; // @[CacheCork.scala:127:26]
wire _q_3_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _q_3_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _q_3_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _q_3_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _q_3_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [2:0] _q_3_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _q_3_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire [63:0] _q_3_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _q_3_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _q_2_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _q_2_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _q_2_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _q_2_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _q_2_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [2:0] _q_2_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _q_2_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire [63:0] _q_2_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _q_2_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _pool_1_io_alloc_valid; // @[CacheCork.scala:127:26]
wire [2:0] _pool_1_io_alloc_bits; // @[CacheCork.scala:127:26]
wire _q_1_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _q_1_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _q_1_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _q_1_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _q_1_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [2:0] _q_1_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _q_1_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire [63:0] _q_1_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _q_1_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _q_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _q_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [2:0] _q_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _q_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire [63:0] _q_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _pool_io_alloc_valid; // @[CacheCork.scala:127:26]
wire [2:0] _pool_io_alloc_bits; // @[CacheCork.scala:127:26]
wire auto_in_7_a_valid_0 = auto_in_7_a_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_7_a_bits_opcode_0 = auto_in_7_a_bits_opcode; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_7_a_bits_param_0 = auto_in_7_a_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_7_a_bits_size_0 = auto_in_7_a_bits_size; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_7_a_bits_source_0 = auto_in_7_a_bits_source; // @[CacheCork.scala:42:9]
wire [31:0] auto_in_7_a_bits_address_0 = auto_in_7_a_bits_address; // @[CacheCork.scala:42:9]
wire [7:0] auto_in_7_a_bits_mask_0 = auto_in_7_a_bits_mask; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_7_a_bits_data_0 = auto_in_7_a_bits_data; // @[CacheCork.scala:42:9]
wire auto_in_7_a_bits_corrupt_0 = auto_in_7_a_bits_corrupt; // @[CacheCork.scala:42:9]
wire auto_in_7_c_valid_0 = auto_in_7_c_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_7_c_bits_opcode_0 = auto_in_7_c_bits_opcode; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_7_c_bits_param_0 = auto_in_7_c_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_7_c_bits_size_0 = auto_in_7_c_bits_size; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_7_c_bits_source_0 = auto_in_7_c_bits_source; // @[CacheCork.scala:42:9]
wire [31:0] auto_in_7_c_bits_address_0 = auto_in_7_c_bits_address; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_7_c_bits_data_0 = auto_in_7_c_bits_data; // @[CacheCork.scala:42:9]
wire auto_in_7_c_bits_corrupt_0 = auto_in_7_c_bits_corrupt; // @[CacheCork.scala:42:9]
wire auto_in_7_d_ready_0 = auto_in_7_d_ready; // @[CacheCork.scala:42:9]
wire auto_in_7_e_valid_0 = auto_in_7_e_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_7_e_bits_sink_0 = auto_in_7_e_bits_sink; // @[CacheCork.scala:42:9]
wire auto_in_6_a_valid_0 = auto_in_6_a_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_6_a_bits_opcode_0 = auto_in_6_a_bits_opcode; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_6_a_bits_param_0 = auto_in_6_a_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_6_a_bits_size_0 = auto_in_6_a_bits_size; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_6_a_bits_source_0 = auto_in_6_a_bits_source; // @[CacheCork.scala:42:9]
wire [31:0] auto_in_6_a_bits_address_0 = auto_in_6_a_bits_address; // @[CacheCork.scala:42:9]
wire [7:0] auto_in_6_a_bits_mask_0 = auto_in_6_a_bits_mask; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_6_a_bits_data_0 = auto_in_6_a_bits_data; // @[CacheCork.scala:42:9]
wire auto_in_6_a_bits_corrupt_0 = auto_in_6_a_bits_corrupt; // @[CacheCork.scala:42:9]
wire auto_in_6_c_valid_0 = auto_in_6_c_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_6_c_bits_opcode_0 = auto_in_6_c_bits_opcode; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_6_c_bits_param_0 = auto_in_6_c_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_6_c_bits_size_0 = auto_in_6_c_bits_size; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_6_c_bits_source_0 = auto_in_6_c_bits_source; // @[CacheCork.scala:42:9]
wire [31:0] auto_in_6_c_bits_address_0 = auto_in_6_c_bits_address; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_6_c_bits_data_0 = auto_in_6_c_bits_data; // @[CacheCork.scala:42:9]
wire auto_in_6_c_bits_corrupt_0 = auto_in_6_c_bits_corrupt; // @[CacheCork.scala:42:9]
wire auto_in_6_d_ready_0 = auto_in_6_d_ready; // @[CacheCork.scala:42:9]
wire auto_in_6_e_valid_0 = auto_in_6_e_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_6_e_bits_sink_0 = auto_in_6_e_bits_sink; // @[CacheCork.scala:42:9]
wire auto_in_5_a_valid_0 = auto_in_5_a_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_5_a_bits_opcode_0 = auto_in_5_a_bits_opcode; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_5_a_bits_param_0 = auto_in_5_a_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_5_a_bits_size_0 = auto_in_5_a_bits_size; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_5_a_bits_source_0 = auto_in_5_a_bits_source; // @[CacheCork.scala:42:9]
wire [31:0] auto_in_5_a_bits_address_0 = auto_in_5_a_bits_address; // @[CacheCork.scala:42:9]
wire [7:0] auto_in_5_a_bits_mask_0 = auto_in_5_a_bits_mask; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_5_a_bits_data_0 = auto_in_5_a_bits_data; // @[CacheCork.scala:42:9]
wire auto_in_5_a_bits_corrupt_0 = auto_in_5_a_bits_corrupt; // @[CacheCork.scala:42:9]
wire auto_in_5_c_valid_0 = auto_in_5_c_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_5_c_bits_opcode_0 = auto_in_5_c_bits_opcode; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_5_c_bits_param_0 = auto_in_5_c_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_5_c_bits_size_0 = auto_in_5_c_bits_size; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_5_c_bits_source_0 = auto_in_5_c_bits_source; // @[CacheCork.scala:42:9]
wire [31:0] auto_in_5_c_bits_address_0 = auto_in_5_c_bits_address; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_5_c_bits_data_0 = auto_in_5_c_bits_data; // @[CacheCork.scala:42:9]
wire auto_in_5_c_bits_corrupt_0 = auto_in_5_c_bits_corrupt; // @[CacheCork.scala:42:9]
wire auto_in_5_d_ready_0 = auto_in_5_d_ready; // @[CacheCork.scala:42:9]
wire auto_in_5_e_valid_0 = auto_in_5_e_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_5_e_bits_sink_0 = auto_in_5_e_bits_sink; // @[CacheCork.scala:42:9]
wire auto_in_4_a_valid_0 = auto_in_4_a_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_4_a_bits_opcode_0 = auto_in_4_a_bits_opcode; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_4_a_bits_param_0 = auto_in_4_a_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_4_a_bits_size_0 = auto_in_4_a_bits_size; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_4_a_bits_source_0 = auto_in_4_a_bits_source; // @[CacheCork.scala:42:9]
wire [31:0] auto_in_4_a_bits_address_0 = auto_in_4_a_bits_address; // @[CacheCork.scala:42:9]
wire [7:0] auto_in_4_a_bits_mask_0 = auto_in_4_a_bits_mask; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_4_a_bits_data_0 = auto_in_4_a_bits_data; // @[CacheCork.scala:42:9]
wire auto_in_4_a_bits_corrupt_0 = auto_in_4_a_bits_corrupt; // @[CacheCork.scala:42:9]
wire auto_in_4_c_valid_0 = auto_in_4_c_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_4_c_bits_opcode_0 = auto_in_4_c_bits_opcode; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_4_c_bits_param_0 = auto_in_4_c_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_4_c_bits_size_0 = auto_in_4_c_bits_size; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_4_c_bits_source_0 = auto_in_4_c_bits_source; // @[CacheCork.scala:42:9]
wire [31:0] auto_in_4_c_bits_address_0 = auto_in_4_c_bits_address; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_4_c_bits_data_0 = auto_in_4_c_bits_data; // @[CacheCork.scala:42:9]
wire auto_in_4_c_bits_corrupt_0 = auto_in_4_c_bits_corrupt; // @[CacheCork.scala:42:9]
wire auto_in_4_d_ready_0 = auto_in_4_d_ready; // @[CacheCork.scala:42:9]
wire auto_in_4_e_valid_0 = auto_in_4_e_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_4_e_bits_sink_0 = auto_in_4_e_bits_sink; // @[CacheCork.scala:42:9]
wire auto_in_3_a_valid_0 = auto_in_3_a_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_3_a_bits_opcode_0 = auto_in_3_a_bits_opcode; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_3_a_bits_param_0 = auto_in_3_a_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_3_a_bits_size_0 = auto_in_3_a_bits_size; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_3_a_bits_source_0 = auto_in_3_a_bits_source; // @[CacheCork.scala:42:9]
wire [31:0] auto_in_3_a_bits_address_0 = auto_in_3_a_bits_address; // @[CacheCork.scala:42:9]
wire [7:0] auto_in_3_a_bits_mask_0 = auto_in_3_a_bits_mask; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_3_a_bits_data_0 = auto_in_3_a_bits_data; // @[CacheCork.scala:42:9]
wire auto_in_3_a_bits_corrupt_0 = auto_in_3_a_bits_corrupt; // @[CacheCork.scala:42:9]
wire auto_in_3_c_valid_0 = auto_in_3_c_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_3_c_bits_opcode_0 = auto_in_3_c_bits_opcode; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_3_c_bits_param_0 = auto_in_3_c_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_3_c_bits_size_0 = auto_in_3_c_bits_size; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_3_c_bits_source_0 = auto_in_3_c_bits_source; // @[CacheCork.scala:42:9]
wire [31:0] auto_in_3_c_bits_address_0 = auto_in_3_c_bits_address; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_3_c_bits_data_0 = auto_in_3_c_bits_data; // @[CacheCork.scala:42:9]
wire auto_in_3_c_bits_corrupt_0 = auto_in_3_c_bits_corrupt; // @[CacheCork.scala:42:9]
wire auto_in_3_d_ready_0 = auto_in_3_d_ready; // @[CacheCork.scala:42:9]
wire auto_in_3_e_valid_0 = auto_in_3_e_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_3_e_bits_sink_0 = auto_in_3_e_bits_sink; // @[CacheCork.scala:42:9]
wire auto_in_2_a_valid_0 = auto_in_2_a_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_2_a_bits_opcode_0 = auto_in_2_a_bits_opcode; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_2_a_bits_param_0 = auto_in_2_a_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_2_a_bits_size_0 = auto_in_2_a_bits_size; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_2_a_bits_source_0 = auto_in_2_a_bits_source; // @[CacheCork.scala:42:9]
wire [31:0] auto_in_2_a_bits_address_0 = auto_in_2_a_bits_address; // @[CacheCork.scala:42:9]
wire [7:0] auto_in_2_a_bits_mask_0 = auto_in_2_a_bits_mask; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_2_a_bits_data_0 = auto_in_2_a_bits_data; // @[CacheCork.scala:42:9]
wire auto_in_2_a_bits_corrupt_0 = auto_in_2_a_bits_corrupt; // @[CacheCork.scala:42:9]
wire auto_in_2_c_valid_0 = auto_in_2_c_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_2_c_bits_opcode_0 = auto_in_2_c_bits_opcode; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_2_c_bits_param_0 = auto_in_2_c_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_2_c_bits_size_0 = auto_in_2_c_bits_size; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_2_c_bits_source_0 = auto_in_2_c_bits_source; // @[CacheCork.scala:42:9]
wire [31:0] auto_in_2_c_bits_address_0 = auto_in_2_c_bits_address; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_2_c_bits_data_0 = auto_in_2_c_bits_data; // @[CacheCork.scala:42:9]
wire auto_in_2_c_bits_corrupt_0 = auto_in_2_c_bits_corrupt; // @[CacheCork.scala:42:9]
wire auto_in_2_d_ready_0 = auto_in_2_d_ready; // @[CacheCork.scala:42:9]
wire auto_in_2_e_valid_0 = auto_in_2_e_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_2_e_bits_sink_0 = auto_in_2_e_bits_sink; // @[CacheCork.scala:42:9]
wire auto_in_1_a_valid_0 = auto_in_1_a_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_1_a_bits_opcode_0 = auto_in_1_a_bits_opcode; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_1_a_bits_param_0 = auto_in_1_a_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_1_a_bits_size_0 = auto_in_1_a_bits_size; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_1_a_bits_source_0 = auto_in_1_a_bits_source; // @[CacheCork.scala:42:9]
wire [31:0] auto_in_1_a_bits_address_0 = auto_in_1_a_bits_address; // @[CacheCork.scala:42:9]
wire [7:0] auto_in_1_a_bits_mask_0 = auto_in_1_a_bits_mask; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_1_a_bits_data_0 = auto_in_1_a_bits_data; // @[CacheCork.scala:42:9]
wire auto_in_1_a_bits_corrupt_0 = auto_in_1_a_bits_corrupt; // @[CacheCork.scala:42:9]
wire auto_in_1_c_valid_0 = auto_in_1_c_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_1_c_bits_opcode_0 = auto_in_1_c_bits_opcode; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_1_c_bits_param_0 = auto_in_1_c_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_1_c_bits_size_0 = auto_in_1_c_bits_size; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_1_c_bits_source_0 = auto_in_1_c_bits_source; // @[CacheCork.scala:42:9]
wire [31:0] auto_in_1_c_bits_address_0 = auto_in_1_c_bits_address; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_1_c_bits_data_0 = auto_in_1_c_bits_data; // @[CacheCork.scala:42:9]
wire auto_in_1_c_bits_corrupt_0 = auto_in_1_c_bits_corrupt; // @[CacheCork.scala:42:9]
wire auto_in_1_d_ready_0 = auto_in_1_d_ready; // @[CacheCork.scala:42:9]
wire auto_in_1_e_valid_0 = auto_in_1_e_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_1_e_bits_sink_0 = auto_in_1_e_bits_sink; // @[CacheCork.scala:42:9]
wire auto_in_0_a_valid_0 = auto_in_0_a_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_0_a_bits_opcode_0 = auto_in_0_a_bits_opcode; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_0_a_bits_param_0 = auto_in_0_a_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_0_a_bits_size_0 = auto_in_0_a_bits_size; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_0_a_bits_source_0 = auto_in_0_a_bits_source; // @[CacheCork.scala:42:9]
wire [31:0] auto_in_0_a_bits_address_0 = auto_in_0_a_bits_address; // @[CacheCork.scala:42:9]
wire [7:0] auto_in_0_a_bits_mask_0 = auto_in_0_a_bits_mask; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_0_a_bits_data_0 = auto_in_0_a_bits_data; // @[CacheCork.scala:42:9]
wire auto_in_0_a_bits_corrupt_0 = auto_in_0_a_bits_corrupt; // @[CacheCork.scala:42:9]
wire auto_in_0_c_valid_0 = auto_in_0_c_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_0_c_bits_opcode_0 = auto_in_0_c_bits_opcode; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_0_c_bits_param_0 = auto_in_0_c_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_0_c_bits_size_0 = auto_in_0_c_bits_size; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_0_c_bits_source_0 = auto_in_0_c_bits_source; // @[CacheCork.scala:42:9]
wire [31:0] auto_in_0_c_bits_address_0 = auto_in_0_c_bits_address; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_0_c_bits_data_0 = auto_in_0_c_bits_data; // @[CacheCork.scala:42:9]
wire auto_in_0_c_bits_corrupt_0 = auto_in_0_c_bits_corrupt; // @[CacheCork.scala:42:9]
wire auto_in_0_d_ready_0 = auto_in_0_d_ready; // @[CacheCork.scala:42:9]
wire auto_in_0_e_valid_0 = auto_in_0_e_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_0_e_bits_sink_0 = auto_in_0_e_bits_sink; // @[CacheCork.scala:42:9]
wire auto_out_7_a_ready_0 = auto_out_7_a_ready; // @[CacheCork.scala:42:9]
wire auto_out_7_d_valid_0 = auto_out_7_d_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_7_d_bits_opcode_0 = auto_out_7_d_bits_opcode; // @[CacheCork.scala:42:9]
wire [1:0] auto_out_7_d_bits_param_0 = auto_out_7_d_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_7_d_bits_size_0 = auto_out_7_d_bits_size; // @[CacheCork.scala:42:9]
wire [4:0] auto_out_7_d_bits_source_0 = auto_out_7_d_bits_source; // @[CacheCork.scala:42:9]
wire auto_out_7_d_bits_sink_0 = auto_out_7_d_bits_sink; // @[CacheCork.scala:42:9]
wire auto_out_7_d_bits_denied_0 = auto_out_7_d_bits_denied; // @[CacheCork.scala:42:9]
wire [63:0] auto_out_7_d_bits_data_0 = auto_out_7_d_bits_data; // @[CacheCork.scala:42:9]
wire auto_out_7_d_bits_corrupt_0 = auto_out_7_d_bits_corrupt; // @[CacheCork.scala:42:9]
wire auto_out_6_a_ready_0 = auto_out_6_a_ready; // @[CacheCork.scala:42:9]
wire auto_out_6_d_valid_0 = auto_out_6_d_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_6_d_bits_opcode_0 = auto_out_6_d_bits_opcode; // @[CacheCork.scala:42:9]
wire [1:0] auto_out_6_d_bits_param_0 = auto_out_6_d_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_6_d_bits_size_0 = auto_out_6_d_bits_size; // @[CacheCork.scala:42:9]
wire [4:0] auto_out_6_d_bits_source_0 = auto_out_6_d_bits_source; // @[CacheCork.scala:42:9]
wire auto_out_6_d_bits_sink_0 = auto_out_6_d_bits_sink; // @[CacheCork.scala:42:9]
wire auto_out_6_d_bits_denied_0 = auto_out_6_d_bits_denied; // @[CacheCork.scala:42:9]
wire [63:0] auto_out_6_d_bits_data_0 = auto_out_6_d_bits_data; // @[CacheCork.scala:42:9]
wire auto_out_6_d_bits_corrupt_0 = auto_out_6_d_bits_corrupt; // @[CacheCork.scala:42:9]
wire auto_out_5_a_ready_0 = auto_out_5_a_ready; // @[CacheCork.scala:42:9]
wire auto_out_5_d_valid_0 = auto_out_5_d_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_5_d_bits_opcode_0 = auto_out_5_d_bits_opcode; // @[CacheCork.scala:42:9]
wire [1:0] auto_out_5_d_bits_param_0 = auto_out_5_d_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_5_d_bits_size_0 = auto_out_5_d_bits_size; // @[CacheCork.scala:42:9]
wire [4:0] auto_out_5_d_bits_source_0 = auto_out_5_d_bits_source; // @[CacheCork.scala:42:9]
wire auto_out_5_d_bits_sink_0 = auto_out_5_d_bits_sink; // @[CacheCork.scala:42:9]
wire auto_out_5_d_bits_denied_0 = auto_out_5_d_bits_denied; // @[CacheCork.scala:42:9]
wire [63:0] auto_out_5_d_bits_data_0 = auto_out_5_d_bits_data; // @[CacheCork.scala:42:9]
wire auto_out_5_d_bits_corrupt_0 = auto_out_5_d_bits_corrupt; // @[CacheCork.scala:42:9]
wire auto_out_4_a_ready_0 = auto_out_4_a_ready; // @[CacheCork.scala:42:9]
wire auto_out_4_d_valid_0 = auto_out_4_d_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_4_d_bits_opcode_0 = auto_out_4_d_bits_opcode; // @[CacheCork.scala:42:9]
wire [1:0] auto_out_4_d_bits_param_0 = auto_out_4_d_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_4_d_bits_size_0 = auto_out_4_d_bits_size; // @[CacheCork.scala:42:9]
wire [4:0] auto_out_4_d_bits_source_0 = auto_out_4_d_bits_source; // @[CacheCork.scala:42:9]
wire auto_out_4_d_bits_sink_0 = auto_out_4_d_bits_sink; // @[CacheCork.scala:42:9]
wire auto_out_4_d_bits_denied_0 = auto_out_4_d_bits_denied; // @[CacheCork.scala:42:9]
wire [63:0] auto_out_4_d_bits_data_0 = auto_out_4_d_bits_data; // @[CacheCork.scala:42:9]
wire auto_out_4_d_bits_corrupt_0 = auto_out_4_d_bits_corrupt; // @[CacheCork.scala:42:9]
wire auto_out_3_a_ready_0 = auto_out_3_a_ready; // @[CacheCork.scala:42:9]
wire auto_out_3_d_valid_0 = auto_out_3_d_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_3_d_bits_opcode_0 = auto_out_3_d_bits_opcode; // @[CacheCork.scala:42:9]
wire [1:0] auto_out_3_d_bits_param_0 = auto_out_3_d_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_3_d_bits_size_0 = auto_out_3_d_bits_size; // @[CacheCork.scala:42:9]
wire [4:0] auto_out_3_d_bits_source_0 = auto_out_3_d_bits_source; // @[CacheCork.scala:42:9]
wire auto_out_3_d_bits_sink_0 = auto_out_3_d_bits_sink; // @[CacheCork.scala:42:9]
wire auto_out_3_d_bits_denied_0 = auto_out_3_d_bits_denied; // @[CacheCork.scala:42:9]
wire [63:0] auto_out_3_d_bits_data_0 = auto_out_3_d_bits_data; // @[CacheCork.scala:42:9]
wire auto_out_3_d_bits_corrupt_0 = auto_out_3_d_bits_corrupt; // @[CacheCork.scala:42:9]
wire auto_out_2_a_ready_0 = auto_out_2_a_ready; // @[CacheCork.scala:42:9]
wire auto_out_2_d_valid_0 = auto_out_2_d_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_2_d_bits_opcode_0 = auto_out_2_d_bits_opcode; // @[CacheCork.scala:42:9]
wire [1:0] auto_out_2_d_bits_param_0 = auto_out_2_d_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_2_d_bits_size_0 = auto_out_2_d_bits_size; // @[CacheCork.scala:42:9]
wire [4:0] auto_out_2_d_bits_source_0 = auto_out_2_d_bits_source; // @[CacheCork.scala:42:9]
wire auto_out_2_d_bits_sink_0 = auto_out_2_d_bits_sink; // @[CacheCork.scala:42:9]
wire auto_out_2_d_bits_denied_0 = auto_out_2_d_bits_denied; // @[CacheCork.scala:42:9]
wire [63:0] auto_out_2_d_bits_data_0 = auto_out_2_d_bits_data; // @[CacheCork.scala:42:9]
wire auto_out_2_d_bits_corrupt_0 = auto_out_2_d_bits_corrupt; // @[CacheCork.scala:42:9]
wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[CacheCork.scala:42:9]
wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[CacheCork.scala:42:9]
wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[CacheCork.scala:42:9]
wire [4:0] auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[CacheCork.scala:42:9]
wire auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[CacheCork.scala:42:9]
wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[CacheCork.scala:42:9]
wire [63:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[CacheCork.scala:42:9]
wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[CacheCork.scala:42:9]
wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[CacheCork.scala:42:9]
wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[CacheCork.scala:42:9]
wire [1:0] auto_out_0_d_bits_param_0 = auto_out_0_d_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[CacheCork.scala:42:9]
wire [4:0] auto_out_0_d_bits_source_0 = auto_out_0_d_bits_source; // @[CacheCork.scala:42:9]
wire auto_out_0_d_bits_sink_0 = auto_out_0_d_bits_sink; // @[CacheCork.scala:42:9]
wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[CacheCork.scala:42:9]
wire [63:0] auto_out_0_d_bits_data_0 = auto_out_0_d_bits_data; // @[CacheCork.scala:42:9]
wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[CacheCork.scala:42:9]
wire auto_in_7_b_ready = 1'h1; // @[CacheCork.scala:42:9]
wire auto_in_7_e_ready = 1'h1; // @[CacheCork.scala:42:9]
wire auto_in_6_b_ready = 1'h1; // @[CacheCork.scala:42:9]
wire auto_in_6_e_ready = 1'h1; // @[CacheCork.scala:42:9]
wire auto_in_5_b_ready = 1'h1; // @[CacheCork.scala:42:9]
wire auto_in_5_e_ready = 1'h1; // @[CacheCork.scala:42:9]
wire auto_in_4_b_ready = 1'h1; // @[CacheCork.scala:42:9]
wire auto_in_4_e_ready = 1'h1; // @[CacheCork.scala:42:9]
wire auto_in_3_b_ready = 1'h1; // @[CacheCork.scala:42:9]
wire auto_in_3_e_ready = 1'h1; // @[CacheCork.scala:42:9]
wire auto_in_2_b_ready = 1'h1; // @[CacheCork.scala:42:9]
wire auto_in_2_e_ready = 1'h1; // @[CacheCork.scala:42:9]
wire auto_in_1_b_ready = 1'h1; // @[CacheCork.scala:42:9]
wire auto_in_1_e_ready = 1'h1; // @[CacheCork.scala:42:9]
wire auto_in_0_b_ready = 1'h1; // @[CacheCork.scala:42:9]
wire auto_in_0_e_ready = 1'h1; // @[CacheCork.scala:42:9]
wire nodeIn_b_ready = 1'h1; // @[MixedNode.scala:551:17]
wire nodeIn_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire nodeIn_1_b_ready = 1'h1; // @[MixedNode.scala:551:17]
wire nodeIn_1_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire nodeIn_2_b_ready = 1'h1; // @[MixedNode.scala:551:17]
wire nodeIn_2_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire nodeIn_3_b_ready = 1'h1; // @[MixedNode.scala:551:17]
wire nodeIn_3_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire nodeIn_4_b_ready = 1'h1; // @[MixedNode.scala:551:17]
wire nodeIn_4_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire nodeIn_5_b_ready = 1'h1; // @[MixedNode.scala:551:17]
wire nodeIn_5_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire nodeIn_6_b_ready = 1'h1; // @[MixedNode.scala:551:17]
wire nodeIn_6_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire nodeIn_7_b_ready = 1'h1; // @[MixedNode.scala:551:17]
wire nodeIn_7_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire _c_a_bits_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _c_a_bits_legal_T_8 = 1'h1; // @[Parameters.scala:137:59]
wire _aWOk_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _dWHeld_T = 1'h1; // @[CacheCork.scala:151:25]
wire opdata = 1'h1; // @[Edges.scala:92:28]
wire _c_a_bits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _c_a_bits_legal_T_18 = 1'h1; // @[Parameters.scala:137:59]
wire _aWOk_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire _dWHeld_T_1 = 1'h1; // @[CacheCork.scala:151:25]
wire opdata_3 = 1'h1; // @[Edges.scala:92:28]
wire _c_a_bits_legal_T_20 = 1'h1; // @[Parameters.scala:92:28]
wire _c_a_bits_legal_T_28 = 1'h1; // @[Parameters.scala:137:59]
wire _aWOk_T_14 = 1'h1; // @[Parameters.scala:137:59]
wire _dWHeld_T_2 = 1'h1; // @[CacheCork.scala:151:25]
wire opdata_6 = 1'h1; // @[Edges.scala:92:28]
wire _c_a_bits_legal_T_30 = 1'h1; // @[Parameters.scala:92:28]
wire _c_a_bits_legal_T_38 = 1'h1; // @[Parameters.scala:137:59]
wire _aWOk_T_19 = 1'h1; // @[Parameters.scala:137:59]
wire _dWHeld_T_3 = 1'h1; // @[CacheCork.scala:151:25]
wire opdata_9 = 1'h1; // @[Edges.scala:92:28]
wire _c_a_bits_legal_T_40 = 1'h1; // @[Parameters.scala:92:28]
wire _c_a_bits_legal_T_48 = 1'h1; // @[Parameters.scala:137:59]
wire _aWOk_T_24 = 1'h1; // @[Parameters.scala:137:59]
wire _dWHeld_T_4 = 1'h1; // @[CacheCork.scala:151:25]
wire opdata_12 = 1'h1; // @[Edges.scala:92:28]
wire _c_a_bits_legal_T_50 = 1'h1; // @[Parameters.scala:92:28]
wire _c_a_bits_legal_T_58 = 1'h1; // @[Parameters.scala:137:59]
wire _aWOk_T_29 = 1'h1; // @[Parameters.scala:137:59]
wire _dWHeld_T_5 = 1'h1; // @[CacheCork.scala:151:25]
wire opdata_15 = 1'h1; // @[Edges.scala:92:28]
wire _c_a_bits_legal_T_60 = 1'h1; // @[Parameters.scala:92:28]
wire _c_a_bits_legal_T_68 = 1'h1; // @[Parameters.scala:137:59]
wire _aWOk_T_34 = 1'h1; // @[Parameters.scala:137:59]
wire _dWHeld_T_6 = 1'h1; // @[CacheCork.scala:151:25]
wire opdata_18 = 1'h1; // @[Edges.scala:92:28]
wire _c_a_bits_legal_T_70 = 1'h1; // @[Parameters.scala:92:28]
wire _c_a_bits_legal_T_78 = 1'h1; // @[Parameters.scala:137:59]
wire _aWOk_T_39 = 1'h1; // @[Parameters.scala:137:59]
wire _dWHeld_T_7 = 1'h1; // @[CacheCork.scala:151:25]
wire opdata_21 = 1'h1; // @[Edges.scala:92:28]
wire auto_in_7_b_valid = 1'h0; // @[CacheCork.scala:42:9]
wire auto_in_7_b_bits_corrupt = 1'h0; // @[CacheCork.scala:42:9]
wire auto_in_6_b_valid = 1'h0; // @[CacheCork.scala:42:9]
wire auto_in_6_b_bits_corrupt = 1'h0; // @[CacheCork.scala:42:9]
wire auto_in_5_b_valid = 1'h0; // @[CacheCork.scala:42:9]
wire auto_in_5_b_bits_corrupt = 1'h0; // @[CacheCork.scala:42:9]
wire auto_in_4_b_valid = 1'h0; // @[CacheCork.scala:42:9]
wire auto_in_4_b_bits_corrupt = 1'h0; // @[CacheCork.scala:42:9]
wire auto_in_3_b_valid = 1'h0; // @[CacheCork.scala:42:9]
wire auto_in_3_b_bits_corrupt = 1'h0; // @[CacheCork.scala:42:9]
wire auto_in_2_b_valid = 1'h0; // @[CacheCork.scala:42:9]
wire auto_in_2_b_bits_corrupt = 1'h0; // @[CacheCork.scala:42:9]
wire auto_in_1_b_valid = 1'h0; // @[CacheCork.scala:42:9]
wire auto_in_1_b_bits_corrupt = 1'h0; // @[CacheCork.scala:42:9]
wire auto_in_0_b_valid = 1'h0; // @[CacheCork.scala:42:9]
wire auto_in_0_b_bits_corrupt = 1'h0; // @[CacheCork.scala:42:9]
wire nodeIn_b_valid = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_1_b_valid = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_1_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_2_b_valid = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_2_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_3_b_valid = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_3_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_4_b_valid = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_4_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_5_b_valid = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_5_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_6_b_valid = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_6_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_7_b_valid = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_7_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire a_d_bits_denied = 1'h0; // @[CacheCork.scala:75:23]
wire a_d_bits_corrupt = 1'h0; // @[CacheCork.scala:75:23]
wire a_d_bits_d_denied = 1'h0; // @[Edges.scala:645:17]
wire a_d_bits_d_corrupt = 1'h0; // @[Edges.scala:645:17]
wire c_d_bits_denied = 1'h0; // @[CacheCork.scala:112:23]
wire c_d_bits_corrupt = 1'h0; // @[CacheCork.scala:112:23]
wire c_d_bits_d_denied = 1'h0; // @[Edges.scala:677:17]
wire c_d_bits_d_corrupt = 1'h0; // @[Edges.scala:677:17]
wire _bypass_T = 1'h0; // @[CacheCork.scala:150:57]
wire bypass = 1'h0; // @[CacheCork.scala:150:71]
wire _opdata_T = 1'h0; // @[Edges.scala:92:37]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire maskedBeats_1_1 = 1'h0; // @[Arbiter.scala:82:69]
wire maskedBeats_2 = 1'h0; // @[Arbiter.scala:82:69]
wire _state_WIRE_1_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1_2 = 1'h0; // @[Arbiter.scala:88:34]
wire a_d_1_bits_denied = 1'h0; // @[CacheCork.scala:75:23]
wire a_d_1_bits_corrupt = 1'h0; // @[CacheCork.scala:75:23]
wire a_d_bits_d_1_denied = 1'h0; // @[Edges.scala:645:17]
wire a_d_bits_d_1_corrupt = 1'h0; // @[Edges.scala:645:17]
wire c_d_1_bits_denied = 1'h0; // @[CacheCork.scala:112:23]
wire c_d_1_bits_corrupt = 1'h0; // @[CacheCork.scala:112:23]
wire c_d_bits_d_1_denied = 1'h0; // @[Edges.scala:677:17]
wire c_d_bits_d_1_corrupt = 1'h0; // @[Edges.scala:677:17]
wire _bypass_T_2 = 1'h0; // @[CacheCork.scala:150:57]
wire bypass_1 = 1'h0; // @[CacheCork.scala:150:71]
wire _opdata_T_2 = 1'h0; // @[Edges.scala:92:37]
wire _state_WIRE_2_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_2_1 = 1'h0; // @[Arbiter.scala:88:34]
wire maskedBeats_1_3 = 1'h0; // @[Arbiter.scala:82:69]
wire maskedBeats_2_1 = 1'h0; // @[Arbiter.scala:82:69]
wire _state_WIRE_3_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_3_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_3_2 = 1'h0; // @[Arbiter.scala:88:34]
wire a_d_2_bits_denied = 1'h0; // @[CacheCork.scala:75:23]
wire a_d_2_bits_corrupt = 1'h0; // @[CacheCork.scala:75:23]
wire a_d_bits_d_2_denied = 1'h0; // @[Edges.scala:645:17]
wire a_d_bits_d_2_corrupt = 1'h0; // @[Edges.scala:645:17]
wire c_d_2_bits_denied = 1'h0; // @[CacheCork.scala:112:23]
wire c_d_2_bits_corrupt = 1'h0; // @[CacheCork.scala:112:23]
wire c_d_bits_d_2_denied = 1'h0; // @[Edges.scala:677:17]
wire c_d_bits_d_2_corrupt = 1'h0; // @[Edges.scala:677:17]
wire _bypass_T_4 = 1'h0; // @[CacheCork.scala:150:57]
wire bypass_2 = 1'h0; // @[CacheCork.scala:150:71]
wire _opdata_T_4 = 1'h0; // @[Edges.scala:92:37]
wire _state_WIRE_4_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_4_1 = 1'h0; // @[Arbiter.scala:88:34]
wire maskedBeats_1_5 = 1'h0; // @[Arbiter.scala:82:69]
wire maskedBeats_2_2 = 1'h0; // @[Arbiter.scala:82:69]
wire _state_WIRE_5_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_5_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_5_2 = 1'h0; // @[Arbiter.scala:88:34]
wire a_d_3_bits_denied = 1'h0; // @[CacheCork.scala:75:23]
wire a_d_3_bits_corrupt = 1'h0; // @[CacheCork.scala:75:23]
wire a_d_bits_d_3_denied = 1'h0; // @[Edges.scala:645:17]
wire a_d_bits_d_3_corrupt = 1'h0; // @[Edges.scala:645:17]
wire c_d_3_bits_denied = 1'h0; // @[CacheCork.scala:112:23]
wire c_d_3_bits_corrupt = 1'h0; // @[CacheCork.scala:112:23]
wire c_d_bits_d_3_denied = 1'h0; // @[Edges.scala:677:17]
wire c_d_bits_d_3_corrupt = 1'h0; // @[Edges.scala:677:17]
wire _bypass_T_6 = 1'h0; // @[CacheCork.scala:150:57]
wire bypass_3 = 1'h0; // @[CacheCork.scala:150:71]
wire _opdata_T_6 = 1'h0; // @[Edges.scala:92:37]
wire _state_WIRE_6_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_6_1 = 1'h0; // @[Arbiter.scala:88:34]
wire maskedBeats_1_7 = 1'h0; // @[Arbiter.scala:82:69]
wire maskedBeats_2_3 = 1'h0; // @[Arbiter.scala:82:69]
wire _state_WIRE_7_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_7_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_7_2 = 1'h0; // @[Arbiter.scala:88:34]
wire a_d_4_bits_denied = 1'h0; // @[CacheCork.scala:75:23]
wire a_d_4_bits_corrupt = 1'h0; // @[CacheCork.scala:75:23]
wire a_d_bits_d_4_denied = 1'h0; // @[Edges.scala:645:17]
wire a_d_bits_d_4_corrupt = 1'h0; // @[Edges.scala:645:17]
wire c_d_4_bits_denied = 1'h0; // @[CacheCork.scala:112:23]
wire c_d_4_bits_corrupt = 1'h0; // @[CacheCork.scala:112:23]
wire c_d_bits_d_4_denied = 1'h0; // @[Edges.scala:677:17]
wire c_d_bits_d_4_corrupt = 1'h0; // @[Edges.scala:677:17]
wire _bypass_T_8 = 1'h0; // @[CacheCork.scala:150:57]
wire bypass_4 = 1'h0; // @[CacheCork.scala:150:71]
wire _opdata_T_8 = 1'h0; // @[Edges.scala:92:37]
wire _state_WIRE_8_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_8_1 = 1'h0; // @[Arbiter.scala:88:34]
wire maskedBeats_1_9 = 1'h0; // @[Arbiter.scala:82:69]
wire maskedBeats_2_4 = 1'h0; // @[Arbiter.scala:82:69]
wire _state_WIRE_9_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_9_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_9_2 = 1'h0; // @[Arbiter.scala:88:34]
wire a_d_5_bits_denied = 1'h0; // @[CacheCork.scala:75:23]
wire a_d_5_bits_corrupt = 1'h0; // @[CacheCork.scala:75:23]
wire a_d_bits_d_5_denied = 1'h0; // @[Edges.scala:645:17]
wire a_d_bits_d_5_corrupt = 1'h0; // @[Edges.scala:645:17]
wire c_d_5_bits_denied = 1'h0; // @[CacheCork.scala:112:23]
wire c_d_5_bits_corrupt = 1'h0; // @[CacheCork.scala:112:23]
wire c_d_bits_d_5_denied = 1'h0; // @[Edges.scala:677:17]
wire c_d_bits_d_5_corrupt = 1'h0; // @[Edges.scala:677:17]
wire _bypass_T_10 = 1'h0; // @[CacheCork.scala:150:57]
wire bypass_5 = 1'h0; // @[CacheCork.scala:150:71]
wire _opdata_T_10 = 1'h0; // @[Edges.scala:92:37]
wire _state_WIRE_10_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_10_1 = 1'h0; // @[Arbiter.scala:88:34]
wire maskedBeats_1_11 = 1'h0; // @[Arbiter.scala:82:69]
wire maskedBeats_2_5 = 1'h0; // @[Arbiter.scala:82:69]
wire _state_WIRE_11_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_11_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_11_2 = 1'h0; // @[Arbiter.scala:88:34]
wire a_d_6_bits_denied = 1'h0; // @[CacheCork.scala:75:23]
wire a_d_6_bits_corrupt = 1'h0; // @[CacheCork.scala:75:23]
wire a_d_bits_d_6_denied = 1'h0; // @[Edges.scala:645:17]
wire a_d_bits_d_6_corrupt = 1'h0; // @[Edges.scala:645:17]
wire c_d_6_bits_denied = 1'h0; // @[CacheCork.scala:112:23]
wire c_d_6_bits_corrupt = 1'h0; // @[CacheCork.scala:112:23]
wire c_d_bits_d_6_denied = 1'h0; // @[Edges.scala:677:17]
wire c_d_bits_d_6_corrupt = 1'h0; // @[Edges.scala:677:17]
wire _bypass_T_12 = 1'h0; // @[CacheCork.scala:150:57]
wire bypass_6 = 1'h0; // @[CacheCork.scala:150:71]
wire _opdata_T_12 = 1'h0; // @[Edges.scala:92:37]
wire _state_WIRE_12_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_12_1 = 1'h0; // @[Arbiter.scala:88:34]
wire maskedBeats_1_13 = 1'h0; // @[Arbiter.scala:82:69]
wire maskedBeats_2_6 = 1'h0; // @[Arbiter.scala:82:69]
wire _state_WIRE_13_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_13_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_13_2 = 1'h0; // @[Arbiter.scala:88:34]
wire a_d_7_bits_denied = 1'h0; // @[CacheCork.scala:75:23]
wire a_d_7_bits_corrupt = 1'h0; // @[CacheCork.scala:75:23]
wire a_d_bits_d_7_denied = 1'h0; // @[Edges.scala:645:17]
wire a_d_bits_d_7_corrupt = 1'h0; // @[Edges.scala:645:17]
wire c_d_7_bits_denied = 1'h0; // @[CacheCork.scala:112:23]
wire c_d_7_bits_corrupt = 1'h0; // @[CacheCork.scala:112:23]
wire c_d_bits_d_7_denied = 1'h0; // @[Edges.scala:677:17]
wire c_d_bits_d_7_corrupt = 1'h0; // @[Edges.scala:677:17]
wire _bypass_T_14 = 1'h0; // @[CacheCork.scala:150:57]
wire bypass_7 = 1'h0; // @[CacheCork.scala:150:71]
wire _opdata_T_14 = 1'h0; // @[Edges.scala:92:37]
wire _state_WIRE_14_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_14_1 = 1'h0; // @[Arbiter.scala:88:34]
wire maskedBeats_1_15 = 1'h0; // @[Arbiter.scala:82:69]
wire maskedBeats_2_7 = 1'h0; // @[Arbiter.scala:82:69]
wire _state_WIRE_15_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_15_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_15_2 = 1'h0; // @[Arbiter.scala:88:34]
wire [2:0] auto_in_7_b_bits_opcode = 3'h0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_7_b_bits_size = 3'h0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_6_b_bits_opcode = 3'h0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_6_b_bits_size = 3'h0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_5_b_bits_opcode = 3'h0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_5_b_bits_size = 3'h0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_4_b_bits_opcode = 3'h0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_4_b_bits_size = 3'h0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_3_b_bits_opcode = 3'h0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_3_b_bits_size = 3'h0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_2_b_bits_opcode = 3'h0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_2_b_bits_size = 3'h0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_1_b_bits_opcode = 3'h0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_1_b_bits_size = 3'h0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_0_b_bits_opcode = 3'h0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_0_b_bits_size = 3'h0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_b_bits_opcode = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_bits_size = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_1_b_bits_opcode = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_1_b_bits_size = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_2_b_bits_opcode = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_2_b_bits_size = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_3_b_bits_opcode = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_3_b_bits_size = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_4_b_bits_opcode = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_4_b_bits_size = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_5_b_bits_opcode = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_5_b_bits_size = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_6_b_bits_opcode = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_6_b_bits_size = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_7_b_bits_opcode = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_7_b_bits_size = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] a_d_bits_sink = 3'h0; // @[CacheCork.scala:75:23]
wire [2:0] a_d_bits_d_sink = 3'h0; // @[Edges.scala:645:17]
wire [2:0] c_a_bits_opcode = 3'h0; // @[CacheCork.scala:101:23]
wire [2:0] c_a_bits_param = 3'h0; // @[CacheCork.scala:101:23]
wire [2:0] c_a_bits_a_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] c_a_bits_a_param = 3'h0; // @[Edges.scala:480:17]
wire [2:0] c_d_bits_sink = 3'h0; // @[CacheCork.scala:112:23]
wire [2:0] c_d_bits_d_sink = 3'h0; // @[Edges.scala:677:17]
wire [2:0] _nodeOut_a_bits_T_18 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_21 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] a_d_1_bits_sink = 3'h0; // @[CacheCork.scala:75:23]
wire [2:0] a_d_bits_d_1_sink = 3'h0; // @[Edges.scala:645:17]
wire [2:0] c_a_1_bits_opcode = 3'h0; // @[CacheCork.scala:101:23]
wire [2:0] c_a_1_bits_param = 3'h0; // @[CacheCork.scala:101:23]
wire [2:0] c_a_bits_a_1_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] c_a_bits_a_1_param = 3'h0; // @[Edges.scala:480:17]
wire [2:0] c_d_1_bits_sink = 3'h0; // @[CacheCork.scala:112:23]
wire [2:0] c_d_bits_d_1_sink = 3'h0; // @[Edges.scala:677:17]
wire [2:0] _nodeOut_a_bits_T_42 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_45 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] a_d_2_bits_sink = 3'h0; // @[CacheCork.scala:75:23]
wire [2:0] a_d_bits_d_2_sink = 3'h0; // @[Edges.scala:645:17]
wire [2:0] c_a_2_bits_opcode = 3'h0; // @[CacheCork.scala:101:23]
wire [2:0] c_a_2_bits_param = 3'h0; // @[CacheCork.scala:101:23]
wire [2:0] c_a_bits_a_2_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] c_a_bits_a_2_param = 3'h0; // @[Edges.scala:480:17]
wire [2:0] c_d_2_bits_sink = 3'h0; // @[CacheCork.scala:112:23]
wire [2:0] c_d_bits_d_2_sink = 3'h0; // @[Edges.scala:677:17]
wire [2:0] _nodeOut_a_bits_T_66 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_69 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] a_d_3_bits_sink = 3'h0; // @[CacheCork.scala:75:23]
wire [2:0] a_d_bits_d_3_sink = 3'h0; // @[Edges.scala:645:17]
wire [2:0] c_a_3_bits_opcode = 3'h0; // @[CacheCork.scala:101:23]
wire [2:0] c_a_3_bits_param = 3'h0; // @[CacheCork.scala:101:23]
wire [2:0] c_a_bits_a_3_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] c_a_bits_a_3_param = 3'h0; // @[Edges.scala:480:17]
wire [2:0] c_d_3_bits_sink = 3'h0; // @[CacheCork.scala:112:23]
wire [2:0] c_d_bits_d_3_sink = 3'h0; // @[Edges.scala:677:17]
wire [2:0] _nodeOut_a_bits_T_90 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_93 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] a_d_4_bits_sink = 3'h0; // @[CacheCork.scala:75:23]
wire [2:0] a_d_bits_d_4_sink = 3'h0; // @[Edges.scala:645:17]
wire [2:0] c_a_4_bits_opcode = 3'h0; // @[CacheCork.scala:101:23]
wire [2:0] c_a_4_bits_param = 3'h0; // @[CacheCork.scala:101:23]
wire [2:0] c_a_bits_a_4_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] c_a_bits_a_4_param = 3'h0; // @[Edges.scala:480:17]
wire [2:0] c_d_4_bits_sink = 3'h0; // @[CacheCork.scala:112:23]
wire [2:0] c_d_bits_d_4_sink = 3'h0; // @[Edges.scala:677:17]
wire [2:0] _nodeOut_a_bits_T_114 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_117 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] a_d_5_bits_sink = 3'h0; // @[CacheCork.scala:75:23]
wire [2:0] a_d_bits_d_5_sink = 3'h0; // @[Edges.scala:645:17]
wire [2:0] c_a_5_bits_opcode = 3'h0; // @[CacheCork.scala:101:23]
wire [2:0] c_a_5_bits_param = 3'h0; // @[CacheCork.scala:101:23]
wire [2:0] c_a_bits_a_5_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] c_a_bits_a_5_param = 3'h0; // @[Edges.scala:480:17]
wire [2:0] c_d_5_bits_sink = 3'h0; // @[CacheCork.scala:112:23]
wire [2:0] c_d_bits_d_5_sink = 3'h0; // @[Edges.scala:677:17]
wire [2:0] _nodeOut_a_bits_T_138 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_141 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] a_d_6_bits_sink = 3'h0; // @[CacheCork.scala:75:23]
wire [2:0] a_d_bits_d_6_sink = 3'h0; // @[Edges.scala:645:17]
wire [2:0] c_a_6_bits_opcode = 3'h0; // @[CacheCork.scala:101:23]
wire [2:0] c_a_6_bits_param = 3'h0; // @[CacheCork.scala:101:23]
wire [2:0] c_a_bits_a_6_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] c_a_bits_a_6_param = 3'h0; // @[Edges.scala:480:17]
wire [2:0] c_d_6_bits_sink = 3'h0; // @[CacheCork.scala:112:23]
wire [2:0] c_d_bits_d_6_sink = 3'h0; // @[Edges.scala:677:17]
wire [2:0] _nodeOut_a_bits_T_162 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_165 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] a_d_7_bits_sink = 3'h0; // @[CacheCork.scala:75:23]
wire [2:0] a_d_bits_d_7_sink = 3'h0; // @[Edges.scala:645:17]
wire [2:0] c_a_7_bits_opcode = 3'h0; // @[CacheCork.scala:101:23]
wire [2:0] c_a_7_bits_param = 3'h0; // @[CacheCork.scala:101:23]
wire [2:0] c_a_bits_a_7_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] c_a_bits_a_7_param = 3'h0; // @[Edges.scala:480:17]
wire [2:0] c_d_7_bits_sink = 3'h0; // @[CacheCork.scala:112:23]
wire [2:0] c_d_bits_d_7_sink = 3'h0; // @[Edges.scala:677:17]
wire [2:0] _nodeOut_a_bits_T_186 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_189 = 3'h0; // @[Mux.scala:30:73]
wire [1:0] auto_in_7_b_bits_param = 2'h0; // @[CacheCork.scala:42:9]
wire [1:0] auto_in_6_b_bits_param = 2'h0; // @[CacheCork.scala:42:9]
wire [1:0] auto_in_5_b_bits_param = 2'h0; // @[CacheCork.scala:42:9]
wire [1:0] auto_in_4_b_bits_param = 2'h0; // @[CacheCork.scala:42:9]
wire [1:0] auto_in_3_b_bits_param = 2'h0; // @[CacheCork.scala:42:9]
wire [1:0] auto_in_2_b_bits_param = 2'h0; // @[CacheCork.scala:42:9]
wire [1:0] auto_in_1_b_bits_param = 2'h0; // @[CacheCork.scala:42:9]
wire [1:0] auto_in_0_b_bits_param = 2'h0; // @[CacheCork.scala:42:9]
wire [1:0] nodeIn_b_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_1_b_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_2_b_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_3_b_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_4_b_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_5_b_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_6_b_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_7_b_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] a_d_bits_param = 2'h0; // @[CacheCork.scala:75:23]
wire [1:0] a_d_bits_d_param = 2'h0; // @[Edges.scala:645:17]
wire [1:0] c_d_bits_param = 2'h0; // @[CacheCork.scala:112:23]
wire [1:0] c_d_bits_d_param = 2'h0; // @[Edges.scala:677:17]
wire [1:0] a_d_1_bits_param = 2'h0; // @[CacheCork.scala:75:23]
wire [1:0] a_d_bits_d_1_param = 2'h0; // @[Edges.scala:645:17]
wire [1:0] c_d_1_bits_param = 2'h0; // @[CacheCork.scala:112:23]
wire [1:0] c_d_bits_d_1_param = 2'h0; // @[Edges.scala:677:17]
wire [1:0] a_d_2_bits_param = 2'h0; // @[CacheCork.scala:75:23]
wire [1:0] a_d_bits_d_2_param = 2'h0; // @[Edges.scala:645:17]
wire [1:0] c_d_2_bits_param = 2'h0; // @[CacheCork.scala:112:23]
wire [1:0] c_d_bits_d_2_param = 2'h0; // @[Edges.scala:677:17]
wire [1:0] a_d_3_bits_param = 2'h0; // @[CacheCork.scala:75:23]
wire [1:0] a_d_bits_d_3_param = 2'h0; // @[Edges.scala:645:17]
wire [1:0] c_d_3_bits_param = 2'h0; // @[CacheCork.scala:112:23]
wire [1:0] c_d_bits_d_3_param = 2'h0; // @[Edges.scala:677:17]
wire [1:0] a_d_4_bits_param = 2'h0; // @[CacheCork.scala:75:23]
wire [1:0] a_d_bits_d_4_param = 2'h0; // @[Edges.scala:645:17]
wire [1:0] c_d_4_bits_param = 2'h0; // @[CacheCork.scala:112:23]
wire [1:0] c_d_bits_d_4_param = 2'h0; // @[Edges.scala:677:17]
wire [1:0] a_d_5_bits_param = 2'h0; // @[CacheCork.scala:75:23]
wire [1:0] a_d_bits_d_5_param = 2'h0; // @[Edges.scala:645:17]
wire [1:0] c_d_5_bits_param = 2'h0; // @[CacheCork.scala:112:23]
wire [1:0] c_d_bits_d_5_param = 2'h0; // @[Edges.scala:677:17]
wire [1:0] a_d_6_bits_param = 2'h0; // @[CacheCork.scala:75:23]
wire [1:0] a_d_bits_d_6_param = 2'h0; // @[Edges.scala:645:17]
wire [1:0] c_d_6_bits_param = 2'h0; // @[CacheCork.scala:112:23]
wire [1:0] c_d_bits_d_6_param = 2'h0; // @[Edges.scala:677:17]
wire [1:0] a_d_7_bits_param = 2'h0; // @[CacheCork.scala:75:23]
wire [1:0] a_d_bits_d_7_param = 2'h0; // @[Edges.scala:645:17]
wire [1:0] c_d_7_bits_param = 2'h0; // @[CacheCork.scala:112:23]
wire [1:0] c_d_bits_d_7_param = 2'h0; // @[Edges.scala:677:17]
wire [3:0] auto_in_7_b_bits_source = 4'h0; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_6_b_bits_source = 4'h0; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_5_b_bits_source = 4'h0; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_4_b_bits_source = 4'h0; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_3_b_bits_source = 4'h0; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_2_b_bits_source = 4'h0; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_1_b_bits_source = 4'h0; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_0_b_bits_source = 4'h0; // @[CacheCork.scala:42:9]
wire [3:0] nodeIn_b_bits_source = 4'h0; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_1_b_bits_source = 4'h0; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_2_b_bits_source = 4'h0; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_3_b_bits_source = 4'h0; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_4_b_bits_source = 4'h0; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_5_b_bits_source = 4'h0; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_6_b_bits_source = 4'h0; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_7_b_bits_source = 4'h0; // @[MixedNode.scala:551:17]
wire [31:0] auto_in_7_b_bits_address = 32'h0; // @[CacheCork.scala:42:9]
wire [31:0] auto_in_6_b_bits_address = 32'h0; // @[CacheCork.scala:42:9]
wire [31:0] auto_in_5_b_bits_address = 32'h0; // @[CacheCork.scala:42:9]
wire [31:0] auto_in_4_b_bits_address = 32'h0; // @[CacheCork.scala:42:9]
wire [31:0] auto_in_3_b_bits_address = 32'h0; // @[CacheCork.scala:42:9]
wire [31:0] auto_in_2_b_bits_address = 32'h0; // @[CacheCork.scala:42:9]
wire [31:0] auto_in_1_b_bits_address = 32'h0; // @[CacheCork.scala:42:9]
wire [31:0] auto_in_0_b_bits_address = 32'h0; // @[CacheCork.scala:42:9]
wire [31:0] nodeIn_b_bits_address = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_1_b_bits_address = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_2_b_bits_address = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_3_b_bits_address = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_4_b_bits_address = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_5_b_bits_address = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_6_b_bits_address = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_7_b_bits_address = 32'h0; // @[MixedNode.scala:551:17]
wire [7:0] auto_in_7_b_bits_mask = 8'h0; // @[CacheCork.scala:42:9]
wire [7:0] auto_in_6_b_bits_mask = 8'h0; // @[CacheCork.scala:42:9]
wire [7:0] auto_in_5_b_bits_mask = 8'h0; // @[CacheCork.scala:42:9]
wire [7:0] auto_in_4_b_bits_mask = 8'h0; // @[CacheCork.scala:42:9]
wire [7:0] auto_in_3_b_bits_mask = 8'h0; // @[CacheCork.scala:42:9]
wire [7:0] auto_in_2_b_bits_mask = 8'h0; // @[CacheCork.scala:42:9]
wire [7:0] auto_in_1_b_bits_mask = 8'h0; // @[CacheCork.scala:42:9]
wire [7:0] auto_in_0_b_bits_mask = 8'h0; // @[CacheCork.scala:42:9]
wire [7:0] nodeIn_b_bits_mask = 8'h0; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_1_b_bits_mask = 8'h0; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_2_b_bits_mask = 8'h0; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_3_b_bits_mask = 8'h0; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_4_b_bits_mask = 8'h0; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_5_b_bits_mask = 8'h0; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_6_b_bits_mask = 8'h0; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_7_b_bits_mask = 8'h0; // @[MixedNode.scala:551:17]
wire [63:0] auto_in_7_b_bits_data = 64'h0; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_6_b_bits_data = 64'h0; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_5_b_bits_data = 64'h0; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_4_b_bits_data = 64'h0; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_3_b_bits_data = 64'h0; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_2_b_bits_data = 64'h0; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_1_b_bits_data = 64'h0; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_0_b_bits_data = 64'h0; // @[CacheCork.scala:42:9]
wire [63:0] nodeIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_1_b_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_2_b_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_3_b_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_4_b_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_5_b_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_6_b_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_7_b_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] a_d_bits_data = 64'h0; // @[CacheCork.scala:75:23]
wire [63:0] a_d_bits_d_data = 64'h0; // @[Edges.scala:645:17]
wire [63:0] c_d_bits_data = 64'h0; // @[CacheCork.scala:112:23]
wire [63:0] c_d_bits_d_data = 64'h0; // @[Edges.scala:677:17]
wire [63:0] a_d_1_bits_data = 64'h0; // @[CacheCork.scala:75:23]
wire [63:0] a_d_bits_d_1_data = 64'h0; // @[Edges.scala:645:17]
wire [63:0] c_d_1_bits_data = 64'h0; // @[CacheCork.scala:112:23]
wire [63:0] c_d_bits_d_1_data = 64'h0; // @[Edges.scala:677:17]
wire [63:0] a_d_2_bits_data = 64'h0; // @[CacheCork.scala:75:23]
wire [63:0] a_d_bits_d_2_data = 64'h0; // @[Edges.scala:645:17]
wire [63:0] c_d_2_bits_data = 64'h0; // @[CacheCork.scala:112:23]
wire [63:0] c_d_bits_d_2_data = 64'h0; // @[Edges.scala:677:17]
wire [63:0] a_d_3_bits_data = 64'h0; // @[CacheCork.scala:75:23]
wire [63:0] a_d_bits_d_3_data = 64'h0; // @[Edges.scala:645:17]
wire [63:0] c_d_3_bits_data = 64'h0; // @[CacheCork.scala:112:23]
wire [63:0] c_d_bits_d_3_data = 64'h0; // @[Edges.scala:677:17]
wire [63:0] a_d_4_bits_data = 64'h0; // @[CacheCork.scala:75:23]
wire [63:0] a_d_bits_d_4_data = 64'h0; // @[Edges.scala:645:17]
wire [63:0] c_d_4_bits_data = 64'h0; // @[CacheCork.scala:112:23]
wire [63:0] c_d_bits_d_4_data = 64'h0; // @[Edges.scala:677:17]
wire [63:0] a_d_5_bits_data = 64'h0; // @[CacheCork.scala:75:23]
wire [63:0] a_d_bits_d_5_data = 64'h0; // @[Edges.scala:645:17]
wire [63:0] c_d_5_bits_data = 64'h0; // @[CacheCork.scala:112:23]
wire [63:0] c_d_bits_d_5_data = 64'h0; // @[Edges.scala:677:17]
wire [63:0] a_d_6_bits_data = 64'h0; // @[CacheCork.scala:75:23]
wire [63:0] a_d_bits_d_6_data = 64'h0; // @[Edges.scala:645:17]
wire [63:0] c_d_6_bits_data = 64'h0; // @[CacheCork.scala:112:23]
wire [63:0] c_d_bits_d_6_data = 64'h0; // @[Edges.scala:677:17]
wire [63:0] a_d_7_bits_data = 64'h0; // @[CacheCork.scala:75:23]
wire [63:0] a_d_bits_d_7_data = 64'h0; // @[Edges.scala:645:17]
wire [63:0] c_d_7_bits_data = 64'h0; // @[CacheCork.scala:112:23]
wire [63:0] c_d_bits_d_7_data = 64'h0; // @[Edges.scala:677:17]
wire [2:0] a_d_bits_opcode = 3'h4; // @[CacheCork.scala:75:23]
wire [2:0] a_d_bits_d_opcode = 3'h4; // @[Edges.scala:645:17]
wire [2:0] a_d_1_bits_opcode = 3'h4; // @[CacheCork.scala:75:23]
wire [2:0] a_d_bits_d_1_opcode = 3'h4; // @[Edges.scala:645:17]
wire [2:0] a_d_2_bits_opcode = 3'h4; // @[CacheCork.scala:75:23]
wire [2:0] a_d_bits_d_2_opcode = 3'h4; // @[Edges.scala:645:17]
wire [2:0] a_d_3_bits_opcode = 3'h4; // @[CacheCork.scala:75:23]
wire [2:0] a_d_bits_d_3_opcode = 3'h4; // @[Edges.scala:645:17]
wire [2:0] a_d_4_bits_opcode = 3'h4; // @[CacheCork.scala:75:23]
wire [2:0] a_d_bits_d_4_opcode = 3'h4; // @[Edges.scala:645:17]
wire [2:0] a_d_5_bits_opcode = 3'h4; // @[CacheCork.scala:75:23]
wire [2:0] a_d_bits_d_5_opcode = 3'h4; // @[Edges.scala:645:17]
wire [2:0] a_d_6_bits_opcode = 3'h4; // @[CacheCork.scala:75:23]
wire [2:0] a_d_bits_d_6_opcode = 3'h4; // @[Edges.scala:645:17]
wire [2:0] a_d_7_bits_opcode = 3'h4; // @[CacheCork.scala:75:23]
wire [2:0] a_d_bits_d_7_opcode = 3'h4; // @[Edges.scala:645:17]
wire [2:0] c_d_bits_opcode = 3'h6; // @[CacheCork.scala:112:23]
wire [2:0] c_d_bits_d_opcode = 3'h6; // @[Edges.scala:677:17]
wire [2:0] c_d_1_bits_opcode = 3'h6; // @[CacheCork.scala:112:23]
wire [2:0] c_d_bits_d_1_opcode = 3'h6; // @[Edges.scala:677:17]
wire [2:0] c_d_2_bits_opcode = 3'h6; // @[CacheCork.scala:112:23]
wire [2:0] c_d_bits_d_2_opcode = 3'h6; // @[Edges.scala:677:17]
wire [2:0] c_d_3_bits_opcode = 3'h6; // @[CacheCork.scala:112:23]
wire [2:0] c_d_bits_d_3_opcode = 3'h6; // @[Edges.scala:677:17]
wire [2:0] c_d_4_bits_opcode = 3'h6; // @[CacheCork.scala:112:23]
wire [2:0] c_d_bits_d_4_opcode = 3'h6; // @[Edges.scala:677:17]
wire [2:0] c_d_5_bits_opcode = 3'h6; // @[CacheCork.scala:112:23]
wire [2:0] c_d_bits_d_5_opcode = 3'h6; // @[Edges.scala:677:17]
wire [2:0] c_d_6_bits_opcode = 3'h6; // @[CacheCork.scala:112:23]
wire [2:0] c_d_bits_d_6_opcode = 3'h6; // @[Edges.scala:677:17]
wire [2:0] c_d_7_bits_opcode = 3'h6; // @[CacheCork.scala:112:23]
wire [2:0] c_d_bits_d_7_opcode = 3'h6; // @[Edges.scala:677:17]
wire [32:0] _c_a_bits_legal_T_6 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _c_a_bits_legal_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _aWOk_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _aWOk_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _c_a_bits_legal_T_16 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _c_a_bits_legal_T_17 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _aWOk_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _aWOk_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _c_a_bits_legal_T_26 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _c_a_bits_legal_T_27 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _aWOk_T_12 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _aWOk_T_13 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _c_a_bits_legal_T_36 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _c_a_bits_legal_T_37 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _aWOk_T_17 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _aWOk_T_18 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _c_a_bits_legal_T_46 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _c_a_bits_legal_T_47 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _aWOk_T_22 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _aWOk_T_23 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _c_a_bits_legal_T_56 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _c_a_bits_legal_T_57 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _aWOk_T_27 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _aWOk_T_28 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _c_a_bits_legal_T_66 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _c_a_bits_legal_T_67 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _aWOk_T_32 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _aWOk_T_33 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _c_a_bits_legal_T_76 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _c_a_bits_legal_T_77 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _aWOk_T_37 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _aWOk_T_38 = 33'h0; // @[Parameters.scala:137:46]
wire nodeIn_7_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_7_a_valid = auto_in_7_a_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_7_a_bits_opcode = auto_in_7_a_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_7_a_bits_param = auto_in_7_a_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_7_a_bits_size = auto_in_7_a_bits_size_0; // @[CacheCork.scala:42:9]
wire [3:0] nodeIn_7_a_bits_source = auto_in_7_a_bits_source_0; // @[CacheCork.scala:42:9]
wire [31:0] nodeIn_7_a_bits_address = auto_in_7_a_bits_address_0; // @[CacheCork.scala:42:9]
wire [7:0] nodeIn_7_a_bits_mask = auto_in_7_a_bits_mask_0; // @[CacheCork.scala:42:9]
wire [63:0] nodeIn_7_a_bits_data = auto_in_7_a_bits_data_0; // @[CacheCork.scala:42:9]
wire nodeIn_7_a_bits_corrupt = auto_in_7_a_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire nodeIn_7_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_7_c_valid = auto_in_7_c_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_7_c_bits_opcode = auto_in_7_c_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_7_c_bits_param = auto_in_7_c_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_7_c_bits_size = auto_in_7_c_bits_size_0; // @[CacheCork.scala:42:9]
wire [3:0] nodeIn_7_c_bits_source = auto_in_7_c_bits_source_0; // @[CacheCork.scala:42:9]
wire [31:0] nodeIn_7_c_bits_address = auto_in_7_c_bits_address_0; // @[CacheCork.scala:42:9]
wire [63:0] nodeIn_7_c_bits_data = auto_in_7_c_bits_data_0; // @[CacheCork.scala:42:9]
wire nodeIn_7_c_bits_corrupt = auto_in_7_c_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire nodeIn_7_d_ready = auto_in_7_d_ready_0; // @[CacheCork.scala:42:9]
wire nodeIn_7_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_7_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_7_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_7_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_7_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_7_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_7_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_7_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_7_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_7_e_valid = auto_in_7_e_valid_0; // @[CacheCork.scala:42:9]
wire nodeIn_6_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_7_e_bits_sink = auto_in_7_e_bits_sink_0; // @[CacheCork.scala:42:9]
wire nodeIn_6_a_valid = auto_in_6_a_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_6_a_bits_opcode = auto_in_6_a_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_6_a_bits_param = auto_in_6_a_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_6_a_bits_size = auto_in_6_a_bits_size_0; // @[CacheCork.scala:42:9]
wire [3:0] nodeIn_6_a_bits_source = auto_in_6_a_bits_source_0; // @[CacheCork.scala:42:9]
wire [31:0] nodeIn_6_a_bits_address = auto_in_6_a_bits_address_0; // @[CacheCork.scala:42:9]
wire [7:0] nodeIn_6_a_bits_mask = auto_in_6_a_bits_mask_0; // @[CacheCork.scala:42:9]
wire [63:0] nodeIn_6_a_bits_data = auto_in_6_a_bits_data_0; // @[CacheCork.scala:42:9]
wire nodeIn_6_a_bits_corrupt = auto_in_6_a_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire nodeIn_6_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_6_c_valid = auto_in_6_c_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_6_c_bits_opcode = auto_in_6_c_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_6_c_bits_param = auto_in_6_c_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_6_c_bits_size = auto_in_6_c_bits_size_0; // @[CacheCork.scala:42:9]
wire [3:0] nodeIn_6_c_bits_source = auto_in_6_c_bits_source_0; // @[CacheCork.scala:42:9]
wire [31:0] nodeIn_6_c_bits_address = auto_in_6_c_bits_address_0; // @[CacheCork.scala:42:9]
wire [63:0] nodeIn_6_c_bits_data = auto_in_6_c_bits_data_0; // @[CacheCork.scala:42:9]
wire nodeIn_6_c_bits_corrupt = auto_in_6_c_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire nodeIn_6_d_ready = auto_in_6_d_ready_0; // @[CacheCork.scala:42:9]
wire nodeIn_6_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_6_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_6_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_6_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_6_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_6_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_6_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_6_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_6_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_6_e_valid = auto_in_6_e_valid_0; // @[CacheCork.scala:42:9]
wire nodeIn_5_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_6_e_bits_sink = auto_in_6_e_bits_sink_0; // @[CacheCork.scala:42:9]
wire nodeIn_5_a_valid = auto_in_5_a_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_5_a_bits_opcode = auto_in_5_a_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_5_a_bits_param = auto_in_5_a_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_5_a_bits_size = auto_in_5_a_bits_size_0; // @[CacheCork.scala:42:9]
wire [3:0] nodeIn_5_a_bits_source = auto_in_5_a_bits_source_0; // @[CacheCork.scala:42:9]
wire [31:0] nodeIn_5_a_bits_address = auto_in_5_a_bits_address_0; // @[CacheCork.scala:42:9]
wire [7:0] nodeIn_5_a_bits_mask = auto_in_5_a_bits_mask_0; // @[CacheCork.scala:42:9]
wire [63:0] nodeIn_5_a_bits_data = auto_in_5_a_bits_data_0; // @[CacheCork.scala:42:9]
wire nodeIn_5_a_bits_corrupt = auto_in_5_a_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire nodeIn_5_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_5_c_valid = auto_in_5_c_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_5_c_bits_opcode = auto_in_5_c_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_5_c_bits_param = auto_in_5_c_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_5_c_bits_size = auto_in_5_c_bits_size_0; // @[CacheCork.scala:42:9]
wire [3:0] nodeIn_5_c_bits_source = auto_in_5_c_bits_source_0; // @[CacheCork.scala:42:9]
wire [31:0] nodeIn_5_c_bits_address = auto_in_5_c_bits_address_0; // @[CacheCork.scala:42:9]
wire [63:0] nodeIn_5_c_bits_data = auto_in_5_c_bits_data_0; // @[CacheCork.scala:42:9]
wire nodeIn_5_c_bits_corrupt = auto_in_5_c_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire nodeIn_5_d_ready = auto_in_5_d_ready_0; // @[CacheCork.scala:42:9]
wire nodeIn_5_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_5_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_5_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_5_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_5_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_5_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_5_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_5_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_5_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_5_e_valid = auto_in_5_e_valid_0; // @[CacheCork.scala:42:9]
wire nodeIn_4_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_5_e_bits_sink = auto_in_5_e_bits_sink_0; // @[CacheCork.scala:42:9]
wire nodeIn_4_a_valid = auto_in_4_a_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_4_a_bits_opcode = auto_in_4_a_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_4_a_bits_param = auto_in_4_a_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_4_a_bits_size = auto_in_4_a_bits_size_0; // @[CacheCork.scala:42:9]
wire [3:0] nodeIn_4_a_bits_source = auto_in_4_a_bits_source_0; // @[CacheCork.scala:42:9]
wire [31:0] nodeIn_4_a_bits_address = auto_in_4_a_bits_address_0; // @[CacheCork.scala:42:9]
wire [7:0] nodeIn_4_a_bits_mask = auto_in_4_a_bits_mask_0; // @[CacheCork.scala:42:9]
wire [63:0] nodeIn_4_a_bits_data = auto_in_4_a_bits_data_0; // @[CacheCork.scala:42:9]
wire nodeIn_4_a_bits_corrupt = auto_in_4_a_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire nodeIn_4_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_4_c_valid = auto_in_4_c_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_4_c_bits_opcode = auto_in_4_c_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_4_c_bits_param = auto_in_4_c_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_4_c_bits_size = auto_in_4_c_bits_size_0; // @[CacheCork.scala:42:9]
wire [3:0] nodeIn_4_c_bits_source = auto_in_4_c_bits_source_0; // @[CacheCork.scala:42:9]
wire [31:0] nodeIn_4_c_bits_address = auto_in_4_c_bits_address_0; // @[CacheCork.scala:42:9]
wire [63:0] nodeIn_4_c_bits_data = auto_in_4_c_bits_data_0; // @[CacheCork.scala:42:9]
wire nodeIn_4_c_bits_corrupt = auto_in_4_c_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire nodeIn_4_d_ready = auto_in_4_d_ready_0; // @[CacheCork.scala:42:9]
wire nodeIn_4_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_4_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_4_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_4_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_4_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_4_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_4_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_4_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_4_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_4_e_valid = auto_in_4_e_valid_0; // @[CacheCork.scala:42:9]
wire nodeIn_3_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_4_e_bits_sink = auto_in_4_e_bits_sink_0; // @[CacheCork.scala:42:9]
wire nodeIn_3_a_valid = auto_in_3_a_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_3_a_bits_opcode = auto_in_3_a_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_3_a_bits_param = auto_in_3_a_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_3_a_bits_size = auto_in_3_a_bits_size_0; // @[CacheCork.scala:42:9]
wire [3:0] nodeIn_3_a_bits_source = auto_in_3_a_bits_source_0; // @[CacheCork.scala:42:9]
wire [31:0] nodeIn_3_a_bits_address = auto_in_3_a_bits_address_0; // @[CacheCork.scala:42:9]
wire [7:0] nodeIn_3_a_bits_mask = auto_in_3_a_bits_mask_0; // @[CacheCork.scala:42:9]
wire [63:0] nodeIn_3_a_bits_data = auto_in_3_a_bits_data_0; // @[CacheCork.scala:42:9]
wire nodeIn_3_a_bits_corrupt = auto_in_3_a_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire nodeIn_3_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_3_c_valid = auto_in_3_c_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_3_c_bits_opcode = auto_in_3_c_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_3_c_bits_param = auto_in_3_c_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_3_c_bits_size = auto_in_3_c_bits_size_0; // @[CacheCork.scala:42:9]
wire [3:0] nodeIn_3_c_bits_source = auto_in_3_c_bits_source_0; // @[CacheCork.scala:42:9]
wire [31:0] nodeIn_3_c_bits_address = auto_in_3_c_bits_address_0; // @[CacheCork.scala:42:9]
wire [63:0] nodeIn_3_c_bits_data = auto_in_3_c_bits_data_0; // @[CacheCork.scala:42:9]
wire nodeIn_3_c_bits_corrupt = auto_in_3_c_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire nodeIn_3_d_ready = auto_in_3_d_ready_0; // @[CacheCork.scala:42:9]
wire nodeIn_3_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_3_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_3_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_3_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_3_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_3_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_3_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_3_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_3_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_3_e_valid = auto_in_3_e_valid_0; // @[CacheCork.scala:42:9]
wire nodeIn_2_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_3_e_bits_sink = auto_in_3_e_bits_sink_0; // @[CacheCork.scala:42:9]
wire nodeIn_2_a_valid = auto_in_2_a_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_2_a_bits_opcode = auto_in_2_a_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_2_a_bits_param = auto_in_2_a_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_2_a_bits_size = auto_in_2_a_bits_size_0; // @[CacheCork.scala:42:9]
wire [3:0] nodeIn_2_a_bits_source = auto_in_2_a_bits_source_0; // @[CacheCork.scala:42:9]
wire [31:0] nodeIn_2_a_bits_address = auto_in_2_a_bits_address_0; // @[CacheCork.scala:42:9]
wire [7:0] nodeIn_2_a_bits_mask = auto_in_2_a_bits_mask_0; // @[CacheCork.scala:42:9]
wire [63:0] nodeIn_2_a_bits_data = auto_in_2_a_bits_data_0; // @[CacheCork.scala:42:9]
wire nodeIn_2_a_bits_corrupt = auto_in_2_a_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire nodeIn_2_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_2_c_valid = auto_in_2_c_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_2_c_bits_opcode = auto_in_2_c_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_2_c_bits_param = auto_in_2_c_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_2_c_bits_size = auto_in_2_c_bits_size_0; // @[CacheCork.scala:42:9]
wire [3:0] nodeIn_2_c_bits_source = auto_in_2_c_bits_source_0; // @[CacheCork.scala:42:9]
wire [31:0] nodeIn_2_c_bits_address = auto_in_2_c_bits_address_0; // @[CacheCork.scala:42:9]
wire [63:0] nodeIn_2_c_bits_data = auto_in_2_c_bits_data_0; // @[CacheCork.scala:42:9]
wire nodeIn_2_c_bits_corrupt = auto_in_2_c_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire nodeIn_2_d_ready = auto_in_2_d_ready_0; // @[CacheCork.scala:42:9]
wire nodeIn_2_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_2_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_2_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_2_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_2_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_2_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_2_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_2_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_2_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_2_e_valid = auto_in_2_e_valid_0; // @[CacheCork.scala:42:9]
wire nodeIn_1_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_2_e_bits_sink = auto_in_2_e_bits_sink_0; // @[CacheCork.scala:42:9]
wire nodeIn_1_a_valid = auto_in_1_a_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_1_a_bits_opcode = auto_in_1_a_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_1_a_bits_param = auto_in_1_a_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_1_a_bits_size = auto_in_1_a_bits_size_0; // @[CacheCork.scala:42:9]
wire [3:0] nodeIn_1_a_bits_source = auto_in_1_a_bits_source_0; // @[CacheCork.scala:42:9]
wire [31:0] nodeIn_1_a_bits_address = auto_in_1_a_bits_address_0; // @[CacheCork.scala:42:9]
wire [7:0] nodeIn_1_a_bits_mask = auto_in_1_a_bits_mask_0; // @[CacheCork.scala:42:9]
wire [63:0] nodeIn_1_a_bits_data = auto_in_1_a_bits_data_0; // @[CacheCork.scala:42:9]
wire nodeIn_1_a_bits_corrupt = auto_in_1_a_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire nodeIn_1_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_1_c_valid = auto_in_1_c_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_1_c_bits_opcode = auto_in_1_c_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_1_c_bits_param = auto_in_1_c_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_1_c_bits_size = auto_in_1_c_bits_size_0; // @[CacheCork.scala:42:9]
wire [3:0] nodeIn_1_c_bits_source = auto_in_1_c_bits_source_0; // @[CacheCork.scala:42:9]
wire [31:0] nodeIn_1_c_bits_address = auto_in_1_c_bits_address_0; // @[CacheCork.scala:42:9]
wire [63:0] nodeIn_1_c_bits_data = auto_in_1_c_bits_data_0; // @[CacheCork.scala:42:9]
wire nodeIn_1_c_bits_corrupt = auto_in_1_c_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire nodeIn_1_d_ready = auto_in_1_d_ready_0; // @[CacheCork.scala:42:9]
wire nodeIn_1_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_1_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_1_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_1_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_1_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_1_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_1_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_1_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_1_e_valid = auto_in_1_e_valid_0; // @[CacheCork.scala:42:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_1_e_bits_sink = auto_in_1_e_bits_sink_0; // @[CacheCork.scala:42:9]
wire nodeIn_a_valid = auto_in_0_a_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_0_a_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_a_bits_param = auto_in_0_a_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_a_bits_size = auto_in_0_a_bits_size_0; // @[CacheCork.scala:42:9]
wire [3:0] nodeIn_a_bits_source = auto_in_0_a_bits_source_0; // @[CacheCork.scala:42:9]
wire [31:0] nodeIn_a_bits_address = auto_in_0_a_bits_address_0; // @[CacheCork.scala:42:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_0_a_bits_mask_0; // @[CacheCork.scala:42:9]
wire [63:0] nodeIn_a_bits_data = auto_in_0_a_bits_data_0; // @[CacheCork.scala:42:9]
wire nodeIn_a_bits_corrupt = auto_in_0_a_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_c_valid = auto_in_0_c_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_c_bits_opcode = auto_in_0_c_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_c_bits_param = auto_in_0_c_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_c_bits_size = auto_in_0_c_bits_size_0; // @[CacheCork.scala:42:9]
wire [3:0] nodeIn_c_bits_source = auto_in_0_c_bits_source_0; // @[CacheCork.scala:42:9]
wire [31:0] nodeIn_c_bits_address = auto_in_0_c_bits_address_0; // @[CacheCork.scala:42:9]
wire [63:0] nodeIn_c_bits_data = auto_in_0_c_bits_data_0; // @[CacheCork.scala:42:9]
wire nodeIn_c_bits_corrupt = auto_in_0_c_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire nodeIn_d_ready = auto_in_0_d_ready_0; // @[CacheCork.scala:42:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_e_valid = auto_in_0_e_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeIn_e_bits_sink = auto_in_0_e_bits_sink_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_6_a_ready = auto_out_7_a_ready_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_6_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_6_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_6_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_6_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_nodeOut_6_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_nodeOut_6_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_nodeOut_6_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_nodeOut_6_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_nodeOut_6_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_nodeOut_6_d_ready; // @[MixedNode.scala:542:17]
wire x1_nodeOut_6_d_valid = auto_out_7_d_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] x1_nodeOut_6_d_bits_opcode = auto_out_7_d_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [1:0] x1_nodeOut_6_d_bits_param = auto_out_7_d_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] x1_nodeOut_6_d_bits_size = auto_out_7_d_bits_size_0; // @[CacheCork.scala:42:9]
wire [4:0] x1_nodeOut_6_d_bits_source = auto_out_7_d_bits_source_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_6_d_bits_sink = auto_out_7_d_bits_sink_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_6_d_bits_denied = auto_out_7_d_bits_denied_0; // @[CacheCork.scala:42:9]
wire [63:0] x1_nodeOut_6_d_bits_data = auto_out_7_d_bits_data_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_6_d_bits_corrupt = auto_out_7_d_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_5_a_ready = auto_out_6_a_ready_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_5_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_5_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_5_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_5_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_nodeOut_5_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_nodeOut_5_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_nodeOut_5_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_nodeOut_5_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_nodeOut_5_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_nodeOut_5_d_ready; // @[MixedNode.scala:542:17]
wire x1_nodeOut_5_d_valid = auto_out_6_d_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] x1_nodeOut_5_d_bits_opcode = auto_out_6_d_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [1:0] x1_nodeOut_5_d_bits_param = auto_out_6_d_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] x1_nodeOut_5_d_bits_size = auto_out_6_d_bits_size_0; // @[CacheCork.scala:42:9]
wire [4:0] x1_nodeOut_5_d_bits_source = auto_out_6_d_bits_source_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_5_d_bits_sink = auto_out_6_d_bits_sink_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_5_d_bits_denied = auto_out_6_d_bits_denied_0; // @[CacheCork.scala:42:9]
wire [63:0] x1_nodeOut_5_d_bits_data = auto_out_6_d_bits_data_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_5_d_bits_corrupt = auto_out_6_d_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_4_a_ready = auto_out_5_a_ready_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_4_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_4_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_4_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_4_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_nodeOut_4_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_nodeOut_4_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_nodeOut_4_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_nodeOut_4_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_nodeOut_4_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_nodeOut_4_d_ready; // @[MixedNode.scala:542:17]
wire x1_nodeOut_4_d_valid = auto_out_5_d_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] x1_nodeOut_4_d_bits_opcode = auto_out_5_d_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [1:0] x1_nodeOut_4_d_bits_param = auto_out_5_d_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] x1_nodeOut_4_d_bits_size = auto_out_5_d_bits_size_0; // @[CacheCork.scala:42:9]
wire [4:0] x1_nodeOut_4_d_bits_source = auto_out_5_d_bits_source_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_4_d_bits_sink = auto_out_5_d_bits_sink_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_4_d_bits_denied = auto_out_5_d_bits_denied_0; // @[CacheCork.scala:42:9]
wire [63:0] x1_nodeOut_4_d_bits_data = auto_out_5_d_bits_data_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_4_d_bits_corrupt = auto_out_5_d_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_3_a_ready = auto_out_4_a_ready_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_3_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_3_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_3_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_3_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_nodeOut_3_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_nodeOut_3_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_nodeOut_3_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_nodeOut_3_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_nodeOut_3_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_nodeOut_3_d_ready; // @[MixedNode.scala:542:17]
wire x1_nodeOut_3_d_valid = auto_out_4_d_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] x1_nodeOut_3_d_bits_opcode = auto_out_4_d_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [1:0] x1_nodeOut_3_d_bits_param = auto_out_4_d_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] x1_nodeOut_3_d_bits_size = auto_out_4_d_bits_size_0; // @[CacheCork.scala:42:9]
wire [4:0] x1_nodeOut_3_d_bits_source = auto_out_4_d_bits_source_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_3_d_bits_sink = auto_out_4_d_bits_sink_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_3_d_bits_denied = auto_out_4_d_bits_denied_0; // @[CacheCork.scala:42:9]
wire [63:0] x1_nodeOut_3_d_bits_data = auto_out_4_d_bits_data_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_3_d_bits_corrupt = auto_out_4_d_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_2_a_ready = auto_out_3_a_ready_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_2_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_2_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_2_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_2_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_nodeOut_2_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_nodeOut_2_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_nodeOut_2_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_nodeOut_2_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_nodeOut_2_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_nodeOut_2_d_ready; // @[MixedNode.scala:542:17]
wire x1_nodeOut_2_d_valid = auto_out_3_d_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] x1_nodeOut_2_d_bits_opcode = auto_out_3_d_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [1:0] x1_nodeOut_2_d_bits_param = auto_out_3_d_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] x1_nodeOut_2_d_bits_size = auto_out_3_d_bits_size_0; // @[CacheCork.scala:42:9]
wire [4:0] x1_nodeOut_2_d_bits_source = auto_out_3_d_bits_source_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_2_d_bits_sink = auto_out_3_d_bits_sink_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_2_d_bits_denied = auto_out_3_d_bits_denied_0; // @[CacheCork.scala:42:9]
wire [63:0] x1_nodeOut_2_d_bits_data = auto_out_3_d_bits_data_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_2_d_bits_corrupt = auto_out_3_d_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_1_a_ready = auto_out_2_a_ready_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_1_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_1_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_1_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_1_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_nodeOut_1_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_nodeOut_1_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_nodeOut_1_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_nodeOut_1_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_nodeOut_1_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_nodeOut_1_d_ready; // @[MixedNode.scala:542:17]
wire x1_nodeOut_1_d_valid = auto_out_2_d_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] x1_nodeOut_1_d_bits_opcode = auto_out_2_d_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [1:0] x1_nodeOut_1_d_bits_param = auto_out_2_d_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] x1_nodeOut_1_d_bits_size = auto_out_2_d_bits_size_0; // @[CacheCork.scala:42:9]
wire [4:0] x1_nodeOut_1_d_bits_source = auto_out_2_d_bits_source_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_1_d_bits_sink = auto_out_2_d_bits_sink_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_1_d_bits_denied = auto_out_2_d_bits_denied_0; // @[CacheCork.scala:42:9]
wire [63:0] x1_nodeOut_1_d_bits_data = auto_out_2_d_bits_data_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_1_d_bits_corrupt = auto_out_2_d_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[CacheCork.scala:42:9]
wire [4:0] x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[CacheCork.scala:42:9]
wire [63:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[CacheCork.scala:42:9]
wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[CacheCork.scala:42:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [1:0] nodeOut_d_bits_param = auto_out_0_d_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[CacheCork.scala:42:9]
wire [4:0] nodeOut_d_bits_source = auto_out_0_d_bits_source_0; // @[CacheCork.scala:42:9]
wire nodeOut_d_bits_sink = auto_out_0_d_bits_sink_0; // @[CacheCork.scala:42:9]
wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[CacheCork.scala:42:9]
wire [63:0] nodeOut_d_bits_data = auto_out_0_d_bits_data_0; // @[CacheCork.scala:42:9]
wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire auto_in_7_a_ready_0; // @[CacheCork.scala:42:9]
wire auto_in_7_c_ready_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_7_d_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [1:0] auto_in_7_d_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_7_d_bits_size_0; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_7_d_bits_source_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_7_d_bits_sink_0; // @[CacheCork.scala:42:9]
wire auto_in_7_d_bits_denied_0; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_7_d_bits_data_0; // @[CacheCork.scala:42:9]
wire auto_in_7_d_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire auto_in_7_d_valid_0; // @[CacheCork.scala:42:9]
wire auto_in_6_a_ready_0; // @[CacheCork.scala:42:9]
wire auto_in_6_c_ready_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_6_d_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [1:0] auto_in_6_d_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_6_d_bits_size_0; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_6_d_bits_source_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_6_d_bits_sink_0; // @[CacheCork.scala:42:9]
wire auto_in_6_d_bits_denied_0; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_6_d_bits_data_0; // @[CacheCork.scala:42:9]
wire auto_in_6_d_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire auto_in_6_d_valid_0; // @[CacheCork.scala:42:9]
wire auto_in_5_a_ready_0; // @[CacheCork.scala:42:9]
wire auto_in_5_c_ready_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_5_d_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [1:0] auto_in_5_d_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_5_d_bits_size_0; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_5_d_bits_source_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_5_d_bits_sink_0; // @[CacheCork.scala:42:9]
wire auto_in_5_d_bits_denied_0; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_5_d_bits_data_0; // @[CacheCork.scala:42:9]
wire auto_in_5_d_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire auto_in_5_d_valid_0; // @[CacheCork.scala:42:9]
wire auto_in_4_a_ready_0; // @[CacheCork.scala:42:9]
wire auto_in_4_c_ready_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_4_d_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [1:0] auto_in_4_d_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_4_d_bits_size_0; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_4_d_bits_source_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_4_d_bits_sink_0; // @[CacheCork.scala:42:9]
wire auto_in_4_d_bits_denied_0; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_4_d_bits_data_0; // @[CacheCork.scala:42:9]
wire auto_in_4_d_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire auto_in_4_d_valid_0; // @[CacheCork.scala:42:9]
wire auto_in_3_a_ready_0; // @[CacheCork.scala:42:9]
wire auto_in_3_c_ready_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_3_d_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [1:0] auto_in_3_d_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_3_d_bits_size_0; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_3_d_bits_source_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_3_d_bits_sink_0; // @[CacheCork.scala:42:9]
wire auto_in_3_d_bits_denied_0; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_3_d_bits_data_0; // @[CacheCork.scala:42:9]
wire auto_in_3_d_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire auto_in_3_d_valid_0; // @[CacheCork.scala:42:9]
wire auto_in_2_a_ready_0; // @[CacheCork.scala:42:9]
wire auto_in_2_c_ready_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_2_d_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [1:0] auto_in_2_d_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_2_d_bits_size_0; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_2_d_bits_source_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_2_d_bits_sink_0; // @[CacheCork.scala:42:9]
wire auto_in_2_d_bits_denied_0; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_2_d_bits_data_0; // @[CacheCork.scala:42:9]
wire auto_in_2_d_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire auto_in_2_d_valid_0; // @[CacheCork.scala:42:9]
wire auto_in_1_a_ready_0; // @[CacheCork.scala:42:9]
wire auto_in_1_c_ready_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_1_d_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [1:0] auto_in_1_d_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_1_d_bits_size_0; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_1_d_bits_source_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_1_d_bits_sink_0; // @[CacheCork.scala:42:9]
wire auto_in_1_d_bits_denied_0; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_1_d_bits_data_0; // @[CacheCork.scala:42:9]
wire auto_in_1_d_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire auto_in_1_d_valid_0; // @[CacheCork.scala:42:9]
wire auto_in_0_a_ready_0; // @[CacheCork.scala:42:9]
wire auto_in_0_c_ready_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_0_d_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [1:0] auto_in_0_d_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_0_d_bits_size_0; // @[CacheCork.scala:42:9]
wire [3:0] auto_in_0_d_bits_source_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_in_0_d_bits_sink_0; // @[CacheCork.scala:42:9]
wire auto_in_0_d_bits_denied_0; // @[CacheCork.scala:42:9]
wire [63:0] auto_in_0_d_bits_data_0; // @[CacheCork.scala:42:9]
wire auto_in_0_d_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire auto_in_0_d_valid_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_7_a_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_7_a_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_7_a_bits_size_0; // @[CacheCork.scala:42:9]
wire [4:0] auto_out_7_a_bits_source_0; // @[CacheCork.scala:42:9]
wire [31:0] auto_out_7_a_bits_address_0; // @[CacheCork.scala:42:9]
wire [7:0] auto_out_7_a_bits_mask_0; // @[CacheCork.scala:42:9]
wire [63:0] auto_out_7_a_bits_data_0; // @[CacheCork.scala:42:9]
wire auto_out_7_a_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire auto_out_7_a_valid_0; // @[CacheCork.scala:42:9]
wire auto_out_7_d_ready_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_6_a_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_6_a_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_6_a_bits_size_0; // @[CacheCork.scala:42:9]
wire [4:0] auto_out_6_a_bits_source_0; // @[CacheCork.scala:42:9]
wire [31:0] auto_out_6_a_bits_address_0; // @[CacheCork.scala:42:9]
wire [7:0] auto_out_6_a_bits_mask_0; // @[CacheCork.scala:42:9]
wire [63:0] auto_out_6_a_bits_data_0; // @[CacheCork.scala:42:9]
wire auto_out_6_a_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire auto_out_6_a_valid_0; // @[CacheCork.scala:42:9]
wire auto_out_6_d_ready_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_5_a_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_5_a_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_5_a_bits_size_0; // @[CacheCork.scala:42:9]
wire [4:0] auto_out_5_a_bits_source_0; // @[CacheCork.scala:42:9]
wire [31:0] auto_out_5_a_bits_address_0; // @[CacheCork.scala:42:9]
wire [7:0] auto_out_5_a_bits_mask_0; // @[CacheCork.scala:42:9]
wire [63:0] auto_out_5_a_bits_data_0; // @[CacheCork.scala:42:9]
wire auto_out_5_a_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire auto_out_5_a_valid_0; // @[CacheCork.scala:42:9]
wire auto_out_5_d_ready_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_4_a_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_4_a_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_4_a_bits_size_0; // @[CacheCork.scala:42:9]
wire [4:0] auto_out_4_a_bits_source_0; // @[CacheCork.scala:42:9]
wire [31:0] auto_out_4_a_bits_address_0; // @[CacheCork.scala:42:9]
wire [7:0] auto_out_4_a_bits_mask_0; // @[CacheCork.scala:42:9]
wire [63:0] auto_out_4_a_bits_data_0; // @[CacheCork.scala:42:9]
wire auto_out_4_a_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire auto_out_4_a_valid_0; // @[CacheCork.scala:42:9]
wire auto_out_4_d_ready_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_3_a_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_3_a_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_3_a_bits_size_0; // @[CacheCork.scala:42:9]
wire [4:0] auto_out_3_a_bits_source_0; // @[CacheCork.scala:42:9]
wire [31:0] auto_out_3_a_bits_address_0; // @[CacheCork.scala:42:9]
wire [7:0] auto_out_3_a_bits_mask_0; // @[CacheCork.scala:42:9]
wire [63:0] auto_out_3_a_bits_data_0; // @[CacheCork.scala:42:9]
wire auto_out_3_a_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire auto_out_3_a_valid_0; // @[CacheCork.scala:42:9]
wire auto_out_3_d_ready_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_2_a_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_2_a_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_2_a_bits_size_0; // @[CacheCork.scala:42:9]
wire [4:0] auto_out_2_a_bits_source_0; // @[CacheCork.scala:42:9]
wire [31:0] auto_out_2_a_bits_address_0; // @[CacheCork.scala:42:9]
wire [7:0] auto_out_2_a_bits_mask_0; // @[CacheCork.scala:42:9]
wire [63:0] auto_out_2_a_bits_data_0; // @[CacheCork.scala:42:9]
wire auto_out_2_a_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire auto_out_2_a_valid_0; // @[CacheCork.scala:42:9]
wire auto_out_2_d_ready_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_1_a_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_1_a_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_1_a_bits_size_0; // @[CacheCork.scala:42:9]
wire [4:0] auto_out_1_a_bits_source_0; // @[CacheCork.scala:42:9]
wire [31:0] auto_out_1_a_bits_address_0; // @[CacheCork.scala:42:9]
wire [7:0] auto_out_1_a_bits_mask_0; // @[CacheCork.scala:42:9]
wire [63:0] auto_out_1_a_bits_data_0; // @[CacheCork.scala:42:9]
wire auto_out_1_a_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire auto_out_1_a_valid_0; // @[CacheCork.scala:42:9]
wire auto_out_1_d_ready_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_0_a_bits_opcode_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_0_a_bits_param_0; // @[CacheCork.scala:42:9]
wire [2:0] auto_out_0_a_bits_size_0; // @[CacheCork.scala:42:9]
wire [4:0] auto_out_0_a_bits_source_0; // @[CacheCork.scala:42:9]
wire [31:0] auto_out_0_a_bits_address_0; // @[CacheCork.scala:42:9]
wire [7:0] auto_out_0_a_bits_mask_0; // @[CacheCork.scala:42:9]
wire [63:0] auto_out_0_a_bits_data_0; // @[CacheCork.scala:42:9]
wire auto_out_0_a_bits_corrupt_0; // @[CacheCork.scala:42:9]
wire auto_out_0_a_valid_0; // @[CacheCork.scala:42:9]
wire auto_out_0_d_ready_0; // @[CacheCork.scala:42:9]
wire _nodeIn_a_ready_T; // @[CacheCork.scala:79:26]
assign auto_in_0_a_ready_0 = nodeIn_a_ready; // @[CacheCork.scala:42:9]
wire [2:0] a_a_bits_size = nodeIn_a_bits_size; // @[CacheCork.scala:74:23]
wire [2:0] a_d_bits_d_size = nodeIn_a_bits_size; // @[Edges.scala:645:17]
wire [3:0] a_d_bits_d_source = nodeIn_a_bits_source; // @[Edges.scala:645:17]
wire [31:0] a_a_bits_address = nodeIn_a_bits_address; // @[CacheCork.scala:74:23]
wire [31:0] _aWOk_T = nodeIn_a_bits_address; // @[Parameters.scala:137:31]
wire [7:0] a_a_bits_mask = nodeIn_a_bits_mask; // @[CacheCork.scala:74:23]
wire [63:0] a_a_bits_data = nodeIn_a_bits_data; // @[CacheCork.scala:74:23]
wire a_a_bits_corrupt = nodeIn_a_bits_corrupt; // @[CacheCork.scala:74:23]
wire _nodeIn_c_ready_T_1; // @[CacheCork.scala:117:26]
assign auto_in_0_c_ready_0 = nodeIn_c_ready; // @[CacheCork.scala:42:9]
wire [2:0] c_a_bits_a_size = nodeIn_c_bits_size; // @[Edges.scala:480:17]
wire [2:0] _c_a_bits_a_mask_sizeOH_T = nodeIn_c_bits_size; // @[Misc.scala:202:34]
wire [2:0] c_d_bits_d_size = nodeIn_c_bits_size; // @[Edges.scala:677:17]
wire [3:0] c_d_bits_d_source = nodeIn_c_bits_source; // @[Edges.scala:677:17]
wire [31:0] _c_a_bits_legal_T_4 = nodeIn_c_bits_address; // @[Parameters.scala:137:31]
wire [31:0] c_a_bits_a_address = nodeIn_c_bits_address; // @[Edges.scala:480:17]
wire [63:0] c_a_bits_a_data = nodeIn_c_bits_data; // @[Edges.scala:480:17]
wire c_a_bits_a_corrupt = nodeIn_c_bits_corrupt; // @[Edges.scala:480:17]
wire _nodeIn_d_valid_T_4; // @[CacheCork.scala:135:34]
assign auto_in_0_d_valid_0 = nodeIn_d_valid; // @[CacheCork.scala:42:9]
wire [2:0] in_d_bits_opcode; // @[CacheCork.scala:131:24]
assign auto_in_0_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[CacheCork.scala:42:9]
wire [1:0] in_d_bits_param; // @[CacheCork.scala:131:24]
assign auto_in_0_d_bits_param_0 = nodeIn_d_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] in_d_bits_size; // @[CacheCork.scala:131:24]
assign auto_in_0_d_bits_size_0 = nodeIn_d_bits_size; // @[CacheCork.scala:42:9]
wire [3:0] in_d_bits_source; // @[CacheCork.scala:131:24]
assign auto_in_0_d_bits_source_0 = nodeIn_d_bits_source; // @[CacheCork.scala:42:9]
wire [2:0] _nodeIn_d_bits_sink_T; // @[package.scala:88:42]
assign auto_in_0_d_bits_sink_0 = nodeIn_d_bits_sink; // @[CacheCork.scala:42:9]
wire in_d_bits_denied; // @[CacheCork.scala:131:24]
assign auto_in_0_d_bits_denied_0 = nodeIn_d_bits_denied; // @[CacheCork.scala:42:9]
wire [63:0] in_d_bits_data; // @[CacheCork.scala:131:24]
assign auto_in_0_d_bits_data_0 = nodeIn_d_bits_data; // @[CacheCork.scala:42:9]
wire in_d_bits_corrupt; // @[CacheCork.scala:131:24]
assign auto_in_0_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[CacheCork.scala:42:9]
wire _pool_io_free_valid_T = nodeIn_e_valid; // @[Decoupled.scala:51:35]
wire _nodeIn_a_ready_T_1; // @[CacheCork.scala:79:26]
assign auto_in_1_a_ready_0 = nodeIn_1_a_ready; // @[CacheCork.scala:42:9]
wire [2:0] a_a_1_bits_size = nodeIn_1_a_bits_size; // @[CacheCork.scala:74:23]
wire [2:0] a_d_bits_d_1_size = nodeIn_1_a_bits_size; // @[Edges.scala:645:17]
wire [3:0] a_d_bits_d_1_source = nodeIn_1_a_bits_source; // @[Edges.scala:645:17]
wire [31:0] a_a_1_bits_address = nodeIn_1_a_bits_address; // @[CacheCork.scala:74:23]
wire [31:0] _aWOk_T_5 = nodeIn_1_a_bits_address; // @[Parameters.scala:137:31]
wire [7:0] a_a_1_bits_mask = nodeIn_1_a_bits_mask; // @[CacheCork.scala:74:23]
wire [63:0] a_a_1_bits_data = nodeIn_1_a_bits_data; // @[CacheCork.scala:74:23]
wire a_a_1_bits_corrupt = nodeIn_1_a_bits_corrupt; // @[CacheCork.scala:74:23]
wire _nodeIn_c_ready_T_3; // @[CacheCork.scala:117:26]
assign auto_in_1_c_ready_0 = nodeIn_1_c_ready; // @[CacheCork.scala:42:9]
wire [2:0] c_a_bits_a_1_size = nodeIn_1_c_bits_size; // @[Edges.scala:480:17]
wire [2:0] _c_a_bits_a_mask_sizeOH_T_3 = nodeIn_1_c_bits_size; // @[Misc.scala:202:34]
wire [2:0] c_d_bits_d_1_size = nodeIn_1_c_bits_size; // @[Edges.scala:677:17]
wire [3:0] c_d_bits_d_1_source = nodeIn_1_c_bits_source; // @[Edges.scala:677:17]
wire [31:0] _c_a_bits_legal_T_14 = nodeIn_1_c_bits_address; // @[Parameters.scala:137:31]
wire [31:0] c_a_bits_a_1_address = nodeIn_1_c_bits_address; // @[Edges.scala:480:17]
wire [63:0] c_a_bits_a_1_data = nodeIn_1_c_bits_data; // @[Edges.scala:480:17]
wire c_a_bits_a_1_corrupt = nodeIn_1_c_bits_corrupt; // @[Edges.scala:480:17]
wire _nodeIn_d_valid_T_9; // @[CacheCork.scala:135:34]
assign auto_in_1_d_valid_0 = nodeIn_1_d_valid; // @[CacheCork.scala:42:9]
wire [2:0] in_d_1_bits_opcode; // @[CacheCork.scala:131:24]
assign auto_in_1_d_bits_opcode_0 = nodeIn_1_d_bits_opcode; // @[CacheCork.scala:42:9]
wire [1:0] in_d_1_bits_param; // @[CacheCork.scala:131:24]
assign auto_in_1_d_bits_param_0 = nodeIn_1_d_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] in_d_1_bits_size; // @[CacheCork.scala:131:24]
assign auto_in_1_d_bits_size_0 = nodeIn_1_d_bits_size; // @[CacheCork.scala:42:9]
wire [3:0] in_d_1_bits_source; // @[CacheCork.scala:131:24]
assign auto_in_1_d_bits_source_0 = nodeIn_1_d_bits_source; // @[CacheCork.scala:42:9]
wire [2:0] _nodeIn_d_bits_sink_T_1; // @[package.scala:88:42]
assign auto_in_1_d_bits_sink_0 = nodeIn_1_d_bits_sink; // @[CacheCork.scala:42:9]
wire in_d_1_bits_denied; // @[CacheCork.scala:131:24]
assign auto_in_1_d_bits_denied_0 = nodeIn_1_d_bits_denied; // @[CacheCork.scala:42:9]
wire [63:0] in_d_1_bits_data; // @[CacheCork.scala:131:24]
assign auto_in_1_d_bits_data_0 = nodeIn_1_d_bits_data; // @[CacheCork.scala:42:9]
wire in_d_1_bits_corrupt; // @[CacheCork.scala:131:24]
assign auto_in_1_d_bits_corrupt_0 = nodeIn_1_d_bits_corrupt; // @[CacheCork.scala:42:9]
wire _pool_io_free_valid_T_1 = nodeIn_1_e_valid; // @[Decoupled.scala:51:35]
wire _nodeIn_a_ready_T_2; // @[CacheCork.scala:79:26]
assign auto_in_2_a_ready_0 = nodeIn_2_a_ready; // @[CacheCork.scala:42:9]
wire [2:0] a_a_2_bits_size = nodeIn_2_a_bits_size; // @[CacheCork.scala:74:23]
wire [2:0] a_d_bits_d_2_size = nodeIn_2_a_bits_size; // @[Edges.scala:645:17]
wire [3:0] a_d_bits_d_2_source = nodeIn_2_a_bits_source; // @[Edges.scala:645:17]
wire [31:0] a_a_2_bits_address = nodeIn_2_a_bits_address; // @[CacheCork.scala:74:23]
wire [31:0] _aWOk_T_10 = nodeIn_2_a_bits_address; // @[Parameters.scala:137:31]
wire [7:0] a_a_2_bits_mask = nodeIn_2_a_bits_mask; // @[CacheCork.scala:74:23]
wire [63:0] a_a_2_bits_data = nodeIn_2_a_bits_data; // @[CacheCork.scala:74:23]
wire a_a_2_bits_corrupt = nodeIn_2_a_bits_corrupt; // @[CacheCork.scala:74:23]
wire _nodeIn_c_ready_T_5; // @[CacheCork.scala:117:26]
assign auto_in_2_c_ready_0 = nodeIn_2_c_ready; // @[CacheCork.scala:42:9]
wire [2:0] c_a_bits_a_2_size = nodeIn_2_c_bits_size; // @[Edges.scala:480:17]
wire [2:0] _c_a_bits_a_mask_sizeOH_T_6 = nodeIn_2_c_bits_size; // @[Misc.scala:202:34]
wire [2:0] c_d_bits_d_2_size = nodeIn_2_c_bits_size; // @[Edges.scala:677:17]
wire [3:0] c_d_bits_d_2_source = nodeIn_2_c_bits_source; // @[Edges.scala:677:17]
wire [31:0] _c_a_bits_legal_T_24 = nodeIn_2_c_bits_address; // @[Parameters.scala:137:31]
wire [31:0] c_a_bits_a_2_address = nodeIn_2_c_bits_address; // @[Edges.scala:480:17]
wire [63:0] c_a_bits_a_2_data = nodeIn_2_c_bits_data; // @[Edges.scala:480:17]
wire c_a_bits_a_2_corrupt = nodeIn_2_c_bits_corrupt; // @[Edges.scala:480:17]
wire _nodeIn_d_valid_T_14; // @[CacheCork.scala:135:34]
assign auto_in_2_d_valid_0 = nodeIn_2_d_valid; // @[CacheCork.scala:42:9]
wire [2:0] in_d_2_bits_opcode; // @[CacheCork.scala:131:24]
assign auto_in_2_d_bits_opcode_0 = nodeIn_2_d_bits_opcode; // @[CacheCork.scala:42:9]
wire [1:0] in_d_2_bits_param; // @[CacheCork.scala:131:24]
assign auto_in_2_d_bits_param_0 = nodeIn_2_d_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] in_d_2_bits_size; // @[CacheCork.scala:131:24]
assign auto_in_2_d_bits_size_0 = nodeIn_2_d_bits_size; // @[CacheCork.scala:42:9]
wire [3:0] in_d_2_bits_source; // @[CacheCork.scala:131:24]
assign auto_in_2_d_bits_source_0 = nodeIn_2_d_bits_source; // @[CacheCork.scala:42:9]
wire [2:0] _nodeIn_d_bits_sink_T_2; // @[package.scala:88:42]
assign auto_in_2_d_bits_sink_0 = nodeIn_2_d_bits_sink; // @[CacheCork.scala:42:9]
wire in_d_2_bits_denied; // @[CacheCork.scala:131:24]
assign auto_in_2_d_bits_denied_0 = nodeIn_2_d_bits_denied; // @[CacheCork.scala:42:9]
wire [63:0] in_d_2_bits_data; // @[CacheCork.scala:131:24]
assign auto_in_2_d_bits_data_0 = nodeIn_2_d_bits_data; // @[CacheCork.scala:42:9]
wire in_d_2_bits_corrupt; // @[CacheCork.scala:131:24]
assign auto_in_2_d_bits_corrupt_0 = nodeIn_2_d_bits_corrupt; // @[CacheCork.scala:42:9]
wire _pool_io_free_valid_T_2 = nodeIn_2_e_valid; // @[Decoupled.scala:51:35]
wire _nodeIn_a_ready_T_3; // @[CacheCork.scala:79:26]
assign auto_in_3_a_ready_0 = nodeIn_3_a_ready; // @[CacheCork.scala:42:9]
wire [2:0] a_a_3_bits_size = nodeIn_3_a_bits_size; // @[CacheCork.scala:74:23]
wire [2:0] a_d_bits_d_3_size = nodeIn_3_a_bits_size; // @[Edges.scala:645:17]
wire [3:0] a_d_bits_d_3_source = nodeIn_3_a_bits_source; // @[Edges.scala:645:17]
wire [31:0] a_a_3_bits_address = nodeIn_3_a_bits_address; // @[CacheCork.scala:74:23]
wire [31:0] _aWOk_T_15 = nodeIn_3_a_bits_address; // @[Parameters.scala:137:31]
wire [7:0] a_a_3_bits_mask = nodeIn_3_a_bits_mask; // @[CacheCork.scala:74:23]
wire [63:0] a_a_3_bits_data = nodeIn_3_a_bits_data; // @[CacheCork.scala:74:23]
wire a_a_3_bits_corrupt = nodeIn_3_a_bits_corrupt; // @[CacheCork.scala:74:23]
wire _nodeIn_c_ready_T_7; // @[CacheCork.scala:117:26]
assign auto_in_3_c_ready_0 = nodeIn_3_c_ready; // @[CacheCork.scala:42:9]
wire [2:0] c_a_bits_a_3_size = nodeIn_3_c_bits_size; // @[Edges.scala:480:17]
wire [2:0] _c_a_bits_a_mask_sizeOH_T_9 = nodeIn_3_c_bits_size; // @[Misc.scala:202:34]
wire [2:0] c_d_bits_d_3_size = nodeIn_3_c_bits_size; // @[Edges.scala:677:17]
wire [3:0] c_d_bits_d_3_source = nodeIn_3_c_bits_source; // @[Edges.scala:677:17]
wire [31:0] _c_a_bits_legal_T_34 = nodeIn_3_c_bits_address; // @[Parameters.scala:137:31]
wire [31:0] c_a_bits_a_3_address = nodeIn_3_c_bits_address; // @[Edges.scala:480:17]
wire [63:0] c_a_bits_a_3_data = nodeIn_3_c_bits_data; // @[Edges.scala:480:17]
wire c_a_bits_a_3_corrupt = nodeIn_3_c_bits_corrupt; // @[Edges.scala:480:17]
wire _nodeIn_d_valid_T_19; // @[CacheCork.scala:135:34]
assign auto_in_3_d_valid_0 = nodeIn_3_d_valid; // @[CacheCork.scala:42:9]
wire [2:0] in_d_3_bits_opcode; // @[CacheCork.scala:131:24]
assign auto_in_3_d_bits_opcode_0 = nodeIn_3_d_bits_opcode; // @[CacheCork.scala:42:9]
wire [1:0] in_d_3_bits_param; // @[CacheCork.scala:131:24]
assign auto_in_3_d_bits_param_0 = nodeIn_3_d_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] in_d_3_bits_size; // @[CacheCork.scala:131:24]
assign auto_in_3_d_bits_size_0 = nodeIn_3_d_bits_size; // @[CacheCork.scala:42:9]
wire [3:0] in_d_3_bits_source; // @[CacheCork.scala:131:24]
assign auto_in_3_d_bits_source_0 = nodeIn_3_d_bits_source; // @[CacheCork.scala:42:9]
wire [2:0] _nodeIn_d_bits_sink_T_3; // @[package.scala:88:42]
assign auto_in_3_d_bits_sink_0 = nodeIn_3_d_bits_sink; // @[CacheCork.scala:42:9]
wire in_d_3_bits_denied; // @[CacheCork.scala:131:24]
assign auto_in_3_d_bits_denied_0 = nodeIn_3_d_bits_denied; // @[CacheCork.scala:42:9]
wire [63:0] in_d_3_bits_data; // @[CacheCork.scala:131:24]
assign auto_in_3_d_bits_data_0 = nodeIn_3_d_bits_data; // @[CacheCork.scala:42:9]
wire in_d_3_bits_corrupt; // @[CacheCork.scala:131:24]
assign auto_in_3_d_bits_corrupt_0 = nodeIn_3_d_bits_corrupt; // @[CacheCork.scala:42:9]
wire _pool_io_free_valid_T_3 = nodeIn_3_e_valid; // @[Decoupled.scala:51:35]
wire _nodeIn_a_ready_T_4; // @[CacheCork.scala:79:26]
assign auto_in_4_a_ready_0 = nodeIn_4_a_ready; // @[CacheCork.scala:42:9]
wire [2:0] a_a_4_bits_size = nodeIn_4_a_bits_size; // @[CacheCork.scala:74:23]
wire [2:0] a_d_bits_d_4_size = nodeIn_4_a_bits_size; // @[Edges.scala:645:17]
wire [3:0] a_d_bits_d_4_source = nodeIn_4_a_bits_source; // @[Edges.scala:645:17]
wire [31:0] a_a_4_bits_address = nodeIn_4_a_bits_address; // @[CacheCork.scala:74:23]
wire [31:0] _aWOk_T_20 = nodeIn_4_a_bits_address; // @[Parameters.scala:137:31]
wire [7:0] a_a_4_bits_mask = nodeIn_4_a_bits_mask; // @[CacheCork.scala:74:23]
wire [63:0] a_a_4_bits_data = nodeIn_4_a_bits_data; // @[CacheCork.scala:74:23]
wire a_a_4_bits_corrupt = nodeIn_4_a_bits_corrupt; // @[CacheCork.scala:74:23]
wire _nodeIn_c_ready_T_9; // @[CacheCork.scala:117:26]
assign auto_in_4_c_ready_0 = nodeIn_4_c_ready; // @[CacheCork.scala:42:9]
wire [2:0] c_a_bits_a_4_size = nodeIn_4_c_bits_size; // @[Edges.scala:480:17]
wire [2:0] _c_a_bits_a_mask_sizeOH_T_12 = nodeIn_4_c_bits_size; // @[Misc.scala:202:34]
wire [2:0] c_d_bits_d_4_size = nodeIn_4_c_bits_size; // @[Edges.scala:677:17]
wire [3:0] c_d_bits_d_4_source = nodeIn_4_c_bits_source; // @[Edges.scala:677:17]
wire [31:0] _c_a_bits_legal_T_44 = nodeIn_4_c_bits_address; // @[Parameters.scala:137:31]
wire [31:0] c_a_bits_a_4_address = nodeIn_4_c_bits_address; // @[Edges.scala:480:17]
wire [63:0] c_a_bits_a_4_data = nodeIn_4_c_bits_data; // @[Edges.scala:480:17]
wire c_a_bits_a_4_corrupt = nodeIn_4_c_bits_corrupt; // @[Edges.scala:480:17]
wire _nodeIn_d_valid_T_24; // @[CacheCork.scala:135:34]
assign auto_in_4_d_valid_0 = nodeIn_4_d_valid; // @[CacheCork.scala:42:9]
wire [2:0] in_d_4_bits_opcode; // @[CacheCork.scala:131:24]
assign auto_in_4_d_bits_opcode_0 = nodeIn_4_d_bits_opcode; // @[CacheCork.scala:42:9]
wire [1:0] in_d_4_bits_param; // @[CacheCork.scala:131:24]
assign auto_in_4_d_bits_param_0 = nodeIn_4_d_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] in_d_4_bits_size; // @[CacheCork.scala:131:24]
assign auto_in_4_d_bits_size_0 = nodeIn_4_d_bits_size; // @[CacheCork.scala:42:9]
wire [3:0] in_d_4_bits_source; // @[CacheCork.scala:131:24]
assign auto_in_4_d_bits_source_0 = nodeIn_4_d_bits_source; // @[CacheCork.scala:42:9]
wire [2:0] _nodeIn_d_bits_sink_T_4; // @[package.scala:88:42]
assign auto_in_4_d_bits_sink_0 = nodeIn_4_d_bits_sink; // @[CacheCork.scala:42:9]
wire in_d_4_bits_denied; // @[CacheCork.scala:131:24]
assign auto_in_4_d_bits_denied_0 = nodeIn_4_d_bits_denied; // @[CacheCork.scala:42:9]
wire [63:0] in_d_4_bits_data; // @[CacheCork.scala:131:24]
assign auto_in_4_d_bits_data_0 = nodeIn_4_d_bits_data; // @[CacheCork.scala:42:9]
wire in_d_4_bits_corrupt; // @[CacheCork.scala:131:24]
assign auto_in_4_d_bits_corrupt_0 = nodeIn_4_d_bits_corrupt; // @[CacheCork.scala:42:9]
wire _pool_io_free_valid_T_4 = nodeIn_4_e_valid; // @[Decoupled.scala:51:35]
wire _nodeIn_a_ready_T_5; // @[CacheCork.scala:79:26]
assign auto_in_5_a_ready_0 = nodeIn_5_a_ready; // @[CacheCork.scala:42:9]
wire [2:0] a_a_5_bits_size = nodeIn_5_a_bits_size; // @[CacheCork.scala:74:23]
wire [2:0] a_d_bits_d_5_size = nodeIn_5_a_bits_size; // @[Edges.scala:645:17]
wire [3:0] a_d_bits_d_5_source = nodeIn_5_a_bits_source; // @[Edges.scala:645:17]
wire [31:0] a_a_5_bits_address = nodeIn_5_a_bits_address; // @[CacheCork.scala:74:23]
wire [31:0] _aWOk_T_25 = nodeIn_5_a_bits_address; // @[Parameters.scala:137:31]
wire [7:0] a_a_5_bits_mask = nodeIn_5_a_bits_mask; // @[CacheCork.scala:74:23]
wire [63:0] a_a_5_bits_data = nodeIn_5_a_bits_data; // @[CacheCork.scala:74:23]
wire a_a_5_bits_corrupt = nodeIn_5_a_bits_corrupt; // @[CacheCork.scala:74:23]
wire _nodeIn_c_ready_T_11; // @[CacheCork.scala:117:26]
assign auto_in_5_c_ready_0 = nodeIn_5_c_ready; // @[CacheCork.scala:42:9]
wire [2:0] c_a_bits_a_5_size = nodeIn_5_c_bits_size; // @[Edges.scala:480:17]
wire [2:0] _c_a_bits_a_mask_sizeOH_T_15 = nodeIn_5_c_bits_size; // @[Misc.scala:202:34]
wire [2:0] c_d_bits_d_5_size = nodeIn_5_c_bits_size; // @[Edges.scala:677:17]
wire [3:0] c_d_bits_d_5_source = nodeIn_5_c_bits_source; // @[Edges.scala:677:17]
wire [31:0] _c_a_bits_legal_T_54 = nodeIn_5_c_bits_address; // @[Parameters.scala:137:31]
wire [31:0] c_a_bits_a_5_address = nodeIn_5_c_bits_address; // @[Edges.scala:480:17]
wire [63:0] c_a_bits_a_5_data = nodeIn_5_c_bits_data; // @[Edges.scala:480:17]
wire c_a_bits_a_5_corrupt = nodeIn_5_c_bits_corrupt; // @[Edges.scala:480:17]
wire _nodeIn_d_valid_T_29; // @[CacheCork.scala:135:34]
assign auto_in_5_d_valid_0 = nodeIn_5_d_valid; // @[CacheCork.scala:42:9]
wire [2:0] in_d_5_bits_opcode; // @[CacheCork.scala:131:24]
assign auto_in_5_d_bits_opcode_0 = nodeIn_5_d_bits_opcode; // @[CacheCork.scala:42:9]
wire [1:0] in_d_5_bits_param; // @[CacheCork.scala:131:24]
assign auto_in_5_d_bits_param_0 = nodeIn_5_d_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] in_d_5_bits_size; // @[CacheCork.scala:131:24]
assign auto_in_5_d_bits_size_0 = nodeIn_5_d_bits_size; // @[CacheCork.scala:42:9]
wire [3:0] in_d_5_bits_source; // @[CacheCork.scala:131:24]
assign auto_in_5_d_bits_source_0 = nodeIn_5_d_bits_source; // @[CacheCork.scala:42:9]
wire [2:0] _nodeIn_d_bits_sink_T_5; // @[package.scala:88:42]
assign auto_in_5_d_bits_sink_0 = nodeIn_5_d_bits_sink; // @[CacheCork.scala:42:9]
wire in_d_5_bits_denied; // @[CacheCork.scala:131:24]
assign auto_in_5_d_bits_denied_0 = nodeIn_5_d_bits_denied; // @[CacheCork.scala:42:9]
wire [63:0] in_d_5_bits_data; // @[CacheCork.scala:131:24]
assign auto_in_5_d_bits_data_0 = nodeIn_5_d_bits_data; // @[CacheCork.scala:42:9]
wire in_d_5_bits_corrupt; // @[CacheCork.scala:131:24]
assign auto_in_5_d_bits_corrupt_0 = nodeIn_5_d_bits_corrupt; // @[CacheCork.scala:42:9]
wire _pool_io_free_valid_T_5 = nodeIn_5_e_valid; // @[Decoupled.scala:51:35]
wire _nodeIn_a_ready_T_6; // @[CacheCork.scala:79:26]
assign auto_in_6_a_ready_0 = nodeIn_6_a_ready; // @[CacheCork.scala:42:9]
wire [2:0] a_a_6_bits_size = nodeIn_6_a_bits_size; // @[CacheCork.scala:74:23]
wire [2:0] a_d_bits_d_6_size = nodeIn_6_a_bits_size; // @[Edges.scala:645:17]
wire [3:0] a_d_bits_d_6_source = nodeIn_6_a_bits_source; // @[Edges.scala:645:17]
wire [31:0] a_a_6_bits_address = nodeIn_6_a_bits_address; // @[CacheCork.scala:74:23]
wire [31:0] _aWOk_T_30 = nodeIn_6_a_bits_address; // @[Parameters.scala:137:31]
wire [7:0] a_a_6_bits_mask = nodeIn_6_a_bits_mask; // @[CacheCork.scala:74:23]
wire [63:0] a_a_6_bits_data = nodeIn_6_a_bits_data; // @[CacheCork.scala:74:23]
wire a_a_6_bits_corrupt = nodeIn_6_a_bits_corrupt; // @[CacheCork.scala:74:23]
wire _nodeIn_c_ready_T_13; // @[CacheCork.scala:117:26]
assign auto_in_6_c_ready_0 = nodeIn_6_c_ready; // @[CacheCork.scala:42:9]
wire [2:0] c_a_bits_a_6_size = nodeIn_6_c_bits_size; // @[Edges.scala:480:17]
wire [2:0] _c_a_bits_a_mask_sizeOH_T_18 = nodeIn_6_c_bits_size; // @[Misc.scala:202:34]
wire [2:0] c_d_bits_d_6_size = nodeIn_6_c_bits_size; // @[Edges.scala:677:17]
wire [3:0] c_d_bits_d_6_source = nodeIn_6_c_bits_source; // @[Edges.scala:677:17]
wire [31:0] _c_a_bits_legal_T_64 = nodeIn_6_c_bits_address; // @[Parameters.scala:137:31]
wire [31:0] c_a_bits_a_6_address = nodeIn_6_c_bits_address; // @[Edges.scala:480:17]
wire [63:0] c_a_bits_a_6_data = nodeIn_6_c_bits_data; // @[Edges.scala:480:17]
wire c_a_bits_a_6_corrupt = nodeIn_6_c_bits_corrupt; // @[Edges.scala:480:17]
wire _nodeIn_d_valid_T_34; // @[CacheCork.scala:135:34]
assign auto_in_6_d_valid_0 = nodeIn_6_d_valid; // @[CacheCork.scala:42:9]
wire [2:0] in_d_6_bits_opcode; // @[CacheCork.scala:131:24]
assign auto_in_6_d_bits_opcode_0 = nodeIn_6_d_bits_opcode; // @[CacheCork.scala:42:9]
wire [1:0] in_d_6_bits_param; // @[CacheCork.scala:131:24]
assign auto_in_6_d_bits_param_0 = nodeIn_6_d_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] in_d_6_bits_size; // @[CacheCork.scala:131:24]
assign auto_in_6_d_bits_size_0 = nodeIn_6_d_bits_size; // @[CacheCork.scala:42:9]
wire [3:0] in_d_6_bits_source; // @[CacheCork.scala:131:24]
assign auto_in_6_d_bits_source_0 = nodeIn_6_d_bits_source; // @[CacheCork.scala:42:9]
wire [2:0] _nodeIn_d_bits_sink_T_6; // @[package.scala:88:42]
assign auto_in_6_d_bits_sink_0 = nodeIn_6_d_bits_sink; // @[CacheCork.scala:42:9]
wire in_d_6_bits_denied; // @[CacheCork.scala:131:24]
assign auto_in_6_d_bits_denied_0 = nodeIn_6_d_bits_denied; // @[CacheCork.scala:42:9]
wire [63:0] in_d_6_bits_data; // @[CacheCork.scala:131:24]
assign auto_in_6_d_bits_data_0 = nodeIn_6_d_bits_data; // @[CacheCork.scala:42:9]
wire in_d_6_bits_corrupt; // @[CacheCork.scala:131:24]
assign auto_in_6_d_bits_corrupt_0 = nodeIn_6_d_bits_corrupt; // @[CacheCork.scala:42:9]
wire _pool_io_free_valid_T_6 = nodeIn_6_e_valid; // @[Decoupled.scala:51:35]
wire _nodeIn_a_ready_T_7; // @[CacheCork.scala:79:26]
assign auto_in_7_a_ready_0 = nodeIn_7_a_ready; // @[CacheCork.scala:42:9]
wire [2:0] a_a_7_bits_size = nodeIn_7_a_bits_size; // @[CacheCork.scala:74:23]
wire [2:0] a_d_bits_d_7_size = nodeIn_7_a_bits_size; // @[Edges.scala:645:17]
wire [3:0] a_d_bits_d_7_source = nodeIn_7_a_bits_source; // @[Edges.scala:645:17]
wire [31:0] a_a_7_bits_address = nodeIn_7_a_bits_address; // @[CacheCork.scala:74:23]
wire [31:0] _aWOk_T_35 = nodeIn_7_a_bits_address; // @[Parameters.scala:137:31]
wire [7:0] a_a_7_bits_mask = nodeIn_7_a_bits_mask; // @[CacheCork.scala:74:23]
wire [63:0] a_a_7_bits_data = nodeIn_7_a_bits_data; // @[CacheCork.scala:74:23]
wire a_a_7_bits_corrupt = nodeIn_7_a_bits_corrupt; // @[CacheCork.scala:74:23]
wire _nodeIn_c_ready_T_15; // @[CacheCork.scala:117:26]
assign auto_in_7_c_ready_0 = nodeIn_7_c_ready; // @[CacheCork.scala:42:9]
wire [2:0] c_a_bits_a_7_size = nodeIn_7_c_bits_size; // @[Edges.scala:480:17]
wire [2:0] _c_a_bits_a_mask_sizeOH_T_21 = nodeIn_7_c_bits_size; // @[Misc.scala:202:34]
wire [2:0] c_d_bits_d_7_size = nodeIn_7_c_bits_size; // @[Edges.scala:677:17]
wire [3:0] c_d_bits_d_7_source = nodeIn_7_c_bits_source; // @[Edges.scala:677:17]
wire [31:0] _c_a_bits_legal_T_74 = nodeIn_7_c_bits_address; // @[Parameters.scala:137:31]
wire [31:0] c_a_bits_a_7_address = nodeIn_7_c_bits_address; // @[Edges.scala:480:17]
wire [63:0] c_a_bits_a_7_data = nodeIn_7_c_bits_data; // @[Edges.scala:480:17]
wire c_a_bits_a_7_corrupt = nodeIn_7_c_bits_corrupt; // @[Edges.scala:480:17]
wire _nodeIn_d_valid_T_39; // @[CacheCork.scala:135:34]
assign auto_in_7_d_valid_0 = nodeIn_7_d_valid; // @[CacheCork.scala:42:9]
wire [2:0] in_d_7_bits_opcode; // @[CacheCork.scala:131:24]
assign auto_in_7_d_bits_opcode_0 = nodeIn_7_d_bits_opcode; // @[CacheCork.scala:42:9]
wire [1:0] in_d_7_bits_param; // @[CacheCork.scala:131:24]
assign auto_in_7_d_bits_param_0 = nodeIn_7_d_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] in_d_7_bits_size; // @[CacheCork.scala:131:24]
assign auto_in_7_d_bits_size_0 = nodeIn_7_d_bits_size; // @[CacheCork.scala:42:9]
wire [3:0] in_d_7_bits_source; // @[CacheCork.scala:131:24]
assign auto_in_7_d_bits_source_0 = nodeIn_7_d_bits_source; // @[CacheCork.scala:42:9]
wire [2:0] _nodeIn_d_bits_sink_T_7; // @[package.scala:88:42]
assign auto_in_7_d_bits_sink_0 = nodeIn_7_d_bits_sink; // @[CacheCork.scala:42:9]
wire in_d_7_bits_denied; // @[CacheCork.scala:131:24]
assign auto_in_7_d_bits_denied_0 = nodeIn_7_d_bits_denied; // @[CacheCork.scala:42:9]
wire [63:0] in_d_7_bits_data; // @[CacheCork.scala:131:24]
assign auto_in_7_d_bits_data_0 = nodeIn_7_d_bits_data; // @[CacheCork.scala:42:9]
wire in_d_7_bits_corrupt; // @[CacheCork.scala:131:24]
assign auto_in_7_d_bits_corrupt_0 = nodeIn_7_d_bits_corrupt; // @[CacheCork.scala:42:9]
wire _pool_io_free_valid_T_7 = nodeIn_7_e_valid; // @[Decoupled.scala:51:35]
wire _nodeOut_a_valid_T_4; // @[Arbiter.scala:96:24]
assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[CacheCork.scala:42:9]
wire [2:0] _nodeOut_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[CacheCork.scala:42:9]
wire [2:0] _nodeOut_a_bits_WIRE_param; // @[Mux.scala:30:73]
assign auto_out_0_a_bits_param_0 = nodeOut_a_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] _nodeOut_a_bits_WIRE_size; // @[Mux.scala:30:73]
assign auto_out_0_a_bits_size_0 = nodeOut_a_bits_size; // @[CacheCork.scala:42:9]
wire [4:0] _nodeOut_a_bits_WIRE_source; // @[Mux.scala:30:73]
assign auto_out_0_a_bits_source_0 = nodeOut_a_bits_source; // @[CacheCork.scala:42:9]
wire [31:0] _nodeOut_a_bits_WIRE_address; // @[Mux.scala:30:73]
assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[CacheCork.scala:42:9]
wire [7:0] _nodeOut_a_bits_WIRE_mask; // @[Mux.scala:30:73]
assign auto_out_0_a_bits_mask_0 = nodeOut_a_bits_mask; // @[CacheCork.scala:42:9]
wire [63:0] _nodeOut_a_bits_WIRE_data; // @[Mux.scala:30:73]
assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[CacheCork.scala:42:9]
wire _nodeOut_a_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign auto_out_0_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[CacheCork.scala:42:9]
wire d_d_ready; // @[CacheCork.scala:141:23]
assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[CacheCork.scala:42:9]
wire d_d_valid = nodeOut_d_valid; // @[CacheCork.scala:141:23]
wire [2:0] d_d_bits_size = nodeOut_d_bits_size; // @[CacheCork.scala:141:23]
wire d_d_bits_denied = nodeOut_d_bits_denied; // @[CacheCork.scala:141:23]
wire [63:0] d_d_bits_data = nodeOut_d_bits_data; // @[CacheCork.scala:141:23]
wire d_d_bits_corrupt = nodeOut_d_bits_corrupt; // @[CacheCork.scala:141:23]
wire _nodeOut_a_valid_T_9; // @[Arbiter.scala:96:24]
assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[CacheCork.scala:42:9]
wire [2:0] _nodeOut_a_bits_WIRE_11_opcode; // @[Mux.scala:30:73]
assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[CacheCork.scala:42:9]
wire [2:0] _nodeOut_a_bits_WIRE_11_param; // @[Mux.scala:30:73]
assign auto_out_1_a_bits_param_0 = x1_nodeOut_a_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] _nodeOut_a_bits_WIRE_11_size; // @[Mux.scala:30:73]
assign auto_out_1_a_bits_size_0 = x1_nodeOut_a_bits_size; // @[CacheCork.scala:42:9]
wire [4:0] _nodeOut_a_bits_WIRE_11_source; // @[Mux.scala:30:73]
assign auto_out_1_a_bits_source_0 = x1_nodeOut_a_bits_source; // @[CacheCork.scala:42:9]
wire [31:0] _nodeOut_a_bits_WIRE_11_address; // @[Mux.scala:30:73]
assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[CacheCork.scala:42:9]
wire [7:0] _nodeOut_a_bits_WIRE_11_mask; // @[Mux.scala:30:73]
assign auto_out_1_a_bits_mask_0 = x1_nodeOut_a_bits_mask; // @[CacheCork.scala:42:9]
wire [63:0] _nodeOut_a_bits_WIRE_11_data; // @[Mux.scala:30:73]
assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[CacheCork.scala:42:9]
wire _nodeOut_a_bits_WIRE_11_corrupt; // @[Mux.scala:30:73]
assign auto_out_1_a_bits_corrupt_0 = x1_nodeOut_a_bits_corrupt; // @[CacheCork.scala:42:9]
wire d_d_1_ready; // @[CacheCork.scala:141:23]
assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[CacheCork.scala:42:9]
wire d_d_1_valid = x1_nodeOut_d_valid; // @[CacheCork.scala:141:23]
wire [2:0] d_d_1_bits_size = x1_nodeOut_d_bits_size; // @[CacheCork.scala:141:23]
wire d_d_1_bits_denied = x1_nodeOut_d_bits_denied; // @[CacheCork.scala:141:23]
wire [63:0] d_d_1_bits_data = x1_nodeOut_d_bits_data; // @[CacheCork.scala:141:23]
wire d_d_1_bits_corrupt = x1_nodeOut_d_bits_corrupt; // @[CacheCork.scala:141:23]
wire _nodeOut_a_valid_T_14; // @[Arbiter.scala:96:24]
assign auto_out_2_a_valid_0 = x1_nodeOut_1_a_valid; // @[CacheCork.scala:42:9]
wire [2:0] _nodeOut_a_bits_WIRE_22_opcode; // @[Mux.scala:30:73]
assign auto_out_2_a_bits_opcode_0 = x1_nodeOut_1_a_bits_opcode; // @[CacheCork.scala:42:9]
wire [2:0] _nodeOut_a_bits_WIRE_22_param; // @[Mux.scala:30:73]
assign auto_out_2_a_bits_param_0 = x1_nodeOut_1_a_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] _nodeOut_a_bits_WIRE_22_size; // @[Mux.scala:30:73]
assign auto_out_2_a_bits_size_0 = x1_nodeOut_1_a_bits_size; // @[CacheCork.scala:42:9]
wire [4:0] _nodeOut_a_bits_WIRE_22_source; // @[Mux.scala:30:73]
assign auto_out_2_a_bits_source_0 = x1_nodeOut_1_a_bits_source; // @[CacheCork.scala:42:9]
wire [31:0] _nodeOut_a_bits_WIRE_22_address; // @[Mux.scala:30:73]
assign auto_out_2_a_bits_address_0 = x1_nodeOut_1_a_bits_address; // @[CacheCork.scala:42:9]
wire [7:0] _nodeOut_a_bits_WIRE_22_mask; // @[Mux.scala:30:73]
assign auto_out_2_a_bits_mask_0 = x1_nodeOut_1_a_bits_mask; // @[CacheCork.scala:42:9]
wire [63:0] _nodeOut_a_bits_WIRE_22_data; // @[Mux.scala:30:73]
assign auto_out_2_a_bits_data_0 = x1_nodeOut_1_a_bits_data; // @[CacheCork.scala:42:9]
wire _nodeOut_a_bits_WIRE_22_corrupt; // @[Mux.scala:30:73]
assign auto_out_2_a_bits_corrupt_0 = x1_nodeOut_1_a_bits_corrupt; // @[CacheCork.scala:42:9]
wire d_d_2_ready; // @[CacheCork.scala:141:23]
assign auto_out_2_d_ready_0 = x1_nodeOut_1_d_ready; // @[CacheCork.scala:42:9]
wire d_d_2_valid = x1_nodeOut_1_d_valid; // @[CacheCork.scala:141:23]
wire [2:0] d_d_2_bits_size = x1_nodeOut_1_d_bits_size; // @[CacheCork.scala:141:23]
wire d_d_2_bits_denied = x1_nodeOut_1_d_bits_denied; // @[CacheCork.scala:141:23]
wire [63:0] d_d_2_bits_data = x1_nodeOut_1_d_bits_data; // @[CacheCork.scala:141:23]
wire d_d_2_bits_corrupt = x1_nodeOut_1_d_bits_corrupt; // @[CacheCork.scala:141:23]
wire _nodeOut_a_valid_T_19; // @[Arbiter.scala:96:24]
assign auto_out_3_a_valid_0 = x1_nodeOut_2_a_valid; // @[CacheCork.scala:42:9]
wire [2:0] _nodeOut_a_bits_WIRE_33_opcode; // @[Mux.scala:30:73]
assign auto_out_3_a_bits_opcode_0 = x1_nodeOut_2_a_bits_opcode; // @[CacheCork.scala:42:9]
wire [2:0] _nodeOut_a_bits_WIRE_33_param; // @[Mux.scala:30:73]
assign auto_out_3_a_bits_param_0 = x1_nodeOut_2_a_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] _nodeOut_a_bits_WIRE_33_size; // @[Mux.scala:30:73]
assign auto_out_3_a_bits_size_0 = x1_nodeOut_2_a_bits_size; // @[CacheCork.scala:42:9]
wire [4:0] _nodeOut_a_bits_WIRE_33_source; // @[Mux.scala:30:73]
assign auto_out_3_a_bits_source_0 = x1_nodeOut_2_a_bits_source; // @[CacheCork.scala:42:9]
wire [31:0] _nodeOut_a_bits_WIRE_33_address; // @[Mux.scala:30:73]
assign auto_out_3_a_bits_address_0 = x1_nodeOut_2_a_bits_address; // @[CacheCork.scala:42:9]
wire [7:0] _nodeOut_a_bits_WIRE_33_mask; // @[Mux.scala:30:73]
assign auto_out_3_a_bits_mask_0 = x1_nodeOut_2_a_bits_mask; // @[CacheCork.scala:42:9]
wire [63:0] _nodeOut_a_bits_WIRE_33_data; // @[Mux.scala:30:73]
assign auto_out_3_a_bits_data_0 = x1_nodeOut_2_a_bits_data; // @[CacheCork.scala:42:9]
wire _nodeOut_a_bits_WIRE_33_corrupt; // @[Mux.scala:30:73]
assign auto_out_3_a_bits_corrupt_0 = x1_nodeOut_2_a_bits_corrupt; // @[CacheCork.scala:42:9]
wire d_d_3_ready; // @[CacheCork.scala:141:23]
assign auto_out_3_d_ready_0 = x1_nodeOut_2_d_ready; // @[CacheCork.scala:42:9]
wire d_d_3_valid = x1_nodeOut_2_d_valid; // @[CacheCork.scala:141:23]
wire [2:0] d_d_3_bits_size = x1_nodeOut_2_d_bits_size; // @[CacheCork.scala:141:23]
wire d_d_3_bits_denied = x1_nodeOut_2_d_bits_denied; // @[CacheCork.scala:141:23]
wire [63:0] d_d_3_bits_data = x1_nodeOut_2_d_bits_data; // @[CacheCork.scala:141:23]
wire d_d_3_bits_corrupt = x1_nodeOut_2_d_bits_corrupt; // @[CacheCork.scala:141:23]
wire _nodeOut_a_valid_T_24; // @[Arbiter.scala:96:24]
assign auto_out_4_a_valid_0 = x1_nodeOut_3_a_valid; // @[CacheCork.scala:42:9]
wire [2:0] _nodeOut_a_bits_WIRE_44_opcode; // @[Mux.scala:30:73]
assign auto_out_4_a_bits_opcode_0 = x1_nodeOut_3_a_bits_opcode; // @[CacheCork.scala:42:9]
wire [2:0] _nodeOut_a_bits_WIRE_44_param; // @[Mux.scala:30:73]
assign auto_out_4_a_bits_param_0 = x1_nodeOut_3_a_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] _nodeOut_a_bits_WIRE_44_size; // @[Mux.scala:30:73]
assign auto_out_4_a_bits_size_0 = x1_nodeOut_3_a_bits_size; // @[CacheCork.scala:42:9]
wire [4:0] _nodeOut_a_bits_WIRE_44_source; // @[Mux.scala:30:73]
assign auto_out_4_a_bits_source_0 = x1_nodeOut_3_a_bits_source; // @[CacheCork.scala:42:9]
wire [31:0] _nodeOut_a_bits_WIRE_44_address; // @[Mux.scala:30:73]
assign auto_out_4_a_bits_address_0 = x1_nodeOut_3_a_bits_address; // @[CacheCork.scala:42:9]
wire [7:0] _nodeOut_a_bits_WIRE_44_mask; // @[Mux.scala:30:73]
assign auto_out_4_a_bits_mask_0 = x1_nodeOut_3_a_bits_mask; // @[CacheCork.scala:42:9]
wire [63:0] _nodeOut_a_bits_WIRE_44_data; // @[Mux.scala:30:73]
assign auto_out_4_a_bits_data_0 = x1_nodeOut_3_a_bits_data; // @[CacheCork.scala:42:9]
wire _nodeOut_a_bits_WIRE_44_corrupt; // @[Mux.scala:30:73]
assign auto_out_4_a_bits_corrupt_0 = x1_nodeOut_3_a_bits_corrupt; // @[CacheCork.scala:42:9]
wire d_d_4_ready; // @[CacheCork.scala:141:23]
assign auto_out_4_d_ready_0 = x1_nodeOut_3_d_ready; // @[CacheCork.scala:42:9]
wire d_d_4_valid = x1_nodeOut_3_d_valid; // @[CacheCork.scala:141:23]
wire [2:0] d_d_4_bits_size = x1_nodeOut_3_d_bits_size; // @[CacheCork.scala:141:23]
wire d_d_4_bits_denied = x1_nodeOut_3_d_bits_denied; // @[CacheCork.scala:141:23]
wire [63:0] d_d_4_bits_data = x1_nodeOut_3_d_bits_data; // @[CacheCork.scala:141:23]
wire d_d_4_bits_corrupt = x1_nodeOut_3_d_bits_corrupt; // @[CacheCork.scala:141:23]
wire _nodeOut_a_valid_T_29; // @[Arbiter.scala:96:24]
assign auto_out_5_a_valid_0 = x1_nodeOut_4_a_valid; // @[CacheCork.scala:42:9]
wire [2:0] _nodeOut_a_bits_WIRE_55_opcode; // @[Mux.scala:30:73]
assign auto_out_5_a_bits_opcode_0 = x1_nodeOut_4_a_bits_opcode; // @[CacheCork.scala:42:9]
wire [2:0] _nodeOut_a_bits_WIRE_55_param; // @[Mux.scala:30:73]
assign auto_out_5_a_bits_param_0 = x1_nodeOut_4_a_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] _nodeOut_a_bits_WIRE_55_size; // @[Mux.scala:30:73]
assign auto_out_5_a_bits_size_0 = x1_nodeOut_4_a_bits_size; // @[CacheCork.scala:42:9]
wire [4:0] _nodeOut_a_bits_WIRE_55_source; // @[Mux.scala:30:73]
assign auto_out_5_a_bits_source_0 = x1_nodeOut_4_a_bits_source; // @[CacheCork.scala:42:9]
wire [31:0] _nodeOut_a_bits_WIRE_55_address; // @[Mux.scala:30:73]
assign auto_out_5_a_bits_address_0 = x1_nodeOut_4_a_bits_address; // @[CacheCork.scala:42:9]
wire [7:0] _nodeOut_a_bits_WIRE_55_mask; // @[Mux.scala:30:73]
assign auto_out_5_a_bits_mask_0 = x1_nodeOut_4_a_bits_mask; // @[CacheCork.scala:42:9]
wire [63:0] _nodeOut_a_bits_WIRE_55_data; // @[Mux.scala:30:73]
assign auto_out_5_a_bits_data_0 = x1_nodeOut_4_a_bits_data; // @[CacheCork.scala:42:9]
wire _nodeOut_a_bits_WIRE_55_corrupt; // @[Mux.scala:30:73]
assign auto_out_5_a_bits_corrupt_0 = x1_nodeOut_4_a_bits_corrupt; // @[CacheCork.scala:42:9]
wire d_d_5_ready; // @[CacheCork.scala:141:23]
assign auto_out_5_d_ready_0 = x1_nodeOut_4_d_ready; // @[CacheCork.scala:42:9]
wire d_d_5_valid = x1_nodeOut_4_d_valid; // @[CacheCork.scala:141:23]
wire [2:0] d_d_5_bits_size = x1_nodeOut_4_d_bits_size; // @[CacheCork.scala:141:23]
wire d_d_5_bits_denied = x1_nodeOut_4_d_bits_denied; // @[CacheCork.scala:141:23]
wire [63:0] d_d_5_bits_data = x1_nodeOut_4_d_bits_data; // @[CacheCork.scala:141:23]
wire d_d_5_bits_corrupt = x1_nodeOut_4_d_bits_corrupt; // @[CacheCork.scala:141:23]
wire _nodeOut_a_valid_T_34; // @[Arbiter.scala:96:24]
assign auto_out_6_a_valid_0 = x1_nodeOut_5_a_valid; // @[CacheCork.scala:42:9]
wire [2:0] _nodeOut_a_bits_WIRE_66_opcode; // @[Mux.scala:30:73]
assign auto_out_6_a_bits_opcode_0 = x1_nodeOut_5_a_bits_opcode; // @[CacheCork.scala:42:9]
wire [2:0] _nodeOut_a_bits_WIRE_66_param; // @[Mux.scala:30:73]
assign auto_out_6_a_bits_param_0 = x1_nodeOut_5_a_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] _nodeOut_a_bits_WIRE_66_size; // @[Mux.scala:30:73]
assign auto_out_6_a_bits_size_0 = x1_nodeOut_5_a_bits_size; // @[CacheCork.scala:42:9]
wire [4:0] _nodeOut_a_bits_WIRE_66_source; // @[Mux.scala:30:73]
assign auto_out_6_a_bits_source_0 = x1_nodeOut_5_a_bits_source; // @[CacheCork.scala:42:9]
wire [31:0] _nodeOut_a_bits_WIRE_66_address; // @[Mux.scala:30:73]
assign auto_out_6_a_bits_address_0 = x1_nodeOut_5_a_bits_address; // @[CacheCork.scala:42:9]
wire [7:0] _nodeOut_a_bits_WIRE_66_mask; // @[Mux.scala:30:73]
assign auto_out_6_a_bits_mask_0 = x1_nodeOut_5_a_bits_mask; // @[CacheCork.scala:42:9]
wire [63:0] _nodeOut_a_bits_WIRE_66_data; // @[Mux.scala:30:73]
assign auto_out_6_a_bits_data_0 = x1_nodeOut_5_a_bits_data; // @[CacheCork.scala:42:9]
wire _nodeOut_a_bits_WIRE_66_corrupt; // @[Mux.scala:30:73]
assign auto_out_6_a_bits_corrupt_0 = x1_nodeOut_5_a_bits_corrupt; // @[CacheCork.scala:42:9]
wire d_d_6_ready; // @[CacheCork.scala:141:23]
assign auto_out_6_d_ready_0 = x1_nodeOut_5_d_ready; // @[CacheCork.scala:42:9]
wire d_d_6_valid = x1_nodeOut_5_d_valid; // @[CacheCork.scala:141:23]
wire [2:0] d_d_6_bits_size = x1_nodeOut_5_d_bits_size; // @[CacheCork.scala:141:23]
wire d_d_6_bits_denied = x1_nodeOut_5_d_bits_denied; // @[CacheCork.scala:141:23]
wire [63:0] d_d_6_bits_data = x1_nodeOut_5_d_bits_data; // @[CacheCork.scala:141:23]
wire d_d_6_bits_corrupt = x1_nodeOut_5_d_bits_corrupt; // @[CacheCork.scala:141:23]
wire _nodeOut_a_valid_T_39; // @[Arbiter.scala:96:24]
assign auto_out_7_a_valid_0 = x1_nodeOut_6_a_valid; // @[CacheCork.scala:42:9]
wire [2:0] _nodeOut_a_bits_WIRE_77_opcode; // @[Mux.scala:30:73]
assign auto_out_7_a_bits_opcode_0 = x1_nodeOut_6_a_bits_opcode; // @[CacheCork.scala:42:9]
wire [2:0] _nodeOut_a_bits_WIRE_77_param; // @[Mux.scala:30:73]
assign auto_out_7_a_bits_param_0 = x1_nodeOut_6_a_bits_param; // @[CacheCork.scala:42:9]
wire [2:0] _nodeOut_a_bits_WIRE_77_size; // @[Mux.scala:30:73]
assign auto_out_7_a_bits_size_0 = x1_nodeOut_6_a_bits_size; // @[CacheCork.scala:42:9]
wire [4:0] _nodeOut_a_bits_WIRE_77_source; // @[Mux.scala:30:73]
assign auto_out_7_a_bits_source_0 = x1_nodeOut_6_a_bits_source; // @[CacheCork.scala:42:9]
wire [31:0] _nodeOut_a_bits_WIRE_77_address; // @[Mux.scala:30:73]
assign auto_out_7_a_bits_address_0 = x1_nodeOut_6_a_bits_address; // @[CacheCork.scala:42:9]
wire [7:0] _nodeOut_a_bits_WIRE_77_mask; // @[Mux.scala:30:73]
assign auto_out_7_a_bits_mask_0 = x1_nodeOut_6_a_bits_mask; // @[CacheCork.scala:42:9]
wire [63:0] _nodeOut_a_bits_WIRE_77_data; // @[Mux.scala:30:73]
assign auto_out_7_a_bits_data_0 = x1_nodeOut_6_a_bits_data; // @[CacheCork.scala:42:9]
wire _nodeOut_a_bits_WIRE_77_corrupt; // @[Mux.scala:30:73]
assign auto_out_7_a_bits_corrupt_0 = x1_nodeOut_6_a_bits_corrupt; // @[CacheCork.scala:42:9]
wire d_d_7_ready; // @[CacheCork.scala:141:23]
assign auto_out_7_d_ready_0 = x1_nodeOut_6_d_ready; // @[CacheCork.scala:42:9]
wire d_d_7_valid = x1_nodeOut_6_d_valid; // @[CacheCork.scala:141:23]
wire [2:0] d_d_7_bits_size = x1_nodeOut_6_d_bits_size; // @[CacheCork.scala:141:23]
wire d_d_7_bits_denied = x1_nodeOut_6_d_bits_denied; // @[CacheCork.scala:141:23]
wire [63:0] d_d_7_bits_data = x1_nodeOut_6_d_bits_data; // @[CacheCork.scala:141:23]
wire d_d_7_bits_corrupt = x1_nodeOut_6_d_bits_corrupt; // @[CacheCork.scala:141:23]
wire _a_a_ready_T; // @[Arbiter.scala:94:31]
wire _a_a_valid_T_1; // @[CacheCork.scala:81:33]
wire [2:0] a_a_bits_opcode; // @[CacheCork.scala:74:23]
wire [2:0] a_a_bits_param; // @[CacheCork.scala:74:23]
wire [4:0] a_a_bits_source; // @[CacheCork.scala:74:23]
wire a_a_ready; // @[CacheCork.scala:74:23]
wire a_a_valid; // @[CacheCork.scala:74:23]
wire _a_d_valid_T; // @[CacheCork.scala:93:33]
wire [2:0] a_d_bits_size; // @[CacheCork.scala:75:23]
wire [3:0] a_d_bits_source; // @[CacheCork.scala:75:23]
wire a_d_ready; // @[CacheCork.scala:75:23]
wire a_d_valid; // @[CacheCork.scala:75:23]
wire _isPut_T = nodeIn_a_bits_opcode == 3'h0; // @[CacheCork.scala:76:38]
wire _isPut_T_1 = nodeIn_a_bits_opcode == 3'h1; // @[CacheCork.scala:76:74]
wire isPut = _isPut_T | _isPut_T_1; // @[CacheCork.scala:76:{38,54,74}]
wire _a_a_bits_source_T_1 = isPut; // @[CacheCork.scala:76:54, :83:55]
wire _toD_T = nodeIn_a_bits_opcode == 3'h6; // @[CacheCork.scala:77:37]
wire _toD_T_1 = nodeIn_a_bits_param == 3'h2; // @[CacheCork.scala:77:73]
wire _toD_T_2 = _toD_T & _toD_T_1; // @[CacheCork.scala:77:{37,54,73}]
wire _toD_T_3 = &nodeIn_a_bits_opcode; // @[CacheCork.scala:78:37]
wire toD = _toD_T_2 | _toD_T_3; // @[CacheCork.scala:77:{54,97}, :78:37]
assign _nodeIn_a_ready_T = toD ? a_d_ready : a_a_ready; // @[CacheCork.scala:74:23, :75:23, :77:97, :79:26]
assign nodeIn_a_ready = _nodeIn_a_ready_T; // @[CacheCork.scala:79:26]
wire _a_a_valid_T = ~toD; // @[CacheCork.scala:77:97, :81:36]
assign _a_a_valid_T_1 = nodeIn_a_valid & _a_a_valid_T; // @[CacheCork.scala:81:{33,36}]
assign a_a_valid = _a_a_valid_T_1; // @[CacheCork.scala:74:23, :81:33]
wire [4:0] _GEN = {nodeIn_a_bits_source, 1'h0}; // @[CacheCork.scala:83:45]
wire [4:0] _a_a_bits_source_T; // @[CacheCork.scala:83:45]
assign _a_a_bits_source_T = _GEN; // @[CacheCork.scala:83:45]
wire [4:0] _a_a_bits_source_T_3; // @[CacheCork.scala:89:47]
assign _a_a_bits_source_T_3 = _GEN; // @[CacheCork.scala:83:45, :89:47]
wire [4:0] _a_a_bits_source_T_2 = {_a_a_bits_source_T[4:1], _a_a_bits_source_T[0] | _a_a_bits_source_T_1}; // @[CacheCork.scala:83:{45,50,55}]
wire _T_2 = _toD_T | (&nodeIn_a_bits_opcode); // @[CacheCork.scala:77:37, :78:37, :86:49]
assign a_a_bits_opcode = _T_2 ? 3'h4 : nodeIn_a_bits_opcode; // @[CacheCork.scala:74:23, :82:18, :86:{49,86}, :87:27]
assign a_a_bits_param = _T_2 ? 3'h0 : nodeIn_a_bits_param; // @[CacheCork.scala:74:23, :82:18, :86:{49,86}, :88:27]
wire [4:0] _a_a_bits_source_T_4 = {_a_a_bits_source_T_3[4:1], 1'h1}; // @[CacheCork.scala:89:{47,52}]
assign a_a_bits_source = _T_2 ? _a_a_bits_source_T_4 : _a_a_bits_source_T_2; // @[CacheCork.scala:74:23, :83:{25,50}, :86:{49,86}, :89:{27,52}]
assign _a_d_valid_T = nodeIn_a_valid & toD; // @[CacheCork.scala:77:97, :93:33]
assign a_d_valid = _a_d_valid_T; // @[CacheCork.scala:75:23, :93:33]
assign a_d_bits_size = a_d_bits_d_size; // @[Edges.scala:645:17]
assign a_d_bits_source = a_d_bits_d_source; // @[Edges.scala:645:17]
wire _c_a_ready_T; // @[Arbiter.scala:94:31]
wire _c_a_valid_T_1; // @[CacheCork.scala:102:33]
wire [4:0] c_a_bits_a_source; // @[Edges.scala:480:17]
wire [7:0] c_a_bits_a_mask; // @[Edges.scala:480:17]
wire [2:0] c_a_bits_size; // @[CacheCork.scala:101:23]
wire [4:0] c_a_bits_source; // @[CacheCork.scala:101:23]
wire [31:0] c_a_bits_address; // @[CacheCork.scala:101:23]
wire [7:0] c_a_bits_mask; // @[CacheCork.scala:101:23]
wire [63:0] c_a_bits_data; // @[CacheCork.scala:101:23]
wire c_a_bits_corrupt; // @[CacheCork.scala:101:23]
wire c_a_ready; // @[CacheCork.scala:101:23]
wire c_a_valid; // @[CacheCork.scala:101:23]
wire _c_a_valid_T = &nodeIn_c_bits_opcode; // @[CacheCork.scala:102:53]
assign _c_a_valid_T_1 = nodeIn_c_valid & _c_a_valid_T; // @[CacheCork.scala:102:{33,53}]
assign c_a_valid = _c_a_valid_T_1; // @[CacheCork.scala:101:23, :102:33]
wire [4:0] _c_a_bits_T = {nodeIn_c_bits_source, 1'h0}; // @[CacheCork.scala:104:41]
assign c_a_bits_a_source = _c_a_bits_T; // @[Edges.scala:480:17]
wire _c_a_bits_legal_T_1 = nodeIn_c_bits_size != 3'h7; // @[Parameters.scala:92:38]
wire _c_a_bits_legal_T_2 = _c_a_bits_legal_T_1; // @[Parameters.scala:92:{33,38}]
wire _c_a_bits_legal_T_3 = _c_a_bits_legal_T_2; // @[Parameters.scala:684:29]
wire _c_a_bits_legal_T_9 = _c_a_bits_legal_T_3; // @[Parameters.scala:684:{29,54}]
wire [32:0] _c_a_bits_legal_T_5 = {1'h0, _c_a_bits_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire c_a_bits_legal = _c_a_bits_legal_T_9; // @[Parameters.scala:684:54, :686:26]
assign c_a_bits_size = c_a_bits_a_size; // @[Edges.scala:480:17]
assign c_a_bits_source = c_a_bits_a_source; // @[Edges.scala:480:17]
assign c_a_bits_address = c_a_bits_a_address; // @[Edges.scala:480:17]
wire [7:0] _c_a_bits_a_mask_T; // @[Misc.scala:222:10]
assign c_a_bits_mask = c_a_bits_a_mask; // @[Edges.scala:480:17]
assign c_a_bits_data = c_a_bits_a_data; // @[Edges.scala:480:17]
assign c_a_bits_corrupt = c_a_bits_a_corrupt; // @[Edges.scala:480:17]
wire [1:0] c_a_bits_a_mask_sizeOH_shiftAmount = _c_a_bits_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _c_a_bits_a_mask_sizeOH_T_1 = 4'h1 << c_a_bits_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _c_a_bits_a_mask_sizeOH_T_2 = _c_a_bits_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] c_a_bits_a_mask_sizeOH = {_c_a_bits_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire c_a_bits_a_mask_sub_sub_sub_0_1 = nodeIn_c_bits_size > 3'h2; // @[Misc.scala:206:21]
wire c_a_bits_a_mask_sub_sub_size = c_a_bits_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire c_a_bits_a_mask_sub_sub_bit = nodeIn_c_bits_address[2]; // @[Misc.scala:210:26]
wire c_a_bits_a_mask_sub_sub_1_2 = c_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire c_a_bits_a_mask_sub_sub_nbit = ~c_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire c_a_bits_a_mask_sub_sub_0_2 = c_a_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_sub_sub_acc_T = c_a_bits_a_mask_sub_sub_size & c_a_bits_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_sub_0_1 = c_a_bits_a_mask_sub_sub_sub_0_1 | _c_a_bits_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _c_a_bits_a_mask_sub_sub_acc_T_1 = c_a_bits_a_mask_sub_sub_size & c_a_bits_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_sub_1_1 = c_a_bits_a_mask_sub_sub_sub_0_1 | _c_a_bits_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire c_a_bits_a_mask_sub_size = c_a_bits_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire c_a_bits_a_mask_sub_bit = nodeIn_c_bits_address[1]; // @[Misc.scala:210:26]
wire c_a_bits_a_mask_sub_nbit = ~c_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire c_a_bits_a_mask_sub_0_2 = c_a_bits_a_mask_sub_sub_0_2 & c_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_sub_acc_T = c_a_bits_a_mask_sub_size & c_a_bits_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_0_1 = c_a_bits_a_mask_sub_sub_0_1 | _c_a_bits_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_sub_1_2 = c_a_bits_a_mask_sub_sub_0_2 & c_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_1 = c_a_bits_a_mask_sub_size & c_a_bits_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_1_1 = c_a_bits_a_mask_sub_sub_0_1 | _c_a_bits_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_sub_2_2 = c_a_bits_a_mask_sub_sub_1_2 & c_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_2 = c_a_bits_a_mask_sub_size & c_a_bits_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_2_1 = c_a_bits_a_mask_sub_sub_1_1 | _c_a_bits_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_sub_3_2 = c_a_bits_a_mask_sub_sub_1_2 & c_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_3 = c_a_bits_a_mask_sub_size & c_a_bits_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_3_1 = c_a_bits_a_mask_sub_sub_1_1 | _c_a_bits_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_size = c_a_bits_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire c_a_bits_a_mask_bit = nodeIn_c_bits_address[0]; // @[Misc.scala:210:26]
wire c_a_bits_a_mask_nbit = ~c_a_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire c_a_bits_a_mask_eq = c_a_bits_a_mask_sub_0_2 & c_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T = c_a_bits_a_mask_size & c_a_bits_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc = c_a_bits_a_mask_sub_0_1 | _c_a_bits_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_1 = c_a_bits_a_mask_sub_0_2 & c_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_1 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_1 = c_a_bits_a_mask_sub_0_1 | _c_a_bits_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_2 = c_a_bits_a_mask_sub_1_2 & c_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_2 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_2 = c_a_bits_a_mask_sub_1_1 | _c_a_bits_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_3 = c_a_bits_a_mask_sub_1_2 & c_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_3 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_3 = c_a_bits_a_mask_sub_1_1 | _c_a_bits_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_4 = c_a_bits_a_mask_sub_2_2 & c_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_4 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_4 = c_a_bits_a_mask_sub_2_1 | _c_a_bits_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_5 = c_a_bits_a_mask_sub_2_2 & c_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_5 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_5 = c_a_bits_a_mask_sub_2_1 | _c_a_bits_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_6 = c_a_bits_a_mask_sub_3_2 & c_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_6 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_6 = c_a_bits_a_mask_sub_3_1 | _c_a_bits_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_7 = c_a_bits_a_mask_sub_3_2 & c_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_7 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_7 = c_a_bits_a_mask_sub_3_1 | _c_a_bits_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] c_a_bits_a_mask_lo_lo = {c_a_bits_a_mask_acc_1, c_a_bits_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] c_a_bits_a_mask_lo_hi = {c_a_bits_a_mask_acc_3, c_a_bits_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] c_a_bits_a_mask_lo = {c_a_bits_a_mask_lo_hi, c_a_bits_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] c_a_bits_a_mask_hi_lo = {c_a_bits_a_mask_acc_5, c_a_bits_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] c_a_bits_a_mask_hi_hi = {c_a_bits_a_mask_acc_7, c_a_bits_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] c_a_bits_a_mask_hi = {c_a_bits_a_mask_hi_hi, c_a_bits_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _c_a_bits_a_mask_T = {c_a_bits_a_mask_hi, c_a_bits_a_mask_lo}; // @[Misc.scala:222:10]
assign c_a_bits_a_mask = _c_a_bits_a_mask_T; // @[Misc.scala:222:10]
wire _c_d_valid_T_1; // @[CacheCork.scala:113:33]
wire [2:0] c_d_bits_size; // @[CacheCork.scala:112:23]
wire [3:0] c_d_bits_source; // @[CacheCork.scala:112:23]
wire c_d_ready; // @[CacheCork.scala:112:23]
wire c_d_valid; // @[CacheCork.scala:112:23]
wire _T_4 = nodeIn_c_bits_opcode == 3'h6; // @[CacheCork.scala:113:53]
wire _c_d_valid_T; // @[CacheCork.scala:113:53]
assign _c_d_valid_T = _T_4; // @[CacheCork.scala:113:53]
wire _nodeIn_c_ready_T; // @[CacheCork.scala:117:44]
assign _nodeIn_c_ready_T = _T_4; // @[CacheCork.scala:113:53, :117:44]
assign _c_d_valid_T_1 = nodeIn_c_valid & _c_d_valid_T; // @[CacheCork.scala:113:{33,53}]
assign c_d_valid = _c_d_valid_T_1; // @[CacheCork.scala:112:23, :113:33]
assign c_d_bits_size = c_d_bits_d_size; // @[Edges.scala:677:17]
assign c_d_bits_source = c_d_bits_d_source; // @[Edges.scala:677:17]
assign _nodeIn_c_ready_T_1 = _nodeIn_c_ready_T ? c_d_ready : c_a_ready; // @[CacheCork.scala:101:23, :112:23, :117:{26,44}]
assign nodeIn_c_ready = _nodeIn_c_ready_T_1; // @[CacheCork.scala:117:26]
wire _in_d_ready_T_4; // @[CacheCork.scala:136:34]
wire _in_d_valid_T_7; // @[Arbiter.scala:96:24]
wire [2:0] _in_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign nodeIn_d_bits_opcode = in_d_bits_opcode; // @[CacheCork.scala:131:24]
wire [1:0] _in_d_bits_WIRE_param; // @[Mux.scala:30:73]
assign nodeIn_d_bits_param = in_d_bits_param; // @[CacheCork.scala:131:24]
wire [2:0] _in_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign nodeIn_d_bits_size = in_d_bits_size; // @[CacheCork.scala:131:24]
wire [3:0] _in_d_bits_WIRE_source; // @[Mux.scala:30:73]
assign nodeIn_d_bits_source = in_d_bits_source; // @[CacheCork.scala:131:24]
wire [2:0] _in_d_bits_WIRE_sink; // @[Mux.scala:30:73]
wire _in_d_bits_WIRE_denied; // @[Mux.scala:30:73]
assign nodeIn_d_bits_denied = in_d_bits_denied; // @[CacheCork.scala:131:24]
wire [63:0] _in_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign nodeIn_d_bits_data = in_d_bits_data; // @[CacheCork.scala:131:24]
wire _in_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign nodeIn_d_bits_corrupt = in_d_bits_corrupt; // @[CacheCork.scala:131:24]
wire [2:0] in_d_bits_sink; // @[CacheCork.scala:131:24]
wire in_d_ready; // @[CacheCork.scala:131:24]
wire in_d_valid; // @[CacheCork.scala:131:24]
wire _GEN_0 = in_d_ready & in_d_valid; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _GEN_0; // @[Decoupled.scala:51:35]
wire _beatsLeft_T_4; // @[Decoupled.scala:51:35]
assign _beatsLeft_T_4 = _GEN_0; // @[Decoupled.scala:51:35]
wire [12:0] _d_first_beats1_decode_T = 13'h3F << in_d_bits_size; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = in_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _d_grant_T = in_d_bits_opcode == 3'h5; // @[CacheCork.scala:131:24, :133:40]
wire _d_grant_T_1 = in_d_bits_opcode == 3'h4; // @[CacheCork.scala:131:24, :133:74]
wire d_grant = _d_grant_T | _d_grant_T_1; // @[CacheCork.scala:133:{40,54,74}]
wire _pool_io_alloc_ready_T = nodeIn_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35]
wire _pool_io_alloc_ready_T_1 = _pool_io_alloc_ready_T & d_first; // @[Decoupled.scala:51:35]
wire _pool_io_alloc_ready_T_2 = _pool_io_alloc_ready_T_1 & d_grant; // @[CacheCork.scala:133:54, :134:{42,53}]
wire _nodeIn_d_valid_T = ~d_first; // @[Edges.scala:231:25]
wire _nodeIn_d_valid_T_1 = _pool_io_alloc_valid | _nodeIn_d_valid_T; // @[CacheCork.scala:127:26, :135:{58,61}]
wire _nodeIn_d_valid_T_2 = ~d_grant; // @[CacheCork.scala:133:54, :135:73]
wire _nodeIn_d_valid_T_3 = _nodeIn_d_valid_T_1 | _nodeIn_d_valid_T_2; // @[CacheCork.scala:135:{58,70,73}]
assign _nodeIn_d_valid_T_4 = in_d_valid & _nodeIn_d_valid_T_3; // @[CacheCork.scala:131:24, :135:{34,70}]
assign nodeIn_d_valid = _nodeIn_d_valid_T_4; // @[CacheCork.scala:135:34]
wire _in_d_ready_T = ~d_first; // @[Edges.scala:231:25]
wire _in_d_ready_T_1 = _pool_io_alloc_valid | _in_d_ready_T; // @[CacheCork.scala:127:26, :136:{58,61}]
wire _in_d_ready_T_2 = ~d_grant; // @[CacheCork.scala:133:54, :135:73, :136:73]
wire _in_d_ready_T_3 = _in_d_ready_T_1 | _in_d_ready_T_2; // @[CacheCork.scala:136:{58,70,73}]
assign _in_d_ready_T_4 = nodeIn_d_ready & _in_d_ready_T_3; // @[CacheCork.scala:136:{34,70}]
assign in_d_ready = _in_d_ready_T_4; // @[CacheCork.scala:131:24, :136:34]
reg [2:0] nodeIn_d_bits_sink_r; // @[package.scala:88:63]
assign _nodeIn_d_bits_sink_T = d_first ? _pool_io_alloc_bits : nodeIn_d_bits_sink_r; // @[package.scala:88:{42,63}]
assign nodeIn_d_bits_sink = _nodeIn_d_bits_sink_T; // @[package.scala:88:42]
wire _d_d_ready_T; // @[Arbiter.scala:94:31]
assign nodeOut_d_ready = d_d_ready; // @[CacheCork.scala:141:23]
wire [3:0] _d_d_bits_source_T; // @[CacheCork.scala:143:46]
wire [2:0] d_d_bits_opcode; // @[CacheCork.scala:141:23]
wire [1:0] d_d_bits_param; // @[CacheCork.scala:141:23]
wire [3:0] d_d_bits_source; // @[CacheCork.scala:141:23]
wire [2:0] d_d_bits_sink; // @[CacheCork.scala:141:23]
assign d_d_bits_sink = {2'h0, nodeOut_d_bits_sink}; // @[CacheCork.scala:141:23, :142:13]
assign _d_d_bits_source_T = nodeOut_d_bits_source[4:1]; // @[CacheCork.scala:143:46]
assign d_d_bits_source = _d_d_bits_source_T; // @[CacheCork.scala:141:23, :143:46]
wire [32:0] _aWOk_T_1 = {1'h0, _aWOk_T}; // @[Parameters.scala:137:{31,41}]
wire _bypass_T_1 = nodeIn_a_bits_source == d_d_bits_source; // @[CacheCork.scala:141:23, :150:91]
reg dWHeld_r; // @[package.scala:88:63]
wire dWHeld = d_first ? _dWHeld_T : dWHeld_r; // @[package.scala:88:{42,63}]
wire _T_18 = nodeOut_d_bits_opcode == 3'h1 & nodeOut_d_bits_source[0]; // @[CacheCork.scala:162:{33,51,71}]
wire [1:0] _d_d_bits_param_T = {1'h0, ~dWHeld}; // @[package.scala:88:42]
assign d_d_bits_param = _T_18 ? _d_d_bits_param_T : nodeOut_d_bits_param; // @[CacheCork.scala:141:23, :142:13, :162:{51,76}, :164:{26,32}]
assign d_d_bits_opcode = nodeOut_d_bits_opcode == 3'h0 & ~(nodeOut_d_bits_source[0]) ? 3'h6 : _T_18 ? 3'h5 : nodeOut_d_bits_opcode; // @[CacheCork.scala:141:23, :142:13, :162:{51,71,76}, :163:27, :166:{33,47,50,73}, :167:27]
wire [12:0] _decode_T = 13'h3F << c_a_bits_size; // @[package.scala:243:71]
wire [5:0] _decode_T_1 = _decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _decode_T_2 = ~_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] decode = _decode_T_2[5:3]; // @[package.scala:243:46]
wire [12:0] _decode_T_3 = 13'h3F << a_a_bits_size; // @[package.scala:243:71]
wire [5:0] _decode_T_4 = _decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _decode_T_5 = ~_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] decode_1 = _decode_T_5[5:3]; // @[package.scala:243:46]
wire _opdata_T_1 = a_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire opdata_1 = ~_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg [2:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & nodeOut_a_ready; // @[Arbiter.scala:61:28, :62:24]
wire [1:0] _readys_T = {a_a_valid, c_a_valid}; // @[CacheCork.scala:74:23, :101:23]
wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_T_2 = _readys_T_1[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_T_3 = _readys_T | _readys_T_2; // @[package.scala:253:{43,53}]
wire [1:0] _readys_T_4 = _readys_T_3; // @[package.scala:253:43, :254:17]
wire [2:0] _readys_T_5 = {_readys_T_4, 1'h0}; // @[package.scala:254:17]
wire [1:0] _readys_T_6 = _readys_T_5[1:0]; // @[Arbiter.scala:16:{78,83}]
wire [1:0] _readys_T_7 = ~_readys_T_6; // @[Arbiter.scala:16:{61,83}]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:16:61, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:16:61, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & c_a_valid; // @[CacheCork.scala:101:23]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & a_a_valid; // @[CacheCork.scala:74:23]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire _nodeOut_a_valid_T = c_a_valid | a_a_valid; // @[CacheCork.scala:74:23, :101:23]
wire [2:0] maskedBeats_0 = winner_0 ? decode : 3'h0; // @[Edges.scala:220:59, :221:14]
wire [2:0] maskedBeats_1 = winner_1 & opdata_1 ? decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [2:0] initBeats = maskedBeats_0 | maskedBeats_1; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T = nodeOut_a_ready & nodeOut_a_valid; // @[Decoupled.scala:51:35]
wire [3:0] _beatsLeft_T_1 = {1'h0, beatsLeft} - {3'h0, _beatsLeft_T}; // @[Decoupled.scala:51:35]
wire [2:0] _beatsLeft_T_2 = _beatsLeft_T_1[2:0]; // @[Arbiter.scala:85:52]
wire [2:0] _beatsLeft_T_3 = latch ? initBeats : _beatsLeft_T_2; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_0; // @[Arbiter.scala:88:26]
reg state_1; // @[Arbiter.scala:88:26]
wire muxState_0 = idle ? winner_0 : state_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1 = idle ? winner_1 : state_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _c_a_ready_T = nodeOut_a_ready & allowed_0; // @[Arbiter.scala:92:24, :94:31]
assign c_a_ready = _c_a_ready_T; // @[CacheCork.scala:101:23]
assign _a_a_ready_T = nodeOut_a_ready & allowed_1; // @[Arbiter.scala:92:24, :94:31]
assign a_a_ready = _a_a_ready_T; // @[CacheCork.scala:74:23]
wire _nodeOut_a_valid_T_1 = state_0 & c_a_valid; // @[Mux.scala:30:73]
wire _nodeOut_a_valid_T_2 = state_1 & a_a_valid; // @[Mux.scala:30:73]
wire _nodeOut_a_valid_T_3 = _nodeOut_a_valid_T_1 | _nodeOut_a_valid_T_2; // @[Mux.scala:30:73]
wire _nodeOut_a_valid_WIRE = _nodeOut_a_valid_T_3; // @[Mux.scala:30:73]
assign _nodeOut_a_valid_T_4 = idle ? _nodeOut_a_valid_T : _nodeOut_a_valid_WIRE; // @[Mux.scala:30:73]
assign nodeOut_a_valid = _nodeOut_a_valid_T_4; // @[Arbiter.scala:96:24]
wire [2:0] _nodeOut_a_bits_WIRE_10; // @[Mux.scala:30:73]
assign nodeOut_a_bits_opcode = _nodeOut_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_WIRE_9; // @[Mux.scala:30:73]
assign nodeOut_a_bits_param = _nodeOut_a_bits_WIRE_param; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_WIRE_8; // @[Mux.scala:30:73]
assign nodeOut_a_bits_size = _nodeOut_a_bits_WIRE_size; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_WIRE_7; // @[Mux.scala:30:73]
assign nodeOut_a_bits_source = _nodeOut_a_bits_WIRE_source; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_WIRE_6; // @[Mux.scala:30:73]
assign nodeOut_a_bits_address = _nodeOut_a_bits_WIRE_address; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_WIRE_3; // @[Mux.scala:30:73]
assign nodeOut_a_bits_mask = _nodeOut_a_bits_WIRE_mask; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_WIRE_2; // @[Mux.scala:30:73]
assign nodeOut_a_bits_data = _nodeOut_a_bits_WIRE_data; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_WIRE_1; // @[Mux.scala:30:73]
assign nodeOut_a_bits_corrupt = _nodeOut_a_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T = muxState_0 & c_a_bits_corrupt; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T_1 = muxState_1 & a_a_bits_corrupt; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T_2 = _nodeOut_a_bits_T | _nodeOut_a_bits_T_1; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_1 = _nodeOut_a_bits_T_2; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_corrupt = _nodeOut_a_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_T_3 = muxState_0 ? c_a_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_T_4 = muxState_1 ? a_a_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_T_5 = _nodeOut_a_bits_T_3 | _nodeOut_a_bits_T_4; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_2 = _nodeOut_a_bits_T_5; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_data = _nodeOut_a_bits_WIRE_2; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_T_6 = muxState_0 ? c_a_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_T_7 = muxState_1 ? a_a_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_T_8 = _nodeOut_a_bits_T_6 | _nodeOut_a_bits_T_7; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_3 = _nodeOut_a_bits_T_8; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_mask = _nodeOut_a_bits_WIRE_3; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_T_9 = muxState_0 ? c_a_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_T_10 = muxState_1 ? a_a_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_T_11 = _nodeOut_a_bits_T_9 | _nodeOut_a_bits_T_10; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_6 = _nodeOut_a_bits_T_11; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_address = _nodeOut_a_bits_WIRE_6; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_T_12 = muxState_0 ? c_a_bits_source : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_T_13 = muxState_1 ? a_a_bits_source : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_T_14 = _nodeOut_a_bits_T_12 | _nodeOut_a_bits_T_13; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_7 = _nodeOut_a_bits_T_14; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_source = _nodeOut_a_bits_WIRE_7; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_15 = muxState_0 ? c_a_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_16 = muxState_1 ? a_a_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_17 = _nodeOut_a_bits_T_15 | _nodeOut_a_bits_T_16; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_8 = _nodeOut_a_bits_T_17; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_size = _nodeOut_a_bits_WIRE_8; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_19 = muxState_1 ? a_a_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_20 = _nodeOut_a_bits_T_19; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_9 = _nodeOut_a_bits_T_20; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_param = _nodeOut_a_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_22 = muxState_1 ? a_a_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_23 = _nodeOut_a_bits_T_22; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_10 = _nodeOut_a_bits_T_23; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_opcode = _nodeOut_a_bits_WIRE_10; // @[Mux.scala:30:73]
wire [12:0] _decode_T_6 = 13'h3F << d_d_bits_size; // @[package.scala:243:71]
wire [5:0] _decode_T_7 = _decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _decode_T_8 = ~_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] decode_2 = _decode_T_8[5:3]; // @[package.scala:243:46]
wire opdata_2 = d_d_bits_opcode[0]; // @[Edges.scala:106:36]
reg [2:0] beatsLeft_1; // @[Arbiter.scala:60:30]
wire idle_1 = beatsLeft_1 == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_1 = idle_1 & in_d_ready; // @[CacheCork.scala:131:24]
wire [1:0] readys_hi = {_q_1_io_deq_valid, _q_io_deq_valid}; // @[Decoupled.scala:362:21]
wire [2:0] _readys_T_10 = {readys_hi, d_d_valid}; // @[CacheCork.scala:141:23]
wire [3:0] _readys_T_11 = {_readys_T_10, 1'h0}; // @[package.scala:253:48]
wire [2:0] _readys_T_12 = _readys_T_11[2:0]; // @[package.scala:253:{48,53}]
wire [2:0] _readys_T_13 = _readys_T_10 | _readys_T_12; // @[package.scala:253:{43,53}]
wire [4:0] _readys_T_14 = {_readys_T_13, 2'h0}; // @[package.scala:253:{43,48}]
wire [2:0] _readys_T_15 = _readys_T_14[2:0]; // @[package.scala:253:{48,53}]
wire [2:0] _readys_T_16 = _readys_T_13 | _readys_T_15; // @[package.scala:253:{43,53}]
wire [2:0] _readys_T_17 = _readys_T_16; // @[package.scala:253:43, :254:17]
wire [3:0] _readys_T_18 = {_readys_T_17, 1'h0}; // @[package.scala:254:17]
wire [2:0] _readys_T_19 = _readys_T_18[2:0]; // @[Arbiter.scala:16:{78,83}]
wire [2:0] _readys_T_20 = ~_readys_T_19; // @[Arbiter.scala:16:{61,83}]
wire _readys_T_21 = _readys_T_20[0]; // @[Arbiter.scala:16:61, :68:76]
wire readys_1_0 = _readys_T_21; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_22 = _readys_T_20[1]; // @[Arbiter.scala:16:61, :68:76]
wire readys_1_1 = _readys_T_22; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_23 = _readys_T_20[2]; // @[Arbiter.scala:16:61, :68:76]
wire readys_1_2 = _readys_T_23; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_2 = readys_1_0 & d_d_valid; // @[CacheCork.scala:141:23]
wire winner_1_0 = _winner_T_2; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_3 = readys_1_1 & _q_io_deq_valid; // @[Decoupled.scala:362:21]
wire winner_1_1 = _winner_T_3; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_4 = readys_1_2 & _q_1_io_deq_valid; // @[Decoupled.scala:362:21]
wire winner_1_2 = _winner_T_4; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_1 = winner_1_0; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_2 = prefixOR_1_1 | winner_1_1; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_1 = prefixOR_2 | winner_1_2; // @[Arbiter.scala:71:27, :76:48]
wire _in_d_valid_T = d_d_valid | _q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] maskedBeats_0_1 = winner_1_0 & opdata_2 ? decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire [2:0] _initBeats_T = maskedBeats_0_1; // @[Arbiter.scala:82:69, :84:44]
wire [2:0] initBeats_1 = _initBeats_T; // @[Arbiter.scala:84:44]
wire [3:0] _beatsLeft_T_5 = {1'h0, beatsLeft_1} - {3'h0, _beatsLeft_T_4}; // @[Decoupled.scala:51:35]
wire [2:0] _beatsLeft_T_6 = _beatsLeft_T_5[2:0]; // @[Arbiter.scala:85:52]
wire [2:0] _beatsLeft_T_7 = latch_1 ? initBeats_1 : _beatsLeft_T_6; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_1_0; // @[Arbiter.scala:88:26]
reg state_1_1; // @[Arbiter.scala:88:26]
reg state_1_2; // @[Arbiter.scala:88:26]
wire muxState_1_0 = idle_1 ? winner_1_0 : state_1_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1_1 = idle_1 ? winner_1_1 : state_1_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1_2 = idle_1 ? winner_1_2 : state_1_2; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_1_0 = idle_1 ? readys_1_0 : state_1_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1_1 = idle_1 ? readys_1_1 : state_1_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1_2 = idle_1 ? readys_1_2 : state_1_2; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _d_d_ready_T = in_d_ready & allowed_1_0; // @[CacheCork.scala:131:24]
assign d_d_ready = _d_d_ready_T; // @[CacheCork.scala:141:23]
wire _q_io_deq_ready_T = in_d_ready & allowed_1_1; // @[CacheCork.scala:131:24]
wire _q_io_deq_ready_T_1 = in_d_ready & allowed_1_2; // @[CacheCork.scala:131:24]
wire _in_d_valid_T_1 = _in_d_valid_T | _q_1_io_deq_valid; // @[Decoupled.scala:362:21]
wire _in_d_valid_T_2 = state_1_0 & d_d_valid; // @[Mux.scala:30:73]
wire _in_d_valid_T_3 = state_1_1 & _q_io_deq_valid; // @[Mux.scala:30:73]
wire _in_d_valid_T_4 = state_1_2 & _q_1_io_deq_valid; // @[Mux.scala:30:73]
wire _in_d_valid_T_5 = _in_d_valid_T_2 | _in_d_valid_T_3; // @[Mux.scala:30:73]
wire _in_d_valid_T_6 = _in_d_valid_T_5 | _in_d_valid_T_4; // @[Mux.scala:30:73]
wire _in_d_valid_WIRE = _in_d_valid_T_6; // @[Mux.scala:30:73]
assign _in_d_valid_T_7 = idle_1 ? _in_d_valid_T_1 : _in_d_valid_WIRE; // @[Mux.scala:30:73]
assign in_d_valid = _in_d_valid_T_7; // @[CacheCork.scala:131:24]
wire [2:0] _in_d_bits_WIRE_10; // @[Mux.scala:30:73]
assign in_d_bits_opcode = _in_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_WIRE_9; // @[Mux.scala:30:73]
assign in_d_bits_param = _in_d_bits_WIRE_param; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_WIRE_8; // @[Mux.scala:30:73]
assign in_d_bits_size = _in_d_bits_WIRE_size; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_WIRE_7; // @[Mux.scala:30:73]
assign in_d_bits_source = _in_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_WIRE_6; // @[Mux.scala:30:73]
assign in_d_bits_sink = _in_d_bits_WIRE_sink; // @[Mux.scala:30:73]
wire _in_d_bits_WIRE_5; // @[Mux.scala:30:73]
assign in_d_bits_denied = _in_d_bits_WIRE_denied; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_WIRE_2; // @[Mux.scala:30:73]
assign in_d_bits_data = _in_d_bits_WIRE_data; // @[Mux.scala:30:73]
wire _in_d_bits_WIRE_1; // @[Mux.scala:30:73]
assign in_d_bits_corrupt = _in_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T = muxState_1_0 & d_d_bits_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_1 = muxState_1_1 & _q_io_deq_bits_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_2 = muxState_1_2 & _q_1_io_deq_bits_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_3 = _in_d_bits_T | _in_d_bits_T_1; // @[Mux.scala:30:73]
wire _in_d_bits_T_4 = _in_d_bits_T_3 | _in_d_bits_T_2; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_1 = _in_d_bits_T_4; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_corrupt = _in_d_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_5 = muxState_1_0 ? d_d_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_6 = muxState_1_1 ? _q_io_deq_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_7 = muxState_1_2 ? _q_1_io_deq_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_8 = _in_d_bits_T_5 | _in_d_bits_T_6; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_9 = _in_d_bits_T_8 | _in_d_bits_T_7; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_2 = _in_d_bits_T_9; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_data = _in_d_bits_WIRE_2; // @[Mux.scala:30:73]
wire _in_d_bits_T_10 = muxState_1_0 & d_d_bits_denied; // @[Mux.scala:30:73]
wire _in_d_bits_T_11 = muxState_1_1 & _q_io_deq_bits_denied; // @[Mux.scala:30:73]
wire _in_d_bits_T_12 = muxState_1_2 & _q_1_io_deq_bits_denied; // @[Mux.scala:30:73]
wire _in_d_bits_T_13 = _in_d_bits_T_10 | _in_d_bits_T_11; // @[Mux.scala:30:73]
wire _in_d_bits_T_14 = _in_d_bits_T_13 | _in_d_bits_T_12; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_5 = _in_d_bits_T_14; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_denied = _in_d_bits_WIRE_5; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_15 = muxState_1_0 ? d_d_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_16 = muxState_1_1 ? _q_io_deq_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_17 = muxState_1_2 ? _q_1_io_deq_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_18 = _in_d_bits_T_15 | _in_d_bits_T_16; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_19 = _in_d_bits_T_18 | _in_d_bits_T_17; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_6 = _in_d_bits_T_19; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_sink = _in_d_bits_WIRE_6; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_20 = muxState_1_0 ? d_d_bits_source : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_21 = muxState_1_1 ? _q_io_deq_bits_source : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_22 = muxState_1_2 ? _q_1_io_deq_bits_source : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_23 = _in_d_bits_T_20 | _in_d_bits_T_21; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_24 = _in_d_bits_T_23 | _in_d_bits_T_22; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_7 = _in_d_bits_T_24; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_source = _in_d_bits_WIRE_7; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_25 = muxState_1_0 ? d_d_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_26 = muxState_1_1 ? _q_io_deq_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_27 = muxState_1_2 ? _q_1_io_deq_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_28 = _in_d_bits_T_25 | _in_d_bits_T_26; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_29 = _in_d_bits_T_28 | _in_d_bits_T_27; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_8 = _in_d_bits_T_29; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_size = _in_d_bits_WIRE_8; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_30 = muxState_1_0 ? d_d_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_31 = muxState_1_1 ? _q_io_deq_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_32 = muxState_1_2 ? _q_1_io_deq_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_33 = _in_d_bits_T_30 | _in_d_bits_T_31; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_34 = _in_d_bits_T_33 | _in_d_bits_T_32; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_9 = _in_d_bits_T_34; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_param = _in_d_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_35 = muxState_1_0 ? d_d_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_36 = muxState_1_1 ? _q_io_deq_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_37 = muxState_1_2 ? _q_1_io_deq_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_38 = _in_d_bits_T_35 | _in_d_bits_T_36; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_39 = _in_d_bits_T_38 | _in_d_bits_T_37; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_10 = _in_d_bits_T_39; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_opcode = _in_d_bits_WIRE_10; // @[Mux.scala:30:73]
wire _a_a_ready_T_1; // @[Arbiter.scala:94:31]
wire _a_a_valid_T_3; // @[CacheCork.scala:81:33]
wire [2:0] a_a_1_bits_opcode; // @[CacheCork.scala:74:23]
wire [2:0] a_a_1_bits_param; // @[CacheCork.scala:74:23]
wire [4:0] a_a_1_bits_source; // @[CacheCork.scala:74:23]
wire a_a_1_ready; // @[CacheCork.scala:74:23]
wire a_a_1_valid; // @[CacheCork.scala:74:23]
wire _a_d_valid_T_1; // @[CacheCork.scala:93:33]
wire [2:0] a_d_1_bits_size; // @[CacheCork.scala:75:23]
wire [3:0] a_d_1_bits_source; // @[CacheCork.scala:75:23]
wire a_d_1_ready; // @[CacheCork.scala:75:23]
wire a_d_1_valid; // @[CacheCork.scala:75:23]
wire _isPut_T_2 = nodeIn_1_a_bits_opcode == 3'h0; // @[CacheCork.scala:76:38]
wire _isPut_T_3 = nodeIn_1_a_bits_opcode == 3'h1; // @[CacheCork.scala:76:74]
wire isPut_1 = _isPut_T_2 | _isPut_T_3; // @[CacheCork.scala:76:{38,54,74}]
wire _a_a_bits_source_T_6 = isPut_1; // @[CacheCork.scala:76:54, :83:55]
wire _toD_T_4 = nodeIn_1_a_bits_opcode == 3'h6; // @[CacheCork.scala:77:37]
wire _toD_T_5 = nodeIn_1_a_bits_param == 3'h2; // @[CacheCork.scala:77:73]
wire _toD_T_6 = _toD_T_4 & _toD_T_5; // @[CacheCork.scala:77:{37,54,73}]
wire _toD_T_7 = &nodeIn_1_a_bits_opcode; // @[CacheCork.scala:78:37]
wire toD_1 = _toD_T_6 | _toD_T_7; // @[CacheCork.scala:77:{54,97}, :78:37]
assign _nodeIn_a_ready_T_1 = toD_1 ? a_d_1_ready : a_a_1_ready; // @[CacheCork.scala:74:23, :75:23, :77:97, :79:26]
assign nodeIn_1_a_ready = _nodeIn_a_ready_T_1; // @[CacheCork.scala:79:26]
wire _a_a_valid_T_2 = ~toD_1; // @[CacheCork.scala:77:97, :81:36]
assign _a_a_valid_T_3 = nodeIn_1_a_valid & _a_a_valid_T_2; // @[CacheCork.scala:81:{33,36}]
assign a_a_1_valid = _a_a_valid_T_3; // @[CacheCork.scala:74:23, :81:33]
wire [4:0] _GEN_1 = {nodeIn_1_a_bits_source, 1'h0}; // @[CacheCork.scala:83:45]
wire [4:0] _a_a_bits_source_T_5; // @[CacheCork.scala:83:45]
assign _a_a_bits_source_T_5 = _GEN_1; // @[CacheCork.scala:83:45]
wire [4:0] _a_a_bits_source_T_8; // @[CacheCork.scala:89:47]
assign _a_a_bits_source_T_8 = _GEN_1; // @[CacheCork.scala:83:45, :89:47]
wire [4:0] _a_a_bits_source_T_7 = {_a_a_bits_source_T_5[4:1], _a_a_bits_source_T_5[0] | _a_a_bits_source_T_6}; // @[CacheCork.scala:83:{45,50,55}]
wire _T_68 = _toD_T_4 | (&nodeIn_1_a_bits_opcode); // @[CacheCork.scala:77:37, :78:37, :86:49]
assign a_a_1_bits_opcode = _T_68 ? 3'h4 : nodeIn_1_a_bits_opcode; // @[CacheCork.scala:74:23, :82:18, :86:{49,86}, :87:27]
assign a_a_1_bits_param = _T_68 ? 3'h0 : nodeIn_1_a_bits_param; // @[CacheCork.scala:74:23, :82:18, :86:{49,86}, :88:27]
wire [4:0] _a_a_bits_source_T_9 = {_a_a_bits_source_T_8[4:1], 1'h1}; // @[CacheCork.scala:89:{47,52}]
assign a_a_1_bits_source = _T_68 ? _a_a_bits_source_T_9 : _a_a_bits_source_T_7; // @[CacheCork.scala:74:23, :83:{25,50}, :86:{49,86}, :89:{27,52}]
assign _a_d_valid_T_1 = nodeIn_1_a_valid & toD_1; // @[CacheCork.scala:77:97, :93:33]
assign a_d_1_valid = _a_d_valid_T_1; // @[CacheCork.scala:75:23, :93:33]
assign a_d_1_bits_size = a_d_bits_d_1_size; // @[Edges.scala:645:17]
assign a_d_1_bits_source = a_d_bits_d_1_source; // @[Edges.scala:645:17]
wire _c_a_ready_T_1; // @[Arbiter.scala:94:31]
wire _c_a_valid_T_3; // @[CacheCork.scala:102:33]
wire [4:0] c_a_bits_a_1_source; // @[Edges.scala:480:17]
wire [7:0] c_a_bits_a_1_mask; // @[Edges.scala:480:17]
wire [2:0] c_a_1_bits_size; // @[CacheCork.scala:101:23]
wire [4:0] c_a_1_bits_source; // @[CacheCork.scala:101:23]
wire [31:0] c_a_1_bits_address; // @[CacheCork.scala:101:23]
wire [7:0] c_a_1_bits_mask; // @[CacheCork.scala:101:23]
wire [63:0] c_a_1_bits_data; // @[CacheCork.scala:101:23]
wire c_a_1_bits_corrupt; // @[CacheCork.scala:101:23]
wire c_a_1_ready; // @[CacheCork.scala:101:23]
wire c_a_1_valid; // @[CacheCork.scala:101:23]
wire _c_a_valid_T_2 = &nodeIn_1_c_bits_opcode; // @[CacheCork.scala:102:53]
assign _c_a_valid_T_3 = nodeIn_1_c_valid & _c_a_valid_T_2; // @[CacheCork.scala:102:{33,53}]
assign c_a_1_valid = _c_a_valid_T_3; // @[CacheCork.scala:101:23, :102:33]
wire [4:0] _c_a_bits_T_1 = {nodeIn_1_c_bits_source, 1'h0}; // @[CacheCork.scala:104:41]
assign c_a_bits_a_1_source = _c_a_bits_T_1; // @[Edges.scala:480:17]
wire _c_a_bits_legal_T_11 = nodeIn_1_c_bits_size != 3'h7; // @[Parameters.scala:92:38]
wire _c_a_bits_legal_T_12 = _c_a_bits_legal_T_11; // @[Parameters.scala:92:{33,38}]
wire _c_a_bits_legal_T_13 = _c_a_bits_legal_T_12; // @[Parameters.scala:684:29]
wire _c_a_bits_legal_T_19 = _c_a_bits_legal_T_13; // @[Parameters.scala:684:{29,54}]
wire [32:0] _c_a_bits_legal_T_15 = {1'h0, _c_a_bits_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire c_a_bits_legal_1 = _c_a_bits_legal_T_19; // @[Parameters.scala:684:54, :686:26]
assign c_a_1_bits_size = c_a_bits_a_1_size; // @[Edges.scala:480:17]
assign c_a_1_bits_source = c_a_bits_a_1_source; // @[Edges.scala:480:17]
assign c_a_1_bits_address = c_a_bits_a_1_address; // @[Edges.scala:480:17]
wire [7:0] _c_a_bits_a_mask_T_1; // @[Misc.scala:222:10]
assign c_a_1_bits_mask = c_a_bits_a_1_mask; // @[Edges.scala:480:17]
assign c_a_1_bits_data = c_a_bits_a_1_data; // @[Edges.scala:480:17]
assign c_a_1_bits_corrupt = c_a_bits_a_1_corrupt; // @[Edges.scala:480:17]
wire [1:0] c_a_bits_a_mask_sizeOH_shiftAmount_1 = _c_a_bits_a_mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _c_a_bits_a_mask_sizeOH_T_4 = 4'h1 << c_a_bits_a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _c_a_bits_a_mask_sizeOH_T_5 = _c_a_bits_a_mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] c_a_bits_a_mask_sizeOH_1 = {_c_a_bits_a_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire c_a_bits_a_mask_sub_sub_sub_0_1_1 = nodeIn_1_c_bits_size > 3'h2; // @[Misc.scala:206:21]
wire c_a_bits_a_mask_sub_sub_size_1 = c_a_bits_a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26]
wire c_a_bits_a_mask_sub_sub_bit_1 = nodeIn_1_c_bits_address[2]; // @[Misc.scala:210:26]
wire c_a_bits_a_mask_sub_sub_1_2_1 = c_a_bits_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire c_a_bits_a_mask_sub_sub_nbit_1 = ~c_a_bits_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire c_a_bits_a_mask_sub_sub_0_2_1 = c_a_bits_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_sub_sub_acc_T_2 = c_a_bits_a_mask_sub_sub_size_1 & c_a_bits_a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_sub_0_1_1 = c_a_bits_a_mask_sub_sub_sub_0_1_1 | _c_a_bits_a_mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}]
wire _c_a_bits_a_mask_sub_sub_acc_T_3 = c_a_bits_a_mask_sub_sub_size_1 & c_a_bits_a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_sub_1_1_1 = c_a_bits_a_mask_sub_sub_sub_0_1_1 | _c_a_bits_a_mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}]
wire c_a_bits_a_mask_sub_size_1 = c_a_bits_a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26]
wire c_a_bits_a_mask_sub_bit_1 = nodeIn_1_c_bits_address[1]; // @[Misc.scala:210:26]
wire c_a_bits_a_mask_sub_nbit_1 = ~c_a_bits_a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire c_a_bits_a_mask_sub_0_2_1 = c_a_bits_a_mask_sub_sub_0_2_1 & c_a_bits_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_4 = c_a_bits_a_mask_sub_size_1 & c_a_bits_a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_0_1_1 = c_a_bits_a_mask_sub_sub_0_1_1 | _c_a_bits_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_sub_1_2_1 = c_a_bits_a_mask_sub_sub_0_2_1 & c_a_bits_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_5 = c_a_bits_a_mask_sub_size_1 & c_a_bits_a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_1_1_1 = c_a_bits_a_mask_sub_sub_0_1_1 | _c_a_bits_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_sub_2_2_1 = c_a_bits_a_mask_sub_sub_1_2_1 & c_a_bits_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_6 = c_a_bits_a_mask_sub_size_1 & c_a_bits_a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_2_1_1 = c_a_bits_a_mask_sub_sub_1_1_1 | _c_a_bits_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_sub_3_2_1 = c_a_bits_a_mask_sub_sub_1_2_1 & c_a_bits_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_7 = c_a_bits_a_mask_sub_size_1 & c_a_bits_a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_3_1_1 = c_a_bits_a_mask_sub_sub_1_1_1 | _c_a_bits_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_size_1 = c_a_bits_a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26]
wire c_a_bits_a_mask_bit_1 = nodeIn_1_c_bits_address[0]; // @[Misc.scala:210:26]
wire c_a_bits_a_mask_nbit_1 = ~c_a_bits_a_mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire c_a_bits_a_mask_eq_8 = c_a_bits_a_mask_sub_0_2_1 & c_a_bits_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_8 = c_a_bits_a_mask_size_1 & c_a_bits_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_8 = c_a_bits_a_mask_sub_0_1_1 | _c_a_bits_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_9 = c_a_bits_a_mask_sub_0_2_1 & c_a_bits_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_9 = c_a_bits_a_mask_size_1 & c_a_bits_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_9 = c_a_bits_a_mask_sub_0_1_1 | _c_a_bits_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_10 = c_a_bits_a_mask_sub_1_2_1 & c_a_bits_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_10 = c_a_bits_a_mask_size_1 & c_a_bits_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_10 = c_a_bits_a_mask_sub_1_1_1 | _c_a_bits_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_11 = c_a_bits_a_mask_sub_1_2_1 & c_a_bits_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_11 = c_a_bits_a_mask_size_1 & c_a_bits_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_11 = c_a_bits_a_mask_sub_1_1_1 | _c_a_bits_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_12 = c_a_bits_a_mask_sub_2_2_1 & c_a_bits_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_12 = c_a_bits_a_mask_size_1 & c_a_bits_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_12 = c_a_bits_a_mask_sub_2_1_1 | _c_a_bits_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_13 = c_a_bits_a_mask_sub_2_2_1 & c_a_bits_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_13 = c_a_bits_a_mask_size_1 & c_a_bits_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_13 = c_a_bits_a_mask_sub_2_1_1 | _c_a_bits_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_14 = c_a_bits_a_mask_sub_3_2_1 & c_a_bits_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_14 = c_a_bits_a_mask_size_1 & c_a_bits_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_14 = c_a_bits_a_mask_sub_3_1_1 | _c_a_bits_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_15 = c_a_bits_a_mask_sub_3_2_1 & c_a_bits_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_15 = c_a_bits_a_mask_size_1 & c_a_bits_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_15 = c_a_bits_a_mask_sub_3_1_1 | _c_a_bits_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] c_a_bits_a_mask_lo_lo_1 = {c_a_bits_a_mask_acc_9, c_a_bits_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] c_a_bits_a_mask_lo_hi_1 = {c_a_bits_a_mask_acc_11, c_a_bits_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] c_a_bits_a_mask_lo_1 = {c_a_bits_a_mask_lo_hi_1, c_a_bits_a_mask_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] c_a_bits_a_mask_hi_lo_1 = {c_a_bits_a_mask_acc_13, c_a_bits_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] c_a_bits_a_mask_hi_hi_1 = {c_a_bits_a_mask_acc_15, c_a_bits_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] c_a_bits_a_mask_hi_1 = {c_a_bits_a_mask_hi_hi_1, c_a_bits_a_mask_hi_lo_1}; // @[Misc.scala:222:10]
assign _c_a_bits_a_mask_T_1 = {c_a_bits_a_mask_hi_1, c_a_bits_a_mask_lo_1}; // @[Misc.scala:222:10]
assign c_a_bits_a_1_mask = _c_a_bits_a_mask_T_1; // @[Misc.scala:222:10]
wire _c_d_valid_T_3; // @[CacheCork.scala:113:33]
wire [2:0] c_d_1_bits_size; // @[CacheCork.scala:112:23]
wire [3:0] c_d_1_bits_source; // @[CacheCork.scala:112:23]
wire c_d_1_ready; // @[CacheCork.scala:112:23]
wire c_d_1_valid; // @[CacheCork.scala:112:23]
wire _T_70 = nodeIn_1_c_bits_opcode == 3'h6; // @[CacheCork.scala:113:53]
wire _c_d_valid_T_2; // @[CacheCork.scala:113:53]
assign _c_d_valid_T_2 = _T_70; // @[CacheCork.scala:113:53]
wire _nodeIn_c_ready_T_2; // @[CacheCork.scala:117:44]
assign _nodeIn_c_ready_T_2 = _T_70; // @[CacheCork.scala:113:53, :117:44]
assign _c_d_valid_T_3 = nodeIn_1_c_valid & _c_d_valid_T_2; // @[CacheCork.scala:113:{33,53}]
assign c_d_1_valid = _c_d_valid_T_3; // @[CacheCork.scala:112:23, :113:33]
assign c_d_1_bits_size = c_d_bits_d_1_size; // @[Edges.scala:677:17]
assign c_d_1_bits_source = c_d_bits_d_1_source; // @[Edges.scala:677:17]
assign _nodeIn_c_ready_T_3 = _nodeIn_c_ready_T_2 ? c_d_1_ready : c_a_1_ready; // @[CacheCork.scala:101:23, :112:23, :117:{26,44}]
assign nodeIn_1_c_ready = _nodeIn_c_ready_T_3; // @[CacheCork.scala:117:26]
wire _in_d_ready_T_9; // @[CacheCork.scala:136:34]
wire _in_d_valid_T_15; // @[Arbiter.scala:96:24]
wire [2:0] _in_d_bits_WIRE_11_opcode; // @[Mux.scala:30:73]
assign nodeIn_1_d_bits_opcode = in_d_1_bits_opcode; // @[CacheCork.scala:131:24]
wire [1:0] _in_d_bits_WIRE_11_param; // @[Mux.scala:30:73]
assign nodeIn_1_d_bits_param = in_d_1_bits_param; // @[CacheCork.scala:131:24]
wire [2:0] _in_d_bits_WIRE_11_size; // @[Mux.scala:30:73]
assign nodeIn_1_d_bits_size = in_d_1_bits_size; // @[CacheCork.scala:131:24]
wire [3:0] _in_d_bits_WIRE_11_source; // @[Mux.scala:30:73]
assign nodeIn_1_d_bits_source = in_d_1_bits_source; // @[CacheCork.scala:131:24]
wire [2:0] _in_d_bits_WIRE_11_sink; // @[Mux.scala:30:73]
wire _in_d_bits_WIRE_11_denied; // @[Mux.scala:30:73]
assign nodeIn_1_d_bits_denied = in_d_1_bits_denied; // @[CacheCork.scala:131:24]
wire [63:0] _in_d_bits_WIRE_11_data; // @[Mux.scala:30:73]
assign nodeIn_1_d_bits_data = in_d_1_bits_data; // @[CacheCork.scala:131:24]
wire _in_d_bits_WIRE_11_corrupt; // @[Mux.scala:30:73]
assign nodeIn_1_d_bits_corrupt = in_d_1_bits_corrupt; // @[CacheCork.scala:131:24]
wire [2:0] in_d_1_bits_sink; // @[CacheCork.scala:131:24]
wire in_d_1_ready; // @[CacheCork.scala:131:24]
wire in_d_1_valid; // @[CacheCork.scala:131:24]
wire _GEN_2 = in_d_1_ready & in_d_1_valid; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _GEN_2; // @[Decoupled.scala:51:35]
wire _beatsLeft_T_12; // @[Decoupled.scala:51:35]
assign _beatsLeft_T_12 = _GEN_2; // @[Decoupled.scala:51:35]
wire [12:0] _d_first_beats1_decode_T_3 = 13'h3F << in_d_1_bits_size; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata_1 = in_d_1_bits_opcode[0]; // @[Edges.scala:106:36]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _d_grant_T_2 = in_d_1_bits_opcode == 3'h5; // @[CacheCork.scala:131:24, :133:40]
wire _d_grant_T_3 = in_d_1_bits_opcode == 3'h4; // @[CacheCork.scala:131:24, :133:74]
wire d_grant_1 = _d_grant_T_2 | _d_grant_T_3; // @[CacheCork.scala:133:{40,54,74}]
wire _pool_io_alloc_ready_T_3 = nodeIn_1_d_ready & nodeIn_1_d_valid; // @[Decoupled.scala:51:35]
wire _pool_io_alloc_ready_T_4 = _pool_io_alloc_ready_T_3 & d_first_1; // @[Decoupled.scala:51:35]
wire _pool_io_alloc_ready_T_5 = _pool_io_alloc_ready_T_4 & d_grant_1; // @[CacheCork.scala:133:54, :134:{42,53}]
wire _nodeIn_d_valid_T_5 = ~d_first_1; // @[Edges.scala:231:25]
wire _nodeIn_d_valid_T_6 = _pool_1_io_alloc_valid | _nodeIn_d_valid_T_5; // @[CacheCork.scala:127:26, :135:{58,61}]
wire _nodeIn_d_valid_T_7 = ~d_grant_1; // @[CacheCork.scala:133:54, :135:73]
wire _nodeIn_d_valid_T_8 = _nodeIn_d_valid_T_6 | _nodeIn_d_valid_T_7; // @[CacheCork.scala:135:{58,70,73}]
assign _nodeIn_d_valid_T_9 = in_d_1_valid & _nodeIn_d_valid_T_8; // @[CacheCork.scala:131:24, :135:{34,70}]
assign nodeIn_1_d_valid = _nodeIn_d_valid_T_9; // @[CacheCork.scala:135:34]
wire _in_d_ready_T_5 = ~d_first_1; // @[Edges.scala:231:25]
wire _in_d_ready_T_6 = _pool_1_io_alloc_valid | _in_d_ready_T_5; // @[CacheCork.scala:127:26, :136:{58,61}]
wire _in_d_ready_T_7 = ~d_grant_1; // @[CacheCork.scala:133:54, :135:73, :136:73]
wire _in_d_ready_T_8 = _in_d_ready_T_6 | _in_d_ready_T_7; // @[CacheCork.scala:136:{58,70,73}]
assign _in_d_ready_T_9 = nodeIn_1_d_ready & _in_d_ready_T_8; // @[CacheCork.scala:136:{34,70}]
assign in_d_1_ready = _in_d_ready_T_9; // @[CacheCork.scala:131:24, :136:34]
reg [2:0] nodeIn_d_bits_sink_r_1; // @[package.scala:88:63]
assign _nodeIn_d_bits_sink_T_1 = d_first_1 ? _pool_1_io_alloc_bits : nodeIn_d_bits_sink_r_1; // @[package.scala:88:{42,63}]
assign nodeIn_1_d_bits_sink = _nodeIn_d_bits_sink_T_1; // @[package.scala:88:42]
wire _d_d_ready_T_1; // @[Arbiter.scala:94:31]
assign x1_nodeOut_d_ready = d_d_1_ready; // @[CacheCork.scala:141:23]
wire [3:0] _d_d_bits_source_T_1; // @[CacheCork.scala:143:46]
wire [2:0] d_d_1_bits_opcode; // @[CacheCork.scala:141:23]
wire [1:0] d_d_1_bits_param; // @[CacheCork.scala:141:23]
wire [3:0] d_d_1_bits_source; // @[CacheCork.scala:141:23]
wire [2:0] d_d_1_bits_sink; // @[CacheCork.scala:141:23]
assign d_d_1_bits_sink = {2'h0, x1_nodeOut_d_bits_sink}; // @[CacheCork.scala:141:23, :142:13]
assign _d_d_bits_source_T_1 = x1_nodeOut_d_bits_source[4:1]; // @[CacheCork.scala:143:46]
assign d_d_1_bits_source = _d_d_bits_source_T_1; // @[CacheCork.scala:141:23, :143:46]
wire [32:0] _aWOk_T_6 = {1'h0, _aWOk_T_5}; // @[Parameters.scala:137:{31,41}]
wire _bypass_T_3 = nodeIn_1_a_bits_source == d_d_1_bits_source; // @[CacheCork.scala:141:23, :150:91]
reg dWHeld_r_1; // @[package.scala:88:63]
wire dWHeld_1 = d_first_1 ? _dWHeld_T_1 : dWHeld_r_1; // @[package.scala:88:{42,63}]
wire _T_84 = x1_nodeOut_d_bits_opcode == 3'h1 & x1_nodeOut_d_bits_source[0]; // @[CacheCork.scala:162:{33,51,71}]
wire [1:0] _d_d_bits_param_T_1 = {1'h0, ~dWHeld_1}; // @[package.scala:88:42]
assign d_d_1_bits_param = _T_84 ? _d_d_bits_param_T_1 : x1_nodeOut_d_bits_param; // @[CacheCork.scala:141:23, :142:13, :162:{51,76}, :164:{26,32}]
assign d_d_1_bits_opcode = x1_nodeOut_d_bits_opcode == 3'h0 & ~(x1_nodeOut_d_bits_source[0]) ? 3'h6 : _T_84 ? 3'h5 : x1_nodeOut_d_bits_opcode; // @[CacheCork.scala:141:23, :142:13, :162:{51,71,76}, :163:27, :166:{33,47,50,73}, :167:27]
wire [12:0] _decode_T_9 = 13'h3F << c_a_1_bits_size; // @[package.scala:243:71]
wire [5:0] _decode_T_10 = _decode_T_9[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _decode_T_11 = ~_decode_T_10; // @[package.scala:243:{46,76}]
wire [2:0] decode_3 = _decode_T_11[5:3]; // @[package.scala:243:46]
wire [12:0] _decode_T_12 = 13'h3F << a_a_1_bits_size; // @[package.scala:243:71]
wire [5:0] _decode_T_13 = _decode_T_12[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _decode_T_14 = ~_decode_T_13; // @[package.scala:243:{46,76}]
wire [2:0] decode_4 = _decode_T_14[5:3]; // @[package.scala:243:46]
wire _opdata_T_3 = a_a_1_bits_opcode[2]; // @[Edges.scala:92:37]
wire opdata_4 = ~_opdata_T_3; // @[Edges.scala:92:{28,37}]
reg [2:0] beatsLeft_2; // @[Arbiter.scala:60:30]
wire idle_2 = beatsLeft_2 == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_2 = idle_2 & x1_nodeOut_a_ready; // @[Arbiter.scala:61:28, :62:24]
wire [1:0] _readys_T_24 = {a_a_1_valid, c_a_1_valid}; // @[CacheCork.scala:74:23, :101:23]
wire [2:0] _readys_T_25 = {_readys_T_24, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_T_26 = _readys_T_25[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_T_27 = _readys_T_24 | _readys_T_26; // @[package.scala:253:{43,53}]
wire [1:0] _readys_T_28 = _readys_T_27; // @[package.scala:253:43, :254:17]
wire [2:0] _readys_T_29 = {_readys_T_28, 1'h0}; // @[package.scala:254:17]
wire [1:0] _readys_T_30 = _readys_T_29[1:0]; // @[Arbiter.scala:16:{78,83}]
wire [1:0] _readys_T_31 = ~_readys_T_30; // @[Arbiter.scala:16:{61,83}]
wire _readys_T_32 = _readys_T_31[0]; // @[Arbiter.scala:16:61, :68:76]
wire readys_2_0 = _readys_T_32; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_33 = _readys_T_31[1]; // @[Arbiter.scala:16:61, :68:76]
wire readys_2_1 = _readys_T_33; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_5 = readys_2_0 & c_a_1_valid; // @[CacheCork.scala:101:23]
wire winner_2_0 = _winner_T_5; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_6 = readys_2_1 & a_a_1_valid; // @[CacheCork.scala:74:23]
wire winner_2_1 = _winner_T_6; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_2 = winner_2_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_2 = prefixOR_1_2 | winner_2_1; // @[Arbiter.scala:71:27, :76:48]
wire _nodeOut_a_valid_T_5 = c_a_1_valid | a_a_1_valid; // @[CacheCork.scala:74:23, :101:23]
wire [2:0] maskedBeats_0_2 = winner_2_0 ? decode_3 : 3'h0; // @[Edges.scala:220:59, :221:14]
wire [2:0] maskedBeats_1_2 = winner_2_1 & opdata_4 ? decode_4 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [2:0] initBeats_2 = maskedBeats_0_2 | maskedBeats_1_2; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_8 = x1_nodeOut_a_ready & x1_nodeOut_a_valid; // @[Decoupled.scala:51:35]
wire [3:0] _beatsLeft_T_9 = {1'h0, beatsLeft_2} - {3'h0, _beatsLeft_T_8}; // @[Decoupled.scala:51:35]
wire [2:0] _beatsLeft_T_10 = _beatsLeft_T_9[2:0]; // @[Arbiter.scala:85:52]
wire [2:0] _beatsLeft_T_11 = latch_2 ? initBeats_2 : _beatsLeft_T_10; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_2_0; // @[Arbiter.scala:88:26]
reg state_2_1; // @[Arbiter.scala:88:26]
wire muxState_2_0 = idle_2 ? winner_2_0 : state_2_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_2_1 = idle_2 ? winner_2_1 : state_2_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_2_0 = idle_2 ? readys_2_0 : state_2_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_2_1 = idle_2 ? readys_2_1 : state_2_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _c_a_ready_T_1 = x1_nodeOut_a_ready & allowed_2_0; // @[Arbiter.scala:92:24, :94:31]
assign c_a_1_ready = _c_a_ready_T_1; // @[CacheCork.scala:101:23]
assign _a_a_ready_T_1 = x1_nodeOut_a_ready & allowed_2_1; // @[Arbiter.scala:92:24, :94:31]
assign a_a_1_ready = _a_a_ready_T_1; // @[CacheCork.scala:74:23]
wire _nodeOut_a_valid_T_6 = state_2_0 & c_a_1_valid; // @[Mux.scala:30:73]
wire _nodeOut_a_valid_T_7 = state_2_1 & a_a_1_valid; // @[Mux.scala:30:73]
wire _nodeOut_a_valid_T_8 = _nodeOut_a_valid_T_6 | _nodeOut_a_valid_T_7; // @[Mux.scala:30:73]
wire _nodeOut_a_valid_WIRE_1 = _nodeOut_a_valid_T_8; // @[Mux.scala:30:73]
assign _nodeOut_a_valid_T_9 = idle_2 ? _nodeOut_a_valid_T_5 : _nodeOut_a_valid_WIRE_1; // @[Mux.scala:30:73]
assign x1_nodeOut_a_valid = _nodeOut_a_valid_T_9; // @[Arbiter.scala:96:24]
wire [2:0] _nodeOut_a_bits_WIRE_21; // @[Mux.scala:30:73]
assign x1_nodeOut_a_bits_opcode = _nodeOut_a_bits_WIRE_11_opcode; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_WIRE_20; // @[Mux.scala:30:73]
assign x1_nodeOut_a_bits_param = _nodeOut_a_bits_WIRE_11_param; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_WIRE_19; // @[Mux.scala:30:73]
assign x1_nodeOut_a_bits_size = _nodeOut_a_bits_WIRE_11_size; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_WIRE_18; // @[Mux.scala:30:73]
assign x1_nodeOut_a_bits_source = _nodeOut_a_bits_WIRE_11_source; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_WIRE_17; // @[Mux.scala:30:73]
assign x1_nodeOut_a_bits_address = _nodeOut_a_bits_WIRE_11_address; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_WIRE_14; // @[Mux.scala:30:73]
assign x1_nodeOut_a_bits_mask = _nodeOut_a_bits_WIRE_11_mask; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_WIRE_13; // @[Mux.scala:30:73]
assign x1_nodeOut_a_bits_data = _nodeOut_a_bits_WIRE_11_data; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_WIRE_12; // @[Mux.scala:30:73]
assign x1_nodeOut_a_bits_corrupt = _nodeOut_a_bits_WIRE_11_corrupt; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T_24 = muxState_2_0 & c_a_1_bits_corrupt; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T_25 = muxState_2_1 & a_a_1_bits_corrupt; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T_26 = _nodeOut_a_bits_T_24 | _nodeOut_a_bits_T_25; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_12 = _nodeOut_a_bits_T_26; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_11_corrupt = _nodeOut_a_bits_WIRE_12; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_T_27 = muxState_2_0 ? c_a_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_T_28 = muxState_2_1 ? a_a_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_T_29 = _nodeOut_a_bits_T_27 | _nodeOut_a_bits_T_28; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_13 = _nodeOut_a_bits_T_29; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_11_data = _nodeOut_a_bits_WIRE_13; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_T_30 = muxState_2_0 ? c_a_1_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_T_31 = muxState_2_1 ? a_a_1_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_T_32 = _nodeOut_a_bits_T_30 | _nodeOut_a_bits_T_31; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_14 = _nodeOut_a_bits_T_32; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_11_mask = _nodeOut_a_bits_WIRE_14; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_T_33 = muxState_2_0 ? c_a_1_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_T_34 = muxState_2_1 ? a_a_1_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_T_35 = _nodeOut_a_bits_T_33 | _nodeOut_a_bits_T_34; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_17 = _nodeOut_a_bits_T_35; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_11_address = _nodeOut_a_bits_WIRE_17; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_T_36 = muxState_2_0 ? c_a_1_bits_source : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_T_37 = muxState_2_1 ? a_a_1_bits_source : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_T_38 = _nodeOut_a_bits_T_36 | _nodeOut_a_bits_T_37; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_18 = _nodeOut_a_bits_T_38; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_11_source = _nodeOut_a_bits_WIRE_18; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_39 = muxState_2_0 ? c_a_1_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_40 = muxState_2_1 ? a_a_1_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_41 = _nodeOut_a_bits_T_39 | _nodeOut_a_bits_T_40; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_19 = _nodeOut_a_bits_T_41; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_11_size = _nodeOut_a_bits_WIRE_19; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_43 = muxState_2_1 ? a_a_1_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_44 = _nodeOut_a_bits_T_43; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_20 = _nodeOut_a_bits_T_44; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_11_param = _nodeOut_a_bits_WIRE_20; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_46 = muxState_2_1 ? a_a_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_47 = _nodeOut_a_bits_T_46; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_21 = _nodeOut_a_bits_T_47; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_11_opcode = _nodeOut_a_bits_WIRE_21; // @[Mux.scala:30:73]
wire [12:0] _decode_T_15 = 13'h3F << d_d_1_bits_size; // @[package.scala:243:71]
wire [5:0] _decode_T_16 = _decode_T_15[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _decode_T_17 = ~_decode_T_16; // @[package.scala:243:{46,76}]
wire [2:0] decode_5 = _decode_T_17[5:3]; // @[package.scala:243:46]
wire opdata_5 = d_d_1_bits_opcode[0]; // @[Edges.scala:106:36]
reg [2:0] beatsLeft_3; // @[Arbiter.scala:60:30]
wire idle_3 = beatsLeft_3 == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_3 = idle_3 & in_d_1_ready; // @[CacheCork.scala:131:24]
wire [1:0] readys_hi_1 = {_q_3_io_deq_valid, _q_2_io_deq_valid}; // @[Decoupled.scala:362:21]
wire [2:0] _readys_T_34 = {readys_hi_1, d_d_1_valid}; // @[CacheCork.scala:141:23]
wire [3:0] _readys_T_35 = {_readys_T_34, 1'h0}; // @[package.scala:253:48]
wire [2:0] _readys_T_36 = _readys_T_35[2:0]; // @[package.scala:253:{48,53}]
wire [2:0] _readys_T_37 = _readys_T_34 | _readys_T_36; // @[package.scala:253:{43,53}]
wire [4:0] _readys_T_38 = {_readys_T_37, 2'h0}; // @[package.scala:253:{43,48}]
wire [2:0] _readys_T_39 = _readys_T_38[2:0]; // @[package.scala:253:{48,53}]
wire [2:0] _readys_T_40 = _readys_T_37 | _readys_T_39; // @[package.scala:253:{43,53}]
wire [2:0] _readys_T_41 = _readys_T_40; // @[package.scala:253:43, :254:17]
wire [3:0] _readys_T_42 = {_readys_T_41, 1'h0}; // @[package.scala:254:17]
wire [2:0] _readys_T_43 = _readys_T_42[2:0]; // @[Arbiter.scala:16:{78,83}]
wire [2:0] _readys_T_44 = ~_readys_T_43; // @[Arbiter.scala:16:{61,83}]
wire _readys_T_45 = _readys_T_44[0]; // @[Arbiter.scala:16:61, :68:76]
wire readys_3_0 = _readys_T_45; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_46 = _readys_T_44[1]; // @[Arbiter.scala:16:61, :68:76]
wire readys_3_1 = _readys_T_46; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_47 = _readys_T_44[2]; // @[Arbiter.scala:16:61, :68:76]
wire readys_3_2 = _readys_T_47; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_7 = readys_3_0 & d_d_1_valid; // @[CacheCork.scala:141:23]
wire winner_3_0 = _winner_T_7; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_8 = readys_3_1 & _q_2_io_deq_valid; // @[Decoupled.scala:362:21]
wire winner_3_1 = _winner_T_8; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_9 = readys_3_2 & _q_3_io_deq_valid; // @[Decoupled.scala:362:21]
wire winner_3_2 = _winner_T_9; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_3 = winner_3_0; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_2_1 = prefixOR_1_3 | winner_3_1; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_3 = prefixOR_2_1 | winner_3_2; // @[Arbiter.scala:71:27, :76:48]
wire _in_d_valid_T_8 = d_d_1_valid | _q_2_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] maskedBeats_0_3 = winner_3_0 & opdata_5 ? decode_5 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire [2:0] _initBeats_T_1 = maskedBeats_0_3; // @[Arbiter.scala:82:69, :84:44]
wire [2:0] initBeats_3 = _initBeats_T_1; // @[Arbiter.scala:84:44]
wire [3:0] _beatsLeft_T_13 = {1'h0, beatsLeft_3} - {3'h0, _beatsLeft_T_12}; // @[Decoupled.scala:51:35]
wire [2:0] _beatsLeft_T_14 = _beatsLeft_T_13[2:0]; // @[Arbiter.scala:85:52]
wire [2:0] _beatsLeft_T_15 = latch_3 ? initBeats_3 : _beatsLeft_T_14; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_3_0; // @[Arbiter.scala:88:26]
reg state_3_1; // @[Arbiter.scala:88:26]
reg state_3_2; // @[Arbiter.scala:88:26]
wire muxState_3_0 = idle_3 ? winner_3_0 : state_3_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_3_1 = idle_3 ? winner_3_1 : state_3_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_3_2 = idle_3 ? winner_3_2 : state_3_2; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_3_0 = idle_3 ? readys_3_0 : state_3_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_3_1 = idle_3 ? readys_3_1 : state_3_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_3_2 = idle_3 ? readys_3_2 : state_3_2; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _d_d_ready_T_1 = in_d_1_ready & allowed_3_0; // @[CacheCork.scala:131:24]
assign d_d_1_ready = _d_d_ready_T_1; // @[CacheCork.scala:141:23]
wire _q_io_deq_ready_T_2 = in_d_1_ready & allowed_3_1; // @[CacheCork.scala:131:24]
wire _q_io_deq_ready_T_3 = in_d_1_ready & allowed_3_2; // @[CacheCork.scala:131:24]
wire _in_d_valid_T_9 = _in_d_valid_T_8 | _q_3_io_deq_valid; // @[Decoupled.scala:362:21]
wire _in_d_valid_T_10 = state_3_0 & d_d_1_valid; // @[Mux.scala:30:73]
wire _in_d_valid_T_11 = state_3_1 & _q_2_io_deq_valid; // @[Mux.scala:30:73]
wire _in_d_valid_T_12 = state_3_2 & _q_3_io_deq_valid; // @[Mux.scala:30:73]
wire _in_d_valid_T_13 = _in_d_valid_T_10 | _in_d_valid_T_11; // @[Mux.scala:30:73]
wire _in_d_valid_T_14 = _in_d_valid_T_13 | _in_d_valid_T_12; // @[Mux.scala:30:73]
wire _in_d_valid_WIRE_1 = _in_d_valid_T_14; // @[Mux.scala:30:73]
assign _in_d_valid_T_15 = idle_3 ? _in_d_valid_T_9 : _in_d_valid_WIRE_1; // @[Mux.scala:30:73]
assign in_d_1_valid = _in_d_valid_T_15; // @[CacheCork.scala:131:24]
wire [2:0] _in_d_bits_WIRE_21; // @[Mux.scala:30:73]
assign in_d_1_bits_opcode = _in_d_bits_WIRE_11_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_WIRE_20; // @[Mux.scala:30:73]
assign in_d_1_bits_param = _in_d_bits_WIRE_11_param; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_WIRE_19; // @[Mux.scala:30:73]
assign in_d_1_bits_size = _in_d_bits_WIRE_11_size; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_WIRE_18; // @[Mux.scala:30:73]
assign in_d_1_bits_source = _in_d_bits_WIRE_11_source; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_WIRE_17; // @[Mux.scala:30:73]
assign in_d_1_bits_sink = _in_d_bits_WIRE_11_sink; // @[Mux.scala:30:73]
wire _in_d_bits_WIRE_16; // @[Mux.scala:30:73]
assign in_d_1_bits_denied = _in_d_bits_WIRE_11_denied; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_WIRE_13; // @[Mux.scala:30:73]
assign in_d_1_bits_data = _in_d_bits_WIRE_11_data; // @[Mux.scala:30:73]
wire _in_d_bits_WIRE_12; // @[Mux.scala:30:73]
assign in_d_1_bits_corrupt = _in_d_bits_WIRE_11_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_40 = muxState_3_0 & d_d_1_bits_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_41 = muxState_3_1 & _q_2_io_deq_bits_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_42 = muxState_3_2 & _q_3_io_deq_bits_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_43 = _in_d_bits_T_40 | _in_d_bits_T_41; // @[Mux.scala:30:73]
wire _in_d_bits_T_44 = _in_d_bits_T_43 | _in_d_bits_T_42; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_12 = _in_d_bits_T_44; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_11_corrupt = _in_d_bits_WIRE_12; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_45 = muxState_3_0 ? d_d_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_46 = muxState_3_1 ? _q_2_io_deq_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_47 = muxState_3_2 ? _q_3_io_deq_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_48 = _in_d_bits_T_45 | _in_d_bits_T_46; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_49 = _in_d_bits_T_48 | _in_d_bits_T_47; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_13 = _in_d_bits_T_49; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_11_data = _in_d_bits_WIRE_13; // @[Mux.scala:30:73]
wire _in_d_bits_T_50 = muxState_3_0 & d_d_1_bits_denied; // @[Mux.scala:30:73]
wire _in_d_bits_T_51 = muxState_3_1 & _q_2_io_deq_bits_denied; // @[Mux.scala:30:73]
wire _in_d_bits_T_52 = muxState_3_2 & _q_3_io_deq_bits_denied; // @[Mux.scala:30:73]
wire _in_d_bits_T_53 = _in_d_bits_T_50 | _in_d_bits_T_51; // @[Mux.scala:30:73]
wire _in_d_bits_T_54 = _in_d_bits_T_53 | _in_d_bits_T_52; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_16 = _in_d_bits_T_54; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_11_denied = _in_d_bits_WIRE_16; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_55 = muxState_3_0 ? d_d_1_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_56 = muxState_3_1 ? _q_2_io_deq_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_57 = muxState_3_2 ? _q_3_io_deq_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_58 = _in_d_bits_T_55 | _in_d_bits_T_56; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_59 = _in_d_bits_T_58 | _in_d_bits_T_57; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_17 = _in_d_bits_T_59; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_11_sink = _in_d_bits_WIRE_17; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_60 = muxState_3_0 ? d_d_1_bits_source : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_61 = muxState_3_1 ? _q_2_io_deq_bits_source : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_62 = muxState_3_2 ? _q_3_io_deq_bits_source : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_63 = _in_d_bits_T_60 | _in_d_bits_T_61; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_64 = _in_d_bits_T_63 | _in_d_bits_T_62; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_18 = _in_d_bits_T_64; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_11_source = _in_d_bits_WIRE_18; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_65 = muxState_3_0 ? d_d_1_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_66 = muxState_3_1 ? _q_2_io_deq_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_67 = muxState_3_2 ? _q_3_io_deq_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_68 = _in_d_bits_T_65 | _in_d_bits_T_66; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_69 = _in_d_bits_T_68 | _in_d_bits_T_67; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_19 = _in_d_bits_T_69; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_11_size = _in_d_bits_WIRE_19; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_70 = muxState_3_0 ? d_d_1_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_71 = muxState_3_1 ? _q_2_io_deq_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_72 = muxState_3_2 ? _q_3_io_deq_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_73 = _in_d_bits_T_70 | _in_d_bits_T_71; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_74 = _in_d_bits_T_73 | _in_d_bits_T_72; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_20 = _in_d_bits_T_74; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_11_param = _in_d_bits_WIRE_20; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_75 = muxState_3_0 ? d_d_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_76 = muxState_3_1 ? _q_2_io_deq_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_77 = muxState_3_2 ? _q_3_io_deq_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_78 = _in_d_bits_T_75 | _in_d_bits_T_76; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_79 = _in_d_bits_T_78 | _in_d_bits_T_77; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_21 = _in_d_bits_T_79; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_11_opcode = _in_d_bits_WIRE_21; // @[Mux.scala:30:73]
wire _a_a_ready_T_2; // @[Arbiter.scala:94:31]
wire _a_a_valid_T_5; // @[CacheCork.scala:81:33]
wire [2:0] a_a_2_bits_opcode; // @[CacheCork.scala:74:23]
wire [2:0] a_a_2_bits_param; // @[CacheCork.scala:74:23]
wire [4:0] a_a_2_bits_source; // @[CacheCork.scala:74:23]
wire a_a_2_ready; // @[CacheCork.scala:74:23]
wire a_a_2_valid; // @[CacheCork.scala:74:23]
wire _a_d_valid_T_2; // @[CacheCork.scala:93:33]
wire [2:0] a_d_2_bits_size; // @[CacheCork.scala:75:23]
wire [3:0] a_d_2_bits_source; // @[CacheCork.scala:75:23]
wire a_d_2_ready; // @[CacheCork.scala:75:23]
wire a_d_2_valid; // @[CacheCork.scala:75:23]
wire _isPut_T_4 = nodeIn_2_a_bits_opcode == 3'h0; // @[CacheCork.scala:76:38]
wire _isPut_T_5 = nodeIn_2_a_bits_opcode == 3'h1; // @[CacheCork.scala:76:74]
wire isPut_2 = _isPut_T_4 | _isPut_T_5; // @[CacheCork.scala:76:{38,54,74}]
wire _a_a_bits_source_T_11 = isPut_2; // @[CacheCork.scala:76:54, :83:55]
wire _toD_T_8 = nodeIn_2_a_bits_opcode == 3'h6; // @[CacheCork.scala:77:37]
wire _toD_T_9 = nodeIn_2_a_bits_param == 3'h2; // @[CacheCork.scala:77:73]
wire _toD_T_10 = _toD_T_8 & _toD_T_9; // @[CacheCork.scala:77:{37,54,73}]
wire _toD_T_11 = &nodeIn_2_a_bits_opcode; // @[CacheCork.scala:78:37]
wire toD_2 = _toD_T_10 | _toD_T_11; // @[CacheCork.scala:77:{54,97}, :78:37]
assign _nodeIn_a_ready_T_2 = toD_2 ? a_d_2_ready : a_a_2_ready; // @[CacheCork.scala:74:23, :75:23, :77:97, :79:26]
assign nodeIn_2_a_ready = _nodeIn_a_ready_T_2; // @[CacheCork.scala:79:26]
wire _a_a_valid_T_4 = ~toD_2; // @[CacheCork.scala:77:97, :81:36]
assign _a_a_valid_T_5 = nodeIn_2_a_valid & _a_a_valid_T_4; // @[CacheCork.scala:81:{33,36}]
assign a_a_2_valid = _a_a_valid_T_5; // @[CacheCork.scala:74:23, :81:33]
wire [4:0] _GEN_3 = {nodeIn_2_a_bits_source, 1'h0}; // @[CacheCork.scala:83:45]
wire [4:0] _a_a_bits_source_T_10; // @[CacheCork.scala:83:45]
assign _a_a_bits_source_T_10 = _GEN_3; // @[CacheCork.scala:83:45]
wire [4:0] _a_a_bits_source_T_13; // @[CacheCork.scala:89:47]
assign _a_a_bits_source_T_13 = _GEN_3; // @[CacheCork.scala:83:45, :89:47]
wire [4:0] _a_a_bits_source_T_12 = {_a_a_bits_source_T_10[4:1], _a_a_bits_source_T_10[0] | _a_a_bits_source_T_11}; // @[CacheCork.scala:83:{45,50,55}]
wire _T_134 = _toD_T_8 | (&nodeIn_2_a_bits_opcode); // @[CacheCork.scala:77:37, :78:37, :86:49]
assign a_a_2_bits_opcode = _T_134 ? 3'h4 : nodeIn_2_a_bits_opcode; // @[CacheCork.scala:74:23, :82:18, :86:{49,86}, :87:27]
assign a_a_2_bits_param = _T_134 ? 3'h0 : nodeIn_2_a_bits_param; // @[CacheCork.scala:74:23, :82:18, :86:{49,86}, :88:27]
wire [4:0] _a_a_bits_source_T_14 = {_a_a_bits_source_T_13[4:1], 1'h1}; // @[CacheCork.scala:89:{47,52}]
assign a_a_2_bits_source = _T_134 ? _a_a_bits_source_T_14 : _a_a_bits_source_T_12; // @[CacheCork.scala:74:23, :83:{25,50}, :86:{49,86}, :89:{27,52}]
assign _a_d_valid_T_2 = nodeIn_2_a_valid & toD_2; // @[CacheCork.scala:77:97, :93:33]
assign a_d_2_valid = _a_d_valid_T_2; // @[CacheCork.scala:75:23, :93:33]
assign a_d_2_bits_size = a_d_bits_d_2_size; // @[Edges.scala:645:17]
assign a_d_2_bits_source = a_d_bits_d_2_source; // @[Edges.scala:645:17]
wire _c_a_ready_T_2; // @[Arbiter.scala:94:31]
wire _c_a_valid_T_5; // @[CacheCork.scala:102:33]
wire [4:0] c_a_bits_a_2_source; // @[Edges.scala:480:17]
wire [7:0] c_a_bits_a_2_mask; // @[Edges.scala:480:17]
wire [2:0] c_a_2_bits_size; // @[CacheCork.scala:101:23]
wire [4:0] c_a_2_bits_source; // @[CacheCork.scala:101:23]
wire [31:0] c_a_2_bits_address; // @[CacheCork.scala:101:23]
wire [7:0] c_a_2_bits_mask; // @[CacheCork.scala:101:23]
wire [63:0] c_a_2_bits_data; // @[CacheCork.scala:101:23]
wire c_a_2_bits_corrupt; // @[CacheCork.scala:101:23]
wire c_a_2_ready; // @[CacheCork.scala:101:23]
wire c_a_2_valid; // @[CacheCork.scala:101:23]
wire _c_a_valid_T_4 = &nodeIn_2_c_bits_opcode; // @[CacheCork.scala:102:53]
assign _c_a_valid_T_5 = nodeIn_2_c_valid & _c_a_valid_T_4; // @[CacheCork.scala:102:{33,53}]
assign c_a_2_valid = _c_a_valid_T_5; // @[CacheCork.scala:101:23, :102:33]
wire [4:0] _c_a_bits_T_2 = {nodeIn_2_c_bits_source, 1'h0}; // @[CacheCork.scala:104:41]
assign c_a_bits_a_2_source = _c_a_bits_T_2; // @[Edges.scala:480:17]
wire _c_a_bits_legal_T_21 = nodeIn_2_c_bits_size != 3'h7; // @[Parameters.scala:92:38]
wire _c_a_bits_legal_T_22 = _c_a_bits_legal_T_21; // @[Parameters.scala:92:{33,38}]
wire _c_a_bits_legal_T_23 = _c_a_bits_legal_T_22; // @[Parameters.scala:684:29]
wire _c_a_bits_legal_T_29 = _c_a_bits_legal_T_23; // @[Parameters.scala:684:{29,54}]
wire [32:0] _c_a_bits_legal_T_25 = {1'h0, _c_a_bits_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire c_a_bits_legal_2 = _c_a_bits_legal_T_29; // @[Parameters.scala:684:54, :686:26]
assign c_a_2_bits_size = c_a_bits_a_2_size; // @[Edges.scala:480:17]
assign c_a_2_bits_source = c_a_bits_a_2_source; // @[Edges.scala:480:17]
assign c_a_2_bits_address = c_a_bits_a_2_address; // @[Edges.scala:480:17]
wire [7:0] _c_a_bits_a_mask_T_2; // @[Misc.scala:222:10]
assign c_a_2_bits_mask = c_a_bits_a_2_mask; // @[Edges.scala:480:17]
assign c_a_2_bits_data = c_a_bits_a_2_data; // @[Edges.scala:480:17]
assign c_a_2_bits_corrupt = c_a_bits_a_2_corrupt; // @[Edges.scala:480:17]
wire [1:0] c_a_bits_a_mask_sizeOH_shiftAmount_2 = _c_a_bits_a_mask_sizeOH_T_6[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _c_a_bits_a_mask_sizeOH_T_7 = 4'h1 << c_a_bits_a_mask_sizeOH_shiftAmount_2; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _c_a_bits_a_mask_sizeOH_T_8 = _c_a_bits_a_mask_sizeOH_T_7[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] c_a_bits_a_mask_sizeOH_2 = {_c_a_bits_a_mask_sizeOH_T_8[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire c_a_bits_a_mask_sub_sub_sub_0_1_2 = nodeIn_2_c_bits_size > 3'h2; // @[Misc.scala:206:21]
wire c_a_bits_a_mask_sub_sub_size_2 = c_a_bits_a_mask_sizeOH_2[2]; // @[Misc.scala:202:81, :209:26]
wire c_a_bits_a_mask_sub_sub_bit_2 = nodeIn_2_c_bits_address[2]; // @[Misc.scala:210:26]
wire c_a_bits_a_mask_sub_sub_1_2_2 = c_a_bits_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27]
wire c_a_bits_a_mask_sub_sub_nbit_2 = ~c_a_bits_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20]
wire c_a_bits_a_mask_sub_sub_0_2_2 = c_a_bits_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_sub_sub_acc_T_4 = c_a_bits_a_mask_sub_sub_size_2 & c_a_bits_a_mask_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_sub_0_1_2 = c_a_bits_a_mask_sub_sub_sub_0_1_2 | _c_a_bits_a_mask_sub_sub_acc_T_4; // @[Misc.scala:206:21, :215:{29,38}]
wire _c_a_bits_a_mask_sub_sub_acc_T_5 = c_a_bits_a_mask_sub_sub_size_2 & c_a_bits_a_mask_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_sub_1_1_2 = c_a_bits_a_mask_sub_sub_sub_0_1_2 | _c_a_bits_a_mask_sub_sub_acc_T_5; // @[Misc.scala:206:21, :215:{29,38}]
wire c_a_bits_a_mask_sub_size_2 = c_a_bits_a_mask_sizeOH_2[1]; // @[Misc.scala:202:81, :209:26]
wire c_a_bits_a_mask_sub_bit_2 = nodeIn_2_c_bits_address[1]; // @[Misc.scala:210:26]
wire c_a_bits_a_mask_sub_nbit_2 = ~c_a_bits_a_mask_sub_bit_2; // @[Misc.scala:210:26, :211:20]
wire c_a_bits_a_mask_sub_0_2_2 = c_a_bits_a_mask_sub_sub_0_2_2 & c_a_bits_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_8 = c_a_bits_a_mask_sub_size_2 & c_a_bits_a_mask_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_0_1_2 = c_a_bits_a_mask_sub_sub_0_1_2 | _c_a_bits_a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_sub_1_2_2 = c_a_bits_a_mask_sub_sub_0_2_2 & c_a_bits_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_9 = c_a_bits_a_mask_sub_size_2 & c_a_bits_a_mask_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_1_1_2 = c_a_bits_a_mask_sub_sub_0_1_2 | _c_a_bits_a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_sub_2_2_2 = c_a_bits_a_mask_sub_sub_1_2_2 & c_a_bits_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_10 = c_a_bits_a_mask_sub_size_2 & c_a_bits_a_mask_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_2_1_2 = c_a_bits_a_mask_sub_sub_1_1_2 | _c_a_bits_a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_sub_3_2_2 = c_a_bits_a_mask_sub_sub_1_2_2 & c_a_bits_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_11 = c_a_bits_a_mask_sub_size_2 & c_a_bits_a_mask_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_3_1_2 = c_a_bits_a_mask_sub_sub_1_1_2 | _c_a_bits_a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_size_2 = c_a_bits_a_mask_sizeOH_2[0]; // @[Misc.scala:202:81, :209:26]
wire c_a_bits_a_mask_bit_2 = nodeIn_2_c_bits_address[0]; // @[Misc.scala:210:26]
wire c_a_bits_a_mask_nbit_2 = ~c_a_bits_a_mask_bit_2; // @[Misc.scala:210:26, :211:20]
wire c_a_bits_a_mask_eq_16 = c_a_bits_a_mask_sub_0_2_2 & c_a_bits_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_16 = c_a_bits_a_mask_size_2 & c_a_bits_a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_16 = c_a_bits_a_mask_sub_0_1_2 | _c_a_bits_a_mask_acc_T_16; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_17 = c_a_bits_a_mask_sub_0_2_2 & c_a_bits_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_17 = c_a_bits_a_mask_size_2 & c_a_bits_a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_17 = c_a_bits_a_mask_sub_0_1_2 | _c_a_bits_a_mask_acc_T_17; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_18 = c_a_bits_a_mask_sub_1_2_2 & c_a_bits_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_18 = c_a_bits_a_mask_size_2 & c_a_bits_a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_18 = c_a_bits_a_mask_sub_1_1_2 | _c_a_bits_a_mask_acc_T_18; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_19 = c_a_bits_a_mask_sub_1_2_2 & c_a_bits_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_19 = c_a_bits_a_mask_size_2 & c_a_bits_a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_19 = c_a_bits_a_mask_sub_1_1_2 | _c_a_bits_a_mask_acc_T_19; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_20 = c_a_bits_a_mask_sub_2_2_2 & c_a_bits_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_20 = c_a_bits_a_mask_size_2 & c_a_bits_a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_20 = c_a_bits_a_mask_sub_2_1_2 | _c_a_bits_a_mask_acc_T_20; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_21 = c_a_bits_a_mask_sub_2_2_2 & c_a_bits_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_21 = c_a_bits_a_mask_size_2 & c_a_bits_a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_21 = c_a_bits_a_mask_sub_2_1_2 | _c_a_bits_a_mask_acc_T_21; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_22 = c_a_bits_a_mask_sub_3_2_2 & c_a_bits_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_22 = c_a_bits_a_mask_size_2 & c_a_bits_a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_22 = c_a_bits_a_mask_sub_3_1_2 | _c_a_bits_a_mask_acc_T_22; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_23 = c_a_bits_a_mask_sub_3_2_2 & c_a_bits_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_23 = c_a_bits_a_mask_size_2 & c_a_bits_a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_23 = c_a_bits_a_mask_sub_3_1_2 | _c_a_bits_a_mask_acc_T_23; // @[Misc.scala:215:{29,38}]
wire [1:0] c_a_bits_a_mask_lo_lo_2 = {c_a_bits_a_mask_acc_17, c_a_bits_a_mask_acc_16}; // @[Misc.scala:215:29, :222:10]
wire [1:0] c_a_bits_a_mask_lo_hi_2 = {c_a_bits_a_mask_acc_19, c_a_bits_a_mask_acc_18}; // @[Misc.scala:215:29, :222:10]
wire [3:0] c_a_bits_a_mask_lo_2 = {c_a_bits_a_mask_lo_hi_2, c_a_bits_a_mask_lo_lo_2}; // @[Misc.scala:222:10]
wire [1:0] c_a_bits_a_mask_hi_lo_2 = {c_a_bits_a_mask_acc_21, c_a_bits_a_mask_acc_20}; // @[Misc.scala:215:29, :222:10]
wire [1:0] c_a_bits_a_mask_hi_hi_2 = {c_a_bits_a_mask_acc_23, c_a_bits_a_mask_acc_22}; // @[Misc.scala:215:29, :222:10]
wire [3:0] c_a_bits_a_mask_hi_2 = {c_a_bits_a_mask_hi_hi_2, c_a_bits_a_mask_hi_lo_2}; // @[Misc.scala:222:10]
assign _c_a_bits_a_mask_T_2 = {c_a_bits_a_mask_hi_2, c_a_bits_a_mask_lo_2}; // @[Misc.scala:222:10]
assign c_a_bits_a_2_mask = _c_a_bits_a_mask_T_2; // @[Misc.scala:222:10]
wire _c_d_valid_T_5; // @[CacheCork.scala:113:33]
wire [2:0] c_d_2_bits_size; // @[CacheCork.scala:112:23]
wire [3:0] c_d_2_bits_source; // @[CacheCork.scala:112:23]
wire c_d_2_ready; // @[CacheCork.scala:112:23]
wire c_d_2_valid; // @[CacheCork.scala:112:23]
wire _T_136 = nodeIn_2_c_bits_opcode == 3'h6; // @[CacheCork.scala:113:53]
wire _c_d_valid_T_4; // @[CacheCork.scala:113:53]
assign _c_d_valid_T_4 = _T_136; // @[CacheCork.scala:113:53]
wire _nodeIn_c_ready_T_4; // @[CacheCork.scala:117:44]
assign _nodeIn_c_ready_T_4 = _T_136; // @[CacheCork.scala:113:53, :117:44]
assign _c_d_valid_T_5 = nodeIn_2_c_valid & _c_d_valid_T_4; // @[CacheCork.scala:113:{33,53}]
assign c_d_2_valid = _c_d_valid_T_5; // @[CacheCork.scala:112:23, :113:33]
assign c_d_2_bits_size = c_d_bits_d_2_size; // @[Edges.scala:677:17]
assign c_d_2_bits_source = c_d_bits_d_2_source; // @[Edges.scala:677:17]
assign _nodeIn_c_ready_T_5 = _nodeIn_c_ready_T_4 ? c_d_2_ready : c_a_2_ready; // @[CacheCork.scala:101:23, :112:23, :117:{26,44}]
assign nodeIn_2_c_ready = _nodeIn_c_ready_T_5; // @[CacheCork.scala:117:26]
wire _in_d_ready_T_14; // @[CacheCork.scala:136:34]
wire _in_d_valid_T_23; // @[Arbiter.scala:96:24]
wire [2:0] _in_d_bits_WIRE_22_opcode; // @[Mux.scala:30:73]
assign nodeIn_2_d_bits_opcode = in_d_2_bits_opcode; // @[CacheCork.scala:131:24]
wire [1:0] _in_d_bits_WIRE_22_param; // @[Mux.scala:30:73]
assign nodeIn_2_d_bits_param = in_d_2_bits_param; // @[CacheCork.scala:131:24]
wire [2:0] _in_d_bits_WIRE_22_size; // @[Mux.scala:30:73]
assign nodeIn_2_d_bits_size = in_d_2_bits_size; // @[CacheCork.scala:131:24]
wire [3:0] _in_d_bits_WIRE_22_source; // @[Mux.scala:30:73]
assign nodeIn_2_d_bits_source = in_d_2_bits_source; // @[CacheCork.scala:131:24]
wire [2:0] _in_d_bits_WIRE_22_sink; // @[Mux.scala:30:73]
wire _in_d_bits_WIRE_22_denied; // @[Mux.scala:30:73]
assign nodeIn_2_d_bits_denied = in_d_2_bits_denied; // @[CacheCork.scala:131:24]
wire [63:0] _in_d_bits_WIRE_22_data; // @[Mux.scala:30:73]
assign nodeIn_2_d_bits_data = in_d_2_bits_data; // @[CacheCork.scala:131:24]
wire _in_d_bits_WIRE_22_corrupt; // @[Mux.scala:30:73]
assign nodeIn_2_d_bits_corrupt = in_d_2_bits_corrupt; // @[CacheCork.scala:131:24]
wire [2:0] in_d_2_bits_sink; // @[CacheCork.scala:131:24]
wire in_d_2_ready; // @[CacheCork.scala:131:24]
wire in_d_2_valid; // @[CacheCork.scala:131:24]
wire _GEN_4 = in_d_2_ready & in_d_2_valid; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _GEN_4; // @[Decoupled.scala:51:35]
wire _beatsLeft_T_20; // @[Decoupled.scala:51:35]
assign _beatsLeft_T_20 = _GEN_4; // @[Decoupled.scala:51:35]
wire [12:0] _d_first_beats1_decode_T_6 = 13'h3F << in_d_2_bits_size; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata_2 = in_d_2_bits_opcode[0]; // @[Edges.scala:106:36]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _d_grant_T_4 = in_d_2_bits_opcode == 3'h5; // @[CacheCork.scala:131:24, :133:40]
wire _d_grant_T_5 = in_d_2_bits_opcode == 3'h4; // @[CacheCork.scala:131:24, :133:74]
wire d_grant_2 = _d_grant_T_4 | _d_grant_T_5; // @[CacheCork.scala:133:{40,54,74}]
wire _pool_io_alloc_ready_T_6 = nodeIn_2_d_ready & nodeIn_2_d_valid; // @[Decoupled.scala:51:35]
wire _pool_io_alloc_ready_T_7 = _pool_io_alloc_ready_T_6 & d_first_2; // @[Decoupled.scala:51:35]
wire _pool_io_alloc_ready_T_8 = _pool_io_alloc_ready_T_7 & d_grant_2; // @[CacheCork.scala:133:54, :134:{42,53}]
wire _nodeIn_d_valid_T_10 = ~d_first_2; // @[Edges.scala:231:25]
wire _nodeIn_d_valid_T_11 = _pool_2_io_alloc_valid | _nodeIn_d_valid_T_10; // @[CacheCork.scala:127:26, :135:{58,61}]
wire _nodeIn_d_valid_T_12 = ~d_grant_2; // @[CacheCork.scala:133:54, :135:73]
wire _nodeIn_d_valid_T_13 = _nodeIn_d_valid_T_11 | _nodeIn_d_valid_T_12; // @[CacheCork.scala:135:{58,70,73}]
assign _nodeIn_d_valid_T_14 = in_d_2_valid & _nodeIn_d_valid_T_13; // @[CacheCork.scala:131:24, :135:{34,70}]
assign nodeIn_2_d_valid = _nodeIn_d_valid_T_14; // @[CacheCork.scala:135:34]
wire _in_d_ready_T_10 = ~d_first_2; // @[Edges.scala:231:25]
wire _in_d_ready_T_11 = _pool_2_io_alloc_valid | _in_d_ready_T_10; // @[CacheCork.scala:127:26, :136:{58,61}]
wire _in_d_ready_T_12 = ~d_grant_2; // @[CacheCork.scala:133:54, :135:73, :136:73]
wire _in_d_ready_T_13 = _in_d_ready_T_11 | _in_d_ready_T_12; // @[CacheCork.scala:136:{58,70,73}]
assign _in_d_ready_T_14 = nodeIn_2_d_ready & _in_d_ready_T_13; // @[CacheCork.scala:136:{34,70}]
assign in_d_2_ready = _in_d_ready_T_14; // @[CacheCork.scala:131:24, :136:34]
reg [2:0] nodeIn_d_bits_sink_r_2; // @[package.scala:88:63]
assign _nodeIn_d_bits_sink_T_2 = d_first_2 ? _pool_2_io_alloc_bits : nodeIn_d_bits_sink_r_2; // @[package.scala:88:{42,63}]
assign nodeIn_2_d_bits_sink = _nodeIn_d_bits_sink_T_2; // @[package.scala:88:42]
wire _d_d_ready_T_2; // @[Arbiter.scala:94:31]
assign x1_nodeOut_1_d_ready = d_d_2_ready; // @[CacheCork.scala:141:23]
wire [3:0] _d_d_bits_source_T_2; // @[CacheCork.scala:143:46]
wire [2:0] d_d_2_bits_opcode; // @[CacheCork.scala:141:23]
wire [1:0] d_d_2_bits_param; // @[CacheCork.scala:141:23]
wire [3:0] d_d_2_bits_source; // @[CacheCork.scala:141:23]
wire [2:0] d_d_2_bits_sink; // @[CacheCork.scala:141:23]
assign d_d_2_bits_sink = {2'h0, x1_nodeOut_1_d_bits_sink}; // @[CacheCork.scala:141:23, :142:13]
assign _d_d_bits_source_T_2 = x1_nodeOut_1_d_bits_source[4:1]; // @[CacheCork.scala:143:46]
assign d_d_2_bits_source = _d_d_bits_source_T_2; // @[CacheCork.scala:141:23, :143:46]
wire [32:0] _aWOk_T_11 = {1'h0, _aWOk_T_10}; // @[Parameters.scala:137:{31,41}]
wire _bypass_T_5 = nodeIn_2_a_bits_source == d_d_2_bits_source; // @[CacheCork.scala:141:23, :150:91]
reg dWHeld_r_2; // @[package.scala:88:63]
wire dWHeld_2 = d_first_2 ? _dWHeld_T_2 : dWHeld_r_2; // @[package.scala:88:{42,63}]
wire _T_150 = x1_nodeOut_1_d_bits_opcode == 3'h1 & x1_nodeOut_1_d_bits_source[0]; // @[CacheCork.scala:162:{33,51,71}]
wire [1:0] _d_d_bits_param_T_2 = {1'h0, ~dWHeld_2}; // @[package.scala:88:42]
assign d_d_2_bits_param = _T_150 ? _d_d_bits_param_T_2 : x1_nodeOut_1_d_bits_param; // @[CacheCork.scala:141:23, :142:13, :162:{51,76}, :164:{26,32}]
assign d_d_2_bits_opcode = x1_nodeOut_1_d_bits_opcode == 3'h0 & ~(x1_nodeOut_1_d_bits_source[0]) ? 3'h6 : _T_150 ? 3'h5 : x1_nodeOut_1_d_bits_opcode; // @[CacheCork.scala:141:23, :142:13, :162:{51,71,76}, :163:27, :166:{33,47,50,73}, :167:27]
wire [12:0] _decode_T_18 = 13'h3F << c_a_2_bits_size; // @[package.scala:243:71]
wire [5:0] _decode_T_19 = _decode_T_18[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _decode_T_20 = ~_decode_T_19; // @[package.scala:243:{46,76}]
wire [2:0] decode_6 = _decode_T_20[5:3]; // @[package.scala:243:46]
wire [12:0] _decode_T_21 = 13'h3F << a_a_2_bits_size; // @[package.scala:243:71]
wire [5:0] _decode_T_22 = _decode_T_21[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _decode_T_23 = ~_decode_T_22; // @[package.scala:243:{46,76}]
wire [2:0] decode_7 = _decode_T_23[5:3]; // @[package.scala:243:46]
wire _opdata_T_5 = a_a_2_bits_opcode[2]; // @[Edges.scala:92:37]
wire opdata_7 = ~_opdata_T_5; // @[Edges.scala:92:{28,37}]
reg [2:0] beatsLeft_4; // @[Arbiter.scala:60:30]
wire idle_4 = beatsLeft_4 == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_4 = idle_4 & x1_nodeOut_1_a_ready; // @[Arbiter.scala:61:28, :62:24]
wire [1:0] _readys_T_48 = {a_a_2_valid, c_a_2_valid}; // @[CacheCork.scala:74:23, :101:23]
wire [2:0] _readys_T_49 = {_readys_T_48, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_T_50 = _readys_T_49[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_T_51 = _readys_T_48 | _readys_T_50; // @[package.scala:253:{43,53}]
wire [1:0] _readys_T_52 = _readys_T_51; // @[package.scala:253:43, :254:17]
wire [2:0] _readys_T_53 = {_readys_T_52, 1'h0}; // @[package.scala:254:17]
wire [1:0] _readys_T_54 = _readys_T_53[1:0]; // @[Arbiter.scala:16:{78,83}]
wire [1:0] _readys_T_55 = ~_readys_T_54; // @[Arbiter.scala:16:{61,83}]
wire _readys_T_56 = _readys_T_55[0]; // @[Arbiter.scala:16:61, :68:76]
wire readys_4_0 = _readys_T_56; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_57 = _readys_T_55[1]; // @[Arbiter.scala:16:61, :68:76]
wire readys_4_1 = _readys_T_57; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_10 = readys_4_0 & c_a_2_valid; // @[CacheCork.scala:101:23]
wire winner_4_0 = _winner_T_10; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_11 = readys_4_1 & a_a_2_valid; // @[CacheCork.scala:74:23]
wire winner_4_1 = _winner_T_11; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_4 = winner_4_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_4 = prefixOR_1_4 | winner_4_1; // @[Arbiter.scala:71:27, :76:48]
wire _nodeOut_a_valid_T_10 = c_a_2_valid | a_a_2_valid; // @[CacheCork.scala:74:23, :101:23]
wire [2:0] maskedBeats_0_4 = winner_4_0 ? decode_6 : 3'h0; // @[Edges.scala:220:59, :221:14]
wire [2:0] maskedBeats_1_4 = winner_4_1 & opdata_7 ? decode_7 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [2:0] initBeats_4 = maskedBeats_0_4 | maskedBeats_1_4; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_16 = x1_nodeOut_1_a_ready & x1_nodeOut_1_a_valid; // @[Decoupled.scala:51:35]
wire [3:0] _beatsLeft_T_17 = {1'h0, beatsLeft_4} - {3'h0, _beatsLeft_T_16}; // @[Decoupled.scala:51:35]
wire [2:0] _beatsLeft_T_18 = _beatsLeft_T_17[2:0]; // @[Arbiter.scala:85:52]
wire [2:0] _beatsLeft_T_19 = latch_4 ? initBeats_4 : _beatsLeft_T_18; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_4_0; // @[Arbiter.scala:88:26]
reg state_4_1; // @[Arbiter.scala:88:26]
wire muxState_4_0 = idle_4 ? winner_4_0 : state_4_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_4_1 = idle_4 ? winner_4_1 : state_4_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_4_0 = idle_4 ? readys_4_0 : state_4_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_4_1 = idle_4 ? readys_4_1 : state_4_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _c_a_ready_T_2 = x1_nodeOut_1_a_ready & allowed_4_0; // @[Arbiter.scala:92:24, :94:31]
assign c_a_2_ready = _c_a_ready_T_2; // @[CacheCork.scala:101:23]
assign _a_a_ready_T_2 = x1_nodeOut_1_a_ready & allowed_4_1; // @[Arbiter.scala:92:24, :94:31]
assign a_a_2_ready = _a_a_ready_T_2; // @[CacheCork.scala:74:23]
wire _nodeOut_a_valid_T_11 = state_4_0 & c_a_2_valid; // @[Mux.scala:30:73]
wire _nodeOut_a_valid_T_12 = state_4_1 & a_a_2_valid; // @[Mux.scala:30:73]
wire _nodeOut_a_valid_T_13 = _nodeOut_a_valid_T_11 | _nodeOut_a_valid_T_12; // @[Mux.scala:30:73]
wire _nodeOut_a_valid_WIRE_2 = _nodeOut_a_valid_T_13; // @[Mux.scala:30:73]
assign _nodeOut_a_valid_T_14 = idle_4 ? _nodeOut_a_valid_T_10 : _nodeOut_a_valid_WIRE_2; // @[Mux.scala:30:73]
assign x1_nodeOut_1_a_valid = _nodeOut_a_valid_T_14; // @[Arbiter.scala:96:24]
wire [2:0] _nodeOut_a_bits_WIRE_32; // @[Mux.scala:30:73]
assign x1_nodeOut_1_a_bits_opcode = _nodeOut_a_bits_WIRE_22_opcode; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_WIRE_31; // @[Mux.scala:30:73]
assign x1_nodeOut_1_a_bits_param = _nodeOut_a_bits_WIRE_22_param; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_WIRE_30; // @[Mux.scala:30:73]
assign x1_nodeOut_1_a_bits_size = _nodeOut_a_bits_WIRE_22_size; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_WIRE_29; // @[Mux.scala:30:73]
assign x1_nodeOut_1_a_bits_source = _nodeOut_a_bits_WIRE_22_source; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_WIRE_28; // @[Mux.scala:30:73]
assign x1_nodeOut_1_a_bits_address = _nodeOut_a_bits_WIRE_22_address; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_WIRE_25; // @[Mux.scala:30:73]
assign x1_nodeOut_1_a_bits_mask = _nodeOut_a_bits_WIRE_22_mask; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_WIRE_24; // @[Mux.scala:30:73]
assign x1_nodeOut_1_a_bits_data = _nodeOut_a_bits_WIRE_22_data; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_WIRE_23; // @[Mux.scala:30:73]
assign x1_nodeOut_1_a_bits_corrupt = _nodeOut_a_bits_WIRE_22_corrupt; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T_48 = muxState_4_0 & c_a_2_bits_corrupt; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T_49 = muxState_4_1 & a_a_2_bits_corrupt; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T_50 = _nodeOut_a_bits_T_48 | _nodeOut_a_bits_T_49; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_23 = _nodeOut_a_bits_T_50; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_22_corrupt = _nodeOut_a_bits_WIRE_23; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_T_51 = muxState_4_0 ? c_a_2_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_T_52 = muxState_4_1 ? a_a_2_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_T_53 = _nodeOut_a_bits_T_51 | _nodeOut_a_bits_T_52; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_24 = _nodeOut_a_bits_T_53; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_22_data = _nodeOut_a_bits_WIRE_24; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_T_54 = muxState_4_0 ? c_a_2_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_T_55 = muxState_4_1 ? a_a_2_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_T_56 = _nodeOut_a_bits_T_54 | _nodeOut_a_bits_T_55; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_25 = _nodeOut_a_bits_T_56; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_22_mask = _nodeOut_a_bits_WIRE_25; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_T_57 = muxState_4_0 ? c_a_2_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_T_58 = muxState_4_1 ? a_a_2_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_T_59 = _nodeOut_a_bits_T_57 | _nodeOut_a_bits_T_58; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_28 = _nodeOut_a_bits_T_59; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_22_address = _nodeOut_a_bits_WIRE_28; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_T_60 = muxState_4_0 ? c_a_2_bits_source : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_T_61 = muxState_4_1 ? a_a_2_bits_source : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_T_62 = _nodeOut_a_bits_T_60 | _nodeOut_a_bits_T_61; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_29 = _nodeOut_a_bits_T_62; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_22_source = _nodeOut_a_bits_WIRE_29; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_63 = muxState_4_0 ? c_a_2_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_64 = muxState_4_1 ? a_a_2_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_65 = _nodeOut_a_bits_T_63 | _nodeOut_a_bits_T_64; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_30 = _nodeOut_a_bits_T_65; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_22_size = _nodeOut_a_bits_WIRE_30; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_67 = muxState_4_1 ? a_a_2_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_68 = _nodeOut_a_bits_T_67; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_31 = _nodeOut_a_bits_T_68; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_22_param = _nodeOut_a_bits_WIRE_31; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_70 = muxState_4_1 ? a_a_2_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_71 = _nodeOut_a_bits_T_70; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_32 = _nodeOut_a_bits_T_71; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_22_opcode = _nodeOut_a_bits_WIRE_32; // @[Mux.scala:30:73]
wire [12:0] _decode_T_24 = 13'h3F << d_d_2_bits_size; // @[package.scala:243:71]
wire [5:0] _decode_T_25 = _decode_T_24[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _decode_T_26 = ~_decode_T_25; // @[package.scala:243:{46,76}]
wire [2:0] decode_8 = _decode_T_26[5:3]; // @[package.scala:243:46]
wire opdata_8 = d_d_2_bits_opcode[0]; // @[Edges.scala:106:36]
reg [2:0] beatsLeft_5; // @[Arbiter.scala:60:30]
wire idle_5 = beatsLeft_5 == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_5 = idle_5 & in_d_2_ready; // @[CacheCork.scala:131:24]
wire [1:0] readys_hi_2 = {_q_5_io_deq_valid, _q_4_io_deq_valid}; // @[Decoupled.scala:362:21]
wire [2:0] _readys_T_58 = {readys_hi_2, d_d_2_valid}; // @[CacheCork.scala:141:23]
wire [3:0] _readys_T_59 = {_readys_T_58, 1'h0}; // @[package.scala:253:48]
wire [2:0] _readys_T_60 = _readys_T_59[2:0]; // @[package.scala:253:{48,53}]
wire [2:0] _readys_T_61 = _readys_T_58 | _readys_T_60; // @[package.scala:253:{43,53}]
wire [4:0] _readys_T_62 = {_readys_T_61, 2'h0}; // @[package.scala:253:{43,48}]
wire [2:0] _readys_T_63 = _readys_T_62[2:0]; // @[package.scala:253:{48,53}]
wire [2:0] _readys_T_64 = _readys_T_61 | _readys_T_63; // @[package.scala:253:{43,53}]
wire [2:0] _readys_T_65 = _readys_T_64; // @[package.scala:253:43, :254:17]
wire [3:0] _readys_T_66 = {_readys_T_65, 1'h0}; // @[package.scala:254:17]
wire [2:0] _readys_T_67 = _readys_T_66[2:0]; // @[Arbiter.scala:16:{78,83}]
wire [2:0] _readys_T_68 = ~_readys_T_67; // @[Arbiter.scala:16:{61,83}]
wire _readys_T_69 = _readys_T_68[0]; // @[Arbiter.scala:16:61, :68:76]
wire readys_5_0 = _readys_T_69; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_70 = _readys_T_68[1]; // @[Arbiter.scala:16:61, :68:76]
wire readys_5_1 = _readys_T_70; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_71 = _readys_T_68[2]; // @[Arbiter.scala:16:61, :68:76]
wire readys_5_2 = _readys_T_71; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_12 = readys_5_0 & d_d_2_valid; // @[CacheCork.scala:141:23]
wire winner_5_0 = _winner_T_12; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_13 = readys_5_1 & _q_4_io_deq_valid; // @[Decoupled.scala:362:21]
wire winner_5_1 = _winner_T_13; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_14 = readys_5_2 & _q_5_io_deq_valid; // @[Decoupled.scala:362:21]
wire winner_5_2 = _winner_T_14; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_5 = winner_5_0; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_2_2 = prefixOR_1_5 | winner_5_1; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_5 = prefixOR_2_2 | winner_5_2; // @[Arbiter.scala:71:27, :76:48]
wire _in_d_valid_T_16 = d_d_2_valid | _q_4_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] maskedBeats_0_5 = winner_5_0 & opdata_8 ? decode_8 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire [2:0] _initBeats_T_2 = maskedBeats_0_5; // @[Arbiter.scala:82:69, :84:44]
wire [2:0] initBeats_5 = _initBeats_T_2; // @[Arbiter.scala:84:44]
wire [3:0] _beatsLeft_T_21 = {1'h0, beatsLeft_5} - {3'h0, _beatsLeft_T_20}; // @[Decoupled.scala:51:35]
wire [2:0] _beatsLeft_T_22 = _beatsLeft_T_21[2:0]; // @[Arbiter.scala:85:52]
wire [2:0] _beatsLeft_T_23 = latch_5 ? initBeats_5 : _beatsLeft_T_22; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_5_0; // @[Arbiter.scala:88:26]
reg state_5_1; // @[Arbiter.scala:88:26]
reg state_5_2; // @[Arbiter.scala:88:26]
wire muxState_5_0 = idle_5 ? winner_5_0 : state_5_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_5_1 = idle_5 ? winner_5_1 : state_5_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_5_2 = idle_5 ? winner_5_2 : state_5_2; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_5_0 = idle_5 ? readys_5_0 : state_5_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_5_1 = idle_5 ? readys_5_1 : state_5_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_5_2 = idle_5 ? readys_5_2 : state_5_2; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _d_d_ready_T_2 = in_d_2_ready & allowed_5_0; // @[CacheCork.scala:131:24]
assign d_d_2_ready = _d_d_ready_T_2; // @[CacheCork.scala:141:23]
wire _q_io_deq_ready_T_4 = in_d_2_ready & allowed_5_1; // @[CacheCork.scala:131:24]
wire _q_io_deq_ready_T_5 = in_d_2_ready & allowed_5_2; // @[CacheCork.scala:131:24]
wire _in_d_valid_T_17 = _in_d_valid_T_16 | _q_5_io_deq_valid; // @[Decoupled.scala:362:21]
wire _in_d_valid_T_18 = state_5_0 & d_d_2_valid; // @[Mux.scala:30:73]
wire _in_d_valid_T_19 = state_5_1 & _q_4_io_deq_valid; // @[Mux.scala:30:73]
wire _in_d_valid_T_20 = state_5_2 & _q_5_io_deq_valid; // @[Mux.scala:30:73]
wire _in_d_valid_T_21 = _in_d_valid_T_18 | _in_d_valid_T_19; // @[Mux.scala:30:73]
wire _in_d_valid_T_22 = _in_d_valid_T_21 | _in_d_valid_T_20; // @[Mux.scala:30:73]
wire _in_d_valid_WIRE_2 = _in_d_valid_T_22; // @[Mux.scala:30:73]
assign _in_d_valid_T_23 = idle_5 ? _in_d_valid_T_17 : _in_d_valid_WIRE_2; // @[Mux.scala:30:73]
assign in_d_2_valid = _in_d_valid_T_23; // @[CacheCork.scala:131:24]
wire [2:0] _in_d_bits_WIRE_32; // @[Mux.scala:30:73]
assign in_d_2_bits_opcode = _in_d_bits_WIRE_22_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_WIRE_31; // @[Mux.scala:30:73]
assign in_d_2_bits_param = _in_d_bits_WIRE_22_param; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_WIRE_30; // @[Mux.scala:30:73]
assign in_d_2_bits_size = _in_d_bits_WIRE_22_size; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_WIRE_29; // @[Mux.scala:30:73]
assign in_d_2_bits_source = _in_d_bits_WIRE_22_source; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_WIRE_28; // @[Mux.scala:30:73]
assign in_d_2_bits_sink = _in_d_bits_WIRE_22_sink; // @[Mux.scala:30:73]
wire _in_d_bits_WIRE_27; // @[Mux.scala:30:73]
assign in_d_2_bits_denied = _in_d_bits_WIRE_22_denied; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_WIRE_24; // @[Mux.scala:30:73]
assign in_d_2_bits_data = _in_d_bits_WIRE_22_data; // @[Mux.scala:30:73]
wire _in_d_bits_WIRE_23; // @[Mux.scala:30:73]
assign in_d_2_bits_corrupt = _in_d_bits_WIRE_22_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_80 = muxState_5_0 & d_d_2_bits_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_81 = muxState_5_1 & _q_4_io_deq_bits_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_82 = muxState_5_2 & _q_5_io_deq_bits_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_83 = _in_d_bits_T_80 | _in_d_bits_T_81; // @[Mux.scala:30:73]
wire _in_d_bits_T_84 = _in_d_bits_T_83 | _in_d_bits_T_82; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_23 = _in_d_bits_T_84; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_22_corrupt = _in_d_bits_WIRE_23; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_85 = muxState_5_0 ? d_d_2_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_86 = muxState_5_1 ? _q_4_io_deq_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_87 = muxState_5_2 ? _q_5_io_deq_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_88 = _in_d_bits_T_85 | _in_d_bits_T_86; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_89 = _in_d_bits_T_88 | _in_d_bits_T_87; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_24 = _in_d_bits_T_89; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_22_data = _in_d_bits_WIRE_24; // @[Mux.scala:30:73]
wire _in_d_bits_T_90 = muxState_5_0 & d_d_2_bits_denied; // @[Mux.scala:30:73]
wire _in_d_bits_T_91 = muxState_5_1 & _q_4_io_deq_bits_denied; // @[Mux.scala:30:73]
wire _in_d_bits_T_92 = muxState_5_2 & _q_5_io_deq_bits_denied; // @[Mux.scala:30:73]
wire _in_d_bits_T_93 = _in_d_bits_T_90 | _in_d_bits_T_91; // @[Mux.scala:30:73]
wire _in_d_bits_T_94 = _in_d_bits_T_93 | _in_d_bits_T_92; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_27 = _in_d_bits_T_94; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_22_denied = _in_d_bits_WIRE_27; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_95 = muxState_5_0 ? d_d_2_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_96 = muxState_5_1 ? _q_4_io_deq_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_97 = muxState_5_2 ? _q_5_io_deq_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_98 = _in_d_bits_T_95 | _in_d_bits_T_96; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_99 = _in_d_bits_T_98 | _in_d_bits_T_97; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_28 = _in_d_bits_T_99; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_22_sink = _in_d_bits_WIRE_28; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_100 = muxState_5_0 ? d_d_2_bits_source : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_101 = muxState_5_1 ? _q_4_io_deq_bits_source : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_102 = muxState_5_2 ? _q_5_io_deq_bits_source : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_103 = _in_d_bits_T_100 | _in_d_bits_T_101; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_104 = _in_d_bits_T_103 | _in_d_bits_T_102; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_29 = _in_d_bits_T_104; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_22_source = _in_d_bits_WIRE_29; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_105 = muxState_5_0 ? d_d_2_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_106 = muxState_5_1 ? _q_4_io_deq_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_107 = muxState_5_2 ? _q_5_io_deq_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_108 = _in_d_bits_T_105 | _in_d_bits_T_106; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_109 = _in_d_bits_T_108 | _in_d_bits_T_107; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_30 = _in_d_bits_T_109; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_22_size = _in_d_bits_WIRE_30; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_110 = muxState_5_0 ? d_d_2_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_111 = muxState_5_1 ? _q_4_io_deq_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_112 = muxState_5_2 ? _q_5_io_deq_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_113 = _in_d_bits_T_110 | _in_d_bits_T_111; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_114 = _in_d_bits_T_113 | _in_d_bits_T_112; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_31 = _in_d_bits_T_114; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_22_param = _in_d_bits_WIRE_31; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_115 = muxState_5_0 ? d_d_2_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_116 = muxState_5_1 ? _q_4_io_deq_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_117 = muxState_5_2 ? _q_5_io_deq_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_118 = _in_d_bits_T_115 | _in_d_bits_T_116; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_119 = _in_d_bits_T_118 | _in_d_bits_T_117; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_32 = _in_d_bits_T_119; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_22_opcode = _in_d_bits_WIRE_32; // @[Mux.scala:30:73]
wire _a_a_ready_T_3; // @[Arbiter.scala:94:31]
wire _a_a_valid_T_7; // @[CacheCork.scala:81:33]
wire [2:0] a_a_3_bits_opcode; // @[CacheCork.scala:74:23]
wire [2:0] a_a_3_bits_param; // @[CacheCork.scala:74:23]
wire [4:0] a_a_3_bits_source; // @[CacheCork.scala:74:23]
wire a_a_3_ready; // @[CacheCork.scala:74:23]
wire a_a_3_valid; // @[CacheCork.scala:74:23]
wire _a_d_valid_T_3; // @[CacheCork.scala:93:33]
wire [2:0] a_d_3_bits_size; // @[CacheCork.scala:75:23]
wire [3:0] a_d_3_bits_source; // @[CacheCork.scala:75:23]
wire a_d_3_ready; // @[CacheCork.scala:75:23]
wire a_d_3_valid; // @[CacheCork.scala:75:23]
wire _isPut_T_6 = nodeIn_3_a_bits_opcode == 3'h0; // @[CacheCork.scala:76:38]
wire _isPut_T_7 = nodeIn_3_a_bits_opcode == 3'h1; // @[CacheCork.scala:76:74]
wire isPut_3 = _isPut_T_6 | _isPut_T_7; // @[CacheCork.scala:76:{38,54,74}]
wire _a_a_bits_source_T_16 = isPut_3; // @[CacheCork.scala:76:54, :83:55]
wire _toD_T_12 = nodeIn_3_a_bits_opcode == 3'h6; // @[CacheCork.scala:77:37]
wire _toD_T_13 = nodeIn_3_a_bits_param == 3'h2; // @[CacheCork.scala:77:73]
wire _toD_T_14 = _toD_T_12 & _toD_T_13; // @[CacheCork.scala:77:{37,54,73}]
wire _toD_T_15 = &nodeIn_3_a_bits_opcode; // @[CacheCork.scala:78:37]
wire toD_3 = _toD_T_14 | _toD_T_15; // @[CacheCork.scala:77:{54,97}, :78:37]
assign _nodeIn_a_ready_T_3 = toD_3 ? a_d_3_ready : a_a_3_ready; // @[CacheCork.scala:74:23, :75:23, :77:97, :79:26]
assign nodeIn_3_a_ready = _nodeIn_a_ready_T_3; // @[CacheCork.scala:79:26]
wire _a_a_valid_T_6 = ~toD_3; // @[CacheCork.scala:77:97, :81:36]
assign _a_a_valid_T_7 = nodeIn_3_a_valid & _a_a_valid_T_6; // @[CacheCork.scala:81:{33,36}]
assign a_a_3_valid = _a_a_valid_T_7; // @[CacheCork.scala:74:23, :81:33]
wire [4:0] _GEN_5 = {nodeIn_3_a_bits_source, 1'h0}; // @[CacheCork.scala:83:45]
wire [4:0] _a_a_bits_source_T_15; // @[CacheCork.scala:83:45]
assign _a_a_bits_source_T_15 = _GEN_5; // @[CacheCork.scala:83:45]
wire [4:0] _a_a_bits_source_T_18; // @[CacheCork.scala:89:47]
assign _a_a_bits_source_T_18 = _GEN_5; // @[CacheCork.scala:83:45, :89:47]
wire [4:0] _a_a_bits_source_T_17 = {_a_a_bits_source_T_15[4:1], _a_a_bits_source_T_15[0] | _a_a_bits_source_T_16}; // @[CacheCork.scala:83:{45,50,55}]
wire _T_200 = _toD_T_12 | (&nodeIn_3_a_bits_opcode); // @[CacheCork.scala:77:37, :78:37, :86:49]
assign a_a_3_bits_opcode = _T_200 ? 3'h4 : nodeIn_3_a_bits_opcode; // @[CacheCork.scala:74:23, :82:18, :86:{49,86}, :87:27]
assign a_a_3_bits_param = _T_200 ? 3'h0 : nodeIn_3_a_bits_param; // @[CacheCork.scala:74:23, :82:18, :86:{49,86}, :88:27]
wire [4:0] _a_a_bits_source_T_19 = {_a_a_bits_source_T_18[4:1], 1'h1}; // @[CacheCork.scala:89:{47,52}]
assign a_a_3_bits_source = _T_200 ? _a_a_bits_source_T_19 : _a_a_bits_source_T_17; // @[CacheCork.scala:74:23, :83:{25,50}, :86:{49,86}, :89:{27,52}]
assign _a_d_valid_T_3 = nodeIn_3_a_valid & toD_3; // @[CacheCork.scala:77:97, :93:33]
assign a_d_3_valid = _a_d_valid_T_3; // @[CacheCork.scala:75:23, :93:33]
assign a_d_3_bits_size = a_d_bits_d_3_size; // @[Edges.scala:645:17]
assign a_d_3_bits_source = a_d_bits_d_3_source; // @[Edges.scala:645:17]
wire _c_a_ready_T_3; // @[Arbiter.scala:94:31]
wire _c_a_valid_T_7; // @[CacheCork.scala:102:33]
wire [4:0] c_a_bits_a_3_source; // @[Edges.scala:480:17]
wire [7:0] c_a_bits_a_3_mask; // @[Edges.scala:480:17]
wire [2:0] c_a_3_bits_size; // @[CacheCork.scala:101:23]
wire [4:0] c_a_3_bits_source; // @[CacheCork.scala:101:23]
wire [31:0] c_a_3_bits_address; // @[CacheCork.scala:101:23]
wire [7:0] c_a_3_bits_mask; // @[CacheCork.scala:101:23]
wire [63:0] c_a_3_bits_data; // @[CacheCork.scala:101:23]
wire c_a_3_bits_corrupt; // @[CacheCork.scala:101:23]
wire c_a_3_ready; // @[CacheCork.scala:101:23]
wire c_a_3_valid; // @[CacheCork.scala:101:23]
wire _c_a_valid_T_6 = &nodeIn_3_c_bits_opcode; // @[CacheCork.scala:102:53]
assign _c_a_valid_T_7 = nodeIn_3_c_valid & _c_a_valid_T_6; // @[CacheCork.scala:102:{33,53}]
assign c_a_3_valid = _c_a_valid_T_7; // @[CacheCork.scala:101:23, :102:33]
wire [4:0] _c_a_bits_T_3 = {nodeIn_3_c_bits_source, 1'h0}; // @[CacheCork.scala:104:41]
assign c_a_bits_a_3_source = _c_a_bits_T_3; // @[Edges.scala:480:17]
wire _c_a_bits_legal_T_31 = nodeIn_3_c_bits_size != 3'h7; // @[Parameters.scala:92:38]
wire _c_a_bits_legal_T_32 = _c_a_bits_legal_T_31; // @[Parameters.scala:92:{33,38}]
wire _c_a_bits_legal_T_33 = _c_a_bits_legal_T_32; // @[Parameters.scala:684:29]
wire _c_a_bits_legal_T_39 = _c_a_bits_legal_T_33; // @[Parameters.scala:684:{29,54}]
wire [32:0] _c_a_bits_legal_T_35 = {1'h0, _c_a_bits_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire c_a_bits_legal_3 = _c_a_bits_legal_T_39; // @[Parameters.scala:684:54, :686:26]
assign c_a_3_bits_size = c_a_bits_a_3_size; // @[Edges.scala:480:17]
assign c_a_3_bits_source = c_a_bits_a_3_source; // @[Edges.scala:480:17]
assign c_a_3_bits_address = c_a_bits_a_3_address; // @[Edges.scala:480:17]
wire [7:0] _c_a_bits_a_mask_T_3; // @[Misc.scala:222:10]
assign c_a_3_bits_mask = c_a_bits_a_3_mask; // @[Edges.scala:480:17]
assign c_a_3_bits_data = c_a_bits_a_3_data; // @[Edges.scala:480:17]
assign c_a_3_bits_corrupt = c_a_bits_a_3_corrupt; // @[Edges.scala:480:17]
wire [1:0] c_a_bits_a_mask_sizeOH_shiftAmount_3 = _c_a_bits_a_mask_sizeOH_T_9[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _c_a_bits_a_mask_sizeOH_T_10 = 4'h1 << c_a_bits_a_mask_sizeOH_shiftAmount_3; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _c_a_bits_a_mask_sizeOH_T_11 = _c_a_bits_a_mask_sizeOH_T_10[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] c_a_bits_a_mask_sizeOH_3 = {_c_a_bits_a_mask_sizeOH_T_11[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire c_a_bits_a_mask_sub_sub_sub_0_1_3 = nodeIn_3_c_bits_size > 3'h2; // @[Misc.scala:206:21]
wire c_a_bits_a_mask_sub_sub_size_3 = c_a_bits_a_mask_sizeOH_3[2]; // @[Misc.scala:202:81, :209:26]
wire c_a_bits_a_mask_sub_sub_bit_3 = nodeIn_3_c_bits_address[2]; // @[Misc.scala:210:26]
wire c_a_bits_a_mask_sub_sub_1_2_3 = c_a_bits_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27]
wire c_a_bits_a_mask_sub_sub_nbit_3 = ~c_a_bits_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20]
wire c_a_bits_a_mask_sub_sub_0_2_3 = c_a_bits_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_sub_sub_acc_T_6 = c_a_bits_a_mask_sub_sub_size_3 & c_a_bits_a_mask_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_sub_0_1_3 = c_a_bits_a_mask_sub_sub_sub_0_1_3 | _c_a_bits_a_mask_sub_sub_acc_T_6; // @[Misc.scala:206:21, :215:{29,38}]
wire _c_a_bits_a_mask_sub_sub_acc_T_7 = c_a_bits_a_mask_sub_sub_size_3 & c_a_bits_a_mask_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_sub_1_1_3 = c_a_bits_a_mask_sub_sub_sub_0_1_3 | _c_a_bits_a_mask_sub_sub_acc_T_7; // @[Misc.scala:206:21, :215:{29,38}]
wire c_a_bits_a_mask_sub_size_3 = c_a_bits_a_mask_sizeOH_3[1]; // @[Misc.scala:202:81, :209:26]
wire c_a_bits_a_mask_sub_bit_3 = nodeIn_3_c_bits_address[1]; // @[Misc.scala:210:26]
wire c_a_bits_a_mask_sub_nbit_3 = ~c_a_bits_a_mask_sub_bit_3; // @[Misc.scala:210:26, :211:20]
wire c_a_bits_a_mask_sub_0_2_3 = c_a_bits_a_mask_sub_sub_0_2_3 & c_a_bits_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_12 = c_a_bits_a_mask_sub_size_3 & c_a_bits_a_mask_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_0_1_3 = c_a_bits_a_mask_sub_sub_0_1_3 | _c_a_bits_a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_sub_1_2_3 = c_a_bits_a_mask_sub_sub_0_2_3 & c_a_bits_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_13 = c_a_bits_a_mask_sub_size_3 & c_a_bits_a_mask_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_1_1_3 = c_a_bits_a_mask_sub_sub_0_1_3 | _c_a_bits_a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_sub_2_2_3 = c_a_bits_a_mask_sub_sub_1_2_3 & c_a_bits_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_14 = c_a_bits_a_mask_sub_size_3 & c_a_bits_a_mask_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_2_1_3 = c_a_bits_a_mask_sub_sub_1_1_3 | _c_a_bits_a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_sub_3_2_3 = c_a_bits_a_mask_sub_sub_1_2_3 & c_a_bits_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_15 = c_a_bits_a_mask_sub_size_3 & c_a_bits_a_mask_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_3_1_3 = c_a_bits_a_mask_sub_sub_1_1_3 | _c_a_bits_a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_size_3 = c_a_bits_a_mask_sizeOH_3[0]; // @[Misc.scala:202:81, :209:26]
wire c_a_bits_a_mask_bit_3 = nodeIn_3_c_bits_address[0]; // @[Misc.scala:210:26]
wire c_a_bits_a_mask_nbit_3 = ~c_a_bits_a_mask_bit_3; // @[Misc.scala:210:26, :211:20]
wire c_a_bits_a_mask_eq_24 = c_a_bits_a_mask_sub_0_2_3 & c_a_bits_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_24 = c_a_bits_a_mask_size_3 & c_a_bits_a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_24 = c_a_bits_a_mask_sub_0_1_3 | _c_a_bits_a_mask_acc_T_24; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_25 = c_a_bits_a_mask_sub_0_2_3 & c_a_bits_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_25 = c_a_bits_a_mask_size_3 & c_a_bits_a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_25 = c_a_bits_a_mask_sub_0_1_3 | _c_a_bits_a_mask_acc_T_25; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_26 = c_a_bits_a_mask_sub_1_2_3 & c_a_bits_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_26 = c_a_bits_a_mask_size_3 & c_a_bits_a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_26 = c_a_bits_a_mask_sub_1_1_3 | _c_a_bits_a_mask_acc_T_26; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_27 = c_a_bits_a_mask_sub_1_2_3 & c_a_bits_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_27 = c_a_bits_a_mask_size_3 & c_a_bits_a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_27 = c_a_bits_a_mask_sub_1_1_3 | _c_a_bits_a_mask_acc_T_27; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_28 = c_a_bits_a_mask_sub_2_2_3 & c_a_bits_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_28 = c_a_bits_a_mask_size_3 & c_a_bits_a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_28 = c_a_bits_a_mask_sub_2_1_3 | _c_a_bits_a_mask_acc_T_28; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_29 = c_a_bits_a_mask_sub_2_2_3 & c_a_bits_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_29 = c_a_bits_a_mask_size_3 & c_a_bits_a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_29 = c_a_bits_a_mask_sub_2_1_3 | _c_a_bits_a_mask_acc_T_29; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_30 = c_a_bits_a_mask_sub_3_2_3 & c_a_bits_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_30 = c_a_bits_a_mask_size_3 & c_a_bits_a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_30 = c_a_bits_a_mask_sub_3_1_3 | _c_a_bits_a_mask_acc_T_30; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_31 = c_a_bits_a_mask_sub_3_2_3 & c_a_bits_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_31 = c_a_bits_a_mask_size_3 & c_a_bits_a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_31 = c_a_bits_a_mask_sub_3_1_3 | _c_a_bits_a_mask_acc_T_31; // @[Misc.scala:215:{29,38}]
wire [1:0] c_a_bits_a_mask_lo_lo_3 = {c_a_bits_a_mask_acc_25, c_a_bits_a_mask_acc_24}; // @[Misc.scala:215:29, :222:10]
wire [1:0] c_a_bits_a_mask_lo_hi_3 = {c_a_bits_a_mask_acc_27, c_a_bits_a_mask_acc_26}; // @[Misc.scala:215:29, :222:10]
wire [3:0] c_a_bits_a_mask_lo_3 = {c_a_bits_a_mask_lo_hi_3, c_a_bits_a_mask_lo_lo_3}; // @[Misc.scala:222:10]
wire [1:0] c_a_bits_a_mask_hi_lo_3 = {c_a_bits_a_mask_acc_29, c_a_bits_a_mask_acc_28}; // @[Misc.scala:215:29, :222:10]
wire [1:0] c_a_bits_a_mask_hi_hi_3 = {c_a_bits_a_mask_acc_31, c_a_bits_a_mask_acc_30}; // @[Misc.scala:215:29, :222:10]
wire [3:0] c_a_bits_a_mask_hi_3 = {c_a_bits_a_mask_hi_hi_3, c_a_bits_a_mask_hi_lo_3}; // @[Misc.scala:222:10]
assign _c_a_bits_a_mask_T_3 = {c_a_bits_a_mask_hi_3, c_a_bits_a_mask_lo_3}; // @[Misc.scala:222:10]
assign c_a_bits_a_3_mask = _c_a_bits_a_mask_T_3; // @[Misc.scala:222:10]
wire _c_d_valid_T_7; // @[CacheCork.scala:113:33]
wire [2:0] c_d_3_bits_size; // @[CacheCork.scala:112:23]
wire [3:0] c_d_3_bits_source; // @[CacheCork.scala:112:23]
wire c_d_3_ready; // @[CacheCork.scala:112:23]
wire c_d_3_valid; // @[CacheCork.scala:112:23]
wire _T_202 = nodeIn_3_c_bits_opcode == 3'h6; // @[CacheCork.scala:113:53]
wire _c_d_valid_T_6; // @[CacheCork.scala:113:53]
assign _c_d_valid_T_6 = _T_202; // @[CacheCork.scala:113:53]
wire _nodeIn_c_ready_T_6; // @[CacheCork.scala:117:44]
assign _nodeIn_c_ready_T_6 = _T_202; // @[CacheCork.scala:113:53, :117:44]
assign _c_d_valid_T_7 = nodeIn_3_c_valid & _c_d_valid_T_6; // @[CacheCork.scala:113:{33,53}]
assign c_d_3_valid = _c_d_valid_T_7; // @[CacheCork.scala:112:23, :113:33]
assign c_d_3_bits_size = c_d_bits_d_3_size; // @[Edges.scala:677:17]
assign c_d_3_bits_source = c_d_bits_d_3_source; // @[Edges.scala:677:17]
assign _nodeIn_c_ready_T_7 = _nodeIn_c_ready_T_6 ? c_d_3_ready : c_a_3_ready; // @[CacheCork.scala:101:23, :112:23, :117:{26,44}]
assign nodeIn_3_c_ready = _nodeIn_c_ready_T_7; // @[CacheCork.scala:117:26]
wire _in_d_ready_T_19; // @[CacheCork.scala:136:34]
wire _in_d_valid_T_31; // @[Arbiter.scala:96:24]
wire [2:0] _in_d_bits_WIRE_33_opcode; // @[Mux.scala:30:73]
assign nodeIn_3_d_bits_opcode = in_d_3_bits_opcode; // @[CacheCork.scala:131:24]
wire [1:0] _in_d_bits_WIRE_33_param; // @[Mux.scala:30:73]
assign nodeIn_3_d_bits_param = in_d_3_bits_param; // @[CacheCork.scala:131:24]
wire [2:0] _in_d_bits_WIRE_33_size; // @[Mux.scala:30:73]
assign nodeIn_3_d_bits_size = in_d_3_bits_size; // @[CacheCork.scala:131:24]
wire [3:0] _in_d_bits_WIRE_33_source; // @[Mux.scala:30:73]
assign nodeIn_3_d_bits_source = in_d_3_bits_source; // @[CacheCork.scala:131:24]
wire [2:0] _in_d_bits_WIRE_33_sink; // @[Mux.scala:30:73]
wire _in_d_bits_WIRE_33_denied; // @[Mux.scala:30:73]
assign nodeIn_3_d_bits_denied = in_d_3_bits_denied; // @[CacheCork.scala:131:24]
wire [63:0] _in_d_bits_WIRE_33_data; // @[Mux.scala:30:73]
assign nodeIn_3_d_bits_data = in_d_3_bits_data; // @[CacheCork.scala:131:24]
wire _in_d_bits_WIRE_33_corrupt; // @[Mux.scala:30:73]
assign nodeIn_3_d_bits_corrupt = in_d_3_bits_corrupt; // @[CacheCork.scala:131:24]
wire [2:0] in_d_3_bits_sink; // @[CacheCork.scala:131:24]
wire in_d_3_ready; // @[CacheCork.scala:131:24]
wire in_d_3_valid; // @[CacheCork.scala:131:24]
wire _GEN_6 = in_d_3_ready & in_d_3_valid; // @[Decoupled.scala:51:35]
wire _d_first_T_3; // @[Decoupled.scala:51:35]
assign _d_first_T_3 = _GEN_6; // @[Decoupled.scala:51:35]
wire _beatsLeft_T_28; // @[Decoupled.scala:51:35]
assign _beatsLeft_T_28 = _GEN_6; // @[Decoupled.scala:51:35]
wire [12:0] _d_first_beats1_decode_T_9 = 13'h3F << in_d_3_bits_size; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata_3 = in_d_3_bits_opcode[0]; // @[Edges.scala:106:36]
wire [2:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_3; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_3 = _d_first_counter1_T_3[2:0]; // @[Edges.scala:230:28]
wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_6 = d_first_counter_3 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_7 = d_first_beats1_3 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _d_grant_T_6 = in_d_3_bits_opcode == 3'h5; // @[CacheCork.scala:131:24, :133:40]
wire _d_grant_T_7 = in_d_3_bits_opcode == 3'h4; // @[CacheCork.scala:131:24, :133:74]
wire d_grant_3 = _d_grant_T_6 | _d_grant_T_7; // @[CacheCork.scala:133:{40,54,74}]
wire _pool_io_alloc_ready_T_9 = nodeIn_3_d_ready & nodeIn_3_d_valid; // @[Decoupled.scala:51:35]
wire _pool_io_alloc_ready_T_10 = _pool_io_alloc_ready_T_9 & d_first_3; // @[Decoupled.scala:51:35]
wire _pool_io_alloc_ready_T_11 = _pool_io_alloc_ready_T_10 & d_grant_3; // @[CacheCork.scala:133:54, :134:{42,53}]
wire _nodeIn_d_valid_T_15 = ~d_first_3; // @[Edges.scala:231:25]
wire _nodeIn_d_valid_T_16 = _pool_3_io_alloc_valid | _nodeIn_d_valid_T_15; // @[CacheCork.scala:127:26, :135:{58,61}]
wire _nodeIn_d_valid_T_17 = ~d_grant_3; // @[CacheCork.scala:133:54, :135:73]
wire _nodeIn_d_valid_T_18 = _nodeIn_d_valid_T_16 | _nodeIn_d_valid_T_17; // @[CacheCork.scala:135:{58,70,73}]
assign _nodeIn_d_valid_T_19 = in_d_3_valid & _nodeIn_d_valid_T_18; // @[CacheCork.scala:131:24, :135:{34,70}]
assign nodeIn_3_d_valid = _nodeIn_d_valid_T_19; // @[CacheCork.scala:135:34]
wire _in_d_ready_T_15 = ~d_first_3; // @[Edges.scala:231:25]
wire _in_d_ready_T_16 = _pool_3_io_alloc_valid | _in_d_ready_T_15; // @[CacheCork.scala:127:26, :136:{58,61}]
wire _in_d_ready_T_17 = ~d_grant_3; // @[CacheCork.scala:133:54, :135:73, :136:73]
wire _in_d_ready_T_18 = _in_d_ready_T_16 | _in_d_ready_T_17; // @[CacheCork.scala:136:{58,70,73}]
assign _in_d_ready_T_19 = nodeIn_3_d_ready & _in_d_ready_T_18; // @[CacheCork.scala:136:{34,70}]
assign in_d_3_ready = _in_d_ready_T_19; // @[CacheCork.scala:131:24, :136:34]
reg [2:0] nodeIn_d_bits_sink_r_3; // @[package.scala:88:63]
assign _nodeIn_d_bits_sink_T_3 = d_first_3 ? _pool_3_io_alloc_bits : nodeIn_d_bits_sink_r_3; // @[package.scala:88:{42,63}]
assign nodeIn_3_d_bits_sink = _nodeIn_d_bits_sink_T_3; // @[package.scala:88:42]
wire _d_d_ready_T_3; // @[Arbiter.scala:94:31]
assign x1_nodeOut_2_d_ready = d_d_3_ready; // @[CacheCork.scala:141:23]
wire [3:0] _d_d_bits_source_T_3; // @[CacheCork.scala:143:46]
wire [2:0] d_d_3_bits_opcode; // @[CacheCork.scala:141:23]
wire [1:0] d_d_3_bits_param; // @[CacheCork.scala:141:23]
wire [3:0] d_d_3_bits_source; // @[CacheCork.scala:141:23]
wire [2:0] d_d_3_bits_sink; // @[CacheCork.scala:141:23]
assign d_d_3_bits_sink = {2'h0, x1_nodeOut_2_d_bits_sink}; // @[CacheCork.scala:141:23, :142:13]
assign _d_d_bits_source_T_3 = x1_nodeOut_2_d_bits_source[4:1]; // @[CacheCork.scala:143:46]
assign d_d_3_bits_source = _d_d_bits_source_T_3; // @[CacheCork.scala:141:23, :143:46]
wire [32:0] _aWOk_T_16 = {1'h0, _aWOk_T_15}; // @[Parameters.scala:137:{31,41}]
wire _bypass_T_7 = nodeIn_3_a_bits_source == d_d_3_bits_source; // @[CacheCork.scala:141:23, :150:91]
reg dWHeld_r_3; // @[package.scala:88:63]
wire dWHeld_3 = d_first_3 ? _dWHeld_T_3 : dWHeld_r_3; // @[package.scala:88:{42,63}]
wire _T_216 = x1_nodeOut_2_d_bits_opcode == 3'h1 & x1_nodeOut_2_d_bits_source[0]; // @[CacheCork.scala:162:{33,51,71}]
wire [1:0] _d_d_bits_param_T_3 = {1'h0, ~dWHeld_3}; // @[package.scala:88:42]
assign d_d_3_bits_param = _T_216 ? _d_d_bits_param_T_3 : x1_nodeOut_2_d_bits_param; // @[CacheCork.scala:141:23, :142:13, :162:{51,76}, :164:{26,32}]
assign d_d_3_bits_opcode = x1_nodeOut_2_d_bits_opcode == 3'h0 & ~(x1_nodeOut_2_d_bits_source[0]) ? 3'h6 : _T_216 ? 3'h5 : x1_nodeOut_2_d_bits_opcode; // @[CacheCork.scala:141:23, :142:13, :162:{51,71,76}, :163:27, :166:{33,47,50,73}, :167:27]
wire [12:0] _decode_T_27 = 13'h3F << c_a_3_bits_size; // @[package.scala:243:71]
wire [5:0] _decode_T_28 = _decode_T_27[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _decode_T_29 = ~_decode_T_28; // @[package.scala:243:{46,76}]
wire [2:0] decode_9 = _decode_T_29[5:3]; // @[package.scala:243:46]
wire [12:0] _decode_T_30 = 13'h3F << a_a_3_bits_size; // @[package.scala:243:71]
wire [5:0] _decode_T_31 = _decode_T_30[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _decode_T_32 = ~_decode_T_31; // @[package.scala:243:{46,76}]
wire [2:0] decode_10 = _decode_T_32[5:3]; // @[package.scala:243:46]
wire _opdata_T_7 = a_a_3_bits_opcode[2]; // @[Edges.scala:92:37]
wire opdata_10 = ~_opdata_T_7; // @[Edges.scala:92:{28,37}]
reg [2:0] beatsLeft_6; // @[Arbiter.scala:60:30]
wire idle_6 = beatsLeft_6 == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_6 = idle_6 & x1_nodeOut_2_a_ready; // @[Arbiter.scala:61:28, :62:24]
wire [1:0] _readys_T_72 = {a_a_3_valid, c_a_3_valid}; // @[CacheCork.scala:74:23, :101:23]
wire [2:0] _readys_T_73 = {_readys_T_72, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_T_74 = _readys_T_73[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_T_75 = _readys_T_72 | _readys_T_74; // @[package.scala:253:{43,53}]
wire [1:0] _readys_T_76 = _readys_T_75; // @[package.scala:253:43, :254:17]
wire [2:0] _readys_T_77 = {_readys_T_76, 1'h0}; // @[package.scala:254:17]
wire [1:0] _readys_T_78 = _readys_T_77[1:0]; // @[Arbiter.scala:16:{78,83}]
wire [1:0] _readys_T_79 = ~_readys_T_78; // @[Arbiter.scala:16:{61,83}]
wire _readys_T_80 = _readys_T_79[0]; // @[Arbiter.scala:16:61, :68:76]
wire readys_6_0 = _readys_T_80; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_81 = _readys_T_79[1]; // @[Arbiter.scala:16:61, :68:76]
wire readys_6_1 = _readys_T_81; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_15 = readys_6_0 & c_a_3_valid; // @[CacheCork.scala:101:23]
wire winner_6_0 = _winner_T_15; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_16 = readys_6_1 & a_a_3_valid; // @[CacheCork.scala:74:23]
wire winner_6_1 = _winner_T_16; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_6 = winner_6_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_6 = prefixOR_1_6 | winner_6_1; // @[Arbiter.scala:71:27, :76:48]
wire _nodeOut_a_valid_T_15 = c_a_3_valid | a_a_3_valid; // @[CacheCork.scala:74:23, :101:23]
wire [2:0] maskedBeats_0_6 = winner_6_0 ? decode_9 : 3'h0; // @[Edges.scala:220:59, :221:14]
wire [2:0] maskedBeats_1_6 = winner_6_1 & opdata_10 ? decode_10 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [2:0] initBeats_6 = maskedBeats_0_6 | maskedBeats_1_6; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_24 = x1_nodeOut_2_a_ready & x1_nodeOut_2_a_valid; // @[Decoupled.scala:51:35]
wire [3:0] _beatsLeft_T_25 = {1'h0, beatsLeft_6} - {3'h0, _beatsLeft_T_24}; // @[Decoupled.scala:51:35]
wire [2:0] _beatsLeft_T_26 = _beatsLeft_T_25[2:0]; // @[Arbiter.scala:85:52]
wire [2:0] _beatsLeft_T_27 = latch_6 ? initBeats_6 : _beatsLeft_T_26; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_6_0; // @[Arbiter.scala:88:26]
reg state_6_1; // @[Arbiter.scala:88:26]
wire muxState_6_0 = idle_6 ? winner_6_0 : state_6_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_6_1 = idle_6 ? winner_6_1 : state_6_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_6_0 = idle_6 ? readys_6_0 : state_6_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_6_1 = idle_6 ? readys_6_1 : state_6_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _c_a_ready_T_3 = x1_nodeOut_2_a_ready & allowed_6_0; // @[Arbiter.scala:92:24, :94:31]
assign c_a_3_ready = _c_a_ready_T_3; // @[CacheCork.scala:101:23]
assign _a_a_ready_T_3 = x1_nodeOut_2_a_ready & allowed_6_1; // @[Arbiter.scala:92:24, :94:31]
assign a_a_3_ready = _a_a_ready_T_3; // @[CacheCork.scala:74:23]
wire _nodeOut_a_valid_T_16 = state_6_0 & c_a_3_valid; // @[Mux.scala:30:73]
wire _nodeOut_a_valid_T_17 = state_6_1 & a_a_3_valid; // @[Mux.scala:30:73]
wire _nodeOut_a_valid_T_18 = _nodeOut_a_valid_T_16 | _nodeOut_a_valid_T_17; // @[Mux.scala:30:73]
wire _nodeOut_a_valid_WIRE_3 = _nodeOut_a_valid_T_18; // @[Mux.scala:30:73]
assign _nodeOut_a_valid_T_19 = idle_6 ? _nodeOut_a_valid_T_15 : _nodeOut_a_valid_WIRE_3; // @[Mux.scala:30:73]
assign x1_nodeOut_2_a_valid = _nodeOut_a_valid_T_19; // @[Arbiter.scala:96:24]
wire [2:0] _nodeOut_a_bits_WIRE_43; // @[Mux.scala:30:73]
assign x1_nodeOut_2_a_bits_opcode = _nodeOut_a_bits_WIRE_33_opcode; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_WIRE_42; // @[Mux.scala:30:73]
assign x1_nodeOut_2_a_bits_param = _nodeOut_a_bits_WIRE_33_param; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_WIRE_41; // @[Mux.scala:30:73]
assign x1_nodeOut_2_a_bits_size = _nodeOut_a_bits_WIRE_33_size; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_WIRE_40; // @[Mux.scala:30:73]
assign x1_nodeOut_2_a_bits_source = _nodeOut_a_bits_WIRE_33_source; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_WIRE_39; // @[Mux.scala:30:73]
assign x1_nodeOut_2_a_bits_address = _nodeOut_a_bits_WIRE_33_address; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_WIRE_36; // @[Mux.scala:30:73]
assign x1_nodeOut_2_a_bits_mask = _nodeOut_a_bits_WIRE_33_mask; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_WIRE_35; // @[Mux.scala:30:73]
assign x1_nodeOut_2_a_bits_data = _nodeOut_a_bits_WIRE_33_data; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_WIRE_34; // @[Mux.scala:30:73]
assign x1_nodeOut_2_a_bits_corrupt = _nodeOut_a_bits_WIRE_33_corrupt; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T_72 = muxState_6_0 & c_a_3_bits_corrupt; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T_73 = muxState_6_1 & a_a_3_bits_corrupt; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T_74 = _nodeOut_a_bits_T_72 | _nodeOut_a_bits_T_73; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_34 = _nodeOut_a_bits_T_74; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_33_corrupt = _nodeOut_a_bits_WIRE_34; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_T_75 = muxState_6_0 ? c_a_3_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_T_76 = muxState_6_1 ? a_a_3_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_T_77 = _nodeOut_a_bits_T_75 | _nodeOut_a_bits_T_76; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_35 = _nodeOut_a_bits_T_77; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_33_data = _nodeOut_a_bits_WIRE_35; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_T_78 = muxState_6_0 ? c_a_3_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_T_79 = muxState_6_1 ? a_a_3_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_T_80 = _nodeOut_a_bits_T_78 | _nodeOut_a_bits_T_79; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_36 = _nodeOut_a_bits_T_80; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_33_mask = _nodeOut_a_bits_WIRE_36; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_T_81 = muxState_6_0 ? c_a_3_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_T_82 = muxState_6_1 ? a_a_3_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_T_83 = _nodeOut_a_bits_T_81 | _nodeOut_a_bits_T_82; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_39 = _nodeOut_a_bits_T_83; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_33_address = _nodeOut_a_bits_WIRE_39; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_T_84 = muxState_6_0 ? c_a_3_bits_source : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_T_85 = muxState_6_1 ? a_a_3_bits_source : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_T_86 = _nodeOut_a_bits_T_84 | _nodeOut_a_bits_T_85; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_40 = _nodeOut_a_bits_T_86; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_33_source = _nodeOut_a_bits_WIRE_40; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_87 = muxState_6_0 ? c_a_3_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_88 = muxState_6_1 ? a_a_3_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_89 = _nodeOut_a_bits_T_87 | _nodeOut_a_bits_T_88; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_41 = _nodeOut_a_bits_T_89; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_33_size = _nodeOut_a_bits_WIRE_41; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_91 = muxState_6_1 ? a_a_3_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_92 = _nodeOut_a_bits_T_91; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_42 = _nodeOut_a_bits_T_92; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_33_param = _nodeOut_a_bits_WIRE_42; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_94 = muxState_6_1 ? a_a_3_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_95 = _nodeOut_a_bits_T_94; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_43 = _nodeOut_a_bits_T_95; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_33_opcode = _nodeOut_a_bits_WIRE_43; // @[Mux.scala:30:73]
wire [12:0] _decode_T_33 = 13'h3F << d_d_3_bits_size; // @[package.scala:243:71]
wire [5:0] _decode_T_34 = _decode_T_33[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _decode_T_35 = ~_decode_T_34; // @[package.scala:243:{46,76}]
wire [2:0] decode_11 = _decode_T_35[5:3]; // @[package.scala:243:46]
wire opdata_11 = d_d_3_bits_opcode[0]; // @[Edges.scala:106:36]
reg [2:0] beatsLeft_7; // @[Arbiter.scala:60:30]
wire idle_7 = beatsLeft_7 == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_7 = idle_7 & in_d_3_ready; // @[CacheCork.scala:131:24]
wire [1:0] readys_hi_3 = {_q_7_io_deq_valid, _q_6_io_deq_valid}; // @[Decoupled.scala:362:21]
wire [2:0] _readys_T_82 = {readys_hi_3, d_d_3_valid}; // @[CacheCork.scala:141:23]
wire [3:0] _readys_T_83 = {_readys_T_82, 1'h0}; // @[package.scala:253:48]
wire [2:0] _readys_T_84 = _readys_T_83[2:0]; // @[package.scala:253:{48,53}]
wire [2:0] _readys_T_85 = _readys_T_82 | _readys_T_84; // @[package.scala:253:{43,53}]
wire [4:0] _readys_T_86 = {_readys_T_85, 2'h0}; // @[package.scala:253:{43,48}]
wire [2:0] _readys_T_87 = _readys_T_86[2:0]; // @[package.scala:253:{48,53}]
wire [2:0] _readys_T_88 = _readys_T_85 | _readys_T_87; // @[package.scala:253:{43,53}]
wire [2:0] _readys_T_89 = _readys_T_88; // @[package.scala:253:43, :254:17]
wire [3:0] _readys_T_90 = {_readys_T_89, 1'h0}; // @[package.scala:254:17]
wire [2:0] _readys_T_91 = _readys_T_90[2:0]; // @[Arbiter.scala:16:{78,83}]
wire [2:0] _readys_T_92 = ~_readys_T_91; // @[Arbiter.scala:16:{61,83}]
wire _readys_T_93 = _readys_T_92[0]; // @[Arbiter.scala:16:61, :68:76]
wire readys_7_0 = _readys_T_93; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_94 = _readys_T_92[1]; // @[Arbiter.scala:16:61, :68:76]
wire readys_7_1 = _readys_T_94; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_95 = _readys_T_92[2]; // @[Arbiter.scala:16:61, :68:76]
wire readys_7_2 = _readys_T_95; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_17 = readys_7_0 & d_d_3_valid; // @[CacheCork.scala:141:23]
wire winner_7_0 = _winner_T_17; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_18 = readys_7_1 & _q_6_io_deq_valid; // @[Decoupled.scala:362:21]
wire winner_7_1 = _winner_T_18; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_19 = readys_7_2 & _q_7_io_deq_valid; // @[Decoupled.scala:362:21]
wire winner_7_2 = _winner_T_19; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_7 = winner_7_0; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_2_3 = prefixOR_1_7 | winner_7_1; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_7 = prefixOR_2_3 | winner_7_2; // @[Arbiter.scala:71:27, :76:48]
wire _in_d_valid_T_24 = d_d_3_valid | _q_6_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] maskedBeats_0_7 = winner_7_0 & opdata_11 ? decode_11 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire [2:0] _initBeats_T_3 = maskedBeats_0_7; // @[Arbiter.scala:82:69, :84:44]
wire [2:0] initBeats_7 = _initBeats_T_3; // @[Arbiter.scala:84:44]
wire [3:0] _beatsLeft_T_29 = {1'h0, beatsLeft_7} - {3'h0, _beatsLeft_T_28}; // @[Decoupled.scala:51:35]
wire [2:0] _beatsLeft_T_30 = _beatsLeft_T_29[2:0]; // @[Arbiter.scala:85:52]
wire [2:0] _beatsLeft_T_31 = latch_7 ? initBeats_7 : _beatsLeft_T_30; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_7_0; // @[Arbiter.scala:88:26]
reg state_7_1; // @[Arbiter.scala:88:26]
reg state_7_2; // @[Arbiter.scala:88:26]
wire muxState_7_0 = idle_7 ? winner_7_0 : state_7_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_7_1 = idle_7 ? winner_7_1 : state_7_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_7_2 = idle_7 ? winner_7_2 : state_7_2; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_7_0 = idle_7 ? readys_7_0 : state_7_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_7_1 = idle_7 ? readys_7_1 : state_7_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_7_2 = idle_7 ? readys_7_2 : state_7_2; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _d_d_ready_T_3 = in_d_3_ready & allowed_7_0; // @[CacheCork.scala:131:24]
assign d_d_3_ready = _d_d_ready_T_3; // @[CacheCork.scala:141:23]
wire _q_io_deq_ready_T_6 = in_d_3_ready & allowed_7_1; // @[CacheCork.scala:131:24]
wire _q_io_deq_ready_T_7 = in_d_3_ready & allowed_7_2; // @[CacheCork.scala:131:24]
wire _in_d_valid_T_25 = _in_d_valid_T_24 | _q_7_io_deq_valid; // @[Decoupled.scala:362:21]
wire _in_d_valid_T_26 = state_7_0 & d_d_3_valid; // @[Mux.scala:30:73]
wire _in_d_valid_T_27 = state_7_1 & _q_6_io_deq_valid; // @[Mux.scala:30:73]
wire _in_d_valid_T_28 = state_7_2 & _q_7_io_deq_valid; // @[Mux.scala:30:73]
wire _in_d_valid_T_29 = _in_d_valid_T_26 | _in_d_valid_T_27; // @[Mux.scala:30:73]
wire _in_d_valid_T_30 = _in_d_valid_T_29 | _in_d_valid_T_28; // @[Mux.scala:30:73]
wire _in_d_valid_WIRE_3 = _in_d_valid_T_30; // @[Mux.scala:30:73]
assign _in_d_valid_T_31 = idle_7 ? _in_d_valid_T_25 : _in_d_valid_WIRE_3; // @[Mux.scala:30:73]
assign in_d_3_valid = _in_d_valid_T_31; // @[CacheCork.scala:131:24]
wire [2:0] _in_d_bits_WIRE_43; // @[Mux.scala:30:73]
assign in_d_3_bits_opcode = _in_d_bits_WIRE_33_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_WIRE_42; // @[Mux.scala:30:73]
assign in_d_3_bits_param = _in_d_bits_WIRE_33_param; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_WIRE_41; // @[Mux.scala:30:73]
assign in_d_3_bits_size = _in_d_bits_WIRE_33_size; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_WIRE_40; // @[Mux.scala:30:73]
assign in_d_3_bits_source = _in_d_bits_WIRE_33_source; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_WIRE_39; // @[Mux.scala:30:73]
assign in_d_3_bits_sink = _in_d_bits_WIRE_33_sink; // @[Mux.scala:30:73]
wire _in_d_bits_WIRE_38; // @[Mux.scala:30:73]
assign in_d_3_bits_denied = _in_d_bits_WIRE_33_denied; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_WIRE_35; // @[Mux.scala:30:73]
assign in_d_3_bits_data = _in_d_bits_WIRE_33_data; // @[Mux.scala:30:73]
wire _in_d_bits_WIRE_34; // @[Mux.scala:30:73]
assign in_d_3_bits_corrupt = _in_d_bits_WIRE_33_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_120 = muxState_7_0 & d_d_3_bits_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_121 = muxState_7_1 & _q_6_io_deq_bits_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_122 = muxState_7_2 & _q_7_io_deq_bits_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_123 = _in_d_bits_T_120 | _in_d_bits_T_121; // @[Mux.scala:30:73]
wire _in_d_bits_T_124 = _in_d_bits_T_123 | _in_d_bits_T_122; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_34 = _in_d_bits_T_124; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_33_corrupt = _in_d_bits_WIRE_34; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_125 = muxState_7_0 ? d_d_3_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_126 = muxState_7_1 ? _q_6_io_deq_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_127 = muxState_7_2 ? _q_7_io_deq_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_128 = _in_d_bits_T_125 | _in_d_bits_T_126; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_129 = _in_d_bits_T_128 | _in_d_bits_T_127; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_35 = _in_d_bits_T_129; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_33_data = _in_d_bits_WIRE_35; // @[Mux.scala:30:73]
wire _in_d_bits_T_130 = muxState_7_0 & d_d_3_bits_denied; // @[Mux.scala:30:73]
wire _in_d_bits_T_131 = muxState_7_1 & _q_6_io_deq_bits_denied; // @[Mux.scala:30:73]
wire _in_d_bits_T_132 = muxState_7_2 & _q_7_io_deq_bits_denied; // @[Mux.scala:30:73]
wire _in_d_bits_T_133 = _in_d_bits_T_130 | _in_d_bits_T_131; // @[Mux.scala:30:73]
wire _in_d_bits_T_134 = _in_d_bits_T_133 | _in_d_bits_T_132; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_38 = _in_d_bits_T_134; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_33_denied = _in_d_bits_WIRE_38; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_135 = muxState_7_0 ? d_d_3_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_136 = muxState_7_1 ? _q_6_io_deq_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_137 = muxState_7_2 ? _q_7_io_deq_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_138 = _in_d_bits_T_135 | _in_d_bits_T_136; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_139 = _in_d_bits_T_138 | _in_d_bits_T_137; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_39 = _in_d_bits_T_139; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_33_sink = _in_d_bits_WIRE_39; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_140 = muxState_7_0 ? d_d_3_bits_source : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_141 = muxState_7_1 ? _q_6_io_deq_bits_source : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_142 = muxState_7_2 ? _q_7_io_deq_bits_source : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_143 = _in_d_bits_T_140 | _in_d_bits_T_141; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_144 = _in_d_bits_T_143 | _in_d_bits_T_142; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_40 = _in_d_bits_T_144; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_33_source = _in_d_bits_WIRE_40; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_145 = muxState_7_0 ? d_d_3_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_146 = muxState_7_1 ? _q_6_io_deq_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_147 = muxState_7_2 ? _q_7_io_deq_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_148 = _in_d_bits_T_145 | _in_d_bits_T_146; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_149 = _in_d_bits_T_148 | _in_d_bits_T_147; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_41 = _in_d_bits_T_149; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_33_size = _in_d_bits_WIRE_41; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_150 = muxState_7_0 ? d_d_3_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_151 = muxState_7_1 ? _q_6_io_deq_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_152 = muxState_7_2 ? _q_7_io_deq_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_153 = _in_d_bits_T_150 | _in_d_bits_T_151; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_154 = _in_d_bits_T_153 | _in_d_bits_T_152; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_42 = _in_d_bits_T_154; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_33_param = _in_d_bits_WIRE_42; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_155 = muxState_7_0 ? d_d_3_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_156 = muxState_7_1 ? _q_6_io_deq_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_157 = muxState_7_2 ? _q_7_io_deq_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_158 = _in_d_bits_T_155 | _in_d_bits_T_156; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_159 = _in_d_bits_T_158 | _in_d_bits_T_157; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_43 = _in_d_bits_T_159; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_33_opcode = _in_d_bits_WIRE_43; // @[Mux.scala:30:73]
wire _a_a_ready_T_4; // @[Arbiter.scala:94:31]
wire _a_a_valid_T_9; // @[CacheCork.scala:81:33]
wire [2:0] a_a_4_bits_opcode; // @[CacheCork.scala:74:23]
wire [2:0] a_a_4_bits_param; // @[CacheCork.scala:74:23]
wire [4:0] a_a_4_bits_source; // @[CacheCork.scala:74:23]
wire a_a_4_ready; // @[CacheCork.scala:74:23]
wire a_a_4_valid; // @[CacheCork.scala:74:23]
wire _a_d_valid_T_4; // @[CacheCork.scala:93:33]
wire [2:0] a_d_4_bits_size; // @[CacheCork.scala:75:23]
wire [3:0] a_d_4_bits_source; // @[CacheCork.scala:75:23]
wire a_d_4_ready; // @[CacheCork.scala:75:23]
wire a_d_4_valid; // @[CacheCork.scala:75:23]
wire _isPut_T_8 = nodeIn_4_a_bits_opcode == 3'h0; // @[CacheCork.scala:76:38]
wire _isPut_T_9 = nodeIn_4_a_bits_opcode == 3'h1; // @[CacheCork.scala:76:74]
wire isPut_4 = _isPut_T_8 | _isPut_T_9; // @[CacheCork.scala:76:{38,54,74}]
wire _a_a_bits_source_T_21 = isPut_4; // @[CacheCork.scala:76:54, :83:55]
wire _toD_T_16 = nodeIn_4_a_bits_opcode == 3'h6; // @[CacheCork.scala:77:37]
wire _toD_T_17 = nodeIn_4_a_bits_param == 3'h2; // @[CacheCork.scala:77:73]
wire _toD_T_18 = _toD_T_16 & _toD_T_17; // @[CacheCork.scala:77:{37,54,73}]
wire _toD_T_19 = &nodeIn_4_a_bits_opcode; // @[CacheCork.scala:78:37]
wire toD_4 = _toD_T_18 | _toD_T_19; // @[CacheCork.scala:77:{54,97}, :78:37]
assign _nodeIn_a_ready_T_4 = toD_4 ? a_d_4_ready : a_a_4_ready; // @[CacheCork.scala:74:23, :75:23, :77:97, :79:26]
assign nodeIn_4_a_ready = _nodeIn_a_ready_T_4; // @[CacheCork.scala:79:26]
wire _a_a_valid_T_8 = ~toD_4; // @[CacheCork.scala:77:97, :81:36]
assign _a_a_valid_T_9 = nodeIn_4_a_valid & _a_a_valid_T_8; // @[CacheCork.scala:81:{33,36}]
assign a_a_4_valid = _a_a_valid_T_9; // @[CacheCork.scala:74:23, :81:33]
wire [4:0] _GEN_7 = {nodeIn_4_a_bits_source, 1'h0}; // @[CacheCork.scala:83:45]
wire [4:0] _a_a_bits_source_T_20; // @[CacheCork.scala:83:45]
assign _a_a_bits_source_T_20 = _GEN_7; // @[CacheCork.scala:83:45]
wire [4:0] _a_a_bits_source_T_23; // @[CacheCork.scala:89:47]
assign _a_a_bits_source_T_23 = _GEN_7; // @[CacheCork.scala:83:45, :89:47]
wire [4:0] _a_a_bits_source_T_22 = {_a_a_bits_source_T_20[4:1], _a_a_bits_source_T_20[0] | _a_a_bits_source_T_21}; // @[CacheCork.scala:83:{45,50,55}]
wire _T_266 = _toD_T_16 | (&nodeIn_4_a_bits_opcode); // @[CacheCork.scala:77:37, :78:37, :86:49]
assign a_a_4_bits_opcode = _T_266 ? 3'h4 : nodeIn_4_a_bits_opcode; // @[CacheCork.scala:74:23, :82:18, :86:{49,86}, :87:27]
assign a_a_4_bits_param = _T_266 ? 3'h0 : nodeIn_4_a_bits_param; // @[CacheCork.scala:74:23, :82:18, :86:{49,86}, :88:27]
wire [4:0] _a_a_bits_source_T_24 = {_a_a_bits_source_T_23[4:1], 1'h1}; // @[CacheCork.scala:89:{47,52}]
assign a_a_4_bits_source = _T_266 ? _a_a_bits_source_T_24 : _a_a_bits_source_T_22; // @[CacheCork.scala:74:23, :83:{25,50}, :86:{49,86}, :89:{27,52}]
assign _a_d_valid_T_4 = nodeIn_4_a_valid & toD_4; // @[CacheCork.scala:77:97, :93:33]
assign a_d_4_valid = _a_d_valid_T_4; // @[CacheCork.scala:75:23, :93:33]
assign a_d_4_bits_size = a_d_bits_d_4_size; // @[Edges.scala:645:17]
assign a_d_4_bits_source = a_d_bits_d_4_source; // @[Edges.scala:645:17]
wire _c_a_ready_T_4; // @[Arbiter.scala:94:31]
wire _c_a_valid_T_9; // @[CacheCork.scala:102:33]
wire [4:0] c_a_bits_a_4_source; // @[Edges.scala:480:17]
wire [7:0] c_a_bits_a_4_mask; // @[Edges.scala:480:17]
wire [2:0] c_a_4_bits_size; // @[CacheCork.scala:101:23]
wire [4:0] c_a_4_bits_source; // @[CacheCork.scala:101:23]
wire [31:0] c_a_4_bits_address; // @[CacheCork.scala:101:23]
wire [7:0] c_a_4_bits_mask; // @[CacheCork.scala:101:23]
wire [63:0] c_a_4_bits_data; // @[CacheCork.scala:101:23]
wire c_a_4_bits_corrupt; // @[CacheCork.scala:101:23]
wire c_a_4_ready; // @[CacheCork.scala:101:23]
wire c_a_4_valid; // @[CacheCork.scala:101:23]
wire _c_a_valid_T_8 = &nodeIn_4_c_bits_opcode; // @[CacheCork.scala:102:53]
assign _c_a_valid_T_9 = nodeIn_4_c_valid & _c_a_valid_T_8; // @[CacheCork.scala:102:{33,53}]
assign c_a_4_valid = _c_a_valid_T_9; // @[CacheCork.scala:101:23, :102:33]
wire [4:0] _c_a_bits_T_4 = {nodeIn_4_c_bits_source, 1'h0}; // @[CacheCork.scala:104:41]
assign c_a_bits_a_4_source = _c_a_bits_T_4; // @[Edges.scala:480:17]
wire _c_a_bits_legal_T_41 = nodeIn_4_c_bits_size != 3'h7; // @[Parameters.scala:92:38]
wire _c_a_bits_legal_T_42 = _c_a_bits_legal_T_41; // @[Parameters.scala:92:{33,38}]
wire _c_a_bits_legal_T_43 = _c_a_bits_legal_T_42; // @[Parameters.scala:684:29]
wire _c_a_bits_legal_T_49 = _c_a_bits_legal_T_43; // @[Parameters.scala:684:{29,54}]
wire [32:0] _c_a_bits_legal_T_45 = {1'h0, _c_a_bits_legal_T_44}; // @[Parameters.scala:137:{31,41}]
wire c_a_bits_legal_4 = _c_a_bits_legal_T_49; // @[Parameters.scala:684:54, :686:26]
assign c_a_4_bits_size = c_a_bits_a_4_size; // @[Edges.scala:480:17]
assign c_a_4_bits_source = c_a_bits_a_4_source; // @[Edges.scala:480:17]
assign c_a_4_bits_address = c_a_bits_a_4_address; // @[Edges.scala:480:17]
wire [7:0] _c_a_bits_a_mask_T_4; // @[Misc.scala:222:10]
assign c_a_4_bits_mask = c_a_bits_a_4_mask; // @[Edges.scala:480:17]
assign c_a_4_bits_data = c_a_bits_a_4_data; // @[Edges.scala:480:17]
assign c_a_4_bits_corrupt = c_a_bits_a_4_corrupt; // @[Edges.scala:480:17]
wire [1:0] c_a_bits_a_mask_sizeOH_shiftAmount_4 = _c_a_bits_a_mask_sizeOH_T_12[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _c_a_bits_a_mask_sizeOH_T_13 = 4'h1 << c_a_bits_a_mask_sizeOH_shiftAmount_4; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _c_a_bits_a_mask_sizeOH_T_14 = _c_a_bits_a_mask_sizeOH_T_13[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] c_a_bits_a_mask_sizeOH_4 = {_c_a_bits_a_mask_sizeOH_T_14[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire c_a_bits_a_mask_sub_sub_sub_0_1_4 = nodeIn_4_c_bits_size > 3'h2; // @[Misc.scala:206:21]
wire c_a_bits_a_mask_sub_sub_size_4 = c_a_bits_a_mask_sizeOH_4[2]; // @[Misc.scala:202:81, :209:26]
wire c_a_bits_a_mask_sub_sub_bit_4 = nodeIn_4_c_bits_address[2]; // @[Misc.scala:210:26]
wire c_a_bits_a_mask_sub_sub_1_2_4 = c_a_bits_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27]
wire c_a_bits_a_mask_sub_sub_nbit_4 = ~c_a_bits_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20]
wire c_a_bits_a_mask_sub_sub_0_2_4 = c_a_bits_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_sub_sub_acc_T_8 = c_a_bits_a_mask_sub_sub_size_4 & c_a_bits_a_mask_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_sub_0_1_4 = c_a_bits_a_mask_sub_sub_sub_0_1_4 | _c_a_bits_a_mask_sub_sub_acc_T_8; // @[Misc.scala:206:21, :215:{29,38}]
wire _c_a_bits_a_mask_sub_sub_acc_T_9 = c_a_bits_a_mask_sub_sub_size_4 & c_a_bits_a_mask_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_sub_1_1_4 = c_a_bits_a_mask_sub_sub_sub_0_1_4 | _c_a_bits_a_mask_sub_sub_acc_T_9; // @[Misc.scala:206:21, :215:{29,38}]
wire c_a_bits_a_mask_sub_size_4 = c_a_bits_a_mask_sizeOH_4[1]; // @[Misc.scala:202:81, :209:26]
wire c_a_bits_a_mask_sub_bit_4 = nodeIn_4_c_bits_address[1]; // @[Misc.scala:210:26]
wire c_a_bits_a_mask_sub_nbit_4 = ~c_a_bits_a_mask_sub_bit_4; // @[Misc.scala:210:26, :211:20]
wire c_a_bits_a_mask_sub_0_2_4 = c_a_bits_a_mask_sub_sub_0_2_4 & c_a_bits_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_16 = c_a_bits_a_mask_sub_size_4 & c_a_bits_a_mask_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_0_1_4 = c_a_bits_a_mask_sub_sub_0_1_4 | _c_a_bits_a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_sub_1_2_4 = c_a_bits_a_mask_sub_sub_0_2_4 & c_a_bits_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_17 = c_a_bits_a_mask_sub_size_4 & c_a_bits_a_mask_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_1_1_4 = c_a_bits_a_mask_sub_sub_0_1_4 | _c_a_bits_a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_sub_2_2_4 = c_a_bits_a_mask_sub_sub_1_2_4 & c_a_bits_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_18 = c_a_bits_a_mask_sub_size_4 & c_a_bits_a_mask_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_2_1_4 = c_a_bits_a_mask_sub_sub_1_1_4 | _c_a_bits_a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_sub_3_2_4 = c_a_bits_a_mask_sub_sub_1_2_4 & c_a_bits_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_19 = c_a_bits_a_mask_sub_size_4 & c_a_bits_a_mask_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_3_1_4 = c_a_bits_a_mask_sub_sub_1_1_4 | _c_a_bits_a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_size_4 = c_a_bits_a_mask_sizeOH_4[0]; // @[Misc.scala:202:81, :209:26]
wire c_a_bits_a_mask_bit_4 = nodeIn_4_c_bits_address[0]; // @[Misc.scala:210:26]
wire c_a_bits_a_mask_nbit_4 = ~c_a_bits_a_mask_bit_4; // @[Misc.scala:210:26, :211:20]
wire c_a_bits_a_mask_eq_32 = c_a_bits_a_mask_sub_0_2_4 & c_a_bits_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_32 = c_a_bits_a_mask_size_4 & c_a_bits_a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_32 = c_a_bits_a_mask_sub_0_1_4 | _c_a_bits_a_mask_acc_T_32; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_33 = c_a_bits_a_mask_sub_0_2_4 & c_a_bits_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_33 = c_a_bits_a_mask_size_4 & c_a_bits_a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_33 = c_a_bits_a_mask_sub_0_1_4 | _c_a_bits_a_mask_acc_T_33; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_34 = c_a_bits_a_mask_sub_1_2_4 & c_a_bits_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_34 = c_a_bits_a_mask_size_4 & c_a_bits_a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_34 = c_a_bits_a_mask_sub_1_1_4 | _c_a_bits_a_mask_acc_T_34; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_35 = c_a_bits_a_mask_sub_1_2_4 & c_a_bits_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_35 = c_a_bits_a_mask_size_4 & c_a_bits_a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_35 = c_a_bits_a_mask_sub_1_1_4 | _c_a_bits_a_mask_acc_T_35; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_36 = c_a_bits_a_mask_sub_2_2_4 & c_a_bits_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_36 = c_a_bits_a_mask_size_4 & c_a_bits_a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_36 = c_a_bits_a_mask_sub_2_1_4 | _c_a_bits_a_mask_acc_T_36; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_37 = c_a_bits_a_mask_sub_2_2_4 & c_a_bits_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_37 = c_a_bits_a_mask_size_4 & c_a_bits_a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_37 = c_a_bits_a_mask_sub_2_1_4 | _c_a_bits_a_mask_acc_T_37; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_38 = c_a_bits_a_mask_sub_3_2_4 & c_a_bits_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_38 = c_a_bits_a_mask_size_4 & c_a_bits_a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_38 = c_a_bits_a_mask_sub_3_1_4 | _c_a_bits_a_mask_acc_T_38; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_39 = c_a_bits_a_mask_sub_3_2_4 & c_a_bits_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_39 = c_a_bits_a_mask_size_4 & c_a_bits_a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_39 = c_a_bits_a_mask_sub_3_1_4 | _c_a_bits_a_mask_acc_T_39; // @[Misc.scala:215:{29,38}]
wire [1:0] c_a_bits_a_mask_lo_lo_4 = {c_a_bits_a_mask_acc_33, c_a_bits_a_mask_acc_32}; // @[Misc.scala:215:29, :222:10]
wire [1:0] c_a_bits_a_mask_lo_hi_4 = {c_a_bits_a_mask_acc_35, c_a_bits_a_mask_acc_34}; // @[Misc.scala:215:29, :222:10]
wire [3:0] c_a_bits_a_mask_lo_4 = {c_a_bits_a_mask_lo_hi_4, c_a_bits_a_mask_lo_lo_4}; // @[Misc.scala:222:10]
wire [1:0] c_a_bits_a_mask_hi_lo_4 = {c_a_bits_a_mask_acc_37, c_a_bits_a_mask_acc_36}; // @[Misc.scala:215:29, :222:10]
wire [1:0] c_a_bits_a_mask_hi_hi_4 = {c_a_bits_a_mask_acc_39, c_a_bits_a_mask_acc_38}; // @[Misc.scala:215:29, :222:10]
wire [3:0] c_a_bits_a_mask_hi_4 = {c_a_bits_a_mask_hi_hi_4, c_a_bits_a_mask_hi_lo_4}; // @[Misc.scala:222:10]
assign _c_a_bits_a_mask_T_4 = {c_a_bits_a_mask_hi_4, c_a_bits_a_mask_lo_4}; // @[Misc.scala:222:10]
assign c_a_bits_a_4_mask = _c_a_bits_a_mask_T_4; // @[Misc.scala:222:10]
wire _c_d_valid_T_9; // @[CacheCork.scala:113:33]
wire [2:0] c_d_4_bits_size; // @[CacheCork.scala:112:23]
wire [3:0] c_d_4_bits_source; // @[CacheCork.scala:112:23]
wire c_d_4_ready; // @[CacheCork.scala:112:23]
wire c_d_4_valid; // @[CacheCork.scala:112:23]
wire _T_268 = nodeIn_4_c_bits_opcode == 3'h6; // @[CacheCork.scala:113:53]
wire _c_d_valid_T_8; // @[CacheCork.scala:113:53]
assign _c_d_valid_T_8 = _T_268; // @[CacheCork.scala:113:53]
wire _nodeIn_c_ready_T_8; // @[CacheCork.scala:117:44]
assign _nodeIn_c_ready_T_8 = _T_268; // @[CacheCork.scala:113:53, :117:44]
assign _c_d_valid_T_9 = nodeIn_4_c_valid & _c_d_valid_T_8; // @[CacheCork.scala:113:{33,53}]
assign c_d_4_valid = _c_d_valid_T_9; // @[CacheCork.scala:112:23, :113:33]
assign c_d_4_bits_size = c_d_bits_d_4_size; // @[Edges.scala:677:17]
assign c_d_4_bits_source = c_d_bits_d_4_source; // @[Edges.scala:677:17]
assign _nodeIn_c_ready_T_9 = _nodeIn_c_ready_T_8 ? c_d_4_ready : c_a_4_ready; // @[CacheCork.scala:101:23, :112:23, :117:{26,44}]
assign nodeIn_4_c_ready = _nodeIn_c_ready_T_9; // @[CacheCork.scala:117:26]
wire _in_d_ready_T_24; // @[CacheCork.scala:136:34]
wire _in_d_valid_T_39; // @[Arbiter.scala:96:24]
wire [2:0] _in_d_bits_WIRE_44_opcode; // @[Mux.scala:30:73]
assign nodeIn_4_d_bits_opcode = in_d_4_bits_opcode; // @[CacheCork.scala:131:24]
wire [1:0] _in_d_bits_WIRE_44_param; // @[Mux.scala:30:73]
assign nodeIn_4_d_bits_param = in_d_4_bits_param; // @[CacheCork.scala:131:24]
wire [2:0] _in_d_bits_WIRE_44_size; // @[Mux.scala:30:73]
assign nodeIn_4_d_bits_size = in_d_4_bits_size; // @[CacheCork.scala:131:24]
wire [3:0] _in_d_bits_WIRE_44_source; // @[Mux.scala:30:73]
assign nodeIn_4_d_bits_source = in_d_4_bits_source; // @[CacheCork.scala:131:24]
wire [2:0] _in_d_bits_WIRE_44_sink; // @[Mux.scala:30:73]
wire _in_d_bits_WIRE_44_denied; // @[Mux.scala:30:73]
assign nodeIn_4_d_bits_denied = in_d_4_bits_denied; // @[CacheCork.scala:131:24]
wire [63:0] _in_d_bits_WIRE_44_data; // @[Mux.scala:30:73]
assign nodeIn_4_d_bits_data = in_d_4_bits_data; // @[CacheCork.scala:131:24]
wire _in_d_bits_WIRE_44_corrupt; // @[Mux.scala:30:73]
assign nodeIn_4_d_bits_corrupt = in_d_4_bits_corrupt; // @[CacheCork.scala:131:24]
wire [2:0] in_d_4_bits_sink; // @[CacheCork.scala:131:24]
wire in_d_4_ready; // @[CacheCork.scala:131:24]
wire in_d_4_valid; // @[CacheCork.scala:131:24]
wire _GEN_8 = in_d_4_ready & in_d_4_valid; // @[Decoupled.scala:51:35]
wire _d_first_T_4; // @[Decoupled.scala:51:35]
assign _d_first_T_4 = _GEN_8; // @[Decoupled.scala:51:35]
wire _beatsLeft_T_36; // @[Decoupled.scala:51:35]
assign _beatsLeft_T_36 = _GEN_8; // @[Decoupled.scala:51:35]
wire [12:0] _d_first_beats1_decode_T_12 = 13'h3F << in_d_4_bits_size; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_13 = _d_first_beats1_decode_T_12[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_14 = ~_d_first_beats1_decode_T_13; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_4 = _d_first_beats1_decode_T_14[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata_4 = in_d_4_bits_opcode[0]; // @[Edges.scala:106:36]
wire [2:0] d_first_beats1_4 = d_first_beats1_opdata_4 ? d_first_beats1_decode_4 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_4; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_4 = {1'h0, d_first_counter_4} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_4 = _d_first_counter1_T_4[2:0]; // @[Edges.scala:230:28]
wire d_first_4 = d_first_counter_4 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_8 = d_first_counter_4 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_9 = d_first_beats1_4 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_4 = _d_first_last_T_8 | _d_first_last_T_9; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_4 = d_first_last_4 & _d_first_T_4; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_4 = ~d_first_counter1_4; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_4 = d_first_beats1_4 & _d_first_count_T_4; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_4 = d_first_4 ? d_first_beats1_4 : d_first_counter1_4; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _d_grant_T_8 = in_d_4_bits_opcode == 3'h5; // @[CacheCork.scala:131:24, :133:40]
wire _d_grant_T_9 = in_d_4_bits_opcode == 3'h4; // @[CacheCork.scala:131:24, :133:74]
wire d_grant_4 = _d_grant_T_8 | _d_grant_T_9; // @[CacheCork.scala:133:{40,54,74}]
wire _pool_io_alloc_ready_T_12 = nodeIn_4_d_ready & nodeIn_4_d_valid; // @[Decoupled.scala:51:35]
wire _pool_io_alloc_ready_T_13 = _pool_io_alloc_ready_T_12 & d_first_4; // @[Decoupled.scala:51:35]
wire _pool_io_alloc_ready_T_14 = _pool_io_alloc_ready_T_13 & d_grant_4; // @[CacheCork.scala:133:54, :134:{42,53}]
wire _nodeIn_d_valid_T_20 = ~d_first_4; // @[Edges.scala:231:25]
wire _nodeIn_d_valid_T_21 = _pool_4_io_alloc_valid | _nodeIn_d_valid_T_20; // @[CacheCork.scala:127:26, :135:{58,61}]
wire _nodeIn_d_valid_T_22 = ~d_grant_4; // @[CacheCork.scala:133:54, :135:73]
wire _nodeIn_d_valid_T_23 = _nodeIn_d_valid_T_21 | _nodeIn_d_valid_T_22; // @[CacheCork.scala:135:{58,70,73}]
assign _nodeIn_d_valid_T_24 = in_d_4_valid & _nodeIn_d_valid_T_23; // @[CacheCork.scala:131:24, :135:{34,70}]
assign nodeIn_4_d_valid = _nodeIn_d_valid_T_24; // @[CacheCork.scala:135:34]
wire _in_d_ready_T_20 = ~d_first_4; // @[Edges.scala:231:25]
wire _in_d_ready_T_21 = _pool_4_io_alloc_valid | _in_d_ready_T_20; // @[CacheCork.scala:127:26, :136:{58,61}]
wire _in_d_ready_T_22 = ~d_grant_4; // @[CacheCork.scala:133:54, :135:73, :136:73]
wire _in_d_ready_T_23 = _in_d_ready_T_21 | _in_d_ready_T_22; // @[CacheCork.scala:136:{58,70,73}]
assign _in_d_ready_T_24 = nodeIn_4_d_ready & _in_d_ready_T_23; // @[CacheCork.scala:136:{34,70}]
assign in_d_4_ready = _in_d_ready_T_24; // @[CacheCork.scala:131:24, :136:34]
reg [2:0] nodeIn_d_bits_sink_r_4; // @[package.scala:88:63]
assign _nodeIn_d_bits_sink_T_4 = d_first_4 ? _pool_4_io_alloc_bits : nodeIn_d_bits_sink_r_4; // @[package.scala:88:{42,63}]
assign nodeIn_4_d_bits_sink = _nodeIn_d_bits_sink_T_4; // @[package.scala:88:42]
wire _d_d_ready_T_4; // @[Arbiter.scala:94:31]
assign x1_nodeOut_3_d_ready = d_d_4_ready; // @[CacheCork.scala:141:23]
wire [3:0] _d_d_bits_source_T_4; // @[CacheCork.scala:143:46]
wire [2:0] d_d_4_bits_opcode; // @[CacheCork.scala:141:23]
wire [1:0] d_d_4_bits_param; // @[CacheCork.scala:141:23]
wire [3:0] d_d_4_bits_source; // @[CacheCork.scala:141:23]
wire [2:0] d_d_4_bits_sink; // @[CacheCork.scala:141:23]
assign d_d_4_bits_sink = {2'h0, x1_nodeOut_3_d_bits_sink}; // @[CacheCork.scala:141:23, :142:13]
assign _d_d_bits_source_T_4 = x1_nodeOut_3_d_bits_source[4:1]; // @[CacheCork.scala:143:46]
assign d_d_4_bits_source = _d_d_bits_source_T_4; // @[CacheCork.scala:141:23, :143:46]
wire [32:0] _aWOk_T_21 = {1'h0, _aWOk_T_20}; // @[Parameters.scala:137:{31,41}]
wire _bypass_T_9 = nodeIn_4_a_bits_source == d_d_4_bits_source; // @[CacheCork.scala:141:23, :150:91]
reg dWHeld_r_4; // @[package.scala:88:63]
wire dWHeld_4 = d_first_4 ? _dWHeld_T_4 : dWHeld_r_4; // @[package.scala:88:{42,63}]
wire _T_282 = x1_nodeOut_3_d_bits_opcode == 3'h1 & x1_nodeOut_3_d_bits_source[0]; // @[CacheCork.scala:162:{33,51,71}]
wire [1:0] _d_d_bits_param_T_4 = {1'h0, ~dWHeld_4}; // @[package.scala:88:42]
assign d_d_4_bits_param = _T_282 ? _d_d_bits_param_T_4 : x1_nodeOut_3_d_bits_param; // @[CacheCork.scala:141:23, :142:13, :162:{51,76}, :164:{26,32}]
assign d_d_4_bits_opcode = x1_nodeOut_3_d_bits_opcode == 3'h0 & ~(x1_nodeOut_3_d_bits_source[0]) ? 3'h6 : _T_282 ? 3'h5 : x1_nodeOut_3_d_bits_opcode; // @[CacheCork.scala:141:23, :142:13, :162:{51,71,76}, :163:27, :166:{33,47,50,73}, :167:27]
wire [12:0] _decode_T_36 = 13'h3F << c_a_4_bits_size; // @[package.scala:243:71]
wire [5:0] _decode_T_37 = _decode_T_36[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _decode_T_38 = ~_decode_T_37; // @[package.scala:243:{46,76}]
wire [2:0] decode_12 = _decode_T_38[5:3]; // @[package.scala:243:46]
wire [12:0] _decode_T_39 = 13'h3F << a_a_4_bits_size; // @[package.scala:243:71]
wire [5:0] _decode_T_40 = _decode_T_39[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _decode_T_41 = ~_decode_T_40; // @[package.scala:243:{46,76}]
wire [2:0] decode_13 = _decode_T_41[5:3]; // @[package.scala:243:46]
wire _opdata_T_9 = a_a_4_bits_opcode[2]; // @[Edges.scala:92:37]
wire opdata_13 = ~_opdata_T_9; // @[Edges.scala:92:{28,37}]
reg [2:0] beatsLeft_8; // @[Arbiter.scala:60:30]
wire idle_8 = beatsLeft_8 == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_8 = idle_8 & x1_nodeOut_3_a_ready; // @[Arbiter.scala:61:28, :62:24]
wire [1:0] _readys_T_96 = {a_a_4_valid, c_a_4_valid}; // @[CacheCork.scala:74:23, :101:23]
wire [2:0] _readys_T_97 = {_readys_T_96, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_T_98 = _readys_T_97[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_T_99 = _readys_T_96 | _readys_T_98; // @[package.scala:253:{43,53}]
wire [1:0] _readys_T_100 = _readys_T_99; // @[package.scala:253:43, :254:17]
wire [2:0] _readys_T_101 = {_readys_T_100, 1'h0}; // @[package.scala:254:17]
wire [1:0] _readys_T_102 = _readys_T_101[1:0]; // @[Arbiter.scala:16:{78,83}]
wire [1:0] _readys_T_103 = ~_readys_T_102; // @[Arbiter.scala:16:{61,83}]
wire _readys_T_104 = _readys_T_103[0]; // @[Arbiter.scala:16:61, :68:76]
wire readys_8_0 = _readys_T_104; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_105 = _readys_T_103[1]; // @[Arbiter.scala:16:61, :68:76]
wire readys_8_1 = _readys_T_105; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_20 = readys_8_0 & c_a_4_valid; // @[CacheCork.scala:101:23]
wire winner_8_0 = _winner_T_20; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_21 = readys_8_1 & a_a_4_valid; // @[CacheCork.scala:74:23]
wire winner_8_1 = _winner_T_21; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_8 = winner_8_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_8 = prefixOR_1_8 | winner_8_1; // @[Arbiter.scala:71:27, :76:48]
wire _nodeOut_a_valid_T_20 = c_a_4_valid | a_a_4_valid; // @[CacheCork.scala:74:23, :101:23]
wire [2:0] maskedBeats_0_8 = winner_8_0 ? decode_12 : 3'h0; // @[Edges.scala:220:59, :221:14]
wire [2:0] maskedBeats_1_8 = winner_8_1 & opdata_13 ? decode_13 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [2:0] initBeats_8 = maskedBeats_0_8 | maskedBeats_1_8; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_32 = x1_nodeOut_3_a_ready & x1_nodeOut_3_a_valid; // @[Decoupled.scala:51:35]
wire [3:0] _beatsLeft_T_33 = {1'h0, beatsLeft_8} - {3'h0, _beatsLeft_T_32}; // @[Decoupled.scala:51:35]
wire [2:0] _beatsLeft_T_34 = _beatsLeft_T_33[2:0]; // @[Arbiter.scala:85:52]
wire [2:0] _beatsLeft_T_35 = latch_8 ? initBeats_8 : _beatsLeft_T_34; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_8_0; // @[Arbiter.scala:88:26]
reg state_8_1; // @[Arbiter.scala:88:26]
wire muxState_8_0 = idle_8 ? winner_8_0 : state_8_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_8_1 = idle_8 ? winner_8_1 : state_8_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_8_0 = idle_8 ? readys_8_0 : state_8_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_8_1 = idle_8 ? readys_8_1 : state_8_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _c_a_ready_T_4 = x1_nodeOut_3_a_ready & allowed_8_0; // @[Arbiter.scala:92:24, :94:31]
assign c_a_4_ready = _c_a_ready_T_4; // @[CacheCork.scala:101:23]
assign _a_a_ready_T_4 = x1_nodeOut_3_a_ready & allowed_8_1; // @[Arbiter.scala:92:24, :94:31]
assign a_a_4_ready = _a_a_ready_T_4; // @[CacheCork.scala:74:23]
wire _nodeOut_a_valid_T_21 = state_8_0 & c_a_4_valid; // @[Mux.scala:30:73]
wire _nodeOut_a_valid_T_22 = state_8_1 & a_a_4_valid; // @[Mux.scala:30:73]
wire _nodeOut_a_valid_T_23 = _nodeOut_a_valid_T_21 | _nodeOut_a_valid_T_22; // @[Mux.scala:30:73]
wire _nodeOut_a_valid_WIRE_4 = _nodeOut_a_valid_T_23; // @[Mux.scala:30:73]
assign _nodeOut_a_valid_T_24 = idle_8 ? _nodeOut_a_valid_T_20 : _nodeOut_a_valid_WIRE_4; // @[Mux.scala:30:73]
assign x1_nodeOut_3_a_valid = _nodeOut_a_valid_T_24; // @[Arbiter.scala:96:24]
wire [2:0] _nodeOut_a_bits_WIRE_54; // @[Mux.scala:30:73]
assign x1_nodeOut_3_a_bits_opcode = _nodeOut_a_bits_WIRE_44_opcode; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_WIRE_53; // @[Mux.scala:30:73]
assign x1_nodeOut_3_a_bits_param = _nodeOut_a_bits_WIRE_44_param; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_WIRE_52; // @[Mux.scala:30:73]
assign x1_nodeOut_3_a_bits_size = _nodeOut_a_bits_WIRE_44_size; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_WIRE_51; // @[Mux.scala:30:73]
assign x1_nodeOut_3_a_bits_source = _nodeOut_a_bits_WIRE_44_source; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_WIRE_50; // @[Mux.scala:30:73]
assign x1_nodeOut_3_a_bits_address = _nodeOut_a_bits_WIRE_44_address; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_WIRE_47; // @[Mux.scala:30:73]
assign x1_nodeOut_3_a_bits_mask = _nodeOut_a_bits_WIRE_44_mask; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_WIRE_46; // @[Mux.scala:30:73]
assign x1_nodeOut_3_a_bits_data = _nodeOut_a_bits_WIRE_44_data; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_WIRE_45; // @[Mux.scala:30:73]
assign x1_nodeOut_3_a_bits_corrupt = _nodeOut_a_bits_WIRE_44_corrupt; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T_96 = muxState_8_0 & c_a_4_bits_corrupt; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T_97 = muxState_8_1 & a_a_4_bits_corrupt; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T_98 = _nodeOut_a_bits_T_96 | _nodeOut_a_bits_T_97; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_45 = _nodeOut_a_bits_T_98; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_44_corrupt = _nodeOut_a_bits_WIRE_45; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_T_99 = muxState_8_0 ? c_a_4_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_T_100 = muxState_8_1 ? a_a_4_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_T_101 = _nodeOut_a_bits_T_99 | _nodeOut_a_bits_T_100; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_46 = _nodeOut_a_bits_T_101; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_44_data = _nodeOut_a_bits_WIRE_46; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_T_102 = muxState_8_0 ? c_a_4_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_T_103 = muxState_8_1 ? a_a_4_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_T_104 = _nodeOut_a_bits_T_102 | _nodeOut_a_bits_T_103; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_47 = _nodeOut_a_bits_T_104; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_44_mask = _nodeOut_a_bits_WIRE_47; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_T_105 = muxState_8_0 ? c_a_4_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_T_106 = muxState_8_1 ? a_a_4_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_T_107 = _nodeOut_a_bits_T_105 | _nodeOut_a_bits_T_106; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_50 = _nodeOut_a_bits_T_107; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_44_address = _nodeOut_a_bits_WIRE_50; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_T_108 = muxState_8_0 ? c_a_4_bits_source : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_T_109 = muxState_8_1 ? a_a_4_bits_source : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_T_110 = _nodeOut_a_bits_T_108 | _nodeOut_a_bits_T_109; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_51 = _nodeOut_a_bits_T_110; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_44_source = _nodeOut_a_bits_WIRE_51; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_111 = muxState_8_0 ? c_a_4_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_112 = muxState_8_1 ? a_a_4_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_113 = _nodeOut_a_bits_T_111 | _nodeOut_a_bits_T_112; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_52 = _nodeOut_a_bits_T_113; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_44_size = _nodeOut_a_bits_WIRE_52; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_115 = muxState_8_1 ? a_a_4_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_116 = _nodeOut_a_bits_T_115; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_53 = _nodeOut_a_bits_T_116; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_44_param = _nodeOut_a_bits_WIRE_53; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_118 = muxState_8_1 ? a_a_4_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_119 = _nodeOut_a_bits_T_118; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_54 = _nodeOut_a_bits_T_119; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_44_opcode = _nodeOut_a_bits_WIRE_54; // @[Mux.scala:30:73]
wire [12:0] _decode_T_42 = 13'h3F << d_d_4_bits_size; // @[package.scala:243:71]
wire [5:0] _decode_T_43 = _decode_T_42[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _decode_T_44 = ~_decode_T_43; // @[package.scala:243:{46,76}]
wire [2:0] decode_14 = _decode_T_44[5:3]; // @[package.scala:243:46]
wire opdata_14 = d_d_4_bits_opcode[0]; // @[Edges.scala:106:36]
reg [2:0] beatsLeft_9; // @[Arbiter.scala:60:30]
wire idle_9 = beatsLeft_9 == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_9 = idle_9 & in_d_4_ready; // @[CacheCork.scala:131:24]
wire [1:0] readys_hi_4 = {_q_9_io_deq_valid, _q_8_io_deq_valid}; // @[Decoupled.scala:362:21]
wire [2:0] _readys_T_106 = {readys_hi_4, d_d_4_valid}; // @[CacheCork.scala:141:23]
wire [3:0] _readys_T_107 = {_readys_T_106, 1'h0}; // @[package.scala:253:48]
wire [2:0] _readys_T_108 = _readys_T_107[2:0]; // @[package.scala:253:{48,53}]
wire [2:0] _readys_T_109 = _readys_T_106 | _readys_T_108; // @[package.scala:253:{43,53}]
wire [4:0] _readys_T_110 = {_readys_T_109, 2'h0}; // @[package.scala:253:{43,48}]
wire [2:0] _readys_T_111 = _readys_T_110[2:0]; // @[package.scala:253:{48,53}]
wire [2:0] _readys_T_112 = _readys_T_109 | _readys_T_111; // @[package.scala:253:{43,53}]
wire [2:0] _readys_T_113 = _readys_T_112; // @[package.scala:253:43, :254:17]
wire [3:0] _readys_T_114 = {_readys_T_113, 1'h0}; // @[package.scala:254:17]
wire [2:0] _readys_T_115 = _readys_T_114[2:0]; // @[Arbiter.scala:16:{78,83}]
wire [2:0] _readys_T_116 = ~_readys_T_115; // @[Arbiter.scala:16:{61,83}]
wire _readys_T_117 = _readys_T_116[0]; // @[Arbiter.scala:16:61, :68:76]
wire readys_9_0 = _readys_T_117; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_118 = _readys_T_116[1]; // @[Arbiter.scala:16:61, :68:76]
wire readys_9_1 = _readys_T_118; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_119 = _readys_T_116[2]; // @[Arbiter.scala:16:61, :68:76]
wire readys_9_2 = _readys_T_119; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_22 = readys_9_0 & d_d_4_valid; // @[CacheCork.scala:141:23]
wire winner_9_0 = _winner_T_22; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_23 = readys_9_1 & _q_8_io_deq_valid; // @[Decoupled.scala:362:21]
wire winner_9_1 = _winner_T_23; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_24 = readys_9_2 & _q_9_io_deq_valid; // @[Decoupled.scala:362:21]
wire winner_9_2 = _winner_T_24; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_9 = winner_9_0; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_2_4 = prefixOR_1_9 | winner_9_1; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_9 = prefixOR_2_4 | winner_9_2; // @[Arbiter.scala:71:27, :76:48]
wire _in_d_valid_T_32 = d_d_4_valid | _q_8_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] maskedBeats_0_9 = winner_9_0 & opdata_14 ? decode_14 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire [2:0] _initBeats_T_4 = maskedBeats_0_9; // @[Arbiter.scala:82:69, :84:44]
wire [2:0] initBeats_9 = _initBeats_T_4; // @[Arbiter.scala:84:44]
wire [3:0] _beatsLeft_T_37 = {1'h0, beatsLeft_9} - {3'h0, _beatsLeft_T_36}; // @[Decoupled.scala:51:35]
wire [2:0] _beatsLeft_T_38 = _beatsLeft_T_37[2:0]; // @[Arbiter.scala:85:52]
wire [2:0] _beatsLeft_T_39 = latch_9 ? initBeats_9 : _beatsLeft_T_38; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_9_0; // @[Arbiter.scala:88:26]
reg state_9_1; // @[Arbiter.scala:88:26]
reg state_9_2; // @[Arbiter.scala:88:26]
wire muxState_9_0 = idle_9 ? winner_9_0 : state_9_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_9_1 = idle_9 ? winner_9_1 : state_9_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_9_2 = idle_9 ? winner_9_2 : state_9_2; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_9_0 = idle_9 ? readys_9_0 : state_9_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_9_1 = idle_9 ? readys_9_1 : state_9_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_9_2 = idle_9 ? readys_9_2 : state_9_2; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _d_d_ready_T_4 = in_d_4_ready & allowed_9_0; // @[CacheCork.scala:131:24]
assign d_d_4_ready = _d_d_ready_T_4; // @[CacheCork.scala:141:23]
wire _q_io_deq_ready_T_8 = in_d_4_ready & allowed_9_1; // @[CacheCork.scala:131:24]
wire _q_io_deq_ready_T_9 = in_d_4_ready & allowed_9_2; // @[CacheCork.scala:131:24]
wire _in_d_valid_T_33 = _in_d_valid_T_32 | _q_9_io_deq_valid; // @[Decoupled.scala:362:21]
wire _in_d_valid_T_34 = state_9_0 & d_d_4_valid; // @[Mux.scala:30:73]
wire _in_d_valid_T_35 = state_9_1 & _q_8_io_deq_valid; // @[Mux.scala:30:73]
wire _in_d_valid_T_36 = state_9_2 & _q_9_io_deq_valid; // @[Mux.scala:30:73]
wire _in_d_valid_T_37 = _in_d_valid_T_34 | _in_d_valid_T_35; // @[Mux.scala:30:73]
wire _in_d_valid_T_38 = _in_d_valid_T_37 | _in_d_valid_T_36; // @[Mux.scala:30:73]
wire _in_d_valid_WIRE_4 = _in_d_valid_T_38; // @[Mux.scala:30:73]
assign _in_d_valid_T_39 = idle_9 ? _in_d_valid_T_33 : _in_d_valid_WIRE_4; // @[Mux.scala:30:73]
assign in_d_4_valid = _in_d_valid_T_39; // @[CacheCork.scala:131:24]
wire [2:0] _in_d_bits_WIRE_54; // @[Mux.scala:30:73]
assign in_d_4_bits_opcode = _in_d_bits_WIRE_44_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_WIRE_53; // @[Mux.scala:30:73]
assign in_d_4_bits_param = _in_d_bits_WIRE_44_param; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_WIRE_52; // @[Mux.scala:30:73]
assign in_d_4_bits_size = _in_d_bits_WIRE_44_size; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_WIRE_51; // @[Mux.scala:30:73]
assign in_d_4_bits_source = _in_d_bits_WIRE_44_source; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_WIRE_50; // @[Mux.scala:30:73]
assign in_d_4_bits_sink = _in_d_bits_WIRE_44_sink; // @[Mux.scala:30:73]
wire _in_d_bits_WIRE_49; // @[Mux.scala:30:73]
assign in_d_4_bits_denied = _in_d_bits_WIRE_44_denied; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_WIRE_46; // @[Mux.scala:30:73]
assign in_d_4_bits_data = _in_d_bits_WIRE_44_data; // @[Mux.scala:30:73]
wire _in_d_bits_WIRE_45; // @[Mux.scala:30:73]
assign in_d_4_bits_corrupt = _in_d_bits_WIRE_44_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_160 = muxState_9_0 & d_d_4_bits_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_161 = muxState_9_1 & _q_8_io_deq_bits_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_162 = muxState_9_2 & _q_9_io_deq_bits_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_163 = _in_d_bits_T_160 | _in_d_bits_T_161; // @[Mux.scala:30:73]
wire _in_d_bits_T_164 = _in_d_bits_T_163 | _in_d_bits_T_162; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_45 = _in_d_bits_T_164; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_44_corrupt = _in_d_bits_WIRE_45; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_165 = muxState_9_0 ? d_d_4_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_166 = muxState_9_1 ? _q_8_io_deq_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_167 = muxState_9_2 ? _q_9_io_deq_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_168 = _in_d_bits_T_165 | _in_d_bits_T_166; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_169 = _in_d_bits_T_168 | _in_d_bits_T_167; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_46 = _in_d_bits_T_169; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_44_data = _in_d_bits_WIRE_46; // @[Mux.scala:30:73]
wire _in_d_bits_T_170 = muxState_9_0 & d_d_4_bits_denied; // @[Mux.scala:30:73]
wire _in_d_bits_T_171 = muxState_9_1 & _q_8_io_deq_bits_denied; // @[Mux.scala:30:73]
wire _in_d_bits_T_172 = muxState_9_2 & _q_9_io_deq_bits_denied; // @[Mux.scala:30:73]
wire _in_d_bits_T_173 = _in_d_bits_T_170 | _in_d_bits_T_171; // @[Mux.scala:30:73]
wire _in_d_bits_T_174 = _in_d_bits_T_173 | _in_d_bits_T_172; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_49 = _in_d_bits_T_174; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_44_denied = _in_d_bits_WIRE_49; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_175 = muxState_9_0 ? d_d_4_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_176 = muxState_9_1 ? _q_8_io_deq_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_177 = muxState_9_2 ? _q_9_io_deq_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_178 = _in_d_bits_T_175 | _in_d_bits_T_176; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_179 = _in_d_bits_T_178 | _in_d_bits_T_177; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_50 = _in_d_bits_T_179; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_44_sink = _in_d_bits_WIRE_50; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_180 = muxState_9_0 ? d_d_4_bits_source : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_181 = muxState_9_1 ? _q_8_io_deq_bits_source : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_182 = muxState_9_2 ? _q_9_io_deq_bits_source : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_183 = _in_d_bits_T_180 | _in_d_bits_T_181; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_184 = _in_d_bits_T_183 | _in_d_bits_T_182; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_51 = _in_d_bits_T_184; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_44_source = _in_d_bits_WIRE_51; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_185 = muxState_9_0 ? d_d_4_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_186 = muxState_9_1 ? _q_8_io_deq_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_187 = muxState_9_2 ? _q_9_io_deq_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_188 = _in_d_bits_T_185 | _in_d_bits_T_186; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_189 = _in_d_bits_T_188 | _in_d_bits_T_187; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_52 = _in_d_bits_T_189; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_44_size = _in_d_bits_WIRE_52; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_190 = muxState_9_0 ? d_d_4_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_191 = muxState_9_1 ? _q_8_io_deq_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_192 = muxState_9_2 ? _q_9_io_deq_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_193 = _in_d_bits_T_190 | _in_d_bits_T_191; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_194 = _in_d_bits_T_193 | _in_d_bits_T_192; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_53 = _in_d_bits_T_194; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_44_param = _in_d_bits_WIRE_53; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_195 = muxState_9_0 ? d_d_4_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_196 = muxState_9_1 ? _q_8_io_deq_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_197 = muxState_9_2 ? _q_9_io_deq_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_198 = _in_d_bits_T_195 | _in_d_bits_T_196; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_199 = _in_d_bits_T_198 | _in_d_bits_T_197; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_54 = _in_d_bits_T_199; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_44_opcode = _in_d_bits_WIRE_54; // @[Mux.scala:30:73]
wire _a_a_ready_T_5; // @[Arbiter.scala:94:31]
wire _a_a_valid_T_11; // @[CacheCork.scala:81:33]
wire [2:0] a_a_5_bits_opcode; // @[CacheCork.scala:74:23]
wire [2:0] a_a_5_bits_param; // @[CacheCork.scala:74:23]
wire [4:0] a_a_5_bits_source; // @[CacheCork.scala:74:23]
wire a_a_5_ready; // @[CacheCork.scala:74:23]
wire a_a_5_valid; // @[CacheCork.scala:74:23]
wire _a_d_valid_T_5; // @[CacheCork.scala:93:33]
wire [2:0] a_d_5_bits_size; // @[CacheCork.scala:75:23]
wire [3:0] a_d_5_bits_source; // @[CacheCork.scala:75:23]
wire a_d_5_ready; // @[CacheCork.scala:75:23]
wire a_d_5_valid; // @[CacheCork.scala:75:23]
wire _isPut_T_10 = nodeIn_5_a_bits_opcode == 3'h0; // @[CacheCork.scala:76:38]
wire _isPut_T_11 = nodeIn_5_a_bits_opcode == 3'h1; // @[CacheCork.scala:76:74]
wire isPut_5 = _isPut_T_10 | _isPut_T_11; // @[CacheCork.scala:76:{38,54,74}]
wire _a_a_bits_source_T_26 = isPut_5; // @[CacheCork.scala:76:54, :83:55]
wire _toD_T_20 = nodeIn_5_a_bits_opcode == 3'h6; // @[CacheCork.scala:77:37]
wire _toD_T_21 = nodeIn_5_a_bits_param == 3'h2; // @[CacheCork.scala:77:73]
wire _toD_T_22 = _toD_T_20 & _toD_T_21; // @[CacheCork.scala:77:{37,54,73}]
wire _toD_T_23 = &nodeIn_5_a_bits_opcode; // @[CacheCork.scala:78:37]
wire toD_5 = _toD_T_22 | _toD_T_23; // @[CacheCork.scala:77:{54,97}, :78:37]
assign _nodeIn_a_ready_T_5 = toD_5 ? a_d_5_ready : a_a_5_ready; // @[CacheCork.scala:74:23, :75:23, :77:97, :79:26]
assign nodeIn_5_a_ready = _nodeIn_a_ready_T_5; // @[CacheCork.scala:79:26]
wire _a_a_valid_T_10 = ~toD_5; // @[CacheCork.scala:77:97, :81:36]
assign _a_a_valid_T_11 = nodeIn_5_a_valid & _a_a_valid_T_10; // @[CacheCork.scala:81:{33,36}]
assign a_a_5_valid = _a_a_valid_T_11; // @[CacheCork.scala:74:23, :81:33]
wire [4:0] _GEN_9 = {nodeIn_5_a_bits_source, 1'h0}; // @[CacheCork.scala:83:45]
wire [4:0] _a_a_bits_source_T_25; // @[CacheCork.scala:83:45]
assign _a_a_bits_source_T_25 = _GEN_9; // @[CacheCork.scala:83:45]
wire [4:0] _a_a_bits_source_T_28; // @[CacheCork.scala:89:47]
assign _a_a_bits_source_T_28 = _GEN_9; // @[CacheCork.scala:83:45, :89:47]
wire [4:0] _a_a_bits_source_T_27 = {_a_a_bits_source_T_25[4:1], _a_a_bits_source_T_25[0] | _a_a_bits_source_T_26}; // @[CacheCork.scala:83:{45,50,55}]
wire _T_332 = _toD_T_20 | (&nodeIn_5_a_bits_opcode); // @[CacheCork.scala:77:37, :78:37, :86:49]
assign a_a_5_bits_opcode = _T_332 ? 3'h4 : nodeIn_5_a_bits_opcode; // @[CacheCork.scala:74:23, :82:18, :86:{49,86}, :87:27]
assign a_a_5_bits_param = _T_332 ? 3'h0 : nodeIn_5_a_bits_param; // @[CacheCork.scala:74:23, :82:18, :86:{49,86}, :88:27]
wire [4:0] _a_a_bits_source_T_29 = {_a_a_bits_source_T_28[4:1], 1'h1}; // @[CacheCork.scala:89:{47,52}]
assign a_a_5_bits_source = _T_332 ? _a_a_bits_source_T_29 : _a_a_bits_source_T_27; // @[CacheCork.scala:74:23, :83:{25,50}, :86:{49,86}, :89:{27,52}]
assign _a_d_valid_T_5 = nodeIn_5_a_valid & toD_5; // @[CacheCork.scala:77:97, :93:33]
assign a_d_5_valid = _a_d_valid_T_5; // @[CacheCork.scala:75:23, :93:33]
assign a_d_5_bits_size = a_d_bits_d_5_size; // @[Edges.scala:645:17]
assign a_d_5_bits_source = a_d_bits_d_5_source; // @[Edges.scala:645:17]
wire _c_a_ready_T_5; // @[Arbiter.scala:94:31]
wire _c_a_valid_T_11; // @[CacheCork.scala:102:33]
wire [4:0] c_a_bits_a_5_source; // @[Edges.scala:480:17]
wire [7:0] c_a_bits_a_5_mask; // @[Edges.scala:480:17]
wire [2:0] c_a_5_bits_size; // @[CacheCork.scala:101:23]
wire [4:0] c_a_5_bits_source; // @[CacheCork.scala:101:23]
wire [31:0] c_a_5_bits_address; // @[CacheCork.scala:101:23]
wire [7:0] c_a_5_bits_mask; // @[CacheCork.scala:101:23]
wire [63:0] c_a_5_bits_data; // @[CacheCork.scala:101:23]
wire c_a_5_bits_corrupt; // @[CacheCork.scala:101:23]
wire c_a_5_ready; // @[CacheCork.scala:101:23]
wire c_a_5_valid; // @[CacheCork.scala:101:23]
wire _c_a_valid_T_10 = &nodeIn_5_c_bits_opcode; // @[CacheCork.scala:102:53]
assign _c_a_valid_T_11 = nodeIn_5_c_valid & _c_a_valid_T_10; // @[CacheCork.scala:102:{33,53}]
assign c_a_5_valid = _c_a_valid_T_11; // @[CacheCork.scala:101:23, :102:33]
wire [4:0] _c_a_bits_T_5 = {nodeIn_5_c_bits_source, 1'h0}; // @[CacheCork.scala:104:41]
assign c_a_bits_a_5_source = _c_a_bits_T_5; // @[Edges.scala:480:17]
wire _c_a_bits_legal_T_51 = nodeIn_5_c_bits_size != 3'h7; // @[Parameters.scala:92:38]
wire _c_a_bits_legal_T_52 = _c_a_bits_legal_T_51; // @[Parameters.scala:92:{33,38}]
wire _c_a_bits_legal_T_53 = _c_a_bits_legal_T_52; // @[Parameters.scala:684:29]
wire _c_a_bits_legal_T_59 = _c_a_bits_legal_T_53; // @[Parameters.scala:684:{29,54}]
wire [32:0] _c_a_bits_legal_T_55 = {1'h0, _c_a_bits_legal_T_54}; // @[Parameters.scala:137:{31,41}]
wire c_a_bits_legal_5 = _c_a_bits_legal_T_59; // @[Parameters.scala:684:54, :686:26]
assign c_a_5_bits_size = c_a_bits_a_5_size; // @[Edges.scala:480:17]
assign c_a_5_bits_source = c_a_bits_a_5_source; // @[Edges.scala:480:17]
assign c_a_5_bits_address = c_a_bits_a_5_address; // @[Edges.scala:480:17]
wire [7:0] _c_a_bits_a_mask_T_5; // @[Misc.scala:222:10]
assign c_a_5_bits_mask = c_a_bits_a_5_mask; // @[Edges.scala:480:17]
assign c_a_5_bits_data = c_a_bits_a_5_data; // @[Edges.scala:480:17]
assign c_a_5_bits_corrupt = c_a_bits_a_5_corrupt; // @[Edges.scala:480:17]
wire [1:0] c_a_bits_a_mask_sizeOH_shiftAmount_5 = _c_a_bits_a_mask_sizeOH_T_15[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _c_a_bits_a_mask_sizeOH_T_16 = 4'h1 << c_a_bits_a_mask_sizeOH_shiftAmount_5; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _c_a_bits_a_mask_sizeOH_T_17 = _c_a_bits_a_mask_sizeOH_T_16[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] c_a_bits_a_mask_sizeOH_5 = {_c_a_bits_a_mask_sizeOH_T_17[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire c_a_bits_a_mask_sub_sub_sub_0_1_5 = nodeIn_5_c_bits_size > 3'h2; // @[Misc.scala:206:21]
wire c_a_bits_a_mask_sub_sub_size_5 = c_a_bits_a_mask_sizeOH_5[2]; // @[Misc.scala:202:81, :209:26]
wire c_a_bits_a_mask_sub_sub_bit_5 = nodeIn_5_c_bits_address[2]; // @[Misc.scala:210:26]
wire c_a_bits_a_mask_sub_sub_1_2_5 = c_a_bits_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27]
wire c_a_bits_a_mask_sub_sub_nbit_5 = ~c_a_bits_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20]
wire c_a_bits_a_mask_sub_sub_0_2_5 = c_a_bits_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_sub_sub_acc_T_10 = c_a_bits_a_mask_sub_sub_size_5 & c_a_bits_a_mask_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_sub_0_1_5 = c_a_bits_a_mask_sub_sub_sub_0_1_5 | _c_a_bits_a_mask_sub_sub_acc_T_10; // @[Misc.scala:206:21, :215:{29,38}]
wire _c_a_bits_a_mask_sub_sub_acc_T_11 = c_a_bits_a_mask_sub_sub_size_5 & c_a_bits_a_mask_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_sub_1_1_5 = c_a_bits_a_mask_sub_sub_sub_0_1_5 | _c_a_bits_a_mask_sub_sub_acc_T_11; // @[Misc.scala:206:21, :215:{29,38}]
wire c_a_bits_a_mask_sub_size_5 = c_a_bits_a_mask_sizeOH_5[1]; // @[Misc.scala:202:81, :209:26]
wire c_a_bits_a_mask_sub_bit_5 = nodeIn_5_c_bits_address[1]; // @[Misc.scala:210:26]
wire c_a_bits_a_mask_sub_nbit_5 = ~c_a_bits_a_mask_sub_bit_5; // @[Misc.scala:210:26, :211:20]
wire c_a_bits_a_mask_sub_0_2_5 = c_a_bits_a_mask_sub_sub_0_2_5 & c_a_bits_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_20 = c_a_bits_a_mask_sub_size_5 & c_a_bits_a_mask_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_0_1_5 = c_a_bits_a_mask_sub_sub_0_1_5 | _c_a_bits_a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_sub_1_2_5 = c_a_bits_a_mask_sub_sub_0_2_5 & c_a_bits_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_21 = c_a_bits_a_mask_sub_size_5 & c_a_bits_a_mask_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_1_1_5 = c_a_bits_a_mask_sub_sub_0_1_5 | _c_a_bits_a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_sub_2_2_5 = c_a_bits_a_mask_sub_sub_1_2_5 & c_a_bits_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_22 = c_a_bits_a_mask_sub_size_5 & c_a_bits_a_mask_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_2_1_5 = c_a_bits_a_mask_sub_sub_1_1_5 | _c_a_bits_a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_sub_3_2_5 = c_a_bits_a_mask_sub_sub_1_2_5 & c_a_bits_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_23 = c_a_bits_a_mask_sub_size_5 & c_a_bits_a_mask_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_3_1_5 = c_a_bits_a_mask_sub_sub_1_1_5 | _c_a_bits_a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_size_5 = c_a_bits_a_mask_sizeOH_5[0]; // @[Misc.scala:202:81, :209:26]
wire c_a_bits_a_mask_bit_5 = nodeIn_5_c_bits_address[0]; // @[Misc.scala:210:26]
wire c_a_bits_a_mask_nbit_5 = ~c_a_bits_a_mask_bit_5; // @[Misc.scala:210:26, :211:20]
wire c_a_bits_a_mask_eq_40 = c_a_bits_a_mask_sub_0_2_5 & c_a_bits_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_40 = c_a_bits_a_mask_size_5 & c_a_bits_a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_40 = c_a_bits_a_mask_sub_0_1_5 | _c_a_bits_a_mask_acc_T_40; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_41 = c_a_bits_a_mask_sub_0_2_5 & c_a_bits_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_41 = c_a_bits_a_mask_size_5 & c_a_bits_a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_41 = c_a_bits_a_mask_sub_0_1_5 | _c_a_bits_a_mask_acc_T_41; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_42 = c_a_bits_a_mask_sub_1_2_5 & c_a_bits_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_42 = c_a_bits_a_mask_size_5 & c_a_bits_a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_42 = c_a_bits_a_mask_sub_1_1_5 | _c_a_bits_a_mask_acc_T_42; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_43 = c_a_bits_a_mask_sub_1_2_5 & c_a_bits_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_43 = c_a_bits_a_mask_size_5 & c_a_bits_a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_43 = c_a_bits_a_mask_sub_1_1_5 | _c_a_bits_a_mask_acc_T_43; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_44 = c_a_bits_a_mask_sub_2_2_5 & c_a_bits_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_44 = c_a_bits_a_mask_size_5 & c_a_bits_a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_44 = c_a_bits_a_mask_sub_2_1_5 | _c_a_bits_a_mask_acc_T_44; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_45 = c_a_bits_a_mask_sub_2_2_5 & c_a_bits_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_45 = c_a_bits_a_mask_size_5 & c_a_bits_a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_45 = c_a_bits_a_mask_sub_2_1_5 | _c_a_bits_a_mask_acc_T_45; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_46 = c_a_bits_a_mask_sub_3_2_5 & c_a_bits_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_46 = c_a_bits_a_mask_size_5 & c_a_bits_a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_46 = c_a_bits_a_mask_sub_3_1_5 | _c_a_bits_a_mask_acc_T_46; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_47 = c_a_bits_a_mask_sub_3_2_5 & c_a_bits_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_47 = c_a_bits_a_mask_size_5 & c_a_bits_a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_47 = c_a_bits_a_mask_sub_3_1_5 | _c_a_bits_a_mask_acc_T_47; // @[Misc.scala:215:{29,38}]
wire [1:0] c_a_bits_a_mask_lo_lo_5 = {c_a_bits_a_mask_acc_41, c_a_bits_a_mask_acc_40}; // @[Misc.scala:215:29, :222:10]
wire [1:0] c_a_bits_a_mask_lo_hi_5 = {c_a_bits_a_mask_acc_43, c_a_bits_a_mask_acc_42}; // @[Misc.scala:215:29, :222:10]
wire [3:0] c_a_bits_a_mask_lo_5 = {c_a_bits_a_mask_lo_hi_5, c_a_bits_a_mask_lo_lo_5}; // @[Misc.scala:222:10]
wire [1:0] c_a_bits_a_mask_hi_lo_5 = {c_a_bits_a_mask_acc_45, c_a_bits_a_mask_acc_44}; // @[Misc.scala:215:29, :222:10]
wire [1:0] c_a_bits_a_mask_hi_hi_5 = {c_a_bits_a_mask_acc_47, c_a_bits_a_mask_acc_46}; // @[Misc.scala:215:29, :222:10]
wire [3:0] c_a_bits_a_mask_hi_5 = {c_a_bits_a_mask_hi_hi_5, c_a_bits_a_mask_hi_lo_5}; // @[Misc.scala:222:10]
assign _c_a_bits_a_mask_T_5 = {c_a_bits_a_mask_hi_5, c_a_bits_a_mask_lo_5}; // @[Misc.scala:222:10]
assign c_a_bits_a_5_mask = _c_a_bits_a_mask_T_5; // @[Misc.scala:222:10]
wire _c_d_valid_T_11; // @[CacheCork.scala:113:33]
wire [2:0] c_d_5_bits_size; // @[CacheCork.scala:112:23]
wire [3:0] c_d_5_bits_source; // @[CacheCork.scala:112:23]
wire c_d_5_ready; // @[CacheCork.scala:112:23]
wire c_d_5_valid; // @[CacheCork.scala:112:23]
wire _T_334 = nodeIn_5_c_bits_opcode == 3'h6; // @[CacheCork.scala:113:53]
wire _c_d_valid_T_10; // @[CacheCork.scala:113:53]
assign _c_d_valid_T_10 = _T_334; // @[CacheCork.scala:113:53]
wire _nodeIn_c_ready_T_10; // @[CacheCork.scala:117:44]
assign _nodeIn_c_ready_T_10 = _T_334; // @[CacheCork.scala:113:53, :117:44]
assign _c_d_valid_T_11 = nodeIn_5_c_valid & _c_d_valid_T_10; // @[CacheCork.scala:113:{33,53}]
assign c_d_5_valid = _c_d_valid_T_11; // @[CacheCork.scala:112:23, :113:33]
assign c_d_5_bits_size = c_d_bits_d_5_size; // @[Edges.scala:677:17]
assign c_d_5_bits_source = c_d_bits_d_5_source; // @[Edges.scala:677:17]
assign _nodeIn_c_ready_T_11 = _nodeIn_c_ready_T_10 ? c_d_5_ready : c_a_5_ready; // @[CacheCork.scala:101:23, :112:23, :117:{26,44}]
assign nodeIn_5_c_ready = _nodeIn_c_ready_T_11; // @[CacheCork.scala:117:26]
wire _in_d_ready_T_29; // @[CacheCork.scala:136:34]
wire _in_d_valid_T_47; // @[Arbiter.scala:96:24]
wire [2:0] _in_d_bits_WIRE_55_opcode; // @[Mux.scala:30:73]
assign nodeIn_5_d_bits_opcode = in_d_5_bits_opcode; // @[CacheCork.scala:131:24]
wire [1:0] _in_d_bits_WIRE_55_param; // @[Mux.scala:30:73]
assign nodeIn_5_d_bits_param = in_d_5_bits_param; // @[CacheCork.scala:131:24]
wire [2:0] _in_d_bits_WIRE_55_size; // @[Mux.scala:30:73]
assign nodeIn_5_d_bits_size = in_d_5_bits_size; // @[CacheCork.scala:131:24]
wire [3:0] _in_d_bits_WIRE_55_source; // @[Mux.scala:30:73]
assign nodeIn_5_d_bits_source = in_d_5_bits_source; // @[CacheCork.scala:131:24]
wire [2:0] _in_d_bits_WIRE_55_sink; // @[Mux.scala:30:73]
wire _in_d_bits_WIRE_55_denied; // @[Mux.scala:30:73]
assign nodeIn_5_d_bits_denied = in_d_5_bits_denied; // @[CacheCork.scala:131:24]
wire [63:0] _in_d_bits_WIRE_55_data; // @[Mux.scala:30:73]
assign nodeIn_5_d_bits_data = in_d_5_bits_data; // @[CacheCork.scala:131:24]
wire _in_d_bits_WIRE_55_corrupt; // @[Mux.scala:30:73]
assign nodeIn_5_d_bits_corrupt = in_d_5_bits_corrupt; // @[CacheCork.scala:131:24]
wire [2:0] in_d_5_bits_sink; // @[CacheCork.scala:131:24]
wire in_d_5_ready; // @[CacheCork.scala:131:24]
wire in_d_5_valid; // @[CacheCork.scala:131:24]
wire _GEN_10 = in_d_5_ready & in_d_5_valid; // @[Decoupled.scala:51:35]
wire _d_first_T_5; // @[Decoupled.scala:51:35]
assign _d_first_T_5 = _GEN_10; // @[Decoupled.scala:51:35]
wire _beatsLeft_T_44; // @[Decoupled.scala:51:35]
assign _beatsLeft_T_44 = _GEN_10; // @[Decoupled.scala:51:35]
wire [12:0] _d_first_beats1_decode_T_15 = 13'h3F << in_d_5_bits_size; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_16 = _d_first_beats1_decode_T_15[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_17 = ~_d_first_beats1_decode_T_16; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_5 = _d_first_beats1_decode_T_17[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata_5 = in_d_5_bits_opcode[0]; // @[Edges.scala:106:36]
wire [2:0] d_first_beats1_5 = d_first_beats1_opdata_5 ? d_first_beats1_decode_5 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_5; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_5 = {1'h0, d_first_counter_5} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_5 = _d_first_counter1_T_5[2:0]; // @[Edges.scala:230:28]
wire d_first_5 = d_first_counter_5 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_10 = d_first_counter_5 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_11 = d_first_beats1_5 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_5 = _d_first_last_T_10 | _d_first_last_T_11; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_5 = d_first_last_5 & _d_first_T_5; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_5 = ~d_first_counter1_5; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_5 = d_first_beats1_5 & _d_first_count_T_5; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_5 = d_first_5 ? d_first_beats1_5 : d_first_counter1_5; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _d_grant_T_10 = in_d_5_bits_opcode == 3'h5; // @[CacheCork.scala:131:24, :133:40]
wire _d_grant_T_11 = in_d_5_bits_opcode == 3'h4; // @[CacheCork.scala:131:24, :133:74]
wire d_grant_5 = _d_grant_T_10 | _d_grant_T_11; // @[CacheCork.scala:133:{40,54,74}]
wire _pool_io_alloc_ready_T_15 = nodeIn_5_d_ready & nodeIn_5_d_valid; // @[Decoupled.scala:51:35]
wire _pool_io_alloc_ready_T_16 = _pool_io_alloc_ready_T_15 & d_first_5; // @[Decoupled.scala:51:35]
wire _pool_io_alloc_ready_T_17 = _pool_io_alloc_ready_T_16 & d_grant_5; // @[CacheCork.scala:133:54, :134:{42,53}]
wire _nodeIn_d_valid_T_25 = ~d_first_5; // @[Edges.scala:231:25]
wire _nodeIn_d_valid_T_26 = _pool_5_io_alloc_valid | _nodeIn_d_valid_T_25; // @[CacheCork.scala:127:26, :135:{58,61}]
wire _nodeIn_d_valid_T_27 = ~d_grant_5; // @[CacheCork.scala:133:54, :135:73]
wire _nodeIn_d_valid_T_28 = _nodeIn_d_valid_T_26 | _nodeIn_d_valid_T_27; // @[CacheCork.scala:135:{58,70,73}]
assign _nodeIn_d_valid_T_29 = in_d_5_valid & _nodeIn_d_valid_T_28; // @[CacheCork.scala:131:24, :135:{34,70}]
assign nodeIn_5_d_valid = _nodeIn_d_valid_T_29; // @[CacheCork.scala:135:34]
wire _in_d_ready_T_25 = ~d_first_5; // @[Edges.scala:231:25]
wire _in_d_ready_T_26 = _pool_5_io_alloc_valid | _in_d_ready_T_25; // @[CacheCork.scala:127:26, :136:{58,61}]
wire _in_d_ready_T_27 = ~d_grant_5; // @[CacheCork.scala:133:54, :135:73, :136:73]
wire _in_d_ready_T_28 = _in_d_ready_T_26 | _in_d_ready_T_27; // @[CacheCork.scala:136:{58,70,73}]
assign _in_d_ready_T_29 = nodeIn_5_d_ready & _in_d_ready_T_28; // @[CacheCork.scala:136:{34,70}]
assign in_d_5_ready = _in_d_ready_T_29; // @[CacheCork.scala:131:24, :136:34]
reg [2:0] nodeIn_d_bits_sink_r_5; // @[package.scala:88:63]
assign _nodeIn_d_bits_sink_T_5 = d_first_5 ? _pool_5_io_alloc_bits : nodeIn_d_bits_sink_r_5; // @[package.scala:88:{42,63}]
assign nodeIn_5_d_bits_sink = _nodeIn_d_bits_sink_T_5; // @[package.scala:88:42]
wire _d_d_ready_T_5; // @[Arbiter.scala:94:31]
assign x1_nodeOut_4_d_ready = d_d_5_ready; // @[CacheCork.scala:141:23]
wire [3:0] _d_d_bits_source_T_5; // @[CacheCork.scala:143:46]
wire [2:0] d_d_5_bits_opcode; // @[CacheCork.scala:141:23]
wire [1:0] d_d_5_bits_param; // @[CacheCork.scala:141:23]
wire [3:0] d_d_5_bits_source; // @[CacheCork.scala:141:23]
wire [2:0] d_d_5_bits_sink; // @[CacheCork.scala:141:23]
assign d_d_5_bits_sink = {2'h0, x1_nodeOut_4_d_bits_sink}; // @[CacheCork.scala:141:23, :142:13]
assign _d_d_bits_source_T_5 = x1_nodeOut_4_d_bits_source[4:1]; // @[CacheCork.scala:143:46]
assign d_d_5_bits_source = _d_d_bits_source_T_5; // @[CacheCork.scala:141:23, :143:46]
wire [32:0] _aWOk_T_26 = {1'h0, _aWOk_T_25}; // @[Parameters.scala:137:{31,41}]
wire _bypass_T_11 = nodeIn_5_a_bits_source == d_d_5_bits_source; // @[CacheCork.scala:141:23, :150:91]
reg dWHeld_r_5; // @[package.scala:88:63]
wire dWHeld_5 = d_first_5 ? _dWHeld_T_5 : dWHeld_r_5; // @[package.scala:88:{42,63}]
wire _T_348 = x1_nodeOut_4_d_bits_opcode == 3'h1 & x1_nodeOut_4_d_bits_source[0]; // @[CacheCork.scala:162:{33,51,71}]
wire [1:0] _d_d_bits_param_T_5 = {1'h0, ~dWHeld_5}; // @[package.scala:88:42]
assign d_d_5_bits_param = _T_348 ? _d_d_bits_param_T_5 : x1_nodeOut_4_d_bits_param; // @[CacheCork.scala:141:23, :142:13, :162:{51,76}, :164:{26,32}]
assign d_d_5_bits_opcode = x1_nodeOut_4_d_bits_opcode == 3'h0 & ~(x1_nodeOut_4_d_bits_source[0]) ? 3'h6 : _T_348 ? 3'h5 : x1_nodeOut_4_d_bits_opcode; // @[CacheCork.scala:141:23, :142:13, :162:{51,71,76}, :163:27, :166:{33,47,50,73}, :167:27]
wire [12:0] _decode_T_45 = 13'h3F << c_a_5_bits_size; // @[package.scala:243:71]
wire [5:0] _decode_T_46 = _decode_T_45[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _decode_T_47 = ~_decode_T_46; // @[package.scala:243:{46,76}]
wire [2:0] decode_15 = _decode_T_47[5:3]; // @[package.scala:243:46]
wire [12:0] _decode_T_48 = 13'h3F << a_a_5_bits_size; // @[package.scala:243:71]
wire [5:0] _decode_T_49 = _decode_T_48[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _decode_T_50 = ~_decode_T_49; // @[package.scala:243:{46,76}]
wire [2:0] decode_16 = _decode_T_50[5:3]; // @[package.scala:243:46]
wire _opdata_T_11 = a_a_5_bits_opcode[2]; // @[Edges.scala:92:37]
wire opdata_16 = ~_opdata_T_11; // @[Edges.scala:92:{28,37}]
reg [2:0] beatsLeft_10; // @[Arbiter.scala:60:30]
wire idle_10 = beatsLeft_10 == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_10 = idle_10 & x1_nodeOut_4_a_ready; // @[Arbiter.scala:61:28, :62:24]
wire [1:0] _readys_T_120 = {a_a_5_valid, c_a_5_valid}; // @[CacheCork.scala:74:23, :101:23]
wire [2:0] _readys_T_121 = {_readys_T_120, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_T_122 = _readys_T_121[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_T_123 = _readys_T_120 | _readys_T_122; // @[package.scala:253:{43,53}]
wire [1:0] _readys_T_124 = _readys_T_123; // @[package.scala:253:43, :254:17]
wire [2:0] _readys_T_125 = {_readys_T_124, 1'h0}; // @[package.scala:254:17]
wire [1:0] _readys_T_126 = _readys_T_125[1:0]; // @[Arbiter.scala:16:{78,83}]
wire [1:0] _readys_T_127 = ~_readys_T_126; // @[Arbiter.scala:16:{61,83}]
wire _readys_T_128 = _readys_T_127[0]; // @[Arbiter.scala:16:61, :68:76]
wire readys_10_0 = _readys_T_128; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_129 = _readys_T_127[1]; // @[Arbiter.scala:16:61, :68:76]
wire readys_10_1 = _readys_T_129; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_25 = readys_10_0 & c_a_5_valid; // @[CacheCork.scala:101:23]
wire winner_10_0 = _winner_T_25; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_26 = readys_10_1 & a_a_5_valid; // @[CacheCork.scala:74:23]
wire winner_10_1 = _winner_T_26; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_10 = winner_10_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_10 = prefixOR_1_10 | winner_10_1; // @[Arbiter.scala:71:27, :76:48]
wire _nodeOut_a_valid_T_25 = c_a_5_valid | a_a_5_valid; // @[CacheCork.scala:74:23, :101:23]
wire [2:0] maskedBeats_0_10 = winner_10_0 ? decode_15 : 3'h0; // @[Edges.scala:220:59, :221:14]
wire [2:0] maskedBeats_1_10 = winner_10_1 & opdata_16 ? decode_16 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [2:0] initBeats_10 = maskedBeats_0_10 | maskedBeats_1_10; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_40 = x1_nodeOut_4_a_ready & x1_nodeOut_4_a_valid; // @[Decoupled.scala:51:35]
wire [3:0] _beatsLeft_T_41 = {1'h0, beatsLeft_10} - {3'h0, _beatsLeft_T_40}; // @[Decoupled.scala:51:35]
wire [2:0] _beatsLeft_T_42 = _beatsLeft_T_41[2:0]; // @[Arbiter.scala:85:52]
wire [2:0] _beatsLeft_T_43 = latch_10 ? initBeats_10 : _beatsLeft_T_42; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_10_0; // @[Arbiter.scala:88:26]
reg state_10_1; // @[Arbiter.scala:88:26]
wire muxState_10_0 = idle_10 ? winner_10_0 : state_10_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_10_1 = idle_10 ? winner_10_1 : state_10_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_10_0 = idle_10 ? readys_10_0 : state_10_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_10_1 = idle_10 ? readys_10_1 : state_10_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _c_a_ready_T_5 = x1_nodeOut_4_a_ready & allowed_10_0; // @[Arbiter.scala:92:24, :94:31]
assign c_a_5_ready = _c_a_ready_T_5; // @[CacheCork.scala:101:23]
assign _a_a_ready_T_5 = x1_nodeOut_4_a_ready & allowed_10_1; // @[Arbiter.scala:92:24, :94:31]
assign a_a_5_ready = _a_a_ready_T_5; // @[CacheCork.scala:74:23]
wire _nodeOut_a_valid_T_26 = state_10_0 & c_a_5_valid; // @[Mux.scala:30:73]
wire _nodeOut_a_valid_T_27 = state_10_1 & a_a_5_valid; // @[Mux.scala:30:73]
wire _nodeOut_a_valid_T_28 = _nodeOut_a_valid_T_26 | _nodeOut_a_valid_T_27; // @[Mux.scala:30:73]
wire _nodeOut_a_valid_WIRE_5 = _nodeOut_a_valid_T_28; // @[Mux.scala:30:73]
assign _nodeOut_a_valid_T_29 = idle_10 ? _nodeOut_a_valid_T_25 : _nodeOut_a_valid_WIRE_5; // @[Mux.scala:30:73]
assign x1_nodeOut_4_a_valid = _nodeOut_a_valid_T_29; // @[Arbiter.scala:96:24]
wire [2:0] _nodeOut_a_bits_WIRE_65; // @[Mux.scala:30:73]
assign x1_nodeOut_4_a_bits_opcode = _nodeOut_a_bits_WIRE_55_opcode; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_WIRE_64; // @[Mux.scala:30:73]
assign x1_nodeOut_4_a_bits_param = _nodeOut_a_bits_WIRE_55_param; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_WIRE_63; // @[Mux.scala:30:73]
assign x1_nodeOut_4_a_bits_size = _nodeOut_a_bits_WIRE_55_size; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_WIRE_62; // @[Mux.scala:30:73]
assign x1_nodeOut_4_a_bits_source = _nodeOut_a_bits_WIRE_55_source; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_WIRE_61; // @[Mux.scala:30:73]
assign x1_nodeOut_4_a_bits_address = _nodeOut_a_bits_WIRE_55_address; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_WIRE_58; // @[Mux.scala:30:73]
assign x1_nodeOut_4_a_bits_mask = _nodeOut_a_bits_WIRE_55_mask; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_WIRE_57; // @[Mux.scala:30:73]
assign x1_nodeOut_4_a_bits_data = _nodeOut_a_bits_WIRE_55_data; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_WIRE_56; // @[Mux.scala:30:73]
assign x1_nodeOut_4_a_bits_corrupt = _nodeOut_a_bits_WIRE_55_corrupt; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T_120 = muxState_10_0 & c_a_5_bits_corrupt; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T_121 = muxState_10_1 & a_a_5_bits_corrupt; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T_122 = _nodeOut_a_bits_T_120 | _nodeOut_a_bits_T_121; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_56 = _nodeOut_a_bits_T_122; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_55_corrupt = _nodeOut_a_bits_WIRE_56; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_T_123 = muxState_10_0 ? c_a_5_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_T_124 = muxState_10_1 ? a_a_5_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_T_125 = _nodeOut_a_bits_T_123 | _nodeOut_a_bits_T_124; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_57 = _nodeOut_a_bits_T_125; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_55_data = _nodeOut_a_bits_WIRE_57; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_T_126 = muxState_10_0 ? c_a_5_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_T_127 = muxState_10_1 ? a_a_5_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_T_128 = _nodeOut_a_bits_T_126 | _nodeOut_a_bits_T_127; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_58 = _nodeOut_a_bits_T_128; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_55_mask = _nodeOut_a_bits_WIRE_58; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_T_129 = muxState_10_0 ? c_a_5_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_T_130 = muxState_10_1 ? a_a_5_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_T_131 = _nodeOut_a_bits_T_129 | _nodeOut_a_bits_T_130; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_61 = _nodeOut_a_bits_T_131; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_55_address = _nodeOut_a_bits_WIRE_61; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_T_132 = muxState_10_0 ? c_a_5_bits_source : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_T_133 = muxState_10_1 ? a_a_5_bits_source : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_T_134 = _nodeOut_a_bits_T_132 | _nodeOut_a_bits_T_133; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_62 = _nodeOut_a_bits_T_134; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_55_source = _nodeOut_a_bits_WIRE_62; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_135 = muxState_10_0 ? c_a_5_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_136 = muxState_10_1 ? a_a_5_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_137 = _nodeOut_a_bits_T_135 | _nodeOut_a_bits_T_136; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_63 = _nodeOut_a_bits_T_137; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_55_size = _nodeOut_a_bits_WIRE_63; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_139 = muxState_10_1 ? a_a_5_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_140 = _nodeOut_a_bits_T_139; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_64 = _nodeOut_a_bits_T_140; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_55_param = _nodeOut_a_bits_WIRE_64; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_142 = muxState_10_1 ? a_a_5_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_143 = _nodeOut_a_bits_T_142; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_65 = _nodeOut_a_bits_T_143; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_55_opcode = _nodeOut_a_bits_WIRE_65; // @[Mux.scala:30:73]
wire [12:0] _decode_T_51 = 13'h3F << d_d_5_bits_size; // @[package.scala:243:71]
wire [5:0] _decode_T_52 = _decode_T_51[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _decode_T_53 = ~_decode_T_52; // @[package.scala:243:{46,76}]
wire [2:0] decode_17 = _decode_T_53[5:3]; // @[package.scala:243:46]
wire opdata_17 = d_d_5_bits_opcode[0]; // @[Edges.scala:106:36]
reg [2:0] beatsLeft_11; // @[Arbiter.scala:60:30]
wire idle_11 = beatsLeft_11 == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_11 = idle_11 & in_d_5_ready; // @[CacheCork.scala:131:24]
wire [1:0] readys_hi_5 = {_q_11_io_deq_valid, _q_10_io_deq_valid}; // @[Decoupled.scala:362:21]
wire [2:0] _readys_T_130 = {readys_hi_5, d_d_5_valid}; // @[CacheCork.scala:141:23]
wire [3:0] _readys_T_131 = {_readys_T_130, 1'h0}; // @[package.scala:253:48]
wire [2:0] _readys_T_132 = _readys_T_131[2:0]; // @[package.scala:253:{48,53}]
wire [2:0] _readys_T_133 = _readys_T_130 | _readys_T_132; // @[package.scala:253:{43,53}]
wire [4:0] _readys_T_134 = {_readys_T_133, 2'h0}; // @[package.scala:253:{43,48}]
wire [2:0] _readys_T_135 = _readys_T_134[2:0]; // @[package.scala:253:{48,53}]
wire [2:0] _readys_T_136 = _readys_T_133 | _readys_T_135; // @[package.scala:253:{43,53}]
wire [2:0] _readys_T_137 = _readys_T_136; // @[package.scala:253:43, :254:17]
wire [3:0] _readys_T_138 = {_readys_T_137, 1'h0}; // @[package.scala:254:17]
wire [2:0] _readys_T_139 = _readys_T_138[2:0]; // @[Arbiter.scala:16:{78,83}]
wire [2:0] _readys_T_140 = ~_readys_T_139; // @[Arbiter.scala:16:{61,83}]
wire _readys_T_141 = _readys_T_140[0]; // @[Arbiter.scala:16:61, :68:76]
wire readys_11_0 = _readys_T_141; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_142 = _readys_T_140[1]; // @[Arbiter.scala:16:61, :68:76]
wire readys_11_1 = _readys_T_142; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_143 = _readys_T_140[2]; // @[Arbiter.scala:16:61, :68:76]
wire readys_11_2 = _readys_T_143; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_27 = readys_11_0 & d_d_5_valid; // @[CacheCork.scala:141:23]
wire winner_11_0 = _winner_T_27; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_28 = readys_11_1 & _q_10_io_deq_valid; // @[Decoupled.scala:362:21]
wire winner_11_1 = _winner_T_28; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_29 = readys_11_2 & _q_11_io_deq_valid; // @[Decoupled.scala:362:21]
wire winner_11_2 = _winner_T_29; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_11 = winner_11_0; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_2_5 = prefixOR_1_11 | winner_11_1; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_11 = prefixOR_2_5 | winner_11_2; // @[Arbiter.scala:71:27, :76:48]
wire _in_d_valid_T_40 = d_d_5_valid | _q_10_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] maskedBeats_0_11 = winner_11_0 & opdata_17 ? decode_17 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire [2:0] _initBeats_T_5 = maskedBeats_0_11; // @[Arbiter.scala:82:69, :84:44]
wire [2:0] initBeats_11 = _initBeats_T_5; // @[Arbiter.scala:84:44]
wire [3:0] _beatsLeft_T_45 = {1'h0, beatsLeft_11} - {3'h0, _beatsLeft_T_44}; // @[Decoupled.scala:51:35]
wire [2:0] _beatsLeft_T_46 = _beatsLeft_T_45[2:0]; // @[Arbiter.scala:85:52]
wire [2:0] _beatsLeft_T_47 = latch_11 ? initBeats_11 : _beatsLeft_T_46; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_11_0; // @[Arbiter.scala:88:26]
reg state_11_1; // @[Arbiter.scala:88:26]
reg state_11_2; // @[Arbiter.scala:88:26]
wire muxState_11_0 = idle_11 ? winner_11_0 : state_11_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_11_1 = idle_11 ? winner_11_1 : state_11_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_11_2 = idle_11 ? winner_11_2 : state_11_2; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_11_0 = idle_11 ? readys_11_0 : state_11_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_11_1 = idle_11 ? readys_11_1 : state_11_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_11_2 = idle_11 ? readys_11_2 : state_11_2; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _d_d_ready_T_5 = in_d_5_ready & allowed_11_0; // @[CacheCork.scala:131:24]
assign d_d_5_ready = _d_d_ready_T_5; // @[CacheCork.scala:141:23]
wire _q_io_deq_ready_T_10 = in_d_5_ready & allowed_11_1; // @[CacheCork.scala:131:24]
wire _q_io_deq_ready_T_11 = in_d_5_ready & allowed_11_2; // @[CacheCork.scala:131:24]
wire _in_d_valid_T_41 = _in_d_valid_T_40 | _q_11_io_deq_valid; // @[Decoupled.scala:362:21]
wire _in_d_valid_T_42 = state_11_0 & d_d_5_valid; // @[Mux.scala:30:73]
wire _in_d_valid_T_43 = state_11_1 & _q_10_io_deq_valid; // @[Mux.scala:30:73]
wire _in_d_valid_T_44 = state_11_2 & _q_11_io_deq_valid; // @[Mux.scala:30:73]
wire _in_d_valid_T_45 = _in_d_valid_T_42 | _in_d_valid_T_43; // @[Mux.scala:30:73]
wire _in_d_valid_T_46 = _in_d_valid_T_45 | _in_d_valid_T_44; // @[Mux.scala:30:73]
wire _in_d_valid_WIRE_5 = _in_d_valid_T_46; // @[Mux.scala:30:73]
assign _in_d_valid_T_47 = idle_11 ? _in_d_valid_T_41 : _in_d_valid_WIRE_5; // @[Mux.scala:30:73]
assign in_d_5_valid = _in_d_valid_T_47; // @[CacheCork.scala:131:24]
wire [2:0] _in_d_bits_WIRE_65; // @[Mux.scala:30:73]
assign in_d_5_bits_opcode = _in_d_bits_WIRE_55_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_WIRE_64; // @[Mux.scala:30:73]
assign in_d_5_bits_param = _in_d_bits_WIRE_55_param; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_WIRE_63; // @[Mux.scala:30:73]
assign in_d_5_bits_size = _in_d_bits_WIRE_55_size; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_WIRE_62; // @[Mux.scala:30:73]
assign in_d_5_bits_source = _in_d_bits_WIRE_55_source; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_WIRE_61; // @[Mux.scala:30:73]
assign in_d_5_bits_sink = _in_d_bits_WIRE_55_sink; // @[Mux.scala:30:73]
wire _in_d_bits_WIRE_60; // @[Mux.scala:30:73]
assign in_d_5_bits_denied = _in_d_bits_WIRE_55_denied; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_WIRE_57; // @[Mux.scala:30:73]
assign in_d_5_bits_data = _in_d_bits_WIRE_55_data; // @[Mux.scala:30:73]
wire _in_d_bits_WIRE_56; // @[Mux.scala:30:73]
assign in_d_5_bits_corrupt = _in_d_bits_WIRE_55_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_200 = muxState_11_0 & d_d_5_bits_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_201 = muxState_11_1 & _q_10_io_deq_bits_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_202 = muxState_11_2 & _q_11_io_deq_bits_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_203 = _in_d_bits_T_200 | _in_d_bits_T_201; // @[Mux.scala:30:73]
wire _in_d_bits_T_204 = _in_d_bits_T_203 | _in_d_bits_T_202; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_56 = _in_d_bits_T_204; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_55_corrupt = _in_d_bits_WIRE_56; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_205 = muxState_11_0 ? d_d_5_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_206 = muxState_11_1 ? _q_10_io_deq_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_207 = muxState_11_2 ? _q_11_io_deq_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_208 = _in_d_bits_T_205 | _in_d_bits_T_206; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_209 = _in_d_bits_T_208 | _in_d_bits_T_207; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_57 = _in_d_bits_T_209; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_55_data = _in_d_bits_WIRE_57; // @[Mux.scala:30:73]
wire _in_d_bits_T_210 = muxState_11_0 & d_d_5_bits_denied; // @[Mux.scala:30:73]
wire _in_d_bits_T_211 = muxState_11_1 & _q_10_io_deq_bits_denied; // @[Mux.scala:30:73]
wire _in_d_bits_T_212 = muxState_11_2 & _q_11_io_deq_bits_denied; // @[Mux.scala:30:73]
wire _in_d_bits_T_213 = _in_d_bits_T_210 | _in_d_bits_T_211; // @[Mux.scala:30:73]
wire _in_d_bits_T_214 = _in_d_bits_T_213 | _in_d_bits_T_212; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_60 = _in_d_bits_T_214; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_55_denied = _in_d_bits_WIRE_60; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_215 = muxState_11_0 ? d_d_5_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_216 = muxState_11_1 ? _q_10_io_deq_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_217 = muxState_11_2 ? _q_11_io_deq_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_218 = _in_d_bits_T_215 | _in_d_bits_T_216; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_219 = _in_d_bits_T_218 | _in_d_bits_T_217; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_61 = _in_d_bits_T_219; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_55_sink = _in_d_bits_WIRE_61; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_220 = muxState_11_0 ? d_d_5_bits_source : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_221 = muxState_11_1 ? _q_10_io_deq_bits_source : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_222 = muxState_11_2 ? _q_11_io_deq_bits_source : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_223 = _in_d_bits_T_220 | _in_d_bits_T_221; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_224 = _in_d_bits_T_223 | _in_d_bits_T_222; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_62 = _in_d_bits_T_224; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_55_source = _in_d_bits_WIRE_62; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_225 = muxState_11_0 ? d_d_5_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_226 = muxState_11_1 ? _q_10_io_deq_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_227 = muxState_11_2 ? _q_11_io_deq_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_228 = _in_d_bits_T_225 | _in_d_bits_T_226; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_229 = _in_d_bits_T_228 | _in_d_bits_T_227; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_63 = _in_d_bits_T_229; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_55_size = _in_d_bits_WIRE_63; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_230 = muxState_11_0 ? d_d_5_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_231 = muxState_11_1 ? _q_10_io_deq_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_232 = muxState_11_2 ? _q_11_io_deq_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_233 = _in_d_bits_T_230 | _in_d_bits_T_231; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_234 = _in_d_bits_T_233 | _in_d_bits_T_232; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_64 = _in_d_bits_T_234; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_55_param = _in_d_bits_WIRE_64; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_235 = muxState_11_0 ? d_d_5_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_236 = muxState_11_1 ? _q_10_io_deq_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_237 = muxState_11_2 ? _q_11_io_deq_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_238 = _in_d_bits_T_235 | _in_d_bits_T_236; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_239 = _in_d_bits_T_238 | _in_d_bits_T_237; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_65 = _in_d_bits_T_239; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_55_opcode = _in_d_bits_WIRE_65; // @[Mux.scala:30:73]
wire _a_a_ready_T_6; // @[Arbiter.scala:94:31]
wire _a_a_valid_T_13; // @[CacheCork.scala:81:33]
wire [2:0] a_a_6_bits_opcode; // @[CacheCork.scala:74:23]
wire [2:0] a_a_6_bits_param; // @[CacheCork.scala:74:23]
wire [4:0] a_a_6_bits_source; // @[CacheCork.scala:74:23]
wire a_a_6_ready; // @[CacheCork.scala:74:23]
wire a_a_6_valid; // @[CacheCork.scala:74:23]
wire _a_d_valid_T_6; // @[CacheCork.scala:93:33]
wire [2:0] a_d_6_bits_size; // @[CacheCork.scala:75:23]
wire [3:0] a_d_6_bits_source; // @[CacheCork.scala:75:23]
wire a_d_6_ready; // @[CacheCork.scala:75:23]
wire a_d_6_valid; // @[CacheCork.scala:75:23]
wire _isPut_T_12 = nodeIn_6_a_bits_opcode == 3'h0; // @[CacheCork.scala:76:38]
wire _isPut_T_13 = nodeIn_6_a_bits_opcode == 3'h1; // @[CacheCork.scala:76:74]
wire isPut_6 = _isPut_T_12 | _isPut_T_13; // @[CacheCork.scala:76:{38,54,74}]
wire _a_a_bits_source_T_31 = isPut_6; // @[CacheCork.scala:76:54, :83:55]
wire _toD_T_24 = nodeIn_6_a_bits_opcode == 3'h6; // @[CacheCork.scala:77:37]
wire _toD_T_25 = nodeIn_6_a_bits_param == 3'h2; // @[CacheCork.scala:77:73]
wire _toD_T_26 = _toD_T_24 & _toD_T_25; // @[CacheCork.scala:77:{37,54,73}]
wire _toD_T_27 = &nodeIn_6_a_bits_opcode; // @[CacheCork.scala:78:37]
wire toD_6 = _toD_T_26 | _toD_T_27; // @[CacheCork.scala:77:{54,97}, :78:37]
assign _nodeIn_a_ready_T_6 = toD_6 ? a_d_6_ready : a_a_6_ready; // @[CacheCork.scala:74:23, :75:23, :77:97, :79:26]
assign nodeIn_6_a_ready = _nodeIn_a_ready_T_6; // @[CacheCork.scala:79:26]
wire _a_a_valid_T_12 = ~toD_6; // @[CacheCork.scala:77:97, :81:36]
assign _a_a_valid_T_13 = nodeIn_6_a_valid & _a_a_valid_T_12; // @[CacheCork.scala:81:{33,36}]
assign a_a_6_valid = _a_a_valid_T_13; // @[CacheCork.scala:74:23, :81:33]
wire [4:0] _GEN_11 = {nodeIn_6_a_bits_source, 1'h0}; // @[CacheCork.scala:83:45]
wire [4:0] _a_a_bits_source_T_30; // @[CacheCork.scala:83:45]
assign _a_a_bits_source_T_30 = _GEN_11; // @[CacheCork.scala:83:45]
wire [4:0] _a_a_bits_source_T_33; // @[CacheCork.scala:89:47]
assign _a_a_bits_source_T_33 = _GEN_11; // @[CacheCork.scala:83:45, :89:47]
wire [4:0] _a_a_bits_source_T_32 = {_a_a_bits_source_T_30[4:1], _a_a_bits_source_T_30[0] | _a_a_bits_source_T_31}; // @[CacheCork.scala:83:{45,50,55}]
wire _T_398 = _toD_T_24 | (&nodeIn_6_a_bits_opcode); // @[CacheCork.scala:77:37, :78:37, :86:49]
assign a_a_6_bits_opcode = _T_398 ? 3'h4 : nodeIn_6_a_bits_opcode; // @[CacheCork.scala:74:23, :82:18, :86:{49,86}, :87:27]
assign a_a_6_bits_param = _T_398 ? 3'h0 : nodeIn_6_a_bits_param; // @[CacheCork.scala:74:23, :82:18, :86:{49,86}, :88:27]
wire [4:0] _a_a_bits_source_T_34 = {_a_a_bits_source_T_33[4:1], 1'h1}; // @[CacheCork.scala:89:{47,52}]
assign a_a_6_bits_source = _T_398 ? _a_a_bits_source_T_34 : _a_a_bits_source_T_32; // @[CacheCork.scala:74:23, :83:{25,50}, :86:{49,86}, :89:{27,52}]
assign _a_d_valid_T_6 = nodeIn_6_a_valid & toD_6; // @[CacheCork.scala:77:97, :93:33]
assign a_d_6_valid = _a_d_valid_T_6; // @[CacheCork.scala:75:23, :93:33]
assign a_d_6_bits_size = a_d_bits_d_6_size; // @[Edges.scala:645:17]
assign a_d_6_bits_source = a_d_bits_d_6_source; // @[Edges.scala:645:17]
wire _c_a_ready_T_6; // @[Arbiter.scala:94:31]
wire _c_a_valid_T_13; // @[CacheCork.scala:102:33]
wire [4:0] c_a_bits_a_6_source; // @[Edges.scala:480:17]
wire [7:0] c_a_bits_a_6_mask; // @[Edges.scala:480:17]
wire [2:0] c_a_6_bits_size; // @[CacheCork.scala:101:23]
wire [4:0] c_a_6_bits_source; // @[CacheCork.scala:101:23]
wire [31:0] c_a_6_bits_address; // @[CacheCork.scala:101:23]
wire [7:0] c_a_6_bits_mask; // @[CacheCork.scala:101:23]
wire [63:0] c_a_6_bits_data; // @[CacheCork.scala:101:23]
wire c_a_6_bits_corrupt; // @[CacheCork.scala:101:23]
wire c_a_6_ready; // @[CacheCork.scala:101:23]
wire c_a_6_valid; // @[CacheCork.scala:101:23]
wire _c_a_valid_T_12 = &nodeIn_6_c_bits_opcode; // @[CacheCork.scala:102:53]
assign _c_a_valid_T_13 = nodeIn_6_c_valid & _c_a_valid_T_12; // @[CacheCork.scala:102:{33,53}]
assign c_a_6_valid = _c_a_valid_T_13; // @[CacheCork.scala:101:23, :102:33]
wire [4:0] _c_a_bits_T_6 = {nodeIn_6_c_bits_source, 1'h0}; // @[CacheCork.scala:104:41]
assign c_a_bits_a_6_source = _c_a_bits_T_6; // @[Edges.scala:480:17]
wire _c_a_bits_legal_T_61 = nodeIn_6_c_bits_size != 3'h7; // @[Parameters.scala:92:38]
wire _c_a_bits_legal_T_62 = _c_a_bits_legal_T_61; // @[Parameters.scala:92:{33,38}]
wire _c_a_bits_legal_T_63 = _c_a_bits_legal_T_62; // @[Parameters.scala:684:29]
wire _c_a_bits_legal_T_69 = _c_a_bits_legal_T_63; // @[Parameters.scala:684:{29,54}]
wire [32:0] _c_a_bits_legal_T_65 = {1'h0, _c_a_bits_legal_T_64}; // @[Parameters.scala:137:{31,41}]
wire c_a_bits_legal_6 = _c_a_bits_legal_T_69; // @[Parameters.scala:684:54, :686:26]
assign c_a_6_bits_size = c_a_bits_a_6_size; // @[Edges.scala:480:17]
assign c_a_6_bits_source = c_a_bits_a_6_source; // @[Edges.scala:480:17]
assign c_a_6_bits_address = c_a_bits_a_6_address; // @[Edges.scala:480:17]
wire [7:0] _c_a_bits_a_mask_T_6; // @[Misc.scala:222:10]
assign c_a_6_bits_mask = c_a_bits_a_6_mask; // @[Edges.scala:480:17]
assign c_a_6_bits_data = c_a_bits_a_6_data; // @[Edges.scala:480:17]
assign c_a_6_bits_corrupt = c_a_bits_a_6_corrupt; // @[Edges.scala:480:17]
wire [1:0] c_a_bits_a_mask_sizeOH_shiftAmount_6 = _c_a_bits_a_mask_sizeOH_T_18[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _c_a_bits_a_mask_sizeOH_T_19 = 4'h1 << c_a_bits_a_mask_sizeOH_shiftAmount_6; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _c_a_bits_a_mask_sizeOH_T_20 = _c_a_bits_a_mask_sizeOH_T_19[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] c_a_bits_a_mask_sizeOH_6 = {_c_a_bits_a_mask_sizeOH_T_20[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire c_a_bits_a_mask_sub_sub_sub_0_1_6 = nodeIn_6_c_bits_size > 3'h2; // @[Misc.scala:206:21]
wire c_a_bits_a_mask_sub_sub_size_6 = c_a_bits_a_mask_sizeOH_6[2]; // @[Misc.scala:202:81, :209:26]
wire c_a_bits_a_mask_sub_sub_bit_6 = nodeIn_6_c_bits_address[2]; // @[Misc.scala:210:26]
wire c_a_bits_a_mask_sub_sub_1_2_6 = c_a_bits_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27]
wire c_a_bits_a_mask_sub_sub_nbit_6 = ~c_a_bits_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20]
wire c_a_bits_a_mask_sub_sub_0_2_6 = c_a_bits_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_sub_sub_acc_T_12 = c_a_bits_a_mask_sub_sub_size_6 & c_a_bits_a_mask_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_sub_0_1_6 = c_a_bits_a_mask_sub_sub_sub_0_1_6 | _c_a_bits_a_mask_sub_sub_acc_T_12; // @[Misc.scala:206:21, :215:{29,38}]
wire _c_a_bits_a_mask_sub_sub_acc_T_13 = c_a_bits_a_mask_sub_sub_size_6 & c_a_bits_a_mask_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_sub_1_1_6 = c_a_bits_a_mask_sub_sub_sub_0_1_6 | _c_a_bits_a_mask_sub_sub_acc_T_13; // @[Misc.scala:206:21, :215:{29,38}]
wire c_a_bits_a_mask_sub_size_6 = c_a_bits_a_mask_sizeOH_6[1]; // @[Misc.scala:202:81, :209:26]
wire c_a_bits_a_mask_sub_bit_6 = nodeIn_6_c_bits_address[1]; // @[Misc.scala:210:26]
wire c_a_bits_a_mask_sub_nbit_6 = ~c_a_bits_a_mask_sub_bit_6; // @[Misc.scala:210:26, :211:20]
wire c_a_bits_a_mask_sub_0_2_6 = c_a_bits_a_mask_sub_sub_0_2_6 & c_a_bits_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_24 = c_a_bits_a_mask_sub_size_6 & c_a_bits_a_mask_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_0_1_6 = c_a_bits_a_mask_sub_sub_0_1_6 | _c_a_bits_a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_sub_1_2_6 = c_a_bits_a_mask_sub_sub_0_2_6 & c_a_bits_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_25 = c_a_bits_a_mask_sub_size_6 & c_a_bits_a_mask_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_1_1_6 = c_a_bits_a_mask_sub_sub_0_1_6 | _c_a_bits_a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_sub_2_2_6 = c_a_bits_a_mask_sub_sub_1_2_6 & c_a_bits_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_26 = c_a_bits_a_mask_sub_size_6 & c_a_bits_a_mask_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_2_1_6 = c_a_bits_a_mask_sub_sub_1_1_6 | _c_a_bits_a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_sub_3_2_6 = c_a_bits_a_mask_sub_sub_1_2_6 & c_a_bits_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_27 = c_a_bits_a_mask_sub_size_6 & c_a_bits_a_mask_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_3_1_6 = c_a_bits_a_mask_sub_sub_1_1_6 | _c_a_bits_a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_size_6 = c_a_bits_a_mask_sizeOH_6[0]; // @[Misc.scala:202:81, :209:26]
wire c_a_bits_a_mask_bit_6 = nodeIn_6_c_bits_address[0]; // @[Misc.scala:210:26]
wire c_a_bits_a_mask_nbit_6 = ~c_a_bits_a_mask_bit_6; // @[Misc.scala:210:26, :211:20]
wire c_a_bits_a_mask_eq_48 = c_a_bits_a_mask_sub_0_2_6 & c_a_bits_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_48 = c_a_bits_a_mask_size_6 & c_a_bits_a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_48 = c_a_bits_a_mask_sub_0_1_6 | _c_a_bits_a_mask_acc_T_48; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_49 = c_a_bits_a_mask_sub_0_2_6 & c_a_bits_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_49 = c_a_bits_a_mask_size_6 & c_a_bits_a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_49 = c_a_bits_a_mask_sub_0_1_6 | _c_a_bits_a_mask_acc_T_49; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_50 = c_a_bits_a_mask_sub_1_2_6 & c_a_bits_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_50 = c_a_bits_a_mask_size_6 & c_a_bits_a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_50 = c_a_bits_a_mask_sub_1_1_6 | _c_a_bits_a_mask_acc_T_50; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_51 = c_a_bits_a_mask_sub_1_2_6 & c_a_bits_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_51 = c_a_bits_a_mask_size_6 & c_a_bits_a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_51 = c_a_bits_a_mask_sub_1_1_6 | _c_a_bits_a_mask_acc_T_51; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_52 = c_a_bits_a_mask_sub_2_2_6 & c_a_bits_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_52 = c_a_bits_a_mask_size_6 & c_a_bits_a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_52 = c_a_bits_a_mask_sub_2_1_6 | _c_a_bits_a_mask_acc_T_52; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_53 = c_a_bits_a_mask_sub_2_2_6 & c_a_bits_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_53 = c_a_bits_a_mask_size_6 & c_a_bits_a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_53 = c_a_bits_a_mask_sub_2_1_6 | _c_a_bits_a_mask_acc_T_53; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_54 = c_a_bits_a_mask_sub_3_2_6 & c_a_bits_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_54 = c_a_bits_a_mask_size_6 & c_a_bits_a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_54 = c_a_bits_a_mask_sub_3_1_6 | _c_a_bits_a_mask_acc_T_54; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_55 = c_a_bits_a_mask_sub_3_2_6 & c_a_bits_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_55 = c_a_bits_a_mask_size_6 & c_a_bits_a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_55 = c_a_bits_a_mask_sub_3_1_6 | _c_a_bits_a_mask_acc_T_55; // @[Misc.scala:215:{29,38}]
wire [1:0] c_a_bits_a_mask_lo_lo_6 = {c_a_bits_a_mask_acc_49, c_a_bits_a_mask_acc_48}; // @[Misc.scala:215:29, :222:10]
wire [1:0] c_a_bits_a_mask_lo_hi_6 = {c_a_bits_a_mask_acc_51, c_a_bits_a_mask_acc_50}; // @[Misc.scala:215:29, :222:10]
wire [3:0] c_a_bits_a_mask_lo_6 = {c_a_bits_a_mask_lo_hi_6, c_a_bits_a_mask_lo_lo_6}; // @[Misc.scala:222:10]
wire [1:0] c_a_bits_a_mask_hi_lo_6 = {c_a_bits_a_mask_acc_53, c_a_bits_a_mask_acc_52}; // @[Misc.scala:215:29, :222:10]
wire [1:0] c_a_bits_a_mask_hi_hi_6 = {c_a_bits_a_mask_acc_55, c_a_bits_a_mask_acc_54}; // @[Misc.scala:215:29, :222:10]
wire [3:0] c_a_bits_a_mask_hi_6 = {c_a_bits_a_mask_hi_hi_6, c_a_bits_a_mask_hi_lo_6}; // @[Misc.scala:222:10]
assign _c_a_bits_a_mask_T_6 = {c_a_bits_a_mask_hi_6, c_a_bits_a_mask_lo_6}; // @[Misc.scala:222:10]
assign c_a_bits_a_6_mask = _c_a_bits_a_mask_T_6; // @[Misc.scala:222:10]
wire _c_d_valid_T_13; // @[CacheCork.scala:113:33]
wire [2:0] c_d_6_bits_size; // @[CacheCork.scala:112:23]
wire [3:0] c_d_6_bits_source; // @[CacheCork.scala:112:23]
wire c_d_6_ready; // @[CacheCork.scala:112:23]
wire c_d_6_valid; // @[CacheCork.scala:112:23]
wire _T_400 = nodeIn_6_c_bits_opcode == 3'h6; // @[CacheCork.scala:113:53]
wire _c_d_valid_T_12; // @[CacheCork.scala:113:53]
assign _c_d_valid_T_12 = _T_400; // @[CacheCork.scala:113:53]
wire _nodeIn_c_ready_T_12; // @[CacheCork.scala:117:44]
assign _nodeIn_c_ready_T_12 = _T_400; // @[CacheCork.scala:113:53, :117:44]
assign _c_d_valid_T_13 = nodeIn_6_c_valid & _c_d_valid_T_12; // @[CacheCork.scala:113:{33,53}]
assign c_d_6_valid = _c_d_valid_T_13; // @[CacheCork.scala:112:23, :113:33]
assign c_d_6_bits_size = c_d_bits_d_6_size; // @[Edges.scala:677:17]
assign c_d_6_bits_source = c_d_bits_d_6_source; // @[Edges.scala:677:17]
assign _nodeIn_c_ready_T_13 = _nodeIn_c_ready_T_12 ? c_d_6_ready : c_a_6_ready; // @[CacheCork.scala:101:23, :112:23, :117:{26,44}]
assign nodeIn_6_c_ready = _nodeIn_c_ready_T_13; // @[CacheCork.scala:117:26]
wire _in_d_ready_T_34; // @[CacheCork.scala:136:34]
wire _in_d_valid_T_55; // @[Arbiter.scala:96:24]
wire [2:0] _in_d_bits_WIRE_66_opcode; // @[Mux.scala:30:73]
assign nodeIn_6_d_bits_opcode = in_d_6_bits_opcode; // @[CacheCork.scala:131:24]
wire [1:0] _in_d_bits_WIRE_66_param; // @[Mux.scala:30:73]
assign nodeIn_6_d_bits_param = in_d_6_bits_param; // @[CacheCork.scala:131:24]
wire [2:0] _in_d_bits_WIRE_66_size; // @[Mux.scala:30:73]
assign nodeIn_6_d_bits_size = in_d_6_bits_size; // @[CacheCork.scala:131:24]
wire [3:0] _in_d_bits_WIRE_66_source; // @[Mux.scala:30:73]
assign nodeIn_6_d_bits_source = in_d_6_bits_source; // @[CacheCork.scala:131:24]
wire [2:0] _in_d_bits_WIRE_66_sink; // @[Mux.scala:30:73]
wire _in_d_bits_WIRE_66_denied; // @[Mux.scala:30:73]
assign nodeIn_6_d_bits_denied = in_d_6_bits_denied; // @[CacheCork.scala:131:24]
wire [63:0] _in_d_bits_WIRE_66_data; // @[Mux.scala:30:73]
assign nodeIn_6_d_bits_data = in_d_6_bits_data; // @[CacheCork.scala:131:24]
wire _in_d_bits_WIRE_66_corrupt; // @[Mux.scala:30:73]
assign nodeIn_6_d_bits_corrupt = in_d_6_bits_corrupt; // @[CacheCork.scala:131:24]
wire [2:0] in_d_6_bits_sink; // @[CacheCork.scala:131:24]
wire in_d_6_ready; // @[CacheCork.scala:131:24]
wire in_d_6_valid; // @[CacheCork.scala:131:24]
wire _GEN_12 = in_d_6_ready & in_d_6_valid; // @[Decoupled.scala:51:35]
wire _d_first_T_6; // @[Decoupled.scala:51:35]
assign _d_first_T_6 = _GEN_12; // @[Decoupled.scala:51:35]
wire _beatsLeft_T_52; // @[Decoupled.scala:51:35]
assign _beatsLeft_T_52 = _GEN_12; // @[Decoupled.scala:51:35]
wire [12:0] _d_first_beats1_decode_T_18 = 13'h3F << in_d_6_bits_size; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_19 = _d_first_beats1_decode_T_18[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_20 = ~_d_first_beats1_decode_T_19; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_6 = _d_first_beats1_decode_T_20[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata_6 = in_d_6_bits_opcode[0]; // @[Edges.scala:106:36]
wire [2:0] d_first_beats1_6 = d_first_beats1_opdata_6 ? d_first_beats1_decode_6 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_6; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_6 = {1'h0, d_first_counter_6} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_6 = _d_first_counter1_T_6[2:0]; // @[Edges.scala:230:28]
wire d_first_6 = d_first_counter_6 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_12 = d_first_counter_6 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_13 = d_first_beats1_6 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_6 = _d_first_last_T_12 | _d_first_last_T_13; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_6 = d_first_last_6 & _d_first_T_6; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_6 = ~d_first_counter1_6; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_6 = d_first_beats1_6 & _d_first_count_T_6; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_6 = d_first_6 ? d_first_beats1_6 : d_first_counter1_6; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _d_grant_T_12 = in_d_6_bits_opcode == 3'h5; // @[CacheCork.scala:131:24, :133:40]
wire _d_grant_T_13 = in_d_6_bits_opcode == 3'h4; // @[CacheCork.scala:131:24, :133:74]
wire d_grant_6 = _d_grant_T_12 | _d_grant_T_13; // @[CacheCork.scala:133:{40,54,74}]
wire _pool_io_alloc_ready_T_18 = nodeIn_6_d_ready & nodeIn_6_d_valid; // @[Decoupled.scala:51:35]
wire _pool_io_alloc_ready_T_19 = _pool_io_alloc_ready_T_18 & d_first_6; // @[Decoupled.scala:51:35]
wire _pool_io_alloc_ready_T_20 = _pool_io_alloc_ready_T_19 & d_grant_6; // @[CacheCork.scala:133:54, :134:{42,53}]
wire _nodeIn_d_valid_T_30 = ~d_first_6; // @[Edges.scala:231:25]
wire _nodeIn_d_valid_T_31 = _pool_6_io_alloc_valid | _nodeIn_d_valid_T_30; // @[CacheCork.scala:127:26, :135:{58,61}]
wire _nodeIn_d_valid_T_32 = ~d_grant_6; // @[CacheCork.scala:133:54, :135:73]
wire _nodeIn_d_valid_T_33 = _nodeIn_d_valid_T_31 | _nodeIn_d_valid_T_32; // @[CacheCork.scala:135:{58,70,73}]
assign _nodeIn_d_valid_T_34 = in_d_6_valid & _nodeIn_d_valid_T_33; // @[CacheCork.scala:131:24, :135:{34,70}]
assign nodeIn_6_d_valid = _nodeIn_d_valid_T_34; // @[CacheCork.scala:135:34]
wire _in_d_ready_T_30 = ~d_first_6; // @[Edges.scala:231:25]
wire _in_d_ready_T_31 = _pool_6_io_alloc_valid | _in_d_ready_T_30; // @[CacheCork.scala:127:26, :136:{58,61}]
wire _in_d_ready_T_32 = ~d_grant_6; // @[CacheCork.scala:133:54, :135:73, :136:73]
wire _in_d_ready_T_33 = _in_d_ready_T_31 | _in_d_ready_T_32; // @[CacheCork.scala:136:{58,70,73}]
assign _in_d_ready_T_34 = nodeIn_6_d_ready & _in_d_ready_T_33; // @[CacheCork.scala:136:{34,70}]
assign in_d_6_ready = _in_d_ready_T_34; // @[CacheCork.scala:131:24, :136:34]
reg [2:0] nodeIn_d_bits_sink_r_6; // @[package.scala:88:63]
assign _nodeIn_d_bits_sink_T_6 = d_first_6 ? _pool_6_io_alloc_bits : nodeIn_d_bits_sink_r_6; // @[package.scala:88:{42,63}]
assign nodeIn_6_d_bits_sink = _nodeIn_d_bits_sink_T_6; // @[package.scala:88:42]
wire _d_d_ready_T_6; // @[Arbiter.scala:94:31]
assign x1_nodeOut_5_d_ready = d_d_6_ready; // @[CacheCork.scala:141:23]
wire [3:0] _d_d_bits_source_T_6; // @[CacheCork.scala:143:46]
wire [2:0] d_d_6_bits_opcode; // @[CacheCork.scala:141:23]
wire [1:0] d_d_6_bits_param; // @[CacheCork.scala:141:23]
wire [3:0] d_d_6_bits_source; // @[CacheCork.scala:141:23]
wire [2:0] d_d_6_bits_sink; // @[CacheCork.scala:141:23]
assign d_d_6_bits_sink = {2'h0, x1_nodeOut_5_d_bits_sink}; // @[CacheCork.scala:141:23, :142:13]
assign _d_d_bits_source_T_6 = x1_nodeOut_5_d_bits_source[4:1]; // @[CacheCork.scala:143:46]
assign d_d_6_bits_source = _d_d_bits_source_T_6; // @[CacheCork.scala:141:23, :143:46]
wire [32:0] _aWOk_T_31 = {1'h0, _aWOk_T_30}; // @[Parameters.scala:137:{31,41}]
wire _bypass_T_13 = nodeIn_6_a_bits_source == d_d_6_bits_source; // @[CacheCork.scala:141:23, :150:91]
reg dWHeld_r_6; // @[package.scala:88:63]
wire dWHeld_6 = d_first_6 ? _dWHeld_T_6 : dWHeld_r_6; // @[package.scala:88:{42,63}]
wire _T_414 = x1_nodeOut_5_d_bits_opcode == 3'h1 & x1_nodeOut_5_d_bits_source[0]; // @[CacheCork.scala:162:{33,51,71}]
wire [1:0] _d_d_bits_param_T_6 = {1'h0, ~dWHeld_6}; // @[package.scala:88:42]
assign d_d_6_bits_param = _T_414 ? _d_d_bits_param_T_6 : x1_nodeOut_5_d_bits_param; // @[CacheCork.scala:141:23, :142:13, :162:{51,76}, :164:{26,32}]
assign d_d_6_bits_opcode = x1_nodeOut_5_d_bits_opcode == 3'h0 & ~(x1_nodeOut_5_d_bits_source[0]) ? 3'h6 : _T_414 ? 3'h5 : x1_nodeOut_5_d_bits_opcode; // @[CacheCork.scala:141:23, :142:13, :162:{51,71,76}, :163:27, :166:{33,47,50,73}, :167:27]
wire [12:0] _decode_T_54 = 13'h3F << c_a_6_bits_size; // @[package.scala:243:71]
wire [5:0] _decode_T_55 = _decode_T_54[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _decode_T_56 = ~_decode_T_55; // @[package.scala:243:{46,76}]
wire [2:0] decode_18 = _decode_T_56[5:3]; // @[package.scala:243:46]
wire [12:0] _decode_T_57 = 13'h3F << a_a_6_bits_size; // @[package.scala:243:71]
wire [5:0] _decode_T_58 = _decode_T_57[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _decode_T_59 = ~_decode_T_58; // @[package.scala:243:{46,76}]
wire [2:0] decode_19 = _decode_T_59[5:3]; // @[package.scala:243:46]
wire _opdata_T_13 = a_a_6_bits_opcode[2]; // @[Edges.scala:92:37]
wire opdata_19 = ~_opdata_T_13; // @[Edges.scala:92:{28,37}]
reg [2:0] beatsLeft_12; // @[Arbiter.scala:60:30]
wire idle_12 = beatsLeft_12 == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_12 = idle_12 & x1_nodeOut_5_a_ready; // @[Arbiter.scala:61:28, :62:24]
wire [1:0] _readys_T_144 = {a_a_6_valid, c_a_6_valid}; // @[CacheCork.scala:74:23, :101:23]
wire [2:0] _readys_T_145 = {_readys_T_144, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_T_146 = _readys_T_145[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_T_147 = _readys_T_144 | _readys_T_146; // @[package.scala:253:{43,53}]
wire [1:0] _readys_T_148 = _readys_T_147; // @[package.scala:253:43, :254:17]
wire [2:0] _readys_T_149 = {_readys_T_148, 1'h0}; // @[package.scala:254:17]
wire [1:0] _readys_T_150 = _readys_T_149[1:0]; // @[Arbiter.scala:16:{78,83}]
wire [1:0] _readys_T_151 = ~_readys_T_150; // @[Arbiter.scala:16:{61,83}]
wire _readys_T_152 = _readys_T_151[0]; // @[Arbiter.scala:16:61, :68:76]
wire readys_12_0 = _readys_T_152; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_153 = _readys_T_151[1]; // @[Arbiter.scala:16:61, :68:76]
wire readys_12_1 = _readys_T_153; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_30 = readys_12_0 & c_a_6_valid; // @[CacheCork.scala:101:23]
wire winner_12_0 = _winner_T_30; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_31 = readys_12_1 & a_a_6_valid; // @[CacheCork.scala:74:23]
wire winner_12_1 = _winner_T_31; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_12 = winner_12_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_12 = prefixOR_1_12 | winner_12_1; // @[Arbiter.scala:71:27, :76:48]
wire _nodeOut_a_valid_T_30 = c_a_6_valid | a_a_6_valid; // @[CacheCork.scala:74:23, :101:23]
wire [2:0] maskedBeats_0_12 = winner_12_0 ? decode_18 : 3'h0; // @[Edges.scala:220:59, :221:14]
wire [2:0] maskedBeats_1_12 = winner_12_1 & opdata_19 ? decode_19 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [2:0] initBeats_12 = maskedBeats_0_12 | maskedBeats_1_12; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_48 = x1_nodeOut_5_a_ready & x1_nodeOut_5_a_valid; // @[Decoupled.scala:51:35]
wire [3:0] _beatsLeft_T_49 = {1'h0, beatsLeft_12} - {3'h0, _beatsLeft_T_48}; // @[Decoupled.scala:51:35]
wire [2:0] _beatsLeft_T_50 = _beatsLeft_T_49[2:0]; // @[Arbiter.scala:85:52]
wire [2:0] _beatsLeft_T_51 = latch_12 ? initBeats_12 : _beatsLeft_T_50; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_12_0; // @[Arbiter.scala:88:26]
reg state_12_1; // @[Arbiter.scala:88:26]
wire muxState_12_0 = idle_12 ? winner_12_0 : state_12_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_12_1 = idle_12 ? winner_12_1 : state_12_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_12_0 = idle_12 ? readys_12_0 : state_12_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_12_1 = idle_12 ? readys_12_1 : state_12_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _c_a_ready_T_6 = x1_nodeOut_5_a_ready & allowed_12_0; // @[Arbiter.scala:92:24, :94:31]
assign c_a_6_ready = _c_a_ready_T_6; // @[CacheCork.scala:101:23]
assign _a_a_ready_T_6 = x1_nodeOut_5_a_ready & allowed_12_1; // @[Arbiter.scala:92:24, :94:31]
assign a_a_6_ready = _a_a_ready_T_6; // @[CacheCork.scala:74:23]
wire _nodeOut_a_valid_T_31 = state_12_0 & c_a_6_valid; // @[Mux.scala:30:73]
wire _nodeOut_a_valid_T_32 = state_12_1 & a_a_6_valid; // @[Mux.scala:30:73]
wire _nodeOut_a_valid_T_33 = _nodeOut_a_valid_T_31 | _nodeOut_a_valid_T_32; // @[Mux.scala:30:73]
wire _nodeOut_a_valid_WIRE_6 = _nodeOut_a_valid_T_33; // @[Mux.scala:30:73]
assign _nodeOut_a_valid_T_34 = idle_12 ? _nodeOut_a_valid_T_30 : _nodeOut_a_valid_WIRE_6; // @[Mux.scala:30:73]
assign x1_nodeOut_5_a_valid = _nodeOut_a_valid_T_34; // @[Arbiter.scala:96:24]
wire [2:0] _nodeOut_a_bits_WIRE_76; // @[Mux.scala:30:73]
assign x1_nodeOut_5_a_bits_opcode = _nodeOut_a_bits_WIRE_66_opcode; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_WIRE_75; // @[Mux.scala:30:73]
assign x1_nodeOut_5_a_bits_param = _nodeOut_a_bits_WIRE_66_param; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_WIRE_74; // @[Mux.scala:30:73]
assign x1_nodeOut_5_a_bits_size = _nodeOut_a_bits_WIRE_66_size; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_WIRE_73; // @[Mux.scala:30:73]
assign x1_nodeOut_5_a_bits_source = _nodeOut_a_bits_WIRE_66_source; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_WIRE_72; // @[Mux.scala:30:73]
assign x1_nodeOut_5_a_bits_address = _nodeOut_a_bits_WIRE_66_address; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_WIRE_69; // @[Mux.scala:30:73]
assign x1_nodeOut_5_a_bits_mask = _nodeOut_a_bits_WIRE_66_mask; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_WIRE_68; // @[Mux.scala:30:73]
assign x1_nodeOut_5_a_bits_data = _nodeOut_a_bits_WIRE_66_data; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_WIRE_67; // @[Mux.scala:30:73]
assign x1_nodeOut_5_a_bits_corrupt = _nodeOut_a_bits_WIRE_66_corrupt; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T_144 = muxState_12_0 & c_a_6_bits_corrupt; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T_145 = muxState_12_1 & a_a_6_bits_corrupt; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T_146 = _nodeOut_a_bits_T_144 | _nodeOut_a_bits_T_145; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_67 = _nodeOut_a_bits_T_146; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_66_corrupt = _nodeOut_a_bits_WIRE_67; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_T_147 = muxState_12_0 ? c_a_6_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_T_148 = muxState_12_1 ? a_a_6_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_T_149 = _nodeOut_a_bits_T_147 | _nodeOut_a_bits_T_148; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_68 = _nodeOut_a_bits_T_149; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_66_data = _nodeOut_a_bits_WIRE_68; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_T_150 = muxState_12_0 ? c_a_6_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_T_151 = muxState_12_1 ? a_a_6_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_T_152 = _nodeOut_a_bits_T_150 | _nodeOut_a_bits_T_151; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_69 = _nodeOut_a_bits_T_152; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_66_mask = _nodeOut_a_bits_WIRE_69; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_T_153 = muxState_12_0 ? c_a_6_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_T_154 = muxState_12_1 ? a_a_6_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_T_155 = _nodeOut_a_bits_T_153 | _nodeOut_a_bits_T_154; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_72 = _nodeOut_a_bits_T_155; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_66_address = _nodeOut_a_bits_WIRE_72; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_T_156 = muxState_12_0 ? c_a_6_bits_source : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_T_157 = muxState_12_1 ? a_a_6_bits_source : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_T_158 = _nodeOut_a_bits_T_156 | _nodeOut_a_bits_T_157; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_73 = _nodeOut_a_bits_T_158; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_66_source = _nodeOut_a_bits_WIRE_73; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_159 = muxState_12_0 ? c_a_6_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_160 = muxState_12_1 ? a_a_6_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_161 = _nodeOut_a_bits_T_159 | _nodeOut_a_bits_T_160; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_74 = _nodeOut_a_bits_T_161; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_66_size = _nodeOut_a_bits_WIRE_74; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_163 = muxState_12_1 ? a_a_6_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_164 = _nodeOut_a_bits_T_163; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_75 = _nodeOut_a_bits_T_164; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_66_param = _nodeOut_a_bits_WIRE_75; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_166 = muxState_12_1 ? a_a_6_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_167 = _nodeOut_a_bits_T_166; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_76 = _nodeOut_a_bits_T_167; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_66_opcode = _nodeOut_a_bits_WIRE_76; // @[Mux.scala:30:73]
wire [12:0] _decode_T_60 = 13'h3F << d_d_6_bits_size; // @[package.scala:243:71]
wire [5:0] _decode_T_61 = _decode_T_60[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _decode_T_62 = ~_decode_T_61; // @[package.scala:243:{46,76}]
wire [2:0] decode_20 = _decode_T_62[5:3]; // @[package.scala:243:46]
wire opdata_20 = d_d_6_bits_opcode[0]; // @[Edges.scala:106:36]
reg [2:0] beatsLeft_13; // @[Arbiter.scala:60:30]
wire idle_13 = beatsLeft_13 == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_13 = idle_13 & in_d_6_ready; // @[CacheCork.scala:131:24]
wire [1:0] readys_hi_6 = {_q_13_io_deq_valid, _q_12_io_deq_valid}; // @[Decoupled.scala:362:21]
wire [2:0] _readys_T_154 = {readys_hi_6, d_d_6_valid}; // @[CacheCork.scala:141:23]
wire [3:0] _readys_T_155 = {_readys_T_154, 1'h0}; // @[package.scala:253:48]
wire [2:0] _readys_T_156 = _readys_T_155[2:0]; // @[package.scala:253:{48,53}]
wire [2:0] _readys_T_157 = _readys_T_154 | _readys_T_156; // @[package.scala:253:{43,53}]
wire [4:0] _readys_T_158 = {_readys_T_157, 2'h0}; // @[package.scala:253:{43,48}]
wire [2:0] _readys_T_159 = _readys_T_158[2:0]; // @[package.scala:253:{48,53}]
wire [2:0] _readys_T_160 = _readys_T_157 | _readys_T_159; // @[package.scala:253:{43,53}]
wire [2:0] _readys_T_161 = _readys_T_160; // @[package.scala:253:43, :254:17]
wire [3:0] _readys_T_162 = {_readys_T_161, 1'h0}; // @[package.scala:254:17]
wire [2:0] _readys_T_163 = _readys_T_162[2:0]; // @[Arbiter.scala:16:{78,83}]
wire [2:0] _readys_T_164 = ~_readys_T_163; // @[Arbiter.scala:16:{61,83}]
wire _readys_T_165 = _readys_T_164[0]; // @[Arbiter.scala:16:61, :68:76]
wire readys_13_0 = _readys_T_165; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_166 = _readys_T_164[1]; // @[Arbiter.scala:16:61, :68:76]
wire readys_13_1 = _readys_T_166; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_167 = _readys_T_164[2]; // @[Arbiter.scala:16:61, :68:76]
wire readys_13_2 = _readys_T_167; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_32 = readys_13_0 & d_d_6_valid; // @[CacheCork.scala:141:23]
wire winner_13_0 = _winner_T_32; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_33 = readys_13_1 & _q_12_io_deq_valid; // @[Decoupled.scala:362:21]
wire winner_13_1 = _winner_T_33; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_34 = readys_13_2 & _q_13_io_deq_valid; // @[Decoupled.scala:362:21]
wire winner_13_2 = _winner_T_34; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_13 = winner_13_0; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_2_6 = prefixOR_1_13 | winner_13_1; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_13 = prefixOR_2_6 | winner_13_2; // @[Arbiter.scala:71:27, :76:48]
wire _in_d_valid_T_48 = d_d_6_valid | _q_12_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] maskedBeats_0_13 = winner_13_0 & opdata_20 ? decode_20 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire [2:0] _initBeats_T_6 = maskedBeats_0_13; // @[Arbiter.scala:82:69, :84:44]
wire [2:0] initBeats_13 = _initBeats_T_6; // @[Arbiter.scala:84:44]
wire [3:0] _beatsLeft_T_53 = {1'h0, beatsLeft_13} - {3'h0, _beatsLeft_T_52}; // @[Decoupled.scala:51:35]
wire [2:0] _beatsLeft_T_54 = _beatsLeft_T_53[2:0]; // @[Arbiter.scala:85:52]
wire [2:0] _beatsLeft_T_55 = latch_13 ? initBeats_13 : _beatsLeft_T_54; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_13_0; // @[Arbiter.scala:88:26]
reg state_13_1; // @[Arbiter.scala:88:26]
reg state_13_2; // @[Arbiter.scala:88:26]
wire muxState_13_0 = idle_13 ? winner_13_0 : state_13_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_13_1 = idle_13 ? winner_13_1 : state_13_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_13_2 = idle_13 ? winner_13_2 : state_13_2; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_13_0 = idle_13 ? readys_13_0 : state_13_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_13_1 = idle_13 ? readys_13_1 : state_13_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_13_2 = idle_13 ? readys_13_2 : state_13_2; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _d_d_ready_T_6 = in_d_6_ready & allowed_13_0; // @[CacheCork.scala:131:24]
assign d_d_6_ready = _d_d_ready_T_6; // @[CacheCork.scala:141:23]
wire _q_io_deq_ready_T_12 = in_d_6_ready & allowed_13_1; // @[CacheCork.scala:131:24]
wire _q_io_deq_ready_T_13 = in_d_6_ready & allowed_13_2; // @[CacheCork.scala:131:24]
wire _in_d_valid_T_49 = _in_d_valid_T_48 | _q_13_io_deq_valid; // @[Decoupled.scala:362:21]
wire _in_d_valid_T_50 = state_13_0 & d_d_6_valid; // @[Mux.scala:30:73]
wire _in_d_valid_T_51 = state_13_1 & _q_12_io_deq_valid; // @[Mux.scala:30:73]
wire _in_d_valid_T_52 = state_13_2 & _q_13_io_deq_valid; // @[Mux.scala:30:73]
wire _in_d_valid_T_53 = _in_d_valid_T_50 | _in_d_valid_T_51; // @[Mux.scala:30:73]
wire _in_d_valid_T_54 = _in_d_valid_T_53 | _in_d_valid_T_52; // @[Mux.scala:30:73]
wire _in_d_valid_WIRE_6 = _in_d_valid_T_54; // @[Mux.scala:30:73]
assign _in_d_valid_T_55 = idle_13 ? _in_d_valid_T_49 : _in_d_valid_WIRE_6; // @[Mux.scala:30:73]
assign in_d_6_valid = _in_d_valid_T_55; // @[CacheCork.scala:131:24]
wire [2:0] _in_d_bits_WIRE_76; // @[Mux.scala:30:73]
assign in_d_6_bits_opcode = _in_d_bits_WIRE_66_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_WIRE_75; // @[Mux.scala:30:73]
assign in_d_6_bits_param = _in_d_bits_WIRE_66_param; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_WIRE_74; // @[Mux.scala:30:73]
assign in_d_6_bits_size = _in_d_bits_WIRE_66_size; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_WIRE_73; // @[Mux.scala:30:73]
assign in_d_6_bits_source = _in_d_bits_WIRE_66_source; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_WIRE_72; // @[Mux.scala:30:73]
assign in_d_6_bits_sink = _in_d_bits_WIRE_66_sink; // @[Mux.scala:30:73]
wire _in_d_bits_WIRE_71; // @[Mux.scala:30:73]
assign in_d_6_bits_denied = _in_d_bits_WIRE_66_denied; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_WIRE_68; // @[Mux.scala:30:73]
assign in_d_6_bits_data = _in_d_bits_WIRE_66_data; // @[Mux.scala:30:73]
wire _in_d_bits_WIRE_67; // @[Mux.scala:30:73]
assign in_d_6_bits_corrupt = _in_d_bits_WIRE_66_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_240 = muxState_13_0 & d_d_6_bits_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_241 = muxState_13_1 & _q_12_io_deq_bits_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_242 = muxState_13_2 & _q_13_io_deq_bits_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_243 = _in_d_bits_T_240 | _in_d_bits_T_241; // @[Mux.scala:30:73]
wire _in_d_bits_T_244 = _in_d_bits_T_243 | _in_d_bits_T_242; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_67 = _in_d_bits_T_244; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_66_corrupt = _in_d_bits_WIRE_67; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_245 = muxState_13_0 ? d_d_6_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_246 = muxState_13_1 ? _q_12_io_deq_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_247 = muxState_13_2 ? _q_13_io_deq_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_248 = _in_d_bits_T_245 | _in_d_bits_T_246; // @[Mux.scala:30:73]
wire [63:0] _in_d_bits_T_249 = _in_d_bits_T_248 | _in_d_bits_T_247; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_68 = _in_d_bits_T_249; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_66_data = _in_d_bits_WIRE_68; // @[Mux.scala:30:73]
wire _in_d_bits_T_250 = muxState_13_0 & d_d_6_bits_denied; // @[Mux.scala:30:73]
wire _in_d_bits_T_251 = muxState_13_1 & _q_12_io_deq_bits_denied; // @[Mux.scala:30:73]
wire _in_d_bits_T_252 = muxState_13_2 & _q_13_io_deq_bits_denied; // @[Mux.scala:30:73]
wire _in_d_bits_T_253 = _in_d_bits_T_250 | _in_d_bits_T_251; // @[Mux.scala:30:73]
wire _in_d_bits_T_254 = _in_d_bits_T_253 | _in_d_bits_T_252; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_71 = _in_d_bits_T_254; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_66_denied = _in_d_bits_WIRE_71; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_255 = muxState_13_0 ? d_d_6_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_256 = muxState_13_1 ? _q_12_io_deq_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_257 = muxState_13_2 ? _q_13_io_deq_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_258 = _in_d_bits_T_255 | _in_d_bits_T_256; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_259 = _in_d_bits_T_258 | _in_d_bits_T_257; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_72 = _in_d_bits_T_259; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_66_sink = _in_d_bits_WIRE_72; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_260 = muxState_13_0 ? d_d_6_bits_source : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_261 = muxState_13_1 ? _q_12_io_deq_bits_source : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_262 = muxState_13_2 ? _q_13_io_deq_bits_source : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_263 = _in_d_bits_T_260 | _in_d_bits_T_261; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_264 = _in_d_bits_T_263 | _in_d_bits_T_262; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_73 = _in_d_bits_T_264; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_66_source = _in_d_bits_WIRE_73; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_265 = muxState_13_0 ? d_d_6_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_266 = muxState_13_1 ? _q_12_io_deq_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_267 = muxState_13_2 ? _q_13_io_deq_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_268 = _in_d_bits_T_265 | _in_d_bits_T_266; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_269 = _in_d_bits_T_268 | _in_d_bits_T_267; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_74 = _in_d_bits_T_269; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_66_size = _in_d_bits_WIRE_74; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_270 = muxState_13_0 ? d_d_6_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_271 = muxState_13_1 ? _q_12_io_deq_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_272 = muxState_13_2 ? _q_13_io_deq_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_273 = _in_d_bits_T_270 | _in_d_bits_T_271; // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_274 = _in_d_bits_T_273 | _in_d_bits_T_272; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_75 = _in_d_bits_T_274; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_66_param = _in_d_bits_WIRE_75; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_275 = muxState_13_0 ? d_d_6_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_276 = muxState_13_1 ? _q_12_io_deq_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_277 = muxState_13_2 ? _q_13_io_deq_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_278 = _in_d_bits_T_275 | _in_d_bits_T_276; // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_279 = _in_d_bits_T_278 | _in_d_bits_T_277; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_76 = _in_d_bits_T_279; // @[Mux.scala:30:73]
assign _in_d_bits_WIRE_66_opcode = _in_d_bits_WIRE_76; // @[Mux.scala:30:73]
wire _a_a_ready_T_7; // @[Arbiter.scala:94:31]
wire _a_a_valid_T_15; // @[CacheCork.scala:81:33]
wire [2:0] a_a_7_bits_opcode; // @[CacheCork.scala:74:23]
wire [2:0] a_a_7_bits_param; // @[CacheCork.scala:74:23]
wire [4:0] a_a_7_bits_source; // @[CacheCork.scala:74:23]
wire a_a_7_ready; // @[CacheCork.scala:74:23]
wire a_a_7_valid; // @[CacheCork.scala:74:23]
wire _a_d_valid_T_7; // @[CacheCork.scala:93:33]
wire [2:0] a_d_7_bits_size; // @[CacheCork.scala:75:23]
wire [3:0] a_d_7_bits_source; // @[CacheCork.scala:75:23]
wire a_d_7_ready; // @[CacheCork.scala:75:23]
wire a_d_7_valid; // @[CacheCork.scala:75:23]
wire _isPut_T_14 = nodeIn_7_a_bits_opcode == 3'h0; // @[CacheCork.scala:76:38]
wire _isPut_T_15 = nodeIn_7_a_bits_opcode == 3'h1; // @[CacheCork.scala:76:74]
wire isPut_7 = _isPut_T_14 | _isPut_T_15; // @[CacheCork.scala:76:{38,54,74}]
wire _a_a_bits_source_T_36 = isPut_7; // @[CacheCork.scala:76:54, :83:55]
wire _toD_T_28 = nodeIn_7_a_bits_opcode == 3'h6; // @[CacheCork.scala:77:37]
wire _toD_T_29 = nodeIn_7_a_bits_param == 3'h2; // @[CacheCork.scala:77:73]
wire _toD_T_30 = _toD_T_28 & _toD_T_29; // @[CacheCork.scala:77:{37,54,73}]
wire _toD_T_31 = &nodeIn_7_a_bits_opcode; // @[CacheCork.scala:78:37]
wire toD_7 = _toD_T_30 | _toD_T_31; // @[CacheCork.scala:77:{54,97}, :78:37]
assign _nodeIn_a_ready_T_7 = toD_7 ? a_d_7_ready : a_a_7_ready; // @[CacheCork.scala:74:23, :75:23, :77:97, :79:26]
assign nodeIn_7_a_ready = _nodeIn_a_ready_T_7; // @[CacheCork.scala:79:26]
wire _a_a_valid_T_14 = ~toD_7; // @[CacheCork.scala:77:97, :81:36]
assign _a_a_valid_T_15 = nodeIn_7_a_valid & _a_a_valid_T_14; // @[CacheCork.scala:81:{33,36}]
assign a_a_7_valid = _a_a_valid_T_15; // @[CacheCork.scala:74:23, :81:33]
wire [4:0] _GEN_13 = {nodeIn_7_a_bits_source, 1'h0}; // @[CacheCork.scala:83:45]
wire [4:0] _a_a_bits_source_T_35; // @[CacheCork.scala:83:45]
assign _a_a_bits_source_T_35 = _GEN_13; // @[CacheCork.scala:83:45]
wire [4:0] _a_a_bits_source_T_38; // @[CacheCork.scala:89:47]
assign _a_a_bits_source_T_38 = _GEN_13; // @[CacheCork.scala:83:45, :89:47]
wire [4:0] _a_a_bits_source_T_37 = {_a_a_bits_source_T_35[4:1], _a_a_bits_source_T_35[0] | _a_a_bits_source_T_36}; // @[CacheCork.scala:83:{45,50,55}]
wire _T_464 = _toD_T_28 | (&nodeIn_7_a_bits_opcode); // @[CacheCork.scala:77:37, :78:37, :86:49]
assign a_a_7_bits_opcode = _T_464 ? 3'h4 : nodeIn_7_a_bits_opcode; // @[CacheCork.scala:74:23, :82:18, :86:{49,86}, :87:27]
assign a_a_7_bits_param = _T_464 ? 3'h0 : nodeIn_7_a_bits_param; // @[CacheCork.scala:74:23, :82:18, :86:{49,86}, :88:27]
wire [4:0] _a_a_bits_source_T_39 = {_a_a_bits_source_T_38[4:1], 1'h1}; // @[CacheCork.scala:89:{47,52}]
assign a_a_7_bits_source = _T_464 ? _a_a_bits_source_T_39 : _a_a_bits_source_T_37; // @[CacheCork.scala:74:23, :83:{25,50}, :86:{49,86}, :89:{27,52}]
assign _a_d_valid_T_7 = nodeIn_7_a_valid & toD_7; // @[CacheCork.scala:77:97, :93:33]
assign a_d_7_valid = _a_d_valid_T_7; // @[CacheCork.scala:75:23, :93:33]
assign a_d_7_bits_size = a_d_bits_d_7_size; // @[Edges.scala:645:17]
assign a_d_7_bits_source = a_d_bits_d_7_source; // @[Edges.scala:645:17]
wire _c_a_ready_T_7; // @[Arbiter.scala:94:31]
wire _c_a_valid_T_15; // @[CacheCork.scala:102:33]
wire [4:0] c_a_bits_a_7_source; // @[Edges.scala:480:17]
wire [7:0] c_a_bits_a_7_mask; // @[Edges.scala:480:17]
wire [2:0] c_a_7_bits_size; // @[CacheCork.scala:101:23]
wire [4:0] c_a_7_bits_source; // @[CacheCork.scala:101:23]
wire [31:0] c_a_7_bits_address; // @[CacheCork.scala:101:23]
wire [7:0] c_a_7_bits_mask; // @[CacheCork.scala:101:23]
wire [63:0] c_a_7_bits_data; // @[CacheCork.scala:101:23]
wire c_a_7_bits_corrupt; // @[CacheCork.scala:101:23]
wire c_a_7_ready; // @[CacheCork.scala:101:23]
wire c_a_7_valid; // @[CacheCork.scala:101:23]
wire _c_a_valid_T_14 = &nodeIn_7_c_bits_opcode; // @[CacheCork.scala:102:53]
assign _c_a_valid_T_15 = nodeIn_7_c_valid & _c_a_valid_T_14; // @[CacheCork.scala:102:{33,53}]
assign c_a_7_valid = _c_a_valid_T_15; // @[CacheCork.scala:101:23, :102:33]
wire [4:0] _c_a_bits_T_7 = {nodeIn_7_c_bits_source, 1'h0}; // @[CacheCork.scala:104:41]
assign c_a_bits_a_7_source = _c_a_bits_T_7; // @[Edges.scala:480:17]
wire _c_a_bits_legal_T_71 = nodeIn_7_c_bits_size != 3'h7; // @[Parameters.scala:92:38]
wire _c_a_bits_legal_T_72 = _c_a_bits_legal_T_71; // @[Parameters.scala:92:{33,38}]
wire _c_a_bits_legal_T_73 = _c_a_bits_legal_T_72; // @[Parameters.scala:684:29]
wire _c_a_bits_legal_T_79 = _c_a_bits_legal_T_73; // @[Parameters.scala:684:{29,54}]
wire [32:0] _c_a_bits_legal_T_75 = {1'h0, _c_a_bits_legal_T_74}; // @[Parameters.scala:137:{31,41}]
wire c_a_bits_legal_7 = _c_a_bits_legal_T_79; // @[Parameters.scala:684:54, :686:26]
assign c_a_7_bits_size = c_a_bits_a_7_size; // @[Edges.scala:480:17]
assign c_a_7_bits_source = c_a_bits_a_7_source; // @[Edges.scala:480:17]
assign c_a_7_bits_address = c_a_bits_a_7_address; // @[Edges.scala:480:17]
wire [7:0] _c_a_bits_a_mask_T_7; // @[Misc.scala:222:10]
assign c_a_7_bits_mask = c_a_bits_a_7_mask; // @[Edges.scala:480:17]
assign c_a_7_bits_data = c_a_bits_a_7_data; // @[Edges.scala:480:17]
assign c_a_7_bits_corrupt = c_a_bits_a_7_corrupt; // @[Edges.scala:480:17]
wire [1:0] c_a_bits_a_mask_sizeOH_shiftAmount_7 = _c_a_bits_a_mask_sizeOH_T_21[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _c_a_bits_a_mask_sizeOH_T_22 = 4'h1 << c_a_bits_a_mask_sizeOH_shiftAmount_7; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _c_a_bits_a_mask_sizeOH_T_23 = _c_a_bits_a_mask_sizeOH_T_22[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] c_a_bits_a_mask_sizeOH_7 = {_c_a_bits_a_mask_sizeOH_T_23[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire c_a_bits_a_mask_sub_sub_sub_0_1_7 = nodeIn_7_c_bits_size > 3'h2; // @[Misc.scala:206:21]
wire c_a_bits_a_mask_sub_sub_size_7 = c_a_bits_a_mask_sizeOH_7[2]; // @[Misc.scala:202:81, :209:26]
wire c_a_bits_a_mask_sub_sub_bit_7 = nodeIn_7_c_bits_address[2]; // @[Misc.scala:210:26]
wire c_a_bits_a_mask_sub_sub_1_2_7 = c_a_bits_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27]
wire c_a_bits_a_mask_sub_sub_nbit_7 = ~c_a_bits_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20]
wire c_a_bits_a_mask_sub_sub_0_2_7 = c_a_bits_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_sub_sub_acc_T_14 = c_a_bits_a_mask_sub_sub_size_7 & c_a_bits_a_mask_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_sub_0_1_7 = c_a_bits_a_mask_sub_sub_sub_0_1_7 | _c_a_bits_a_mask_sub_sub_acc_T_14; // @[Misc.scala:206:21, :215:{29,38}]
wire _c_a_bits_a_mask_sub_sub_acc_T_15 = c_a_bits_a_mask_sub_sub_size_7 & c_a_bits_a_mask_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_sub_1_1_7 = c_a_bits_a_mask_sub_sub_sub_0_1_7 | _c_a_bits_a_mask_sub_sub_acc_T_15; // @[Misc.scala:206:21, :215:{29,38}]
wire c_a_bits_a_mask_sub_size_7 = c_a_bits_a_mask_sizeOH_7[1]; // @[Misc.scala:202:81, :209:26]
wire c_a_bits_a_mask_sub_bit_7 = nodeIn_7_c_bits_address[1]; // @[Misc.scala:210:26]
wire c_a_bits_a_mask_sub_nbit_7 = ~c_a_bits_a_mask_sub_bit_7; // @[Misc.scala:210:26, :211:20]
wire c_a_bits_a_mask_sub_0_2_7 = c_a_bits_a_mask_sub_sub_0_2_7 & c_a_bits_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_28 = c_a_bits_a_mask_sub_size_7 & c_a_bits_a_mask_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_0_1_7 = c_a_bits_a_mask_sub_sub_0_1_7 | _c_a_bits_a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_sub_1_2_7 = c_a_bits_a_mask_sub_sub_0_2_7 & c_a_bits_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_29 = c_a_bits_a_mask_sub_size_7 & c_a_bits_a_mask_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_1_1_7 = c_a_bits_a_mask_sub_sub_0_1_7 | _c_a_bits_a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_sub_2_2_7 = c_a_bits_a_mask_sub_sub_1_2_7 & c_a_bits_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_30 = c_a_bits_a_mask_sub_size_7 & c_a_bits_a_mask_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_2_1_7 = c_a_bits_a_mask_sub_sub_1_1_7 | _c_a_bits_a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_sub_3_2_7 = c_a_bits_a_mask_sub_sub_1_2_7 & c_a_bits_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_sub_acc_T_31 = c_a_bits_a_mask_sub_size_7 & c_a_bits_a_mask_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_sub_3_1_7 = c_a_bits_a_mask_sub_sub_1_1_7 | _c_a_bits_a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_size_7 = c_a_bits_a_mask_sizeOH_7[0]; // @[Misc.scala:202:81, :209:26]
wire c_a_bits_a_mask_bit_7 = nodeIn_7_c_bits_address[0]; // @[Misc.scala:210:26]
wire c_a_bits_a_mask_nbit_7 = ~c_a_bits_a_mask_bit_7; // @[Misc.scala:210:26, :211:20]
wire c_a_bits_a_mask_eq_56 = c_a_bits_a_mask_sub_0_2_7 & c_a_bits_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_56 = c_a_bits_a_mask_size_7 & c_a_bits_a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_56 = c_a_bits_a_mask_sub_0_1_7 | _c_a_bits_a_mask_acc_T_56; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_57 = c_a_bits_a_mask_sub_0_2_7 & c_a_bits_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_57 = c_a_bits_a_mask_size_7 & c_a_bits_a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_57 = c_a_bits_a_mask_sub_0_1_7 | _c_a_bits_a_mask_acc_T_57; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_58 = c_a_bits_a_mask_sub_1_2_7 & c_a_bits_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_58 = c_a_bits_a_mask_size_7 & c_a_bits_a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_58 = c_a_bits_a_mask_sub_1_1_7 | _c_a_bits_a_mask_acc_T_58; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_59 = c_a_bits_a_mask_sub_1_2_7 & c_a_bits_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_59 = c_a_bits_a_mask_size_7 & c_a_bits_a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_59 = c_a_bits_a_mask_sub_1_1_7 | _c_a_bits_a_mask_acc_T_59; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_60 = c_a_bits_a_mask_sub_2_2_7 & c_a_bits_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_60 = c_a_bits_a_mask_size_7 & c_a_bits_a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_60 = c_a_bits_a_mask_sub_2_1_7 | _c_a_bits_a_mask_acc_T_60; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_61 = c_a_bits_a_mask_sub_2_2_7 & c_a_bits_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_61 = c_a_bits_a_mask_size_7 & c_a_bits_a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_61 = c_a_bits_a_mask_sub_2_1_7 | _c_a_bits_a_mask_acc_T_61; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_62 = c_a_bits_a_mask_sub_3_2_7 & c_a_bits_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _c_a_bits_a_mask_acc_T_62 = c_a_bits_a_mask_size_7 & c_a_bits_a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_62 = c_a_bits_a_mask_sub_3_1_7 | _c_a_bits_a_mask_acc_T_62; // @[Misc.scala:215:{29,38}]
wire c_a_bits_a_mask_eq_63 = c_a_bits_a_mask_sub_3_2_7 & c_a_bits_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _c_a_bits_a_mask_acc_T_63 = c_a_bits_a_mask_size_7 & c_a_bits_a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38]
wire c_a_bits_a_mask_acc_63 = c_a_bits_a_mask_sub_3_1_7 | _c_a_bits_a_mask_acc_T_63; // @[Misc.scala:215:{29,38}]
wire [1:0] c_a_bits_a_mask_lo_lo_7 = {c_a_bits_a_mask_acc_57, c_a_bits_a_mask_acc_56}; // @[Misc.scala:215:29, :222:10]
wire [1:0] c_a_bits_a_mask_lo_hi_7 = {c_a_bits_a_mask_acc_59, c_a_bits_a_mask_acc_58}; // @[Misc.scala:215:29, :222:10]
wire [3:0] c_a_bits_a_mask_lo_7 = {c_a_bits_a_mask_lo_hi_7, c_a_bits_a_mask_lo_lo_7}; // @[Misc.scala:222:10]
wire [1:0] c_a_bits_a_mask_hi_lo_7 = {c_a_bits_a_mask_acc_61, c_a_bits_a_mask_acc_60}; // @[Misc.scala:215:29, :222:10]
wire [1:0] c_a_bits_a_mask_hi_hi_7 = {c_a_bits_a_mask_acc_63, c_a_bits_a_mask_acc_62}; // @[Misc.scala:215:29, :222:10]
wire [3:0] c_a_bits_a_mask_hi_7 = {c_a_bits_a_mask_hi_hi_7, c_a_bits_a_mask_hi_lo_7}; // @[Misc.scala:222:10]
assign _c_a_bits_a_mask_T_7 = {c_a_bits_a_mask_hi_7, c_a_bits_a_mask_lo_7}; // @[Misc.scala:222:10]
assign c_a_bits_a_7_mask = _c_a_bits_a_mask_T_7; // @[Misc.scala:222:10]
wire _c_d_valid_T_15; // @[CacheCork.scala:113:33]
wire [2:0] c_d_7_bits_size; // @[CacheCork.scala:112:23]
wire [3:0] c_d_7_bits_source; // @[CacheCork.scala:112:23]
wire c_d_7_ready; // @[CacheCork.scala:112:23]
wire c_d_7_valid; // @[CacheCork.scala:112:23]
wire _T_466 = nodeIn_7_c_bits_opcode == 3'h6; // @[CacheCork.scala:113:53]
wire _c_d_valid_T_14; // @[CacheCork.scala:113:53]
assign _c_d_valid_T_14 = _T_466; // @[CacheCork.scala:113:53]
wire _nodeIn_c_ready_T_14; // @[CacheCork.scala:117:44]
assign _nodeIn_c_ready_T_14 = _T_466; // @[CacheCork.scala:113:53, :117:44]
assign _c_d_valid_T_15 = nodeIn_7_c_valid & _c_d_valid_T_14; // @[CacheCork.scala:113:{33,53}]
assign c_d_7_valid = _c_d_valid_T_15; // @[CacheCork.scala:112:23, :113:33]
assign c_d_7_bits_size = c_d_bits_d_7_size; // @[Edges.scala:677:17]
assign c_d_7_bits_source = c_d_bits_d_7_source; // @[Edges.scala:677:17]
assign _nodeIn_c_ready_T_15 = _nodeIn_c_ready_T_14 ? c_d_7_ready : c_a_7_ready; // @[CacheCork.scala:101:23, :112:23, :117:{26,44}]
assign nodeIn_7_c_ready = _nodeIn_c_ready_T_15; // @[CacheCork.scala:117:26]
wire _in_d_ready_T_39; // @[CacheCork.scala:136:34]
wire _in_d_valid_T_63; // @[Arbiter.scala:96:24]
wire [2:0] _in_d_bits_WIRE_77_opcode; // @[Mux.scala:30:73]
assign nodeIn_7_d_bits_opcode = in_d_7_bits_opcode; // @[CacheCork.scala:131:24]
wire [1:0] _in_d_bits_WIRE_77_param; // @[Mux.scala:30:73]
assign nodeIn_7_d_bits_param = in_d_7_bits_param; // @[CacheCork.scala:131:24]
wire [2:0] _in_d_bits_WIRE_77_size; // @[Mux.scala:30:73]
assign nodeIn_7_d_bits_size = in_d_7_bits_size; // @[CacheCork.scala:131:24]
wire [3:0] _in_d_bits_WIRE_77_source; // @[Mux.scala:30:73]
assign nodeIn_7_d_bits_source = in_d_7_bits_source; // @[CacheCork.scala:131:24]
wire [2:0] _in_d_bits_WIRE_77_sink; // @[Mux.scala:30:73]
wire _in_d_bits_WIRE_77_denied; // @[Mux.scala:30:73]
assign nodeIn_7_d_bits_denied = in_d_7_bits_denied; // @[CacheCork.scala:131:24]
wire [63:0] _in_d_bits_WIRE_77_data; // @[Mux.scala:30:73]
assign nodeIn_7_d_bits_data = in_d_7_bits_data; // @[CacheCork.scala:131:24]
wire _in_d_bits_WIRE_77_corrupt; // @[Mux.scala:30:73]
assign nodeIn_7_d_bits_corrupt = in_d_7_bits_corrupt; // @[CacheCork.scala:131:24]
wire [2:0] in_d_7_bits_sink; // @[CacheCork.scala:131:24]
wire in_d_7_ready; // @[CacheCork.scala:131:24]
wire in_d_7_valid; // @[CacheCork.scala:131:24]
wire _GEN_14 = in_d_7_ready & in_d_7_valid; // @[Decoupled.scala:51:35]
wire _d_first_T_7; // @[Decoupled.scala:51:35]
assign _d_first_T_7 = _GEN_14; // @[Decoupled.scala:51:35]
wire _beatsLeft_T_60; // @[Decoupled.scala:51:35]
assign _beatsLeft_T_60 = _GEN_14; // @[Decoupled.scala:51:35]
wire [12:0] _d_first_beats1_decode_T_21 = 13'h3F << in_d_7_bits_size; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_22 = _d_first_beats1_decode_T_21[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_23 = ~_d_first_beats1_decode_T_22; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_7 = _d_first_beats1_decode_T_23[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata_7 = in_d_7_bits_opcode[0]; // @[Edges.scala:106:36]
wire [2:0] d_first_beats1_7 = d_first_beats1_opdata_7 ? d_first_beats1_decode_7 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_7; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_7 = {1'h0, d_first_counter_7} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_7 = _d_first_counter1_T_7[2:0]; // @[Edges.scala:230:28]
wire d_first_7 = d_first_counter_7 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_14 = d_first_counter_7 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_15 = d_first_beats1_7 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_7 = _d_first_last_T_14 | _d_first_last_T_15; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_7 = d_first_last_7 & _d_first_T_7; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_7 = ~d_first_counter1_7; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_7 = d_first_beats1_7 & _d_first_count_T_7; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_7 = d_first_7 ? d_first_beats1_7 : d_first_counter1_7; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _d_grant_T_14 = in_d_7_bits_opcode == 3'h5; // @[CacheCork.scala:131:24, :133:40]
wire _d_grant_T_15 = in_d_7_bits_opcode == 3'h4; // @[CacheCork.scala:131:24, :133:74]
wire d_grant_7 = _d_grant_T_14 | _d_grant_T_15; // @[CacheCork.scala:133:{40,54,74}]
wire _pool_io_alloc_ready_T_21 = nodeIn_7_d_ready & nodeIn_7_d_valid; // @[Decoupled.scala:51:35]
wire _pool_io_alloc_ready_T_22 = _pool_io_alloc_ready_T_21 & d_first_7; // @[Decoupled.scala:51:35]
wire _pool_io_alloc_ready_T_23 = _pool_io_alloc_ready_T_22 & d_grant_7; // @[CacheCork.scala:133:54, :134:{42,53}]
wire _nodeIn_d_valid_T_35 = ~d_first_7; // @[Edges.scala:231:25]
wire _nodeIn_d_valid_T_36 = _pool_7_io_alloc_valid | _nodeIn_d_valid_T_35; // @[CacheCork.scala:127:26, :135:{58,61}]
wire _nodeIn_d_valid_T_37 = ~d_grant_7; // @[CacheCork.scala:133:54, :135:73]
wire _nodeIn_d_valid_T_38 = _nodeIn_d_valid_T_36 | _nodeIn_d_valid_T_37; // @[CacheCork.scala:135:{58,70,73}]
assign _nodeIn_d_valid_T_39 = in_d_7_valid & _nodeIn_d_valid_T_38; // @[CacheCork.scala:131:24, :135:{34,70}]
assign nodeIn_7_d_valid = _nodeIn_d_valid_T_39; // @[CacheCork.scala:135:34]
wire _in_d_ready_T_35 = ~d_first_7; // @[Edges.scala:231:25]
wire _in_d_ready_T_36 = _pool_7_io_alloc_valid | _in_d_ready_T_35; // @[CacheCork.scala:127:26, :136:{58,61}]
wire _in_d_ready_T_37 = ~d_grant_7; // @[CacheCork.scala:133:54, :135:73, :136:73]
wire _in_d_ready_T_38 = _in_d_ready_T_36 | _in_d_ready_T_37; // @[CacheCork.scala:136:{58,70,73}]
assign _in_d_ready_T_39 = nodeIn_7_d_ready & _in_d_ready_T_38; // @[CacheCork.scala:136:{34,70}]
assign in_d_7_ready = _in_d_ready_T_39; // @[CacheCork.scala:131:24, :136:34]
reg [2:0] nodeIn_d_bits_sink_r_7; // @[package.scala:88:63]
assign _nodeIn_d_bits_sink_T_7 = d_first_7 ? _pool_7_io_alloc_bits : nodeIn_d_bits_sink_r_7; // @[package.scala:88:{42,63}]
assign nodeIn_7_d_bits_sink = _nodeIn_d_bits_sink_T_7; // @[package.scala:88:42]
wire _d_d_ready_T_7; // @[Arbiter.scala:94:31]
assign x1_nodeOut_6_d_ready = d_d_7_ready; // @[CacheCork.scala:141:23]
wire [3:0] _d_d_bits_source_T_7; // @[CacheCork.scala:143:46]
wire [2:0] d_d_7_bits_opcode; // @[CacheCork.scala:141:23]
wire [1:0] d_d_7_bits_param; // @[CacheCork.scala:141:23]
wire [3:0] d_d_7_bits_source; // @[CacheCork.scala:141:23]
wire [2:0] d_d_7_bits_sink; // @[CacheCork.scala:141:23]
assign d_d_7_bits_sink = {2'h0, x1_nodeOut_6_d_bits_sink}; // @[CacheCork.scala:141:23, :142:13]
assign _d_d_bits_source_T_7 = x1_nodeOut_6_d_bits_source[4:1]; // @[CacheCork.scala:143:46]
assign d_d_7_bits_source = _d_d_bits_source_T_7; // @[CacheCork.scala:141:23, :143:46]
wire [32:0] _aWOk_T_36 = {1'h0, _aWOk_T_35}; // @[Parameters.scala:137:{31,41}]
wire _bypass_T_15 = nodeIn_7_a_bits_source == d_d_7_bits_source; // @[CacheCork.scala:141:23, :150:91]
reg dWHeld_r_7; // @[package.scala:88:63]
wire dWHeld_7 = d_first_7 ? _dWHeld_T_7 : dWHeld_r_7; // @[package.scala:88:{42,63}]
wire _T_480 = x1_nodeOut_6_d_bits_opcode == 3'h1 & x1_nodeOut_6_d_bits_source[0]; // @[CacheCork.scala:162:{33,51,71}]
wire [1:0] _d_d_bits_param_T_7 = {1'h0, ~dWHeld_7}; // @[package.scala:88:42]
assign d_d_7_bits_param = _T_480 ? _d_d_bits_param_T_7 : x1_nodeOut_6_d_bits_param; // @[CacheCork.scala:141:23, :142:13, :162:{51,76}, :164:{26,32}]
assign d_d_7_bits_opcode = x1_nodeOut_6_d_bits_opcode == 3'h0 & ~(x1_nodeOut_6_d_bits_source[0]) ? 3'h6 : _T_480 ? 3'h5 : x1_nodeOut_6_d_bits_opcode; // @[CacheCork.scala:141:23, :142:13, :162:{51,71,76}, :163:27, :166:{33,47,50,73}, :167:27]
wire [12:0] _decode_T_63 = 13'h3F << c_a_7_bits_size; // @[package.scala:243:71]
wire [5:0] _decode_T_64 = _decode_T_63[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _decode_T_65 = ~_decode_T_64; // @[package.scala:243:{46,76}]
wire [2:0] decode_21 = _decode_T_65[5:3]; // @[package.scala:243:46]
wire [12:0] _decode_T_66 = 13'h3F << a_a_7_bits_size; // @[package.scala:243:71]
wire [5:0] _decode_T_67 = _decode_T_66[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _decode_T_68 = ~_decode_T_67; // @[package.scala:243:{46,76}]
wire [2:0] decode_22 = _decode_T_68[5:3]; // @[package.scala:243:46]
wire _opdata_T_15 = a_a_7_bits_opcode[2]; // @[Edges.scala:92:37]
wire opdata_22 = ~_opdata_T_15; // @[Edges.scala:92:{28,37}]
reg [2:0] beatsLeft_14; // @[Arbiter.scala:60:30]
wire idle_14 = beatsLeft_14 == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_14 = idle_14 & x1_nodeOut_6_a_ready; // @[Arbiter.scala:61:28, :62:24]
wire [1:0] _readys_T_168 = {a_a_7_valid, c_a_7_valid}; // @[CacheCork.scala:74:23, :101:23]
wire [2:0] _readys_T_169 = {_readys_T_168, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_T_170 = _readys_T_169[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_T_171 = _readys_T_168 | _readys_T_170; // @[package.scala:253:{43,53}]
wire [1:0] _readys_T_172 = _readys_T_171; // @[package.scala:253:43, :254:17]
wire [2:0] _readys_T_173 = {_readys_T_172, 1'h0}; // @[package.scala:254:17]
wire [1:0] _readys_T_174 = _readys_T_173[1:0]; // @[Arbiter.scala:16:{78,83}]
wire [1:0] _readys_T_175 = ~_readys_T_174; // @[Arbiter.scala:16:{61,83}]
wire _readys_T_176 = _readys_T_175[0]; // @[Arbiter.scala:16:61, :68:76]
wire readys_14_0 = _readys_T_176; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_177 = _readys_T_175[1]; // @[Arbiter.scala:16:61, :68:76]
wire readys_14_1 = _readys_T_177; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_35 = readys_14_0 & c_a_7_valid; // @[CacheCork.scala:101:23]
wire winner_14_0 = _winner_T_35; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_36 = readys_14_1 & a_a_7_valid; // @[CacheCork.scala:74:23]
wire winner_14_1 = _winner_T_36; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_14 = winner_14_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_14 = prefixOR_1_14 | winner_14_1; // @[Arbiter.scala:71:27, :76:48]
wire _nodeOut_a_valid_T_35 = c_a_7_valid | a_a_7_valid; // @[CacheCork.scala:74:23, :101:23]
wire [2:0] maskedBeats_0_14 = winner_14_0 ? decode_21 : 3'h0; // @[Edges.scala:220:59, :221:14]
wire [2:0] maskedBeats_1_14 = winner_14_1 & opdata_22 ? decode_22 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [2:0] initBeats_14 = maskedBeats_0_14 | maskedBeats_1_14; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_56 = x1_nodeOut_6_a_ready & x1_nodeOut_6_a_valid; // @[Decoupled.scala:51:35]
wire [3:0] _beatsLeft_T_57 = {1'h0, beatsLeft_14} - {3'h0, _beatsLeft_T_56}; // @[Decoupled.scala:51:35]
wire [2:0] _beatsLeft_T_58 = _beatsLeft_T_57[2:0]; // @[Arbiter.scala:85:52]
wire [2:0] _beatsLeft_T_59 = latch_14 ? initBeats_14 : _beatsLeft_T_58; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_14_0; // @[Arbiter.scala:88:26]
reg state_14_1; // @[Arbiter.scala:88:26]
wire muxState_14_0 = idle_14 ? winner_14_0 : state_14_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_14_1 = idle_14 ? winner_14_1 : state_14_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_14_0 = idle_14 ? readys_14_0 : state_14_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_14_1 = idle_14 ? readys_14_1 : state_14_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _c_a_ready_T_7 = x1_nodeOut_6_a_ready & allowed_14_0; // @[Arbiter.scala:92:24, :94:31]
assign c_a_7_ready = _c_a_ready_T_7; // @[CacheCork.scala:101:23]
assign _a_a_ready_T_7 = x1_nodeOut_6_a_ready & allowed_14_1; // @[Arbiter.scala:92:24, :94:31]
assign a_a_7_ready = _a_a_ready_T_7; // @[CacheCork.scala:74:23]
wire _nodeOut_a_valid_T_36 = state_14_0 & c_a_7_valid; // @[Mux.scala:30:73]
wire _nodeOut_a_valid_T_37 = state_14_1 & a_a_7_valid; // @[Mux.scala:30:73]
wire _nodeOut_a_valid_T_38 = _nodeOut_a_valid_T_36 | _nodeOut_a_valid_T_37; // @[Mux.scala:30:73]
wire _nodeOut_a_valid_WIRE_7 = _nodeOut_a_valid_T_38; // @[Mux.scala:30:73]
assign _nodeOut_a_valid_T_39 = idle_14 ? _nodeOut_a_valid_T_35 : _nodeOut_a_valid_WIRE_7; // @[Mux.scala:30:73]
assign x1_nodeOut_6_a_valid = _nodeOut_a_valid_T_39; // @[Arbiter.scala:96:24]
wire [2:0] _nodeOut_a_bits_WIRE_87; // @[Mux.scala:30:73]
assign x1_nodeOut_6_a_bits_opcode = _nodeOut_a_bits_WIRE_77_opcode; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_WIRE_86; // @[Mux.scala:30:73]
assign x1_nodeOut_6_a_bits_param = _nodeOut_a_bits_WIRE_77_param; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_WIRE_85; // @[Mux.scala:30:73]
assign x1_nodeOut_6_a_bits_size = _nodeOut_a_bits_WIRE_77_size; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_WIRE_84; // @[Mux.scala:30:73]
assign x1_nodeOut_6_a_bits_source = _nodeOut_a_bits_WIRE_77_source; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_WIRE_83; // @[Mux.scala:30:73]
assign x1_nodeOut_6_a_bits_address = _nodeOut_a_bits_WIRE_77_address; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_WIRE_80; // @[Mux.scala:30:73]
assign x1_nodeOut_6_a_bits_mask = _nodeOut_a_bits_WIRE_77_mask; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_WIRE_79; // @[Mux.scala:30:73]
assign x1_nodeOut_6_a_bits_data = _nodeOut_a_bits_WIRE_77_data; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_WIRE_78; // @[Mux.scala:30:73]
assign x1_nodeOut_6_a_bits_corrupt = _nodeOut_a_bits_WIRE_77_corrupt; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T_168 = muxState_14_0 & c_a_7_bits_corrupt; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T_169 = muxState_14_1 & a_a_7_bits_corrupt; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T_170 = _nodeOut_a_bits_T_168 | _nodeOut_a_bits_T_169; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_78 = _nodeOut_a_bits_T_170; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_77_corrupt = _nodeOut_a_bits_WIRE_78; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_T_171 = muxState_14_0 ? c_a_7_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_T_172 = muxState_14_1 ? a_a_7_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_a_bits_T_173 = _nodeOut_a_bits_T_171 | _nodeOut_a_bits_T_172; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_79 = _nodeOut_a_bits_T_173; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_77_data = _nodeOut_a_bits_WIRE_79; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_T_174 = muxState_14_0 ? c_a_7_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_T_175 = muxState_14_1 ? a_a_7_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _nodeOut_a_bits_T_176 = _nodeOut_a_bits_T_174 | _nodeOut_a_bits_T_175; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_80 = _nodeOut_a_bits_T_176; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_77_mask = _nodeOut_a_bits_WIRE_80; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_T_177 = muxState_14_0 ? c_a_7_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_T_178 = muxState_14_1 ? a_a_7_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_a_bits_T_179 = _nodeOut_a_bits_T_177 | _nodeOut_a_bits_T_178; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_83 = _nodeOut_a_bits_T_179; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_77_address = _nodeOut_a_bits_WIRE_83; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_T_180 = muxState_14_0 ? c_a_7_bits_source : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_T_181 = muxState_14_1 ? a_a_7_bits_source : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _nodeOut_a_bits_T_182 = _nodeOut_a_bits_T_180 | _nodeOut_a_bits_T_181; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_84 = _nodeOut_a_bits_T_182; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_77_source = _nodeOut_a_bits_WIRE_84; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_183 = muxState_14_0 ? c_a_7_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_184 = muxState_14_1 ? a_a_7_bits_size : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_185 = _nodeOut_a_bits_T_183 | _nodeOut_a_bits_T_184; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_85 = _nodeOut_a_bits_T_185; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_77_size = _nodeOut_a_bits_WIRE_85; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_187 = muxState_14_1 ? a_a_7_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_188 = _nodeOut_a_bits_T_187; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_86 = _nodeOut_a_bits_T_188; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_77_param = _nodeOut_a_bits_WIRE_86; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_190 = muxState_14_1 ? a_a_7_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_191 = _nodeOut_a_bits_T_190; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_87 = _nodeOut_a_bits_T_191; // @[Mux.scala:30:73]
assign _nodeOut_a_bits_WIRE_77_opcode = _nodeOut_a_bits_WIRE_87; // @[Mux.scala:30:73]
wire [12:0] _decode_T_69 = 13'h3F << d_d_7_bits_size; // @[package.scala:243:71]
wire [5:0] _decode_T_70 = _decode_T_69[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _decode_T_71 = ~_decode_T_70; // @[package.scala:243:{46,76}]
wire [2:0] decode_23 = _decode_T_71[5:3]; // @[package.scala:243:46]
wire opdata_23 = d_d_7_bits_opcode[0]; // @[Edges.scala:106:36]
reg [2:0] beatsLeft_15; // @[Arbiter.scala:60:30]
wire idle_15 = beatsLeft_15 == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_15 = idle_15 & in_d_7_ready; // @[CacheCork.scala:131:24]
wire [1:0] readys_hi_7 = {_q_15_io_deq_valid, _q_14_io_deq_valid}; // @[Decoupled.scala:362:21]
wire [2:0] _readys_T_178 = {readys_hi_7, d_d_7_valid}; // @[CacheCork.scala:141:23]
wire [3:0] _readys_T_179 = {_readys_T_178, 1'h0}; // @[package.scala:253:48]
wire [2:0] _readys_T_180 = _readys_T_179[2:0]; // @[package.scala:253:{48,53}]
wire [2:0] _readys_T_181 = _readys_T_178 | _readys_T_180; // @[package.scala:253:{43,53}]
wire [4:0] _readys_T_182 = {_readys_T_181, 2'h0}; // @[package.scala:253:{43,48}]
wire [2:0] _readys_T_183 = _readys_T_182[2:0]; // @[package.scala:253:{48,53}]
wire [2:0] _readys_T_184 = _readys_T_181 | _readys_T_183; // @[package.scala:253:{43,53}]
wire [2:0] _readys_T_185 = _readys_T_184; // @[package.scala:253:43, :254:17]
wire [3:0] _readys_T_186 = {_readys_T_185, 1'h0}; // @[package.scala:254:17]
wire [2:0] _readys_T_187 = _readys_T_186[2:0]; // @[Arbiter.scala:16:{78,83}]
wire [2:0] _readys_T_188 = ~_readys_T_187; // @[Arbiter.scala:16:{61,83}]
wire _readys_T_189 = _readys_T_188[0]; // @[Arbiter.scala:16:61, :68:76]
wire readys_15_0 = _readys_T_189; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_190 = _readys_T_188[1]; // @[Arbiter.scala:16:61, :68:76]
wire readys_15_1 = _readys_T_190; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_191 = _readys_T_188[2]; // @[Arbiter.scala:16:61, :68:76]
wire readys_15_2 = _readys_T_191; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_37 = readys_15_0 & d_d_7_valid; // @[CacheCork.scala:141:23]
wire winner_15_0 = _winner_T_37; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_38 = readys_15_1 & _q_14_io_deq_valid; // @[Decoupled.scala:362:21]
wire winner_15_1 = _winner_T_38; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_39 = readys_15_2 & _q_15_io_deq_valid; // @[Decoupled.scala:362:21]
wire winner_15_2 = _winner_T_39; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_15 = winner_15_0; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_2_7 = prefixOR_1_15 | winner_15_1; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_15 = prefixOR_2_7 | winner_15_2; // @[Arbiter.scala:71:27, :76:48]
wire _in_d_valid_T_56 = d_d_7_valid | _q_14_io_deq_valid; // @[Decoupled.scala:362:21] |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a28d64s5k1z3u_1 :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_67
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a28d64s5k1z3u_1
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a28d64s5k1z3u_1
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<28>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<28>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<28>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_10.bits.sink, UInt<1>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLBuffer_a28d64s5k1z3u_1( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [27:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [4:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [27:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [4:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21]
wire auto_out_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21]
wire auto_out_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire [1:0] auto_out_d_bits_param = 2'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [4:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [27:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [27:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [4:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [4:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [4:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [27:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
TLMonitor_67 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a28d64s5k1z3u_1 nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a28d64s5k1z3u_1 nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PLICClockSinkDomain :
output auto : { flip plic_int_in : UInt<1>[1], flip plic_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, int_in_clock_xing_out : { sync : UInt<1>[1]}, flip clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst plic of TLPLIC
connect plic.clock, childClock
connect plic.reset, childReset
inst intsource of IntSyncCrossingSource_n1x1_3
connect intsource.clock, childClock
connect intsource.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
wire intInClockXingOut : { sync : UInt<1>[1]}
invalidate intInClockXingOut.sync[0]
wire intInClockXingIn : { sync : UInt<1>[1]}
invalidate intInClockXingIn.sync[0]
connect intInClockXingOut, intInClockXingIn
connect intsource.auto.in[0], plic.auto.int_out[0]
connect intInClockXingIn, intsource.auto.out
connect clockNodeIn, auto.clock_in
connect auto.int_in_clock_xing_out, intInClockXingOut
connect plic.auto.in, auto.plic_in
connect plic.auto.int_in[0], auto.plic_int_in[0]
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset
extmodule plusarg_reader_81 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_82 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module PLICClockSinkDomain( // @[ClockDomain.scala:14:9]
input auto_plic_int_in_0, // @[LazyModuleImp.scala:107:25]
output auto_plic_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_plic_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_plic_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_plic_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_plic_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_plic_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [27:0] auto_plic_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_plic_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_plic_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_plic_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_plic_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_plic_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_plic_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_plic_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_plic_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_plic_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
wire _plic_auto_int_out_0; // @[Plic.scala:367:46]
wire auto_plic_int_in_0_0 = auto_plic_int_in_0; // @[ClockDomain.scala:14:9]
wire auto_plic_in_a_valid_0 = auto_plic_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_plic_in_a_bits_opcode_0 = auto_plic_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_plic_in_a_bits_param_0 = auto_plic_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [1:0] auto_plic_in_a_bits_size_0 = auto_plic_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [11:0] auto_plic_in_a_bits_source_0 = auto_plic_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [27:0] auto_plic_in_a_bits_address_0 = auto_plic_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_plic_in_a_bits_mask_0 = auto_plic_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_plic_in_a_bits_data_0 = auto_plic_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_plic_in_a_bits_corrupt_0 = auto_plic_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_plic_in_d_ready_0 = auto_plic_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire [1:0] auto_plic_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire auto_plic_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_plic_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_plic_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire intInClockXingOut_sync_0; // @[MixedNode.scala:542:17]
wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9]
wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9]
wire auto_plic_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_plic_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_plic_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [11:0] auto_plic_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_plic_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_plic_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_out_sync_0_0; // @[ClockDomain.scala:14:9]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17]
wire intInClockXingIn_sync_0; // @[MixedNode.scala:551:17]
assign auto_int_in_clock_xing_out_sync_0_0 = intInClockXingOut_sync_0; // @[ClockDomain.scala:14:9]
assign intInClockXingOut_sync_0 = intInClockXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
TLPLIC plic ( // @[Plic.scala:367:46]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_int_in_0 (auto_plic_int_in_0_0), // @[ClockDomain.scala:14:9]
.auto_int_out_0 (_plic_auto_int_out_0),
.auto_in_a_ready (auto_plic_in_a_ready_0),
.auto_in_a_valid (auto_plic_in_a_valid_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_opcode (auto_plic_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_param (auto_plic_in_a_bits_param_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_size (auto_plic_in_a_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_source (auto_plic_in_a_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_address (auto_plic_in_a_bits_address_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_mask (auto_plic_in_a_bits_mask_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_data (auto_plic_in_a_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_corrupt (auto_plic_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9]
.auto_in_d_ready (auto_plic_in_d_ready_0), // @[ClockDomain.scala:14:9]
.auto_in_d_valid (auto_plic_in_d_valid_0),
.auto_in_d_bits_opcode (auto_plic_in_d_bits_opcode_0),
.auto_in_d_bits_size (auto_plic_in_d_bits_size_0),
.auto_in_d_bits_source (auto_plic_in_d_bits_source_0),
.auto_in_d_bits_data (auto_plic_in_d_bits_data_0)
); // @[Plic.scala:367:46]
IntSyncCrossingSource_n1x1_3 intsource ( // @[Crossing.scala:29:31]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_0 (_plic_auto_int_out_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (intInClockXingIn_sync_0)
); // @[Crossing.scala:29:31]
assign auto_plic_in_a_ready = auto_plic_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_plic_in_d_valid = auto_plic_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_plic_in_d_bits_opcode = auto_plic_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_plic_in_d_bits_size = auto_plic_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_plic_in_d_bits_source = auto_plic_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_plic_in_d_bits_data = auto_plic_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_int_in_clock_xing_out_sync_0 = auto_int_in_clock_xing_out_sync_0_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Router_10 :
input clock : Clock
input reset : Reset
output auto : { debug_out : { va_stall : UInt[2], sa_stall : UInt[2]}, egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip ingress_nodes_in : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}, flip dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}}
wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}
invalidate destNodesIn.vc_free
invalidate destNodesIn.credit_return
invalidate destNodesIn.flit[0].bits.virt_channel_id
invalidate destNodesIn.flit[0].bits.flow.egress_node_id
invalidate destNodesIn.flit[0].bits.flow.egress_node
invalidate destNodesIn.flit[0].bits.flow.ingress_node_id
invalidate destNodesIn.flit[0].bits.flow.ingress_node
invalidate destNodesIn.flit[0].bits.flow.vnet_id
invalidate destNodesIn.flit[0].bits.payload
invalidate destNodesIn.flit[0].bits.tail
invalidate destNodesIn.flit[0].bits.head
invalidate destNodesIn.flit[0].valid
inst monitor of NoCMonitor_10
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.vc_free, destNodesIn.vc_free
connect monitor.io.in.credit_return, destNodesIn.credit_return
connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id
connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id
connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node
connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id
connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node
connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id
connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload
connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail
connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head
connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid
wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}
invalidate sourceNodesOut.vc_free
invalidate sourceNodesOut.credit_return
invalidate sourceNodesOut.flit[0].bits.virt_channel_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node
invalidate sourceNodesOut.flit[0].bits.flow.vnet_id
invalidate sourceNodesOut.flit[0].bits.payload
invalidate sourceNodesOut.flit[0].bits.tail
invalidate sourceNodesOut.flit[0].bits.head
invalidate sourceNodesOut.flit[0].valid
wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesIn.flit.bits.egress_id
invalidate ingressNodesIn.flit.bits.payload
invalidate ingressNodesIn.flit.bits.tail
invalidate ingressNodesIn.flit.bits.head
invalidate ingressNodesIn.flit.valid
invalidate ingressNodesIn.flit.ready
wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesOut.flit.bits.ingress_id
invalidate egressNodesOut.flit.bits.payload
invalidate egressNodesOut.flit.bits.tail
invalidate egressNodesOut.flit.bits.head
invalidate egressNodesOut.flit.valid
invalidate egressNodesOut.flit.ready
wire egressNodesOut_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesOut_1.flit.bits.ingress_id
invalidate egressNodesOut_1.flit.bits.payload
invalidate egressNodesOut_1.flit.bits.tail
invalidate egressNodesOut_1.flit.bits.head
invalidate egressNodesOut_1.flit.valid
invalidate egressNodesOut_1.flit.ready
wire debugNodeOut : { va_stall : UInt[2], sa_stall : UInt[2]}
invalidate debugNodeOut.sa_stall[0]
invalidate debugNodeOut.sa_stall[1]
invalidate debugNodeOut.va_stall[0]
invalidate debugNodeOut.va_stall[1]
connect destNodesIn, auto.dest_nodes_in
connect auto.source_nodes_out, sourceNodesOut
connect ingressNodesIn, auto.ingress_nodes_in
connect auto.egress_nodes_out_0, egressNodesOut
connect auto.egress_nodes_out_1, egressNodesOut_1
connect auto.debug_out, debugNodeOut
inst input_unit_0_from_9 of InputUnit_10
connect input_unit_0_from_9.clock, clock
connect input_unit_0_from_9.reset, reset
inst ingress_unit_1_from_20 of IngressUnit_20
connect ingress_unit_1_from_20.clock, clock
connect ingress_unit_1_from_20.reset, reset
inst output_unit_0_to_11 of OutputUnit_10
connect output_unit_0_to_11.clock, clock
connect output_unit_0_to_11.reset, reset
inst egress_unit_1_to_13 of EgressUnit_13
connect egress_unit_1_to_13.clock, clock
connect egress_unit_1_to_13.reset, reset
inst egress_unit_2_to_14 of EgressUnit_14
connect egress_unit_2_to_14.clock, clock
connect egress_unit_2_to_14.reset, reset
inst switch of Switch_10
connect switch.clock, clock
connect switch.reset, reset
inst switch_allocator of SwitchAllocator_10
connect switch_allocator.clock, clock
connect switch_allocator.reset, reset
inst vc_allocator of RotatingSingleVCAllocator_10
connect vc_allocator.clock, clock
connect vc_allocator.reset, reset
inst route_computer of RouteComputer_10
connect route_computer.clock, clock
connect route_computer.reset, reset
node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid)
node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid)
node _fires_count_T_2 = add(_fires_count_T, _fires_count_T_1)
node _fires_count_T_3 = bits(_fires_count_T_2, 1, 0)
wire fires_count : UInt
connect fires_count, _fires_count_T_3
connect input_unit_0_from_9.io.in, destNodesIn
connect ingress_unit_1_from_20.io.in, ingressNodesIn.flit
connect output_unit_0_to_11.io.out.vc_free, sourceNodesOut.vc_free
connect output_unit_0_to_11.io.out.credit_return, sourceNodesOut.credit_return
connect sourceNodesOut.flit, output_unit_0_to_11.io.out.flit
connect egressNodesOut.flit.bits, egress_unit_1_to_13.io.out.bits
connect egressNodesOut.flit.valid, egress_unit_1_to_13.io.out.valid
connect egress_unit_1_to_13.io.out.ready, egressNodesOut.flit.ready
connect egressNodesOut_1.flit.bits, egress_unit_2_to_14.io.out.bits
connect egressNodesOut_1.flit.valid, egress_unit_2_to_14.io.out.valid
connect egress_unit_2_to_14.io.out.ready, egressNodesOut_1.flit.ready
connect route_computer.io.req.`0`, input_unit_0_from_9.io.router_req
connect route_computer.io.req.`1`, ingress_unit_1_from_20.io.router_req
connect input_unit_0_from_9.io.router_resp, route_computer.io.resp.`0`
connect ingress_unit_1_from_20.io.router_resp, route_computer.io.resp.`1`
connect vc_allocator.io.req.`0`, input_unit_0_from_9.io.vcalloc_req
connect vc_allocator.io.req.`1`, ingress_unit_1_from_20.io.vcalloc_req
connect input_unit_0_from_9.io.vcalloc_resp, vc_allocator.io.resp.`0`
connect ingress_unit_1_from_20.io.vcalloc_resp, vc_allocator.io.resp.`1`
connect output_unit_0_to_11.io.allocs, vc_allocator.io.out_allocs.`0`
connect egress_unit_1_to_13.io.allocs, vc_allocator.io.out_allocs.`1`
connect egress_unit_2_to_14.io.allocs, vc_allocator.io.out_allocs.`2`
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_11.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_11.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_11.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_11.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_11.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_11.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_11.io.channel_status[1].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_11.io.channel_status[1].flow.egress_node
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_11.io.channel_status[1].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_11.io.channel_status[1].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_11.io.channel_status[1].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_11.io.channel_status[1].occupied
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_11.io.channel_status[2].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_11.io.channel_status[2].flow.egress_node
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_11.io.channel_status[2].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_11.io.channel_status[2].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_11.io.channel_status[2].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_11.io.channel_status[2].occupied
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_11.io.channel_status[3].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_11.io.channel_status[3].flow.egress_node
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_11.io.channel_status[3].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_11.io.channel_status[3].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_11.io.channel_status[3].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_11.io.channel_status[3].occupied
connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_11.io.channel_status[4].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_11.io.channel_status[4].flow.egress_node
connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_11.io.channel_status[4].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_11.io.channel_status[4].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_11.io.channel_status[4].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_11.io.channel_status[4].occupied
connect vc_allocator.io.channel_status.`0`[5].flow.egress_node_id, output_unit_0_to_11.io.channel_status[5].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[5].flow.egress_node, output_unit_0_to_11.io.channel_status[5].flow.egress_node
connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node_id, output_unit_0_to_11.io.channel_status[5].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node, output_unit_0_to_11.io.channel_status[5].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[5].flow.vnet_id, output_unit_0_to_11.io.channel_status[5].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[5].occupied, output_unit_0_to_11.io.channel_status[5].occupied
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, egress_unit_1_to_13.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, egress_unit_1_to_13.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, egress_unit_1_to_13.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, egress_unit_1_to_13.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, egress_unit_1_to_13.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[0].occupied, egress_unit_1_to_13.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, egress_unit_2_to_14.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, egress_unit_2_to_14.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, egress_unit_2_to_14.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, egress_unit_2_to_14.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, egress_unit_2_to_14.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[0].occupied, egress_unit_2_to_14.io.channel_status[0].occupied
connect input_unit_0_from_9.io.out_credit_available.`0`[0], output_unit_0_to_11.io.credit_available[0]
connect input_unit_0_from_9.io.out_credit_available.`0`[1], output_unit_0_to_11.io.credit_available[1]
connect input_unit_0_from_9.io.out_credit_available.`0`[2], output_unit_0_to_11.io.credit_available[2]
connect input_unit_0_from_9.io.out_credit_available.`0`[3], output_unit_0_to_11.io.credit_available[3]
connect input_unit_0_from_9.io.out_credit_available.`0`[4], output_unit_0_to_11.io.credit_available[4]
connect input_unit_0_from_9.io.out_credit_available.`0`[5], output_unit_0_to_11.io.credit_available[5]
connect input_unit_0_from_9.io.out_credit_available.`1`[0], egress_unit_1_to_13.io.credit_available[0]
connect input_unit_0_from_9.io.out_credit_available.`2`[0], egress_unit_2_to_14.io.credit_available[0]
connect ingress_unit_1_from_20.io.out_credit_available.`0`[0], output_unit_0_to_11.io.credit_available[0]
connect ingress_unit_1_from_20.io.out_credit_available.`0`[1], output_unit_0_to_11.io.credit_available[1]
connect ingress_unit_1_from_20.io.out_credit_available.`0`[2], output_unit_0_to_11.io.credit_available[2]
connect ingress_unit_1_from_20.io.out_credit_available.`0`[3], output_unit_0_to_11.io.credit_available[3]
connect ingress_unit_1_from_20.io.out_credit_available.`0`[4], output_unit_0_to_11.io.credit_available[4]
connect ingress_unit_1_from_20.io.out_credit_available.`0`[5], output_unit_0_to_11.io.credit_available[5]
connect ingress_unit_1_from_20.io.out_credit_available.`1`[0], egress_unit_1_to_13.io.credit_available[0]
connect ingress_unit_1_from_20.io.out_credit_available.`2`[0], egress_unit_2_to_14.io.credit_available[0]
connect switch_allocator.io.req.`0`[0], input_unit_0_from_9.io.salloc_req[0]
connect switch_allocator.io.req.`1`[0], ingress_unit_1_from_20.io.salloc_req[0]
connect output_unit_0_to_11.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail
connect output_unit_0_to_11.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc
connect output_unit_0_to_11.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail
connect output_unit_0_to_11.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc
connect output_unit_0_to_11.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail
connect output_unit_0_to_11.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc
connect output_unit_0_to_11.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail
connect output_unit_0_to_11.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc
connect output_unit_0_to_11.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail
connect output_unit_0_to_11.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc
connect output_unit_0_to_11.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`0`[5].tail
connect output_unit_0_to_11.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`0`[5].alloc
connect egress_unit_1_to_13.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail
connect egress_unit_1_to_13.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc
connect egress_unit_2_to_14.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail
connect egress_unit_2_to_14.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc
connect switch.io.in.`0`[0], input_unit_0_from_9.io.out[0]
connect switch.io.in.`1`[0], ingress_unit_1_from_20.io.out[0]
connect output_unit_0_to_11.io.in, switch.io.out.`0`
connect egress_unit_1_to_13.io.in, switch.io.out.`1`
connect egress_unit_2_to_14.io.in, switch.io.out.`2`
reg REG : { `2` : { `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock
connect REG, switch_allocator.io.switch_sel
connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0]
connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0]
connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0]
connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0]
connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0]
connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0]
connect input_unit_0_from_9.io.block, UInt<1>(0h0)
connect ingress_unit_1_from_20.io.block, UInt<1>(0h0)
connect debugNodeOut.va_stall[0], input_unit_0_from_9.io.debug.va_stall
connect debugNodeOut.va_stall[1], ingress_unit_1_from_20.io.debug.va_stall
connect debugNodeOut.sa_stall[0], input_unit_0_from_9.io.debug.sa_stall
connect debugNodeOut.sa_stall[1], ingress_unit_1_from_20.io.debug.sa_stall
regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1))
node _debug_tsc_T_1 = tail(_debug_tsc_T, 1)
connect debug_tsc, _debug_tsc_T_1
regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_sample_T = add(debug_sample, UInt<1>(0h1))
node _debug_sample_T_1 = tail(_debug_sample_T, 1)
connect debug_sample, _debug_sample_T_1
inst plusarg_reader of plusarg_reader_28
node _T = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_1 = tail(_T, 1)
node _T_2 = eq(debug_sample, _T_1)
when _T_2 :
connect debug_sample, UInt<1>(0h0)
regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid)
node _util_ctr_T_1 = tail(_util_ctr_T, 1)
connect util_ctr, _util_ctr_T_1
node _fired_T = or(fired, destNodesIn.flit[0].valid)
connect fired, _fired_T
node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_5 = tail(_T_4, 1)
node _T_6 = eq(debug_sample, _T_5)
node _T_7 = and(_T_3, _T_6)
node _T_8 = and(_T_7, fired)
when _T_8 :
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
printf(clock, UInt<1>(0h1), "nocsample %d 9 10 %d\n", debug_tsc, util_ctr) : printf
connect fired, destNodesIn.flit[0].valid
node _T_11 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid)
regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_2 = add(util_ctr_1, _T_11)
node _util_ctr_T_3 = tail(_util_ctr_T_2, 1)
connect util_ctr_1, _util_ctr_T_3
node _fired_T_1 = or(fired_1, _T_11)
connect fired_1, _fired_T_1
node _T_12 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_13 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_14 = tail(_T_13, 1)
node _T_15 = eq(debug_sample, _T_14)
node _T_16 = and(_T_12, _T_15)
node _T_17 = and(_T_16, fired_1)
when _T_17 :
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "nocsample %d i20 10 %d\n", debug_tsc, util_ctr_1) : printf_1
connect fired_1, _T_11
node _T_20 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid)
regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_4 = add(util_ctr_2, _T_20)
node _util_ctr_T_5 = tail(_util_ctr_T_4, 1)
connect util_ctr_2, _util_ctr_T_5
node _fired_T_2 = or(fired_2, _T_20)
connect fired_2, _fired_T_2
node _T_21 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_22 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_23 = tail(_T_22, 1)
node _T_24 = eq(debug_sample, _T_23)
node _T_25 = and(_T_21, _T_24)
node _T_26 = and(_T_25, fired_2)
when _T_26 :
node _T_27 = asUInt(reset)
node _T_28 = eq(_T_27, UInt<1>(0h0))
when _T_28 :
printf(clock, UInt<1>(0h1), "nocsample %d 10 e13 %d\n", debug_tsc, util_ctr_2) : printf_2
connect fired_2, _T_20
node _T_29 = and(egressNodesOut_1.flit.ready, egressNodesOut_1.flit.valid)
regreset util_ctr_3 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_3 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_6 = add(util_ctr_3, _T_29)
node _util_ctr_T_7 = tail(_util_ctr_T_6, 1)
connect util_ctr_3, _util_ctr_T_7
node _fired_T_3 = or(fired_3, _T_29)
connect fired_3, _fired_T_3
node _T_30 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_31 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_32 = tail(_T_31, 1)
node _T_33 = eq(debug_sample, _T_32)
node _T_34 = and(_T_30, _T_33)
node _T_35 = and(_T_34, fired_3)
when _T_35 :
node _T_36 = asUInt(reset)
node _T_37 = eq(_T_36, UInt<1>(0h0))
when _T_37 :
printf(clock, UInt<1>(0h1), "nocsample %d 10 e14 %d\n", debug_tsc, util_ctr_3) : printf_3
connect fired_3, _T_29 | module Router_10( // @[Router.scala:89:25]
input clock, // @[Router.scala:89:25]
input reset, // @[Router.scala:89:25]
output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_ingress_nodes_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_ingress_nodes_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25]
);
wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _route_computer_io_resp_1_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_3; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_4; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_5; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_3; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_4; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_5; // @[Router.scala:136:32]
wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30]
wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34]
wire _switch_io_out_2_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_1_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_0_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _egress_unit_2_to_14_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_2_to_14_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_2_to_14_io_out_valid; // @[Router.scala:125:13]
wire _egress_unit_1_to_13_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_1_to_13_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_1_to_13_io_out_valid; // @[Router.scala:125:13]
wire _output_unit_0_to_11_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_0_to_11_io_credit_available_2; // @[Router.scala:122:13]
wire _output_unit_0_to_11_io_credit_available_3; // @[Router.scala:122:13]
wire _output_unit_0_to_11_io_credit_available_4; // @[Router.scala:122:13]
wire _output_unit_0_to_11_io_credit_available_5; // @[Router.scala:122:13]
wire _output_unit_0_to_11_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_11_io_channel_status_2_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_11_io_channel_status_3_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_11_io_channel_status_4_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_11_io_channel_status_5_occupied; // @[Router.scala:122:13]
wire [3:0] _ingress_unit_1_from_20_io_router_req_bits_flow_egress_node; // @[Router.scala:116:13]
wire _ingress_unit_1_from_20_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_20_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_20_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_20_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_20_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_1_from_20_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_1_from_20_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_1_from_20_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_1_from_20_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_1_from_20_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_20_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_20_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_20_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_20_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_1_from_20_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_1_from_20_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_1_from_20_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_1_from_20_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_1_from_20_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_1_from_20_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_20_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_1_from_20_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [72:0] _ingress_unit_1_from_20_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_1_from_20_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_1_from_20_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_1_from_20_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_1_from_20_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_1_from_20_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_1_from_20_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_1_from_20_io_in_ready; // @[Router.scala:116:13]
wire [2:0] _input_unit_0_from_9_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_9_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_9_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_9_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_9_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_9_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_0_from_9_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_9_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_9_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_9_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_9_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_9_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_9_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_9_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_20_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35]
reg REG_2_0_1_0; // @[Router.scala:178:14]
reg REG_2_0_0_0; // @[Router.scala:178:14]
reg REG_1_0_1_0; // @[Router.scala:178:14]
reg REG_1_0_0_0; // @[Router.scala:178:14]
reg REG_0_0_1_0; // @[Router.scala:178:14]
reg REG_0_0_0_0; // @[Router.scala:178:14]
reg [63:0] debug_tsc; // @[Router.scala:195:28]
reg [63:0] debug_sample; // @[Router.scala:197:31]
wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11]
reg [63:0] util_ctr; // @[Router.scala:203:29]
reg fired; // @[Router.scala:204:26]
wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11]
wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_1; // @[Router.scala:203:29]
reg fired_1; // @[Router.scala:204:26]
wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_2; // @[Router.scala:203:29]
reg fired_2; // @[Router.scala:204:26]
wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_3; // @[Router.scala:203:29]
reg fired_3; // @[Router.scala:204:26]
wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}] |
Generate the Verilog code corresponding to this FIRRTL code module TLNoC_router_6ClockSinkDomain :
output auto : { routers_debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, routers_egress_nodes_out_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, routers_egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, routers_egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip routers_ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip routers_ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, routers_source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip routers_dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst routers of Router_6
connect routers.clock, childClock
connect routers.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
connect clockNodeIn, auto.clock_in
connect routers.auto.dest_nodes_in, auto.routers_dest_nodes_in
connect routers.auto.source_nodes_out.vc_free, auto.routers_source_nodes_out.vc_free
connect routers.auto.source_nodes_out.credit_return, auto.routers_source_nodes_out.credit_return
connect auto.routers_source_nodes_out.flit, routers.auto.source_nodes_out.flit
connect routers.auto.ingress_nodes_in_0, auto.routers_ingress_nodes_in_0
connect routers.auto.ingress_nodes_in_1, auto.routers_ingress_nodes_in_1
connect auto.routers_egress_nodes_out_0.flit.bits, routers.auto.egress_nodes_out_0.flit.bits
connect auto.routers_egress_nodes_out_0.flit.valid, routers.auto.egress_nodes_out_0.flit.valid
connect routers.auto.egress_nodes_out_0.flit.ready, auto.routers_egress_nodes_out_0.flit.ready
connect auto.routers_egress_nodes_out_1.flit.bits, routers.auto.egress_nodes_out_1.flit.bits
connect auto.routers_egress_nodes_out_1.flit.valid, routers.auto.egress_nodes_out_1.flit.valid
connect routers.auto.egress_nodes_out_1.flit.ready, auto.routers_egress_nodes_out_1.flit.ready
connect auto.routers_egress_nodes_out_2.flit.bits, routers.auto.egress_nodes_out_2.flit.bits
connect auto.routers_egress_nodes_out_2.flit.valid, routers.auto.egress_nodes_out_2.flit.valid
connect routers.auto.egress_nodes_out_2.flit.ready, auto.routers_egress_nodes_out_2.flit.ready
connect auto.routers_debug_out, routers.auto.debug_out
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset | module TLNoC_router_6ClockSinkDomain( // @[ClockDomain.scala:14:9]
output [2:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_2_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_2_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_2_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_egress_nodes_out_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_routers_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_routers_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
Router_6 routers ( // @[NoC.scala:67:22]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0),
.auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1),
.auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2),
.auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0),
.auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1),
.auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2),
.auto_egress_nodes_out_2_flit_valid (auto_routers_egress_nodes_out_2_flit_valid),
.auto_egress_nodes_out_2_flit_bits_head (auto_routers_egress_nodes_out_2_flit_bits_head),
.auto_egress_nodes_out_2_flit_bits_tail (auto_routers_egress_nodes_out_2_flit_bits_tail),
.auto_egress_nodes_out_2_flit_bits_payload (auto_routers_egress_nodes_out_2_flit_bits_payload),
.auto_egress_nodes_out_1_flit_ready (auto_routers_egress_nodes_out_1_flit_ready),
.auto_egress_nodes_out_1_flit_valid (auto_routers_egress_nodes_out_1_flit_valid),
.auto_egress_nodes_out_1_flit_bits_head (auto_routers_egress_nodes_out_1_flit_bits_head),
.auto_egress_nodes_out_1_flit_bits_tail (auto_routers_egress_nodes_out_1_flit_bits_tail),
.auto_egress_nodes_out_1_flit_bits_payload (auto_routers_egress_nodes_out_1_flit_bits_payload),
.auto_egress_nodes_out_0_flit_ready (auto_routers_egress_nodes_out_0_flit_ready),
.auto_egress_nodes_out_0_flit_valid (auto_routers_egress_nodes_out_0_flit_valid),
.auto_egress_nodes_out_0_flit_bits_head (auto_routers_egress_nodes_out_0_flit_bits_head),
.auto_egress_nodes_out_0_flit_bits_tail (auto_routers_egress_nodes_out_0_flit_bits_tail),
.auto_egress_nodes_out_0_flit_bits_payload (auto_routers_egress_nodes_out_0_flit_bits_payload),
.auto_ingress_nodes_in_1_flit_ready (auto_routers_ingress_nodes_in_1_flit_ready),
.auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid),
.auto_ingress_nodes_in_1_flit_bits_head (auto_routers_ingress_nodes_in_1_flit_bits_head),
.auto_ingress_nodes_in_1_flit_bits_tail (auto_routers_ingress_nodes_in_1_flit_bits_tail),
.auto_ingress_nodes_in_1_flit_bits_payload (auto_routers_ingress_nodes_in_1_flit_bits_payload),
.auto_ingress_nodes_in_1_flit_bits_egress_id (auto_routers_ingress_nodes_in_1_flit_bits_egress_id),
.auto_ingress_nodes_in_0_flit_ready (auto_routers_ingress_nodes_in_0_flit_ready),
.auto_ingress_nodes_in_0_flit_valid (auto_routers_ingress_nodes_in_0_flit_valid),
.auto_ingress_nodes_in_0_flit_bits_head (auto_routers_ingress_nodes_in_0_flit_bits_head),
.auto_ingress_nodes_in_0_flit_bits_tail (auto_routers_ingress_nodes_in_0_flit_bits_tail),
.auto_ingress_nodes_in_0_flit_bits_payload (auto_routers_ingress_nodes_in_0_flit_bits_payload),
.auto_ingress_nodes_in_0_flit_bits_egress_id (auto_routers_ingress_nodes_in_0_flit_bits_egress_id),
.auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid),
.auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head),
.auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail),
.auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload),
.auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return),
.auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free),
.auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid),
.auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head),
.auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail),
.auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload),
.auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return),
.auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free)
); // @[NoC.scala:67:22]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_131 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_131( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ListBuffer_QueuedRequest_q21_e33 :
input clock : Clock
input reset : Reset
output io : { flip push : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<5>, data : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, tag : UInt<12>, offset : UInt<6>, put : UInt<6>}}}, valid : UInt<21>, flip pop : { valid : UInt<1>, bits : UInt<5>}, data : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, tag : UInt<12>, offset : UInt<6>, put : UInt<6>}}
regreset valid : UInt<21>, clock, reset, UInt<21>(0h0)
cmem head : UInt<6> [21]
cmem tail : UInt<6> [21]
regreset used : UInt<33>, clock, reset, UInt<33>(0h0)
cmem next : UInt<6> [33]
cmem data : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, tag : UInt<12>, offset : UInt<6>, put : UInt<6>} [33]
node _freeOH_T = not(used)
node _freeOH_T_1 = shl(_freeOH_T, 1)
node _freeOH_T_2 = bits(_freeOH_T_1, 32, 0)
node _freeOH_T_3 = or(_freeOH_T, _freeOH_T_2)
node _freeOH_T_4 = shl(_freeOH_T_3, 2)
node _freeOH_T_5 = bits(_freeOH_T_4, 32, 0)
node _freeOH_T_6 = or(_freeOH_T_3, _freeOH_T_5)
node _freeOH_T_7 = shl(_freeOH_T_6, 4)
node _freeOH_T_8 = bits(_freeOH_T_7, 32, 0)
node _freeOH_T_9 = or(_freeOH_T_6, _freeOH_T_8)
node _freeOH_T_10 = shl(_freeOH_T_9, 8)
node _freeOH_T_11 = bits(_freeOH_T_10, 32, 0)
node _freeOH_T_12 = or(_freeOH_T_9, _freeOH_T_11)
node _freeOH_T_13 = shl(_freeOH_T_12, 16)
node _freeOH_T_14 = bits(_freeOH_T_13, 32, 0)
node _freeOH_T_15 = or(_freeOH_T_12, _freeOH_T_14)
node _freeOH_T_16 = shl(_freeOH_T_15, 32)
node _freeOH_T_17 = bits(_freeOH_T_16, 32, 0)
node _freeOH_T_18 = or(_freeOH_T_15, _freeOH_T_17)
node _freeOH_T_19 = bits(_freeOH_T_18, 32, 0)
node _freeOH_T_20 = shl(_freeOH_T_19, 1)
node _freeOH_T_21 = not(_freeOH_T_20)
node _freeOH_T_22 = not(used)
node freeOH = and(_freeOH_T_21, _freeOH_T_22)
node freeIdx_hi = bits(freeOH, 33, 32)
node freeIdx_lo = bits(freeOH, 31, 0)
node _freeIdx_T = orr(freeIdx_hi)
node _freeIdx_T_1 = or(freeIdx_hi, freeIdx_lo)
node freeIdx_hi_1 = bits(_freeIdx_T_1, 31, 16)
node freeIdx_lo_1 = bits(_freeIdx_T_1, 15, 0)
node _freeIdx_T_2 = orr(freeIdx_hi_1)
node _freeIdx_T_3 = or(freeIdx_hi_1, freeIdx_lo_1)
node freeIdx_hi_2 = bits(_freeIdx_T_3, 15, 8)
node freeIdx_lo_2 = bits(_freeIdx_T_3, 7, 0)
node _freeIdx_T_4 = orr(freeIdx_hi_2)
node _freeIdx_T_5 = or(freeIdx_hi_2, freeIdx_lo_2)
node freeIdx_hi_3 = bits(_freeIdx_T_5, 7, 4)
node freeIdx_lo_3 = bits(_freeIdx_T_5, 3, 0)
node _freeIdx_T_6 = orr(freeIdx_hi_3)
node _freeIdx_T_7 = or(freeIdx_hi_3, freeIdx_lo_3)
node freeIdx_hi_4 = bits(_freeIdx_T_7, 3, 2)
node freeIdx_lo_4 = bits(_freeIdx_T_7, 1, 0)
node _freeIdx_T_8 = orr(freeIdx_hi_4)
node _freeIdx_T_9 = or(freeIdx_hi_4, freeIdx_lo_4)
node _freeIdx_T_10 = bits(_freeIdx_T_9, 1, 1)
node _freeIdx_T_11 = cat(_freeIdx_T_8, _freeIdx_T_10)
node _freeIdx_T_12 = cat(_freeIdx_T_6, _freeIdx_T_11)
node _freeIdx_T_13 = cat(_freeIdx_T_4, _freeIdx_T_12)
node _freeIdx_T_14 = cat(_freeIdx_T_2, _freeIdx_T_13)
node freeIdx = cat(_freeIdx_T, _freeIdx_T_14)
wire valid_set : UInt<21>
connect valid_set, UInt<21>(0h0)
wire valid_clr : UInt<21>
connect valid_clr, UInt<21>(0h0)
wire used_set : UInt<33>
connect used_set, UInt<33>(0h0)
wire used_clr : UInt<33>
connect used_clr, UInt<33>(0h0)
read mport push_tail = tail[io.push.bits.index], clock
node _push_valid_T = dshr(valid, io.push.bits.index)
node push_valid = bits(_push_valid_T, 0, 0)
node _io_push_ready_T = andr(used)
node _io_push_ready_T_1 = eq(_io_push_ready_T, UInt<1>(0h0))
connect io.push.ready, _io_push_ready_T_1
node _T = and(io.push.ready, io.push.valid)
when _T :
node valid_set_shiftAmount = bits(io.push.bits.index, 4, 0)
node _valid_set_T = dshl(UInt<1>(0h1), valid_set_shiftAmount)
node _valid_set_T_1 = bits(_valid_set_T, 20, 0)
connect valid_set, _valid_set_T_1
connect used_set, freeOH
write mport MPORT = data[freeIdx], clock
connect MPORT, io.push.bits.data
when push_valid :
write mport MPORT_1 = next[push_tail], clock
connect MPORT_1, freeIdx
else :
write mport MPORT_2 = head[io.push.bits.index], clock
connect MPORT_2, freeIdx
write mport MPORT_3 = tail[io.push.bits.index], clock
connect MPORT_3, freeIdx
read mport pop_head = head[io.pop.bits], clock
node _pop_valid_T = dshr(valid, io.pop.bits)
node pop_valid = bits(_pop_valid_T, 0, 0)
read mport io_data_MPORT = data[pop_head], clock
connect io.data, io_data_MPORT
connect io.valid, valid
node _T_1 = eq(io.pop.valid, UInt<1>(0h0))
node _T_2 = dshr(io.valid, io.pop.bits)
node _T_3 = bits(_T_2, 0, 0)
node _T_4 = or(_T_1, _T_3)
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
node _T_7 = eq(_T_4, UInt<1>(0h0))
when _T_7 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at ListBuffer.scala:86 assert (!io.pop.fire || (io.valid)(io.pop.bits))\n") : printf
assert(clock, _T_4, UInt<1>(0h1), "") : assert
when io.pop.valid :
node used_clr_shiftAmount = bits(pop_head, 5, 0)
node _used_clr_T = dshl(UInt<1>(0h1), used_clr_shiftAmount)
node _used_clr_T_1 = bits(_used_clr_T, 32, 0)
connect used_clr, _used_clr_T_1
read mport MPORT_4 = tail[io.pop.bits], clock
node _T_8 = eq(pop_head, MPORT_4)
when _T_8 :
node valid_clr_shiftAmount = bits(io.pop.bits, 4, 0)
node _valid_clr_T = dshl(UInt<1>(0h1), valid_clr_shiftAmount)
node _valid_clr_T_1 = bits(_valid_clr_T, 20, 0)
connect valid_clr, _valid_clr_T_1
node _T_9 = and(io.push.ready, io.push.valid)
node _T_10 = and(_T_9, push_valid)
node _T_11 = eq(push_tail, pop_head)
node _T_12 = and(_T_10, _T_11)
read mport MPORT_5 = next[pop_head], clock
node _T_13 = mux(_T_12, freeIdx, MPORT_5)
write mport MPORT_6 = head[io.pop.bits], clock
connect MPORT_6, _T_13
node _T_14 = eq(io.pop.valid, UInt<1>(0h0))
node _T_15 = or(UInt<1>(0h1), _T_14)
node _T_16 = or(_T_15, pop_valid)
when _T_16 :
node _used_T = not(used_clr)
node _used_T_1 = and(used, _used_T)
node _used_T_2 = or(_used_T_1, used_set)
connect used, _used_T_2
node _valid_T = not(valid_clr)
node _valid_T_1 = and(valid, _valid_T)
node _valid_T_2 = or(_valid_T_1, valid_set)
connect valid, _valid_T_2 | module ListBuffer_QueuedRequest_q21_e33( // @[ListBuffer.scala:36:7]
input clock, // @[ListBuffer.scala:36:7]
input reset, // @[ListBuffer.scala:36:7]
output io_push_ready, // @[ListBuffer.scala:39:14]
input io_push_valid, // @[ListBuffer.scala:39:14]
input [4:0] io_push_bits_index, // @[ListBuffer.scala:39:14]
input io_push_bits_data_prio_0, // @[ListBuffer.scala:39:14]
input io_push_bits_data_prio_2, // @[ListBuffer.scala:39:14]
input io_push_bits_data_control, // @[ListBuffer.scala:39:14]
input [2:0] io_push_bits_data_opcode, // @[ListBuffer.scala:39:14]
input [2:0] io_push_bits_data_param, // @[ListBuffer.scala:39:14]
input [2:0] io_push_bits_data_size, // @[ListBuffer.scala:39:14]
input [4:0] io_push_bits_data_source, // @[ListBuffer.scala:39:14]
input [11:0] io_push_bits_data_tag, // @[ListBuffer.scala:39:14]
input [5:0] io_push_bits_data_offset, // @[ListBuffer.scala:39:14]
input [5:0] io_push_bits_data_put, // @[ListBuffer.scala:39:14]
output [20:0] io_valid, // @[ListBuffer.scala:39:14]
input io_pop_valid, // @[ListBuffer.scala:39:14]
input [4:0] io_pop_bits, // @[ListBuffer.scala:39:14]
output io_data_prio_0, // @[ListBuffer.scala:39:14]
output io_data_prio_1, // @[ListBuffer.scala:39:14]
output io_data_prio_2, // @[ListBuffer.scala:39:14]
output io_data_control, // @[ListBuffer.scala:39:14]
output [2:0] io_data_opcode, // @[ListBuffer.scala:39:14]
output [2:0] io_data_param, // @[ListBuffer.scala:39:14]
output [2:0] io_data_size, // @[ListBuffer.scala:39:14]
output [4:0] io_data_source, // @[ListBuffer.scala:39:14]
output [11:0] io_data_tag, // @[ListBuffer.scala:39:14]
output [5:0] io_data_offset, // @[ListBuffer.scala:39:14]
output [5:0] io_data_put // @[ListBuffer.scala:39:14]
);
wire [41:0] _data_ext_R0_data; // @[ListBuffer.scala:52:18]
wire [5:0] _next_ext_R0_data; // @[ListBuffer.scala:51:18]
wire [5:0] _tail_ext_R0_data; // @[ListBuffer.scala:49:18]
wire [5:0] _tail_ext_R1_data; // @[ListBuffer.scala:49:18]
wire [5:0] _head_ext_R0_data; // @[ListBuffer.scala:48:18]
wire io_push_valid_0 = io_push_valid; // @[ListBuffer.scala:36:7]
wire [4:0] io_push_bits_index_0 = io_push_bits_index; // @[ListBuffer.scala:36:7]
wire io_push_bits_data_prio_0_0 = io_push_bits_data_prio_0; // @[ListBuffer.scala:36:7]
wire io_push_bits_data_prio_2_0 = io_push_bits_data_prio_2; // @[ListBuffer.scala:36:7]
wire io_push_bits_data_control_0 = io_push_bits_data_control; // @[ListBuffer.scala:36:7]
wire [2:0] io_push_bits_data_opcode_0 = io_push_bits_data_opcode; // @[ListBuffer.scala:36:7]
wire [2:0] io_push_bits_data_param_0 = io_push_bits_data_param; // @[ListBuffer.scala:36:7]
wire [2:0] io_push_bits_data_size_0 = io_push_bits_data_size; // @[ListBuffer.scala:36:7]
wire [4:0] io_push_bits_data_source_0 = io_push_bits_data_source; // @[ListBuffer.scala:36:7]
wire [11:0] io_push_bits_data_tag_0 = io_push_bits_data_tag; // @[ListBuffer.scala:36:7]
wire [5:0] io_push_bits_data_offset_0 = io_push_bits_data_offset; // @[ListBuffer.scala:36:7]
wire [5:0] io_push_bits_data_put_0 = io_push_bits_data_put; // @[ListBuffer.scala:36:7]
wire io_pop_valid_0 = io_pop_valid; // @[ListBuffer.scala:36:7]
wire [4:0] io_pop_bits_0 = io_pop_bits; // @[ListBuffer.scala:36:7]
wire io_push_bits_data_prio_1 = 1'h0; // @[ListBuffer.scala:36:7]
wire _io_push_ready_T_1; // @[ListBuffer.scala:65:20]
wire [4:0] valid_set_shiftAmount = io_push_bits_index_0; // @[OneHot.scala:64:49]
wire [4:0] valid_clr_shiftAmount = io_pop_bits_0; // @[OneHot.scala:64:49]
wire io_push_ready_0; // @[ListBuffer.scala:36:7]
wire io_data_prio_0_0; // @[ListBuffer.scala:36:7]
wire io_data_prio_1_0; // @[ListBuffer.scala:36:7]
wire io_data_prio_2_0; // @[ListBuffer.scala:36:7]
wire io_data_control_0; // @[ListBuffer.scala:36:7]
wire [2:0] io_data_opcode_0; // @[ListBuffer.scala:36:7]
wire [2:0] io_data_param_0; // @[ListBuffer.scala:36:7]
wire [2:0] io_data_size_0; // @[ListBuffer.scala:36:7]
wire [4:0] io_data_source_0; // @[ListBuffer.scala:36:7]
wire [11:0] io_data_tag_0; // @[ListBuffer.scala:36:7]
wire [5:0] io_data_offset_0; // @[ListBuffer.scala:36:7]
wire [5:0] io_data_put_0; // @[ListBuffer.scala:36:7]
wire [20:0] io_valid_0; // @[ListBuffer.scala:36:7]
reg [20:0] valid; // @[ListBuffer.scala:47:22]
assign io_valid_0 = valid; // @[ListBuffer.scala:36:7, :47:22]
reg [32:0] used; // @[ListBuffer.scala:50:22]
assign io_data_prio_0_0 = _data_ext_R0_data[0]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_prio_1_0 = _data_ext_R0_data[1]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_prio_2_0 = _data_ext_R0_data[2]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_control_0 = _data_ext_R0_data[3]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_opcode_0 = _data_ext_R0_data[6:4]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_param_0 = _data_ext_R0_data[9:7]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_size_0 = _data_ext_R0_data[12:10]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_source_0 = _data_ext_R0_data[17:13]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_tag_0 = _data_ext_R0_data[29:18]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_offset_0 = _data_ext_R0_data[35:30]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_put_0 = _data_ext_R0_data[41:36]; // @[ListBuffer.scala:36:7, :52:18]
wire [32:0] _freeOH_T = ~used; // @[ListBuffer.scala:50:22, :54:25]
wire [33:0] _freeOH_T_1 = {_freeOH_T, 1'h0}; // @[package.scala:253:48]
wire [32:0] _freeOH_T_2 = _freeOH_T_1[32:0]; // @[package.scala:253:{48,53}]
wire [32:0] _freeOH_T_3 = _freeOH_T | _freeOH_T_2; // @[package.scala:253:{43,53}]
wire [34:0] _freeOH_T_4 = {_freeOH_T_3, 2'h0}; // @[package.scala:253:{43,48}]
wire [32:0] _freeOH_T_5 = _freeOH_T_4[32:0]; // @[package.scala:253:{48,53}]
wire [32:0] _freeOH_T_6 = _freeOH_T_3 | _freeOH_T_5; // @[package.scala:253:{43,53}]
wire [36:0] _freeOH_T_7 = {_freeOH_T_6, 4'h0}; // @[package.scala:253:{43,48}]
wire [32:0] _freeOH_T_8 = _freeOH_T_7[32:0]; // @[package.scala:253:{48,53}]
wire [32:0] _freeOH_T_9 = _freeOH_T_6 | _freeOH_T_8; // @[package.scala:253:{43,53}]
wire [40:0] _freeOH_T_10 = {_freeOH_T_9, 8'h0}; // @[package.scala:253:{43,48}]
wire [32:0] _freeOH_T_11 = _freeOH_T_10[32:0]; // @[package.scala:253:{48,53}]
wire [32:0] _freeOH_T_12 = _freeOH_T_9 | _freeOH_T_11; // @[package.scala:253:{43,53}]
wire [48:0] _freeOH_T_13 = {_freeOH_T_12, 16'h0}; // @[package.scala:253:{43,48}]
wire [32:0] _freeOH_T_14 = _freeOH_T_13[32:0]; // @[package.scala:253:{48,53}]
wire [32:0] _freeOH_T_15 = _freeOH_T_12 | _freeOH_T_14; // @[package.scala:253:{43,53}]
wire [64:0] _freeOH_T_16 = {_freeOH_T_15, 32'h0}; // @[package.scala:253:{43,48}]
wire [32:0] _freeOH_T_17 = _freeOH_T_16[32:0]; // @[package.scala:253:{48,53}]
wire [32:0] _freeOH_T_18 = _freeOH_T_15 | _freeOH_T_17; // @[package.scala:253:{43,53}]
wire [32:0] _freeOH_T_19 = _freeOH_T_18; // @[package.scala:253:43, :254:17]
wire [33:0] _freeOH_T_20 = {_freeOH_T_19, 1'h0}; // @[package.scala:254:17]
wire [33:0] _freeOH_T_21 = ~_freeOH_T_20; // @[ListBuffer.scala:54:{16,32}]
wire [32:0] _freeOH_T_22 = ~used; // @[ListBuffer.scala:50:22, :54:{25,40}]
wire [33:0] freeOH = {1'h0, _freeOH_T_21[32:0] & _freeOH_T_22}; // @[ListBuffer.scala:54:{16,38,40}]
wire [1:0] freeIdx_hi = freeOH[33:32]; // @[OneHot.scala:30:18]
wire [31:0] freeIdx_lo = freeOH[31:0]; // @[OneHot.scala:31:18]
wire _freeIdx_T = |freeIdx_hi; // @[OneHot.scala:30:18, :32:14]
wire [31:0] _freeIdx_T_1 = {30'h0, freeIdx_hi} | freeIdx_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [15:0] freeIdx_hi_1 = _freeIdx_T_1[31:16]; // @[OneHot.scala:30:18, :32:28]
wire [15:0] freeIdx_lo_1 = _freeIdx_T_1[15:0]; // @[OneHot.scala:31:18, :32:28]
wire _freeIdx_T_2 = |freeIdx_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [15:0] _freeIdx_T_3 = freeIdx_hi_1 | freeIdx_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [7:0] freeIdx_hi_2 = _freeIdx_T_3[15:8]; // @[OneHot.scala:30:18, :32:28]
wire [7:0] freeIdx_lo_2 = _freeIdx_T_3[7:0]; // @[OneHot.scala:31:18, :32:28]
wire _freeIdx_T_4 = |freeIdx_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _freeIdx_T_5 = freeIdx_hi_2 | freeIdx_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] freeIdx_hi_3 = _freeIdx_T_5[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] freeIdx_lo_3 = _freeIdx_T_5[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _freeIdx_T_6 = |freeIdx_hi_3; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _freeIdx_T_7 = freeIdx_hi_3 | freeIdx_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] freeIdx_hi_4 = _freeIdx_T_7[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] freeIdx_lo_4 = _freeIdx_T_7[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _freeIdx_T_8 = |freeIdx_hi_4; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _freeIdx_T_9 = freeIdx_hi_4 | freeIdx_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _freeIdx_T_10 = _freeIdx_T_9[1]; // @[OneHot.scala:32:28]
wire [1:0] _freeIdx_T_11 = {_freeIdx_T_8, _freeIdx_T_10}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _freeIdx_T_12 = {_freeIdx_T_6, _freeIdx_T_11}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _freeIdx_T_13 = {_freeIdx_T_4, _freeIdx_T_12}; // @[OneHot.scala:32:{10,14}]
wire [4:0] _freeIdx_T_14 = {_freeIdx_T_2, _freeIdx_T_13}; // @[OneHot.scala:32:{10,14}]
wire [5:0] freeIdx = {_freeIdx_T, _freeIdx_T_14}; // @[OneHot.scala:32:{10,14}]
wire [20:0] valid_set; // @[ListBuffer.scala:57:30]
wire [20:0] valid_clr; // @[ListBuffer.scala:58:30]
wire [32:0] used_set; // @[ListBuffer.scala:59:30]
wire [32:0] used_clr; // @[ListBuffer.scala:60:30]
wire [20:0] _push_valid_T = valid >> io_push_bits_index_0; // @[ListBuffer.scala:36:7, :47:22, :63:25]
wire push_valid = _push_valid_T[0]; // @[ListBuffer.scala:63:25]
wire _io_push_ready_T = &used; // @[ListBuffer.scala:50:22, :65:26]
assign _io_push_ready_T_1 = ~_io_push_ready_T; // @[ListBuffer.scala:65:{20,26}]
assign io_push_ready_0 = _io_push_ready_T_1; // @[ListBuffer.scala:36:7, :65:20]
wire data_MPORT_en = io_push_ready_0 & io_push_valid_0; // @[Decoupled.scala:51:35]
wire [31:0] _valid_set_T = 32'h1 << valid_set_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [20:0] _valid_set_T_1 = _valid_set_T[20:0]; // @[OneHot.scala:65:{12,27}]
assign valid_set = data_MPORT_en ? _valid_set_T_1 : 21'h0; // @[OneHot.scala:65:27]
assign used_set = data_MPORT_en ? freeOH[32:0] : 33'h0; // @[Decoupled.scala:51:35]
wire [20:0] _GEN = {16'h0, io_pop_bits_0}; // @[ListBuffer.scala:36:7, :79:24]
wire [20:0] _pop_valid_T = valid >> _GEN; // @[ListBuffer.scala:47:22, :79:24]
wire pop_valid = _pop_valid_T[0]; // @[ListBuffer.scala:79:24] |
Generate the Verilog code corresponding to this FIRRTL code module MSHR_2 :
input clock : Clock
input reset : Reset
output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}}
regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock
regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock
when meta_valid :
node _T = eq(meta.state, UInt<2>(0h0))
when _T :
node _T_1 = orr(meta.clients)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _T_6 = eq(meta.dirty, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = eq(meta.state, UInt<2>(0h1))
when _T_10 :
node _T_11 = eq(meta.dirty, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = eq(meta.state, UInt<2>(0h2))
when _T_15 :
node _T_16 = orr(meta.clients)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = sub(meta.clients, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = and(meta.clients, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4
assert(clock, _T_23, UInt<1>(0h1), "") : assert_4
node _T_27 = eq(meta.state, UInt<2>(0h3))
when _T_27 :
skip
regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1)
reg sink : UInt<3>, clock
reg gotT : UInt<1>, clock
reg bad_grant : UInt<1>, clock
reg probes_done : UInt<1>, clock
reg probes_toN : UInt<1>, clock
reg probes_noT : UInt<1>, clock
node _T_28 = neq(meta.state, UInt<2>(0h0))
node _T_29 = and(meta_valid, _T_28)
node _T_30 = eq(io.nestedwb.set, request.set)
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.nestedwb.tag, meta.tag)
node _T_33 = and(_T_31, _T_32)
when _T_33 :
when io.nestedwb.b_clr_dirty :
connect meta.dirty, UInt<1>(0h0)
when io.nestedwb.c_set_dirty :
connect meta.dirty, UInt<1>(0h1)
when io.nestedwb.b_toB :
connect meta.state, UInt<2>(0h1)
when io.nestedwb.b_toN :
connect meta.hit, UInt<1>(0h0)
connect io.status.valid, request_valid
connect io.status.bits.set, request.set
connect io.status.bits.tag, request.tag
connect io.status.bits.way, meta.way
node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0))
node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0))
node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2)
node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4)
node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6)
node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7)
connect io.status.bits.blockB, _io_status_bits_blockB_T_8
node _io_status_bits_nestB_T = and(meta_valid, w_releaseack)
node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast)
node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast)
node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3)
connect io.status.bits.nestB, _io_status_bits_nestB_T_4
node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0))
connect io.status.bits.blockC, _io_status_bits_blockC_T
node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1)
node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3)
node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4)
connect io.status.bits.nestC, _io_status_bits_nestC_T_5
node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0))
node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5
assert(clock, _T_36, UInt<1>(0h1), "") : assert_5
node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0))
node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6
assert(clock, _T_42, UInt<1>(0h1), "") : assert_6
node _no_wait_T = and(w_rprobeacklast, w_releaseack)
node _no_wait_T_1 = and(_no_wait_T, w_grantlast)
node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast)
node no_wait = and(_no_wait_T_2, w_grantack)
node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0))
node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release)
node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe)
connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2
node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1)
connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2
node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst)
node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst)
node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3)
connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4
node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0))
node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack)
node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant)
connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2
node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0))
node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst)
connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1
node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0))
node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack)
connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1
node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst)
node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait)
node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3)
connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4
connect io.schedule.bits.reload, no_wait
node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid)
node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid)
node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid)
node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid)
node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid)
node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid)
connect io.schedule.valid, _io_schedule_valid_T_5
when io.schedule.ready :
connect s_rprobe, UInt<1>(0h1)
when w_rprobeackfirst :
connect s_release, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
node _T_46 = and(s_release, s_pprobe)
when _T_46 :
connect s_acquire, UInt<1>(0h1)
when w_releaseack :
connect s_flush, UInt<1>(0h1)
when w_pprobeackfirst :
connect s_probeack, UInt<1>(0h1)
when w_grantfirst :
connect s_grantack, UInt<1>(0h1)
node _T_47 = and(w_pprobeack, w_grant)
when _T_47 :
connect s_execute, UInt<1>(0h1)
when no_wait :
connect s_writeback, UInt<1>(0h1)
when no_wait :
connect request_valid, UInt<1>(0h0)
connect meta_valid, UInt<1>(0h0)
wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}
connect final_meta_writeback, meta
node _req_clientBit_uncommonBits_T = or(request.source, UInt<2>(0h0))
node req_clientBit_uncommonBits = bits(_req_clientBit_uncommonBits_T, 1, 0)
node _req_clientBit_T = shr(request.source, 2)
node _req_clientBit_T_1 = eq(_req_clientBit_T, UInt<4>(0h8))
node _req_clientBit_T_2 = leq(UInt<1>(0h0), req_clientBit_uncommonBits)
node _req_clientBit_T_3 = and(_req_clientBit_T_1, _req_clientBit_T_2)
node _req_clientBit_T_4 = leq(req_clientBit_uncommonBits, UInt<2>(0h3))
node req_clientBit = and(_req_clientBit_T_3, _req_clientBit_T_4)
node _req_needT_T = bits(request.opcode, 2, 2)
node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0))
node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5))
node _req_needT_T_3 = eq(request.param, UInt<1>(0h1))
node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3)
node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4)
node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6))
node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7))
node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7)
node _req_needT_T_9 = neq(request.param, UInt<2>(0h0))
node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9)
node req_needT = or(_req_needT_T_5, _req_needT_T_10)
node _req_acquire_T = eq(request.opcode, UInt<3>(0h6))
node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7))
node req_acquire = or(_req_acquire_T, _req_acquire_T_1)
node _meta_no_clients_T = orr(meta.clients)
node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0))
node _req_promoteT_T = eq(meta.state, UInt<2>(0h3))
node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T)
node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT)
node req_promoteT = and(req_acquire, _req_promoteT_T_2)
node _T_48 = and(request.prio[2], UInt<1>(0h1))
when _T_48 :
node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0)
node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1
node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3))
node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2))
node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1)
node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state)
connect final_meta_writeback.state, _final_meta_writeback_state_T_3
node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1))
node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2))
node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1)
node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5))
node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3)
node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5)
node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7
connect final_meta_writeback.hit, UInt<1>(0h1)
else :
node _T_49 = and(request.control, UInt<1>(0h1))
when _T_49 :
when meta.hit :
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
node _final_meta_writeback_clients_T_8 = not(probes_toN)
node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9
connect final_meta_writeback.hit, UInt<1>(0h0)
else :
node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty)
node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2)
node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0))
node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5
node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0))
node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1))
node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire)
node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state)
node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1))
node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state)
node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11)
node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state)
node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13)
node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15)
node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16)
connect final_meta_writeback.state, _final_meta_writeback_state_T_17
node _final_meta_writeback_clients_T_10 = not(probes_toN)
node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10)
node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0))
node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14
connect final_meta_writeback.tag, request.tag
connect final_meta_writeback.hit, UInt<1>(0h1)
when bad_grant :
when meta.hit :
node _T_50 = eq(meta_valid, UInt<1>(0h0))
node _T_51 = eq(meta.state, UInt<2>(0h1))
node _T_52 = or(_T_50, _T_51)
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7
assert(clock, _T_52, UInt<1>(0h1), "") : assert_7
connect final_meta_writeback.hit, UInt<1>(0h1)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h1)
node _final_meta_writeback_clients_T_15 = not(probes_toN)
node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16
else :
connect final_meta_writeback.hit, UInt<1>(0h0)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
connect final_meta_writeback.clients, UInt<1>(0h0)
wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}
connect invalid.dirty, UInt<1>(0h0)
connect invalid.state, UInt<2>(0h0)
connect invalid.clients, UInt<1>(0h0)
connect invalid.tag, UInt<1>(0h0)
node _honour_BtoT_T = and(meta.clients, req_clientBit)
node _honour_BtoT_T_1 = orr(_honour_BtoT_T)
node honour_BtoT = and(meta.hit, _honour_BtoT_T_1)
node _excluded_client_T = and(meta.hit, request.prio[0])
node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6))
node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7))
node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2)
node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4))
node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4)
node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5))
node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0))
node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7)
node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8)
node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0))
connect io.schedule.bits.a.bits.tag, request.tag
connect io.schedule.bits.a.bits.set, request.set
node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0))
connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1
node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6))
node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7))
node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2)
node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4)
connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5
connect io.schedule.bits.a.bits.source, UInt<1>(0h0)
node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1)
node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2)
connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3
node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag)
connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1
connect io.schedule.bits.b.bits.set, request.set
node _io_schedule_bits_b_bits_clients_T = not(excluded_client)
node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T)
connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1
node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6))
connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T
node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1))
node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1))
connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1
connect io.schedule.bits.c.bits.source, UInt<1>(0h0)
connect io.schedule.bits.c.bits.tag, meta.tag
connect io.schedule.bits.c.bits.set, request.set
connect io.schedule.bits.c.bits.way, meta.way
connect io.schedule.bits.c.bits.dirty, meta.dirty
connect io.schedule.bits.d.bits.set, request.set
connect io.schedule.bits.d.bits.put, request.put
connect io.schedule.bits.d.bits.offset, request.offset
connect io.schedule.bits.d.bits.tag, request.tag
connect io.schedule.bits.d.bits.source, request.source
connect io.schedule.bits.d.bits.size, request.size
connect io.schedule.bits.d.bits.param, request.param
connect io.schedule.bits.d.bits.opcode, request.opcode
connect io.schedule.bits.d.bits.control, request.control
connect io.schedule.bits.d.bits.prio, request.prio
node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0))
node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0))
node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param)
node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param)
node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param)
node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4)
node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param)
node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6)
node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8)
connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9
connect io.schedule.bits.d.bits.sink, UInt<1>(0h0)
connect io.schedule.bits.d.bits.way, meta.way
connect io.schedule.bits.d.bits.bad, bad_grant
connect io.schedule.bits.e.bits.sink, sink
connect io.schedule.bits.x.bits.fail, UInt<1>(0h0)
connect io.schedule.bits.dir.bits.set, request.set
connect io.schedule.bits.dir.bits.way, meta.way
node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0))
wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}
connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag
connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients
connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state
connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty
node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE)
connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1
node _evict_T = eq(meta.hit, UInt<1>(0h0))
wire evict : UInt
connect evict, UInt<1>(0h0)
node evict_c = orr(meta.clients)
node _evict_T_1 = eq(UInt<2>(0h1), meta.state)
when _evict_T_1 :
node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1))
connect evict, _evict_out_T
else :
node _evict_T_2 = eq(UInt<2>(0h2), meta.state)
when _evict_T_2 :
node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect evict, _evict_out_T_1
else :
node _evict_T_3 = eq(UInt<2>(0h3), meta.state)
when _evict_T_3 :
node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3)
connect evict, _evict_out_T_4
else :
node _evict_T_4 = eq(UInt<2>(0h0), meta.state)
when _evict_T_4 :
connect evict, UInt<4>(0h8)
node _evict_T_5 = eq(_evict_T, UInt<1>(0h0))
when _evict_T_5 :
connect evict, UInt<4>(0h8)
wire before : UInt
connect before, UInt<1>(0h0)
node before_c = orr(meta.clients)
node _before_T = eq(UInt<2>(0h1), meta.state)
when _before_T :
node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1))
connect before, _before_out_T
else :
node _before_T_1 = eq(UInt<2>(0h2), meta.state)
when _before_T_1 :
node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect before, _before_out_T_1
else :
node _before_T_2 = eq(UInt<2>(0h3), meta.state)
when _before_T_2 :
node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3)
connect before, _before_out_T_4
else :
node _before_T_3 = eq(UInt<2>(0h0), meta.state)
when _before_T_3 :
connect before, UInt<4>(0h8)
node _before_T_4 = eq(meta.hit, UInt<1>(0h0))
when _before_T_4 :
connect before, UInt<4>(0h8)
wire after : UInt
connect after, UInt<1>(0h0)
node after_c = orr(final_meta_writeback.clients)
node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _after_T :
node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1))
connect after, _after_out_T
else :
node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _after_T_1 :
node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect after, _after_out_T_1
else :
node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _after_T_2 :
node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3)
connect after, _after_out_T_4
else :
node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _after_T_3 :
connect after, UInt<4>(0h8)
node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _after_T_4 :
connect after, UInt<4>(0h8)
node _T_56 = eq(s_release, UInt<1>(0h0))
node _T_57 = and(_T_56, w_rprobeackfirst)
node _T_58 = and(_T_57, io.schedule.ready)
when _T_58 :
node _T_59 = eq(evict, UInt<1>(0h1))
node _T_60 = eq(_T_59, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8
assert(clock, _T_60, UInt<1>(0h1), "") : assert_8
node _T_64 = eq(before, UInt<1>(0h1))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(evict, UInt<1>(0h0))
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10
assert(clock, _T_70, UInt<1>(0h1), "") : assert_10
node _T_74 = eq(before, UInt<1>(0h0))
node _T_75 = eq(_T_74, UInt<1>(0h0))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11
assert(clock, _T_75, UInt<1>(0h1), "") : assert_11
node _T_79 = eq(evict, UInt<3>(0h7))
node _T_80 = eq(before, UInt<3>(0h7))
node _T_81 = eq(evict, UInt<3>(0h5))
node _T_82 = eq(before, UInt<3>(0h5))
node _T_83 = eq(evict, UInt<3>(0h4))
node _T_84 = eq(before, UInt<3>(0h4))
node _T_85 = eq(evict, UInt<3>(0h6))
node _T_86 = eq(before, UInt<3>(0h6))
node _T_87 = eq(evict, UInt<2>(0h3))
node _T_88 = eq(before, UInt<2>(0h3))
node _T_89 = eq(evict, UInt<2>(0h2))
node _T_90 = eq(before, UInt<2>(0h2))
node _T_91 = eq(s_writeback, UInt<1>(0h0))
node _T_92 = and(_T_91, no_wait)
node _T_93 = and(_T_92, io.schedule.ready)
when _T_93 :
node _T_94 = eq(before, UInt<4>(0h8))
node _T_95 = eq(after, UInt<1>(0h1))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12
assert(clock, _T_97, UInt<1>(0h1), "") : assert_12
node _T_101 = eq(before, UInt<4>(0h8))
node _T_102 = eq(after, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13
assert(clock, _T_104, UInt<1>(0h1), "") : assert_13
node _T_108 = eq(before, UInt<4>(0h8))
node _T_109 = eq(after, UInt<3>(0h7))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(before, UInt<4>(0h8))
node _T_112 = eq(after, UInt<3>(0h5))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(_T_113, UInt<1>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14
assert(clock, _T_114, UInt<1>(0h1), "") : assert_14
node _T_118 = eq(before, UInt<4>(0h8))
node _T_119 = eq(after, UInt<3>(0h4))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15
assert(clock, _T_121, UInt<1>(0h1), "") : assert_15
node _T_125 = eq(before, UInt<4>(0h8))
node _T_126 = eq(after, UInt<3>(0h6))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(before, UInt<4>(0h8))
node _T_129 = eq(after, UInt<2>(0h3))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(before, UInt<4>(0h8))
node _T_132 = eq(after, UInt<2>(0h2))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16
assert(clock, _T_134, UInt<1>(0h1), "") : assert_16
node _T_138 = eq(before, UInt<1>(0h1))
node _T_139 = eq(after, UInt<4>(0h8))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(_T_140, UInt<1>(0h0))
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17
assert(clock, _T_141, UInt<1>(0h1), "") : assert_17
node _T_145 = eq(before, UInt<1>(0h1))
node _T_146 = eq(after, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(_T_147, UInt<1>(0h0))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18
assert(clock, _T_148, UInt<1>(0h1), "") : assert_18
node _T_152 = eq(before, UInt<1>(0h1))
node _T_153 = eq(after, UInt<3>(0h7))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(_T_154, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19
assert(clock, _T_155, UInt<1>(0h1), "") : assert_19
node _T_159 = eq(before, UInt<1>(0h1))
node _T_160 = eq(after, UInt<3>(0h5))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(_T_161, UInt<1>(0h0))
node _T_163 = asUInt(reset)
node _T_164 = eq(_T_163, UInt<1>(0h0))
when _T_164 :
node _T_165 = eq(_T_162, UInt<1>(0h0))
when _T_165 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20
assert(clock, _T_162, UInt<1>(0h1), "") : assert_20
node _T_166 = eq(before, UInt<1>(0h1))
node _T_167 = eq(after, UInt<3>(0h4))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21
assert(clock, _T_169, UInt<1>(0h1), "") : assert_21
node _T_173 = eq(before, UInt<1>(0h1))
node _T_174 = eq(after, UInt<3>(0h6))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(_T_175, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22
assert(clock, _T_176, UInt<1>(0h1), "") : assert_22
node _T_180 = eq(before, UInt<1>(0h1))
node _T_181 = eq(after, UInt<2>(0h3))
node _T_182 = and(_T_180, _T_181)
node _T_183 = eq(_T_182, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(before, UInt<1>(0h1))
node _T_188 = eq(after, UInt<2>(0h2))
node _T_189 = and(_T_187, _T_188)
node _T_190 = eq(_T_189, UInt<1>(0h0))
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(_T_190, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24
assert(clock, _T_190, UInt<1>(0h1), "") : assert_24
node _T_194 = eq(before, UInt<1>(0h0))
node _T_195 = eq(after, UInt<4>(0h8))
node _T_196 = and(_T_194, _T_195)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25
assert(clock, _T_197, UInt<1>(0h1), "") : assert_25
node _T_201 = eq(before, UInt<1>(0h0))
node _T_202 = eq(after, UInt<1>(0h1))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26
assert(clock, _T_204, UInt<1>(0h1), "") : assert_26
node _T_208 = eq(before, UInt<1>(0h0))
node _T_209 = eq(after, UInt<3>(0h7))
node _T_210 = and(_T_208, _T_209)
node _T_211 = eq(_T_210, UInt<1>(0h0))
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27
assert(clock, _T_211, UInt<1>(0h1), "") : assert_27
node _T_215 = eq(before, UInt<1>(0h0))
node _T_216 = eq(after, UInt<3>(0h5))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(_T_217, UInt<1>(0h0))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28
assert(clock, _T_218, UInt<1>(0h1), "") : assert_28
node _T_222 = eq(before, UInt<1>(0h0))
node _T_223 = eq(after, UInt<3>(0h6))
node _T_224 = and(_T_222, _T_223)
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29
assert(clock, _T_225, UInt<1>(0h1), "") : assert_29
node _T_229 = eq(before, UInt<1>(0h0))
node _T_230 = eq(after, UInt<3>(0h4))
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(before, UInt<1>(0h0))
node _T_237 = eq(after, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31
assert(clock, _T_239, UInt<1>(0h1), "") : assert_31
node _T_243 = eq(before, UInt<1>(0h0))
node _T_244 = eq(after, UInt<2>(0h2))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(_T_245, UInt<1>(0h0))
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32
assert(clock, _T_246, UInt<1>(0h1), "") : assert_32
node _T_250 = eq(before, UInt<3>(0h7))
node _T_251 = eq(after, UInt<4>(0h8))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33
assert(clock, _T_253, UInt<1>(0h1), "") : assert_33
node _T_257 = eq(before, UInt<3>(0h7))
node _T_258 = eq(after, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(_T_259, UInt<1>(0h0))
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34
assert(clock, _T_260, UInt<1>(0h1), "") : assert_34
node _T_264 = eq(before, UInt<3>(0h7))
node _T_265 = eq(after, UInt<1>(0h0))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35
assert(clock, _T_267, UInt<1>(0h1), "") : assert_35
node _T_271 = eq(before, UInt<3>(0h7))
node _T_272 = eq(after, UInt<3>(0h5))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(_T_273, UInt<1>(0h0))
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36
assert(clock, _T_274, UInt<1>(0h1), "") : assert_36
node _T_278 = eq(before, UInt<3>(0h7))
node _T_279 = eq(after, UInt<3>(0h6))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(before, UInt<3>(0h7))
node _T_282 = eq(after, UInt<3>(0h4))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37
assert(clock, _T_284, UInt<1>(0h1), "") : assert_37
node _T_288 = eq(before, UInt<3>(0h7))
node _T_289 = eq(after, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(before, UInt<3>(0h7))
node _T_292 = eq(after, UInt<2>(0h2))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(_T_293, UInt<1>(0h0))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38
assert(clock, _T_294, UInt<1>(0h1), "") : assert_38
node _T_298 = eq(before, UInt<3>(0h5))
node _T_299 = eq(after, UInt<4>(0h8))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(_T_300, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39
assert(clock, _T_301, UInt<1>(0h1), "") : assert_39
node _T_305 = eq(before, UInt<3>(0h5))
node _T_306 = eq(after, UInt<1>(0h1))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(_T_307, UInt<1>(0h0))
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40
assert(clock, _T_308, UInt<1>(0h1), "") : assert_40
node _T_312 = eq(before, UInt<3>(0h5))
node _T_313 = eq(after, UInt<1>(0h0))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(_T_314, UInt<1>(0h0))
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(_T_315, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41
assert(clock, _T_315, UInt<1>(0h1), "") : assert_41
node _T_319 = eq(before, UInt<3>(0h5))
node _T_320 = eq(after, UInt<3>(0h7))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(before, UInt<3>(0h5))
node _T_323 = eq(after, UInt<3>(0h6))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(before, UInt<3>(0h5))
node _T_326 = eq(after, UInt<3>(0h4))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(_T_327, UInt<1>(0h0))
node _T_329 = asUInt(reset)
node _T_330 = eq(_T_329, UInt<1>(0h0))
when _T_330 :
node _T_331 = eq(_T_328, UInt<1>(0h0))
when _T_331 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42
assert(clock, _T_328, UInt<1>(0h1), "") : assert_42
node _T_332 = eq(before, UInt<3>(0h5))
node _T_333 = eq(after, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(before, UInt<3>(0h5))
node _T_336 = eq(after, UInt<2>(0h2))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(_T_337, UInt<1>(0h0))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43
assert(clock, _T_338, UInt<1>(0h1), "") : assert_43
node _T_342 = eq(before, UInt<3>(0h6))
node _T_343 = eq(after, UInt<4>(0h8))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(_T_344, UInt<1>(0h0))
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44
assert(clock, _T_345, UInt<1>(0h1), "") : assert_44
node _T_349 = eq(before, UInt<3>(0h6))
node _T_350 = eq(after, UInt<1>(0h1))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(_T_351, UInt<1>(0h0))
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(_T_352, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45
assert(clock, _T_352, UInt<1>(0h1), "") : assert_45
node _T_356 = eq(before, UInt<3>(0h6))
node _T_357 = eq(after, UInt<1>(0h0))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(_T_358, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46
assert(clock, _T_359, UInt<1>(0h1), "") : assert_46
node _T_363 = eq(before, UInt<3>(0h6))
node _T_364 = eq(after, UInt<3>(0h7))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47
assert(clock, _T_366, UInt<1>(0h1), "") : assert_47
node _T_370 = eq(before, UInt<3>(0h6))
node _T_371 = eq(after, UInt<3>(0h5))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(_T_372, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48
assert(clock, _T_373, UInt<1>(0h1), "") : assert_48
node _T_377 = eq(before, UInt<3>(0h6))
node _T_378 = eq(after, UInt<3>(0h4))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(_T_379, UInt<1>(0h0))
node _T_381 = asUInt(reset)
node _T_382 = eq(_T_381, UInt<1>(0h0))
when _T_382 :
node _T_383 = eq(_T_380, UInt<1>(0h0))
when _T_383 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49
assert(clock, _T_380, UInt<1>(0h1), "") : assert_49
node _T_384 = eq(before, UInt<3>(0h6))
node _T_385 = eq(after, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(_T_386, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50
assert(clock, _T_387, UInt<1>(0h1), "") : assert_50
node _T_391 = eq(before, UInt<3>(0h6))
node _T_392 = eq(after, UInt<2>(0h2))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(before, UInt<3>(0h4))
node _T_395 = eq(after, UInt<4>(0h8))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51
assert(clock, _T_397, UInt<1>(0h1), "") : assert_51
node _T_401 = eq(before, UInt<3>(0h4))
node _T_402 = eq(after, UInt<1>(0h1))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(_T_403, UInt<1>(0h0))
node _T_405 = asUInt(reset)
node _T_406 = eq(_T_405, UInt<1>(0h0))
when _T_406 :
node _T_407 = eq(_T_404, UInt<1>(0h0))
when _T_407 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52
assert(clock, _T_404, UInt<1>(0h1), "") : assert_52
node _T_408 = eq(before, UInt<3>(0h4))
node _T_409 = eq(after, UInt<1>(0h0))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(_T_410, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53
assert(clock, _T_411, UInt<1>(0h1), "") : assert_53
node _T_415 = eq(before, UInt<3>(0h4))
node _T_416 = eq(after, UInt<3>(0h7))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(_T_417, UInt<1>(0h0))
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54
assert(clock, _T_418, UInt<1>(0h1), "") : assert_54
node _T_422 = eq(before, UInt<3>(0h4))
node _T_423 = eq(after, UInt<3>(0h5))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = asUInt(reset)
node _T_427 = eq(_T_426, UInt<1>(0h0))
when _T_427 :
node _T_428 = eq(_T_425, UInt<1>(0h0))
when _T_428 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55
assert(clock, _T_425, UInt<1>(0h1), "") : assert_55
node _T_429 = eq(before, UInt<3>(0h4))
node _T_430 = eq(after, UInt<3>(0h6))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(before, UInt<3>(0h4))
node _T_433 = eq(after, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(_T_434, UInt<1>(0h0))
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56
assert(clock, _T_435, UInt<1>(0h1), "") : assert_56
node _T_439 = eq(before, UInt<3>(0h4))
node _T_440 = eq(after, UInt<2>(0h2))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(before, UInt<2>(0h3))
node _T_443 = eq(after, UInt<4>(0h8))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(_T_444, UInt<1>(0h0))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57
assert(clock, _T_445, UInt<1>(0h1), "") : assert_57
node _T_449 = eq(before, UInt<2>(0h3))
node _T_450 = eq(after, UInt<1>(0h1))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(_T_451, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58
assert(clock, _T_452, UInt<1>(0h1), "") : assert_58
node _T_456 = eq(before, UInt<2>(0h3))
node _T_457 = eq(after, UInt<1>(0h0))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59
assert(clock, _T_459, UInt<1>(0h1), "") : assert_59
node _T_463 = eq(before, UInt<2>(0h3))
node _T_464 = eq(after, UInt<3>(0h7))
node _T_465 = and(_T_463, _T_464)
node _T_466 = eq(before, UInt<2>(0h3))
node _T_467 = eq(after, UInt<3>(0h5))
node _T_468 = and(_T_466, _T_467)
node _T_469 = eq(before, UInt<2>(0h3))
node _T_470 = eq(after, UInt<3>(0h6))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(before, UInt<2>(0h3))
node _T_473 = eq(after, UInt<3>(0h4))
node _T_474 = and(_T_472, _T_473)
node _T_475 = eq(before, UInt<2>(0h3))
node _T_476 = eq(after, UInt<2>(0h2))
node _T_477 = and(_T_475, _T_476)
node _T_478 = eq(before, UInt<2>(0h2))
node _T_479 = eq(after, UInt<4>(0h8))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60
assert(clock, _T_481, UInt<1>(0h1), "") : assert_60
node _T_485 = eq(before, UInt<2>(0h2))
node _T_486 = eq(after, UInt<1>(0h1))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(_T_487, UInt<1>(0h0))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61
assert(clock, _T_488, UInt<1>(0h1), "") : assert_61
node _T_492 = eq(before, UInt<2>(0h2))
node _T_493 = eq(after, UInt<1>(0h0))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62
assert(clock, _T_495, UInt<1>(0h1), "") : assert_62
node _T_499 = eq(before, UInt<2>(0h2))
node _T_500 = eq(after, UInt<3>(0h7))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(_T_501, UInt<1>(0h0))
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63
assert(clock, _T_502, UInt<1>(0h1), "") : assert_63
node _T_506 = eq(before, UInt<2>(0h2))
node _T_507 = eq(after, UInt<3>(0h5))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(_T_508, UInt<1>(0h0))
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64
assert(clock, _T_509, UInt<1>(0h1), "") : assert_64
node _T_513 = eq(before, UInt<2>(0h2))
node _T_514 = eq(after, UInt<3>(0h6))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(before, UInt<2>(0h2))
node _T_517 = eq(after, UInt<3>(0h4))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(before, UInt<2>(0h2))
node _T_520 = eq(after, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(_T_521, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65
assert(clock, _T_522, UInt<1>(0h1), "") : assert_65
node _probe_bit_uncommonBits_T = or(io.sinkc.bits.source, UInt<2>(0h0))
node probe_bit_uncommonBits = bits(_probe_bit_uncommonBits_T, 1, 0)
node _probe_bit_T = shr(io.sinkc.bits.source, 2)
node _probe_bit_T_1 = eq(_probe_bit_T, UInt<4>(0h8))
node _probe_bit_T_2 = leq(UInt<1>(0h0), probe_bit_uncommonBits)
node _probe_bit_T_3 = and(_probe_bit_T_1, _probe_bit_T_2)
node _probe_bit_T_4 = leq(probe_bit_uncommonBits, UInt<2>(0h3))
node probe_bit = and(_probe_bit_T_3, _probe_bit_T_4)
node _last_probe_T = or(probes_done, probe_bit)
node _last_probe_T_1 = not(excluded_client)
node _last_probe_T_2 = and(meta.clients, _last_probe_T_1)
node last_probe = eq(_last_probe_T, _last_probe_T_2)
node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1))
node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2))
node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1)
node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5))
node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3)
when io.sinkc.valid :
node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_527 = and(probe_toN, _T_526)
node _T_528 = eq(probe_toN, UInt<1>(0h0))
node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_530 = and(_T_528, _T_529)
node _probes_done_T = or(probes_done, probe_bit)
connect probes_done, _probes_done_T
node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0))
node _probes_toN_T_1 = or(probes_toN, _probes_toN_T)
connect probes_toN, _probes_toN_T_1
node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3))
node _probes_noT_T_1 = or(probes_noT, _probes_noT_T)
connect probes_noT, _probes_noT_T_1
node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe)
connect w_rprobeackfirst, _w_rprobeackfirst_T
node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T)
connect w_rprobeacklast, _w_rprobeacklast_T_1
node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe)
connect w_pprobeackfirst, _w_pprobeackfirst_T
node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T)
connect w_pprobeacklast, _w_pprobeacklast_T_1
node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0))
node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T)
node set_pprobeack = and(last_probe, _set_pprobeack_T_1)
node _w_pprobeack_T = or(w_pprobeack, set_pprobeack)
connect w_pprobeack, _w_pprobeack_T
node _T_531 = eq(set_pprobeack, UInt<1>(0h0))
node _T_532 = and(_T_531, w_rprobeackfirst)
node _T_533 = and(set_pprobeack, w_rprobeackfirst)
node _T_534 = neq(meta.state, UInt<2>(0h0))
node _T_535 = eq(io.sinkc.bits.tag, meta.tag)
node _T_536 = and(_T_534, _T_535)
node _T_537 = and(_T_536, io.sinkc.bits.data)
when _T_537 :
connect meta.dirty, UInt<1>(0h1)
when io.sinkd.valid :
node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4))
node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_540 = or(_T_538, _T_539)
when _T_540 :
connect sink, io.sinkd.bits.sink
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, io.sinkd.bits.last
connect bad_grant, io.sinkd.bits.denied
node _w_grant_T = eq(request.offset, UInt<1>(0h0))
node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last)
connect w_grant, _w_grant_T_1
node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_542 = eq(request.offset, UInt<1>(0h0))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_545 = neq(request.offset, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0))
connect gotT, _gotT_T
else :
node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6))
when _T_547 :
connect w_releaseack, UInt<1>(0h1)
when io.sinke.valid :
connect w_grantack, UInt<1>(0h1)
wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}
connect allocate_as_full.set, io.allocate.bits.set
connect allocate_as_full.put, io.allocate.bits.put
connect allocate_as_full.offset, io.allocate.bits.offset
connect allocate_as_full.tag, io.allocate.bits.tag
connect allocate_as_full.source, io.allocate.bits.source
connect allocate_as_full.size, io.allocate.bits.size
connect allocate_as_full.param, io.allocate.bits.param
connect allocate_as_full.opcode, io.allocate.bits.opcode
connect allocate_as_full.control, io.allocate.bits.control
connect allocate_as_full.prio, io.allocate.bits.prio
node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat)
node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits)
node new_request = mux(io.allocate.valid, allocate_as_full, request)
node _new_needT_T = bits(new_request.opcode, 2, 2)
node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0))
node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5))
node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1))
node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3)
node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4)
node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6))
node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7))
node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7)
node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0))
node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9)
node new_needT = or(_new_needT_T_5, _new_needT_T_10)
node _new_clientBit_uncommonBits_T = or(new_request.source, UInt<2>(0h0))
node new_clientBit_uncommonBits = bits(_new_clientBit_uncommonBits_T, 1, 0)
node _new_clientBit_T = shr(new_request.source, 2)
node _new_clientBit_T_1 = eq(_new_clientBit_T, UInt<4>(0h8))
node _new_clientBit_T_2 = leq(UInt<1>(0h0), new_clientBit_uncommonBits)
node _new_clientBit_T_3 = and(_new_clientBit_T_1, _new_clientBit_T_2)
node _new_clientBit_T_4 = leq(new_clientBit_uncommonBits, UInt<2>(0h3))
node new_clientBit = and(_new_clientBit_T_3, _new_clientBit_T_4)
node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6))
node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7))
node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1)
node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4))
node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3)
node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5))
node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0))
node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6)
node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0))
wire prior : UInt
connect prior, UInt<1>(0h0)
node prior_c = orr(final_meta_writeback.clients)
node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _prior_T :
node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1))
connect prior, _prior_out_T
else :
node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _prior_T_1 :
node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect prior, _prior_out_T_1
else :
node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _prior_T_2 :
node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3)
connect prior, _prior_out_T_4
else :
node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _prior_T_3 :
connect prior, UInt<4>(0h8)
node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _prior_T_4 :
connect prior, UInt<4>(0h8)
node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat)
when _T_548 :
node _T_549 = eq(prior, UInt<4>(0h8))
node _T_550 = eq(prior, UInt<1>(0h1))
node _T_551 = eq(_T_550, UInt<1>(0h0))
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66
assert(clock, _T_551, UInt<1>(0h1), "") : assert_66
node _T_555 = eq(prior, UInt<1>(0h0))
node _T_556 = eq(_T_555, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67
assert(clock, _T_556, UInt<1>(0h1), "") : assert_67
node _T_560 = eq(prior, UInt<3>(0h7))
node _T_561 = eq(prior, UInt<3>(0h5))
node _T_562 = eq(prior, UInt<3>(0h4))
node _T_563 = eq(prior, UInt<3>(0h6))
node _T_564 = eq(prior, UInt<2>(0h3))
node _T_565 = eq(prior, UInt<2>(0h2))
when io.allocate.valid :
node _T_566 = eq(request_valid, UInt<1>(0h0))
node _T_567 = and(io.schedule.ready, io.schedule.valid)
node _T_568 = and(no_wait, _T_567)
node _T_569 = or(_T_566, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68
assert(clock, _T_569, UInt<1>(0h1), "") : assert_68
connect request_valid, UInt<1>(0h1)
connect request.set, io.allocate.bits.set
connect request.put, io.allocate.bits.put
connect request.offset, io.allocate.bits.offset
connect request.tag, io.allocate.bits.tag
connect request.source, io.allocate.bits.source
connect request.size, io.allocate.bits.size
connect request.param, io.allocate.bits.param
connect request.opcode, io.allocate.bits.opcode
connect request.control, io.allocate.bits.control
connect request.prio, io.allocate.bits.prio
node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat)
node _T_574 = or(io.directory.valid, _T_573)
when _T_574 :
connect meta_valid, UInt<1>(0h1)
connect meta, new_meta
connect probes_done, UInt<1>(0h0)
connect probes_toN, UInt<1>(0h0)
connect probes_noT, UInt<1>(0h0)
connect gotT, UInt<1>(0h0)
connect bad_grant, UInt<1>(0h0)
connect s_rprobe, UInt<1>(0h1)
connect w_rprobeackfirst, UInt<1>(0h1)
connect w_rprobeacklast, UInt<1>(0h1)
connect s_release, UInt<1>(0h1)
connect w_releaseack, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
connect s_acquire, UInt<1>(0h1)
connect s_flush, UInt<1>(0h1)
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, UInt<1>(0h1)
connect w_grant, UInt<1>(0h1)
connect w_pprobeackfirst, UInt<1>(0h1)
connect w_pprobeacklast, UInt<1>(0h1)
connect w_pprobeack, UInt<1>(0h1)
connect s_probeack, UInt<1>(0h1)
connect s_grantack, UInt<1>(0h1)
connect s_execute, UInt<1>(0h1)
connect w_grantack, UInt<1>(0h1)
connect s_writeback, UInt<1>(0h1)
node _T_575 = and(new_request.prio[2], UInt<1>(0h1))
when _T_575 :
connect s_execute, UInt<1>(0h0)
node _T_576 = bits(new_request.opcode, 0, 0)
node _T_577 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_578 = and(_T_576, _T_577)
when _T_578 :
connect s_writeback, UInt<1>(0h0)
node _T_579 = eq(new_request.param, UInt<3>(0h0))
node _T_580 = eq(new_request.param, UInt<3>(0h4))
node _T_581 = or(_T_579, _T_580)
node _T_582 = eq(new_meta.state, UInt<2>(0h2))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
connect s_writeback, UInt<1>(0h0)
node _T_584 = eq(new_request.param, UInt<3>(0h1))
node _T_585 = eq(new_request.param, UInt<3>(0h2))
node _T_586 = or(_T_584, _T_585)
node _T_587 = eq(new_request.param, UInt<3>(0h5))
node _T_588 = or(_T_586, _T_587)
node _T_589 = and(new_meta.clients, new_clientBit)
node _T_590 = neq(_T_589, UInt<1>(0h0))
node _T_591 = and(_T_588, _T_590)
when _T_591 :
connect s_writeback, UInt<1>(0h0)
node _T_592 = asUInt(reset)
node _T_593 = eq(_T_592, UInt<1>(0h0))
when _T_593 :
node _T_594 = eq(new_meta.hit, UInt<1>(0h0))
when _T_594 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69
assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69
else :
node _T_595 = and(new_request.control, UInt<1>(0h1))
when _T_595 :
connect s_flush, UInt<1>(0h0)
when new_meta.hit :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_596 = neq(new_meta.clients, UInt<1>(0h0))
node _T_597 = and(UInt<1>(0h1), _T_596)
when _T_597 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
else :
connect s_execute, UInt<1>(0h0)
node _T_598 = eq(new_meta.hit, UInt<1>(0h0))
node _T_599 = neq(new_meta.state, UInt<2>(0h0))
node _T_600 = and(_T_598, _T_599)
when _T_600 :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_601 = neq(new_meta.clients, UInt<1>(0h0))
node _T_602 = and(UInt<1>(0h1), _T_601)
when _T_602 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
node _T_603 = eq(new_meta.hit, UInt<1>(0h0))
node _T_604 = eq(new_meta.state, UInt<2>(0h1))
node _T_605 = and(_T_604, new_needT)
node _T_606 = or(_T_603, _T_605)
when _T_606 :
connect s_acquire, UInt<1>(0h0)
connect w_grantfirst, UInt<1>(0h0)
connect w_grantlast, UInt<1>(0h0)
connect w_grant, UInt<1>(0h0)
connect s_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_607 = eq(new_meta.state, UInt<2>(0h2))
node _T_608 = or(new_needT, _T_607)
node _T_609 = and(new_meta.hit, _T_608)
node _T_610 = not(new_skipProbe)
node _T_611 = and(new_meta.clients, _T_610)
node _T_612 = neq(_T_611, UInt<1>(0h0))
node _T_613 = and(_T_609, _T_612)
node _T_614 = and(UInt<1>(0h1), _T_613)
when _T_614 :
connect s_pprobe, UInt<1>(0h0)
connect w_pprobeackfirst, UInt<1>(0h0)
connect w_pprobeacklast, UInt<1>(0h0)
connect w_pprobeack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_615 = eq(new_request.opcode, UInt<3>(0h6))
node _T_616 = eq(new_request.opcode, UInt<3>(0h7))
node _T_617 = or(_T_615, _T_616)
when _T_617 :
connect w_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_618 = bits(new_request.opcode, 2, 2)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = and(_T_619, new_meta.hit)
node _T_621 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_622 = and(_T_620, _T_621)
when _T_622 :
connect s_writeback, UInt<1>(0h0) | module MSHR_2( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [9:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [2:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _req_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _req_clientBit_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _probe_bit_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _probe_bit_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _new_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _new_clientBit_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [5:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29]
wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
wire [5:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29]
reg [12:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [9:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
reg [12:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [2:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire [1:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _req_clientBit_T = request_source[5:2]; // @[Parameters.scala:54:10]
wire _req_clientBit_T_1 = _req_clientBit_T == 4'h8; // @[Parameters.scala:54:{10,32}]
wire _req_clientBit_T_3 = _req_clientBit_T_1; // @[Parameters.scala:54:{32,67}]
wire req_clientBit = _req_clientBit_T_3; // @[Parameters.scala:54:67, :56:48]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:56:48]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:56:48]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:56:48]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:56:48]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire [1:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _probe_bit_T = io_sinkc_bits_source_0[5:2]; // @[Parameters.scala:54:10]
wire _probe_bit_T_1 = _probe_bit_T == 4'h8; // @[Parameters.scala:54:{10,32}]
wire _probe_bit_T_3 = _probe_bit_T_1; // @[Parameters.scala:54:{32,67}]
wire probe_bit = _probe_bit_T_3; // @[Parameters.scala:54:67, :56:48]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:56:48]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:56:48]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire [1:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _new_clientBit_T = new_request_source[5:2]; // @[Parameters.scala:54:10]
wire _new_clientBit_T_1 = _new_clientBit_T == 4'h8; // @[Parameters.scala:54:{10,32}]
wire _new_clientBit_T_3 = _new_clientBit_T_1; // @[Parameters.scala:54:{32,67}]
wire new_clientBit = _new_clientBit_T_3; // @[Parameters.scala:54:67, :56:48]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:56:48]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to this FIRRTL code module SourceD :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, pb_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, flip pb_beat : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>}, rel_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, flip rel_beat : { data : UInt<64>, corrupt : UInt<1>}, bs_radr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, flip bs_rdat : { data : UInt<64>}, bs_wadr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, bs_wdat : { data : UInt<64>}, flip evict_req : { set : UInt<10>, way : UInt<3>}, evict_safe : UInt<1>, flip grant_req : { set : UInt<10>, way : UInt<3>}, grant_safe : UInt<1>}
wire s1_valid : UInt<1>
wire s2_valid : UInt<1>
wire s3_valid : UInt<1>
wire s2_ready : UInt<1>
wire s3_ready : UInt<1>
wire s4_ready : UInt<1>
regreset busy : UInt<1>, clock, reset, UInt<1>(0h0)
regreset s1_block_r : UInt<1>, clock, reset, UInt<1>(0h0)
regreset s1_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _s1_req_reg_T = eq(busy, UInt<1>(0h0))
node _s1_req_reg_T_1 = and(_s1_req_reg_T, io.req.valid)
reg s1_req_reg : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock
when _s1_req_reg_T_1 :
connect s1_req_reg, io.req.bits
node _s1_req_T = eq(busy, UInt<1>(0h0))
node s1_req = mux(_s1_req_T, io.req.bits, s1_req_reg)
wire s1_x_bypass : UInt<1>
node _s1_latch_bypass_T = or(busy, io.req.valid)
node _s1_latch_bypass_T_1 = eq(_s1_latch_bypass_T, UInt<1>(0h0))
node _s1_latch_bypass_T_2 = or(_s1_latch_bypass_T_1, s2_ready)
reg s1_latch_bypass : UInt<1>, clock
connect s1_latch_bypass, _s1_latch_bypass_T_2
reg s1_bypass_r : UInt<1>, clock
when s1_latch_bypass :
connect s1_bypass_r, s1_x_bypass
node s1_bypass = mux(s1_latch_bypass, s1_x_bypass, s1_bypass_r)
node _s1_mask_sizeOH_T = or(s1_req.size, UInt<3>(0h0))
node s1_mask_sizeOH_shiftAmount = bits(_s1_mask_sizeOH_T, 1, 0)
node _s1_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_mask_sizeOH_shiftAmount)
node _s1_mask_sizeOH_T_2 = bits(_s1_mask_sizeOH_T_1, 2, 0)
node s1_mask_sizeOH = or(_s1_mask_sizeOH_T_2, UInt<4>(0hf))
node _s1_mask_T = not(s1_bypass)
node s1_mask = and(UInt<1>(0h1), _s1_mask_T)
node _s1_grant_T = eq(s1_req.opcode, UInt<3>(0h6))
node _s1_grant_T_1 = eq(s1_req.param, UInt<2>(0h2))
node _s1_grant_T_2 = and(_s1_grant_T, _s1_grant_T_1)
node _s1_grant_T_3 = eq(s1_req.opcode, UInt<3>(0h7))
node s1_grant = or(_s1_grant_T_2, _s1_grant_T_3)
node _s1_need_r_T = orr(s1_mask)
node _s1_need_r_T_1 = and(_s1_need_r_T, s1_req.prio[0])
node _s1_need_r_T_2 = neq(s1_req.opcode, UInt<3>(0h5))
node _s1_need_r_T_3 = and(_s1_need_r_T_1, _s1_need_r_T_2)
node _s1_need_r_T_4 = eq(s1_grant, UInt<1>(0h0))
node _s1_need_r_T_5 = and(_s1_need_r_T_3, _s1_need_r_T_4)
node _s1_need_r_T_6 = neq(s1_req.opcode, UInt<1>(0h0))
node _s1_need_r_T_7 = lt(s1_req.size, UInt<2>(0h3))
node _s1_need_r_T_8 = or(_s1_need_r_T_6, _s1_need_r_T_7)
node s1_need_r = and(_s1_need_r_T_5, _s1_need_r_T_8)
node _s1_valid_r_T = or(busy, io.req.valid)
node _s1_valid_r_T_1 = and(_s1_valid_r_T, s1_need_r)
node _s1_valid_r_T_2 = eq(s1_block_r, UInt<1>(0h0))
node s1_valid_r = and(_s1_valid_r_T_1, _s1_valid_r_T_2)
node _s1_need_pb_T = bits(s1_req.opcode, 2, 2)
node _s1_need_pb_T_1 = eq(_s1_need_pb_T, UInt<1>(0h0))
node _s1_need_pb_T_2 = bits(s1_req.opcode, 0, 0)
node s1_need_pb = mux(s1_req.prio[0], _s1_need_pb_T_1, _s1_need_pb_T_2)
node _s1_single_T = eq(s1_req.opcode, UInt<3>(0h5))
node _s1_single_T_1 = or(_s1_single_T, s1_grant)
node _s1_single_T_2 = eq(s1_req.opcode, UInt<3>(0h6))
node s1_single = mux(s1_req.prio[0], _s1_single_T_1, _s1_single_T_2)
node s1_retires = eq(s1_single, UInt<1>(0h0))
node _s1_beats1_T = dshl(UInt<6>(0h3f), s1_req.size)
node _s1_beats1_T_1 = bits(_s1_beats1_T, 5, 0)
node _s1_beats1_T_2 = not(_s1_beats1_T_1)
node _s1_beats1_T_3 = shr(_s1_beats1_T_2, 3)
node s1_beats1 = mux(s1_single, UInt<1>(0h0), _s1_beats1_T_3)
node _s1_beat_T = shr(s1_req.offset, 3)
node s1_beat = or(_s1_beat_T, s1_counter)
node s1_last = eq(s1_counter, s1_beats1)
node s1_first = eq(s1_counter, UInt<1>(0h0))
node _T = eq(s1_latch_bypass, UInt<1>(0h0))
node _T_1 = or(busy, io.req.valid)
node _T_2 = eq(s1_need_r, UInt<1>(0h0))
node _T_3 = and(_T_1, _T_2)
connect io.bs_radr.valid, s1_valid_r
connect io.bs_radr.bits.noop, UInt<1>(0h0)
connect io.bs_radr.bits.way, s1_req.way
connect io.bs_radr.bits.set, s1_req.set
connect io.bs_radr.bits.beat, s1_beat
connect io.bs_radr.bits.mask, s1_mask
node _T_4 = eq(io.bs_radr.ready, UInt<1>(0h0))
node _T_5 = and(io.bs_radr.valid, _T_4)
inst queue of Queue3_BankedStoreInnerDecoded
connect queue.clock, clock
connect queue.reset, reset
node _queue_io_enq_valid_T = and(io.bs_radr.ready, io.bs_radr.valid)
reg queue_io_enq_valid_REG : UInt<1>, clock
connect queue_io_enq_valid_REG, _queue_io_enq_valid_T
reg queue_io_enq_valid_REG_1 : UInt<1>, clock
connect queue_io_enq_valid_REG_1, queue_io_enq_valid_REG
connect queue.io.enq.valid, queue_io_enq_valid_REG_1
connect queue.io.enq.bits.data, io.bs_rdat.data
node _T_6 = eq(queue.io.enq.valid, UInt<1>(0h0))
node _T_7 = or(_T_6, queue.io.enq.ready)
node _T_8 = asUInt(reset)
node _T_9 = eq(_T_8, UInt<1>(0h0))
when _T_9 :
node _T_10 = eq(_T_7, UInt<1>(0h0))
when _T_10 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceD.scala:123 assert (!queue.io.enq.valid || queue.io.enq.ready)\n") : printf
assert(clock, _T_7, UInt<1>(0h1), "") : assert
node _T_11 = eq(queue.io.enq.ready, UInt<1>(0h0))
node _T_12 = and(io.bs_radr.ready, io.bs_radr.valid)
when _T_12 :
connect s1_block_r, UInt<1>(0h1)
when io.req.valid :
connect busy, UInt<1>(0h1)
node _T_13 = and(s1_valid, s2_ready)
when _T_13 :
node _s1_counter_T = add(s1_counter, UInt<1>(0h1))
node _s1_counter_T_1 = tail(_s1_counter_T, 1)
connect s1_counter, _s1_counter_T_1
connect s1_block_r, UInt<1>(0h0)
when s1_last :
connect s1_counter, UInt<1>(0h0)
connect busy, UInt<1>(0h0)
node _T_14 = eq(s2_ready, UInt<1>(0h0))
node _T_15 = and(s1_valid, _T_14)
node _io_req_ready_T = eq(busy, UInt<1>(0h0))
connect io.req.ready, _io_req_ready_T
node _s1_valid_T = or(busy, io.req.valid)
node _s1_valid_T_1 = eq(s1_valid_r, UInt<1>(0h0))
node _s1_valid_T_2 = or(_s1_valid_T_1, io.bs_radr.ready)
node _s1_valid_T_3 = and(_s1_valid_T, _s1_valid_T_2)
connect s1_valid, _s1_valid_T_3
node s2_latch = and(s1_valid, s2_ready)
regreset s2_full : UInt<1>, clock, reset, UInt<1>(0h0)
regreset s2_valid_pb : UInt<1>, clock, reset, UInt<1>(0h0)
reg s2_beat : UInt<3>, clock
when s2_latch :
connect s2_beat, s1_beat
reg s2_bypass : UInt<1>, clock
when s2_latch :
connect s2_bypass, s1_bypass
reg s2_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock
when s2_latch :
connect s2_req, s1_req
reg s2_last : UInt<1>, clock
when s2_latch :
connect s2_last, s1_last
reg s2_need_r : UInt<1>, clock
when s2_latch :
connect s2_need_r, s1_need_r
reg s2_need_pb : UInt<1>, clock
when s2_latch :
connect s2_need_pb, s1_need_pb
reg s2_retires : UInt<1>, clock
when s2_latch :
connect s2_retires, s1_retires
node _s2_need_d_T = eq(s1_need_pb, UInt<1>(0h0))
node _s2_need_d_T_1 = or(_s2_need_d_T, s1_first)
reg s2_need_d : UInt<1>, clock
when s2_latch :
connect s2_need_d, _s2_need_d_T_1
wire s2_pdata_raw : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>}
reg s2_pdata_r : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>}, clock
when s2_valid_pb :
connect s2_pdata_r, s2_pdata_raw
node s2_pdata = mux(s2_valid_pb, s2_pdata_raw, s2_pdata_r)
node _s2_pdata_raw_data_T = mux(s2_req.prio[0], io.pb_beat.data, io.rel_beat.data)
connect s2_pdata_raw.data, _s2_pdata_raw_data_T
node _s2_pdata_raw_mask_T = not(UInt<8>(0h0))
node _s2_pdata_raw_mask_T_1 = mux(s2_req.prio[0], io.pb_beat.mask, _s2_pdata_raw_mask_T)
connect s2_pdata_raw.mask, _s2_pdata_raw_mask_T_1
node _s2_pdata_raw_corrupt_T = mux(s2_req.prio[0], io.pb_beat.corrupt, io.rel_beat.corrupt)
connect s2_pdata_raw.corrupt, _s2_pdata_raw_corrupt_T
node _io_pb_pop_valid_T = and(s2_valid_pb, s2_req.prio[0])
connect io.pb_pop.valid, _io_pb_pop_valid_T
connect io.pb_pop.bits.index, s2_req.put
connect io.pb_pop.bits.last, s2_last
node _io_rel_pop_valid_T = eq(s2_req.prio[0], UInt<1>(0h0))
node _io_rel_pop_valid_T_1 = and(s2_valid_pb, _io_rel_pop_valid_T)
connect io.rel_pop.valid, _io_rel_pop_valid_T_1
connect io.rel_pop.bits.index, s2_req.put
connect io.rel_pop.bits.last, s2_last
node _T_16 = eq(io.pb_pop.ready, UInt<1>(0h0))
node _T_17 = and(io.pb_pop.valid, _T_16)
node _T_18 = eq(io.rel_pop.ready, UInt<1>(0h0))
node _T_19 = and(io.rel_pop.valid, _T_18)
node pb_ready = mux(s2_req.prio[0], io.pb_pop.ready, io.rel_pop.ready)
when pb_ready :
connect s2_valid_pb, UInt<1>(0h0)
node _T_20 = and(s2_valid, s3_ready)
when _T_20 :
connect s2_full, UInt<1>(0h0)
when s2_latch :
connect s2_valid_pb, s1_need_pb
when s2_latch :
connect s2_full, UInt<1>(0h1)
node _T_21 = eq(s3_ready, UInt<1>(0h0))
node _T_22 = and(s2_valid, _T_21)
node _s2_valid_T = eq(s2_valid_pb, UInt<1>(0h0))
node _s2_valid_T_1 = or(_s2_valid_T, pb_ready)
node _s2_valid_T_2 = and(s2_full, _s2_valid_T_1)
connect s2_valid, _s2_valid_T_2
node _s2_ready_T = eq(s2_full, UInt<1>(0h0))
node _s2_ready_T_1 = eq(s2_valid_pb, UInt<1>(0h0))
node _s2_ready_T_2 = or(_s2_ready_T_1, pb_ready)
node _s2_ready_T_3 = and(s3_ready, _s2_ready_T_2)
node _s2_ready_T_4 = or(_s2_ready_T, _s2_ready_T_3)
connect s2_ready, _s2_ready_T_4
node s3_latch = and(s2_valid, s3_ready)
regreset s3_full : UInt<1>, clock, reset, UInt<1>(0h0)
regreset s3_valid_d : UInt<1>, clock, reset, UInt<1>(0h0)
reg s3_beat : UInt<3>, clock
when s3_latch :
connect s3_beat, s2_beat
reg s3_bypass : UInt<1>, clock
when s3_latch :
connect s3_bypass, s2_bypass
reg s3_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock
when s3_latch :
connect s3_req, s2_req
node s3_adjusted_opcode = mux(s3_req.bad, UInt<3>(0h4), s3_req.opcode)
reg s3_last : UInt<1>, clock
when s3_latch :
connect s3_last, s2_last
reg s3_pdata : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>}, clock
when s3_latch :
connect s3_pdata, s2_pdata
reg s3_need_pb : UInt<1>, clock
when s3_latch :
connect s3_need_pb, s2_need_pb
reg s3_retires : UInt<1>, clock
when s3_latch :
connect s3_retires, s2_retires
reg s3_need_r : UInt<1>, clock
when s3_latch :
connect s3_need_r, s2_need_r
node _s3_acq_T = eq(s3_req.opcode, UInt<3>(0h6))
node _s3_acq_T_1 = eq(s3_req.opcode, UInt<3>(0h7))
node s3_acq = or(_s3_acq_T, _s3_acq_T_1)
wire s3_bypass_data : UInt
node _s3_rdata_T = bits(s3_bypass, 0, 0)
node _s3_rdata_T_1 = bits(s3_bypass_data, 63, 0)
node _s3_rdata_T_2 = bits(queue.io.deq.bits.data, 63, 0)
node s3_rdata = mux(_s3_rdata_T, _s3_rdata_T_1, _s3_rdata_T_2)
node _grant_T = eq(s3_req.param, UInt<2>(0h2))
node grant = mux(_grant_T, UInt<3>(0h4), UInt<3>(0h5))
wire resp_opcode : UInt<3>[8]
connect resp_opcode[0], UInt<1>(0h0)
connect resp_opcode[1], UInt<1>(0h0)
connect resp_opcode[2], UInt<1>(0h1)
connect resp_opcode[3], UInt<1>(0h1)
connect resp_opcode[4], UInt<1>(0h1)
connect resp_opcode[5], UInt<2>(0h2)
connect resp_opcode[6], grant
connect resp_opcode[7], UInt<3>(0h4)
wire d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect io.d, d
connect d.valid, s3_valid_d
node _d_bits_opcode_T = mux(s3_req.prio[0], resp_opcode[s3_req.opcode], UInt<3>(0h6))
connect d.bits.opcode, _d_bits_opcode_T
node _d_bits_param_T = and(s3_req.prio[0], s3_acq)
node _d_bits_param_T_1 = neq(s3_req.param, UInt<2>(0h0))
node _d_bits_param_T_2 = mux(_d_bits_param_T_1, UInt<2>(0h0), UInt<2>(0h1))
node _d_bits_param_T_3 = mux(_d_bits_param_T, _d_bits_param_T_2, UInt<1>(0h0))
connect d.bits.param, _d_bits_param_T_3
connect d.bits.size, s3_req.size
connect d.bits.source, s3_req.source
connect d.bits.sink, s3_req.sink
connect d.bits.denied, s3_req.bad
connect d.bits.data, s3_rdata
node _d_bits_corrupt_T = bits(d.bits.opcode, 0, 0)
node _d_bits_corrupt_T_1 = and(s3_req.bad, _d_bits_corrupt_T)
connect d.bits.corrupt, _d_bits_corrupt_T_1
node _queue_io_deq_ready_T = and(s3_valid, s4_ready)
node _queue_io_deq_ready_T_1 = and(_queue_io_deq_ready_T, s3_need_r)
connect queue.io.deq.ready, _queue_io_deq_ready_T_1
node _T_23 = eq(s3_full, UInt<1>(0h0))
node _T_24 = eq(s3_need_r, UInt<1>(0h0))
node _T_25 = or(_T_23, _T_24)
node _T_26 = or(_T_25, queue.io.deq.valid)
node _T_27 = asUInt(reset)
node _T_28 = eq(_T_27, UInt<1>(0h0))
when _T_28 :
node _T_29 = eq(_T_26, UInt<1>(0h0))
when _T_29 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceD.scala:232 assert (!s3_full || !s3_need_r || queue.io.deq.valid)\n") : printf_1
assert(clock, _T_26, UInt<1>(0h1), "") : assert_1
when d.ready :
connect s3_valid_d, UInt<1>(0h0)
node _T_30 = and(s3_valid, s4_ready)
when _T_30 :
connect s3_full, UInt<1>(0h0)
when s3_latch :
connect s3_valid_d, s2_need_d
when s3_latch :
connect s3_full, UInt<1>(0h1)
node _T_31 = eq(s4_ready, UInt<1>(0h0))
node _T_32 = and(s3_valid, _T_31)
node _s3_valid_T = eq(s3_valid_d, UInt<1>(0h0))
node _s3_valid_T_1 = or(_s3_valid_T, d.ready)
node _s3_valid_T_2 = and(s3_full, _s3_valid_T_1)
connect s3_valid, _s3_valid_T_2
node _s3_ready_T = eq(s3_full, UInt<1>(0h0))
node _s3_ready_T_1 = eq(s3_valid_d, UInt<1>(0h0))
node _s3_ready_T_2 = or(_s3_ready_T_1, d.ready)
node _s3_ready_T_3 = and(s4_ready, _s3_ready_T_2)
node _s3_ready_T_4 = or(_s3_ready_T, _s3_ready_T_3)
connect s3_ready, _s3_ready_T_4
node _s4_latch_T = and(s3_valid, s3_retires)
node s4_latch = and(_s4_latch_T, s4_ready)
regreset s4_full : UInt<1>, clock, reset, UInt<1>(0h0)
reg s4_beat : UInt<3>, clock
when s4_latch :
connect s4_beat, s3_beat
reg s4_need_r : UInt<1>, clock
when s4_latch :
connect s4_need_r, s3_need_r
reg s4_need_bs : UInt<1>, clock
when s4_latch :
connect s4_need_bs, s3_need_pb
reg s4_need_pb : UInt<1>, clock
when s4_latch :
connect s4_need_pb, s3_need_pb
reg s4_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock
when s4_latch :
connect s4_req, s3_req
reg s4_adjusted_opcode : UInt<3>, clock
when s4_latch :
connect s4_adjusted_opcode, s3_adjusted_opcode
reg s4_pdata : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>}, clock
when s4_latch :
connect s4_pdata, s3_pdata
reg s4_rdata : UInt<64>, clock
when s4_latch :
connect s4_rdata, s3_rdata
inst atomics of Atomics
connect atomics.clock, clock
connect atomics.reset, reset
connect atomics.io.write, s4_req.prio[2]
connect atomics.io.a.opcode, s4_adjusted_opcode
connect atomics.io.a.param, s4_req.param
connect atomics.io.a.size, UInt<1>(0h0)
connect atomics.io.a.source, UInt<1>(0h0)
connect atomics.io.a.address, UInt<1>(0h0)
connect atomics.io.a.mask, s4_pdata.mask
connect atomics.io.a.data, s4_pdata.data
invalidate atomics.io.a.corrupt
connect atomics.io.data_in, s4_rdata
node _io_bs_wadr_valid_T = and(s4_full, s4_need_bs)
connect io.bs_wadr.valid, _io_bs_wadr_valid_T
connect io.bs_wadr.bits.noop, UInt<1>(0h0)
connect io.bs_wadr.bits.way, s4_req.way
connect io.bs_wadr.bits.set, s4_req.set
connect io.bs_wadr.bits.beat, s4_beat
node _io_bs_wadr_bits_mask_T = bits(s4_pdata.mask, 0, 0)
node _io_bs_wadr_bits_mask_T_1 = bits(s4_pdata.mask, 1, 1)
node _io_bs_wadr_bits_mask_T_2 = bits(s4_pdata.mask, 2, 2)
node _io_bs_wadr_bits_mask_T_3 = bits(s4_pdata.mask, 3, 3)
node _io_bs_wadr_bits_mask_T_4 = bits(s4_pdata.mask, 4, 4)
node _io_bs_wadr_bits_mask_T_5 = bits(s4_pdata.mask, 5, 5)
node _io_bs_wadr_bits_mask_T_6 = bits(s4_pdata.mask, 6, 6)
node _io_bs_wadr_bits_mask_T_7 = bits(s4_pdata.mask, 7, 7)
node _io_bs_wadr_bits_mask_T_8 = or(_io_bs_wadr_bits_mask_T, _io_bs_wadr_bits_mask_T_1)
node _io_bs_wadr_bits_mask_T_9 = or(_io_bs_wadr_bits_mask_T_8, _io_bs_wadr_bits_mask_T_2)
node _io_bs_wadr_bits_mask_T_10 = or(_io_bs_wadr_bits_mask_T_9, _io_bs_wadr_bits_mask_T_3)
node _io_bs_wadr_bits_mask_T_11 = or(_io_bs_wadr_bits_mask_T_10, _io_bs_wadr_bits_mask_T_4)
node _io_bs_wadr_bits_mask_T_12 = or(_io_bs_wadr_bits_mask_T_11, _io_bs_wadr_bits_mask_T_5)
node _io_bs_wadr_bits_mask_T_13 = or(_io_bs_wadr_bits_mask_T_12, _io_bs_wadr_bits_mask_T_6)
node _io_bs_wadr_bits_mask_T_14 = or(_io_bs_wadr_bits_mask_T_13, _io_bs_wadr_bits_mask_T_7)
connect io.bs_wadr.bits.mask, _io_bs_wadr_bits_mask_T_14
connect io.bs_wdat.data, atomics.io.data_out
node _T_33 = and(s4_full, s4_need_pb)
node _T_34 = and(_T_33, s4_pdata.corrupt)
node _T_35 = eq(_T_34, UInt<1>(0h0))
node _T_36 = asUInt(reset)
node _T_37 = eq(_T_36, UInt<1>(0h0))
when _T_37 :
node _T_38 = eq(_T_35, UInt<1>(0h0))
when _T_38 :
printf(clock, UInt<1>(0h1), "Assertion failed: Data poisoning unsupported\n at SourceD.scala:277 assert (!(s4_full && s4_need_pb && s4_pdata.corrupt), \"Data poisoning unsupported\")\n") : printf_2
assert(clock, _T_35, UInt<1>(0h1), "") : assert_2
node _T_39 = eq(io.bs_wadr.ready, UInt<1>(0h0))
node _T_40 = and(io.bs_wadr.valid, _T_39)
node _T_41 = eq(s4_req.opcode, UInt<2>(0h2))
node _T_42 = and(s4_req.prio[0], _T_41)
node _T_43 = eq(s4_req.param, UInt<3>(0h0))
node _T_44 = and(_T_42, _T_43)
node _T_45 = eq(s4_req.opcode, UInt<2>(0h2))
node _T_46 = and(s4_req.prio[0], _T_45)
node _T_47 = eq(s4_req.param, UInt<3>(0h1))
node _T_48 = and(_T_46, _T_47)
node _T_49 = eq(s4_req.opcode, UInt<2>(0h2))
node _T_50 = and(s4_req.prio[0], _T_49)
node _T_51 = eq(s4_req.param, UInt<3>(0h2))
node _T_52 = and(_T_50, _T_51)
node _T_53 = eq(s4_req.opcode, UInt<2>(0h2))
node _T_54 = and(s4_req.prio[0], _T_53)
node _T_55 = eq(s4_req.param, UInt<3>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(s4_req.opcode, UInt<2>(0h2))
node _T_58 = and(s4_req.prio[0], _T_57)
node _T_59 = eq(s4_req.param, UInt<3>(0h4))
node _T_60 = and(_T_58, _T_59)
node _T_61 = eq(s4_req.opcode, UInt<2>(0h3))
node _T_62 = and(s4_req.prio[0], _T_61)
node _T_63 = eq(s4_req.param, UInt<3>(0h0))
node _T_64 = and(_T_62, _T_63)
node _T_65 = eq(s4_req.opcode, UInt<2>(0h3))
node _T_66 = and(s4_req.prio[0], _T_65)
node _T_67 = eq(s4_req.param, UInt<3>(0h1))
node _T_68 = and(_T_66, _T_67)
node _T_69 = eq(s4_req.opcode, UInt<2>(0h3))
node _T_70 = and(s4_req.prio[0], _T_69)
node _T_71 = eq(s4_req.param, UInt<3>(0h2))
node _T_72 = and(_T_70, _T_71)
node _T_73 = eq(s4_req.opcode, UInt<2>(0h3))
node _T_74 = and(s4_req.prio[0], _T_73)
node _T_75 = eq(s4_req.param, UInt<3>(0h3))
node _T_76 = and(_T_74, _T_75)
node _T_77 = eq(s4_need_bs, UInt<1>(0h0))
node _T_78 = or(io.bs_wadr.ready, _T_77)
when _T_78 :
connect s4_full, UInt<1>(0h0)
when s4_latch :
connect s4_full, UInt<1>(0h1)
node _s4_ready_T = eq(s3_retires, UInt<1>(0h0))
node _s4_ready_T_1 = eq(s4_full, UInt<1>(0h0))
node _s4_ready_T_2 = or(_s4_ready_T, _s4_ready_T_1)
node _s4_ready_T_3 = or(_s4_ready_T_2, io.bs_wadr.ready)
node _s4_ready_T_4 = eq(s4_need_bs, UInt<1>(0h0))
node _s4_ready_T_5 = or(_s4_ready_T_3, _s4_ready_T_4)
connect s4_ready, _s4_ready_T_5
node _retire_T = eq(s4_need_bs, UInt<1>(0h0))
node _retire_T_1 = or(io.bs_wadr.ready, _retire_T)
node retire = and(s4_full, _retire_T_1)
reg s5_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock
when retire :
connect s5_req, s4_req
reg s5_beat : UInt<3>, clock
when retire :
connect s5_beat, s4_beat
reg s5_dat : UInt<64>, clock
when retire :
connect s5_dat, atomics.io.data_out
reg s6_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock
when retire :
connect s6_req, s5_req
reg s6_beat : UInt<3>, clock
when retire :
connect s6_beat, s5_beat
reg s6_dat : UInt<64>, clock
when retire :
connect s6_dat, s5_dat
reg s7_dat : UInt<64>, clock
when retire :
connect s7_dat, s6_dat
node pre_s3_req = mux(s3_latch, s2_req, s3_req)
node pre_s4_req = mux(s4_latch, s3_req, s4_req)
node pre_s5_req = mux(retire, s4_req, s5_req)
node pre_s6_req = mux(retire, s5_req, s6_req)
node pre_s3_beat = mux(s3_latch, s2_beat, s3_beat)
node pre_s4_beat = mux(s4_latch, s3_beat, s4_beat)
node pre_s5_beat = mux(retire, s4_beat, s5_beat)
node pre_s6_beat = mux(retire, s5_beat, s6_beat)
node pre_s5_dat = mux(retire, atomics.io.data_out, s5_dat)
node pre_s6_dat = mux(retire, s5_dat, s6_dat)
node pre_s7_dat = mux(retire, s6_dat, s7_dat)
node _pre_s4_full_T = eq(s4_need_bs, UInt<1>(0h0))
node _pre_s4_full_T_1 = or(io.bs_wadr.ready, _pre_s4_full_T)
node _pre_s4_full_T_2 = eq(_pre_s4_full_T_1, UInt<1>(0h0))
node _pre_s4_full_T_3 = and(_pre_s4_full_T_2, s4_full)
node pre_s4_full = or(s4_latch, _pre_s4_full_T_3)
node _pre_s3_4_match_T = eq(pre_s4_req.set, pre_s3_req.set)
node _pre_s3_4_match_T_1 = eq(pre_s4_req.way, pre_s3_req.way)
node _pre_s3_4_match_T_2 = and(_pre_s3_4_match_T, _pre_s3_4_match_T_1)
node _pre_s3_4_match_T_3 = eq(pre_s4_beat, pre_s3_beat)
node _pre_s3_4_match_T_4 = and(_pre_s3_4_match_T_2, _pre_s3_4_match_T_3)
node pre_s3_4_match = and(_pre_s3_4_match_T_4, pre_s4_full)
node _pre_s3_5_match_T = eq(pre_s5_req.set, pre_s3_req.set)
node _pre_s3_5_match_T_1 = eq(pre_s5_req.way, pre_s3_req.way)
node _pre_s3_5_match_T_2 = and(_pre_s3_5_match_T, _pre_s3_5_match_T_1)
node _pre_s3_5_match_T_3 = eq(pre_s5_beat, pre_s3_beat)
node pre_s3_5_match = and(_pre_s3_5_match_T_2, _pre_s3_5_match_T_3)
node _pre_s3_6_match_T = eq(pre_s6_req.set, pre_s3_req.set)
node _pre_s3_6_match_T_1 = eq(pre_s6_req.way, pre_s3_req.way)
node _pre_s3_6_match_T_2 = and(_pre_s3_6_match_T, _pre_s3_6_match_T_1)
node _pre_s3_6_match_T_3 = eq(pre_s6_beat, pre_s3_beat)
node pre_s3_6_match = and(_pre_s3_6_match_T_2, _pre_s3_6_match_T_3)
node _pre_s3_4_bypass_sizeOH_T = or(pre_s4_req.size, UInt<3>(0h0))
node pre_s3_4_bypass_sizeOH_shiftAmount = bits(_pre_s3_4_bypass_sizeOH_T, 1, 0)
node _pre_s3_4_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_4_bypass_sizeOH_shiftAmount)
node _pre_s3_4_bypass_sizeOH_T_2 = bits(_pre_s3_4_bypass_sizeOH_T_1, 2, 0)
node pre_s3_4_bypass_sizeOH = or(_pre_s3_4_bypass_sizeOH_T_2, UInt<4>(0hf))
node pre_s3_4_bypass = mux(pre_s3_4_match, UInt<1>(0h1), UInt<1>(0h0))
node _pre_s3_5_bypass_sizeOH_T = or(pre_s5_req.size, UInt<3>(0h0))
node pre_s3_5_bypass_sizeOH_shiftAmount = bits(_pre_s3_5_bypass_sizeOH_T, 1, 0)
node _pre_s3_5_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_5_bypass_sizeOH_shiftAmount)
node _pre_s3_5_bypass_sizeOH_T_2 = bits(_pre_s3_5_bypass_sizeOH_T_1, 2, 0)
node pre_s3_5_bypass_sizeOH = or(_pre_s3_5_bypass_sizeOH_T_2, UInt<4>(0hf))
node pre_s3_5_bypass = mux(pre_s3_5_match, UInt<1>(0h1), UInt<1>(0h0))
node _pre_s3_6_bypass_sizeOH_T = or(pre_s6_req.size, UInt<3>(0h0))
node pre_s3_6_bypass_sizeOH_shiftAmount = bits(_pre_s3_6_bypass_sizeOH_T, 1, 0)
node _pre_s3_6_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_6_bypass_sizeOH_shiftAmount)
node _pre_s3_6_bypass_sizeOH_T_2 = bits(_pre_s3_6_bypass_sizeOH_T_1, 2, 0)
node pre_s3_6_bypass_sizeOH = or(_pre_s3_6_bypass_sizeOH_T_2, UInt<4>(0hf))
node pre_s3_6_bypass = mux(pre_s3_6_match, UInt<1>(0h1), UInt<1>(0h0))
reg s3_bypass_data_REG : UInt, clock
connect s3_bypass_data_REG, pre_s3_4_bypass
node _s3_bypass_data_T = bits(pre_s3_6_bypass, 0, 0)
node _s3_bypass_data_T_1 = bits(pre_s6_dat, 63, 0)
node _s3_bypass_data_T_2 = bits(pre_s7_dat, 63, 0)
node _s3_bypass_data_T_3 = mux(_s3_bypass_data_T, _s3_bypass_data_T_1, _s3_bypass_data_T_2)
node _s3_bypass_data_T_4 = bits(pre_s3_5_bypass, 0, 0)
node _s3_bypass_data_T_5 = bits(pre_s5_dat, 63, 0)
node _s3_bypass_data_T_6 = bits(_s3_bypass_data_T_3, 63, 0)
node _s3_bypass_data_T_7 = mux(_s3_bypass_data_T_4, _s3_bypass_data_T_5, _s3_bypass_data_T_6)
reg s3_bypass_data_REG_1 : UInt, clock
connect s3_bypass_data_REG_1, _s3_bypass_data_T_7
node _s3_bypass_data_T_8 = bits(s3_bypass_data_REG, 0, 0)
node _s3_bypass_data_T_9 = bits(atomics.io.data_out, 63, 0)
node _s3_bypass_data_T_10 = bits(s3_bypass_data_REG_1, 63, 0)
node _s3_bypass_data_T_11 = mux(_s3_bypass_data_T_8, _s3_bypass_data_T_9, _s3_bypass_data_T_10)
connect s3_bypass_data, _s3_bypass_data_T_11
node _s1_2_match_T = eq(s2_req.set, s1_req.set)
node _s1_2_match_T_1 = eq(s2_req.way, s1_req.way)
node _s1_2_match_T_2 = and(_s1_2_match_T, _s1_2_match_T_1)
node _s1_2_match_T_3 = eq(s2_beat, s1_beat)
node _s1_2_match_T_4 = and(_s1_2_match_T_2, _s1_2_match_T_3)
node _s1_2_match_T_5 = and(_s1_2_match_T_4, s2_full)
node s1_2_match = and(_s1_2_match_T_5, s2_retires)
node _s1_3_match_T = eq(s3_req.set, s1_req.set)
node _s1_3_match_T_1 = eq(s3_req.way, s1_req.way)
node _s1_3_match_T_2 = and(_s1_3_match_T, _s1_3_match_T_1)
node _s1_3_match_T_3 = eq(s3_beat, s1_beat)
node _s1_3_match_T_4 = and(_s1_3_match_T_2, _s1_3_match_T_3)
node _s1_3_match_T_5 = and(_s1_3_match_T_4, s3_full)
node s1_3_match = and(_s1_3_match_T_5, s3_retires)
node _s1_4_match_T = eq(s4_req.set, s1_req.set)
node _s1_4_match_T_1 = eq(s4_req.way, s1_req.way)
node _s1_4_match_T_2 = and(_s1_4_match_T, _s1_4_match_T_1)
node _s1_4_match_T_3 = eq(s4_beat, s1_beat)
node _s1_4_match_T_4 = and(_s1_4_match_T_2, _s1_4_match_T_3)
node s1_4_match = and(_s1_4_match_T_4, s4_full)
node s2 = eq(s1_2_match, UInt<1>(0h1))
node s3 = eq(s1_3_match, UInt<1>(0h0))
node s4 = eq(s1_4_match, UInt<1>(0h0))
node _T_79 = and(io.req.valid, s2)
node _T_80 = and(_T_79, s3)
node _T_81 = and(_T_80, s4)
node s2_1 = eq(s1_2_match, UInt<1>(0h1))
node s3_1 = eq(s1_3_match, UInt<1>(0h0))
node s4_1 = eq(s1_4_match, UInt<1>(0h0))
node _T_82 = and(io.req.valid, s2_1)
node _T_83 = and(_T_82, s3_1)
node _T_84 = and(_T_83, s4_1)
node s2_2 = eq(s1_2_match, UInt<1>(0h1))
node s3_2 = eq(s1_3_match, UInt<1>(0h0))
node s4_2 = eq(s1_4_match, UInt<1>(0h0))
node _T_85 = and(io.req.valid, s2_2)
node _T_86 = and(_T_85, s3_2)
node _T_87 = and(_T_86, s4_2)
node s2_3 = eq(s1_2_match, UInt<1>(0h1))
node s3_3 = eq(s1_3_match, UInt<1>(0h0))
node s4_3 = eq(s1_4_match, UInt<1>(0h0))
node _T_88 = and(io.req.valid, s2_3)
node _T_89 = and(_T_88, s3_3)
node _T_90 = and(_T_89, s4_3)
node s2_4 = eq(s1_2_match, UInt<1>(0h1))
node s3_4 = eq(s1_3_match, UInt<1>(0h0))
node s4_4 = eq(s1_4_match, UInt<1>(0h0))
node _T_91 = and(io.req.valid, s2_4)
node _T_92 = and(_T_91, s3_4)
node _T_93 = and(_T_92, s4_4)
node s2_5 = eq(s1_2_match, UInt<1>(0h1))
node s3_5 = eq(s1_3_match, UInt<1>(0h0))
node s4_5 = eq(s1_4_match, UInt<1>(0h0))
node _T_94 = and(io.req.valid, s2_5)
node _T_95 = and(_T_94, s3_5)
node _T_96 = and(_T_95, s4_5)
node s2_6 = eq(s1_2_match, UInt<1>(0h1))
node s3_6 = eq(s1_3_match, UInt<1>(0h0))
node s4_6 = eq(s1_4_match, UInt<1>(0h0))
node _T_97 = and(io.req.valid, s2_6)
node _T_98 = and(_T_97, s3_6)
node _T_99 = and(_T_98, s4_6)
node s2_7 = eq(s1_2_match, UInt<1>(0h1))
node s3_7 = eq(s1_3_match, UInt<1>(0h0))
node s4_7 = eq(s1_4_match, UInt<1>(0h0))
node _T_100 = and(io.req.valid, s2_7)
node _T_101 = and(_T_100, s3_7)
node _T_102 = and(_T_101, s4_7)
node _s1_2_bypass_sizeOH_T = or(s2_req.size, UInt<3>(0h0))
node s1_2_bypass_sizeOH_shiftAmount = bits(_s1_2_bypass_sizeOH_T, 1, 0)
node _s1_2_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_2_bypass_sizeOH_shiftAmount)
node _s1_2_bypass_sizeOH_T_2 = bits(_s1_2_bypass_sizeOH_T_1, 2, 0)
node s1_2_bypass_sizeOH = or(_s1_2_bypass_sizeOH_T_2, UInt<4>(0hf))
node s1_2_bypass = mux(s1_2_match, UInt<1>(0h1), UInt<1>(0h0))
node _s1_3_bypass_sizeOH_T = or(s3_req.size, UInt<3>(0h0))
node s1_3_bypass_sizeOH_shiftAmount = bits(_s1_3_bypass_sizeOH_T, 1, 0)
node _s1_3_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_3_bypass_sizeOH_shiftAmount)
node _s1_3_bypass_sizeOH_T_2 = bits(_s1_3_bypass_sizeOH_T_1, 2, 0)
node s1_3_bypass_sizeOH = or(_s1_3_bypass_sizeOH_T_2, UInt<4>(0hf))
node s1_3_bypass = mux(s1_3_match, UInt<1>(0h1), UInt<1>(0h0))
node _s1_4_bypass_sizeOH_T = or(s4_req.size, UInt<3>(0h0))
node s1_4_bypass_sizeOH_shiftAmount = bits(_s1_4_bypass_sizeOH_T, 1, 0)
node _s1_4_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_4_bypass_sizeOH_shiftAmount)
node _s1_4_bypass_sizeOH_T_2 = bits(_s1_4_bypass_sizeOH_T_1, 2, 0)
node s1_4_bypass_sizeOH = or(_s1_4_bypass_sizeOH_T_2, UInt<4>(0hf))
node s1_4_bypass = mux(s1_4_match, UInt<1>(0h1), UInt<1>(0h0))
node _s1_x_bypass_T = or(s1_2_bypass, s1_3_bypass)
node _s1_x_bypass_T_1 = or(_s1_x_bypass_T, s1_4_bypass)
connect s1_x_bypass, _s1_x_bypass_T_1
node _io_evict_safe_T = eq(busy, UInt<1>(0h0))
node _io_evict_safe_T_1 = neq(io.evict_req.way, s1_req_reg.way)
node _io_evict_safe_T_2 = or(_io_evict_safe_T, _io_evict_safe_T_1)
node _io_evict_safe_T_3 = neq(io.evict_req.set, s1_req_reg.set)
node _io_evict_safe_T_4 = or(_io_evict_safe_T_2, _io_evict_safe_T_3)
node _io_evict_safe_T_5 = eq(s2_full, UInt<1>(0h0))
node _io_evict_safe_T_6 = neq(io.evict_req.way, s2_req.way)
node _io_evict_safe_T_7 = or(_io_evict_safe_T_5, _io_evict_safe_T_6)
node _io_evict_safe_T_8 = neq(io.evict_req.set, s2_req.set)
node _io_evict_safe_T_9 = or(_io_evict_safe_T_7, _io_evict_safe_T_8)
node _io_evict_safe_T_10 = and(_io_evict_safe_T_4, _io_evict_safe_T_9)
node _io_evict_safe_T_11 = eq(s3_full, UInt<1>(0h0))
node _io_evict_safe_T_12 = neq(io.evict_req.way, s3_req.way)
node _io_evict_safe_T_13 = or(_io_evict_safe_T_11, _io_evict_safe_T_12)
node _io_evict_safe_T_14 = neq(io.evict_req.set, s3_req.set)
node _io_evict_safe_T_15 = or(_io_evict_safe_T_13, _io_evict_safe_T_14)
node _io_evict_safe_T_16 = and(_io_evict_safe_T_10, _io_evict_safe_T_15)
node _io_evict_safe_T_17 = eq(s4_full, UInt<1>(0h0))
node _io_evict_safe_T_18 = neq(io.evict_req.way, s4_req.way)
node _io_evict_safe_T_19 = or(_io_evict_safe_T_17, _io_evict_safe_T_18)
node _io_evict_safe_T_20 = neq(io.evict_req.set, s4_req.set)
node _io_evict_safe_T_21 = or(_io_evict_safe_T_19, _io_evict_safe_T_20)
node _io_evict_safe_T_22 = and(_io_evict_safe_T_16, _io_evict_safe_T_21)
connect io.evict_safe, _io_evict_safe_T_22
node _io_grant_safe_T = eq(busy, UInt<1>(0h0))
node _io_grant_safe_T_1 = neq(io.grant_req.way, s1_req_reg.way)
node _io_grant_safe_T_2 = or(_io_grant_safe_T, _io_grant_safe_T_1)
node _io_grant_safe_T_3 = neq(io.grant_req.set, s1_req_reg.set)
node _io_grant_safe_T_4 = or(_io_grant_safe_T_2, _io_grant_safe_T_3)
node _io_grant_safe_T_5 = eq(s2_full, UInt<1>(0h0))
node _io_grant_safe_T_6 = neq(io.grant_req.way, s2_req.way)
node _io_grant_safe_T_7 = or(_io_grant_safe_T_5, _io_grant_safe_T_6)
node _io_grant_safe_T_8 = neq(io.grant_req.set, s2_req.set)
node _io_grant_safe_T_9 = or(_io_grant_safe_T_7, _io_grant_safe_T_8)
node _io_grant_safe_T_10 = and(_io_grant_safe_T_4, _io_grant_safe_T_9)
node _io_grant_safe_T_11 = eq(s3_full, UInt<1>(0h0))
node _io_grant_safe_T_12 = neq(io.grant_req.way, s3_req.way)
node _io_grant_safe_T_13 = or(_io_grant_safe_T_11, _io_grant_safe_T_12)
node _io_grant_safe_T_14 = neq(io.grant_req.set, s3_req.set)
node _io_grant_safe_T_15 = or(_io_grant_safe_T_13, _io_grant_safe_T_14)
node _io_grant_safe_T_16 = and(_io_grant_safe_T_10, _io_grant_safe_T_15)
node _io_grant_safe_T_17 = eq(s4_full, UInt<1>(0h0))
node _io_grant_safe_T_18 = neq(io.grant_req.way, s4_req.way)
node _io_grant_safe_T_19 = or(_io_grant_safe_T_17, _io_grant_safe_T_18)
node _io_grant_safe_T_20 = neq(io.grant_req.set, s4_req.set)
node _io_grant_safe_T_21 = or(_io_grant_safe_T_19, _io_grant_safe_T_20)
node _io_grant_safe_T_22 = and(_io_grant_safe_T_16, _io_grant_safe_T_21)
connect io.grant_safe, _io_grant_safe_T_22 | module SourceD( // @[SourceD.scala:48:7]
input clock, // @[SourceD.scala:48:7]
input reset, // @[SourceD.scala:48:7]
output io_req_ready, // @[SourceD.scala:50:14]
input io_req_valid, // @[SourceD.scala:50:14]
input io_req_bits_prio_0, // @[SourceD.scala:50:14]
input io_req_bits_prio_1, // @[SourceD.scala:50:14]
input io_req_bits_prio_2, // @[SourceD.scala:50:14]
input io_req_bits_control, // @[SourceD.scala:50:14]
input [2:0] io_req_bits_opcode, // @[SourceD.scala:50:14]
input [2:0] io_req_bits_param, // @[SourceD.scala:50:14]
input [2:0] io_req_bits_size, // @[SourceD.scala:50:14]
input [8:0] io_req_bits_source, // @[SourceD.scala:50:14]
input [12:0] io_req_bits_tag, // @[SourceD.scala:50:14]
input [5:0] io_req_bits_offset, // @[SourceD.scala:50:14]
input [5:0] io_req_bits_put, // @[SourceD.scala:50:14]
input [9:0] io_req_bits_set, // @[SourceD.scala:50:14]
input [2:0] io_req_bits_sink, // @[SourceD.scala:50:14]
input [2:0] io_req_bits_way, // @[SourceD.scala:50:14]
input io_req_bits_bad, // @[SourceD.scala:50:14]
input io_d_ready, // @[SourceD.scala:50:14]
output io_d_valid, // @[SourceD.scala:50:14]
output [2:0] io_d_bits_opcode, // @[SourceD.scala:50:14]
output [1:0] io_d_bits_param, // @[SourceD.scala:50:14]
output [2:0] io_d_bits_size, // @[SourceD.scala:50:14]
output [8:0] io_d_bits_source, // @[SourceD.scala:50:14]
output [2:0] io_d_bits_sink, // @[SourceD.scala:50:14]
output io_d_bits_denied, // @[SourceD.scala:50:14]
output [63:0] io_d_bits_data, // @[SourceD.scala:50:14]
output io_d_bits_corrupt, // @[SourceD.scala:50:14]
input io_pb_pop_ready, // @[SourceD.scala:50:14]
output io_pb_pop_valid, // @[SourceD.scala:50:14]
output [5:0] io_pb_pop_bits_index, // @[SourceD.scala:50:14]
output io_pb_pop_bits_last, // @[SourceD.scala:50:14]
input [63:0] io_pb_beat_data, // @[SourceD.scala:50:14]
input [7:0] io_pb_beat_mask, // @[SourceD.scala:50:14]
input io_pb_beat_corrupt, // @[SourceD.scala:50:14]
input io_rel_pop_ready, // @[SourceD.scala:50:14]
output io_rel_pop_valid, // @[SourceD.scala:50:14]
output [5:0] io_rel_pop_bits_index, // @[SourceD.scala:50:14]
output io_rel_pop_bits_last, // @[SourceD.scala:50:14]
input [63:0] io_rel_beat_data, // @[SourceD.scala:50:14]
input io_rel_beat_corrupt, // @[SourceD.scala:50:14]
input io_bs_radr_ready, // @[SourceD.scala:50:14]
output io_bs_radr_valid, // @[SourceD.scala:50:14]
output [2:0] io_bs_radr_bits_way, // @[SourceD.scala:50:14]
output [9:0] io_bs_radr_bits_set, // @[SourceD.scala:50:14]
output [2:0] io_bs_radr_bits_beat, // @[SourceD.scala:50:14]
output io_bs_radr_bits_mask, // @[SourceD.scala:50:14]
input [63:0] io_bs_rdat_data, // @[SourceD.scala:50:14]
input io_bs_wadr_ready, // @[SourceD.scala:50:14]
output io_bs_wadr_valid, // @[SourceD.scala:50:14]
output [2:0] io_bs_wadr_bits_way, // @[SourceD.scala:50:14]
output [9:0] io_bs_wadr_bits_set, // @[SourceD.scala:50:14]
output [2:0] io_bs_wadr_bits_beat, // @[SourceD.scala:50:14]
output io_bs_wadr_bits_mask, // @[SourceD.scala:50:14]
output [63:0] io_bs_wdat_data, // @[SourceD.scala:50:14]
input [9:0] io_evict_req_set, // @[SourceD.scala:50:14]
input [2:0] io_evict_req_way, // @[SourceD.scala:50:14]
output io_evict_safe, // @[SourceD.scala:50:14]
input [9:0] io_grant_req_set, // @[SourceD.scala:50:14]
input [2:0] io_grant_req_way, // @[SourceD.scala:50:14]
output io_grant_safe // @[SourceD.scala:50:14]
);
wire [63:0] _atomics_io_data_out; // @[SourceD.scala:258:23]
wire _queue_io_enq_ready; // @[SourceD.scala:120:21]
wire _queue_io_deq_valid; // @[SourceD.scala:120:21]
wire io_req_valid_0 = io_req_valid; // @[SourceD.scala:48:7]
wire io_req_bits_prio_0_0 = io_req_bits_prio_0; // @[SourceD.scala:48:7]
wire io_req_bits_prio_1_0 = io_req_bits_prio_1; // @[SourceD.scala:48:7]
wire io_req_bits_prio_2_0 = io_req_bits_prio_2; // @[SourceD.scala:48:7]
wire io_req_bits_control_0 = io_req_bits_control; // @[SourceD.scala:48:7]
wire [2:0] io_req_bits_opcode_0 = io_req_bits_opcode; // @[SourceD.scala:48:7]
wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceD.scala:48:7]
wire [2:0] io_req_bits_size_0 = io_req_bits_size; // @[SourceD.scala:48:7]
wire [8:0] io_req_bits_source_0 = io_req_bits_source; // @[SourceD.scala:48:7]
wire [12:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceD.scala:48:7]
wire [5:0] io_req_bits_offset_0 = io_req_bits_offset; // @[SourceD.scala:48:7]
wire [5:0] io_req_bits_put_0 = io_req_bits_put; // @[SourceD.scala:48:7]
wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceD.scala:48:7]
wire [2:0] io_req_bits_sink_0 = io_req_bits_sink; // @[SourceD.scala:48:7]
wire [2:0] io_req_bits_way_0 = io_req_bits_way; // @[SourceD.scala:48:7]
wire io_req_bits_bad_0 = io_req_bits_bad; // @[SourceD.scala:48:7]
wire io_d_ready_0 = io_d_ready; // @[SourceD.scala:48:7]
wire io_pb_pop_ready_0 = io_pb_pop_ready; // @[SourceD.scala:48:7]
wire [63:0] io_pb_beat_data_0 = io_pb_beat_data; // @[SourceD.scala:48:7]
wire [7:0] io_pb_beat_mask_0 = io_pb_beat_mask; // @[SourceD.scala:48:7]
wire io_pb_beat_corrupt_0 = io_pb_beat_corrupt; // @[SourceD.scala:48:7]
wire io_rel_pop_ready_0 = io_rel_pop_ready; // @[SourceD.scala:48:7]
wire [63:0] io_rel_beat_data_0 = io_rel_beat_data; // @[SourceD.scala:48:7]
wire io_rel_beat_corrupt_0 = io_rel_beat_corrupt; // @[SourceD.scala:48:7]
wire io_bs_radr_ready_0 = io_bs_radr_ready; // @[SourceD.scala:48:7]
wire [63:0] io_bs_rdat_data_0 = io_bs_rdat_data; // @[SourceD.scala:48:7]
wire io_bs_wadr_ready_0 = io_bs_wadr_ready; // @[SourceD.scala:48:7]
wire [9:0] io_evict_req_set_0 = io_evict_req_set; // @[SourceD.scala:48:7]
wire [2:0] io_evict_req_way_0 = io_evict_req_way; // @[SourceD.scala:48:7]
wire [9:0] io_grant_req_set_0 = io_grant_req_set; // @[SourceD.scala:48:7]
wire [2:0] io_grant_req_way_0 = io_grant_req_way; // @[SourceD.scala:48:7]
wire io_bs_radr_bits_noop = 1'h0; // @[SourceD.scala:48:7]
wire io_bs_wadr_bits_noop = 1'h0; // @[SourceD.scala:48:7]
wire [3:0] s1_mask_sizeOH = 4'hF; // @[Misc.scala:202:81]
wire [3:0] pre_s3_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81]
wire [3:0] pre_s3_5_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81]
wire [3:0] pre_s3_6_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81]
wire [3:0] s1_2_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81]
wire [3:0] s1_3_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81]
wire [3:0] s1_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81]
wire [2:0] resp_opcode_0 = 3'h0; // @[SourceD.scala:215:28]
wire [2:0] resp_opcode_1 = 3'h0; // @[SourceD.scala:215:28]
wire [2:0] resp_opcode_7 = 3'h4; // @[SourceD.scala:215:28]
wire [2:0] resp_opcode_5 = 3'h2; // @[SourceD.scala:215:28]
wire [2:0] resp_opcode_2 = 3'h1; // @[SourceD.scala:215:28]
wire [2:0] resp_opcode_3 = 3'h1; // @[SourceD.scala:215:28]
wire [2:0] resp_opcode_4 = 3'h1; // @[SourceD.scala:215:28]
wire [7:0] _s2_pdata_raw_mask_T = 8'hFF; // @[SourceD.scala:161:64]
wire _io_req_ready_T; // @[SourceD.scala:140:19]
wire d_ready = io_d_ready_0; // @[SourceD.scala:48:7, :218:15]
wire d_valid; // @[SourceD.scala:218:15]
wire [2:0] d_bits_opcode; // @[SourceD.scala:218:15]
wire [1:0] d_bits_param; // @[SourceD.scala:218:15]
wire [2:0] d_bits_size; // @[SourceD.scala:218:15]
wire [8:0] d_bits_source; // @[SourceD.scala:218:15]
wire [2:0] d_bits_sink; // @[SourceD.scala:218:15]
wire d_bits_denied; // @[SourceD.scala:218:15]
wire [63:0] d_bits_data; // @[SourceD.scala:218:15]
wire d_bits_corrupt; // @[SourceD.scala:218:15]
wire _io_pb_pop_valid_T; // @[SourceD.scala:164:34]
wire _io_rel_pop_valid_T_1; // @[SourceD.scala:167:35]
wire s1_valid_r; // @[SourceD.scala:96:56]
wire [2:0] s1_req_way; // @[SourceD.scala:88:19]
wire [9:0] s1_req_set; // @[SourceD.scala:88:19]
wire [2:0] s1_beat; // @[SourceD.scala:102:56]
wire s1_mask; // @[SourceD.scala:92:76]
wire _io_bs_wadr_valid_T; // @[SourceD.scala:270:31]
wire _io_bs_wadr_bits_mask_T_14; // @[SourceD.scala:275:87]
wire _io_evict_safe_T_22; // @[SourceD.scala:378:90]
wire _io_grant_safe_T_22; // @[SourceD.scala:385:90]
wire io_req_ready_0; // @[SourceD.scala:48:7]
wire [2:0] io_d_bits_opcode_0; // @[SourceD.scala:48:7]
wire [1:0] io_d_bits_param_0; // @[SourceD.scala:48:7]
wire [2:0] io_d_bits_size_0; // @[SourceD.scala:48:7]
wire [8:0] io_d_bits_source_0; // @[SourceD.scala:48:7]
wire [2:0] io_d_bits_sink_0; // @[SourceD.scala:48:7]
wire io_d_bits_denied_0; // @[SourceD.scala:48:7]
wire [63:0] io_d_bits_data_0; // @[SourceD.scala:48:7]
wire io_d_bits_corrupt_0; // @[SourceD.scala:48:7]
wire io_d_valid_0; // @[SourceD.scala:48:7]
wire [5:0] io_pb_pop_bits_index_0; // @[SourceD.scala:48:7]
wire io_pb_pop_bits_last_0; // @[SourceD.scala:48:7]
wire io_pb_pop_valid_0; // @[SourceD.scala:48:7]
wire [5:0] io_rel_pop_bits_index_0; // @[SourceD.scala:48:7]
wire io_rel_pop_bits_last_0; // @[SourceD.scala:48:7]
wire io_rel_pop_valid_0; // @[SourceD.scala:48:7]
wire [2:0] io_bs_radr_bits_way_0; // @[SourceD.scala:48:7]
wire [9:0] io_bs_radr_bits_set_0; // @[SourceD.scala:48:7]
wire [2:0] io_bs_radr_bits_beat_0; // @[SourceD.scala:48:7]
wire io_bs_radr_bits_mask_0; // @[SourceD.scala:48:7]
wire io_bs_radr_valid_0; // @[SourceD.scala:48:7]
wire [2:0] io_bs_wadr_bits_way_0; // @[SourceD.scala:48:7]
wire [9:0] io_bs_wadr_bits_set_0; // @[SourceD.scala:48:7]
wire [2:0] io_bs_wadr_bits_beat_0; // @[SourceD.scala:48:7]
wire io_bs_wadr_bits_mask_0; // @[SourceD.scala:48:7]
wire io_bs_wadr_valid_0; // @[SourceD.scala:48:7]
wire [63:0] io_bs_wdat_data_0; // @[SourceD.scala:48:7]
wire io_evict_safe_0; // @[SourceD.scala:48:7]
wire io_grant_safe_0; // @[SourceD.scala:48:7]
wire _s1_valid_T_3; // @[SourceD.scala:141:38]
wire s1_valid; // @[SourceD.scala:74:22]
wire _s2_valid_T_2; // @[SourceD.scala:183:23]
wire s2_valid; // @[SourceD.scala:75:22]
wire _s3_valid_T_2; // @[SourceD.scala:241:23]
wire s3_valid; // @[SourceD.scala:76:22]
wire _s2_ready_T_4; // @[SourceD.scala:184:24]
wire s2_ready; // @[SourceD.scala:77:22]
wire _s3_ready_T_4; // @[SourceD.scala:242:24]
wire s3_ready; // @[SourceD.scala:78:22]
wire _s4_ready_T_5; // @[SourceD.scala:293:59]
wire s4_ready; // @[SourceD.scala:79:22]
reg busy; // @[SourceD.scala:84:21]
reg s1_block_r; // @[SourceD.scala:85:27]
reg [2:0] s1_counter; // @[SourceD.scala:86:27]
wire _s1_req_reg_T = ~busy; // @[SourceD.scala:84:21, :87:43]
wire _s1_req_reg_T_1 = _s1_req_reg_T & io_req_valid_0; // @[SourceD.scala:48:7, :87:{43,49}]
reg s1_req_reg_prio_0; // @[SourceD.scala:87:29]
reg s1_req_reg_prio_1; // @[SourceD.scala:87:29]
reg s1_req_reg_prio_2; // @[SourceD.scala:87:29]
reg s1_req_reg_control; // @[SourceD.scala:87:29]
reg [2:0] s1_req_reg_opcode; // @[SourceD.scala:87:29]
reg [2:0] s1_req_reg_param; // @[SourceD.scala:87:29]
reg [2:0] s1_req_reg_size; // @[SourceD.scala:87:29]
reg [8:0] s1_req_reg_source; // @[SourceD.scala:87:29]
reg [12:0] s1_req_reg_tag; // @[SourceD.scala:87:29]
reg [5:0] s1_req_reg_offset; // @[SourceD.scala:87:29]
reg [5:0] s1_req_reg_put; // @[SourceD.scala:87:29]
reg [9:0] s1_req_reg_set; // @[SourceD.scala:87:29]
reg [2:0] s1_req_reg_sink; // @[SourceD.scala:87:29]
reg [2:0] s1_req_reg_way; // @[SourceD.scala:87:29]
reg s1_req_reg_bad; // @[SourceD.scala:87:29]
wire _s1_req_T = ~busy; // @[SourceD.scala:84:21, :87:43, :88:20]
wire s1_req_prio_0 = _s1_req_T ? io_req_bits_prio_0_0 : s1_req_reg_prio_0; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire s1_req_prio_1 = _s1_req_T ? io_req_bits_prio_1_0 : s1_req_reg_prio_1; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire s1_req_prio_2 = _s1_req_T ? io_req_bits_prio_2_0 : s1_req_reg_prio_2; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire s1_req_control = _s1_req_T ? io_req_bits_control_0 : s1_req_reg_control; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire [2:0] s1_req_opcode = _s1_req_T ? io_req_bits_opcode_0 : s1_req_reg_opcode; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire [2:0] s1_req_param = _s1_req_T ? io_req_bits_param_0 : s1_req_reg_param; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire [2:0] s1_req_size = _s1_req_T ? io_req_bits_size_0 : s1_req_reg_size; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire [8:0] s1_req_source = _s1_req_T ? io_req_bits_source_0 : s1_req_reg_source; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire [12:0] s1_req_tag = _s1_req_T ? io_req_bits_tag_0 : s1_req_reg_tag; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire [5:0] s1_req_offset = _s1_req_T ? io_req_bits_offset_0 : s1_req_reg_offset; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire [5:0] s1_req_put = _s1_req_T ? io_req_bits_put_0 : s1_req_reg_put; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
assign s1_req_set = _s1_req_T ? io_req_bits_set_0 : s1_req_reg_set; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire [2:0] s1_req_sink = _s1_req_T ? io_req_bits_sink_0 : s1_req_reg_sink; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
assign s1_req_way = _s1_req_T ? io_req_bits_way_0 : s1_req_reg_way; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire s1_req_bad = _s1_req_T ? io_req_bits_bad_0 : s1_req_reg_bad; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire [2:0] _s1_mask_sizeOH_T = s1_req_size; // @[Misc.scala:202:34]
assign io_bs_radr_bits_set_0 = s1_req_set; // @[SourceD.scala:48:7, :88:19]
assign io_bs_radr_bits_way_0 = s1_req_way; // @[SourceD.scala:48:7, :88:19]
wire _s1_x_bypass_T_1; // @[SourceD.scala:360:44]
wire s1_x_bypass; // @[SourceD.scala:89:25]
wire _T_1 = busy | io_req_valid_0; // @[SourceD.scala:48:7, :84:21, :90:40]
wire _s1_latch_bypass_T; // @[SourceD.scala:90:40]
assign _s1_latch_bypass_T = _T_1; // @[SourceD.scala:90:40]
wire _s1_valid_r_T; // @[SourceD.scala:96:26]
assign _s1_valid_r_T = _T_1; // @[SourceD.scala:90:40, :96:26]
wire _s1_valid_T; // @[SourceD.scala:141:21]
assign _s1_valid_T = _T_1; // @[SourceD.scala:90:40, :141:21]
wire _s1_latch_bypass_T_1 = ~_s1_latch_bypass_T; // @[SourceD.scala:90:{33,40}]
wire _s1_latch_bypass_T_2 = _s1_latch_bypass_T_1 | s2_ready; // @[SourceD.scala:77:22, :90:{33,57}]
reg s1_latch_bypass; // @[SourceD.scala:90:32]
reg s1_bypass_r; // @[SourceD.scala:91:62]
wire s1_bypass = s1_latch_bypass ? s1_x_bypass : s1_bypass_r; // @[SourceD.scala:89:25, :90:32, :91:{22,62}]
wire [1:0] s1_mask_sizeOH_shiftAmount = _s1_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _s1_mask_sizeOH_T_1 = 4'h1 << s1_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _s1_mask_sizeOH_T_2 = _s1_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire _s1_mask_T = ~s1_bypass; // @[SourceD.scala:91:22, :92:78]
assign s1_mask = _s1_mask_T; // @[SourceD.scala:92:{76,78}]
assign io_bs_radr_bits_mask_0 = s1_mask; // @[SourceD.scala:48:7, :92:76]
wire _s1_need_r_T = s1_mask; // @[SourceD.scala:92:76, :94:27]
wire _GEN = s1_req_opcode == 3'h6; // @[SourceD.scala:88:19, :93:33]
wire _s1_grant_T; // @[SourceD.scala:93:33]
assign _s1_grant_T = _GEN; // @[SourceD.scala:93:33]
wire _s1_single_T_2; // @[SourceD.scala:98:89]
assign _s1_single_T_2 = _GEN; // @[SourceD.scala:93:33, :98:89]
wire _s1_grant_T_1 = s1_req_param == 3'h2; // @[SourceD.scala:88:19, :93:66]
wire _s1_grant_T_2 = _s1_grant_T & _s1_grant_T_1; // @[SourceD.scala:93:{33,50,66}]
wire _s1_grant_T_3 = &s1_req_opcode; // @[SourceD.scala:88:19, :93:93]
wire s1_grant = _s1_grant_T_2 | _s1_grant_T_3; // @[SourceD.scala:93:{50,76,93}]
wire _s1_need_r_T_1 = _s1_need_r_T & s1_req_prio_0; // @[SourceD.scala:88:19, :94:{27,31}]
wire _s1_need_r_T_2 = s1_req_opcode != 3'h5; // @[SourceD.scala:88:19, :94:66]
wire _s1_need_r_T_3 = _s1_need_r_T_1 & _s1_need_r_T_2; // @[SourceD.scala:94:{31,49,66}]
wire _s1_need_r_T_4 = ~s1_grant; // @[SourceD.scala:93:76, :94:78]
wire _s1_need_r_T_5 = _s1_need_r_T_3 & _s1_need_r_T_4; // @[SourceD.scala:94:{49,75,78}]
wire _s1_need_r_T_6 = |s1_req_opcode; // @[SourceD.scala:88:19, :95:34]
wire _s1_need_r_T_7 = s1_req_size < 3'h3; // @[SourceD.scala:88:19, :95:65]
wire _s1_need_r_T_8 = _s1_need_r_T_6 | _s1_need_r_T_7; // @[SourceD.scala:95:{34,50,65}]
wire s1_need_r = _s1_need_r_T_5 & _s1_need_r_T_8; // @[SourceD.scala:94:{75,88}, :95:50]
wire _s1_valid_r_T_1 = _s1_valid_r_T & s1_need_r; // @[SourceD.scala:94:88, :96:{26,43}]
wire _s1_valid_r_T_2 = ~s1_block_r; // @[SourceD.scala:85:27, :96:59]
assign s1_valid_r = _s1_valid_r_T_1 & _s1_valid_r_T_2; // @[SourceD.scala:96:{43,56,59}]
assign io_bs_radr_valid_0 = s1_valid_r; // @[SourceD.scala:48:7, :96:56]
wire _s1_need_pb_T = s1_req_opcode[2]; // @[SourceD.scala:88:19, :97:54]
wire _s1_need_pb_T_1 = ~_s1_need_pb_T; // @[SourceD.scala:97:{40,54}]
wire _s1_need_pb_T_2 = s1_req_opcode[0]; // @[SourceD.scala:88:19, :97:72]
wire s1_need_pb = s1_req_prio_0 ? _s1_need_pb_T_1 : _s1_need_pb_T_2; // @[SourceD.scala:88:19, :97:{23,40,72}]
wire _s1_single_T = s1_req_opcode == 3'h5; // @[SourceD.scala:88:19, :98:53]
wire _s1_single_T_1 = _s1_single_T | s1_grant; // @[SourceD.scala:93:76, :98:{53,62}]
wire s1_single = s1_req_prio_0 ? _s1_single_T_1 : _s1_single_T_2; // @[SourceD.scala:88:19, :98:{22,62,89}]
wire s1_retires = ~s1_single; // @[SourceD.scala:98:22, :99:20]
wire [12:0] _s1_beats1_T = 13'h3F << s1_req_size; // @[package.scala:243:71]
wire [5:0] _s1_beats1_T_1 = _s1_beats1_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _s1_beats1_T_2 = ~_s1_beats1_T_1; // @[package.scala:243:{46,76}]
wire [2:0] _s1_beats1_T_3 = _s1_beats1_T_2[5:3]; // @[package.scala:243:46]
wire [2:0] s1_beats1 = s1_single ? 3'h0 : _s1_beats1_T_3; // @[SourceD.scala:98:22, :101:{22,95}]
wire [2:0] _s1_beat_T = s1_req_offset[5:3]; // @[SourceD.scala:88:19, :102:32]
assign s1_beat = _s1_beat_T | s1_counter; // @[SourceD.scala:86:27, :102:{32,56}]
assign io_bs_radr_bits_beat_0 = s1_beat; // @[SourceD.scala:48:7, :102:56]
wire s1_last = s1_counter == s1_beats1; // @[SourceD.scala:86:27, :101:22, :103:28]
wire s1_first = s1_counter == 3'h0; // @[SourceD.scala:86:27, :104:29]
wire _queue_io_enq_valid_T = io_bs_radr_ready_0 & io_bs_radr_valid_0; // @[Decoupled.scala:51:35]
reg queue_io_enq_valid_REG; // @[SourceD.scala:121:40]
reg queue_io_enq_valid_REG_1; // @[SourceD.scala:121:32]
wire s2_latch = s1_valid & s2_ready; // @[SourceD.scala:74:22, :77:22, :129:18, :146:27]
wire [3:0] _s1_counter_T = {1'h0, s1_counter} + 4'h1; // @[SourceD.scala:86:27, :130:30]
wire [2:0] _s1_counter_T_1 = _s1_counter_T[2:0]; // @[SourceD.scala:130:30]
assign _io_req_ready_T = ~busy; // @[SourceD.scala:84:21, :87:43, :140:19]
assign io_req_ready_0 = _io_req_ready_T; // @[SourceD.scala:48:7, :140:19]
wire _s1_valid_T_1 = ~s1_valid_r; // @[SourceD.scala:96:56, :141:42]
wire _s1_valid_T_2 = _s1_valid_T_1 | io_bs_radr_ready_0; // @[SourceD.scala:48:7, :141:{42,54}]
assign _s1_valid_T_3 = _s1_valid_T & _s1_valid_T_2; // @[SourceD.scala:141:{21,38,54}]
assign s1_valid = _s1_valid_T_3; // @[SourceD.scala:74:22, :141:38]
reg s2_full; // @[SourceD.scala:147:24]
reg s2_valid_pb; // @[SourceD.scala:148:28]
reg [2:0] s2_beat; // @[SourceD.scala:149:26]
reg s2_bypass; // @[SourceD.scala:150:28]
reg s2_req_prio_0; // @[SourceD.scala:151:25]
reg s2_req_prio_1; // @[SourceD.scala:151:25]
reg s2_req_prio_2; // @[SourceD.scala:151:25]
reg s2_req_control; // @[SourceD.scala:151:25]
reg [2:0] s2_req_opcode; // @[SourceD.scala:151:25]
reg [2:0] s2_req_param; // @[SourceD.scala:151:25]
reg [2:0] s2_req_size; // @[SourceD.scala:151:25]
wire [2:0] _s1_2_bypass_sizeOH_T = s2_req_size; // @[Misc.scala:202:34]
reg [8:0] s2_req_source; // @[SourceD.scala:151:25]
reg [12:0] s2_req_tag; // @[SourceD.scala:151:25]
reg [5:0] s2_req_offset; // @[SourceD.scala:151:25]
reg [5:0] s2_req_put; // @[SourceD.scala:151:25]
assign io_pb_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25]
assign io_rel_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25]
reg [9:0] s2_req_set; // @[SourceD.scala:151:25]
reg [2:0] s2_req_sink; // @[SourceD.scala:151:25]
reg [2:0] s2_req_way; // @[SourceD.scala:151:25]
reg s2_req_bad; // @[SourceD.scala:151:25]
reg s2_last; // @[SourceD.scala:152:26]
assign io_pb_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26]
assign io_rel_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26]
reg s2_need_r; // @[SourceD.scala:153:28]
reg s2_need_pb; // @[SourceD.scala:154:29]
reg s2_retires; // @[SourceD.scala:155:29]
wire _s2_need_d_T = ~s1_need_pb; // @[SourceD.scala:97:23, :156:29]
wire _s2_need_d_T_1 = _s2_need_d_T | s1_first; // @[SourceD.scala:104:29, :156:{29,41}]
reg s2_need_d; // @[SourceD.scala:156:28]
wire [63:0] _s2_pdata_raw_data_T; // @[SourceD.scala:160:30]
wire [7:0] _s2_pdata_raw_mask_T_1; // @[SourceD.scala:161:30]
wire _s2_pdata_raw_corrupt_T; // @[SourceD.scala:162:30]
wire [63:0] s2_pdata_raw_data; // @[SourceD.scala:157:26]
wire [7:0] s2_pdata_raw_mask; // @[SourceD.scala:157:26]
wire s2_pdata_raw_corrupt; // @[SourceD.scala:157:26]
reg [63:0] s2_pdata_r_data; // @[package.scala:88:63]
reg [7:0] s2_pdata_r_mask; // @[package.scala:88:63]
reg s2_pdata_r_corrupt; // @[package.scala:88:63]
wire [63:0] s2_pdata_data = s2_valid_pb ? s2_pdata_raw_data : s2_pdata_r_data; // @[package.scala:88:{42,63}]
wire [7:0] s2_pdata_mask = s2_valid_pb ? s2_pdata_raw_mask : s2_pdata_r_mask; // @[package.scala:88:{42,63}]
wire s2_pdata_corrupt = s2_valid_pb ? s2_pdata_raw_corrupt : s2_pdata_r_corrupt; // @[package.scala:88:{42,63}]
assign _s2_pdata_raw_data_T = s2_req_prio_0 ? io_pb_beat_data_0 : io_rel_beat_data_0; // @[SourceD.scala:48:7, :151:25, :160:30]
assign s2_pdata_raw_data = _s2_pdata_raw_data_T; // @[SourceD.scala:157:26, :160:30]
assign _s2_pdata_raw_mask_T_1 = s2_req_prio_0 ? io_pb_beat_mask_0 : 8'hFF; // @[SourceD.scala:48:7, :151:25, :161:30]
assign s2_pdata_raw_mask = _s2_pdata_raw_mask_T_1; // @[SourceD.scala:157:26, :161:30]
assign _s2_pdata_raw_corrupt_T = s2_req_prio_0 ? io_pb_beat_corrupt_0 : io_rel_beat_corrupt_0; // @[SourceD.scala:48:7, :151:25, :162:30]
assign s2_pdata_raw_corrupt = _s2_pdata_raw_corrupt_T; // @[SourceD.scala:157:26, :162:30]
assign _io_pb_pop_valid_T = s2_valid_pb & s2_req_prio_0; // @[SourceD.scala:148:28, :151:25, :164:34]
assign io_pb_pop_valid_0 = _io_pb_pop_valid_T; // @[SourceD.scala:48:7, :164:34]
wire _io_rel_pop_valid_T = ~s2_req_prio_0; // @[SourceD.scala:151:25, :167:38]
assign _io_rel_pop_valid_T_1 = s2_valid_pb & _io_rel_pop_valid_T; // @[SourceD.scala:148:28, :167:{35,38}]
assign io_rel_pop_valid_0 = _io_rel_pop_valid_T_1; // @[SourceD.scala:48:7, :167:35]
wire pb_ready = s2_req_prio_0 ? io_pb_pop_ready_0 : io_rel_pop_ready_0; // @[SourceD.scala:48:7, :151:25, :175:21]
wire s3_latch = s2_valid & s3_ready; // @[SourceD.scala:75:22, :78:22, :177:18, :189:27]
wire _s2_valid_T = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27]
wire _s2_valid_T_1 = _s2_valid_T | pb_ready; // @[SourceD.scala:175:21, :183:{27,40}]
assign _s2_valid_T_2 = s2_full & _s2_valid_T_1; // @[SourceD.scala:147:24, :183:{23,40}]
assign s2_valid = _s2_valid_T_2; // @[SourceD.scala:75:22, :183:23]
wire _s2_ready_T = ~s2_full; // @[SourceD.scala:147:24, :184:15]
wire _s2_ready_T_1 = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27, :184:41]
wire _s2_ready_T_2 = _s2_ready_T_1 | pb_ready; // @[SourceD.scala:175:21, :184:{41,54}]
wire _s2_ready_T_3 = s3_ready & _s2_ready_T_2; // @[SourceD.scala:78:22, :184:{37,54}]
assign _s2_ready_T_4 = _s2_ready_T | _s2_ready_T_3; // @[SourceD.scala:184:{15,24,37}]
assign s2_ready = _s2_ready_T_4; // @[SourceD.scala:77:22, :184:24]
reg s3_full; // @[SourceD.scala:190:24]
reg s3_valid_d; // @[SourceD.scala:191:27]
assign d_valid = s3_valid_d; // @[SourceD.scala:191:27, :218:15]
reg [2:0] s3_beat; // @[SourceD.scala:192:26]
wire [2:0] pre_s3_beat = s3_latch ? s2_beat : s3_beat; // @[SourceD.scala:149:26, :189:27, :192:26, :319:24]
reg s3_bypass; // @[SourceD.scala:193:28]
wire _s3_rdata_T = s3_bypass; // @[SourceD.scala:193:28, :208:78]
reg s3_req_prio_0; // @[SourceD.scala:194:25]
reg s3_req_prio_1; // @[SourceD.scala:194:25]
reg s3_req_prio_2; // @[SourceD.scala:194:25]
reg s3_req_control; // @[SourceD.scala:194:25]
reg [2:0] s3_req_opcode; // @[SourceD.scala:194:25]
reg [2:0] s3_req_param; // @[SourceD.scala:194:25]
reg [2:0] s3_req_size; // @[SourceD.scala:194:25]
assign d_bits_size = s3_req_size; // @[SourceD.scala:194:25, :218:15]
wire [2:0] _s1_3_bypass_sizeOH_T = s3_req_size; // @[Misc.scala:202:34]
reg [8:0] s3_req_source; // @[SourceD.scala:194:25]
assign d_bits_source = s3_req_source; // @[SourceD.scala:194:25, :218:15]
reg [12:0] s3_req_tag; // @[SourceD.scala:194:25]
reg [5:0] s3_req_offset; // @[SourceD.scala:194:25]
reg [5:0] s3_req_put; // @[SourceD.scala:194:25]
reg [9:0] s3_req_set; // @[SourceD.scala:194:25]
reg [2:0] s3_req_sink; // @[SourceD.scala:194:25]
assign d_bits_sink = s3_req_sink; // @[SourceD.scala:194:25, :218:15]
reg [2:0] s3_req_way; // @[SourceD.scala:194:25]
reg s3_req_bad; // @[SourceD.scala:194:25]
assign d_bits_denied = s3_req_bad; // @[SourceD.scala:194:25, :218:15]
wire pre_s3_req_prio_0 = s3_latch ? s2_req_prio_0 : s3_req_prio_0; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire pre_s3_req_prio_1 = s3_latch ? s2_req_prio_1 : s3_req_prio_1; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire pre_s3_req_prio_2 = s3_latch ? s2_req_prio_2 : s3_req_prio_2; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire pre_s3_req_control = s3_latch ? s2_req_control : s3_req_control; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [2:0] pre_s3_req_opcode = s3_latch ? s2_req_opcode : s3_req_opcode; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [2:0] pre_s3_req_param = s3_latch ? s2_req_param : s3_req_param; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [2:0] pre_s3_req_size = s3_latch ? s2_req_size : s3_req_size; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [8:0] pre_s3_req_source = s3_latch ? s2_req_source : s3_req_source; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [12:0] pre_s3_req_tag = s3_latch ? s2_req_tag : s3_req_tag; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [5:0] pre_s3_req_offset = s3_latch ? s2_req_offset : s3_req_offset; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [5:0] pre_s3_req_put = s3_latch ? s2_req_put : s3_req_put; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [9:0] pre_s3_req_set = s3_latch ? s2_req_set : s3_req_set; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [2:0] pre_s3_req_sink = s3_latch ? s2_req_sink : s3_req_sink; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [2:0] pre_s3_req_way = s3_latch ? s2_req_way : s3_req_way; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire pre_s3_req_bad = s3_latch ? s2_req_bad : s3_req_bad; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [2:0] s3_adjusted_opcode = s3_req_bad ? 3'h4 : s3_req_opcode; // @[SourceD.scala:194:25, :195:31]
reg s3_last; // @[SourceD.scala:196:26]
reg [63:0] s3_pdata_data; // @[SourceD.scala:197:27]
reg [7:0] s3_pdata_mask; // @[SourceD.scala:197:27]
reg s3_pdata_corrupt; // @[SourceD.scala:197:27]
reg s3_need_pb; // @[SourceD.scala:198:29]
reg s3_retires; // @[SourceD.scala:199:29]
reg s3_need_r; // @[SourceD.scala:200:28]
wire _s3_acq_T = s3_req_opcode == 3'h6; // @[SourceD.scala:194:25, :202:30]
wire _s3_acq_T_1 = &s3_req_opcode; // @[SourceD.scala:194:25, :202:64]
wire s3_acq = _s3_acq_T | _s3_acq_T_1; // @[SourceD.scala:202:{30,47,64}]
wire [63:0] _s3_bypass_data_T_11; // @[SourceD.scala:210:75]
wire [63:0] s3_bypass_data; // @[SourceD.scala:206:28]
wire [63:0] _s3_rdata_T_1 = s3_bypass_data; // @[SourceD.scala:206:28, :207:78]
wire [63:0] _s3_rdata_T_2; // @[SourceD.scala:207:78]
wire [63:0] s3_rdata = _s3_rdata_T ? _s3_rdata_T_1 : _s3_rdata_T_2; // @[SourceD.scala:207:78, :208:78, :210:75]
assign d_bits_data = s3_rdata; // @[SourceD.scala:210:75, :218:15]
wire _grant_T = s3_req_param == 3'h2; // @[SourceD.scala:194:25, :214:32]
wire [2:0] grant = {2'h2, ~_grant_T}; // @[SourceD.scala:214:{18,32}]
wire [2:0] resp_opcode_6 = grant; // @[SourceD.scala:214:18, :215:28]
assign io_d_valid_0 = d_valid; // @[SourceD.scala:48:7, :218:15]
wire [2:0] _d_bits_opcode_T; // @[SourceD.scala:222:24]
assign io_d_bits_opcode_0 = d_bits_opcode; // @[SourceD.scala:48:7, :218:15]
wire [1:0] _d_bits_param_T_3; // @[SourceD.scala:223:24]
assign io_d_bits_param_0 = d_bits_param; // @[SourceD.scala:48:7, :218:15]
assign io_d_bits_size_0 = d_bits_size; // @[SourceD.scala:48:7, :218:15]
assign io_d_bits_source_0 = d_bits_source; // @[SourceD.scala:48:7, :218:15]
assign io_d_bits_sink_0 = d_bits_sink; // @[SourceD.scala:48:7, :218:15]
assign io_d_bits_denied_0 = d_bits_denied; // @[SourceD.scala:48:7, :218:15]
assign io_d_bits_data_0 = d_bits_data; // @[SourceD.scala:48:7, :218:15]
wire _d_bits_corrupt_T_1; // @[SourceD.scala:229:32]
assign io_d_bits_corrupt_0 = d_bits_corrupt; // @[SourceD.scala:48:7, :218:15]
wire [7:0][2:0] _GEN_0 = {{3'h4}, {resp_opcode_6}, {3'h2}, {3'h1}, {3'h1}, {3'h1}, {3'h0}, {3'h0}}; // @[SourceD.scala:215:28, :222:24]
assign _d_bits_opcode_T = s3_req_prio_0 ? _GEN_0[s3_req_opcode] : 3'h6; // @[SourceD.scala:194:25, :222:24]
assign d_bits_opcode = _d_bits_opcode_T; // @[SourceD.scala:218:15, :222:24]
wire _d_bits_param_T = s3_req_prio_0 & s3_acq; // @[SourceD.scala:194:25, :202:47, :223:40]
wire _d_bits_param_T_1 = |s3_req_param; // @[SourceD.scala:194:25, :223:68]
wire [1:0] _d_bits_param_T_2 = {1'h0, ~_d_bits_param_T_1}; // @[SourceD.scala:223:{54,68}]
assign _d_bits_param_T_3 = _d_bits_param_T ? _d_bits_param_T_2 : 2'h0; // @[SourceD.scala:223:{24,40,54}]
assign d_bits_param = _d_bits_param_T_3; // @[SourceD.scala:218:15, :223:24]
wire _d_bits_corrupt_T = d_bits_opcode[0]; // @[SourceD.scala:218:15, :229:48]
assign _d_bits_corrupt_T_1 = s3_req_bad & _d_bits_corrupt_T; // @[SourceD.scala:194:25, :229:{32,48}]
assign d_bits_corrupt = _d_bits_corrupt_T_1; // @[SourceD.scala:218:15, :229:32]
wire _queue_io_deq_ready_T = s3_valid & s4_ready; // @[SourceD.scala:76:22, :79:22, :231:34]
wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & s3_need_r; // @[SourceD.scala:200:28, :231:{34,46}]
wire _s3_valid_T = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27]
wire _s3_valid_T_1 = _s3_valid_T | d_ready; // @[SourceD.scala:218:15, :241:{27,39}]
assign _s3_valid_T_2 = s3_full & _s3_valid_T_1; // @[SourceD.scala:190:24, :241:{23,39}]
assign s3_valid = _s3_valid_T_2; // @[SourceD.scala:76:22, :241:23]
wire _s3_ready_T = ~s3_full; // @[SourceD.scala:190:24, :232:11, :242:15]
wire _s3_ready_T_1 = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27, :242:41]
wire _s3_ready_T_2 = _s3_ready_T_1 | d_ready; // @[SourceD.scala:218:15, :242:{41,53}]
wire _s3_ready_T_3 = s4_ready & _s3_ready_T_2; // @[SourceD.scala:79:22, :242:{37,53}]
assign _s3_ready_T_4 = _s3_ready_T | _s3_ready_T_3; // @[SourceD.scala:242:{15,24,37}]
assign s3_ready = _s3_ready_T_4; // @[SourceD.scala:78:22, :242:24]
wire _s4_latch_T = s3_valid & s3_retires; // @[SourceD.scala:76:22, :199:29, :247:27]
wire s4_latch = _s4_latch_T & s4_ready; // @[SourceD.scala:79:22, :247:{27,41}]
reg s4_full; // @[SourceD.scala:248:24]
reg [2:0] s4_beat; // @[SourceD.scala:249:26]
assign io_bs_wadr_bits_beat_0 = s4_beat; // @[SourceD.scala:48:7, :249:26]
wire [2:0] pre_s4_beat = s4_latch ? s3_beat : s4_beat; // @[SourceD.scala:192:26, :247:41, :249:26, :320:24]
reg s4_need_r; // @[SourceD.scala:250:28]
reg s4_need_bs; // @[SourceD.scala:251:29]
reg s4_need_pb; // @[SourceD.scala:252:29]
reg s4_req_prio_0; // @[SourceD.scala:253:25]
reg s4_req_prio_1; // @[SourceD.scala:253:25]
reg s4_req_prio_2; // @[SourceD.scala:253:25]
reg s4_req_control; // @[SourceD.scala:253:25]
reg [2:0] s4_req_opcode; // @[SourceD.scala:253:25]
reg [2:0] s4_req_param; // @[SourceD.scala:253:25]
reg [2:0] s4_req_size; // @[SourceD.scala:253:25]
wire [2:0] _s1_4_bypass_sizeOH_T = s4_req_size; // @[Misc.scala:202:34]
reg [8:0] s4_req_source; // @[SourceD.scala:253:25]
reg [12:0] s4_req_tag; // @[SourceD.scala:253:25]
reg [5:0] s4_req_offset; // @[SourceD.scala:253:25]
reg [5:0] s4_req_put; // @[SourceD.scala:253:25]
reg [9:0] s4_req_set; // @[SourceD.scala:253:25]
assign io_bs_wadr_bits_set_0 = s4_req_set; // @[SourceD.scala:48:7, :253:25]
reg [2:0] s4_req_sink; // @[SourceD.scala:253:25]
reg [2:0] s4_req_way; // @[SourceD.scala:253:25]
assign io_bs_wadr_bits_way_0 = s4_req_way; // @[SourceD.scala:48:7, :253:25]
reg s4_req_bad; // @[SourceD.scala:253:25]
wire pre_s4_req_prio_0 = s4_latch ? s3_req_prio_0 : s4_req_prio_0; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire pre_s4_req_prio_1 = s4_latch ? s3_req_prio_1 : s4_req_prio_1; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire pre_s4_req_prio_2 = s4_latch ? s3_req_prio_2 : s4_req_prio_2; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire pre_s4_req_control = s4_latch ? s3_req_control : s4_req_control; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [2:0] pre_s4_req_opcode = s4_latch ? s3_req_opcode : s4_req_opcode; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [2:0] pre_s4_req_param = s4_latch ? s3_req_param : s4_req_param; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [2:0] pre_s4_req_size = s4_latch ? s3_req_size : s4_req_size; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [8:0] pre_s4_req_source = s4_latch ? s3_req_source : s4_req_source; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [12:0] pre_s4_req_tag = s4_latch ? s3_req_tag : s4_req_tag; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [5:0] pre_s4_req_offset = s4_latch ? s3_req_offset : s4_req_offset; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [5:0] pre_s4_req_put = s4_latch ? s3_req_put : s4_req_put; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [9:0] pre_s4_req_set = s4_latch ? s3_req_set : s4_req_set; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [2:0] pre_s4_req_sink = s4_latch ? s3_req_sink : s4_req_sink; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [2:0] pre_s4_req_way = s4_latch ? s3_req_way : s4_req_way; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire pre_s4_req_bad = s4_latch ? s3_req_bad : s4_req_bad; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
reg [2:0] s4_adjusted_opcode; // @[SourceD.scala:254:37]
reg [63:0] s4_pdata_data; // @[SourceD.scala:255:27]
reg [7:0] s4_pdata_mask; // @[SourceD.scala:255:27]
reg s4_pdata_corrupt; // @[SourceD.scala:255:27]
reg [63:0] s4_rdata; // @[SourceD.scala:256:27]
assign _io_bs_wadr_valid_T = s4_full & s4_need_bs; // @[SourceD.scala:248:24, :251:29, :270:31]
assign io_bs_wadr_valid_0 = _io_bs_wadr_valid_T; // @[SourceD.scala:48:7, :270:31]
wire _io_bs_wadr_bits_mask_T = s4_pdata_mask[0]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_1 = s4_pdata_mask[1]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_2 = s4_pdata_mask[2]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_3 = s4_pdata_mask[3]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_4 = s4_pdata_mask[4]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_5 = s4_pdata_mask[5]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_6 = s4_pdata_mask[6]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_7 = s4_pdata_mask[7]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_8 = _io_bs_wadr_bits_mask_T | _io_bs_wadr_bits_mask_T_1; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_9 = _io_bs_wadr_bits_mask_T_8 | _io_bs_wadr_bits_mask_T_2; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_10 = _io_bs_wadr_bits_mask_T_9 | _io_bs_wadr_bits_mask_T_3; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_11 = _io_bs_wadr_bits_mask_T_10 | _io_bs_wadr_bits_mask_T_4; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_12 = _io_bs_wadr_bits_mask_T_11 | _io_bs_wadr_bits_mask_T_5; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_13 = _io_bs_wadr_bits_mask_T_12 | _io_bs_wadr_bits_mask_T_6; // @[SourceD.scala:275:{45,87}]
assign _io_bs_wadr_bits_mask_T_14 = _io_bs_wadr_bits_mask_T_13 | _io_bs_wadr_bits_mask_T_7; // @[SourceD.scala:275:{45,87}]
assign io_bs_wadr_bits_mask_0 = _io_bs_wadr_bits_mask_T_14; // @[SourceD.scala:48:7, :275:87] |
Generate the Verilog code corresponding to this FIRRTL code module CompareRecFN_1 :
output io : { flip a : UInt<33>, flip b : UInt<33>, flip signaling : UInt<1>, lt : UInt<1>, eq : UInt<1>, gt : UInt<1>, exceptionFlags : UInt<5>}
node rawA_exp = bits(io.a, 31, 23)
node _rawA_isZero_T = bits(rawA_exp, 8, 6)
node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0))
node _rawA_isSpecial_T = bits(rawA_exp, 8, 7)
node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3))
wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6)
node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T)
connect rawA.isNaN, _rawA_out_isNaN_T_1
node _rawA_out_isInf_T = bits(rawA_exp, 6, 6)
node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0))
node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1)
connect rawA.isInf, _rawA_out_isInf_T_2
connect rawA.isZero, rawA_isZero
node _rawA_out_sign_T = bits(io.a, 32, 32)
connect rawA.sign, _rawA_out_sign_T
node _rawA_out_sExp_T = cvt(rawA_exp)
connect rawA.sExp, _rawA_out_sExp_T
node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0))
node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T)
node _rawA_out_sig_T_2 = bits(io.a, 22, 0)
node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2)
connect rawA.sig, _rawA_out_sig_T_3
node rawB_exp = bits(io.b, 31, 23)
node _rawB_isZero_T = bits(rawB_exp, 8, 6)
node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0))
node _rawB_isSpecial_T = bits(rawB_exp, 8, 7)
node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3))
wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6)
node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T)
connect rawB.isNaN, _rawB_out_isNaN_T_1
node _rawB_out_isInf_T = bits(rawB_exp, 6, 6)
node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0))
node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1)
connect rawB.isInf, _rawB_out_isInf_T_2
connect rawB.isZero, rawB_isZero
node _rawB_out_sign_T = bits(io.b, 32, 32)
connect rawB.sign, _rawB_out_sign_T
node _rawB_out_sExp_T = cvt(rawB_exp)
connect rawB.sExp, _rawB_out_sExp_T
node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0))
node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T)
node _rawB_out_sig_T_2 = bits(io.b, 22, 0)
node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2)
connect rawB.sig, _rawB_out_sig_T_3
node _ordered_T = eq(rawA.isNaN, UInt<1>(0h0))
node _ordered_T_1 = eq(rawB.isNaN, UInt<1>(0h0))
node ordered = and(_ordered_T, _ordered_T_1)
node bothInfs = and(rawA.isInf, rawB.isInf)
node bothZeros = and(rawA.isZero, rawB.isZero)
node eqExps = eq(rawA.sExp, rawB.sExp)
node _common_ltMags_T = lt(rawA.sExp, rawB.sExp)
node _common_ltMags_T_1 = lt(rawA.sig, rawB.sig)
node _common_ltMags_T_2 = and(eqExps, _common_ltMags_T_1)
node common_ltMags = or(_common_ltMags_T, _common_ltMags_T_2)
node _common_eqMags_T = eq(rawA.sig, rawB.sig)
node common_eqMags = and(eqExps, _common_eqMags_T)
node _ordered_lt_T = eq(bothZeros, UInt<1>(0h0))
node _ordered_lt_T_1 = eq(rawB.sign, UInt<1>(0h0))
node _ordered_lt_T_2 = and(rawA.sign, _ordered_lt_T_1)
node _ordered_lt_T_3 = eq(bothInfs, UInt<1>(0h0))
node _ordered_lt_T_4 = eq(common_ltMags, UInt<1>(0h0))
node _ordered_lt_T_5 = and(rawA.sign, _ordered_lt_T_4)
node _ordered_lt_T_6 = eq(common_eqMags, UInt<1>(0h0))
node _ordered_lt_T_7 = and(_ordered_lt_T_5, _ordered_lt_T_6)
node _ordered_lt_T_8 = eq(rawB.sign, UInt<1>(0h0))
node _ordered_lt_T_9 = and(_ordered_lt_T_8, common_ltMags)
node _ordered_lt_T_10 = or(_ordered_lt_T_7, _ordered_lt_T_9)
node _ordered_lt_T_11 = and(_ordered_lt_T_3, _ordered_lt_T_10)
node _ordered_lt_T_12 = or(_ordered_lt_T_2, _ordered_lt_T_11)
node ordered_lt = and(_ordered_lt_T, _ordered_lt_T_12)
node _ordered_eq_T = eq(rawA.sign, rawB.sign)
node _ordered_eq_T_1 = or(bothInfs, common_eqMags)
node _ordered_eq_T_2 = and(_ordered_eq_T, _ordered_eq_T_1)
node ordered_eq = or(bothZeros, _ordered_eq_T_2)
node _invalid_T = bits(rawA.sig, 22, 22)
node _invalid_T_1 = eq(_invalid_T, UInt<1>(0h0))
node _invalid_T_2 = and(rawA.isNaN, _invalid_T_1)
node _invalid_T_3 = bits(rawB.sig, 22, 22)
node _invalid_T_4 = eq(_invalid_T_3, UInt<1>(0h0))
node _invalid_T_5 = and(rawB.isNaN, _invalid_T_4)
node _invalid_T_6 = or(_invalid_T_2, _invalid_T_5)
node _invalid_T_7 = eq(ordered, UInt<1>(0h0))
node _invalid_T_8 = and(io.signaling, _invalid_T_7)
node invalid = or(_invalid_T_6, _invalid_T_8)
node _io_lt_T = and(ordered, ordered_lt)
connect io.lt, _io_lt_T
node _io_eq_T = and(ordered, ordered_eq)
connect io.eq, _io_eq_T
node _io_gt_T = eq(ordered_lt, UInt<1>(0h0))
node _io_gt_T_1 = and(ordered, _io_gt_T)
node _io_gt_T_2 = eq(ordered_eq, UInt<1>(0h0))
node _io_gt_T_3 = and(_io_gt_T_1, _io_gt_T_2)
connect io.gt, _io_gt_T_3
node _io_exceptionFlags_T = cat(invalid, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T | module CompareRecFN_1( // @[CompareRecFN.scala:42:7]
input [32:0] io_a, // @[CompareRecFN.scala:44:16]
input [32:0] io_b, // @[CompareRecFN.scala:44:16]
output io_gt // @[CompareRecFN.scala:44:16]
);
wire [32:0] io_a_0 = io_a; // @[CompareRecFN.scala:42:7]
wire [32:0] io_b_0 = io_b; // @[CompareRecFN.scala:42:7]
wire io_signaling = 1'h0; // @[CompareRecFN.scala:42:7]
wire _invalid_T_8 = 1'h0; // @[CompareRecFN.scala:76:27]
wire _io_lt_T; // @[CompareRecFN.scala:78:22]
wire _io_eq_T; // @[CompareRecFN.scala:79:22]
wire _io_gt_T_3; // @[CompareRecFN.scala:80:38]
wire [4:0] _io_exceptionFlags_T; // @[CompareRecFN.scala:81:34]
wire io_lt; // @[CompareRecFN.scala:42:7]
wire io_eq; // @[CompareRecFN.scala:42:7]
wire io_gt_0; // @[CompareRecFN.scala:42:7]
wire [4:0] io_exceptionFlags; // @[CompareRecFN.scala:42:7]
wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawA_isZero_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawB_isZero = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawB_isZero_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawB_out_sig_T = ~rawB_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _ordered_T = ~rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire _ordered_T_1 = ~rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire ordered = _ordered_T & _ordered_T_1; // @[CompareRecFN.scala:57:{19,32,35}]
wire bothInfs = rawA_isInf & rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire bothZeros = rawA_isZero_0 & rawB_isZero_0; // @[rawFloatFromRecFN.scala:55:23]
wire eqExps = rawA_sExp == rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire _common_ltMags_T = $signed(rawA_sExp) < $signed(rawB_sExp); // @[rawFloatFromRecFN.scala:55:23]
wire _common_ltMags_T_1 = rawA_sig < rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _common_ltMags_T_2 = eqExps & _common_ltMags_T_1; // @[CompareRecFN.scala:60:29, :62:{44,57}]
wire common_ltMags = _common_ltMags_T | _common_ltMags_T_2; // @[CompareRecFN.scala:62:{20,33,44}]
wire _common_eqMags_T = rawA_sig == rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire common_eqMags = eqExps & _common_eqMags_T; // @[CompareRecFN.scala:60:29, :63:{32,45}]
wire _ordered_lt_T = ~bothZeros; // @[CompareRecFN.scala:59:33, :66:9]
wire _ordered_lt_T_1 = ~rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _ordered_lt_T_2 = rawA_sign & _ordered_lt_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _ordered_lt_T_3 = ~bothInfs; // @[CompareRecFN.scala:58:33, :68:19]
wire _ordered_lt_T_4 = ~common_ltMags; // @[CompareRecFN.scala:62:33, :69:38]
wire _ordered_lt_T_5 = rawA_sign & _ordered_lt_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _ordered_lt_T_6 = ~common_eqMags; // @[CompareRecFN.scala:63:32, :69:57]
wire _ordered_lt_T_7 = _ordered_lt_T_5 & _ordered_lt_T_6; // @[CompareRecFN.scala:69:{35,54,57}]
wire _ordered_lt_T_8 = ~rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _ordered_lt_T_9 = _ordered_lt_T_8 & common_ltMags; // @[CompareRecFN.scala:62:33, :70:{29,41}]
wire _ordered_lt_T_10 = _ordered_lt_T_7 | _ordered_lt_T_9; // @[CompareRecFN.scala:69:{54,74}, :70:41]
wire _ordered_lt_T_11 = _ordered_lt_T_3 & _ordered_lt_T_10; // @[CompareRecFN.scala:68:{19,30}, :69:74]
wire _ordered_lt_T_12 = _ordered_lt_T_2 | _ordered_lt_T_11; // @[CompareRecFN.scala:67:{25,41}, :68:30]
wire ordered_lt = _ordered_lt_T & _ordered_lt_T_12; // @[CompareRecFN.scala:66:{9,21}, :67:41]
wire _ordered_eq_T = rawA_sign == rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _ordered_eq_T_1 = bothInfs | common_eqMags; // @[CompareRecFN.scala:58:33, :63:32, :72:62]
wire _ordered_eq_T_2 = _ordered_eq_T & _ordered_eq_T_1; // @[CompareRecFN.scala:72:{34,49,62}]
wire ordered_eq = bothZeros | _ordered_eq_T_2; // @[CompareRecFN.scala:59:33, :72:{19,49}]
wire _invalid_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _invalid_T_1 = ~_invalid_T; // @[common.scala:82:{49,56}]
wire _invalid_T_2 = rawA_isNaN & _invalid_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _invalid_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _invalid_T_4 = ~_invalid_T_3; // @[common.scala:82:{49,56}]
wire _invalid_T_5 = rawB_isNaN & _invalid_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _invalid_T_6 = _invalid_T_2 | _invalid_T_5; // @[common.scala:82:46]
wire invalid = _invalid_T_6; // @[CompareRecFN.scala:75:{32,58}]
wire _invalid_T_7 = ~ordered; // @[CompareRecFN.scala:57:32, :76:30]
assign _io_lt_T = ordered & ordered_lt; // @[CompareRecFN.scala:57:32, :66:21, :78:22]
assign io_lt = _io_lt_T; // @[CompareRecFN.scala:42:7, :78:22]
assign _io_eq_T = ordered & ordered_eq; // @[CompareRecFN.scala:57:32, :72:19, :79:22]
assign io_eq = _io_eq_T; // @[CompareRecFN.scala:42:7, :79:22]
wire _io_gt_T = ~ordered_lt; // @[CompareRecFN.scala:66:21, :80:25]
wire _io_gt_T_1 = ordered & _io_gt_T; // @[CompareRecFN.scala:57:32, :80:{22,25}]
wire _io_gt_T_2 = ~ordered_eq; // @[CompareRecFN.scala:72:19, :80:41]
assign _io_gt_T_3 = _io_gt_T_1 & _io_gt_T_2; // @[CompareRecFN.scala:80:{22,38,41}]
assign io_gt_0 = _io_gt_T_3; // @[CompareRecFN.scala:42:7, :80:38]
assign _io_exceptionFlags_T = {invalid, 4'h0}; // @[CompareRecFN.scala:75:58, :81:34]
assign io_exceptionFlags = _io_exceptionFlags_T; // @[CompareRecFN.scala:42:7, :81:34]
assign io_gt = io_gt_0; // @[CompareRecFN.scala:42:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PhitToFlit_p32_f32_2 :
input clock : Clock
input reset : Reset
output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}}
reg data : UInt<32>[0], clock
regreset beat : UInt<0>, clock, reset, UInt<0>(0h0)
node _io_in_ready_T = neq(beat, UInt<1>(0h0))
node _io_in_ready_T_1 = or(io.out.ready, _io_in_ready_T)
connect io.in.ready, _io_in_ready_T_1
node _io_out_valid_T = eq(beat, UInt<1>(0h0))
node _io_out_valid_T_1 = and(io.in.valid, _io_out_valid_T)
connect io.out.valid, _io_out_valid_T_1
connect io.out.bits.flit, io.in.bits.phit
node _T = and(io.in.ready, io.in.valid)
when _T :
node _beat_T = eq(beat, UInt<1>(0h0))
node _beat_T_1 = add(beat, UInt<1>(0h1))
node _beat_T_2 = tail(_beat_T_1, 1)
node _beat_T_3 = mux(_beat_T, UInt<1>(0h0), _beat_T_2)
connect beat, _beat_T_3 | module PhitToFlit_p32_f32_2( // @[Serdes.scala:103:7]
input clock, // @[Serdes.scala:103:7]
input reset, // @[Serdes.scala:103:7]
output io_in_ready, // @[Serdes.scala:105:14]
input io_in_valid, // @[Serdes.scala:105:14]
input [31:0] io_in_bits_phit, // @[Serdes.scala:105:14]
input io_out_ready, // @[Serdes.scala:105:14]
output io_out_valid, // @[Serdes.scala:105:14]
output [31:0] io_out_bits_flit // @[Serdes.scala:105:14]
);
wire io_in_valid_0 = io_in_valid; // @[Serdes.scala:103:7]
wire [31:0] io_in_bits_phit_0 = io_in_bits_phit; // @[Serdes.scala:103:7]
wire io_out_ready_0 = io_out_ready; // @[Serdes.scala:103:7]
wire [1:0] _beat_T_1 = 2'h1; // @[Serdes.scala:120:53]
wire _io_out_valid_T = 1'h1; // @[Serdes.scala:116:39]
wire _beat_T = 1'h1; // @[Serdes.scala:120:22]
wire _beat_T_2 = 1'h1; // @[Serdes.scala:120:53]
wire _io_in_ready_T = 1'h0; // @[Serdes.scala:115:39]
wire _io_in_ready_T_1; // @[Serdes.scala:115:31]
wire _beat_T_3 = 1'h0; // @[Serdes.scala:120:16]
wire _io_out_valid_T_1 = io_in_valid_0; // @[Serdes.scala:103:7, :116:31]
wire [31:0] io_out_bits_flit_0 = io_in_bits_phit_0; // @[Serdes.scala:103:7]
assign _io_in_ready_T_1 = io_out_ready_0; // @[Serdes.scala:103:7, :115:31]
wire io_in_ready_0; // @[Serdes.scala:103:7]
wire io_out_valid_0; // @[Serdes.scala:103:7]
assign io_in_ready_0 = _io_in_ready_T_1; // @[Serdes.scala:103:7, :115:31]
assign io_out_valid_0 = _io_out_valid_T_1; // @[Serdes.scala:103:7, :116:31]
assign io_in_ready = io_in_ready_0; // @[Serdes.scala:103:7]
assign io_out_valid = io_out_valid_0; // @[Serdes.scala:103:7]
assign io_out_bits_flit = io_out_bits_flit_0; // @[Serdes.scala:103:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_20 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<8>(0h90))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<6>(0h20))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<6>(0h21))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<6>(0h22))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<6>(0h23))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 5, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 6)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<1>(0h1))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<6>(0h3f))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 5, 0)
node _source_ok_T_31 = shr(io.in.a.bits.source, 6)
node _source_ok_T_32 = eq(_source_ok_T_31, UInt<1>(0h0))
node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<6>(0h3f))
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<9>(0h100))
wire _source_ok_WIRE : UInt<1>[11]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_36
connect _source_ok_WIRE[7], _source_ok_T_37
connect _source_ok_WIRE[8], _source_ok_T_38
connect _source_ok_WIRE[9], _source_ok_T_39
connect _source_ok_WIRE[10], _source_ok_T_40
node _source_ok_T_41 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[2])
node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[3])
node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[4])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[5])
node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[6])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[7])
node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[8])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[9])
node source_ok = or(_source_ok_T_49, _source_ok_WIRE[10])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<6>(0h20))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<6>(0h21))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<6>(0h22))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<6>(0h23))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 5, 0)
node _T_64 = shr(io.in.a.bits.source, 6)
node _T_65 = eq(_T_64, UInt<1>(0h1))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<6>(0h3f))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 5, 0)
node _T_77 = shr(io.in.a.bits.source, 6)
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_80 = and(_T_78, _T_79)
node _T_81 = leq(uncommonBits_5, UInt<6>(0h3f))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(_T_82, UInt<1>(0h0))
node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = or(_T_83, _T_88)
node _T_90 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_91 = eq(_T_90, UInt<1>(0h0))
node _T_92 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_93 = cvt(_T_92)
node _T_94 = and(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = asSInt(_T_94)
node _T_96 = eq(_T_95, asSInt(UInt<1>(0h0)))
node _T_97 = or(_T_91, _T_96)
node _T_98 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = or(_T_99, _T_104)
node _T_106 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_107 = eq(_T_106, UInt<1>(0h0))
node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_109 = cvt(_T_108)
node _T_110 = and(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = asSInt(_T_110)
node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0)))
node _T_113 = or(_T_107, _T_112)
node _T_114 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_115 = eq(_T_114, UInt<1>(0h0))
node _T_116 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_117 = cvt(_T_116)
node _T_118 = and(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = asSInt(_T_118)
node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0)))
node _T_121 = or(_T_115, _T_120)
node _T_122 = and(_T_11, _T_24)
node _T_123 = and(_T_122, _T_37)
node _T_124 = and(_T_123, _T_50)
node _T_125 = and(_T_124, _T_63)
node _T_126 = and(_T_125, _T_76)
node _T_127 = and(_T_126, _T_89)
node _T_128 = and(_T_127, _T_97)
node _T_129 = and(_T_128, _T_105)
node _T_130 = and(_T_129, _T_113)
node _T_131 = and(_T_130, _T_121)
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_131, UInt<1>(0h1), "") : assert_1
node _T_135 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_135 :
node _T_136 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_137 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_138 = and(_T_136, _T_137)
node _T_139 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_140 = shr(io.in.a.bits.source, 2)
node _T_141 = eq(_T_140, UInt<6>(0h20))
node _T_142 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_143 = and(_T_141, _T_142)
node _T_144 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_145 = and(_T_143, _T_144)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_146 = shr(io.in.a.bits.source, 2)
node _T_147 = eq(_T_146, UInt<6>(0h21))
node _T_148 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_149 = and(_T_147, _T_148)
node _T_150 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_152 = shr(io.in.a.bits.source, 2)
node _T_153 = eq(_T_152, UInt<6>(0h22))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_157 = and(_T_155, _T_156)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_158 = shr(io.in.a.bits.source, 2)
node _T_159 = eq(_T_158, UInt<6>(0h23))
node _T_160 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_161 = and(_T_159, _T_160)
node _T_162 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_163 = and(_T_161, _T_162)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 5, 0)
node _T_164 = shr(io.in.a.bits.source, 6)
node _T_165 = eq(_T_164, UInt<1>(0h1))
node _T_166 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_167 = and(_T_165, _T_166)
node _T_168 = leq(uncommonBits_10, UInt<6>(0h3f))
node _T_169 = and(_T_167, _T_168)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 5, 0)
node _T_170 = shr(io.in.a.bits.source, 6)
node _T_171 = eq(_T_170, UInt<1>(0h0))
node _T_172 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_173 = and(_T_171, _T_172)
node _T_174 = leq(uncommonBits_11, UInt<6>(0h3f))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_177 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_178 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_179 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_180 = or(_T_139, _T_145)
node _T_181 = or(_T_180, _T_151)
node _T_182 = or(_T_181, _T_157)
node _T_183 = or(_T_182, _T_163)
node _T_184 = or(_T_183, _T_169)
node _T_185 = or(_T_184, _T_175)
node _T_186 = or(_T_185, _T_176)
node _T_187 = or(_T_186, _T_177)
node _T_188 = or(_T_187, _T_178)
node _T_189 = or(_T_188, _T_179)
node _T_190 = and(_T_138, _T_189)
node _T_191 = or(UInt<1>(0h0), _T_190)
node _T_192 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_193 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_194 = cvt(_T_193)
node _T_195 = and(_T_194, asSInt(UInt<14>(0h2000)))
node _T_196 = asSInt(_T_195)
node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0)))
node _T_198 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_199 = cvt(_T_198)
node _T_200 = and(_T_199, asSInt(UInt<13>(0h1000)))
node _T_201 = asSInt(_T_200)
node _T_202 = eq(_T_201, asSInt(UInt<1>(0h0)))
node _T_203 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_204 = cvt(_T_203)
node _T_205 = and(_T_204, asSInt(UInt<17>(0h10000)))
node _T_206 = asSInt(_T_205)
node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0)))
node _T_208 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_209 = cvt(_T_208)
node _T_210 = and(_T_209, asSInt(UInt<18>(0h2f000)))
node _T_211 = asSInt(_T_210)
node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0)))
node _T_213 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_214 = cvt(_T_213)
node _T_215 = and(_T_214, asSInt(UInt<17>(0h10000)))
node _T_216 = asSInt(_T_215)
node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0)))
node _T_218 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_219 = cvt(_T_218)
node _T_220 = and(_T_219, asSInt(UInt<13>(0h1000)))
node _T_221 = asSInt(_T_220)
node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0)))
node _T_223 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_224 = cvt(_T_223)
node _T_225 = and(_T_224, asSInt(UInt<27>(0h4000000)))
node _T_226 = asSInt(_T_225)
node _T_227 = eq(_T_226, asSInt(UInt<1>(0h0)))
node _T_228 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_229 = cvt(_T_228)
node _T_230 = and(_T_229, asSInt(UInt<13>(0h1000)))
node _T_231 = asSInt(_T_230)
node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0)))
node _T_233 = or(_T_197, _T_202)
node _T_234 = or(_T_233, _T_207)
node _T_235 = or(_T_234, _T_212)
node _T_236 = or(_T_235, _T_217)
node _T_237 = or(_T_236, _T_222)
node _T_238 = or(_T_237, _T_227)
node _T_239 = or(_T_238, _T_232)
node _T_240 = and(_T_192, _T_239)
node _T_241 = or(UInt<1>(0h0), _T_240)
node _T_242 = and(_T_191, _T_241)
node _T_243 = asUInt(reset)
node _T_244 = eq(_T_243, UInt<1>(0h0))
when _T_244 :
node _T_245 = eq(_T_242, UInt<1>(0h0))
when _T_245 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_242, UInt<1>(0h1), "") : assert_2
node _T_246 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_247 = shr(io.in.a.bits.source, 2)
node _T_248 = eq(_T_247, UInt<6>(0h20))
node _T_249 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_250 = and(_T_248, _T_249)
node _T_251 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_252 = and(_T_250, _T_251)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_253 = shr(io.in.a.bits.source, 2)
node _T_254 = eq(_T_253, UInt<6>(0h21))
node _T_255 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_256 = and(_T_254, _T_255)
node _T_257 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_258 = and(_T_256, _T_257)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_259 = shr(io.in.a.bits.source, 2)
node _T_260 = eq(_T_259, UInt<6>(0h22))
node _T_261 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_262 = and(_T_260, _T_261)
node _T_263 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_264 = and(_T_262, _T_263)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_265 = shr(io.in.a.bits.source, 2)
node _T_266 = eq(_T_265, UInt<6>(0h23))
node _T_267 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_268 = and(_T_266, _T_267)
node _T_269 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_270 = and(_T_268, _T_269)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 5, 0)
node _T_271 = shr(io.in.a.bits.source, 6)
node _T_272 = eq(_T_271, UInt<1>(0h1))
node _T_273 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_274 = and(_T_272, _T_273)
node _T_275 = leq(uncommonBits_16, UInt<6>(0h3f))
node _T_276 = and(_T_274, _T_275)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 5, 0)
node _T_277 = shr(io.in.a.bits.source, 6)
node _T_278 = eq(_T_277, UInt<1>(0h0))
node _T_279 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_280 = and(_T_278, _T_279)
node _T_281 = leq(uncommonBits_17, UInt<6>(0h3f))
node _T_282 = and(_T_280, _T_281)
node _T_283 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_284 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_285 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_286 = eq(io.in.a.bits.source, UInt<9>(0h100))
wire _WIRE : UInt<1>[11]
connect _WIRE[0], _T_246
connect _WIRE[1], _T_252
connect _WIRE[2], _T_258
connect _WIRE[3], _T_264
connect _WIRE[4], _T_270
connect _WIRE[5], _T_276
connect _WIRE[6], _T_282
connect _WIRE[7], _T_283
connect _WIRE[8], _T_284
connect _WIRE[9], _T_285
connect _WIRE[10], _T_286
node _T_287 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_288 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_289 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_290 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_291 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_293 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_294 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_295 = mux(_WIRE[7], _T_287, UInt<1>(0h0))
node _T_296 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_297 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_298 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_299 = or(_T_288, _T_289)
node _T_300 = or(_T_299, _T_290)
node _T_301 = or(_T_300, _T_291)
node _T_302 = or(_T_301, _T_292)
node _T_303 = or(_T_302, _T_293)
node _T_304 = or(_T_303, _T_294)
node _T_305 = or(_T_304, _T_295)
node _T_306 = or(_T_305, _T_296)
node _T_307 = or(_T_306, _T_297)
node _T_308 = or(_T_307, _T_298)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_308
node _T_309 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_310 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_311 = and(_T_309, _T_310)
node _T_312 = or(UInt<1>(0h0), _T_311)
node _T_313 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_314 = cvt(_T_313)
node _T_315 = and(_T_314, asSInt(UInt<14>(0h2000)))
node _T_316 = asSInt(_T_315)
node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0)))
node _T_318 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_319 = cvt(_T_318)
node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000)))
node _T_321 = asSInt(_T_320)
node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0)))
node _T_323 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_324 = cvt(_T_323)
node _T_325 = and(_T_324, asSInt(UInt<17>(0h10000)))
node _T_326 = asSInt(_T_325)
node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0)))
node _T_328 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_329 = cvt(_T_328)
node _T_330 = and(_T_329, asSInt(UInt<18>(0h2f000)))
node _T_331 = asSInt(_T_330)
node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0)))
node _T_333 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_334 = cvt(_T_333)
node _T_335 = and(_T_334, asSInt(UInt<17>(0h10000)))
node _T_336 = asSInt(_T_335)
node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0)))
node _T_338 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_339 = cvt(_T_338)
node _T_340 = and(_T_339, asSInt(UInt<13>(0h1000)))
node _T_341 = asSInt(_T_340)
node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0)))
node _T_343 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_344 = cvt(_T_343)
node _T_345 = and(_T_344, asSInt(UInt<27>(0h4000000)))
node _T_346 = asSInt(_T_345)
node _T_347 = eq(_T_346, asSInt(UInt<1>(0h0)))
node _T_348 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_349 = cvt(_T_348)
node _T_350 = and(_T_349, asSInt(UInt<13>(0h1000)))
node _T_351 = asSInt(_T_350)
node _T_352 = eq(_T_351, asSInt(UInt<1>(0h0)))
node _T_353 = or(_T_317, _T_322)
node _T_354 = or(_T_353, _T_327)
node _T_355 = or(_T_354, _T_332)
node _T_356 = or(_T_355, _T_337)
node _T_357 = or(_T_356, _T_342)
node _T_358 = or(_T_357, _T_347)
node _T_359 = or(_T_358, _T_352)
node _T_360 = and(_T_312, _T_359)
node _T_361 = or(UInt<1>(0h0), _T_360)
node _T_362 = and(_WIRE_1, _T_361)
node _T_363 = asUInt(reset)
node _T_364 = eq(_T_363, UInt<1>(0h0))
when _T_364 :
node _T_365 = eq(_T_362, UInt<1>(0h0))
when _T_365 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_362, UInt<1>(0h1), "") : assert_3
node _T_366 = asUInt(reset)
node _T_367 = eq(_T_366, UInt<1>(0h0))
when _T_367 :
node _T_368 = eq(source_ok, UInt<1>(0h0))
when _T_368 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_369 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(_T_369, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_369, UInt<1>(0h1), "") : assert_5
node _T_373 = asUInt(reset)
node _T_374 = eq(_T_373, UInt<1>(0h0))
when _T_374 :
node _T_375 = eq(is_aligned, UInt<1>(0h0))
when _T_375 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_376 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_377 = asUInt(reset)
node _T_378 = eq(_T_377, UInt<1>(0h0))
when _T_378 :
node _T_379 = eq(_T_376, UInt<1>(0h0))
when _T_379 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_376, UInt<1>(0h1), "") : assert_7
node _T_380 = not(io.in.a.bits.mask)
node _T_381 = eq(_T_380, UInt<1>(0h0))
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(_T_381, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_381, UInt<1>(0h1), "") : assert_8
node _T_385 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_385, UInt<1>(0h1), "") : assert_9
node _T_389 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_389 :
node _T_390 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_391 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_392 = and(_T_390, _T_391)
node _T_393 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_394 = shr(io.in.a.bits.source, 2)
node _T_395 = eq(_T_394, UInt<6>(0h20))
node _T_396 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_397 = and(_T_395, _T_396)
node _T_398 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_399 = and(_T_397, _T_398)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_400 = shr(io.in.a.bits.source, 2)
node _T_401 = eq(_T_400, UInt<6>(0h21))
node _T_402 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_403 = and(_T_401, _T_402)
node _T_404 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_405 = and(_T_403, _T_404)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_406 = shr(io.in.a.bits.source, 2)
node _T_407 = eq(_T_406, UInt<6>(0h22))
node _T_408 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_409 = and(_T_407, _T_408)
node _T_410 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_411 = and(_T_409, _T_410)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_412 = shr(io.in.a.bits.source, 2)
node _T_413 = eq(_T_412, UInt<6>(0h23))
node _T_414 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_415 = and(_T_413, _T_414)
node _T_416 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_417 = and(_T_415, _T_416)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 5, 0)
node _T_418 = shr(io.in.a.bits.source, 6)
node _T_419 = eq(_T_418, UInt<1>(0h1))
node _T_420 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_421 = and(_T_419, _T_420)
node _T_422 = leq(uncommonBits_22, UInt<6>(0h3f))
node _T_423 = and(_T_421, _T_422)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 5, 0)
node _T_424 = shr(io.in.a.bits.source, 6)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_427 = and(_T_425, _T_426)
node _T_428 = leq(uncommonBits_23, UInt<6>(0h3f))
node _T_429 = and(_T_427, _T_428)
node _T_430 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_431 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_432 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_433 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_434 = or(_T_393, _T_399)
node _T_435 = or(_T_434, _T_405)
node _T_436 = or(_T_435, _T_411)
node _T_437 = or(_T_436, _T_417)
node _T_438 = or(_T_437, _T_423)
node _T_439 = or(_T_438, _T_429)
node _T_440 = or(_T_439, _T_430)
node _T_441 = or(_T_440, _T_431)
node _T_442 = or(_T_441, _T_432)
node _T_443 = or(_T_442, _T_433)
node _T_444 = and(_T_392, _T_443)
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_447 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_448 = cvt(_T_447)
node _T_449 = and(_T_448, asSInt(UInt<14>(0h2000)))
node _T_450 = asSInt(_T_449)
node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0)))
node _T_452 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_453 = cvt(_T_452)
node _T_454 = and(_T_453, asSInt(UInt<13>(0h1000)))
node _T_455 = asSInt(_T_454)
node _T_456 = eq(_T_455, asSInt(UInt<1>(0h0)))
node _T_457 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_458 = cvt(_T_457)
node _T_459 = and(_T_458, asSInt(UInt<17>(0h10000)))
node _T_460 = asSInt(_T_459)
node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0)))
node _T_462 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_463 = cvt(_T_462)
node _T_464 = and(_T_463, asSInt(UInt<18>(0h2f000)))
node _T_465 = asSInt(_T_464)
node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0)))
node _T_467 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_468 = cvt(_T_467)
node _T_469 = and(_T_468, asSInt(UInt<17>(0h10000)))
node _T_470 = asSInt(_T_469)
node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0)))
node _T_472 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_473 = cvt(_T_472)
node _T_474 = and(_T_473, asSInt(UInt<13>(0h1000)))
node _T_475 = asSInt(_T_474)
node _T_476 = eq(_T_475, asSInt(UInt<1>(0h0)))
node _T_477 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_478 = cvt(_T_477)
node _T_479 = and(_T_478, asSInt(UInt<27>(0h4000000)))
node _T_480 = asSInt(_T_479)
node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0)))
node _T_482 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_483 = cvt(_T_482)
node _T_484 = and(_T_483, asSInt(UInt<13>(0h1000)))
node _T_485 = asSInt(_T_484)
node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0)))
node _T_487 = or(_T_451, _T_456)
node _T_488 = or(_T_487, _T_461)
node _T_489 = or(_T_488, _T_466)
node _T_490 = or(_T_489, _T_471)
node _T_491 = or(_T_490, _T_476)
node _T_492 = or(_T_491, _T_481)
node _T_493 = or(_T_492, _T_486)
node _T_494 = and(_T_446, _T_493)
node _T_495 = or(UInt<1>(0h0), _T_494)
node _T_496 = and(_T_445, _T_495)
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(_T_496, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_496, UInt<1>(0h1), "") : assert_10
node _T_500 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_501 = shr(io.in.a.bits.source, 2)
node _T_502 = eq(_T_501, UInt<6>(0h20))
node _T_503 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_504 = and(_T_502, _T_503)
node _T_505 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_506 = and(_T_504, _T_505)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_507 = shr(io.in.a.bits.source, 2)
node _T_508 = eq(_T_507, UInt<6>(0h21))
node _T_509 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_510 = and(_T_508, _T_509)
node _T_511 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_512 = and(_T_510, _T_511)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_513 = shr(io.in.a.bits.source, 2)
node _T_514 = eq(_T_513, UInt<6>(0h22))
node _T_515 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_516 = and(_T_514, _T_515)
node _T_517 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_518 = and(_T_516, _T_517)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_519 = shr(io.in.a.bits.source, 2)
node _T_520 = eq(_T_519, UInt<6>(0h23))
node _T_521 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_522 = and(_T_520, _T_521)
node _T_523 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_524 = and(_T_522, _T_523)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 5, 0)
node _T_525 = shr(io.in.a.bits.source, 6)
node _T_526 = eq(_T_525, UInt<1>(0h1))
node _T_527 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_528 = and(_T_526, _T_527)
node _T_529 = leq(uncommonBits_28, UInt<6>(0h3f))
node _T_530 = and(_T_528, _T_529)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 5, 0)
node _T_531 = shr(io.in.a.bits.source, 6)
node _T_532 = eq(_T_531, UInt<1>(0h0))
node _T_533 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_534 = and(_T_532, _T_533)
node _T_535 = leq(uncommonBits_29, UInt<6>(0h3f))
node _T_536 = and(_T_534, _T_535)
node _T_537 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_538 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_539 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_540 = eq(io.in.a.bits.source, UInt<9>(0h100))
wire _WIRE_2 : UInt<1>[11]
connect _WIRE_2[0], _T_500
connect _WIRE_2[1], _T_506
connect _WIRE_2[2], _T_512
connect _WIRE_2[3], _T_518
connect _WIRE_2[4], _T_524
connect _WIRE_2[5], _T_530
connect _WIRE_2[6], _T_536
connect _WIRE_2[7], _T_537
connect _WIRE_2[8], _T_538
connect _WIRE_2[9], _T_539
connect _WIRE_2[10], _T_540
node _T_541 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_542 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_543 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_544 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_545 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_546 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_547 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_548 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_549 = mux(_WIRE_2[7], _T_541, UInt<1>(0h0))
node _T_550 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_551 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_552 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_553 = or(_T_542, _T_543)
node _T_554 = or(_T_553, _T_544)
node _T_555 = or(_T_554, _T_545)
node _T_556 = or(_T_555, _T_546)
node _T_557 = or(_T_556, _T_547)
node _T_558 = or(_T_557, _T_548)
node _T_559 = or(_T_558, _T_549)
node _T_560 = or(_T_559, _T_550)
node _T_561 = or(_T_560, _T_551)
node _T_562 = or(_T_561, _T_552)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_562
node _T_563 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_564 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_565 = and(_T_563, _T_564)
node _T_566 = or(UInt<1>(0h0), _T_565)
node _T_567 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_568 = cvt(_T_567)
node _T_569 = and(_T_568, asSInt(UInt<14>(0h2000)))
node _T_570 = asSInt(_T_569)
node _T_571 = eq(_T_570, asSInt(UInt<1>(0h0)))
node _T_572 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_573 = cvt(_T_572)
node _T_574 = and(_T_573, asSInt(UInt<13>(0h1000)))
node _T_575 = asSInt(_T_574)
node _T_576 = eq(_T_575, asSInt(UInt<1>(0h0)))
node _T_577 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_578 = cvt(_T_577)
node _T_579 = and(_T_578, asSInt(UInt<17>(0h10000)))
node _T_580 = asSInt(_T_579)
node _T_581 = eq(_T_580, asSInt(UInt<1>(0h0)))
node _T_582 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_583 = cvt(_T_582)
node _T_584 = and(_T_583, asSInt(UInt<18>(0h2f000)))
node _T_585 = asSInt(_T_584)
node _T_586 = eq(_T_585, asSInt(UInt<1>(0h0)))
node _T_587 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_588 = cvt(_T_587)
node _T_589 = and(_T_588, asSInt(UInt<17>(0h10000)))
node _T_590 = asSInt(_T_589)
node _T_591 = eq(_T_590, asSInt(UInt<1>(0h0)))
node _T_592 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_593 = cvt(_T_592)
node _T_594 = and(_T_593, asSInt(UInt<13>(0h1000)))
node _T_595 = asSInt(_T_594)
node _T_596 = eq(_T_595, asSInt(UInt<1>(0h0)))
node _T_597 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_598 = cvt(_T_597)
node _T_599 = and(_T_598, asSInt(UInt<27>(0h4000000)))
node _T_600 = asSInt(_T_599)
node _T_601 = eq(_T_600, asSInt(UInt<1>(0h0)))
node _T_602 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_603 = cvt(_T_602)
node _T_604 = and(_T_603, asSInt(UInt<13>(0h1000)))
node _T_605 = asSInt(_T_604)
node _T_606 = eq(_T_605, asSInt(UInt<1>(0h0)))
node _T_607 = or(_T_571, _T_576)
node _T_608 = or(_T_607, _T_581)
node _T_609 = or(_T_608, _T_586)
node _T_610 = or(_T_609, _T_591)
node _T_611 = or(_T_610, _T_596)
node _T_612 = or(_T_611, _T_601)
node _T_613 = or(_T_612, _T_606)
node _T_614 = and(_T_566, _T_613)
node _T_615 = or(UInt<1>(0h0), _T_614)
node _T_616 = and(_WIRE_3, _T_615)
node _T_617 = asUInt(reset)
node _T_618 = eq(_T_617, UInt<1>(0h0))
when _T_618 :
node _T_619 = eq(_T_616, UInt<1>(0h0))
when _T_619 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_616, UInt<1>(0h1), "") : assert_11
node _T_620 = asUInt(reset)
node _T_621 = eq(_T_620, UInt<1>(0h0))
when _T_621 :
node _T_622 = eq(source_ok, UInt<1>(0h0))
when _T_622 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_623 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_624 = asUInt(reset)
node _T_625 = eq(_T_624, UInt<1>(0h0))
when _T_625 :
node _T_626 = eq(_T_623, UInt<1>(0h0))
when _T_626 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_623, UInt<1>(0h1), "") : assert_13
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(is_aligned, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_630 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_630, UInt<1>(0h1), "") : assert_15
node _T_634 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_T_634, UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_634, UInt<1>(0h1), "") : assert_16
node _T_638 = not(io.in.a.bits.mask)
node _T_639 = eq(_T_638, UInt<1>(0h0))
node _T_640 = asUInt(reset)
node _T_641 = eq(_T_640, UInt<1>(0h0))
when _T_641 :
node _T_642 = eq(_T_639, UInt<1>(0h0))
when _T_642 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_639, UInt<1>(0h1), "") : assert_17
node _T_643 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_644 = asUInt(reset)
node _T_645 = eq(_T_644, UInt<1>(0h0))
when _T_645 :
node _T_646 = eq(_T_643, UInt<1>(0h0))
when _T_646 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_643, UInt<1>(0h1), "") : assert_18
node _T_647 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_647 :
node _T_648 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_649 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_650 = and(_T_648, _T_649)
node _T_651 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_652 = shr(io.in.a.bits.source, 2)
node _T_653 = eq(_T_652, UInt<6>(0h20))
node _T_654 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_655 = and(_T_653, _T_654)
node _T_656 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_657 = and(_T_655, _T_656)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_658 = shr(io.in.a.bits.source, 2)
node _T_659 = eq(_T_658, UInt<6>(0h21))
node _T_660 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_661 = and(_T_659, _T_660)
node _T_662 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_663 = and(_T_661, _T_662)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_664 = shr(io.in.a.bits.source, 2)
node _T_665 = eq(_T_664, UInt<6>(0h22))
node _T_666 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_667 = and(_T_665, _T_666)
node _T_668 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_669 = and(_T_667, _T_668)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_670 = shr(io.in.a.bits.source, 2)
node _T_671 = eq(_T_670, UInt<6>(0h23))
node _T_672 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_673 = and(_T_671, _T_672)
node _T_674 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_675 = and(_T_673, _T_674)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 5, 0)
node _T_676 = shr(io.in.a.bits.source, 6)
node _T_677 = eq(_T_676, UInt<1>(0h1))
node _T_678 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_679 = and(_T_677, _T_678)
node _T_680 = leq(uncommonBits_34, UInt<6>(0h3f))
node _T_681 = and(_T_679, _T_680)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 5, 0)
node _T_682 = shr(io.in.a.bits.source, 6)
node _T_683 = eq(_T_682, UInt<1>(0h0))
node _T_684 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_685 = and(_T_683, _T_684)
node _T_686 = leq(uncommonBits_35, UInt<6>(0h3f))
node _T_687 = and(_T_685, _T_686)
node _T_688 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_689 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_690 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_691 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_692 = or(_T_651, _T_657)
node _T_693 = or(_T_692, _T_663)
node _T_694 = or(_T_693, _T_669)
node _T_695 = or(_T_694, _T_675)
node _T_696 = or(_T_695, _T_681)
node _T_697 = or(_T_696, _T_687)
node _T_698 = or(_T_697, _T_688)
node _T_699 = or(_T_698, _T_689)
node _T_700 = or(_T_699, _T_690)
node _T_701 = or(_T_700, _T_691)
node _T_702 = and(_T_650, _T_701)
node _T_703 = or(UInt<1>(0h0), _T_702)
node _T_704 = asUInt(reset)
node _T_705 = eq(_T_704, UInt<1>(0h0))
when _T_705 :
node _T_706 = eq(_T_703, UInt<1>(0h0))
when _T_706 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_703, UInt<1>(0h1), "") : assert_19
node _T_707 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_708 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_709 = and(_T_707, _T_708)
node _T_710 = or(UInt<1>(0h0), _T_709)
node _T_711 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_712 = cvt(_T_711)
node _T_713 = and(_T_712, asSInt(UInt<13>(0h1000)))
node _T_714 = asSInt(_T_713)
node _T_715 = eq(_T_714, asSInt(UInt<1>(0h0)))
node _T_716 = and(_T_710, _T_715)
node _T_717 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_718 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_719 = and(_T_717, _T_718)
node _T_720 = or(UInt<1>(0h0), _T_719)
node _T_721 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_722 = cvt(_T_721)
node _T_723 = and(_T_722, asSInt(UInt<14>(0h2000)))
node _T_724 = asSInt(_T_723)
node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0)))
node _T_726 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_727 = cvt(_T_726)
node _T_728 = and(_T_727, asSInt(UInt<17>(0h10000)))
node _T_729 = asSInt(_T_728)
node _T_730 = eq(_T_729, asSInt(UInt<1>(0h0)))
node _T_731 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_732 = cvt(_T_731)
node _T_733 = and(_T_732, asSInt(UInt<18>(0h2f000)))
node _T_734 = asSInt(_T_733)
node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0)))
node _T_736 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_737 = cvt(_T_736)
node _T_738 = and(_T_737, asSInt(UInt<17>(0h10000)))
node _T_739 = asSInt(_T_738)
node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0)))
node _T_741 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_742 = cvt(_T_741)
node _T_743 = and(_T_742, asSInt(UInt<13>(0h1000)))
node _T_744 = asSInt(_T_743)
node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0)))
node _T_746 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_747 = cvt(_T_746)
node _T_748 = and(_T_747, asSInt(UInt<27>(0h4000000)))
node _T_749 = asSInt(_T_748)
node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0)))
node _T_751 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_752 = cvt(_T_751)
node _T_753 = and(_T_752, asSInt(UInt<13>(0h1000)))
node _T_754 = asSInt(_T_753)
node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0)))
node _T_756 = or(_T_725, _T_730)
node _T_757 = or(_T_756, _T_735)
node _T_758 = or(_T_757, _T_740)
node _T_759 = or(_T_758, _T_745)
node _T_760 = or(_T_759, _T_750)
node _T_761 = or(_T_760, _T_755)
node _T_762 = and(_T_720, _T_761)
node _T_763 = or(UInt<1>(0h0), _T_716)
node _T_764 = or(_T_763, _T_762)
node _T_765 = asUInt(reset)
node _T_766 = eq(_T_765, UInt<1>(0h0))
when _T_766 :
node _T_767 = eq(_T_764, UInt<1>(0h0))
when _T_767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_764, UInt<1>(0h1), "") : assert_20
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(source_ok, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_771 = asUInt(reset)
node _T_772 = eq(_T_771, UInt<1>(0h0))
when _T_772 :
node _T_773 = eq(is_aligned, UInt<1>(0h0))
when _T_773 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_774 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_775 = asUInt(reset)
node _T_776 = eq(_T_775, UInt<1>(0h0))
when _T_776 :
node _T_777 = eq(_T_774, UInt<1>(0h0))
when _T_777 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_774, UInt<1>(0h1), "") : assert_23
node _T_778 = eq(io.in.a.bits.mask, mask)
node _T_779 = asUInt(reset)
node _T_780 = eq(_T_779, UInt<1>(0h0))
when _T_780 :
node _T_781 = eq(_T_778, UInt<1>(0h0))
when _T_781 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_778, UInt<1>(0h1), "") : assert_24
node _T_782 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_783 = asUInt(reset)
node _T_784 = eq(_T_783, UInt<1>(0h0))
when _T_784 :
node _T_785 = eq(_T_782, UInt<1>(0h0))
when _T_785 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_782, UInt<1>(0h1), "") : assert_25
node _T_786 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_786 :
node _T_787 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_788 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_789 = and(_T_787, _T_788)
node _T_790 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_791 = shr(io.in.a.bits.source, 2)
node _T_792 = eq(_T_791, UInt<6>(0h20))
node _T_793 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_794 = and(_T_792, _T_793)
node _T_795 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_796 = and(_T_794, _T_795)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_797 = shr(io.in.a.bits.source, 2)
node _T_798 = eq(_T_797, UInt<6>(0h21))
node _T_799 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_800 = and(_T_798, _T_799)
node _T_801 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_802 = and(_T_800, _T_801)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_803 = shr(io.in.a.bits.source, 2)
node _T_804 = eq(_T_803, UInt<6>(0h22))
node _T_805 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_806 = and(_T_804, _T_805)
node _T_807 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_808 = and(_T_806, _T_807)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_809 = shr(io.in.a.bits.source, 2)
node _T_810 = eq(_T_809, UInt<6>(0h23))
node _T_811 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_812 = and(_T_810, _T_811)
node _T_813 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_814 = and(_T_812, _T_813)
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 5, 0)
node _T_815 = shr(io.in.a.bits.source, 6)
node _T_816 = eq(_T_815, UInt<1>(0h1))
node _T_817 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_818 = and(_T_816, _T_817)
node _T_819 = leq(uncommonBits_40, UInt<6>(0h3f))
node _T_820 = and(_T_818, _T_819)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 5, 0)
node _T_821 = shr(io.in.a.bits.source, 6)
node _T_822 = eq(_T_821, UInt<1>(0h0))
node _T_823 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_824 = and(_T_822, _T_823)
node _T_825 = leq(uncommonBits_41, UInt<6>(0h3f))
node _T_826 = and(_T_824, _T_825)
node _T_827 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_828 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_829 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_830 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_831 = or(_T_790, _T_796)
node _T_832 = or(_T_831, _T_802)
node _T_833 = or(_T_832, _T_808)
node _T_834 = or(_T_833, _T_814)
node _T_835 = or(_T_834, _T_820)
node _T_836 = or(_T_835, _T_826)
node _T_837 = or(_T_836, _T_827)
node _T_838 = or(_T_837, _T_828)
node _T_839 = or(_T_838, _T_829)
node _T_840 = or(_T_839, _T_830)
node _T_841 = and(_T_789, _T_840)
node _T_842 = or(UInt<1>(0h0), _T_841)
node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_845 = and(_T_843, _T_844)
node _T_846 = or(UInt<1>(0h0), _T_845)
node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_848 = cvt(_T_847)
node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000)))
node _T_850 = asSInt(_T_849)
node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0)))
node _T_852 = and(_T_846, _T_851)
node _T_853 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_854 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_855 = and(_T_853, _T_854)
node _T_856 = or(UInt<1>(0h0), _T_855)
node _T_857 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_858 = cvt(_T_857)
node _T_859 = and(_T_858, asSInt(UInt<14>(0h2000)))
node _T_860 = asSInt(_T_859)
node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0)))
node _T_862 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_863 = cvt(_T_862)
node _T_864 = and(_T_863, asSInt(UInt<18>(0h2f000)))
node _T_865 = asSInt(_T_864)
node _T_866 = eq(_T_865, asSInt(UInt<1>(0h0)))
node _T_867 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_868 = cvt(_T_867)
node _T_869 = and(_T_868, asSInt(UInt<17>(0h10000)))
node _T_870 = asSInt(_T_869)
node _T_871 = eq(_T_870, asSInt(UInt<1>(0h0)))
node _T_872 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_873 = cvt(_T_872)
node _T_874 = and(_T_873, asSInt(UInt<13>(0h1000)))
node _T_875 = asSInt(_T_874)
node _T_876 = eq(_T_875, asSInt(UInt<1>(0h0)))
node _T_877 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_878 = cvt(_T_877)
node _T_879 = and(_T_878, asSInt(UInt<27>(0h4000000)))
node _T_880 = asSInt(_T_879)
node _T_881 = eq(_T_880, asSInt(UInt<1>(0h0)))
node _T_882 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_883 = cvt(_T_882)
node _T_884 = and(_T_883, asSInt(UInt<13>(0h1000)))
node _T_885 = asSInt(_T_884)
node _T_886 = eq(_T_885, asSInt(UInt<1>(0h0)))
node _T_887 = or(_T_861, _T_866)
node _T_888 = or(_T_887, _T_871)
node _T_889 = or(_T_888, _T_876)
node _T_890 = or(_T_889, _T_881)
node _T_891 = or(_T_890, _T_886)
node _T_892 = and(_T_856, _T_891)
node _T_893 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_894 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_895 = cvt(_T_894)
node _T_896 = and(_T_895, asSInt(UInt<17>(0h10000)))
node _T_897 = asSInt(_T_896)
node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0)))
node _T_899 = and(_T_893, _T_898)
node _T_900 = or(UInt<1>(0h0), _T_852)
node _T_901 = or(_T_900, _T_892)
node _T_902 = or(_T_901, _T_899)
node _T_903 = and(_T_842, _T_902)
node _T_904 = asUInt(reset)
node _T_905 = eq(_T_904, UInt<1>(0h0))
when _T_905 :
node _T_906 = eq(_T_903, UInt<1>(0h0))
when _T_906 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_903, UInt<1>(0h1), "") : assert_26
node _T_907 = asUInt(reset)
node _T_908 = eq(_T_907, UInt<1>(0h0))
when _T_908 :
node _T_909 = eq(source_ok, UInt<1>(0h0))
when _T_909 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_910 = asUInt(reset)
node _T_911 = eq(_T_910, UInt<1>(0h0))
when _T_911 :
node _T_912 = eq(is_aligned, UInt<1>(0h0))
when _T_912 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_913 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_914 = asUInt(reset)
node _T_915 = eq(_T_914, UInt<1>(0h0))
when _T_915 :
node _T_916 = eq(_T_913, UInt<1>(0h0))
when _T_916 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_913, UInt<1>(0h1), "") : assert_29
node _T_917 = eq(io.in.a.bits.mask, mask)
node _T_918 = asUInt(reset)
node _T_919 = eq(_T_918, UInt<1>(0h0))
when _T_919 :
node _T_920 = eq(_T_917, UInt<1>(0h0))
when _T_920 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_917, UInt<1>(0h1), "") : assert_30
node _T_921 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_921 :
node _T_922 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_923 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_924 = and(_T_922, _T_923)
node _T_925 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_926 = shr(io.in.a.bits.source, 2)
node _T_927 = eq(_T_926, UInt<6>(0h20))
node _T_928 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_929 = and(_T_927, _T_928)
node _T_930 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_931 = and(_T_929, _T_930)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_932 = shr(io.in.a.bits.source, 2)
node _T_933 = eq(_T_932, UInt<6>(0h21))
node _T_934 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_935 = and(_T_933, _T_934)
node _T_936 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_937 = and(_T_935, _T_936)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_938 = shr(io.in.a.bits.source, 2)
node _T_939 = eq(_T_938, UInt<6>(0h22))
node _T_940 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_941 = and(_T_939, _T_940)
node _T_942 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_943 = and(_T_941, _T_942)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_944 = shr(io.in.a.bits.source, 2)
node _T_945 = eq(_T_944, UInt<6>(0h23))
node _T_946 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_947 = and(_T_945, _T_946)
node _T_948 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_949 = and(_T_947, _T_948)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 5, 0)
node _T_950 = shr(io.in.a.bits.source, 6)
node _T_951 = eq(_T_950, UInt<1>(0h1))
node _T_952 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_953 = and(_T_951, _T_952)
node _T_954 = leq(uncommonBits_46, UInt<6>(0h3f))
node _T_955 = and(_T_953, _T_954)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 5, 0)
node _T_956 = shr(io.in.a.bits.source, 6)
node _T_957 = eq(_T_956, UInt<1>(0h0))
node _T_958 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_959 = and(_T_957, _T_958)
node _T_960 = leq(uncommonBits_47, UInt<6>(0h3f))
node _T_961 = and(_T_959, _T_960)
node _T_962 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_963 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_964 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_965 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_966 = or(_T_925, _T_931)
node _T_967 = or(_T_966, _T_937)
node _T_968 = or(_T_967, _T_943)
node _T_969 = or(_T_968, _T_949)
node _T_970 = or(_T_969, _T_955)
node _T_971 = or(_T_970, _T_961)
node _T_972 = or(_T_971, _T_962)
node _T_973 = or(_T_972, _T_963)
node _T_974 = or(_T_973, _T_964)
node _T_975 = or(_T_974, _T_965)
node _T_976 = and(_T_924, _T_975)
node _T_977 = or(UInt<1>(0h0), _T_976)
node _T_978 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_979 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_980 = and(_T_978, _T_979)
node _T_981 = or(UInt<1>(0h0), _T_980)
node _T_982 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_983 = cvt(_T_982)
node _T_984 = and(_T_983, asSInt(UInt<13>(0h1000)))
node _T_985 = asSInt(_T_984)
node _T_986 = eq(_T_985, asSInt(UInt<1>(0h0)))
node _T_987 = and(_T_981, _T_986)
node _T_988 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_989 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_990 = and(_T_988, _T_989)
node _T_991 = or(UInt<1>(0h0), _T_990)
node _T_992 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_993 = cvt(_T_992)
node _T_994 = and(_T_993, asSInt(UInt<14>(0h2000)))
node _T_995 = asSInt(_T_994)
node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0)))
node _T_997 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_998 = cvt(_T_997)
node _T_999 = and(_T_998, asSInt(UInt<18>(0h2f000)))
node _T_1000 = asSInt(_T_999)
node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0)))
node _T_1002 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1003 = cvt(_T_1002)
node _T_1004 = and(_T_1003, asSInt(UInt<17>(0h10000)))
node _T_1005 = asSInt(_T_1004)
node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0)))
node _T_1007 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1008 = cvt(_T_1007)
node _T_1009 = and(_T_1008, asSInt(UInt<13>(0h1000)))
node _T_1010 = asSInt(_T_1009)
node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0)))
node _T_1012 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1013 = cvt(_T_1012)
node _T_1014 = and(_T_1013, asSInt(UInt<27>(0h4000000)))
node _T_1015 = asSInt(_T_1014)
node _T_1016 = eq(_T_1015, asSInt(UInt<1>(0h0)))
node _T_1017 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1018 = cvt(_T_1017)
node _T_1019 = and(_T_1018, asSInt(UInt<13>(0h1000)))
node _T_1020 = asSInt(_T_1019)
node _T_1021 = eq(_T_1020, asSInt(UInt<1>(0h0)))
node _T_1022 = or(_T_996, _T_1001)
node _T_1023 = or(_T_1022, _T_1006)
node _T_1024 = or(_T_1023, _T_1011)
node _T_1025 = or(_T_1024, _T_1016)
node _T_1026 = or(_T_1025, _T_1021)
node _T_1027 = and(_T_991, _T_1026)
node _T_1028 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1029 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1030 = cvt(_T_1029)
node _T_1031 = and(_T_1030, asSInt(UInt<17>(0h10000)))
node _T_1032 = asSInt(_T_1031)
node _T_1033 = eq(_T_1032, asSInt(UInt<1>(0h0)))
node _T_1034 = and(_T_1028, _T_1033)
node _T_1035 = or(UInt<1>(0h0), _T_987)
node _T_1036 = or(_T_1035, _T_1027)
node _T_1037 = or(_T_1036, _T_1034)
node _T_1038 = and(_T_977, _T_1037)
node _T_1039 = asUInt(reset)
node _T_1040 = eq(_T_1039, UInt<1>(0h0))
when _T_1040 :
node _T_1041 = eq(_T_1038, UInt<1>(0h0))
when _T_1041 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_1038, UInt<1>(0h1), "") : assert_31
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(source_ok, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_1045 = asUInt(reset)
node _T_1046 = eq(_T_1045, UInt<1>(0h0))
when _T_1046 :
node _T_1047 = eq(is_aligned, UInt<1>(0h0))
when _T_1047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_1048 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1049 = asUInt(reset)
node _T_1050 = eq(_T_1049, UInt<1>(0h0))
when _T_1050 :
node _T_1051 = eq(_T_1048, UInt<1>(0h0))
when _T_1051 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_1048, UInt<1>(0h1), "") : assert_34
node _T_1052 = not(mask)
node _T_1053 = and(io.in.a.bits.mask, _T_1052)
node _T_1054 = eq(_T_1053, UInt<1>(0h0))
node _T_1055 = asUInt(reset)
node _T_1056 = eq(_T_1055, UInt<1>(0h0))
when _T_1056 :
node _T_1057 = eq(_T_1054, UInt<1>(0h0))
when _T_1057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_1054, UInt<1>(0h1), "") : assert_35
node _T_1058 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_1058 :
node _T_1059 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1060 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1061 = and(_T_1059, _T_1060)
node _T_1062 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_1063 = shr(io.in.a.bits.source, 2)
node _T_1064 = eq(_T_1063, UInt<6>(0h20))
node _T_1065 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_1066 = and(_T_1064, _T_1065)
node _T_1067 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_1068 = and(_T_1066, _T_1067)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_1069 = shr(io.in.a.bits.source, 2)
node _T_1070 = eq(_T_1069, UInt<6>(0h21))
node _T_1071 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_1072 = and(_T_1070, _T_1071)
node _T_1073 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_1074 = and(_T_1072, _T_1073)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_1075 = shr(io.in.a.bits.source, 2)
node _T_1076 = eq(_T_1075, UInt<6>(0h22))
node _T_1077 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_1078 = and(_T_1076, _T_1077)
node _T_1079 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_1080 = and(_T_1078, _T_1079)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_1081 = shr(io.in.a.bits.source, 2)
node _T_1082 = eq(_T_1081, UInt<6>(0h23))
node _T_1083 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_1084 = and(_T_1082, _T_1083)
node _T_1085 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_1086 = and(_T_1084, _T_1085)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 5, 0)
node _T_1087 = shr(io.in.a.bits.source, 6)
node _T_1088 = eq(_T_1087, UInt<1>(0h1))
node _T_1089 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_1090 = and(_T_1088, _T_1089)
node _T_1091 = leq(uncommonBits_52, UInt<6>(0h3f))
node _T_1092 = and(_T_1090, _T_1091)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 5, 0)
node _T_1093 = shr(io.in.a.bits.source, 6)
node _T_1094 = eq(_T_1093, UInt<1>(0h0))
node _T_1095 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_1096 = and(_T_1094, _T_1095)
node _T_1097 = leq(uncommonBits_53, UInt<6>(0h3f))
node _T_1098 = and(_T_1096, _T_1097)
node _T_1099 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_1100 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_1101 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_1102 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_1103 = or(_T_1062, _T_1068)
node _T_1104 = or(_T_1103, _T_1074)
node _T_1105 = or(_T_1104, _T_1080)
node _T_1106 = or(_T_1105, _T_1086)
node _T_1107 = or(_T_1106, _T_1092)
node _T_1108 = or(_T_1107, _T_1098)
node _T_1109 = or(_T_1108, _T_1099)
node _T_1110 = or(_T_1109, _T_1100)
node _T_1111 = or(_T_1110, _T_1101)
node _T_1112 = or(_T_1111, _T_1102)
node _T_1113 = and(_T_1061, _T_1112)
node _T_1114 = or(UInt<1>(0h0), _T_1113)
node _T_1115 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1116 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1117 = and(_T_1115, _T_1116)
node _T_1118 = or(UInt<1>(0h0), _T_1117)
node _T_1119 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1120 = cvt(_T_1119)
node _T_1121 = and(_T_1120, asSInt(UInt<15>(0h5000)))
node _T_1122 = asSInt(_T_1121)
node _T_1123 = eq(_T_1122, asSInt(UInt<1>(0h0)))
node _T_1124 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1125 = cvt(_T_1124)
node _T_1126 = and(_T_1125, asSInt(UInt<13>(0h1000)))
node _T_1127 = asSInt(_T_1126)
node _T_1128 = eq(_T_1127, asSInt(UInt<1>(0h0)))
node _T_1129 = or(_T_1123, _T_1128)
node _T_1130 = and(_T_1118, _T_1129)
node _T_1131 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1132 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1133 = cvt(_T_1132)
node _T_1134 = and(_T_1133, asSInt(UInt<13>(0h1000)))
node _T_1135 = asSInt(_T_1134)
node _T_1136 = eq(_T_1135, asSInt(UInt<1>(0h0)))
node _T_1137 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1138 = cvt(_T_1137)
node _T_1139 = and(_T_1138, asSInt(UInt<17>(0h10000)))
node _T_1140 = asSInt(_T_1139)
node _T_1141 = eq(_T_1140, asSInt(UInt<1>(0h0)))
node _T_1142 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1143 = cvt(_T_1142)
node _T_1144 = and(_T_1143, asSInt(UInt<18>(0h2f000)))
node _T_1145 = asSInt(_T_1144)
node _T_1146 = eq(_T_1145, asSInt(UInt<1>(0h0)))
node _T_1147 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1148 = cvt(_T_1147)
node _T_1149 = and(_T_1148, asSInt(UInt<17>(0h10000)))
node _T_1150 = asSInt(_T_1149)
node _T_1151 = eq(_T_1150, asSInt(UInt<1>(0h0)))
node _T_1152 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1153 = cvt(_T_1152)
node _T_1154 = and(_T_1153, asSInt(UInt<13>(0h1000)))
node _T_1155 = asSInt(_T_1154)
node _T_1156 = eq(_T_1155, asSInt(UInt<1>(0h0)))
node _T_1157 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1158 = cvt(_T_1157)
node _T_1159 = and(_T_1158, asSInt(UInt<27>(0h4000000)))
node _T_1160 = asSInt(_T_1159)
node _T_1161 = eq(_T_1160, asSInt(UInt<1>(0h0)))
node _T_1162 = or(_T_1136, _T_1141)
node _T_1163 = or(_T_1162, _T_1146)
node _T_1164 = or(_T_1163, _T_1151)
node _T_1165 = or(_T_1164, _T_1156)
node _T_1166 = or(_T_1165, _T_1161)
node _T_1167 = and(_T_1131, _T_1166)
node _T_1168 = or(UInt<1>(0h0), _T_1130)
node _T_1169 = or(_T_1168, _T_1167)
node _T_1170 = and(_T_1114, _T_1169)
node _T_1171 = asUInt(reset)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
when _T_1172 :
node _T_1173 = eq(_T_1170, UInt<1>(0h0))
when _T_1173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1170, UInt<1>(0h1), "") : assert_36
node _T_1174 = asUInt(reset)
node _T_1175 = eq(_T_1174, UInt<1>(0h0))
when _T_1175 :
node _T_1176 = eq(source_ok, UInt<1>(0h0))
when _T_1176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1177 = asUInt(reset)
node _T_1178 = eq(_T_1177, UInt<1>(0h0))
when _T_1178 :
node _T_1179 = eq(is_aligned, UInt<1>(0h0))
when _T_1179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1180 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(_T_1180, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1180, UInt<1>(0h1), "") : assert_39
node _T_1184 = eq(io.in.a.bits.mask, mask)
node _T_1185 = asUInt(reset)
node _T_1186 = eq(_T_1185, UInt<1>(0h0))
when _T_1186 :
node _T_1187 = eq(_T_1184, UInt<1>(0h0))
when _T_1187 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1184, UInt<1>(0h1), "") : assert_40
node _T_1188 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1188 :
node _T_1189 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1190 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1191 = and(_T_1189, _T_1190)
node _T_1192 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0)
node _T_1193 = shr(io.in.a.bits.source, 2)
node _T_1194 = eq(_T_1193, UInt<6>(0h20))
node _T_1195 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_1196 = and(_T_1194, _T_1195)
node _T_1197 = leq(uncommonBits_54, UInt<2>(0h3))
node _T_1198 = and(_T_1196, _T_1197)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0)
node _T_1199 = shr(io.in.a.bits.source, 2)
node _T_1200 = eq(_T_1199, UInt<6>(0h21))
node _T_1201 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_1202 = and(_T_1200, _T_1201)
node _T_1203 = leq(uncommonBits_55, UInt<2>(0h3))
node _T_1204 = and(_T_1202, _T_1203)
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_1205 = shr(io.in.a.bits.source, 2)
node _T_1206 = eq(_T_1205, UInt<6>(0h22))
node _T_1207 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_1208 = and(_T_1206, _T_1207)
node _T_1209 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_1210 = and(_T_1208, _T_1209)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_1211 = shr(io.in.a.bits.source, 2)
node _T_1212 = eq(_T_1211, UInt<6>(0h23))
node _T_1213 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_1214 = and(_T_1212, _T_1213)
node _T_1215 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_1216 = and(_T_1214, _T_1215)
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 5, 0)
node _T_1217 = shr(io.in.a.bits.source, 6)
node _T_1218 = eq(_T_1217, UInt<1>(0h1))
node _T_1219 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_1220 = and(_T_1218, _T_1219)
node _T_1221 = leq(uncommonBits_58, UInt<6>(0h3f))
node _T_1222 = and(_T_1220, _T_1221)
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 5, 0)
node _T_1223 = shr(io.in.a.bits.source, 6)
node _T_1224 = eq(_T_1223, UInt<1>(0h0))
node _T_1225 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_1226 = and(_T_1224, _T_1225)
node _T_1227 = leq(uncommonBits_59, UInt<6>(0h3f))
node _T_1228 = and(_T_1226, _T_1227)
node _T_1229 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_1230 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_1231 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_1232 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_1233 = or(_T_1192, _T_1198)
node _T_1234 = or(_T_1233, _T_1204)
node _T_1235 = or(_T_1234, _T_1210)
node _T_1236 = or(_T_1235, _T_1216)
node _T_1237 = or(_T_1236, _T_1222)
node _T_1238 = or(_T_1237, _T_1228)
node _T_1239 = or(_T_1238, _T_1229)
node _T_1240 = or(_T_1239, _T_1230)
node _T_1241 = or(_T_1240, _T_1231)
node _T_1242 = or(_T_1241, _T_1232)
node _T_1243 = and(_T_1191, _T_1242)
node _T_1244 = or(UInt<1>(0h0), _T_1243)
node _T_1245 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1246 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1247 = and(_T_1245, _T_1246)
node _T_1248 = or(UInt<1>(0h0), _T_1247)
node _T_1249 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1250 = cvt(_T_1249)
node _T_1251 = and(_T_1250, asSInt(UInt<15>(0h5000)))
node _T_1252 = asSInt(_T_1251)
node _T_1253 = eq(_T_1252, asSInt(UInt<1>(0h0)))
node _T_1254 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1255 = cvt(_T_1254)
node _T_1256 = and(_T_1255, asSInt(UInt<13>(0h1000)))
node _T_1257 = asSInt(_T_1256)
node _T_1258 = eq(_T_1257, asSInt(UInt<1>(0h0)))
node _T_1259 = or(_T_1253, _T_1258)
node _T_1260 = and(_T_1248, _T_1259)
node _T_1261 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1262 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1263 = cvt(_T_1262)
node _T_1264 = and(_T_1263, asSInt(UInt<13>(0h1000)))
node _T_1265 = asSInt(_T_1264)
node _T_1266 = eq(_T_1265, asSInt(UInt<1>(0h0)))
node _T_1267 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1268 = cvt(_T_1267)
node _T_1269 = and(_T_1268, asSInt(UInt<17>(0h10000)))
node _T_1270 = asSInt(_T_1269)
node _T_1271 = eq(_T_1270, asSInt(UInt<1>(0h0)))
node _T_1272 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1273 = cvt(_T_1272)
node _T_1274 = and(_T_1273, asSInt(UInt<18>(0h2f000)))
node _T_1275 = asSInt(_T_1274)
node _T_1276 = eq(_T_1275, asSInt(UInt<1>(0h0)))
node _T_1277 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1278 = cvt(_T_1277)
node _T_1279 = and(_T_1278, asSInt(UInt<17>(0h10000)))
node _T_1280 = asSInt(_T_1279)
node _T_1281 = eq(_T_1280, asSInt(UInt<1>(0h0)))
node _T_1282 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1283 = cvt(_T_1282)
node _T_1284 = and(_T_1283, asSInt(UInt<13>(0h1000)))
node _T_1285 = asSInt(_T_1284)
node _T_1286 = eq(_T_1285, asSInt(UInt<1>(0h0)))
node _T_1287 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1288 = cvt(_T_1287)
node _T_1289 = and(_T_1288, asSInt(UInt<27>(0h4000000)))
node _T_1290 = asSInt(_T_1289)
node _T_1291 = eq(_T_1290, asSInt(UInt<1>(0h0)))
node _T_1292 = or(_T_1266, _T_1271)
node _T_1293 = or(_T_1292, _T_1276)
node _T_1294 = or(_T_1293, _T_1281)
node _T_1295 = or(_T_1294, _T_1286)
node _T_1296 = or(_T_1295, _T_1291)
node _T_1297 = and(_T_1261, _T_1296)
node _T_1298 = or(UInt<1>(0h0), _T_1260)
node _T_1299 = or(_T_1298, _T_1297)
node _T_1300 = and(_T_1244, _T_1299)
node _T_1301 = asUInt(reset)
node _T_1302 = eq(_T_1301, UInt<1>(0h0))
when _T_1302 :
node _T_1303 = eq(_T_1300, UInt<1>(0h0))
when _T_1303 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1300, UInt<1>(0h1), "") : assert_41
node _T_1304 = asUInt(reset)
node _T_1305 = eq(_T_1304, UInt<1>(0h0))
when _T_1305 :
node _T_1306 = eq(source_ok, UInt<1>(0h0))
when _T_1306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1307 = asUInt(reset)
node _T_1308 = eq(_T_1307, UInt<1>(0h0))
when _T_1308 :
node _T_1309 = eq(is_aligned, UInt<1>(0h0))
when _T_1309 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1310 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1311 = asUInt(reset)
node _T_1312 = eq(_T_1311, UInt<1>(0h0))
when _T_1312 :
node _T_1313 = eq(_T_1310, UInt<1>(0h0))
when _T_1313 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1310, UInt<1>(0h1), "") : assert_44
node _T_1314 = eq(io.in.a.bits.mask, mask)
node _T_1315 = asUInt(reset)
node _T_1316 = eq(_T_1315, UInt<1>(0h0))
when _T_1316 :
node _T_1317 = eq(_T_1314, UInt<1>(0h0))
when _T_1317 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1314, UInt<1>(0h1), "") : assert_45
node _T_1318 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1318 :
node _T_1319 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1320 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1321 = and(_T_1319, _T_1320)
node _T_1322 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_1323 = shr(io.in.a.bits.source, 2)
node _T_1324 = eq(_T_1323, UInt<6>(0h20))
node _T_1325 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_1326 = and(_T_1324, _T_1325)
node _T_1327 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_1328 = and(_T_1326, _T_1327)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_1329 = shr(io.in.a.bits.source, 2)
node _T_1330 = eq(_T_1329, UInt<6>(0h21))
node _T_1331 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_1332 = and(_T_1330, _T_1331)
node _T_1333 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_1334 = and(_T_1332, _T_1333)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_1335 = shr(io.in.a.bits.source, 2)
node _T_1336 = eq(_T_1335, UInt<6>(0h22))
node _T_1337 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_1338 = and(_T_1336, _T_1337)
node _T_1339 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_1340 = and(_T_1338, _T_1339)
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_1341 = shr(io.in.a.bits.source, 2)
node _T_1342 = eq(_T_1341, UInt<6>(0h23))
node _T_1343 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_1344 = and(_T_1342, _T_1343)
node _T_1345 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_1346 = and(_T_1344, _T_1345)
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 5, 0)
node _T_1347 = shr(io.in.a.bits.source, 6)
node _T_1348 = eq(_T_1347, UInt<1>(0h1))
node _T_1349 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_1350 = and(_T_1348, _T_1349)
node _T_1351 = leq(uncommonBits_64, UInt<6>(0h3f))
node _T_1352 = and(_T_1350, _T_1351)
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 5, 0)
node _T_1353 = shr(io.in.a.bits.source, 6)
node _T_1354 = eq(_T_1353, UInt<1>(0h0))
node _T_1355 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_1356 = and(_T_1354, _T_1355)
node _T_1357 = leq(uncommonBits_65, UInt<6>(0h3f))
node _T_1358 = and(_T_1356, _T_1357)
node _T_1359 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_1360 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_1361 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_1362 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_1363 = or(_T_1322, _T_1328)
node _T_1364 = or(_T_1363, _T_1334)
node _T_1365 = or(_T_1364, _T_1340)
node _T_1366 = or(_T_1365, _T_1346)
node _T_1367 = or(_T_1366, _T_1352)
node _T_1368 = or(_T_1367, _T_1358)
node _T_1369 = or(_T_1368, _T_1359)
node _T_1370 = or(_T_1369, _T_1360)
node _T_1371 = or(_T_1370, _T_1361)
node _T_1372 = or(_T_1371, _T_1362)
node _T_1373 = and(_T_1321, _T_1372)
node _T_1374 = or(UInt<1>(0h0), _T_1373)
node _T_1375 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1376 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1377 = and(_T_1375, _T_1376)
node _T_1378 = or(UInt<1>(0h0), _T_1377)
node _T_1379 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1380 = cvt(_T_1379)
node _T_1381 = and(_T_1380, asSInt(UInt<13>(0h1000)))
node _T_1382 = asSInt(_T_1381)
node _T_1383 = eq(_T_1382, asSInt(UInt<1>(0h0)))
node _T_1384 = and(_T_1378, _T_1383)
node _T_1385 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1386 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1387 = cvt(_T_1386)
node _T_1388 = and(_T_1387, asSInt(UInt<14>(0h2000)))
node _T_1389 = asSInt(_T_1388)
node _T_1390 = eq(_T_1389, asSInt(UInt<1>(0h0)))
node _T_1391 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1392 = cvt(_T_1391)
node _T_1393 = and(_T_1392, asSInt(UInt<17>(0h10000)))
node _T_1394 = asSInt(_T_1393)
node _T_1395 = eq(_T_1394, asSInt(UInt<1>(0h0)))
node _T_1396 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1397 = cvt(_T_1396)
node _T_1398 = and(_T_1397, asSInt(UInt<18>(0h2f000)))
node _T_1399 = asSInt(_T_1398)
node _T_1400 = eq(_T_1399, asSInt(UInt<1>(0h0)))
node _T_1401 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1402 = cvt(_T_1401)
node _T_1403 = and(_T_1402, asSInt(UInt<17>(0h10000)))
node _T_1404 = asSInt(_T_1403)
node _T_1405 = eq(_T_1404, asSInt(UInt<1>(0h0)))
node _T_1406 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1407 = cvt(_T_1406)
node _T_1408 = and(_T_1407, asSInt(UInt<13>(0h1000)))
node _T_1409 = asSInt(_T_1408)
node _T_1410 = eq(_T_1409, asSInt(UInt<1>(0h0)))
node _T_1411 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1412 = cvt(_T_1411)
node _T_1413 = and(_T_1412, asSInt(UInt<27>(0h4000000)))
node _T_1414 = asSInt(_T_1413)
node _T_1415 = eq(_T_1414, asSInt(UInt<1>(0h0)))
node _T_1416 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1417 = cvt(_T_1416)
node _T_1418 = and(_T_1417, asSInt(UInt<13>(0h1000)))
node _T_1419 = asSInt(_T_1418)
node _T_1420 = eq(_T_1419, asSInt(UInt<1>(0h0)))
node _T_1421 = or(_T_1390, _T_1395)
node _T_1422 = or(_T_1421, _T_1400)
node _T_1423 = or(_T_1422, _T_1405)
node _T_1424 = or(_T_1423, _T_1410)
node _T_1425 = or(_T_1424, _T_1415)
node _T_1426 = or(_T_1425, _T_1420)
node _T_1427 = and(_T_1385, _T_1426)
node _T_1428 = or(UInt<1>(0h0), _T_1384)
node _T_1429 = or(_T_1428, _T_1427)
node _T_1430 = and(_T_1374, _T_1429)
node _T_1431 = asUInt(reset)
node _T_1432 = eq(_T_1431, UInt<1>(0h0))
when _T_1432 :
node _T_1433 = eq(_T_1430, UInt<1>(0h0))
when _T_1433 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1430, UInt<1>(0h1), "") : assert_46
node _T_1434 = asUInt(reset)
node _T_1435 = eq(_T_1434, UInt<1>(0h0))
when _T_1435 :
node _T_1436 = eq(source_ok, UInt<1>(0h0))
when _T_1436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1437 = asUInt(reset)
node _T_1438 = eq(_T_1437, UInt<1>(0h0))
when _T_1438 :
node _T_1439 = eq(is_aligned, UInt<1>(0h0))
when _T_1439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1440 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1441 = asUInt(reset)
node _T_1442 = eq(_T_1441, UInt<1>(0h0))
when _T_1442 :
node _T_1443 = eq(_T_1440, UInt<1>(0h0))
when _T_1443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1440, UInt<1>(0h1), "") : assert_49
node _T_1444 = eq(io.in.a.bits.mask, mask)
node _T_1445 = asUInt(reset)
node _T_1446 = eq(_T_1445, UInt<1>(0h0))
when _T_1446 :
node _T_1447 = eq(_T_1444, UInt<1>(0h0))
when _T_1447 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1444, UInt<1>(0h1), "") : assert_50
node _T_1448 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1449 = asUInt(reset)
node _T_1450 = eq(_T_1449, UInt<1>(0h0))
when _T_1450 :
node _T_1451 = eq(_T_1448, UInt<1>(0h0))
when _T_1451 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1448, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1452 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1453 = asUInt(reset)
node _T_1454 = eq(_T_1453, UInt<1>(0h0))
when _T_1454 :
node _T_1455 = eq(_T_1452, UInt<1>(0h0))
when _T_1455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1452, UInt<1>(0h1), "") : assert_52
node _source_ok_T_50 = eq(io.in.d.bits.source, UInt<8>(0h90))
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_51 = shr(io.in.d.bits.source, 2)
node _source_ok_T_52 = eq(_source_ok_T_51, UInt<6>(0h20))
node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_57 = shr(io.in.d.bits.source, 2)
node _source_ok_T_58 = eq(_source_ok_T_57, UInt<6>(0h21))
node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_63 = shr(io.in.d.bits.source, 2)
node _source_ok_T_64 = eq(_source_ok_T_63, UInt<6>(0h22))
node _source_ok_T_65 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65)
node _source_ok_T_67 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_69 = shr(io.in.d.bits.source, 2)
node _source_ok_T_70 = eq(_source_ok_T_69, UInt<6>(0h23))
node _source_ok_T_71 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71)
node _source_ok_T_73 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73)
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 5, 0)
node _source_ok_T_75 = shr(io.in.d.bits.source, 6)
node _source_ok_T_76 = eq(_source_ok_T_75, UInt<1>(0h1))
node _source_ok_T_77 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77)
node _source_ok_T_79 = leq(source_ok_uncommonBits_10, UInt<6>(0h3f))
node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79)
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 5, 0)
node _source_ok_T_81 = shr(io.in.d.bits.source, 6)
node _source_ok_T_82 = eq(_source_ok_T_81, UInt<1>(0h0))
node _source_ok_T_83 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83)
node _source_ok_T_85 = leq(source_ok_uncommonBits_11, UInt<6>(0h3f))
node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85)
node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<8>(0ha0))
node _source_ok_T_88 = eq(io.in.d.bits.source, UInt<8>(0ha1))
node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<8>(0ha2))
node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<9>(0h100))
wire _source_ok_WIRE_1 : UInt<1>[11]
connect _source_ok_WIRE_1[0], _source_ok_T_50
connect _source_ok_WIRE_1[1], _source_ok_T_56
connect _source_ok_WIRE_1[2], _source_ok_T_62
connect _source_ok_WIRE_1[3], _source_ok_T_68
connect _source_ok_WIRE_1[4], _source_ok_T_74
connect _source_ok_WIRE_1[5], _source_ok_T_80
connect _source_ok_WIRE_1[6], _source_ok_T_86
connect _source_ok_WIRE_1[7], _source_ok_T_87
connect _source_ok_WIRE_1[8], _source_ok_T_88
connect _source_ok_WIRE_1[9], _source_ok_T_89
connect _source_ok_WIRE_1[10], _source_ok_T_90
node _source_ok_T_91 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE_1[2])
node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[3])
node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[4])
node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[5])
node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[6])
node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[7])
node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[8])
node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[9])
node source_ok_1 = or(_source_ok_T_99, _source_ok_WIRE_1[10])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1456 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1456 :
node _T_1457 = asUInt(reset)
node _T_1458 = eq(_T_1457, UInt<1>(0h0))
when _T_1458 :
node _T_1459 = eq(source_ok_1, UInt<1>(0h0))
when _T_1459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1460 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1461 = asUInt(reset)
node _T_1462 = eq(_T_1461, UInt<1>(0h0))
when _T_1462 :
node _T_1463 = eq(_T_1460, UInt<1>(0h0))
when _T_1463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1460, UInt<1>(0h1), "") : assert_54
node _T_1464 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1465 = asUInt(reset)
node _T_1466 = eq(_T_1465, UInt<1>(0h0))
when _T_1466 :
node _T_1467 = eq(_T_1464, UInt<1>(0h0))
when _T_1467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1464, UInt<1>(0h1), "") : assert_55
node _T_1468 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1469 = asUInt(reset)
node _T_1470 = eq(_T_1469, UInt<1>(0h0))
when _T_1470 :
node _T_1471 = eq(_T_1468, UInt<1>(0h0))
when _T_1471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1468, UInt<1>(0h1), "") : assert_56
node _T_1472 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1473 = asUInt(reset)
node _T_1474 = eq(_T_1473, UInt<1>(0h0))
when _T_1474 :
node _T_1475 = eq(_T_1472, UInt<1>(0h0))
when _T_1475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1472, UInt<1>(0h1), "") : assert_57
node _T_1476 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1476 :
node _T_1477 = asUInt(reset)
node _T_1478 = eq(_T_1477, UInt<1>(0h0))
when _T_1478 :
node _T_1479 = eq(source_ok_1, UInt<1>(0h0))
when _T_1479 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1480 = asUInt(reset)
node _T_1481 = eq(_T_1480, UInt<1>(0h0))
when _T_1481 :
node _T_1482 = eq(sink_ok, UInt<1>(0h0))
when _T_1482 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1483 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1484 = asUInt(reset)
node _T_1485 = eq(_T_1484, UInt<1>(0h0))
when _T_1485 :
node _T_1486 = eq(_T_1483, UInt<1>(0h0))
when _T_1486 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1483, UInt<1>(0h1), "") : assert_60
node _T_1487 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1488 = asUInt(reset)
node _T_1489 = eq(_T_1488, UInt<1>(0h0))
when _T_1489 :
node _T_1490 = eq(_T_1487, UInt<1>(0h0))
when _T_1490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1487, UInt<1>(0h1), "") : assert_61
node _T_1491 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1492 = asUInt(reset)
node _T_1493 = eq(_T_1492, UInt<1>(0h0))
when _T_1493 :
node _T_1494 = eq(_T_1491, UInt<1>(0h0))
when _T_1494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1491, UInt<1>(0h1), "") : assert_62
node _T_1495 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1496 = asUInt(reset)
node _T_1497 = eq(_T_1496, UInt<1>(0h0))
when _T_1497 :
node _T_1498 = eq(_T_1495, UInt<1>(0h0))
when _T_1498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1495, UInt<1>(0h1), "") : assert_63
node _T_1499 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1500 = or(UInt<1>(0h1), _T_1499)
node _T_1501 = asUInt(reset)
node _T_1502 = eq(_T_1501, UInt<1>(0h0))
when _T_1502 :
node _T_1503 = eq(_T_1500, UInt<1>(0h0))
when _T_1503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1500, UInt<1>(0h1), "") : assert_64
node _T_1504 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1504 :
node _T_1505 = asUInt(reset)
node _T_1506 = eq(_T_1505, UInt<1>(0h0))
when _T_1506 :
node _T_1507 = eq(source_ok_1, UInt<1>(0h0))
when _T_1507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1508 = asUInt(reset)
node _T_1509 = eq(_T_1508, UInt<1>(0h0))
when _T_1509 :
node _T_1510 = eq(sink_ok, UInt<1>(0h0))
when _T_1510 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1511 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1512 = asUInt(reset)
node _T_1513 = eq(_T_1512, UInt<1>(0h0))
when _T_1513 :
node _T_1514 = eq(_T_1511, UInt<1>(0h0))
when _T_1514 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1511, UInt<1>(0h1), "") : assert_67
node _T_1515 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1516 = asUInt(reset)
node _T_1517 = eq(_T_1516, UInt<1>(0h0))
when _T_1517 :
node _T_1518 = eq(_T_1515, UInt<1>(0h0))
when _T_1518 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1515, UInt<1>(0h1), "") : assert_68
node _T_1519 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1520 = asUInt(reset)
node _T_1521 = eq(_T_1520, UInt<1>(0h0))
when _T_1521 :
node _T_1522 = eq(_T_1519, UInt<1>(0h0))
when _T_1522 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1519, UInt<1>(0h1), "") : assert_69
node _T_1523 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1524 = or(_T_1523, io.in.d.bits.corrupt)
node _T_1525 = asUInt(reset)
node _T_1526 = eq(_T_1525, UInt<1>(0h0))
when _T_1526 :
node _T_1527 = eq(_T_1524, UInt<1>(0h0))
when _T_1527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1524, UInt<1>(0h1), "") : assert_70
node _T_1528 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1529 = or(UInt<1>(0h1), _T_1528)
node _T_1530 = asUInt(reset)
node _T_1531 = eq(_T_1530, UInt<1>(0h0))
when _T_1531 :
node _T_1532 = eq(_T_1529, UInt<1>(0h0))
when _T_1532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1529, UInt<1>(0h1), "") : assert_71
node _T_1533 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1533 :
node _T_1534 = asUInt(reset)
node _T_1535 = eq(_T_1534, UInt<1>(0h0))
when _T_1535 :
node _T_1536 = eq(source_ok_1, UInt<1>(0h0))
when _T_1536 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1537 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1538 = asUInt(reset)
node _T_1539 = eq(_T_1538, UInt<1>(0h0))
when _T_1539 :
node _T_1540 = eq(_T_1537, UInt<1>(0h0))
when _T_1540 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1537, UInt<1>(0h1), "") : assert_73
node _T_1541 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1542 = asUInt(reset)
node _T_1543 = eq(_T_1542, UInt<1>(0h0))
when _T_1543 :
node _T_1544 = eq(_T_1541, UInt<1>(0h0))
when _T_1544 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1541, UInt<1>(0h1), "") : assert_74
node _T_1545 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1546 = or(UInt<1>(0h1), _T_1545)
node _T_1547 = asUInt(reset)
node _T_1548 = eq(_T_1547, UInt<1>(0h0))
when _T_1548 :
node _T_1549 = eq(_T_1546, UInt<1>(0h0))
when _T_1549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1546, UInt<1>(0h1), "") : assert_75
node _T_1550 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1550 :
node _T_1551 = asUInt(reset)
node _T_1552 = eq(_T_1551, UInt<1>(0h0))
when _T_1552 :
node _T_1553 = eq(source_ok_1, UInt<1>(0h0))
when _T_1553 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1554 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1555 = asUInt(reset)
node _T_1556 = eq(_T_1555, UInt<1>(0h0))
when _T_1556 :
node _T_1557 = eq(_T_1554, UInt<1>(0h0))
when _T_1557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1554, UInt<1>(0h1), "") : assert_77
node _T_1558 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1559 = or(_T_1558, io.in.d.bits.corrupt)
node _T_1560 = asUInt(reset)
node _T_1561 = eq(_T_1560, UInt<1>(0h0))
when _T_1561 :
node _T_1562 = eq(_T_1559, UInt<1>(0h0))
when _T_1562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1559, UInt<1>(0h1), "") : assert_78
node _T_1563 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1564 = or(UInt<1>(0h1), _T_1563)
node _T_1565 = asUInt(reset)
node _T_1566 = eq(_T_1565, UInt<1>(0h0))
when _T_1566 :
node _T_1567 = eq(_T_1564, UInt<1>(0h0))
when _T_1567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1564, UInt<1>(0h1), "") : assert_79
node _T_1568 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1568 :
node _T_1569 = asUInt(reset)
node _T_1570 = eq(_T_1569, UInt<1>(0h0))
when _T_1570 :
node _T_1571 = eq(source_ok_1, UInt<1>(0h0))
when _T_1571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1572 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1573 = asUInt(reset)
node _T_1574 = eq(_T_1573, UInt<1>(0h0))
when _T_1574 :
node _T_1575 = eq(_T_1572, UInt<1>(0h0))
when _T_1575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1572, UInt<1>(0h1), "") : assert_81
node _T_1576 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1577 = asUInt(reset)
node _T_1578 = eq(_T_1577, UInt<1>(0h0))
when _T_1578 :
node _T_1579 = eq(_T_1576, UInt<1>(0h0))
when _T_1579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1576, UInt<1>(0h1), "") : assert_82
node _T_1580 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1581 = or(UInt<1>(0h1), _T_1580)
node _T_1582 = asUInt(reset)
node _T_1583 = eq(_T_1582, UInt<1>(0h0))
when _T_1583 :
node _T_1584 = eq(_T_1581, UInt<1>(0h0))
when _T_1584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1581, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<9>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1585 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1586 = asUInt(reset)
node _T_1587 = eq(_T_1586, UInt<1>(0h0))
when _T_1587 :
node _T_1588 = eq(_T_1585, UInt<1>(0h0))
when _T_1588 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1585, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<9>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1589 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1590 = asUInt(reset)
node _T_1591 = eq(_T_1590, UInt<1>(0h0))
when _T_1591 :
node _T_1592 = eq(_T_1589, UInt<1>(0h0))
when _T_1592 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1589, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1593 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1594 = asUInt(reset)
node _T_1595 = eq(_T_1594, UInt<1>(0h0))
when _T_1595 :
node _T_1596 = eq(_T_1593, UInt<1>(0h0))
when _T_1596 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1593, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1597 = eq(a_first, UInt<1>(0h0))
node _T_1598 = and(io.in.a.valid, _T_1597)
when _T_1598 :
node _T_1599 = eq(io.in.a.bits.opcode, opcode)
node _T_1600 = asUInt(reset)
node _T_1601 = eq(_T_1600, UInt<1>(0h0))
when _T_1601 :
node _T_1602 = eq(_T_1599, UInt<1>(0h0))
when _T_1602 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1599, UInt<1>(0h1), "") : assert_87
node _T_1603 = eq(io.in.a.bits.param, param)
node _T_1604 = asUInt(reset)
node _T_1605 = eq(_T_1604, UInt<1>(0h0))
when _T_1605 :
node _T_1606 = eq(_T_1603, UInt<1>(0h0))
when _T_1606 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1603, UInt<1>(0h1), "") : assert_88
node _T_1607 = eq(io.in.a.bits.size, size)
node _T_1608 = asUInt(reset)
node _T_1609 = eq(_T_1608, UInt<1>(0h0))
when _T_1609 :
node _T_1610 = eq(_T_1607, UInt<1>(0h0))
when _T_1610 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1607, UInt<1>(0h1), "") : assert_89
node _T_1611 = eq(io.in.a.bits.source, source)
node _T_1612 = asUInt(reset)
node _T_1613 = eq(_T_1612, UInt<1>(0h0))
when _T_1613 :
node _T_1614 = eq(_T_1611, UInt<1>(0h0))
when _T_1614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1611, UInt<1>(0h1), "") : assert_90
node _T_1615 = eq(io.in.a.bits.address, address)
node _T_1616 = asUInt(reset)
node _T_1617 = eq(_T_1616, UInt<1>(0h0))
when _T_1617 :
node _T_1618 = eq(_T_1615, UInt<1>(0h0))
when _T_1618 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1615, UInt<1>(0h1), "") : assert_91
node _T_1619 = and(io.in.a.ready, io.in.a.valid)
node _T_1620 = and(_T_1619, a_first)
when _T_1620 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1621 = eq(d_first, UInt<1>(0h0))
node _T_1622 = and(io.in.d.valid, _T_1621)
when _T_1622 :
node _T_1623 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1624 = asUInt(reset)
node _T_1625 = eq(_T_1624, UInt<1>(0h0))
when _T_1625 :
node _T_1626 = eq(_T_1623, UInt<1>(0h0))
when _T_1626 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1623, UInt<1>(0h1), "") : assert_92
node _T_1627 = eq(io.in.d.bits.param, param_1)
node _T_1628 = asUInt(reset)
node _T_1629 = eq(_T_1628, UInt<1>(0h0))
when _T_1629 :
node _T_1630 = eq(_T_1627, UInt<1>(0h0))
when _T_1630 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1627, UInt<1>(0h1), "") : assert_93
node _T_1631 = eq(io.in.d.bits.size, size_1)
node _T_1632 = asUInt(reset)
node _T_1633 = eq(_T_1632, UInt<1>(0h0))
when _T_1633 :
node _T_1634 = eq(_T_1631, UInt<1>(0h0))
when _T_1634 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1631, UInt<1>(0h1), "") : assert_94
node _T_1635 = eq(io.in.d.bits.source, source_1)
node _T_1636 = asUInt(reset)
node _T_1637 = eq(_T_1636, UInt<1>(0h0))
when _T_1637 :
node _T_1638 = eq(_T_1635, UInt<1>(0h0))
when _T_1638 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1635, UInt<1>(0h1), "") : assert_95
node _T_1639 = eq(io.in.d.bits.sink, sink)
node _T_1640 = asUInt(reset)
node _T_1641 = eq(_T_1640, UInt<1>(0h0))
when _T_1641 :
node _T_1642 = eq(_T_1639, UInt<1>(0h0))
when _T_1642 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1639, UInt<1>(0h1), "") : assert_96
node _T_1643 = eq(io.in.d.bits.denied, denied)
node _T_1644 = asUInt(reset)
node _T_1645 = eq(_T_1644, UInt<1>(0h0))
when _T_1645 :
node _T_1646 = eq(_T_1643, UInt<1>(0h0))
when _T_1646 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1643, UInt<1>(0h1), "") : assert_97
node _T_1647 = and(io.in.d.ready, io.in.d.valid)
node _T_1648 = and(_T_1647, d_first)
when _T_1648 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<257>, clock, reset, UInt<257>(0h0)
regreset inflight_opcodes : UInt<1028>, clock, reset, UInt<1028>(0h0)
regreset inflight_sizes : UInt<2056>, clock, reset, UInt<2056>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<257>
connect a_set, UInt<257>(0h0)
wire a_set_wo_ready : UInt<257>
connect a_set_wo_ready, UInt<257>(0h0)
wire a_opcodes_set : UInt<1028>
connect a_opcodes_set, UInt<1028>(0h0)
wire a_sizes_set : UInt<2056>
connect a_sizes_set, UInt<2056>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1649 = and(io.in.a.valid, a_first_1)
node _T_1650 = and(_T_1649, UInt<1>(0h1))
when _T_1650 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1651 = and(io.in.a.ready, io.in.a.valid)
node _T_1652 = and(_T_1651, a_first_1)
node _T_1653 = and(_T_1652, UInt<1>(0h1))
when _T_1653 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1654 = dshr(inflight, io.in.a.bits.source)
node _T_1655 = bits(_T_1654, 0, 0)
node _T_1656 = eq(_T_1655, UInt<1>(0h0))
node _T_1657 = asUInt(reset)
node _T_1658 = eq(_T_1657, UInt<1>(0h0))
when _T_1658 :
node _T_1659 = eq(_T_1656, UInt<1>(0h0))
when _T_1659 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1656, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<257>
connect d_clr, UInt<257>(0h0)
wire d_clr_wo_ready : UInt<257>
connect d_clr_wo_ready, UInt<257>(0h0)
wire d_opcodes_clr : UInt<1028>
connect d_opcodes_clr, UInt<1028>(0h0)
wire d_sizes_clr : UInt<2056>
connect d_sizes_clr, UInt<2056>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1660 = and(io.in.d.valid, d_first_1)
node _T_1661 = and(_T_1660, UInt<1>(0h1))
node _T_1662 = eq(d_release_ack, UInt<1>(0h0))
node _T_1663 = and(_T_1661, _T_1662)
when _T_1663 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1664 = and(io.in.d.ready, io.in.d.valid)
node _T_1665 = and(_T_1664, d_first_1)
node _T_1666 = and(_T_1665, UInt<1>(0h1))
node _T_1667 = eq(d_release_ack, UInt<1>(0h0))
node _T_1668 = and(_T_1666, _T_1667)
when _T_1668 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1669 = and(io.in.d.valid, d_first_1)
node _T_1670 = and(_T_1669, UInt<1>(0h1))
node _T_1671 = eq(d_release_ack, UInt<1>(0h0))
node _T_1672 = and(_T_1670, _T_1671)
when _T_1672 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1673 = dshr(inflight, io.in.d.bits.source)
node _T_1674 = bits(_T_1673, 0, 0)
node _T_1675 = or(_T_1674, same_cycle_resp)
node _T_1676 = asUInt(reset)
node _T_1677 = eq(_T_1676, UInt<1>(0h0))
when _T_1677 :
node _T_1678 = eq(_T_1675, UInt<1>(0h0))
when _T_1678 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1675, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1679 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1680 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1681 = or(_T_1679, _T_1680)
node _T_1682 = asUInt(reset)
node _T_1683 = eq(_T_1682, UInt<1>(0h0))
when _T_1683 :
node _T_1684 = eq(_T_1681, UInt<1>(0h0))
when _T_1684 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1681, UInt<1>(0h1), "") : assert_100
node _T_1685 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1686 = asUInt(reset)
node _T_1687 = eq(_T_1686, UInt<1>(0h0))
when _T_1687 :
node _T_1688 = eq(_T_1685, UInt<1>(0h0))
when _T_1688 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1685, UInt<1>(0h1), "") : assert_101
else :
node _T_1689 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1690 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1691 = or(_T_1689, _T_1690)
node _T_1692 = asUInt(reset)
node _T_1693 = eq(_T_1692, UInt<1>(0h0))
when _T_1693 :
node _T_1694 = eq(_T_1691, UInt<1>(0h0))
when _T_1694 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1691, UInt<1>(0h1), "") : assert_102
node _T_1695 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1696 = asUInt(reset)
node _T_1697 = eq(_T_1696, UInt<1>(0h0))
when _T_1697 :
node _T_1698 = eq(_T_1695, UInt<1>(0h0))
when _T_1698 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1695, UInt<1>(0h1), "") : assert_103
node _T_1699 = and(io.in.d.valid, d_first_1)
node _T_1700 = and(_T_1699, a_first_1)
node _T_1701 = and(_T_1700, io.in.a.valid)
node _T_1702 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1703 = and(_T_1701, _T_1702)
node _T_1704 = eq(d_release_ack, UInt<1>(0h0))
node _T_1705 = and(_T_1703, _T_1704)
when _T_1705 :
node _T_1706 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1707 = or(_T_1706, io.in.a.ready)
node _T_1708 = asUInt(reset)
node _T_1709 = eq(_T_1708, UInt<1>(0h0))
when _T_1709 :
node _T_1710 = eq(_T_1707, UInt<1>(0h0))
when _T_1710 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1707, UInt<1>(0h1), "") : assert_104
node _T_1711 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1712 = orr(a_set_wo_ready)
node _T_1713 = eq(_T_1712, UInt<1>(0h0))
node _T_1714 = or(_T_1711, _T_1713)
node _T_1715 = asUInt(reset)
node _T_1716 = eq(_T_1715, UInt<1>(0h0))
when _T_1716 :
node _T_1717 = eq(_T_1714, UInt<1>(0h0))
when _T_1717 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1714, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_40
node _T_1718 = orr(inflight)
node _T_1719 = eq(_T_1718, UInt<1>(0h0))
node _T_1720 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1721 = or(_T_1719, _T_1720)
node _T_1722 = lt(watchdog, plusarg_reader.out)
node _T_1723 = or(_T_1721, _T_1722)
node _T_1724 = asUInt(reset)
node _T_1725 = eq(_T_1724, UInt<1>(0h0))
when _T_1725 :
node _T_1726 = eq(_T_1723, UInt<1>(0h0))
when _T_1726 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1723, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1727 = and(io.in.a.ready, io.in.a.valid)
node _T_1728 = and(io.in.d.ready, io.in.d.valid)
node _T_1729 = or(_T_1727, _T_1728)
when _T_1729 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<257>, clock, reset, UInt<257>(0h0)
regreset inflight_opcodes_1 : UInt<1028>, clock, reset, UInt<1028>(0h0)
regreset inflight_sizes_1 : UInt<2056>, clock, reset, UInt<2056>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<9>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<9>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<257>
connect c_set, UInt<257>(0h0)
wire c_set_wo_ready : UInt<257>
connect c_set_wo_ready, UInt<257>(0h0)
wire c_opcodes_set : UInt<1028>
connect c_opcodes_set, UInt<1028>(0h0)
wire c_sizes_set : UInt<2056>
connect c_sizes_set, UInt<2056>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<9>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1730 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<9>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1731 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1732 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1733 = and(_T_1731, _T_1732)
node _T_1734 = and(_T_1730, _T_1733)
when _T_1734 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<9>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<9>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1735 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1736 = and(_T_1735, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<9>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1737 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1738 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1739 = and(_T_1737, _T_1738)
node _T_1740 = and(_T_1736, _T_1739)
when _T_1740 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<9>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<9>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<9>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<9>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<9>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<9>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1741 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1742 = bits(_T_1741, 0, 0)
node _T_1743 = eq(_T_1742, UInt<1>(0h0))
node _T_1744 = asUInt(reset)
node _T_1745 = eq(_T_1744, UInt<1>(0h0))
when _T_1745 :
node _T_1746 = eq(_T_1743, UInt<1>(0h0))
when _T_1746 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1743, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<9>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<9>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<257>
connect d_clr_1, UInt<257>(0h0)
wire d_clr_wo_ready_1 : UInt<257>
connect d_clr_wo_ready_1, UInt<257>(0h0)
wire d_opcodes_clr_1 : UInt<1028>
connect d_opcodes_clr_1, UInt<1028>(0h0)
wire d_sizes_clr_1 : UInt<2056>
connect d_sizes_clr_1, UInt<2056>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1747 = and(io.in.d.valid, d_first_2)
node _T_1748 = and(_T_1747, UInt<1>(0h1))
node _T_1749 = and(_T_1748, d_release_ack_1)
when _T_1749 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1750 = and(io.in.d.ready, io.in.d.valid)
node _T_1751 = and(_T_1750, d_first_2)
node _T_1752 = and(_T_1751, UInt<1>(0h1))
node _T_1753 = and(_T_1752, d_release_ack_1)
when _T_1753 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1754 = and(io.in.d.valid, d_first_2)
node _T_1755 = and(_T_1754, UInt<1>(0h1))
node _T_1756 = and(_T_1755, d_release_ack_1)
when _T_1756 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<9>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1757 = dshr(inflight_1, io.in.d.bits.source)
node _T_1758 = bits(_T_1757, 0, 0)
node _T_1759 = or(_T_1758, same_cycle_resp_1)
node _T_1760 = asUInt(reset)
node _T_1761 = eq(_T_1760, UInt<1>(0h0))
when _T_1761 :
node _T_1762 = eq(_T_1759, UInt<1>(0h0))
when _T_1762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1759, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<9>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1763 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1764 = asUInt(reset)
node _T_1765 = eq(_T_1764, UInt<1>(0h0))
when _T_1765 :
node _T_1766 = eq(_T_1763, UInt<1>(0h0))
when _T_1766 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1763, UInt<1>(0h1), "") : assert_109
else :
node _T_1767 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1768 = asUInt(reset)
node _T_1769 = eq(_T_1768, UInt<1>(0h0))
when _T_1769 :
node _T_1770 = eq(_T_1767, UInt<1>(0h0))
when _T_1770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1767, UInt<1>(0h1), "") : assert_110
node _T_1771 = and(io.in.d.valid, d_first_2)
node _T_1772 = and(_T_1771, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<9>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1773 = and(_T_1772, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<9>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1774 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1775 = and(_T_1773, _T_1774)
node _T_1776 = and(_T_1775, d_release_ack_1)
node _T_1777 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1778 = and(_T_1776, _T_1777)
when _T_1778 :
node _T_1779 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<9>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1780 = or(_T_1779, _WIRE_27.ready)
node _T_1781 = asUInt(reset)
node _T_1782 = eq(_T_1781, UInt<1>(0h0))
when _T_1782 :
node _T_1783 = eq(_T_1780, UInt<1>(0h0))
when _T_1783 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1780, UInt<1>(0h1), "") : assert_111
node _T_1784 = orr(c_set_wo_ready)
when _T_1784 :
node _T_1785 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1786 = asUInt(reset)
node _T_1787 = eq(_T_1786, UInt<1>(0h0))
when _T_1787 :
node _T_1788 = eq(_T_1785, UInt<1>(0h0))
when _T_1788 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1785, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_41
node _T_1789 = orr(inflight_1)
node _T_1790 = eq(_T_1789, UInt<1>(0h0))
node _T_1791 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1792 = or(_T_1790, _T_1791)
node _T_1793 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1794 = or(_T_1792, _T_1793)
node _T_1795 = asUInt(reset)
node _T_1796 = eq(_T_1795, UInt<1>(0h0))
when _T_1796 :
node _T_1797 = eq(_T_1794, UInt<1>(0h0))
when _T_1797 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1794, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<9>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1798 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1799 = and(io.in.d.ready, io.in.d.valid)
node _T_1800 = or(_T_1798, _T_1799)
when _T_1800 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_20( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [8:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [8:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [8:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] _c_first_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire [8:0] _c_set_wo_ready_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_wo_ready_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_4_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_5_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [4099:0] _c_sizes_set_T_1 = 4100'h0; // @[Monitor.scala:768:52]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_opcodes_set_T = 12'h0; // @[Monitor.scala:767:79]
wire [11:0] _c_sizes_set_T = 12'h0; // @[Monitor.scala:768:77]
wire [4098:0] _c_opcodes_set_T_1 = 4099'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [511:0] _c_set_wo_ready_T = 512'h1; // @[OneHot.scala:58:35]
wire [511:0] _c_set_T = 512'h1; // @[OneHot.scala:58:35]
wire [2055:0] c_sizes_set = 2056'h0; // @[Monitor.scala:741:34]
wire [1027:0] c_opcodes_set = 1028'h0; // @[Monitor.scala:740:34]
wire [256:0] c_set = 257'h0; // @[Monitor.scala:738:34]
wire [256:0] c_set_wo_ready = 257'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [8:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 9'h90; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [6:0] _source_ok_T_1 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_7 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_13 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_19 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 7'h20; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 7'h21; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 7'h22; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 7'h23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_25 = io_in_a_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_31 = io_in_a_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 9'hA0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 9'hA1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 9'hA2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = io_in_a_bits_source_0 == 9'h100; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_4 = _uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_5 = _uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_10 = _uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_11 = _uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_16 = _uncommonBits_T_16[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_17 = _uncommonBits_T_17[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_22 = _uncommonBits_T_22[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_23 = _uncommonBits_T_23[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_28 = _uncommonBits_T_28[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_29 = _uncommonBits_T_29[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_34 = _uncommonBits_T_34[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_35 = _uncommonBits_T_35[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_40 = _uncommonBits_T_40[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_41 = _uncommonBits_T_41[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_46 = _uncommonBits_T_46[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_47 = _uncommonBits_T_47[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_52 = _uncommonBits_T_52[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_53 = _uncommonBits_T_53[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_58 = _uncommonBits_T_58[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_59 = _uncommonBits_T_59[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_64 = _uncommonBits_T_64[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_65 = _uncommonBits_T_65[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = io_in_d_bits_source_0 == 9'h90; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [6:0] _source_ok_T_51 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_57 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_63 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_69 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_52 = _source_ok_T_51 == 7'h20; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_58 = _source_ok_T_57 == 7'h21; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_64 = _source_ok_T_63 == 7'h22; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_70 = _source_ok_T_69 == 7'h23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_75 = io_in_d_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_81 = io_in_d_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire _source_ok_T_76 = _source_ok_T_75 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_80; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_82 = _source_ok_T_81 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_86; // @[Parameters.scala:1138:31]
wire _source_ok_T_87 = io_in_d_bits_source_0 == 9'hA0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_87; // @[Parameters.scala:1138:31]
wire _source_ok_T_88 = io_in_d_bits_source_0 == 9'hA1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 9'hA2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire _source_ok_T_90 = io_in_d_bits_source_0 == 9'h100; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1727 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1727; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1727; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [8:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1800 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1800; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1800; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1800; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [8:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [256:0] inflight; // @[Monitor.scala:614:27]
reg [1027:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [2055:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [256:0] a_set; // @[Monitor.scala:626:34]
wire [256:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [1027:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [2055:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [11:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [11:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [11:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [11:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [11:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [1027:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [1027:0] _a_opcode_lookup_T_6 = {1024'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [1027:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [11:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [11:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [11:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [11:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [11:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [2055:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [2055:0] _a_size_lookup_T_6 = {2048'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [2055:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[2055:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [511:0] _GEN_3 = 512'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [511:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [511:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1653 = _T_1727 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1653 ? _a_set_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1653 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1653 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [11:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [4098:0] _a_opcodes_set_T_1 = {4095'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1653 ? _a_opcodes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [11:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [4099:0] _a_sizes_set_T_1 = {4095'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1653 ? _a_sizes_set_T_1[2055:0] : 2056'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [256:0] d_clr; // @[Monitor.scala:664:34]
wire [256:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [1027:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [2055:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1699 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [511:0] _GEN_5 = 512'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1699 & ~d_release_ack ? _d_clr_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1668 = _T_1800 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1668 ? _d_clr_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [4110:0] _d_opcodes_clr_T_5 = 4111'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1668 ? _d_opcodes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [4110:0] _d_sizes_clr_T_5 = 4111'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1668 ? _d_sizes_clr_T_5[2055:0] : 2056'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [256:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [256:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [256:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [1027:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [1027:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [1027:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [2055:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [2055:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [2055:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [256:0] inflight_1; // @[Monitor.scala:726:35]
wire [256:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [1027:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [1027:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [2055:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [2055:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [1027:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [1027:0] _c_opcode_lookup_T_6 = {1024'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [1027:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [2055:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [2055:0] _c_size_lookup_T_6 = {2048'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [2055:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[2055:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [256:0] d_clr_1; // @[Monitor.scala:774:34]
wire [256:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [1027:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [2055:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1771 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1771 & d_release_ack_1 ? _d_clr_wo_ready_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1753 = _T_1800 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1753 ? _d_clr_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [4110:0] _d_opcodes_clr_T_11 = 4111'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1753 ? _d_opcodes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [4110:0] _d_sizes_clr_T_11 = 4111'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1753 ? _d_sizes_clr_T_11[2055:0] : 2056'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 9'h0; // @[Monitor.scala:36:7, :795:113]
wire [256:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [256:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [1027:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [1027:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [2055:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [2055:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_10 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0)
node _source_ok_T = shr(io.in.a.bits.source, 11)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits = bits(_uncommonBits_T, 10, 0)
node _T_4 = shr(io.in.a.bits.source, 11)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<11>(0h40f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0)
node _T_24 = shr(io.in.a.bits.source, 11)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0)
node _T_86 = shr(io.in.a.bits.source, 11)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0)
node _T_152 = shr(io.in.a.bits.source, 11)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0)
node _T_199 = shr(io.in.a.bits.source, 11)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0)
node _T_240 = shr(io.in.a.bits.source, 11)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0)
node _T_283 = shr(io.in.a.bits.source, 11)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0)
node _T_321 = shr(io.in.a.bits.source, 11)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0)
node _T_359 = shr(io.in.a.bits.source, 11)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 11)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<13>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<13>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1040>
connect a_set, UInt<1040>(0h0)
wire a_set_wo_ready : UInt<1040>
connect a_set_wo_ready, UInt<1040>(0h0)
wire a_opcodes_set : UInt<4160>
connect a_opcodes_set, UInt<4160>(0h0)
wire a_sizes_set : UInt<4160>
connect a_sizes_set, UInt<4160>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1040>
connect d_clr, UInt<1040>(0h0)
wire d_clr_wo_ready : UInt<1040>
connect d_clr_wo_ready, UInt<1040>(0h0)
wire d_opcodes_clr : UInt<4160>
connect d_opcodes_clr, UInt<4160>(0h0)
wire d_sizes_clr : UInt<4160>
connect d_sizes_clr, UInt<4160>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_20
node _T_656 = orr(inflight)
node _T_657 = eq(_T_656, UInt<1>(0h0))
node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_659 = or(_T_657, _T_658)
node _T_660 = lt(watchdog, plusarg_reader.out)
node _T_661 = or(_T_659, _T_660)
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_661, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_665 = and(io.in.a.ready, io.in.a.valid)
node _T_666 = and(io.in.d.ready, io.in.d.valid)
node _T_667 = or(_T_665, _T_666)
when _T_667 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<13>(0h0)
connect _c_first_WIRE.bits.source, UInt<11>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<13>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1040>
connect c_set, UInt<1040>(0h0)
wire c_set_wo_ready : UInt<1040>
connect c_set_wo_ready, UInt<1040>(0h0)
wire c_opcodes_set : UInt<4160>
connect c_opcodes_set, UInt<4160>(0h0)
wire c_sizes_set : UInt<4160>
connect c_sizes_set, UInt<4160>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<13>(0h0)
connect _WIRE_6.bits.source, UInt<11>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_668 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<13>(0h0)
connect _WIRE_8.bits.source, UInt<11>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_671 = and(_T_669, _T_670)
node _T_672 = and(_T_668, _T_671)
when _T_672 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<13>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<13>(0h0)
connect _WIRE_10.bits.source, UInt<11>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_674 = and(_T_673, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<13>(0h0)
connect _WIRE_12.bits.source, UInt<11>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_677 = and(_T_675, _T_676)
node _T_678 = and(_T_674, _T_677)
when _T_678 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<13>(0h0)
connect _c_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<13>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<13>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<13>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<13>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<13>(0h0)
connect _WIRE_14.bits.source, UInt<11>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_679 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_680 = bits(_T_679, 0, 0)
node _T_681 = eq(_T_680, UInt<1>(0h0))
node _T_682 = asUInt(reset)
node _T_683 = eq(_T_682, UInt<1>(0h0))
when _T_683 :
node _T_684 = eq(_T_681, UInt<1>(0h0))
when _T_684 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_681, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<13>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<13>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1040>
connect d_clr_1, UInt<1040>(0h0)
wire d_clr_wo_ready_1 : UInt<1040>
connect d_clr_wo_ready_1, UInt<1040>(0h0)
wire d_opcodes_clr_1 : UInt<4160>
connect d_opcodes_clr_1, UInt<4160>(0h0)
wire d_sizes_clr_1 : UInt<4160>
connect d_sizes_clr_1, UInt<4160>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_685 = and(io.in.d.valid, d_first_2)
node _T_686 = and(_T_685, UInt<1>(0h1))
node _T_687 = and(_T_686, d_release_ack_1)
when _T_687 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_688 = and(io.in.d.ready, io.in.d.valid)
node _T_689 = and(_T_688, d_first_2)
node _T_690 = and(_T_689, UInt<1>(0h1))
node _T_691 = and(_T_690, d_release_ack_1)
when _T_691 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<13>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<13>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<13>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_695 = dshr(inflight_1, io.in.d.bits.source)
node _T_696 = bits(_T_695, 0, 0)
node _T_697 = or(_T_696, same_cycle_resp_1)
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_697, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<13>(0h0)
connect _WIRE_16.bits.source, UInt<11>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_702 = asUInt(reset)
node _T_703 = eq(_T_702, UInt<1>(0h0))
when _T_703 :
node _T_704 = eq(_T_701, UInt<1>(0h0))
when _T_704 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_701, UInt<1>(0h1), "") : assert_108
else :
node _T_705 = eq(io.in.d.bits.size, c_size_lookup)
node _T_706 = asUInt(reset)
node _T_707 = eq(_T_706, UInt<1>(0h0))
when _T_707 :
node _T_708 = eq(_T_705, UInt<1>(0h0))
when _T_708 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_705, UInt<1>(0h1), "") : assert_109
node _T_709 = and(io.in.d.valid, d_first_2)
node _T_710 = and(_T_709, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<13>(0h0)
connect _WIRE_18.bits.source, UInt<11>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_711 = and(_T_710, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<13>(0h0)
connect _WIRE_20.bits.source, UInt<11>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_713 = and(_T_711, _T_712)
node _T_714 = and(_T_713, d_release_ack_1)
node _T_715 = eq(c_probe_ack, UInt<1>(0h0))
node _T_716 = and(_T_714, _T_715)
when _T_716 :
node _T_717 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<13>(0h0)
connect _WIRE_22.bits.source, UInt<11>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_718 = or(_T_717, _WIRE_23.ready)
node _T_719 = asUInt(reset)
node _T_720 = eq(_T_719, UInt<1>(0h0))
when _T_720 :
node _T_721 = eq(_T_718, UInt<1>(0h0))
when _T_721 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_718, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_21
node _T_722 = orr(inflight_1)
node _T_723 = eq(_T_722, UInt<1>(0h0))
node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_725 = or(_T_723, _T_724)
node _T_726 = lt(watchdog_1, plusarg_reader_1.out)
node _T_727 = or(_T_725, _T_726)
node _T_728 = asUInt(reset)
node _T_729 = eq(_T_728, UInt<1>(0h0))
when _T_729 :
node _T_730 = eq(_T_727, UInt<1>(0h0))
when _T_730 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_727, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<13>(0h0)
connect _WIRE_24.bits.source, UInt<11>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_732 = and(io.in.d.ready, io.in.d.valid)
node _T_733 = or(_T_731, _T_732)
when _T_733 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_10( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [12:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [12:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module PE_18 :
input clock : Clock
input reset : Reset
output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>}
node _reg_T = eq(io.dir, UInt<1>(0h0))
node _reg_T_1 = mux(_reg_T, io.inR, io.inD)
reg reg : SInt<8>, clock
when io.en :
connect reg, _reg_T_1
connect io.outU, reg
connect io.outL, reg | module PE_18( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_62 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], credit_return : UInt<2>, vc_free : UInt<2>}}
wire _in_flight_WIRE : UInt<1>[2]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
regreset in_flight : UInt<1>[2], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_8 = and(_T_6, _T_7)
node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_10 = and(_T_8, _T_9)
node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_12 = and(_T_10, _T_11)
node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_19 = and(_T_17, _T_18)
node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_24 = and(_T_22, _T_23)
node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_26 = and(_T_24, _T_25)
node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_29 = and(_T_27, _T_28)
node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_33 = and(_T_31, _T_32)
node _T_34 = or(_T_12, _T_19)
node _T_35 = or(_T_34, _T_26)
node _T_36 = or(_T_35, _T_33)
node _T_37 = or(_T_5, _T_36)
node _T_38 = asUInt(reset)
node _T_39 = eq(_T_38, UInt<1>(0h0))
when _T_39 :
node _T_40 = eq(_T_37, UInt<1>(0h0))
when _T_40 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_37, UInt<1>(0h1), "") : assert_1
node _T_41 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_42 = or(_T_41, UInt<1>(0h0))
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_42, UInt<1>(0h1), "") : assert_2 | module NoCMonitor_62( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26] |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s1k3z4u :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_65
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a32d64s1k3z4u
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a32d64s1k3z4u
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits.sink, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_10.bits.sink, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLBuffer_a32d64s1k3z4u( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_a_bits_source = 1'h0; // @[Decoupled.scala:362:21]
wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_bits_source = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire [2:0] auto_in_a_bits_param = 3'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_a_bits_param = 3'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
TLMonitor_65 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d64s1k3z4u nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d64s1k3z4u nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e11_s53_7 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>}
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_7
connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc
connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc
connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig
connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp
connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign
connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module RoundRawFNToRecFN_e11_s53_7( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [12:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [55:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [12:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [55:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_7 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_infiniteExc (io_infiniteExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_128 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_149
connect io_out_source_valid_0.clock, clock
connect io_out_source_valid_0.reset, reset
connect io_out_source_valid_0.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid_0.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_128( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_149 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_35 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[5], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>}
regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock
wire next_valid : UInt<1>
connect next_valid, slot_valid
wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop_out, slot_uop
node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T)
connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1
wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop, next_uop_out
node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _killed_T_1 = neq(_killed_T, UInt<1>(0h0))
node killed = or(_killed_T_1, io.kill)
connect io.valid, slot_valid
connect io.out_uop, next_uop
node _io_will_be_valid_T = eq(killed, UInt<1>(0h0))
node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T)
connect io.will_be_valid, _io_will_be_valid_T_1
when io.kill :
connect slot_valid, UInt<1>(0h0)
else :
when io.in_uop.valid :
connect slot_valid, UInt<1>(0h1)
else :
when io.clear :
connect slot_valid, UInt<1>(0h0)
else :
node _slot_valid_T = eq(killed, UInt<1>(0h0))
node _slot_valid_T_1 = and(next_valid, _slot_valid_T)
connect slot_valid, _slot_valid_T_1
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T = eq(slot_valid, UInt<1>(0h0))
node _T_1 = or(_T, io.clear)
node _T_2 = or(_T_1, io.kill)
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid || io.clear || io.kill)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
else :
connect slot_uop, next_uop
connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p1_speculative_child, UInt<1>(0h0)
connect next_uop.iw_p2_speculative_child, UInt<1>(0h0)
wire rebusied_prs1 : UInt<1>
connect rebusied_prs1, UInt<1>(0h0)
wire rebusied_prs2 : UInt<1>
connect rebusied_prs2, UInt<1>(0h0)
node rebusied = or(rebusied_prs1, rebusied_prs2)
node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs1)
node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs2)
node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs3)
node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0)
node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1)
node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2)
node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3)
node prs1_wakeups_4 = and(io.wakeup_ports[4].valid, prs1_matches_4)
node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0)
node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1)
node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2)
node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3)
node prs2_wakeups_4 = and(io.wakeup_ports[4].valid, prs2_matches_4)
node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0)
node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1)
node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2)
node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3)
node prs3_wakeups_4 = and(io.wakeup_ports[4].valid, prs3_matches_4)
node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0)
node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1)
node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2)
node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3)
node prs1_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs1_matches_4)
node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0)
node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1)
node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2)
node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3)
node prs2_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs2_matches_4)
node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1)
node _T_7 = or(_T_6, prs1_wakeups_2)
node _T_8 = or(_T_7, prs1_wakeups_3)
node _T_9 = or(_T_8, prs1_wakeups_4)
when _T_9 :
connect next_uop.prs1_busy, UInt<1>(0h0)
node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_5 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1)
node _next_uop_iw_p1_speculative_child_T_6 = or(_next_uop_iw_p1_speculative_child_T_5, _next_uop_iw_p1_speculative_child_T_2)
node _next_uop_iw_p1_speculative_child_T_7 = or(_next_uop_iw_p1_speculative_child_T_6, _next_uop_iw_p1_speculative_child_T_3)
node _next_uop_iw_p1_speculative_child_T_8 = or(_next_uop_iw_p1_speculative_child_T_7, _next_uop_iw_p1_speculative_child_T_4)
wire _next_uop_iw_p1_speculative_child_WIRE : UInt<3>
connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_8
connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE
node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_5 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1)
node _next_uop_iw_p1_bypass_hint_T_6 = or(_next_uop_iw_p1_bypass_hint_T_5, _next_uop_iw_p1_bypass_hint_T_2)
node _next_uop_iw_p1_bypass_hint_T_7 = or(_next_uop_iw_p1_bypass_hint_T_6, _next_uop_iw_p1_bypass_hint_T_3)
node _next_uop_iw_p1_bypass_hint_T_8 = or(_next_uop_iw_p1_bypass_hint_T_7, _next_uop_iw_p1_bypass_hint_T_4)
wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_8
connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE
node _T_10 = or(prs1_rebusys_0, prs1_rebusys_1)
node _T_11 = or(_T_10, prs1_rebusys_2)
node _T_12 = or(_T_11, prs1_rebusys_3)
node _T_13 = or(_T_12, prs1_rebusys_4)
node _T_14 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child)
node _T_15 = neq(_T_14, UInt<1>(0h0))
node _T_16 = or(_T_13, _T_15)
node _T_17 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0))
node _T_18 = and(_T_16, _T_17)
when _T_18 :
connect next_uop.prs1_busy, UInt<1>(0h1)
connect rebusied_prs1, UInt<1>(0h1)
node _T_19 = or(prs2_wakeups_0, prs2_wakeups_1)
node _T_20 = or(_T_19, prs2_wakeups_2)
node _T_21 = or(_T_20, prs2_wakeups_3)
node _T_22 = or(_T_21, prs2_wakeups_4)
when _T_22 :
connect next_uop.prs2_busy, UInt<1>(0h0)
node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_5 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1)
node _next_uop_iw_p2_speculative_child_T_6 = or(_next_uop_iw_p2_speculative_child_T_5, _next_uop_iw_p2_speculative_child_T_2)
node _next_uop_iw_p2_speculative_child_T_7 = or(_next_uop_iw_p2_speculative_child_T_6, _next_uop_iw_p2_speculative_child_T_3)
node _next_uop_iw_p2_speculative_child_T_8 = or(_next_uop_iw_p2_speculative_child_T_7, _next_uop_iw_p2_speculative_child_T_4)
wire _next_uop_iw_p2_speculative_child_WIRE : UInt<3>
connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_8
connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE
node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_5 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1)
node _next_uop_iw_p2_bypass_hint_T_6 = or(_next_uop_iw_p2_bypass_hint_T_5, _next_uop_iw_p2_bypass_hint_T_2)
node _next_uop_iw_p2_bypass_hint_T_7 = or(_next_uop_iw_p2_bypass_hint_T_6, _next_uop_iw_p2_bypass_hint_T_3)
node _next_uop_iw_p2_bypass_hint_T_8 = or(_next_uop_iw_p2_bypass_hint_T_7, _next_uop_iw_p2_bypass_hint_T_4)
wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_8
connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE
node _T_23 = or(prs2_rebusys_0, prs2_rebusys_1)
node _T_24 = or(_T_23, prs2_rebusys_2)
node _T_25 = or(_T_24, prs2_rebusys_3)
node _T_26 = or(_T_25, prs2_rebusys_4)
node _T_27 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child)
node _T_28 = neq(_T_27, UInt<1>(0h0))
node _T_29 = or(_T_26, _T_28)
node _T_30 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0))
node _T_31 = and(_T_29, _T_30)
when _T_31 :
connect next_uop.prs2_busy, UInt<1>(0h1)
connect rebusied_prs2, UInt<1>(0h1)
node _T_32 = or(prs3_wakeups_0, prs3_wakeups_1)
node _T_33 = or(_T_32, prs3_wakeups_2)
node _T_34 = or(_T_33, prs3_wakeups_3)
node _T_35 = or(_T_34, prs3_wakeups_4)
when _T_35 :
connect next_uop.prs3_busy, UInt<1>(0h0)
node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_2 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_3 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_4 = mux(prs3_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_5 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1)
node _next_uop_iw_p3_bypass_hint_T_6 = or(_next_uop_iw_p3_bypass_hint_T_5, _next_uop_iw_p3_bypass_hint_T_2)
node _next_uop_iw_p3_bypass_hint_T_7 = or(_next_uop_iw_p3_bypass_hint_T_6, _next_uop_iw_p3_bypass_hint_T_3)
node _next_uop_iw_p3_bypass_hint_T_8 = or(_next_uop_iw_p3_bypass_hint_T_7, _next_uop_iw_p3_bypass_hint_T_4)
wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_8
connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE
node _T_36 = eq(io.pred_wakeup_port.bits, slot_uop.ppred)
node _T_37 = and(io.pred_wakeup_port.valid, _T_36)
when _T_37 :
connect next_uop.ppred_busy, UInt<1>(0h0)
node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1)
node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0))
node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4)
node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h0))
node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0))
node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7)
node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T)
node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0))
node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3)
node agen_ready = and(_agen_ready_T_4, UInt<1>(0h1))
node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T)
node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0))
node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3)
node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h1))
node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0))
node _io_request_T_1 = and(slot_valid, _io_request_T)
node _io_request_T_2 = or(iss_ready, agen_ready)
node _io_request_T_3 = or(_io_request_T_2, dgen_ready)
node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3)
connect io.request, _io_request_T_4
connect io.iss_uop, slot_uop
connect next_uop.iw_issued, UInt<1>(0h0)
connect next_uop.iw_issued_partial_agen, UInt<1>(0h0)
connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0)
node _T_38 = eq(io.squash_grant, UInt<1>(0h0))
node _T_39 = and(io.grant, _T_38)
when _T_39 :
connect next_uop.iw_issued, UInt<1>(0h1)
node _T_40 = and(slot_uop.fu_code[1], slot_uop.fu_code[2])
when _T_40 :
when agen_ready :
node _T_41 = eq(io.squash_grant, UInt<1>(0h0))
node _T_42 = and(io.grant, _T_41)
when _T_42 :
connect next_uop.iw_issued_partial_agen, UInt<1>(0h1)
connect io.iss_uop.fu_code[1], UInt<1>(0h1)
connect io.iss_uop.fu_code[2], UInt<1>(0h0)
else :
node _T_43 = eq(io.squash_grant, UInt<1>(0h0))
node _T_44 = and(io.grant, _T_43)
when _T_44 :
connect next_uop.iw_issued_partial_dgen, UInt<1>(0h1)
connect io.iss_uop.fu_code[1], UInt<1>(0h0)
connect io.iss_uop.fu_code[2], UInt<1>(0h1)
connect io.iss_uop.imm_sel, UInt<3>(0h6)
connect io.iss_uop.prs1, slot_uop.prs2
connect io.iss_uop.lrs1_rtype, slot_uop.lrs2_rtype
connect io.iss_uop.iw_p1_bypass_hint, slot_uop.iw_p2_bypass_hint
else :
when slot_uop.fu_code[2] :
connect io.iss_uop.imm_sel, UInt<3>(0h6)
connect io.iss_uop.prs1, slot_uop.prs2
connect io.iss_uop.lrs1_rtype, slot_uop.lrs2_rtype
connect io.iss_uop.iw_p1_bypass_hint, slot_uop.iw_p2_bypass_hint
connect io.iss_uop.lrs2_rtype, UInt<2>(0h2)
connect io.iss_uop.prs2, io.iss_uop.prs1
node _T_45 = and(slot_valid, slot_uop.iw_issued)
when _T_45 :
connect next_valid, rebusied
when slot_uop.iw_issued_partial_agen :
connect next_valid, UInt<1>(0h1)
node _T_46 = eq(rebusied_prs1, UInt<1>(0h0))
when _T_46 :
connect next_uop.fu_code[1], UInt<1>(0h0)
connect next_uop.fu_code[2], UInt<1>(0h1)
else :
when slot_uop.iw_issued_partial_dgen :
connect next_valid, UInt<1>(0h1)
node _T_47 = eq(rebusied_prs2, UInt<1>(0h0))
when _T_47 :
connect next_uop.fu_code[1], UInt<1>(0h1)
connect next_uop.fu_code[2], UInt<1>(0h0) | module IssueSlot_35( // @[issue-slot.scala:49:7]
input clock, // @[issue-slot.scala:49:7]
input reset, // @[issue-slot.scala:49:7]
output io_valid, // @[issue-slot.scala:52:14]
output io_will_be_valid, // @[issue-slot.scala:52:14]
output io_request, // @[issue-slot.scala:52:14]
input io_grant, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_amo, // @[issue-slot.scala:52:14]
output io_iss_uop_is_eret, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_iss_uop_taken, // @[issue-slot.scala:52:14]
output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14]
output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_iss_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14]
output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_iss_uop_is_unique, // @[issue-slot.scala:52:14]
output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_in_uop_valid, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:52:14]
input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:52:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_out_uop_is_fence, // @[issue-slot.scala:52:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_out_uop_is_amo, // @[issue-slot.scala:52:14]
output io_out_uop_is_eret, // @[issue-slot.scala:52:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_out_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_out_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_out_uop_taken, // @[issue-slot.scala:52:14]
output io_out_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_out_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_out_uop_is_unique, // @[issue-slot.scala:52:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_out_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14]
input io_kill, // @[issue-slot.scala:52:14]
input io_clear, // @[issue-slot.scala:52:14]
input io_squash_grant, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [2:0] io_child_rebusys // @[issue-slot.scala:52:14]
);
wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23]
wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_agen_0 = io_in_uop_bits_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_dgen_0 = io_in_uop_bits_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7]
wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91]
wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91]
wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131]
wire [1:0] io_iss_uop_lrs2_rtype = 2'h2; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7]
wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110]
wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7]
wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34]
wire _io_request_T_4; // @[issue-slot.scala:140:51]
wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs2_0 = io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28]
wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28]
wire next_uop_is_rvc; // @[issue-slot.scala:59:28]
wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_0; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_1; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_2; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_0; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_1; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_2; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_4; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_5; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_6; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_7; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_8; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_9; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_agen; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_dgen; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28]
wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28]
wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28]
wire next_uop_is_sfb; // @[issue-slot.scala:59:28]
wire next_uop_is_fence; // @[issue-slot.scala:59:28]
wire next_uop_is_fencei; // @[issue-slot.scala:59:28]
wire next_uop_is_sfence; // @[issue-slot.scala:59:28]
wire next_uop_is_amo; // @[issue-slot.scala:59:28]
wire next_uop_is_eret; // @[issue-slot.scala:59:28]
wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28]
wire next_uop_is_rocc; // @[issue-slot.scala:59:28]
wire next_uop_is_mov; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28]
wire next_uop_edge_inst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28]
wire next_uop_taken; // @[issue-slot.scala:59:28]
wire next_uop_imm_rename; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28]
wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28]
wire next_uop_prs1_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs2_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs3_busy; // @[issue-slot.scala:59:28]
wire next_uop_ppred_busy; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28]
wire next_uop_exception; // @[issue-slot.scala:59:28]
wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28]
wire next_uop_mem_signed; // @[issue-slot.scala:59:28]
wire next_uop_uses_ldq; // @[issue-slot.scala:59:28]
wire next_uop_uses_stq; // @[issue-slot.scala:59:28]
wire next_uop_is_unique; // @[issue-slot.scala:59:28]
wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28]
wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28]
wire next_uop_frs3_en; // @[issue-slot.scala:59:28]
wire next_uop_fcn_dw; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28]
wire next_uop_fp_val; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28]
wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_agen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_dgen_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_agen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_dgen_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_valid_0; // @[issue-slot.scala:49:7]
wire io_will_be_valid_0; // @[issue-slot.scala:49:7]
wire io_request_0; // @[issue-slot.scala:49:7]
reg slot_valid; // @[issue-slot.scala:55:27]
assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23]
reg slot_uop_is_rvc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21]
wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23]
reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23]
reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23]
reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23]
reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23]
reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23]
reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21]
wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23]
reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21]
wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23]
reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23]
reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23]
reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23]
reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23]
reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23]
reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23]
reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23]
reg slot_uop_iw_issued; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23]
reg slot_uop_iw_issued_partial_agen; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_partial_agen_0 = slot_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued_partial_agen = slot_uop_iw_issued_partial_agen; // @[util.scala:104:23]
reg slot_uop_iw_issued_partial_dgen; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_partial_dgen_0 = slot_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued_partial_dgen = slot_uop_iw_issued_partial_dgen; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23]
reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21]
wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23]
reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23]
reg slot_uop_is_sfb; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23]
reg slot_uop_is_fence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23]
reg slot_uop_is_fencei; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23]
reg slot_uop_is_sfence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23]
reg slot_uop_is_amo; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23]
reg slot_uop_is_eret; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23]
reg slot_uop_is_rocc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23]
reg slot_uop_is_mov; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23]
reg slot_uop_edge_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21]
assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23]
reg slot_uop_taken; // @[issue-slot.scala:56:21]
assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23]
reg slot_uop_imm_rename; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23]
reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21]
wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23]
reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21]
assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21]
wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23]
reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23]
reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21]
wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21]
wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23]
reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23]
reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23]
reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23]
reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23]
wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88]
wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95]
wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23]
reg slot_uop_exception; // @[issue-slot.scala:56:21]
assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21]
assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21]
wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23]
reg slot_uop_mem_signed; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23]
reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23]
reg slot_uop_uses_stq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23]
reg slot_uop_is_unique; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21]
assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23]
reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21]
wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21]
wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23]
reg slot_uop_frs3_en; // @[issue-slot.scala:56:21]
assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23]
reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23]
reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23]
reg slot_uop_fp_val; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23]
reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23]
wire next_valid; // @[issue-slot.scala:58:28]
assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23]
assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23]
assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23]
assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23]
assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23]
assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23]
assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23]
assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23]
assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23]
assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23]
assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23]
assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23]
assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23]
assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23]
assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23]
assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25]
assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23]
assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23]
assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23]
assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23]
assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23]
assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23]
assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23]
assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23]
assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23]
assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23]
assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23]
assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23]
assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23]
assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23]
assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23]
assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23]
assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23]
assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23]
assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23]
assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23]
assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23]
assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23]
assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23]
assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23]
assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23]
assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23]
assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23]
assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23]
assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23]
assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23]
assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23]
assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23]
assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23]
assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23]
assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23]
assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23]
assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23]
assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23]
assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23]
assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23]
assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23]
assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23]
assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23]
assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23]
assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23]
assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23]
assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23]
assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23]
assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23]
assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23]
assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23]
assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23]
assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23]
assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23]
assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23]
assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23]
assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23]
assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23]
assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23]
assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23]
assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23]
assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23]
assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23]
assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23]
assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23]
assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23]
assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23]
assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}]
assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_partial_agen_0 = next_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_partial_dgen_0 = next_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28]
wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51]
wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}]
wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61]
assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}]
assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34]
wire _slot_valid_T = ~killed; // @[util.scala:61:61]
wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}] |
Generate the Verilog code corresponding to this FIRRTL code module PE_427 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_171
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_427( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_171 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_207 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_207( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_7 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0)
node _source_ok_T = shr(io.in.a.bits.source, 11)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits = bits(_uncommonBits_T, 10, 0)
node _T_4 = shr(io.in.a.bits.source, 11)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<11>(0h40f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0)
node _T_24 = shr(io.in.a.bits.source, 11)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0)
node _T_86 = shr(io.in.a.bits.source, 11)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0)
node _T_152 = shr(io.in.a.bits.source, 11)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0)
node _T_199 = shr(io.in.a.bits.source, 11)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0)
node _T_240 = shr(io.in.a.bits.source, 11)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0)
node _T_283 = shr(io.in.a.bits.source, 11)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0)
node _T_321 = shr(io.in.a.bits.source, 11)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0)
node _T_359 = shr(io.in.a.bits.source, 11)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 11)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<13>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<13>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1040>
connect a_set, UInt<1040>(0h0)
wire a_set_wo_ready : UInt<1040>
connect a_set_wo_ready, UInt<1040>(0h0)
wire a_opcodes_set : UInt<4160>
connect a_opcodes_set, UInt<4160>(0h0)
wire a_sizes_set : UInt<4160>
connect a_sizes_set, UInt<4160>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1040>
connect d_clr, UInt<1040>(0h0)
wire d_clr_wo_ready : UInt<1040>
connect d_clr_wo_ready, UInt<1040>(0h0)
wire d_opcodes_clr : UInt<4160>
connect d_opcodes_clr, UInt<4160>(0h0)
wire d_sizes_clr : UInt<4160>
connect d_sizes_clr, UInt<4160>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_14
node _T_656 = orr(inflight)
node _T_657 = eq(_T_656, UInt<1>(0h0))
node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_659 = or(_T_657, _T_658)
node _T_660 = lt(watchdog, plusarg_reader.out)
node _T_661 = or(_T_659, _T_660)
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_661, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_665 = and(io.in.a.ready, io.in.a.valid)
node _T_666 = and(io.in.d.ready, io.in.d.valid)
node _T_667 = or(_T_665, _T_666)
when _T_667 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<13>(0h0)
connect _c_first_WIRE.bits.source, UInt<11>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<13>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1040>
connect c_set, UInt<1040>(0h0)
wire c_set_wo_ready : UInt<1040>
connect c_set_wo_ready, UInt<1040>(0h0)
wire c_opcodes_set : UInt<4160>
connect c_opcodes_set, UInt<4160>(0h0)
wire c_sizes_set : UInt<4160>
connect c_sizes_set, UInt<4160>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<13>(0h0)
connect _WIRE_6.bits.source, UInt<11>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_668 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<13>(0h0)
connect _WIRE_8.bits.source, UInt<11>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_671 = and(_T_669, _T_670)
node _T_672 = and(_T_668, _T_671)
when _T_672 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<13>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<13>(0h0)
connect _WIRE_10.bits.source, UInt<11>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_674 = and(_T_673, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<13>(0h0)
connect _WIRE_12.bits.source, UInt<11>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_677 = and(_T_675, _T_676)
node _T_678 = and(_T_674, _T_677)
when _T_678 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<13>(0h0)
connect _c_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<13>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<13>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<13>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<13>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<13>(0h0)
connect _WIRE_14.bits.source, UInt<11>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_679 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_680 = bits(_T_679, 0, 0)
node _T_681 = eq(_T_680, UInt<1>(0h0))
node _T_682 = asUInt(reset)
node _T_683 = eq(_T_682, UInt<1>(0h0))
when _T_683 :
node _T_684 = eq(_T_681, UInt<1>(0h0))
when _T_684 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_681, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<13>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<13>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1040>
connect d_clr_1, UInt<1040>(0h0)
wire d_clr_wo_ready_1 : UInt<1040>
connect d_clr_wo_ready_1, UInt<1040>(0h0)
wire d_opcodes_clr_1 : UInt<4160>
connect d_opcodes_clr_1, UInt<4160>(0h0)
wire d_sizes_clr_1 : UInt<4160>
connect d_sizes_clr_1, UInt<4160>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_685 = and(io.in.d.valid, d_first_2)
node _T_686 = and(_T_685, UInt<1>(0h1))
node _T_687 = and(_T_686, d_release_ack_1)
when _T_687 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_688 = and(io.in.d.ready, io.in.d.valid)
node _T_689 = and(_T_688, d_first_2)
node _T_690 = and(_T_689, UInt<1>(0h1))
node _T_691 = and(_T_690, d_release_ack_1)
when _T_691 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<13>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<13>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<13>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_695 = dshr(inflight_1, io.in.d.bits.source)
node _T_696 = bits(_T_695, 0, 0)
node _T_697 = or(_T_696, same_cycle_resp_1)
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_697, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<13>(0h0)
connect _WIRE_16.bits.source, UInt<11>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_702 = asUInt(reset)
node _T_703 = eq(_T_702, UInt<1>(0h0))
when _T_703 :
node _T_704 = eq(_T_701, UInt<1>(0h0))
when _T_704 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_701, UInt<1>(0h1), "") : assert_108
else :
node _T_705 = eq(io.in.d.bits.size, c_size_lookup)
node _T_706 = asUInt(reset)
node _T_707 = eq(_T_706, UInt<1>(0h0))
when _T_707 :
node _T_708 = eq(_T_705, UInt<1>(0h0))
when _T_708 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_705, UInt<1>(0h1), "") : assert_109
node _T_709 = and(io.in.d.valid, d_first_2)
node _T_710 = and(_T_709, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<13>(0h0)
connect _WIRE_18.bits.source, UInt<11>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_711 = and(_T_710, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<13>(0h0)
connect _WIRE_20.bits.source, UInt<11>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_713 = and(_T_711, _T_712)
node _T_714 = and(_T_713, d_release_ack_1)
node _T_715 = eq(c_probe_ack, UInt<1>(0h0))
node _T_716 = and(_T_714, _T_715)
when _T_716 :
node _T_717 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<13>(0h0)
connect _WIRE_22.bits.source, UInt<11>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_718 = or(_T_717, _WIRE_23.ready)
node _T_719 = asUInt(reset)
node _T_720 = eq(_T_719, UInt<1>(0h0))
when _T_720 :
node _T_721 = eq(_T_718, UInt<1>(0h0))
when _T_721 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_718, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_15
node _T_722 = orr(inflight_1)
node _T_723 = eq(_T_722, UInt<1>(0h0))
node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_725 = or(_T_723, _T_724)
node _T_726 = lt(watchdog_1, plusarg_reader_1.out)
node _T_727 = or(_T_725, _T_726)
node _T_728 = asUInt(reset)
node _T_729 = eq(_T_728, UInt<1>(0h0))
when _T_729 :
node _T_730 = eq(_T_727, UInt<1>(0h0))
when _T_730 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_727, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<13>(0h0)
connect _WIRE_24.bits.source, UInt<11>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_732 = and(io.in.d.ready, io.in.d.valid)
node _T_733 = or(_T_731, _T_732)
when _T_733 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_7( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [12:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [12:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_first_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_first_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_first_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_first_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_set_wo_ready_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_set_wo_ready_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_opcodes_set_interm_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_opcodes_set_interm_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_sizes_set_interm_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_sizes_set_interm_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_opcodes_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_opcodes_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_sizes_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_sizes_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_probe_ack_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_probe_ack_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_probe_ack_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_probe_ack_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _same_cycle_resp_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _same_cycle_resp_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _same_cycle_resp_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _same_cycle_resp_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _same_cycle_resp_WIRE_4_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _same_cycle_resp_WIRE_5_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52]
wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79]
wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77]
wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35]
wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35]
wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34]
wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34]
wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34]
wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [12:0] _is_aligned_T = {10'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 13'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_665; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [12:0] address; // @[Monitor.scala:391:22]
wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_733; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [1039:0] a_set; // @[Monitor.scala:626:34]
wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [1039:0] d_clr; // @[Monitor.scala:664:34]
wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [1039:0] d_clr_1; // @[Monitor.scala:774:34]
wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113]
wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_164 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_164( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x1_34 :
input clock : Clock
input reset : Reset
output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}}
wire nodeIn : UInt<1>[1]
invalidate nodeIn[0]
wire nodeOut : { sync : UInt<1>[1]}
invalidate nodeOut.sync[0]
connect auto.out, nodeOut
connect nodeIn, auto.in
inst reg of AsyncResetRegVec_w1_i0_34
connect reg.clock, clock
connect reg.reset, reset
connect reg.io.d, nodeIn[0]
connect reg.io.en, UInt<1>(0h1)
node _T = bits(reg.io.q, 0, 0)
connect nodeOut.sync[0], _T | module IntSyncCrossingSource_n1x1_34( // @[Crossing.scala:41:9]
input clock, // @[Crossing.scala:41:9]
input reset, // @[Crossing.scala:41:9]
input auto_in_0, // @[LazyModuleImp.scala:107:25]
output auto_out_sync_0 // @[LazyModuleImp.scala:107:25]
);
wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9]
wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9]
wire nodeOut_sync_0; // @[MixedNode.scala:542:17]
wire auto_out_sync_0_0; // @[Crossing.scala:41:9]
assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9]
AsyncResetRegVec_w1_i0_34 reg_0 ( // @[AsyncResetReg.scala:86:21]
.clock (clock),
.reset (reset),
.io_d (nodeIn_0), // @[MixedNode.scala:551:17]
.io_q (nodeOut_sync_0)
); // @[AsyncResetReg.scala:86:21]
assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_235 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_252
connect io_out_sink_valid.clock, clock
connect io_out_sink_valid.reset, reset
connect io_out_sink_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_235( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_252 io_out_sink_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_66 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_102
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_66( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_102 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_33 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_33( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLSlaveToNoC :
input clock : Clock
input reset : Reset
output io : { tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flits : { flip a : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}, b : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip c : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}, d : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip e : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}}
inst a of TLAFromNoC
connect a.clock, clock
connect a.reset, reset
inst b of TLBToNoC
connect b.clock, clock
connect b.reset, reset
inst c of TLCFromNoC
connect c.clock, clock
connect c.reset, reset
inst d of TLDToNoC
connect d.clock, clock
connect d.reset, reset
inst e of TLEFromNoC
connect e.clock, clock
connect e.reset, reset
connect io.tilelink.a.bits, a.io.protocol.bits
connect io.tilelink.a.valid, a.io.protocol.valid
connect a.io.protocol.ready, io.tilelink.a.ready
connect b.io.protocol, io.tilelink.b
connect io.tilelink.c.bits, c.io.protocol.bits
connect io.tilelink.c.valid, c.io.protocol.valid
connect c.io.protocol.ready, io.tilelink.c.ready
connect d.io.protocol, io.tilelink.d
connect io.tilelink.e.bits, e.io.protocol.bits
connect io.tilelink.e.valid, e.io.protocol.valid
connect e.io.protocol.ready, io.tilelink.e.ready
connect a.io.flit, io.flits.a
connect io.flits.b.bits, b.io.flit.bits
connect io.flits.b.valid, b.io.flit.valid
connect b.io.flit.ready, io.flits.b.ready
connect c.io.flit, io.flits.c
connect io.flits.d.bits, d.io.flit.bits
connect io.flits.d.valid, d.io.flit.valid
connect d.io.flit.ready, io.flits.d.ready
connect e.io.flit, io.flits.e | module TLSlaveToNoC( // @[Tilelink.scala:125:7]
input clock, // @[Tilelink.scala:125:7]
input reset, // @[Tilelink.scala:125:7]
input io_tilelink_a_ready, // @[Tilelink.scala:132:14]
output io_tilelink_a_valid, // @[Tilelink.scala:132:14]
output [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:132:14]
output [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:132:14]
output [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:132:14]
output [5:0] io_tilelink_a_bits_source, // @[Tilelink.scala:132:14]
output [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:132:14]
output [7:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:132:14]
output [63:0] io_tilelink_a_bits_data, // @[Tilelink.scala:132:14]
output io_tilelink_a_bits_corrupt, // @[Tilelink.scala:132:14]
output io_tilelink_d_ready, // @[Tilelink.scala:132:14]
input io_tilelink_d_valid, // @[Tilelink.scala:132:14]
input [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:132:14]
input [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:132:14]
input [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:132:14]
input [5:0] io_tilelink_d_bits_source, // @[Tilelink.scala:132:14]
input [4:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:132:14]
input io_tilelink_d_bits_denied, // @[Tilelink.scala:132:14]
input [63:0] io_tilelink_d_bits_data, // @[Tilelink.scala:132:14]
input io_tilelink_d_bits_corrupt, // @[Tilelink.scala:132:14]
output io_flits_a_ready, // @[Tilelink.scala:132:14]
input io_flits_a_valid, // @[Tilelink.scala:132:14]
input io_flits_a_bits_head, // @[Tilelink.scala:132:14]
input io_flits_a_bits_tail, // @[Tilelink.scala:132:14]
input [72:0] io_flits_a_bits_payload, // @[Tilelink.scala:132:14]
output io_flits_b_valid, // @[Tilelink.scala:132:14]
output io_flits_c_ready, // @[Tilelink.scala:132:14]
input io_flits_c_valid, // @[Tilelink.scala:132:14]
input io_flits_c_bits_head, // @[Tilelink.scala:132:14]
input io_flits_c_bits_tail, // @[Tilelink.scala:132:14]
input io_flits_d_ready, // @[Tilelink.scala:132:14]
output io_flits_d_valid, // @[Tilelink.scala:132:14]
output io_flits_d_bits_head, // @[Tilelink.scala:132:14]
output io_flits_d_bits_tail, // @[Tilelink.scala:132:14]
output [72:0] io_flits_d_bits_payload, // @[Tilelink.scala:132:14]
output [4:0] io_flits_d_bits_egress_id, // @[Tilelink.scala:132:14]
output io_flits_e_ready, // @[Tilelink.scala:132:14]
input io_flits_e_valid, // @[Tilelink.scala:132:14]
input io_flits_e_bits_head, // @[Tilelink.scala:132:14]
input io_flits_e_bits_tail // @[Tilelink.scala:132:14]
);
wire [64:0] _d_io_flit_bits_payload; // @[Tilelink.scala:146:17]
TLAFromNoC a ( // @[Tilelink.scala:143:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_a_ready),
.io_protocol_valid (io_tilelink_a_valid),
.io_protocol_bits_opcode (io_tilelink_a_bits_opcode),
.io_protocol_bits_param (io_tilelink_a_bits_param),
.io_protocol_bits_size (io_tilelink_a_bits_size),
.io_protocol_bits_source (io_tilelink_a_bits_source),
.io_protocol_bits_address (io_tilelink_a_bits_address),
.io_protocol_bits_mask (io_tilelink_a_bits_mask),
.io_protocol_bits_data (io_tilelink_a_bits_data),
.io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt),
.io_flit_ready (io_flits_a_ready),
.io_flit_valid (io_flits_a_valid),
.io_flit_bits_head (io_flits_a_bits_head),
.io_flit_bits_tail (io_flits_a_bits_tail),
.io_flit_bits_payload (io_flits_a_bits_payload)
); // @[Tilelink.scala:143:17]
TLBToNoC b ( // @[Tilelink.scala:144:17]
.clock (clock),
.reset (reset),
.io_flit_valid (io_flits_b_valid)
); // @[Tilelink.scala:144:17]
TLCFromNoC c ( // @[Tilelink.scala:145:17]
.clock (clock),
.reset (reset),
.io_flit_ready (io_flits_c_ready),
.io_flit_valid (io_flits_c_valid),
.io_flit_bits_head (io_flits_c_bits_head),
.io_flit_bits_tail (io_flits_c_bits_tail)
); // @[Tilelink.scala:145:17]
TLDToNoC d ( // @[Tilelink.scala:146:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_d_ready),
.io_protocol_valid (io_tilelink_d_valid),
.io_protocol_bits_opcode (io_tilelink_d_bits_opcode),
.io_protocol_bits_param (io_tilelink_d_bits_param),
.io_protocol_bits_size (io_tilelink_d_bits_size),
.io_protocol_bits_source (io_tilelink_d_bits_source),
.io_protocol_bits_sink (io_tilelink_d_bits_sink),
.io_protocol_bits_denied (io_tilelink_d_bits_denied),
.io_protocol_bits_data (io_tilelink_d_bits_data),
.io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt),
.io_flit_ready (io_flits_d_ready),
.io_flit_valid (io_flits_d_valid),
.io_flit_bits_head (io_flits_d_bits_head),
.io_flit_bits_tail (io_flits_d_bits_tail),
.io_flit_bits_payload (_d_io_flit_bits_payload),
.io_flit_bits_egress_id (io_flits_d_bits_egress_id)
); // @[Tilelink.scala:146:17]
TLEFromNoC e ( // @[Tilelink.scala:147:17]
.clock (clock),
.reset (reset),
.io_flit_ready (io_flits_e_ready),
.io_flit_valid (io_flits_e_valid),
.io_flit_bits_head (io_flits_e_bits_head),
.io_flit_bits_tail (io_flits_e_bits_tail)
); // @[Tilelink.scala:147:17]
assign io_flits_d_bits_payload = {8'h0, _d_io_flit_bits_payload}; // @[Tilelink.scala:125:7, :146:17, :157:14]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MSHR_7 :
input clock : Clock
input reset : Reset
output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<4>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<4>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<4>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<4>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<7>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}}
regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock
regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<4>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock
when meta_valid :
node _T = eq(meta.state, UInt<2>(0h0))
when _T :
node _T_1 = orr(meta.clients)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _T_6 = eq(meta.dirty, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = eq(meta.state, UInt<2>(0h1))
when _T_10 :
node _T_11 = eq(meta.dirty, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = eq(meta.state, UInt<2>(0h2))
when _T_15 :
node _T_16 = orr(meta.clients)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = sub(meta.clients, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = and(meta.clients, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4
assert(clock, _T_23, UInt<1>(0h1), "") : assert_4
node _T_27 = eq(meta.state, UInt<2>(0h3))
when _T_27 :
skip
regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1)
reg sink : UInt<3>, clock
reg gotT : UInt<1>, clock
reg bad_grant : UInt<1>, clock
reg probes_done : UInt<4>, clock
reg probes_toN : UInt<4>, clock
reg probes_noT : UInt<1>, clock
node _T_28 = neq(meta.state, UInt<2>(0h0))
node _T_29 = and(meta_valid, _T_28)
node _T_30 = eq(io.nestedwb.set, request.set)
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.nestedwb.tag, meta.tag)
node _T_33 = and(_T_31, _T_32)
when _T_33 :
when io.nestedwb.b_clr_dirty :
connect meta.dirty, UInt<1>(0h0)
when io.nestedwb.c_set_dirty :
connect meta.dirty, UInt<1>(0h1)
when io.nestedwb.b_toB :
connect meta.state, UInt<2>(0h1)
when io.nestedwb.b_toN :
connect meta.hit, UInt<1>(0h0)
connect io.status.valid, request_valid
connect io.status.bits.set, request.set
connect io.status.bits.tag, request.tag
connect io.status.bits.way, meta.way
node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0))
node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0))
node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2)
node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4)
node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6)
node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7)
connect io.status.bits.blockB, _io_status_bits_blockB_T_8
node _io_status_bits_nestB_T = and(meta_valid, w_releaseack)
node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast)
node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast)
node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3)
connect io.status.bits.nestB, _io_status_bits_nestB_T_4
node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0))
connect io.status.bits.blockC, _io_status_bits_blockC_T
node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1)
node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3)
node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4)
connect io.status.bits.nestC, _io_status_bits_nestC_T_5
node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0))
node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5
assert(clock, _T_36, UInt<1>(0h1), "") : assert_5
node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0))
node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6
assert(clock, _T_42, UInt<1>(0h1), "") : assert_6
node _no_wait_T = and(w_rprobeacklast, w_releaseack)
node _no_wait_T_1 = and(_no_wait_T, w_grantlast)
node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast)
node no_wait = and(_no_wait_T_2, w_grantack)
node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0))
node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release)
node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe)
connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2
node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1)
connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2
node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst)
node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst)
node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3)
connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4
node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0))
node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack)
node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant)
connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2
node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0))
node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst)
connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1
node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0))
node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack)
connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1
node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst)
node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait)
node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3)
connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4
connect io.schedule.bits.reload, no_wait
node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid)
node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid)
node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid)
node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid)
node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid)
node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid)
connect io.schedule.valid, _io_schedule_valid_T_5
when io.schedule.ready :
connect s_rprobe, UInt<1>(0h1)
when w_rprobeackfirst :
connect s_release, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
node _T_46 = and(s_release, s_pprobe)
when _T_46 :
connect s_acquire, UInt<1>(0h1)
when w_releaseack :
connect s_flush, UInt<1>(0h1)
when w_pprobeackfirst :
connect s_probeack, UInt<1>(0h1)
when w_grantfirst :
connect s_grantack, UInt<1>(0h1)
node _T_47 = and(w_pprobeack, w_grant)
when _T_47 :
connect s_execute, UInt<1>(0h1)
when no_wait :
connect s_writeback, UInt<1>(0h1)
when no_wait :
connect request_valid, UInt<1>(0h0)
connect meta_valid, UInt<1>(0h0)
wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<4>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}
connect final_meta_writeback, meta
node _req_clientBit_T = eq(request.source, UInt<7>(0h44))
node _req_clientBit_T_1 = eq(request.source, UInt<7>(0h40))
node _req_clientBit_uncommonBits_T = or(request.source, UInt<3>(0h0))
node req_clientBit_uncommonBits = bits(_req_clientBit_uncommonBits_T, 2, 0)
node _req_clientBit_T_2 = shr(request.source, 3)
node _req_clientBit_T_3 = eq(_req_clientBit_T_2, UInt<3>(0h6))
node _req_clientBit_T_4 = leq(UInt<1>(0h0), req_clientBit_uncommonBits)
node _req_clientBit_T_5 = and(_req_clientBit_T_3, _req_clientBit_T_4)
node _req_clientBit_T_6 = leq(req_clientBit_uncommonBits, UInt<3>(0h4))
node _req_clientBit_T_7 = and(_req_clientBit_T_5, _req_clientBit_T_6)
node _req_clientBit_uncommonBits_T_1 = or(request.source, UInt<3>(0h0))
node req_clientBit_uncommonBits_1 = bits(_req_clientBit_uncommonBits_T_1, 2, 0)
node _req_clientBit_T_8 = shr(request.source, 3)
node _req_clientBit_T_9 = eq(_req_clientBit_T_8, UInt<3>(0h4))
node _req_clientBit_T_10 = leq(UInt<1>(0h0), req_clientBit_uncommonBits_1)
node _req_clientBit_T_11 = and(_req_clientBit_T_9, _req_clientBit_T_10)
node _req_clientBit_T_12 = leq(req_clientBit_uncommonBits_1, UInt<3>(0h4))
node _req_clientBit_T_13 = and(_req_clientBit_T_11, _req_clientBit_T_12)
node req_clientBit_lo = cat(_req_clientBit_T_1, _req_clientBit_T)
node req_clientBit_hi = cat(_req_clientBit_T_13, _req_clientBit_T_7)
node req_clientBit = cat(req_clientBit_hi, req_clientBit_lo)
node _req_needT_T = bits(request.opcode, 2, 2)
node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0))
node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5))
node _req_needT_T_3 = eq(request.param, UInt<1>(0h1))
node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3)
node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4)
node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6))
node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7))
node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7)
node _req_needT_T_9 = neq(request.param, UInt<2>(0h0))
node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9)
node req_needT = or(_req_needT_T_5, _req_needT_T_10)
node _req_acquire_T = eq(request.opcode, UInt<3>(0h6))
node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7))
node req_acquire = or(_req_acquire_T, _req_acquire_T_1)
node _meta_no_clients_T = orr(meta.clients)
node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0))
node _req_promoteT_T = eq(meta.state, UInt<2>(0h3))
node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T)
node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT)
node req_promoteT = and(req_acquire, _req_promoteT_T_2)
node _T_48 = and(request.prio[2], UInt<1>(0h1))
when _T_48 :
node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0)
node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1
node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3))
node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2))
node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1)
node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state)
connect final_meta_writeback.state, _final_meta_writeback_state_T_3
node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1))
node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2))
node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1)
node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5))
node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3)
node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5)
node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7
connect final_meta_writeback.hit, UInt<1>(0h1)
else :
node _T_49 = and(request.control, UInt<1>(0h1))
when _T_49 :
when meta.hit :
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
node _final_meta_writeback_clients_T_8 = not(probes_toN)
node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9
connect final_meta_writeback.hit, UInt<1>(0h0)
else :
node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty)
node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2)
node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0))
node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5
node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0))
node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1))
node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire)
node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state)
node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1))
node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state)
node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11)
node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state)
node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13)
node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15)
node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16)
connect final_meta_writeback.state, _final_meta_writeback_state_T_17
node _final_meta_writeback_clients_T_10 = not(probes_toN)
node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10)
node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0))
node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14
connect final_meta_writeback.tag, request.tag
connect final_meta_writeback.hit, UInt<1>(0h1)
when bad_grant :
when meta.hit :
node _T_50 = eq(meta_valid, UInt<1>(0h0))
node _T_51 = eq(meta.state, UInt<2>(0h1))
node _T_52 = or(_T_50, _T_51)
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7
assert(clock, _T_52, UInt<1>(0h1), "") : assert_7
connect final_meta_writeback.hit, UInt<1>(0h1)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h1)
node _final_meta_writeback_clients_T_15 = not(probes_toN)
node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16
else :
connect final_meta_writeback.hit, UInt<1>(0h0)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
connect final_meta_writeback.clients, UInt<1>(0h0)
wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<4>, tag : UInt<13>}
connect invalid.dirty, UInt<1>(0h0)
connect invalid.state, UInt<2>(0h0)
connect invalid.clients, UInt<1>(0h0)
connect invalid.tag, UInt<1>(0h0)
node _honour_BtoT_T = and(meta.clients, req_clientBit)
node _honour_BtoT_T_1 = orr(_honour_BtoT_T)
node honour_BtoT = and(meta.hit, _honour_BtoT_T_1)
node _excluded_client_T = and(meta.hit, request.prio[0])
node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6))
node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7))
node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2)
node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4))
node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4)
node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5))
node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0))
node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7)
node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8)
node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0))
connect io.schedule.bits.a.bits.tag, request.tag
connect io.schedule.bits.a.bits.set, request.set
node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0))
connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1
node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6))
node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7))
node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2)
node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4)
connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5
connect io.schedule.bits.a.bits.source, UInt<1>(0h0)
node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1)
node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2)
connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3
node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag)
connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1
connect io.schedule.bits.b.bits.set, request.set
node _io_schedule_bits_b_bits_clients_T = not(excluded_client)
node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T)
connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1
node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6))
connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T
node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1))
node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1))
connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1
connect io.schedule.bits.c.bits.source, UInt<1>(0h0)
connect io.schedule.bits.c.bits.tag, meta.tag
connect io.schedule.bits.c.bits.set, request.set
connect io.schedule.bits.c.bits.way, meta.way
connect io.schedule.bits.c.bits.dirty, meta.dirty
connect io.schedule.bits.d.bits.set, request.set
connect io.schedule.bits.d.bits.put, request.put
connect io.schedule.bits.d.bits.offset, request.offset
connect io.schedule.bits.d.bits.tag, request.tag
connect io.schedule.bits.d.bits.source, request.source
connect io.schedule.bits.d.bits.size, request.size
connect io.schedule.bits.d.bits.param, request.param
connect io.schedule.bits.d.bits.opcode, request.opcode
connect io.schedule.bits.d.bits.control, request.control
connect io.schedule.bits.d.bits.prio, request.prio
node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0))
node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0))
node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param)
node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param)
node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param)
node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4)
node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param)
node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6)
node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8)
connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9
connect io.schedule.bits.d.bits.sink, UInt<1>(0h0)
connect io.schedule.bits.d.bits.way, meta.way
connect io.schedule.bits.d.bits.bad, bad_grant
connect io.schedule.bits.e.bits.sink, sink
connect io.schedule.bits.x.bits.fail, UInt<1>(0h0)
connect io.schedule.bits.dir.bits.set, request.set
connect io.schedule.bits.dir.bits.way, meta.way
node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0))
wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<4>, tag : UInt<13>}
connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag
connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients
connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state
connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty
node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE)
connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1
node _evict_T = eq(meta.hit, UInt<1>(0h0))
wire evict : UInt
connect evict, UInt<1>(0h0)
node evict_c = orr(meta.clients)
node _evict_T_1 = eq(UInt<2>(0h1), meta.state)
when _evict_T_1 :
node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1))
connect evict, _evict_out_T
else :
node _evict_T_2 = eq(UInt<2>(0h2), meta.state)
when _evict_T_2 :
node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect evict, _evict_out_T_1
else :
node _evict_T_3 = eq(UInt<2>(0h3), meta.state)
when _evict_T_3 :
node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3)
connect evict, _evict_out_T_4
else :
node _evict_T_4 = eq(UInt<2>(0h0), meta.state)
when _evict_T_4 :
connect evict, UInt<4>(0h8)
node _evict_T_5 = eq(_evict_T, UInt<1>(0h0))
when _evict_T_5 :
connect evict, UInt<4>(0h8)
wire before : UInt
connect before, UInt<1>(0h0)
node before_c = orr(meta.clients)
node _before_T = eq(UInt<2>(0h1), meta.state)
when _before_T :
node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1))
connect before, _before_out_T
else :
node _before_T_1 = eq(UInt<2>(0h2), meta.state)
when _before_T_1 :
node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect before, _before_out_T_1
else :
node _before_T_2 = eq(UInt<2>(0h3), meta.state)
when _before_T_2 :
node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3)
connect before, _before_out_T_4
else :
node _before_T_3 = eq(UInt<2>(0h0), meta.state)
when _before_T_3 :
connect before, UInt<4>(0h8)
node _before_T_4 = eq(meta.hit, UInt<1>(0h0))
when _before_T_4 :
connect before, UInt<4>(0h8)
wire after : UInt
connect after, UInt<1>(0h0)
node after_c = orr(final_meta_writeback.clients)
node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _after_T :
node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1))
connect after, _after_out_T
else :
node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _after_T_1 :
node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect after, _after_out_T_1
else :
node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _after_T_2 :
node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3)
connect after, _after_out_T_4
else :
node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _after_T_3 :
connect after, UInt<4>(0h8)
node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _after_T_4 :
connect after, UInt<4>(0h8)
node _T_56 = eq(s_release, UInt<1>(0h0))
node _T_57 = and(_T_56, w_rprobeackfirst)
node _T_58 = and(_T_57, io.schedule.ready)
when _T_58 :
node _T_59 = eq(evict, UInt<1>(0h1))
node _T_60 = eq(_T_59, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8
assert(clock, _T_60, UInt<1>(0h1), "") : assert_8
node _T_64 = eq(before, UInt<1>(0h1))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(evict, UInt<1>(0h0))
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10
assert(clock, _T_70, UInt<1>(0h1), "") : assert_10
node _T_74 = eq(before, UInt<1>(0h0))
node _T_75 = eq(_T_74, UInt<1>(0h0))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11
assert(clock, _T_75, UInt<1>(0h1), "") : assert_11
node _T_79 = eq(evict, UInt<3>(0h7))
node _T_80 = eq(before, UInt<3>(0h7))
node _T_81 = eq(evict, UInt<3>(0h5))
node _T_82 = eq(before, UInt<3>(0h5))
node _T_83 = eq(evict, UInt<3>(0h4))
node _T_84 = eq(before, UInt<3>(0h4))
node _T_85 = eq(evict, UInt<3>(0h6))
node _T_86 = eq(before, UInt<3>(0h6))
node _T_87 = eq(evict, UInt<2>(0h3))
node _T_88 = eq(before, UInt<2>(0h3))
node _T_89 = eq(evict, UInt<2>(0h2))
node _T_90 = eq(before, UInt<2>(0h2))
node _T_91 = eq(s_writeback, UInt<1>(0h0))
node _T_92 = and(_T_91, no_wait)
node _T_93 = and(_T_92, io.schedule.ready)
when _T_93 :
node _T_94 = eq(before, UInt<4>(0h8))
node _T_95 = eq(after, UInt<1>(0h1))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12
assert(clock, _T_97, UInt<1>(0h1), "") : assert_12
node _T_101 = eq(before, UInt<4>(0h8))
node _T_102 = eq(after, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13
assert(clock, _T_104, UInt<1>(0h1), "") : assert_13
node _T_108 = eq(before, UInt<4>(0h8))
node _T_109 = eq(after, UInt<3>(0h7))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(before, UInt<4>(0h8))
node _T_112 = eq(after, UInt<3>(0h5))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(_T_113, UInt<1>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14
assert(clock, _T_114, UInt<1>(0h1), "") : assert_14
node _T_118 = eq(before, UInt<4>(0h8))
node _T_119 = eq(after, UInt<3>(0h4))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15
assert(clock, _T_121, UInt<1>(0h1), "") : assert_15
node _T_125 = eq(before, UInt<4>(0h8))
node _T_126 = eq(after, UInt<3>(0h6))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(before, UInt<4>(0h8))
node _T_129 = eq(after, UInt<2>(0h3))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(before, UInt<4>(0h8))
node _T_132 = eq(after, UInt<2>(0h2))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16
assert(clock, _T_134, UInt<1>(0h1), "") : assert_16
node _T_138 = eq(before, UInt<1>(0h1))
node _T_139 = eq(after, UInt<4>(0h8))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(_T_140, UInt<1>(0h0))
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17
assert(clock, _T_141, UInt<1>(0h1), "") : assert_17
node _T_145 = eq(before, UInt<1>(0h1))
node _T_146 = eq(after, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(_T_147, UInt<1>(0h0))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18
assert(clock, _T_148, UInt<1>(0h1), "") : assert_18
node _T_152 = eq(before, UInt<1>(0h1))
node _T_153 = eq(after, UInt<3>(0h7))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(_T_154, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19
assert(clock, _T_155, UInt<1>(0h1), "") : assert_19
node _T_159 = eq(before, UInt<1>(0h1))
node _T_160 = eq(after, UInt<3>(0h5))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(_T_161, UInt<1>(0h0))
node _T_163 = asUInt(reset)
node _T_164 = eq(_T_163, UInt<1>(0h0))
when _T_164 :
node _T_165 = eq(_T_162, UInt<1>(0h0))
when _T_165 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20
assert(clock, _T_162, UInt<1>(0h1), "") : assert_20
node _T_166 = eq(before, UInt<1>(0h1))
node _T_167 = eq(after, UInt<3>(0h4))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21
assert(clock, _T_169, UInt<1>(0h1), "") : assert_21
node _T_173 = eq(before, UInt<1>(0h1))
node _T_174 = eq(after, UInt<3>(0h6))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(_T_175, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22
assert(clock, _T_176, UInt<1>(0h1), "") : assert_22
node _T_180 = eq(before, UInt<1>(0h1))
node _T_181 = eq(after, UInt<2>(0h3))
node _T_182 = and(_T_180, _T_181)
node _T_183 = eq(_T_182, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(before, UInt<1>(0h1))
node _T_188 = eq(after, UInt<2>(0h2))
node _T_189 = and(_T_187, _T_188)
node _T_190 = eq(_T_189, UInt<1>(0h0))
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(_T_190, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24
assert(clock, _T_190, UInt<1>(0h1), "") : assert_24
node _T_194 = eq(before, UInt<1>(0h0))
node _T_195 = eq(after, UInt<4>(0h8))
node _T_196 = and(_T_194, _T_195)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25
assert(clock, _T_197, UInt<1>(0h1), "") : assert_25
node _T_201 = eq(before, UInt<1>(0h0))
node _T_202 = eq(after, UInt<1>(0h1))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26
assert(clock, _T_204, UInt<1>(0h1), "") : assert_26
node _T_208 = eq(before, UInt<1>(0h0))
node _T_209 = eq(after, UInt<3>(0h7))
node _T_210 = and(_T_208, _T_209)
node _T_211 = eq(_T_210, UInt<1>(0h0))
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27
assert(clock, _T_211, UInt<1>(0h1), "") : assert_27
node _T_215 = eq(before, UInt<1>(0h0))
node _T_216 = eq(after, UInt<3>(0h5))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(_T_217, UInt<1>(0h0))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28
assert(clock, _T_218, UInt<1>(0h1), "") : assert_28
node _T_222 = eq(before, UInt<1>(0h0))
node _T_223 = eq(after, UInt<3>(0h6))
node _T_224 = and(_T_222, _T_223)
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29
assert(clock, _T_225, UInt<1>(0h1), "") : assert_29
node _T_229 = eq(before, UInt<1>(0h0))
node _T_230 = eq(after, UInt<3>(0h4))
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(before, UInt<1>(0h0))
node _T_237 = eq(after, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31
assert(clock, _T_239, UInt<1>(0h1), "") : assert_31
node _T_243 = eq(before, UInt<1>(0h0))
node _T_244 = eq(after, UInt<2>(0h2))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(_T_245, UInt<1>(0h0))
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32
assert(clock, _T_246, UInt<1>(0h1), "") : assert_32
node _T_250 = eq(before, UInt<3>(0h7))
node _T_251 = eq(after, UInt<4>(0h8))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33
assert(clock, _T_253, UInt<1>(0h1), "") : assert_33
node _T_257 = eq(before, UInt<3>(0h7))
node _T_258 = eq(after, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(_T_259, UInt<1>(0h0))
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34
assert(clock, _T_260, UInt<1>(0h1), "") : assert_34
node _T_264 = eq(before, UInt<3>(0h7))
node _T_265 = eq(after, UInt<1>(0h0))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35
assert(clock, _T_267, UInt<1>(0h1), "") : assert_35
node _T_271 = eq(before, UInt<3>(0h7))
node _T_272 = eq(after, UInt<3>(0h5))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(_T_273, UInt<1>(0h0))
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36
assert(clock, _T_274, UInt<1>(0h1), "") : assert_36
node _T_278 = eq(before, UInt<3>(0h7))
node _T_279 = eq(after, UInt<3>(0h6))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(before, UInt<3>(0h7))
node _T_282 = eq(after, UInt<3>(0h4))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37
assert(clock, _T_284, UInt<1>(0h1), "") : assert_37
node _T_288 = eq(before, UInt<3>(0h7))
node _T_289 = eq(after, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(before, UInt<3>(0h7))
node _T_292 = eq(after, UInt<2>(0h2))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(_T_293, UInt<1>(0h0))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38
assert(clock, _T_294, UInt<1>(0h1), "") : assert_38
node _T_298 = eq(before, UInt<3>(0h5))
node _T_299 = eq(after, UInt<4>(0h8))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(_T_300, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39
assert(clock, _T_301, UInt<1>(0h1), "") : assert_39
node _T_305 = eq(before, UInt<3>(0h5))
node _T_306 = eq(after, UInt<1>(0h1))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(_T_307, UInt<1>(0h0))
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40
assert(clock, _T_308, UInt<1>(0h1), "") : assert_40
node _T_312 = eq(before, UInt<3>(0h5))
node _T_313 = eq(after, UInt<1>(0h0))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(_T_314, UInt<1>(0h0))
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(_T_315, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41
assert(clock, _T_315, UInt<1>(0h1), "") : assert_41
node _T_319 = eq(before, UInt<3>(0h5))
node _T_320 = eq(after, UInt<3>(0h7))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(before, UInt<3>(0h5))
node _T_323 = eq(after, UInt<3>(0h6))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(before, UInt<3>(0h5))
node _T_326 = eq(after, UInt<3>(0h4))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(_T_327, UInt<1>(0h0))
node _T_329 = asUInt(reset)
node _T_330 = eq(_T_329, UInt<1>(0h0))
when _T_330 :
node _T_331 = eq(_T_328, UInt<1>(0h0))
when _T_331 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42
assert(clock, _T_328, UInt<1>(0h1), "") : assert_42
node _T_332 = eq(before, UInt<3>(0h5))
node _T_333 = eq(after, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(before, UInt<3>(0h5))
node _T_336 = eq(after, UInt<2>(0h2))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(_T_337, UInt<1>(0h0))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43
assert(clock, _T_338, UInt<1>(0h1), "") : assert_43
node _T_342 = eq(before, UInt<3>(0h6))
node _T_343 = eq(after, UInt<4>(0h8))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(_T_344, UInt<1>(0h0))
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44
assert(clock, _T_345, UInt<1>(0h1), "") : assert_44
node _T_349 = eq(before, UInt<3>(0h6))
node _T_350 = eq(after, UInt<1>(0h1))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(_T_351, UInt<1>(0h0))
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(_T_352, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45
assert(clock, _T_352, UInt<1>(0h1), "") : assert_45
node _T_356 = eq(before, UInt<3>(0h6))
node _T_357 = eq(after, UInt<1>(0h0))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(_T_358, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46
assert(clock, _T_359, UInt<1>(0h1), "") : assert_46
node _T_363 = eq(before, UInt<3>(0h6))
node _T_364 = eq(after, UInt<3>(0h7))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47
assert(clock, _T_366, UInt<1>(0h1), "") : assert_47
node _T_370 = eq(before, UInt<3>(0h6))
node _T_371 = eq(after, UInt<3>(0h5))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(_T_372, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48
assert(clock, _T_373, UInt<1>(0h1), "") : assert_48
node _T_377 = eq(before, UInt<3>(0h6))
node _T_378 = eq(after, UInt<3>(0h4))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(_T_379, UInt<1>(0h0))
node _T_381 = asUInt(reset)
node _T_382 = eq(_T_381, UInt<1>(0h0))
when _T_382 :
node _T_383 = eq(_T_380, UInt<1>(0h0))
when _T_383 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49
assert(clock, _T_380, UInt<1>(0h1), "") : assert_49
node _T_384 = eq(before, UInt<3>(0h6))
node _T_385 = eq(after, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(_T_386, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50
assert(clock, _T_387, UInt<1>(0h1), "") : assert_50
node _T_391 = eq(before, UInt<3>(0h6))
node _T_392 = eq(after, UInt<2>(0h2))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(before, UInt<3>(0h4))
node _T_395 = eq(after, UInt<4>(0h8))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51
assert(clock, _T_397, UInt<1>(0h1), "") : assert_51
node _T_401 = eq(before, UInt<3>(0h4))
node _T_402 = eq(after, UInt<1>(0h1))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(_T_403, UInt<1>(0h0))
node _T_405 = asUInt(reset)
node _T_406 = eq(_T_405, UInt<1>(0h0))
when _T_406 :
node _T_407 = eq(_T_404, UInt<1>(0h0))
when _T_407 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52
assert(clock, _T_404, UInt<1>(0h1), "") : assert_52
node _T_408 = eq(before, UInt<3>(0h4))
node _T_409 = eq(after, UInt<1>(0h0))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(_T_410, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53
assert(clock, _T_411, UInt<1>(0h1), "") : assert_53
node _T_415 = eq(before, UInt<3>(0h4))
node _T_416 = eq(after, UInt<3>(0h7))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(_T_417, UInt<1>(0h0))
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54
assert(clock, _T_418, UInt<1>(0h1), "") : assert_54
node _T_422 = eq(before, UInt<3>(0h4))
node _T_423 = eq(after, UInt<3>(0h5))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = asUInt(reset)
node _T_427 = eq(_T_426, UInt<1>(0h0))
when _T_427 :
node _T_428 = eq(_T_425, UInt<1>(0h0))
when _T_428 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55
assert(clock, _T_425, UInt<1>(0h1), "") : assert_55
node _T_429 = eq(before, UInt<3>(0h4))
node _T_430 = eq(after, UInt<3>(0h6))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(before, UInt<3>(0h4))
node _T_433 = eq(after, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(_T_434, UInt<1>(0h0))
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56
assert(clock, _T_435, UInt<1>(0h1), "") : assert_56
node _T_439 = eq(before, UInt<3>(0h4))
node _T_440 = eq(after, UInt<2>(0h2))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(before, UInt<2>(0h3))
node _T_443 = eq(after, UInt<4>(0h8))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(_T_444, UInt<1>(0h0))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57
assert(clock, _T_445, UInt<1>(0h1), "") : assert_57
node _T_449 = eq(before, UInt<2>(0h3))
node _T_450 = eq(after, UInt<1>(0h1))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(_T_451, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58
assert(clock, _T_452, UInt<1>(0h1), "") : assert_58
node _T_456 = eq(before, UInt<2>(0h3))
node _T_457 = eq(after, UInt<1>(0h0))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59
assert(clock, _T_459, UInt<1>(0h1), "") : assert_59
node _T_463 = eq(before, UInt<2>(0h3))
node _T_464 = eq(after, UInt<3>(0h7))
node _T_465 = and(_T_463, _T_464)
node _T_466 = eq(before, UInt<2>(0h3))
node _T_467 = eq(after, UInt<3>(0h5))
node _T_468 = and(_T_466, _T_467)
node _T_469 = eq(before, UInt<2>(0h3))
node _T_470 = eq(after, UInt<3>(0h6))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(before, UInt<2>(0h3))
node _T_473 = eq(after, UInt<3>(0h4))
node _T_474 = and(_T_472, _T_473)
node _T_475 = eq(before, UInt<2>(0h3))
node _T_476 = eq(after, UInt<2>(0h2))
node _T_477 = and(_T_475, _T_476)
node _T_478 = eq(before, UInt<2>(0h2))
node _T_479 = eq(after, UInt<4>(0h8))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60
assert(clock, _T_481, UInt<1>(0h1), "") : assert_60
node _T_485 = eq(before, UInt<2>(0h2))
node _T_486 = eq(after, UInt<1>(0h1))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(_T_487, UInt<1>(0h0))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61
assert(clock, _T_488, UInt<1>(0h1), "") : assert_61
node _T_492 = eq(before, UInt<2>(0h2))
node _T_493 = eq(after, UInt<1>(0h0))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62
assert(clock, _T_495, UInt<1>(0h1), "") : assert_62
node _T_499 = eq(before, UInt<2>(0h2))
node _T_500 = eq(after, UInt<3>(0h7))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(_T_501, UInt<1>(0h0))
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63
assert(clock, _T_502, UInt<1>(0h1), "") : assert_63
node _T_506 = eq(before, UInt<2>(0h2))
node _T_507 = eq(after, UInt<3>(0h5))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(_T_508, UInt<1>(0h0))
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64
assert(clock, _T_509, UInt<1>(0h1), "") : assert_64
node _T_513 = eq(before, UInt<2>(0h2))
node _T_514 = eq(after, UInt<3>(0h6))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(before, UInt<2>(0h2))
node _T_517 = eq(after, UInt<3>(0h4))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(before, UInt<2>(0h2))
node _T_520 = eq(after, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(_T_521, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65
assert(clock, _T_522, UInt<1>(0h1), "") : assert_65
node _probe_bit_T = eq(io.sinkc.bits.source, UInt<7>(0h44))
node _probe_bit_T_1 = eq(io.sinkc.bits.source, UInt<7>(0h40))
node _probe_bit_uncommonBits_T = or(io.sinkc.bits.source, UInt<3>(0h0))
node probe_bit_uncommonBits = bits(_probe_bit_uncommonBits_T, 2, 0)
node _probe_bit_T_2 = shr(io.sinkc.bits.source, 3)
node _probe_bit_T_3 = eq(_probe_bit_T_2, UInt<3>(0h6))
node _probe_bit_T_4 = leq(UInt<1>(0h0), probe_bit_uncommonBits)
node _probe_bit_T_5 = and(_probe_bit_T_3, _probe_bit_T_4)
node _probe_bit_T_6 = leq(probe_bit_uncommonBits, UInt<3>(0h4))
node _probe_bit_T_7 = and(_probe_bit_T_5, _probe_bit_T_6)
node _probe_bit_uncommonBits_T_1 = or(io.sinkc.bits.source, UInt<3>(0h0))
node probe_bit_uncommonBits_1 = bits(_probe_bit_uncommonBits_T_1, 2, 0)
node _probe_bit_T_8 = shr(io.sinkc.bits.source, 3)
node _probe_bit_T_9 = eq(_probe_bit_T_8, UInt<3>(0h4))
node _probe_bit_T_10 = leq(UInt<1>(0h0), probe_bit_uncommonBits_1)
node _probe_bit_T_11 = and(_probe_bit_T_9, _probe_bit_T_10)
node _probe_bit_T_12 = leq(probe_bit_uncommonBits_1, UInt<3>(0h4))
node _probe_bit_T_13 = and(_probe_bit_T_11, _probe_bit_T_12)
node probe_bit_lo = cat(_probe_bit_T_1, _probe_bit_T)
node probe_bit_hi = cat(_probe_bit_T_13, _probe_bit_T_7)
node probe_bit = cat(probe_bit_hi, probe_bit_lo)
node _last_probe_T = or(probes_done, probe_bit)
node _last_probe_T_1 = not(excluded_client)
node _last_probe_T_2 = and(meta.clients, _last_probe_T_1)
node last_probe = eq(_last_probe_T, _last_probe_T_2)
node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1))
node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2))
node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1)
node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5))
node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3)
when io.sinkc.valid :
node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_527 = and(probe_toN, _T_526)
node _T_528 = eq(probe_toN, UInt<1>(0h0))
node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_530 = and(_T_528, _T_529)
node _probes_done_T = or(probes_done, probe_bit)
connect probes_done, _probes_done_T
node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0))
node _probes_toN_T_1 = or(probes_toN, _probes_toN_T)
connect probes_toN, _probes_toN_T_1
node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3))
node _probes_noT_T_1 = or(probes_noT, _probes_noT_T)
connect probes_noT, _probes_noT_T_1
node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe)
connect w_rprobeackfirst, _w_rprobeackfirst_T
node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T)
connect w_rprobeacklast, _w_rprobeacklast_T_1
node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe)
connect w_pprobeackfirst, _w_pprobeackfirst_T
node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T)
connect w_pprobeacklast, _w_pprobeacklast_T_1
node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0))
node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T)
node set_pprobeack = and(last_probe, _set_pprobeack_T_1)
node _w_pprobeack_T = or(w_pprobeack, set_pprobeack)
connect w_pprobeack, _w_pprobeack_T
node _T_531 = eq(set_pprobeack, UInt<1>(0h0))
node _T_532 = and(_T_531, w_rprobeackfirst)
node _T_533 = and(set_pprobeack, w_rprobeackfirst)
node _T_534 = neq(meta.state, UInt<2>(0h0))
node _T_535 = eq(io.sinkc.bits.tag, meta.tag)
node _T_536 = and(_T_534, _T_535)
node _T_537 = and(_T_536, io.sinkc.bits.data)
when _T_537 :
connect meta.dirty, UInt<1>(0h1)
when io.sinkd.valid :
node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4))
node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_540 = or(_T_538, _T_539)
when _T_540 :
connect sink, io.sinkd.bits.sink
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, io.sinkd.bits.last
connect bad_grant, io.sinkd.bits.denied
node _w_grant_T = eq(request.offset, UInt<1>(0h0))
node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last)
connect w_grant, _w_grant_T_1
node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_542 = eq(request.offset, UInt<1>(0h0))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_545 = neq(request.offset, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0))
connect gotT, _gotT_T
else :
node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6))
when _T_547 :
connect w_releaseack, UInt<1>(0h1)
when io.sinke.valid :
connect w_grantack, UInt<1>(0h1)
wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}
connect allocate_as_full.set, io.allocate.bits.set
connect allocate_as_full.put, io.allocate.bits.put
connect allocate_as_full.offset, io.allocate.bits.offset
connect allocate_as_full.tag, io.allocate.bits.tag
connect allocate_as_full.source, io.allocate.bits.source
connect allocate_as_full.size, io.allocate.bits.size
connect allocate_as_full.param, io.allocate.bits.param
connect allocate_as_full.opcode, io.allocate.bits.opcode
connect allocate_as_full.control, io.allocate.bits.control
connect allocate_as_full.prio, io.allocate.bits.prio
node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat)
node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits)
node new_request = mux(io.allocate.valid, allocate_as_full, request)
node _new_needT_T = bits(new_request.opcode, 2, 2)
node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0))
node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5))
node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1))
node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3)
node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4)
node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6))
node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7))
node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7)
node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0))
node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9)
node new_needT = or(_new_needT_T_5, _new_needT_T_10)
node _new_clientBit_T = eq(new_request.source, UInt<7>(0h44))
node _new_clientBit_T_1 = eq(new_request.source, UInt<7>(0h40))
node _new_clientBit_uncommonBits_T = or(new_request.source, UInt<3>(0h0))
node new_clientBit_uncommonBits = bits(_new_clientBit_uncommonBits_T, 2, 0)
node _new_clientBit_T_2 = shr(new_request.source, 3)
node _new_clientBit_T_3 = eq(_new_clientBit_T_2, UInt<3>(0h6))
node _new_clientBit_T_4 = leq(UInt<1>(0h0), new_clientBit_uncommonBits)
node _new_clientBit_T_5 = and(_new_clientBit_T_3, _new_clientBit_T_4)
node _new_clientBit_T_6 = leq(new_clientBit_uncommonBits, UInt<3>(0h4))
node _new_clientBit_T_7 = and(_new_clientBit_T_5, _new_clientBit_T_6)
node _new_clientBit_uncommonBits_T_1 = or(new_request.source, UInt<3>(0h0))
node new_clientBit_uncommonBits_1 = bits(_new_clientBit_uncommonBits_T_1, 2, 0)
node _new_clientBit_T_8 = shr(new_request.source, 3)
node _new_clientBit_T_9 = eq(_new_clientBit_T_8, UInt<3>(0h4))
node _new_clientBit_T_10 = leq(UInt<1>(0h0), new_clientBit_uncommonBits_1)
node _new_clientBit_T_11 = and(_new_clientBit_T_9, _new_clientBit_T_10)
node _new_clientBit_T_12 = leq(new_clientBit_uncommonBits_1, UInt<3>(0h4))
node _new_clientBit_T_13 = and(_new_clientBit_T_11, _new_clientBit_T_12)
node new_clientBit_lo = cat(_new_clientBit_T_1, _new_clientBit_T)
node new_clientBit_hi = cat(_new_clientBit_T_13, _new_clientBit_T_7)
node new_clientBit = cat(new_clientBit_hi, new_clientBit_lo)
node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6))
node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7))
node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1)
node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4))
node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3)
node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5))
node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0))
node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6)
node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0))
wire prior : UInt
connect prior, UInt<1>(0h0)
node prior_c = orr(final_meta_writeback.clients)
node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _prior_T :
node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1))
connect prior, _prior_out_T
else :
node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _prior_T_1 :
node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect prior, _prior_out_T_1
else :
node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _prior_T_2 :
node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3)
connect prior, _prior_out_T_4
else :
node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _prior_T_3 :
connect prior, UInt<4>(0h8)
node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _prior_T_4 :
connect prior, UInt<4>(0h8)
node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat)
when _T_548 :
node _T_549 = eq(prior, UInt<4>(0h8))
node _T_550 = eq(prior, UInt<1>(0h1))
node _T_551 = eq(_T_550, UInt<1>(0h0))
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66
assert(clock, _T_551, UInt<1>(0h1), "") : assert_66
node _T_555 = eq(prior, UInt<1>(0h0))
node _T_556 = eq(_T_555, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67
assert(clock, _T_556, UInt<1>(0h1), "") : assert_67
node _T_560 = eq(prior, UInt<3>(0h7))
node _T_561 = eq(prior, UInt<3>(0h5))
node _T_562 = eq(prior, UInt<3>(0h4))
node _T_563 = eq(prior, UInt<3>(0h6))
node _T_564 = eq(prior, UInt<2>(0h3))
node _T_565 = eq(prior, UInt<2>(0h2))
when io.allocate.valid :
node _T_566 = eq(request_valid, UInt<1>(0h0))
node _T_567 = and(io.schedule.ready, io.schedule.valid)
node _T_568 = and(no_wait, _T_567)
node _T_569 = or(_T_566, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68
assert(clock, _T_569, UInt<1>(0h1), "") : assert_68
connect request_valid, UInt<1>(0h1)
connect request.set, io.allocate.bits.set
connect request.put, io.allocate.bits.put
connect request.offset, io.allocate.bits.offset
connect request.tag, io.allocate.bits.tag
connect request.source, io.allocate.bits.source
connect request.size, io.allocate.bits.size
connect request.param, io.allocate.bits.param
connect request.opcode, io.allocate.bits.opcode
connect request.control, io.allocate.bits.control
connect request.prio, io.allocate.bits.prio
node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat)
node _T_574 = or(io.directory.valid, _T_573)
when _T_574 :
connect meta_valid, UInt<1>(0h1)
connect meta, new_meta
connect probes_done, UInt<1>(0h0)
connect probes_toN, UInt<1>(0h0)
connect probes_noT, UInt<1>(0h0)
connect gotT, UInt<1>(0h0)
connect bad_grant, UInt<1>(0h0)
connect s_rprobe, UInt<1>(0h1)
connect w_rprobeackfirst, UInt<1>(0h1)
connect w_rprobeacklast, UInt<1>(0h1)
connect s_release, UInt<1>(0h1)
connect w_releaseack, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
connect s_acquire, UInt<1>(0h1)
connect s_flush, UInt<1>(0h1)
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, UInt<1>(0h1)
connect w_grant, UInt<1>(0h1)
connect w_pprobeackfirst, UInt<1>(0h1)
connect w_pprobeacklast, UInt<1>(0h1)
connect w_pprobeack, UInt<1>(0h1)
connect s_probeack, UInt<1>(0h1)
connect s_grantack, UInt<1>(0h1)
connect s_execute, UInt<1>(0h1)
connect w_grantack, UInt<1>(0h1)
connect s_writeback, UInt<1>(0h1)
node _T_575 = and(new_request.prio[2], UInt<1>(0h1))
when _T_575 :
connect s_execute, UInt<1>(0h0)
node _T_576 = bits(new_request.opcode, 0, 0)
node _T_577 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_578 = and(_T_576, _T_577)
when _T_578 :
connect s_writeback, UInt<1>(0h0)
node _T_579 = eq(new_request.param, UInt<3>(0h0))
node _T_580 = eq(new_request.param, UInt<3>(0h4))
node _T_581 = or(_T_579, _T_580)
node _T_582 = eq(new_meta.state, UInt<2>(0h2))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
connect s_writeback, UInt<1>(0h0)
node _T_584 = eq(new_request.param, UInt<3>(0h1))
node _T_585 = eq(new_request.param, UInt<3>(0h2))
node _T_586 = or(_T_584, _T_585)
node _T_587 = eq(new_request.param, UInt<3>(0h5))
node _T_588 = or(_T_586, _T_587)
node _T_589 = and(new_meta.clients, new_clientBit)
node _T_590 = neq(_T_589, UInt<1>(0h0))
node _T_591 = and(_T_588, _T_590)
when _T_591 :
connect s_writeback, UInt<1>(0h0)
node _T_592 = asUInt(reset)
node _T_593 = eq(_T_592, UInt<1>(0h0))
when _T_593 :
node _T_594 = eq(new_meta.hit, UInt<1>(0h0))
when _T_594 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69
assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69
else :
node _T_595 = and(new_request.control, UInt<1>(0h1))
when _T_595 :
connect s_flush, UInt<1>(0h0)
when new_meta.hit :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_596 = neq(new_meta.clients, UInt<1>(0h0))
node _T_597 = and(UInt<1>(0h1), _T_596)
when _T_597 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
else :
connect s_execute, UInt<1>(0h0)
node _T_598 = eq(new_meta.hit, UInt<1>(0h0))
node _T_599 = neq(new_meta.state, UInt<2>(0h0))
node _T_600 = and(_T_598, _T_599)
when _T_600 :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_601 = neq(new_meta.clients, UInt<1>(0h0))
node _T_602 = and(UInt<1>(0h1), _T_601)
when _T_602 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
node _T_603 = eq(new_meta.hit, UInt<1>(0h0))
node _T_604 = eq(new_meta.state, UInt<2>(0h1))
node _T_605 = and(_T_604, new_needT)
node _T_606 = or(_T_603, _T_605)
when _T_606 :
connect s_acquire, UInt<1>(0h0)
connect w_grantfirst, UInt<1>(0h0)
connect w_grantlast, UInt<1>(0h0)
connect w_grant, UInt<1>(0h0)
connect s_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_607 = eq(new_meta.state, UInt<2>(0h2))
node _T_608 = or(new_needT, _T_607)
node _T_609 = and(new_meta.hit, _T_608)
node _T_610 = not(new_skipProbe)
node _T_611 = and(new_meta.clients, _T_610)
node _T_612 = neq(_T_611, UInt<1>(0h0))
node _T_613 = and(_T_609, _T_612)
node _T_614 = and(UInt<1>(0h1), _T_613)
when _T_614 :
connect s_pprobe, UInt<1>(0h0)
connect w_pprobeackfirst, UInt<1>(0h0)
connect w_pprobeacklast, UInt<1>(0h0)
connect w_pprobeack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_615 = eq(new_request.opcode, UInt<3>(0h6))
node _T_616 = eq(new_request.opcode, UInt<3>(0h7))
node _T_617 = or(_T_615, _T_616)
when _T_617 :
connect w_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_618 = bits(new_request.opcode, 2, 2)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = and(_T_619, new_meta.hit)
node _T_621 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_622 = and(_T_620, _T_621)
when _T_622 :
connect s_writeback, UInt<1>(0h0) | module MSHR_7( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [6:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input [3:0] io_directory_bits_clients, // @[MSHR.scala:86:14]
input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [9:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [2:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [6:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [6:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire [3:0] final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [6:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire [3:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [6:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] invalid_clients = 4'h0; // @[MSHR.scala:268:21]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _req_clientBit_T_4 = 1'h1; // @[Parameters.scala:56:32]
wire _req_clientBit_T_10 = 1'h1; // @[Parameters.scala:56:32]
wire _probe_bit_T_4 = 1'h1; // @[Parameters.scala:56:32]
wire _probe_bit_T_10 = 1'h1; // @[Parameters.scala:56:32]
wire _new_clientBit_T_4 = 1'h1; // @[Parameters.scala:56:32]
wire _new_clientBit_T_10 = 1'h1; // @[Parameters.scala:56:32]
wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [6:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire [3:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire [3:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [6:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29]
wire [6:0] _probe_bit_uncommonBits_T_1 = io_sinkc_bits_source_0; // @[Parameters.scala:52:29]
wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [6:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [6:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
wire [6:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29]
wire [6:0] _req_clientBit_uncommonBits_T_1 = request_source; // @[Parameters.scala:52:29]
reg [12:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [9:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg [3:0] meta_clients; // @[MSHR.scala:100:17]
reg [12:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [2:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg [3:0] probes_done; // @[MSHR.scala:150:24]
reg [3:0] probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire [3:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire _req_clientBit_T = request_source == 7'h44; // @[Parameters.scala:46:9]
wire _req_clientBit_T_1 = request_source == 7'h40; // @[Parameters.scala:46:9]
wire [2:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _req_clientBit_T_2 = request_source[6:3]; // @[Parameters.scala:54:10]
wire [3:0] _req_clientBit_T_8 = request_source[6:3]; // @[Parameters.scala:54:10]
wire _req_clientBit_T_3 = _req_clientBit_T_2 == 4'h6; // @[Parameters.scala:54:{10,32}]
wire _req_clientBit_T_5 = _req_clientBit_T_3; // @[Parameters.scala:54:{32,67}]
wire _req_clientBit_T_6 = req_clientBit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _req_clientBit_T_7 = _req_clientBit_T_5 & _req_clientBit_T_6; // @[Parameters.scala:54:67, :56:48, :57:20]
wire [2:0] req_clientBit_uncommonBits_1 = _req_clientBit_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire _req_clientBit_T_9 = _req_clientBit_T_8 == 4'h4; // @[Parameters.scala:54:{10,32}]
wire _req_clientBit_T_11 = _req_clientBit_T_9; // @[Parameters.scala:54:{32,67}]
wire _req_clientBit_T_12 = req_clientBit_uncommonBits_1 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _req_clientBit_T_13 = _req_clientBit_T_11 & _req_clientBit_T_12; // @[Parameters.scala:54:67, :56:48, :57:20]
wire [1:0] req_clientBit_lo = {_req_clientBit_T_1, _req_clientBit_T}; // @[Parameters.scala:46:9]
wire [1:0] req_clientBit_hi = {_req_clientBit_T_13, _req_clientBit_T_7}; // @[Parameters.scala:56:48]
wire [3:0] req_clientBit = {req_clientBit_hi, req_clientBit_lo}; // @[Parameters.scala:201:10]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire _meta_no_clients_T = |meta_clients; // @[MSHR.scala:100:17, :220:39]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire [3:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 4'h0; // @[Parameters.scala:201:10, :282:66]
wire [3:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire [3:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire [3:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire [3:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire [3:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire [3:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire [3:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 4'h0; // @[MSHR.scala:100:17, :245:{40,64}]
wire [3:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 4'h0; // @[Parameters.scala:201:10]
wire [3:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire [3:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire [3:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 4'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire [3:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10]
wire _honour_BtoT_T_1 = |_honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire [3:0] excluded_client = _excluded_client_T_9 ? req_clientBit : 4'h0; // @[Parameters.scala:201:10]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire [3:0] _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 4'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire evict_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire before_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire after_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _probe_bit_T = io_sinkc_bits_source_0 == 7'h44; // @[Parameters.scala:46:9]
wire _probe_bit_T_1 = io_sinkc_bits_source_0 == 7'h40; // @[Parameters.scala:46:9]
wire [2:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _probe_bit_T_2 = io_sinkc_bits_source_0[6:3]; // @[Parameters.scala:54:10]
wire [3:0] _probe_bit_T_8 = io_sinkc_bits_source_0[6:3]; // @[Parameters.scala:54:10]
wire _probe_bit_T_3 = _probe_bit_T_2 == 4'h6; // @[Parameters.scala:54:{10,32}]
wire _probe_bit_T_5 = _probe_bit_T_3; // @[Parameters.scala:54:{32,67}]
wire _probe_bit_T_6 = probe_bit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _probe_bit_T_7 = _probe_bit_T_5 & _probe_bit_T_6; // @[Parameters.scala:54:67, :56:48, :57:20]
wire [2:0] probe_bit_uncommonBits_1 = _probe_bit_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire _probe_bit_T_9 = _probe_bit_T_8 == 4'h4; // @[Parameters.scala:54:{10,32}]
wire _probe_bit_T_11 = _probe_bit_T_9; // @[Parameters.scala:54:{32,67}]
wire _probe_bit_T_12 = probe_bit_uncommonBits_1 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _probe_bit_T_13 = _probe_bit_T_11 & _probe_bit_T_12; // @[Parameters.scala:54:67, :56:48, :57:20]
wire [1:0] probe_bit_lo = {_probe_bit_T_1, _probe_bit_T}; // @[Parameters.scala:46:9]
wire [1:0] probe_bit_hi = {_probe_bit_T_13, _probe_bit_T_7}; // @[Parameters.scala:56:48]
wire [3:0] probe_bit = {probe_bit_hi, probe_bit_lo}; // @[Parameters.scala:201:10]
wire [3:0] _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:201:10]
wire [3:0] _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire [3:0] _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire [3:0] _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire [3:0] _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire [3:0] _probes_toN_T = probe_toN ? probe_bit : 4'h0; // @[Parameters.scala:201:10, :282:66]
wire [3:0] _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [3:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [6:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [6:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29]
wire [6:0] _new_clientBit_uncommonBits_T_1 = new_request_source; // @[Parameters.scala:52:29]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _new_clientBit_T = new_request_source == 7'h44; // @[Parameters.scala:46:9]
wire _new_clientBit_T_1 = new_request_source == 7'h40; // @[Parameters.scala:46:9]
wire [2:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _new_clientBit_T_2 = new_request_source[6:3]; // @[Parameters.scala:54:10]
wire [3:0] _new_clientBit_T_8 = new_request_source[6:3]; // @[Parameters.scala:54:10]
wire _new_clientBit_T_3 = _new_clientBit_T_2 == 4'h6; // @[Parameters.scala:54:{10,32}]
wire _new_clientBit_T_5 = _new_clientBit_T_3; // @[Parameters.scala:54:{32,67}]
wire _new_clientBit_T_6 = new_clientBit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _new_clientBit_T_7 = _new_clientBit_T_5 & _new_clientBit_T_6; // @[Parameters.scala:54:67, :56:48, :57:20]
wire [2:0] new_clientBit_uncommonBits_1 = _new_clientBit_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire _new_clientBit_T_9 = _new_clientBit_T_8 == 4'h4; // @[Parameters.scala:54:{10,32}]
wire _new_clientBit_T_11 = _new_clientBit_T_9; // @[Parameters.scala:54:{32,67}]
wire _new_clientBit_T_12 = new_clientBit_uncommonBits_1 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _new_clientBit_T_13 = _new_clientBit_T_11 & _new_clientBit_T_12; // @[Parameters.scala:54:67, :56:48, :57:20]
wire [1:0] new_clientBit_lo = {_new_clientBit_T_1, _new_clientBit_T}; // @[Parameters.scala:46:9]
wire [1:0] new_clientBit_hi = {_new_clientBit_T_13, _new_clientBit_T_7}; // @[Parameters.scala:56:48]
wire [3:0] new_clientBit = {new_clientBit_hi, new_clientBit_lo}; // @[Parameters.scala:201:10]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire [3:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 4'h0; // @[Parameters.scala:201:10, :279:106]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire prior_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to this FIRRTL code module DCache :
input clock : Clock
input reset : Reset
output auto : { flip mmio_address_prefix_sink_in : UInt<1>, flip hart_id_sink_in : UInt<1>, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
output io : { flip cpu : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, errors : { bus : { valid : UInt<1>, bits : UInt<32>}}, tlb_port : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, s1_resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip s2_kill : UInt<1>}}
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
wire hartIdSinkNodeOptIn : UInt<1>
invalidate hartIdSinkNodeOptIn
wire mmioAddressPrefixSinkNodeOptIn : UInt<1>
invalidate mmioAddressPrefixSinkNodeOptIn
connect auto.out, nodeOut
connect hartIdSinkNodeOptIn, auto.hart_id_sink_in
connect mmioAddressPrefixSinkNodeOptIn, auto.mmio_address_prefix_sink_in
reg clock_en_reg : UInt<1>, clock
connect io.cpu.clock_enabled, clock_en_reg
inst tlb of DTLB
connect tlb.clock, clock
connect tlb.reset, reset
inst pma_checker of DTLB_1
connect pma_checker.clock, clock
connect pma_checker.reset, reset
wire replace : UInt<1>
connect replace, UInt<1>(0h0)
inst lfsr_prng of MaxPeriodFibonacciLFSR_1
connect lfsr_prng.clock, clock
connect lfsr_prng.reset, reset
connect lfsr_prng.io.seed.valid, UInt<1>(0h0)
invalidate lfsr_prng.io.seed.bits[0]
invalidate lfsr_prng.io.seed.bits[1]
invalidate lfsr_prng.io.seed.bits[2]
invalidate lfsr_prng.io.seed.bits[3]
invalidate lfsr_prng.io.seed.bits[4]
invalidate lfsr_prng.io.seed.bits[5]
invalidate lfsr_prng.io.seed.bits[6]
invalidate lfsr_prng.io.seed.bits[7]
invalidate lfsr_prng.io.seed.bits[8]
invalidate lfsr_prng.io.seed.bits[9]
invalidate lfsr_prng.io.seed.bits[10]
invalidate lfsr_prng.io.seed.bits[11]
invalidate lfsr_prng.io.seed.bits[12]
invalidate lfsr_prng.io.seed.bits[13]
invalidate lfsr_prng.io.seed.bits[14]
invalidate lfsr_prng.io.seed.bits[15]
connect lfsr_prng.io.increment, replace
node lfsr_lo_lo_lo = cat(lfsr_prng.io.out[1], lfsr_prng.io.out[0])
node lfsr_lo_lo_hi = cat(lfsr_prng.io.out[3], lfsr_prng.io.out[2])
node lfsr_lo_lo = cat(lfsr_lo_lo_hi, lfsr_lo_lo_lo)
node lfsr_lo_hi_lo = cat(lfsr_prng.io.out[5], lfsr_prng.io.out[4])
node lfsr_lo_hi_hi = cat(lfsr_prng.io.out[7], lfsr_prng.io.out[6])
node lfsr_lo_hi = cat(lfsr_lo_hi_hi, lfsr_lo_hi_lo)
node lfsr_lo = cat(lfsr_lo_hi, lfsr_lo_lo)
node lfsr_hi_lo_lo = cat(lfsr_prng.io.out[9], lfsr_prng.io.out[8])
node lfsr_hi_lo_hi = cat(lfsr_prng.io.out[11], lfsr_prng.io.out[10])
node lfsr_hi_lo = cat(lfsr_hi_lo_hi, lfsr_hi_lo_lo)
node lfsr_hi_hi_lo = cat(lfsr_prng.io.out[13], lfsr_prng.io.out[12])
node lfsr_hi_hi_hi = cat(lfsr_prng.io.out[15], lfsr_prng.io.out[14])
node lfsr_hi_hi = cat(lfsr_hi_hi_hi, lfsr_hi_hi_lo)
node lfsr_hi = cat(lfsr_hi_hi, lfsr_hi_lo)
node lfsr = cat(lfsr_hi, lfsr_lo)
inst metaArb of Arbiter8_DCacheMetadataReq
connect metaArb.clock, clock
connect metaArb.reset, reset
smem rockettile_dcache_tag_array : UInt<23>[1] [32]
inst data of DCacheDataArray
connect data.clock, clock
connect data.reset, reset
inst dataArb of Arbiter4_DCacheDataReq
connect dataArb.clock, clock
connect dataArb.reset, reset
connect dataArb.io.in[1].bits.wdata, dataArb.io.in[0].bits.wdata
connect dataArb.io.in[2].bits.wdata, dataArb.io.in[0].bits.wdata
connect dataArb.io.in[3].bits.wdata, dataArb.io.in[0].bits.wdata
connect data.io.req.bits, dataArb.io.out.bits
connect data.io.req.valid, dataArb.io.out.valid
connect dataArb.io.out.ready, UInt<1>(0h1)
connect metaArb.io.out.ready, clock_en_reg
wire tl_out_a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
wire nodeOut_a_deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect nodeOut_a_deq.valid, tl_out_a.valid
connect nodeOut_a_deq.bits, tl_out_a.bits
connect tl_out_a.ready, nodeOut_a_deq.ready
connect nodeOut.a, nodeOut_a_deq
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<3>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire tl_out_c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect tl_out_c.bits, _WIRE.bits
connect tl_out_c.valid, _WIRE.valid
connect tl_out_c.ready, _WIRE.ready
node _s1_valid_T = and(io.cpu.req.ready, io.cpu.req.valid)
regreset s1_valid : UInt<1>, clock, reset, UInt<1>(0h0)
connect s1_valid, _s1_valid_T
wire _s1_probe_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _s1_probe_WIRE.bits.corrupt, UInt<1>(0h0)
connect _s1_probe_WIRE.bits.data, UInt<64>(0h0)
connect _s1_probe_WIRE.bits.mask, UInt<8>(0h0)
connect _s1_probe_WIRE.bits.address, UInt<32>(0h0)
connect _s1_probe_WIRE.bits.source, UInt<1>(0h0)
connect _s1_probe_WIRE.bits.size, UInt<4>(0h0)
connect _s1_probe_WIRE.bits.param, UInt<2>(0h0)
connect _s1_probe_WIRE.bits.opcode, UInt<3>(0h0)
connect _s1_probe_WIRE.valid, UInt<1>(0h0)
connect _s1_probe_WIRE.ready, UInt<1>(0h0)
wire _s1_probe_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _s1_probe_WIRE_1.bits, _s1_probe_WIRE.bits
connect _s1_probe_WIRE_1.valid, _s1_probe_WIRE.valid
connect _s1_probe_WIRE_1.ready, _s1_probe_WIRE.ready
node _s1_probe_T = and(_s1_probe_WIRE_1.ready, _s1_probe_WIRE_1.valid)
regreset s1_probe : UInt<1>, clock, reset, UInt<1>(0h0)
connect s1_probe, _s1_probe_T
wire _probe_bits_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _probe_bits_WIRE.bits.corrupt, UInt<1>(0h0)
connect _probe_bits_WIRE.bits.data, UInt<64>(0h0)
connect _probe_bits_WIRE.bits.mask, UInt<8>(0h0)
connect _probe_bits_WIRE.bits.address, UInt<32>(0h0)
connect _probe_bits_WIRE.bits.source, UInt<1>(0h0)
connect _probe_bits_WIRE.bits.size, UInt<4>(0h0)
connect _probe_bits_WIRE.bits.param, UInt<2>(0h0)
connect _probe_bits_WIRE.bits.opcode, UInt<3>(0h0)
connect _probe_bits_WIRE.valid, UInt<1>(0h0)
connect _probe_bits_WIRE.ready, UInt<1>(0h0)
wire _probe_bits_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _probe_bits_WIRE_1.bits, _probe_bits_WIRE.bits
connect _probe_bits_WIRE_1.valid, _probe_bits_WIRE.valid
connect _probe_bits_WIRE_1.ready, _probe_bits_WIRE.ready
wire _probe_bits_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _probe_bits_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _probe_bits_WIRE_2.bits.data, UInt<64>(0h0)
connect _probe_bits_WIRE_2.bits.mask, UInt<8>(0h0)
connect _probe_bits_WIRE_2.bits.address, UInt<32>(0h0)
connect _probe_bits_WIRE_2.bits.source, UInt<1>(0h0)
connect _probe_bits_WIRE_2.bits.size, UInt<4>(0h0)
connect _probe_bits_WIRE_2.bits.param, UInt<2>(0h0)
connect _probe_bits_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _probe_bits_WIRE_2.valid, UInt<1>(0h0)
connect _probe_bits_WIRE_2.ready, UInt<1>(0h0)
wire _probe_bits_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _probe_bits_WIRE_3.bits, _probe_bits_WIRE_2.bits
connect _probe_bits_WIRE_3.valid, _probe_bits_WIRE_2.valid
connect _probe_bits_WIRE_3.ready, _probe_bits_WIRE_2.ready
node _probe_bits_T = and(_probe_bits_WIRE_3.ready, _probe_bits_WIRE_3.valid)
reg probe_bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock
when _probe_bits_T :
connect probe_bits, _probe_bits_WIRE_1.bits
wire s1_nack : UInt<1>
connect s1_nack, UInt<1>(0h0)
node _s1_valid_masked_T = eq(io.cpu.s1_kill, UInt<1>(0h0))
node s1_valid_masked = and(s1_valid, _s1_valid_masked_T)
node _s1_valid_not_nacked_T = eq(s1_nack, UInt<1>(0h0))
node s1_valid_not_nacked = and(s1_valid, _s1_valid_not_nacked_T)
node _s1_tlb_req_valid_T = and(io.tlb_port.req.ready, io.tlb_port.req.valid)
regreset s1_tlb_req_valid : UInt<1>, clock, reset, UInt<1>(0h0)
connect s1_tlb_req_valid, _s1_tlb_req_valid_T
regreset s2_tlb_req_valid : UInt<1>, clock, reset, UInt<1>(0h0)
connect s2_tlb_req_valid, s1_tlb_req_valid
node _s0_clk_en_T = eq(metaArb.io.out.bits.write, UInt<1>(0h0))
node s0_clk_en = and(metaArb.io.out.valid, _s0_clk_en_T)
wire s0_req : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}
connect s0_req, io.cpu.req.bits
node _s0_req_addr_T = shr(metaArb.io.out.bits.addr, 6)
node _s0_req_addr_T_1 = bits(io.cpu.req.bits.addr, 5, 0)
node _s0_req_addr_T_2 = cat(_s0_req_addr_T, _s0_req_addr_T_1)
connect s0_req.addr, _s0_req_addr_T_2
node _T = eq(metaArb.io.in[7].ready, UInt<1>(0h0))
when _T :
connect s0_req.phys, UInt<1>(0h1)
reg s1_req : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}, clock
when s0_clk_en :
connect s1_req, s0_req
node _s1_vaddr_T = shr(s1_req.addr, 11)
node _s1_vaddr_T_1 = bits(s1_req.addr, 10, 0)
node s1_vaddr = cat(_s1_vaddr_T, _s1_vaddr_T_1)
wire s0_tlb_req : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}
connect s0_tlb_req, io.tlb_port.req.bits
node _T_1 = and(io.tlb_port.req.ready, io.tlb_port.req.valid)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
connect s0_tlb_req.passthrough, s0_req.phys
connect s0_tlb_req.vaddr, s0_req.addr
connect s0_tlb_req.size, s0_req.size
connect s0_tlb_req.cmd, s0_req.cmd
connect s0_tlb_req.prv, s0_req.dprv
connect s0_tlb_req.v, s0_req.dv
node _s1_tlb_req_T = or(s0_clk_en, io.tlb_port.req.valid)
reg s1_tlb_req : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}, clock
when _s1_tlb_req_T :
connect s1_tlb_req, s0_tlb_req
node _s1_read_T = eq(s1_req.cmd, UInt<1>(0h0))
node _s1_read_T_1 = eq(s1_req.cmd, UInt<5>(0h10))
node _s1_read_T_2 = eq(s1_req.cmd, UInt<3>(0h6))
node _s1_read_T_3 = eq(s1_req.cmd, UInt<3>(0h7))
node _s1_read_T_4 = or(_s1_read_T, _s1_read_T_1)
node _s1_read_T_5 = or(_s1_read_T_4, _s1_read_T_2)
node _s1_read_T_6 = or(_s1_read_T_5, _s1_read_T_3)
node _s1_read_T_7 = eq(s1_req.cmd, UInt<3>(0h4))
node _s1_read_T_8 = eq(s1_req.cmd, UInt<4>(0h9))
node _s1_read_T_9 = eq(s1_req.cmd, UInt<4>(0ha))
node _s1_read_T_10 = eq(s1_req.cmd, UInt<4>(0hb))
node _s1_read_T_11 = or(_s1_read_T_7, _s1_read_T_8)
node _s1_read_T_12 = or(_s1_read_T_11, _s1_read_T_9)
node _s1_read_T_13 = or(_s1_read_T_12, _s1_read_T_10)
node _s1_read_T_14 = eq(s1_req.cmd, UInt<4>(0h8))
node _s1_read_T_15 = eq(s1_req.cmd, UInt<4>(0hc))
node _s1_read_T_16 = eq(s1_req.cmd, UInt<4>(0hd))
node _s1_read_T_17 = eq(s1_req.cmd, UInt<4>(0he))
node _s1_read_T_18 = eq(s1_req.cmd, UInt<4>(0hf))
node _s1_read_T_19 = or(_s1_read_T_14, _s1_read_T_15)
node _s1_read_T_20 = or(_s1_read_T_19, _s1_read_T_16)
node _s1_read_T_21 = or(_s1_read_T_20, _s1_read_T_17)
node _s1_read_T_22 = or(_s1_read_T_21, _s1_read_T_18)
node _s1_read_T_23 = or(_s1_read_T_13, _s1_read_T_22)
node s1_read = or(_s1_read_T_6, _s1_read_T_23)
node _s1_write_T = eq(s1_req.cmd, UInt<1>(0h1))
node _s1_write_T_1 = eq(s1_req.cmd, UInt<5>(0h11))
node _s1_write_T_2 = or(_s1_write_T, _s1_write_T_1)
node _s1_write_T_3 = eq(s1_req.cmd, UInt<3>(0h7))
node _s1_write_T_4 = or(_s1_write_T_2, _s1_write_T_3)
node _s1_write_T_5 = eq(s1_req.cmd, UInt<3>(0h4))
node _s1_write_T_6 = eq(s1_req.cmd, UInt<4>(0h9))
node _s1_write_T_7 = eq(s1_req.cmd, UInt<4>(0ha))
node _s1_write_T_8 = eq(s1_req.cmd, UInt<4>(0hb))
node _s1_write_T_9 = or(_s1_write_T_5, _s1_write_T_6)
node _s1_write_T_10 = or(_s1_write_T_9, _s1_write_T_7)
node _s1_write_T_11 = or(_s1_write_T_10, _s1_write_T_8)
node _s1_write_T_12 = eq(s1_req.cmd, UInt<4>(0h8))
node _s1_write_T_13 = eq(s1_req.cmd, UInt<4>(0hc))
node _s1_write_T_14 = eq(s1_req.cmd, UInt<4>(0hd))
node _s1_write_T_15 = eq(s1_req.cmd, UInt<4>(0he))
node _s1_write_T_16 = eq(s1_req.cmd, UInt<4>(0hf))
node _s1_write_T_17 = or(_s1_write_T_12, _s1_write_T_13)
node _s1_write_T_18 = or(_s1_write_T_17, _s1_write_T_14)
node _s1_write_T_19 = or(_s1_write_T_18, _s1_write_T_15)
node _s1_write_T_20 = or(_s1_write_T_19, _s1_write_T_16)
node _s1_write_T_21 = or(_s1_write_T_11, _s1_write_T_20)
node s1_write = or(_s1_write_T_4, _s1_write_T_21)
node s1_readwrite = or(s1_read, s1_write)
node _s1_sfence_T = eq(s1_req.cmd, UInt<5>(0h14))
node _s1_sfence_T_1 = eq(s1_req.cmd, UInt<5>(0h15))
node _s1_sfence_T_2 = or(_s1_sfence_T, _s1_sfence_T_1)
node _s1_sfence_T_3 = eq(s1_req.cmd, UInt<5>(0h16))
node s1_sfence = or(_s1_sfence_T_2, _s1_sfence_T_3)
node _s1_flush_line_T = eq(s1_req.cmd, UInt<3>(0h5))
node _s1_flush_line_T_1 = bits(s1_req.size, 0, 0)
node s1_flush_line = and(_s1_flush_line_T, _s1_flush_line_T_1)
reg s1_flush_valid : UInt<1>, clock
wire s1_waw_hazard : UInt<1>
regreset flushed : UInt<1>, clock, reset, UInt<1>(0h1)
regreset flushing : UInt<1>, clock, reset, UInt<1>(0h0)
reg flushing_req : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}, clock
regreset cached_grant_wait : UInt<1>, clock, reset, UInt<1>(0h0)
regreset resetting : UInt<1>, clock, reset, UInt<1>(0h0)
regreset flushCounter : UInt<5>, clock, reset, UInt<5>(0h0)
regreset release_ack_wait : UInt<1>, clock, reset, UInt<1>(0h0)
reg release_ack_addr : UInt<32>, clock
regreset release_state : UInt<4>, clock, reset, UInt<4>(0h0)
reg refill_way : UInt, clock
wire any_pstore_valid : UInt<1>
node _inWriteback_T = eq(release_state, UInt<4>(0h1))
node _inWriteback_T_1 = eq(release_state, UInt<4>(0h2))
node inWriteback = or(_inWriteback_T, _inWriteback_T_1)
wire releaseWay : UInt
node _io_cpu_req_ready_T = eq(release_state, UInt<4>(0h0))
node _io_cpu_req_ready_T_1 = eq(cached_grant_wait, UInt<1>(0h0))
node _io_cpu_req_ready_T_2 = and(_io_cpu_req_ready_T, _io_cpu_req_ready_T_1)
node _io_cpu_req_ready_T_3 = eq(s1_nack, UInt<1>(0h0))
node _io_cpu_req_ready_T_4 = and(_io_cpu_req_ready_T_2, _io_cpu_req_ready_T_3)
connect io.cpu.req.ready, _io_cpu_req_ready_T_4
wire _uncachedInFlight_WIRE : UInt<1>[1]
connect _uncachedInFlight_WIRE[0], UInt<1>(0h0)
regreset uncachedInFlight : UInt<1>[1], clock, reset, _uncachedInFlight_WIRE
reg uncachedReqs : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}[1], clock
wire uncachedResp : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}
invalidate uncachedResp.mask
invalidate uncachedResp.data
invalidate uncachedResp.no_xcpt
invalidate uncachedResp.no_alloc
invalidate uncachedResp.no_resp
invalidate uncachedResp.phys
invalidate uncachedResp.dv
invalidate uncachedResp.dprv
invalidate uncachedResp.signed
invalidate uncachedResp.size
invalidate uncachedResp.cmd
invalidate uncachedResp.tag
invalidate uncachedResp.addr
node _s0_read_T = eq(io.cpu.req.bits.cmd, UInt<1>(0h0))
node _s0_read_T_1 = eq(io.cpu.req.bits.cmd, UInt<5>(0h10))
node _s0_read_T_2 = eq(io.cpu.req.bits.cmd, UInt<3>(0h6))
node _s0_read_T_3 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7))
node _s0_read_T_4 = or(_s0_read_T, _s0_read_T_1)
node _s0_read_T_5 = or(_s0_read_T_4, _s0_read_T_2)
node _s0_read_T_6 = or(_s0_read_T_5, _s0_read_T_3)
node _s0_read_T_7 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4))
node _s0_read_T_8 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9))
node _s0_read_T_9 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha))
node _s0_read_T_10 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb))
node _s0_read_T_11 = or(_s0_read_T_7, _s0_read_T_8)
node _s0_read_T_12 = or(_s0_read_T_11, _s0_read_T_9)
node _s0_read_T_13 = or(_s0_read_T_12, _s0_read_T_10)
node _s0_read_T_14 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8))
node _s0_read_T_15 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc))
node _s0_read_T_16 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd))
node _s0_read_T_17 = eq(io.cpu.req.bits.cmd, UInt<4>(0he))
node _s0_read_T_18 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf))
node _s0_read_T_19 = or(_s0_read_T_14, _s0_read_T_15)
node _s0_read_T_20 = or(_s0_read_T_19, _s0_read_T_16)
node _s0_read_T_21 = or(_s0_read_T_20, _s0_read_T_17)
node _s0_read_T_22 = or(_s0_read_T_21, _s0_read_T_18)
node _s0_read_T_23 = or(_s0_read_T_13, _s0_read_T_22)
node s0_read = or(_s0_read_T_6, _s0_read_T_23)
node _dataArb_io_in_3_valid_res_T = eq(io.cpu.req.bits.cmd, UInt<1>(0h1))
node _dataArb_io_in_3_valid_res_T_1 = eq(io.cpu.req.bits.cmd, UInt<2>(0h3))
node _dataArb_io_in_3_valid_res_T_2 = or(_dataArb_io_in_3_valid_res_T, _dataArb_io_in_3_valid_res_T_1)
node _dataArb_io_in_3_valid_res_T_3 = eq(_dataArb_io_in_3_valid_res_T_2, UInt<1>(0h0))
node _dataArb_io_in_3_valid_res_T_4 = lt(io.cpu.req.bits.size, UInt<1>(0h0))
node dataArb_io_in_3_valid_res = or(_dataArb_io_in_3_valid_res_T_3, _dataArb_io_in_3_valid_res_T_4)
node _dataArb_io_in_3_valid_T = eq(io.cpu.req.bits.cmd, UInt<1>(0h0))
node _dataArb_io_in_3_valid_T_1 = eq(io.cpu.req.bits.cmd, UInt<5>(0h10))
node _dataArb_io_in_3_valid_T_2 = eq(io.cpu.req.bits.cmd, UInt<3>(0h6))
node _dataArb_io_in_3_valid_T_3 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7))
node _dataArb_io_in_3_valid_T_4 = or(_dataArb_io_in_3_valid_T, _dataArb_io_in_3_valid_T_1)
node _dataArb_io_in_3_valid_T_5 = or(_dataArb_io_in_3_valid_T_4, _dataArb_io_in_3_valid_T_2)
node _dataArb_io_in_3_valid_T_6 = or(_dataArb_io_in_3_valid_T_5, _dataArb_io_in_3_valid_T_3)
node _dataArb_io_in_3_valid_T_7 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4))
node _dataArb_io_in_3_valid_T_8 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9))
node _dataArb_io_in_3_valid_T_9 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha))
node _dataArb_io_in_3_valid_T_10 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb))
node _dataArb_io_in_3_valid_T_11 = or(_dataArb_io_in_3_valid_T_7, _dataArb_io_in_3_valid_T_8)
node _dataArb_io_in_3_valid_T_12 = or(_dataArb_io_in_3_valid_T_11, _dataArb_io_in_3_valid_T_9)
node _dataArb_io_in_3_valid_T_13 = or(_dataArb_io_in_3_valid_T_12, _dataArb_io_in_3_valid_T_10)
node _dataArb_io_in_3_valid_T_14 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8))
node _dataArb_io_in_3_valid_T_15 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc))
node _dataArb_io_in_3_valid_T_16 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd))
node _dataArb_io_in_3_valid_T_17 = eq(io.cpu.req.bits.cmd, UInt<4>(0he))
node _dataArb_io_in_3_valid_T_18 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf))
node _dataArb_io_in_3_valid_T_19 = or(_dataArb_io_in_3_valid_T_14, _dataArb_io_in_3_valid_T_15)
node _dataArb_io_in_3_valid_T_20 = or(_dataArb_io_in_3_valid_T_19, _dataArb_io_in_3_valid_T_16)
node _dataArb_io_in_3_valid_T_21 = or(_dataArb_io_in_3_valid_T_20, _dataArb_io_in_3_valid_T_17)
node _dataArb_io_in_3_valid_T_22 = or(_dataArb_io_in_3_valid_T_21, _dataArb_io_in_3_valid_T_18)
node _dataArb_io_in_3_valid_T_23 = or(_dataArb_io_in_3_valid_T_13, _dataArb_io_in_3_valid_T_22)
node _dataArb_io_in_3_valid_T_24 = or(_dataArb_io_in_3_valid_T_6, _dataArb_io_in_3_valid_T_23)
node _dataArb_io_in_3_valid_T_25 = eq(io.cpu.req.bits.cmd, UInt<1>(0h1))
node _dataArb_io_in_3_valid_T_26 = eq(io.cpu.req.bits.cmd, UInt<5>(0h11))
node _dataArb_io_in_3_valid_T_27 = or(_dataArb_io_in_3_valid_T_25, _dataArb_io_in_3_valid_T_26)
node _dataArb_io_in_3_valid_T_28 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7))
node _dataArb_io_in_3_valid_T_29 = or(_dataArb_io_in_3_valid_T_27, _dataArb_io_in_3_valid_T_28)
node _dataArb_io_in_3_valid_T_30 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4))
node _dataArb_io_in_3_valid_T_31 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9))
node _dataArb_io_in_3_valid_T_32 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha))
node _dataArb_io_in_3_valid_T_33 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb))
node _dataArb_io_in_3_valid_T_34 = or(_dataArb_io_in_3_valid_T_30, _dataArb_io_in_3_valid_T_31)
node _dataArb_io_in_3_valid_T_35 = or(_dataArb_io_in_3_valid_T_34, _dataArb_io_in_3_valid_T_32)
node _dataArb_io_in_3_valid_T_36 = or(_dataArb_io_in_3_valid_T_35, _dataArb_io_in_3_valid_T_33)
node _dataArb_io_in_3_valid_T_37 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8))
node _dataArb_io_in_3_valid_T_38 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc))
node _dataArb_io_in_3_valid_T_39 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd))
node _dataArb_io_in_3_valid_T_40 = eq(io.cpu.req.bits.cmd, UInt<4>(0he))
node _dataArb_io_in_3_valid_T_41 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf))
node _dataArb_io_in_3_valid_T_42 = or(_dataArb_io_in_3_valid_T_37, _dataArb_io_in_3_valid_T_38)
node _dataArb_io_in_3_valid_T_43 = or(_dataArb_io_in_3_valid_T_42, _dataArb_io_in_3_valid_T_39)
node _dataArb_io_in_3_valid_T_44 = or(_dataArb_io_in_3_valid_T_43, _dataArb_io_in_3_valid_T_40)
node _dataArb_io_in_3_valid_T_45 = or(_dataArb_io_in_3_valid_T_44, _dataArb_io_in_3_valid_T_41)
node _dataArb_io_in_3_valid_T_46 = or(_dataArb_io_in_3_valid_T_36, _dataArb_io_in_3_valid_T_45)
node _dataArb_io_in_3_valid_T_47 = or(_dataArb_io_in_3_valid_T_29, _dataArb_io_in_3_valid_T_46)
node _dataArb_io_in_3_valid_T_48 = eq(io.cpu.req.bits.cmd, UInt<5>(0h11))
node _dataArb_io_in_3_valid_T_49 = lt(io.cpu.req.bits.size, UInt<1>(0h0))
node _dataArb_io_in_3_valid_T_50 = or(_dataArb_io_in_3_valid_T_48, _dataArb_io_in_3_valid_T_49)
node _dataArb_io_in_3_valid_T_51 = and(_dataArb_io_in_3_valid_T_47, _dataArb_io_in_3_valid_T_50)
node _dataArb_io_in_3_valid_T_52 = or(_dataArb_io_in_3_valid_T_24, _dataArb_io_in_3_valid_T_51)
node _dataArb_io_in_3_valid_T_53 = eq(_dataArb_io_in_3_valid_T_52, UInt<1>(0h0))
node _dataArb_io_in_3_valid_T_54 = or(_dataArb_io_in_3_valid_T_53, dataArb_io_in_3_valid_res)
node _dataArb_io_in_3_valid_T_55 = asUInt(reset)
node _dataArb_io_in_3_valid_T_56 = eq(_dataArb_io_in_3_valid_T_55, UInt<1>(0h0))
when _dataArb_io_in_3_valid_T_56 :
node _dataArb_io_in_3_valid_T_57 = eq(_dataArb_io_in_3_valid_T_54, UInt<1>(0h0))
when _dataArb_io_in_3_valid_T_57 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:1186 assert(!needsRead(req) || res)\n") : dataArb_io_in_3_valid_printf
assert(clock, _dataArb_io_in_3_valid_T_54, UInt<1>(0h1), "") : dataArb_io_in_3_valid_assert
node _dataArb_io_in_3_valid_T_58 = and(io.cpu.req.valid, dataArb_io_in_3_valid_res)
connect dataArb.io.in[3].valid, _dataArb_io_in_3_valid_T_58
connect dataArb.io.in[3].bits.way_en, dataArb.io.in[1].bits.way_en
connect dataArb.io.in[3].bits.eccMask, dataArb.io.in[1].bits.eccMask
connect dataArb.io.in[3].bits.wordMask, dataArb.io.in[1].bits.wordMask
connect dataArb.io.in[3].bits.wdata, dataArb.io.in[1].bits.wdata
connect dataArb.io.in[3].bits.write, dataArb.io.in[1].bits.write
connect dataArb.io.in[3].bits.addr, dataArb.io.in[1].bits.addr
connect dataArb.io.in[3].bits.write, UInt<1>(0h0)
node _dataArb_io_in_3_bits_addr_T = shr(io.cpu.req.bits.addr, 11)
node _dataArb_io_in_3_bits_addr_T_1 = bits(io.cpu.req.bits.addr, 10, 0)
node _dataArb_io_in_3_bits_addr_T_2 = cat(_dataArb_io_in_3_bits_addr_T, _dataArb_io_in_3_bits_addr_T_1)
connect dataArb.io.in[3].bits.addr, _dataArb_io_in_3_bits_addr_T_2
node _dataArb_io_in_3_bits_wordMask_T = mux(UInt<1>(0h1), UInt<8>(0hff), UInt<8>(0h0))
connect dataArb.io.in[3].bits.wordMask, _dataArb_io_in_3_bits_wordMask_T
node _dataArb_io_in_3_bits_eccMask_T = not(UInt<8>(0h0))
connect dataArb.io.in[3].bits.eccMask, _dataArb_io_in_3_bits_eccMask_T
node _dataArb_io_in_3_bits_way_en_T = not(UInt<1>(0h0))
connect dataArb.io.in[3].bits.way_en, _dataArb_io_in_3_bits_way_en_T
node _T_3 = eq(dataArb.io.in[3].ready, UInt<1>(0h0))
node _T_4 = and(_T_3, s0_read)
when _T_4 :
connect io.cpu.req.ready, UInt<1>(0h0)
node _s1_did_read_T = eq(io.cpu.req.bits.cmd, UInt<1>(0h0))
node _s1_did_read_T_1 = eq(io.cpu.req.bits.cmd, UInt<5>(0h10))
node _s1_did_read_T_2 = eq(io.cpu.req.bits.cmd, UInt<3>(0h6))
node _s1_did_read_T_3 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7))
node _s1_did_read_T_4 = or(_s1_did_read_T, _s1_did_read_T_1)
node _s1_did_read_T_5 = or(_s1_did_read_T_4, _s1_did_read_T_2)
node _s1_did_read_T_6 = or(_s1_did_read_T_5, _s1_did_read_T_3)
node _s1_did_read_T_7 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4))
node _s1_did_read_T_8 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9))
node _s1_did_read_T_9 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha))
node _s1_did_read_T_10 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb))
node _s1_did_read_T_11 = or(_s1_did_read_T_7, _s1_did_read_T_8)
node _s1_did_read_T_12 = or(_s1_did_read_T_11, _s1_did_read_T_9)
node _s1_did_read_T_13 = or(_s1_did_read_T_12, _s1_did_read_T_10)
node _s1_did_read_T_14 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8))
node _s1_did_read_T_15 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc))
node _s1_did_read_T_16 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd))
node _s1_did_read_T_17 = eq(io.cpu.req.bits.cmd, UInt<4>(0he))
node _s1_did_read_T_18 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf))
node _s1_did_read_T_19 = or(_s1_did_read_T_14, _s1_did_read_T_15)
node _s1_did_read_T_20 = or(_s1_did_read_T_19, _s1_did_read_T_16)
node _s1_did_read_T_21 = or(_s1_did_read_T_20, _s1_did_read_T_17)
node _s1_did_read_T_22 = or(_s1_did_read_T_21, _s1_did_read_T_18)
node _s1_did_read_T_23 = or(_s1_did_read_T_13, _s1_did_read_T_22)
node _s1_did_read_T_24 = or(_s1_did_read_T_6, _s1_did_read_T_23)
node _s1_did_read_T_25 = eq(io.cpu.req.bits.cmd, UInt<1>(0h1))
node _s1_did_read_T_26 = eq(io.cpu.req.bits.cmd, UInt<5>(0h11))
node _s1_did_read_T_27 = or(_s1_did_read_T_25, _s1_did_read_T_26)
node _s1_did_read_T_28 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7))
node _s1_did_read_T_29 = or(_s1_did_read_T_27, _s1_did_read_T_28)
node _s1_did_read_T_30 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4))
node _s1_did_read_T_31 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9))
node _s1_did_read_T_32 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha))
node _s1_did_read_T_33 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb))
node _s1_did_read_T_34 = or(_s1_did_read_T_30, _s1_did_read_T_31)
node _s1_did_read_T_35 = or(_s1_did_read_T_34, _s1_did_read_T_32)
node _s1_did_read_T_36 = or(_s1_did_read_T_35, _s1_did_read_T_33)
node _s1_did_read_T_37 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8))
node _s1_did_read_T_38 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc))
node _s1_did_read_T_39 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd))
node _s1_did_read_T_40 = eq(io.cpu.req.bits.cmd, UInt<4>(0he))
node _s1_did_read_T_41 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf))
node _s1_did_read_T_42 = or(_s1_did_read_T_37, _s1_did_read_T_38)
node _s1_did_read_T_43 = or(_s1_did_read_T_42, _s1_did_read_T_39)
node _s1_did_read_T_44 = or(_s1_did_read_T_43, _s1_did_read_T_40)
node _s1_did_read_T_45 = or(_s1_did_read_T_44, _s1_did_read_T_41)
node _s1_did_read_T_46 = or(_s1_did_read_T_36, _s1_did_read_T_45)
node _s1_did_read_T_47 = or(_s1_did_read_T_29, _s1_did_read_T_46)
node _s1_did_read_T_48 = eq(io.cpu.req.bits.cmd, UInt<5>(0h11))
node _s1_did_read_T_49 = lt(io.cpu.req.bits.size, UInt<1>(0h0))
node _s1_did_read_T_50 = or(_s1_did_read_T_48, _s1_did_read_T_49)
node _s1_did_read_T_51 = and(_s1_did_read_T_47, _s1_did_read_T_50)
node _s1_did_read_T_52 = or(_s1_did_read_T_24, _s1_did_read_T_51)
node _s1_did_read_T_53 = and(io.cpu.req.valid, _s1_did_read_T_52)
node _s1_did_read_T_54 = and(dataArb.io.in[3].ready, _s1_did_read_T_53)
reg s1_did_read : UInt<1>, clock
when s0_clk_en :
connect s1_did_read, _s1_did_read_T_54
reg s1_read_mask : UInt<1>, clock
when s0_clk_en :
connect s1_read_mask, dataArb.io.in[3].bits.wordMask
connect metaArb.io.in[7].valid, io.cpu.req.valid
connect metaArb.io.in[7].bits.write, UInt<1>(0h0)
node _metaArb_io_in_7_bits_idx_T = bits(dataArb.io.in[3].bits.addr, 10, 6)
connect metaArb.io.in[7].bits.idx, _metaArb_io_in_7_bits_idx_T
connect metaArb.io.in[7].bits.addr, io.cpu.req.bits.addr
connect metaArb.io.in[7].bits.way_en, metaArb.io.in[4].bits.way_en
connect metaArb.io.in[7].bits.data, metaArb.io.in[4].bits.data
node _T_5 = eq(metaArb.io.in[7].ready, UInt<1>(0h0))
when _T_5 :
connect io.cpu.req.ready, UInt<1>(0h0)
node _s1_cmd_uses_tlb_T = or(s1_readwrite, s1_flush_line)
node _s1_cmd_uses_tlb_T_1 = eq(s1_req.cmd, UInt<5>(0h17))
node s1_cmd_uses_tlb = or(_s1_cmd_uses_tlb_T, _s1_cmd_uses_tlb_T_1)
connect tlb.io.ptw.customCSRs, io.ptw.customCSRs
connect tlb.io.ptw.pmp[0], io.ptw.pmp[0]
connect tlb.io.ptw.pmp[1], io.ptw.pmp[1]
connect tlb.io.ptw.pmp[2], io.ptw.pmp[2]
connect tlb.io.ptw.pmp[3], io.ptw.pmp[3]
connect tlb.io.ptw.pmp[4], io.ptw.pmp[4]
connect tlb.io.ptw.pmp[5], io.ptw.pmp[5]
connect tlb.io.ptw.pmp[6], io.ptw.pmp[6]
connect tlb.io.ptw.pmp[7], io.ptw.pmp[7]
connect tlb.io.ptw.gstatus, io.ptw.gstatus
connect tlb.io.ptw.hstatus, io.ptw.hstatus
connect tlb.io.ptw.status, io.ptw.status
connect tlb.io.ptw.vsatp, io.ptw.vsatp
connect tlb.io.ptw.hgatp, io.ptw.hgatp
connect tlb.io.ptw.ptbr, io.ptw.ptbr
connect tlb.io.ptw.resp, io.ptw.resp
connect io.ptw.req.bits, tlb.io.ptw.req.bits
connect io.ptw.req.valid, tlb.io.ptw.req.valid
connect tlb.io.ptw.req.ready, io.ptw.req.ready
node _tlb_io_kill_T = and(s2_tlb_req_valid, io.tlb_port.s2_kill)
node _tlb_io_kill_T_1 = or(io.cpu.s2_kill, _tlb_io_kill_T)
connect tlb.io.kill, _tlb_io_kill_T_1
node _tlb_io_req_valid_T = eq(io.cpu.s1_kill, UInt<1>(0h0))
node _tlb_io_req_valid_T_1 = and(s1_valid, _tlb_io_req_valid_T)
node _tlb_io_req_valid_T_2 = and(_tlb_io_req_valid_T_1, s1_cmd_uses_tlb)
node _tlb_io_req_valid_T_3 = or(s1_tlb_req_valid, _tlb_io_req_valid_T_2)
connect tlb.io.req.valid, _tlb_io_req_valid_T_3
connect tlb.io.req.bits.v, s1_tlb_req.v
connect tlb.io.req.bits.prv, s1_tlb_req.prv
connect tlb.io.req.bits.cmd, s1_tlb_req.cmd
connect tlb.io.req.bits.size, s1_tlb_req.size
connect tlb.io.req.bits.passthrough, s1_tlb_req.passthrough
connect tlb.io.req.bits.vaddr, s1_tlb_req.vaddr
node _T_6 = eq(tlb.io.req.ready, UInt<1>(0h0))
node _T_7 = eq(tlb.io.ptw.resp.valid, UInt<1>(0h0))
node _T_8 = and(_T_6, _T_7)
node _T_9 = eq(io.cpu.req.bits.phys, UInt<1>(0h0))
node _T_10 = and(_T_8, _T_9)
when _T_10 :
connect io.cpu.req.ready, UInt<1>(0h0)
node _T_11 = eq(s1_tlb_req_valid, UInt<1>(0h0))
node _T_12 = and(_T_11, s1_valid)
node _T_13 = and(_T_12, s1_cmd_uses_tlb)
node _T_14 = and(_T_13, tlb.io.resp.miss)
when _T_14 :
connect s1_nack, UInt<1>(0h1)
node _tlb_io_sfence_valid_T = eq(io.cpu.s1_kill, UInt<1>(0h0))
node _tlb_io_sfence_valid_T_1 = and(s1_valid, _tlb_io_sfence_valid_T)
node _tlb_io_sfence_valid_T_2 = and(_tlb_io_sfence_valid_T_1, s1_sfence)
connect tlb.io.sfence.valid, _tlb_io_sfence_valid_T_2
node _tlb_io_sfence_bits_rs1_T = bits(s1_req.size, 0, 0)
connect tlb.io.sfence.bits.rs1, _tlb_io_sfence_bits_rs1_T
node _tlb_io_sfence_bits_rs2_T = bits(s1_req.size, 1, 1)
connect tlb.io.sfence.bits.rs2, _tlb_io_sfence_bits_rs2_T
connect tlb.io.sfence.bits.asid, io.cpu.s1_data.data
connect tlb.io.sfence.bits.addr, s1_req.addr
node _tlb_io_sfence_bits_hv_T = eq(s1_req.cmd, UInt<5>(0h15))
connect tlb.io.sfence.bits.hv, _tlb_io_sfence_bits_hv_T
node _tlb_io_sfence_bits_hg_T = eq(s1_req.cmd, UInt<5>(0h16))
connect tlb.io.sfence.bits.hg, _tlb_io_sfence_bits_hg_T
connect io.tlb_port.req.ready, clock_en_reg
connect io.tlb_port.s1_resp, tlb.io.resp
node _T_15 = and(s1_tlb_req_valid, s1_valid)
node _T_16 = and(s1_req.phys, s1_req.no_xcpt)
node _T_17 = eq(_T_16, UInt<1>(0h0))
node _T_18 = and(_T_15, _T_17)
when _T_18 :
connect s1_nack, UInt<1>(0h1)
invalidate pma_checker.io.kill
invalidate pma_checker.io.ptw.customCSRs.csrs[0].sdata
invalidate pma_checker.io.ptw.customCSRs.csrs[0].set
invalidate pma_checker.io.ptw.customCSRs.csrs[0].stall
invalidate pma_checker.io.ptw.customCSRs.csrs[0].value
invalidate pma_checker.io.ptw.customCSRs.csrs[0].wdata
invalidate pma_checker.io.ptw.customCSRs.csrs[0].wen
invalidate pma_checker.io.ptw.customCSRs.csrs[0].ren
invalidate pma_checker.io.ptw.customCSRs.csrs[1].sdata
invalidate pma_checker.io.ptw.customCSRs.csrs[1].set
invalidate pma_checker.io.ptw.customCSRs.csrs[1].stall
invalidate pma_checker.io.ptw.customCSRs.csrs[1].value
invalidate pma_checker.io.ptw.customCSRs.csrs[1].wdata
invalidate pma_checker.io.ptw.customCSRs.csrs[1].wen
invalidate pma_checker.io.ptw.customCSRs.csrs[1].ren
invalidate pma_checker.io.ptw.customCSRs.csrs[2].sdata
invalidate pma_checker.io.ptw.customCSRs.csrs[2].set
invalidate pma_checker.io.ptw.customCSRs.csrs[2].stall
invalidate pma_checker.io.ptw.customCSRs.csrs[2].value
invalidate pma_checker.io.ptw.customCSRs.csrs[2].wdata
invalidate pma_checker.io.ptw.customCSRs.csrs[2].wen
invalidate pma_checker.io.ptw.customCSRs.csrs[2].ren
invalidate pma_checker.io.ptw.customCSRs.csrs[3].sdata
invalidate pma_checker.io.ptw.customCSRs.csrs[3].set
invalidate pma_checker.io.ptw.customCSRs.csrs[3].stall
invalidate pma_checker.io.ptw.customCSRs.csrs[3].value
invalidate pma_checker.io.ptw.customCSRs.csrs[3].wdata
invalidate pma_checker.io.ptw.customCSRs.csrs[3].wen
invalidate pma_checker.io.ptw.customCSRs.csrs[3].ren
invalidate pma_checker.io.ptw.pmp[0].mask
invalidate pma_checker.io.ptw.pmp[0].addr
invalidate pma_checker.io.ptw.pmp[0].cfg.r
invalidate pma_checker.io.ptw.pmp[0].cfg.w
invalidate pma_checker.io.ptw.pmp[0].cfg.x
invalidate pma_checker.io.ptw.pmp[0].cfg.a
invalidate pma_checker.io.ptw.pmp[0].cfg.res
invalidate pma_checker.io.ptw.pmp[0].cfg.l
invalidate pma_checker.io.ptw.pmp[1].mask
invalidate pma_checker.io.ptw.pmp[1].addr
invalidate pma_checker.io.ptw.pmp[1].cfg.r
invalidate pma_checker.io.ptw.pmp[1].cfg.w
invalidate pma_checker.io.ptw.pmp[1].cfg.x
invalidate pma_checker.io.ptw.pmp[1].cfg.a
invalidate pma_checker.io.ptw.pmp[1].cfg.res
invalidate pma_checker.io.ptw.pmp[1].cfg.l
invalidate pma_checker.io.ptw.pmp[2].mask
invalidate pma_checker.io.ptw.pmp[2].addr
invalidate pma_checker.io.ptw.pmp[2].cfg.r
invalidate pma_checker.io.ptw.pmp[2].cfg.w
invalidate pma_checker.io.ptw.pmp[2].cfg.x
invalidate pma_checker.io.ptw.pmp[2].cfg.a
invalidate pma_checker.io.ptw.pmp[2].cfg.res
invalidate pma_checker.io.ptw.pmp[2].cfg.l
invalidate pma_checker.io.ptw.pmp[3].mask
invalidate pma_checker.io.ptw.pmp[3].addr
invalidate pma_checker.io.ptw.pmp[3].cfg.r
invalidate pma_checker.io.ptw.pmp[3].cfg.w
invalidate pma_checker.io.ptw.pmp[3].cfg.x
invalidate pma_checker.io.ptw.pmp[3].cfg.a
invalidate pma_checker.io.ptw.pmp[3].cfg.res
invalidate pma_checker.io.ptw.pmp[3].cfg.l
invalidate pma_checker.io.ptw.pmp[4].mask
invalidate pma_checker.io.ptw.pmp[4].addr
invalidate pma_checker.io.ptw.pmp[4].cfg.r
invalidate pma_checker.io.ptw.pmp[4].cfg.w
invalidate pma_checker.io.ptw.pmp[4].cfg.x
invalidate pma_checker.io.ptw.pmp[4].cfg.a
invalidate pma_checker.io.ptw.pmp[4].cfg.res
invalidate pma_checker.io.ptw.pmp[4].cfg.l
invalidate pma_checker.io.ptw.pmp[5].mask
invalidate pma_checker.io.ptw.pmp[5].addr
invalidate pma_checker.io.ptw.pmp[5].cfg.r
invalidate pma_checker.io.ptw.pmp[5].cfg.w
invalidate pma_checker.io.ptw.pmp[5].cfg.x
invalidate pma_checker.io.ptw.pmp[5].cfg.a
invalidate pma_checker.io.ptw.pmp[5].cfg.res
invalidate pma_checker.io.ptw.pmp[5].cfg.l
invalidate pma_checker.io.ptw.pmp[6].mask
invalidate pma_checker.io.ptw.pmp[6].addr
invalidate pma_checker.io.ptw.pmp[6].cfg.r
invalidate pma_checker.io.ptw.pmp[6].cfg.w
invalidate pma_checker.io.ptw.pmp[6].cfg.x
invalidate pma_checker.io.ptw.pmp[6].cfg.a
invalidate pma_checker.io.ptw.pmp[6].cfg.res
invalidate pma_checker.io.ptw.pmp[6].cfg.l
invalidate pma_checker.io.ptw.pmp[7].mask
invalidate pma_checker.io.ptw.pmp[7].addr
invalidate pma_checker.io.ptw.pmp[7].cfg.r
invalidate pma_checker.io.ptw.pmp[7].cfg.w
invalidate pma_checker.io.ptw.pmp[7].cfg.x
invalidate pma_checker.io.ptw.pmp[7].cfg.a
invalidate pma_checker.io.ptw.pmp[7].cfg.res
invalidate pma_checker.io.ptw.pmp[7].cfg.l
invalidate pma_checker.io.ptw.gstatus.uie
invalidate pma_checker.io.ptw.gstatus.sie
invalidate pma_checker.io.ptw.gstatus.hie
invalidate pma_checker.io.ptw.gstatus.mie
invalidate pma_checker.io.ptw.gstatus.upie
invalidate pma_checker.io.ptw.gstatus.spie
invalidate pma_checker.io.ptw.gstatus.ube
invalidate pma_checker.io.ptw.gstatus.mpie
invalidate pma_checker.io.ptw.gstatus.spp
invalidate pma_checker.io.ptw.gstatus.vs
invalidate pma_checker.io.ptw.gstatus.mpp
invalidate pma_checker.io.ptw.gstatus.fs
invalidate pma_checker.io.ptw.gstatus.xs
invalidate pma_checker.io.ptw.gstatus.mprv
invalidate pma_checker.io.ptw.gstatus.sum
invalidate pma_checker.io.ptw.gstatus.mxr
invalidate pma_checker.io.ptw.gstatus.tvm
invalidate pma_checker.io.ptw.gstatus.tw
invalidate pma_checker.io.ptw.gstatus.tsr
invalidate pma_checker.io.ptw.gstatus.zero1
invalidate pma_checker.io.ptw.gstatus.sd_rv32
invalidate pma_checker.io.ptw.gstatus.uxl
invalidate pma_checker.io.ptw.gstatus.sxl
invalidate pma_checker.io.ptw.gstatus.sbe
invalidate pma_checker.io.ptw.gstatus.mbe
invalidate pma_checker.io.ptw.gstatus.gva
invalidate pma_checker.io.ptw.gstatus.mpv
invalidate pma_checker.io.ptw.gstatus.zero2
invalidate pma_checker.io.ptw.gstatus.sd
invalidate pma_checker.io.ptw.gstatus.v
invalidate pma_checker.io.ptw.gstatus.prv
invalidate pma_checker.io.ptw.gstatus.dv
invalidate pma_checker.io.ptw.gstatus.dprv
invalidate pma_checker.io.ptw.gstatus.isa
invalidate pma_checker.io.ptw.gstatus.wfi
invalidate pma_checker.io.ptw.gstatus.cease
invalidate pma_checker.io.ptw.gstatus.debug
invalidate pma_checker.io.ptw.hstatus.zero1
invalidate pma_checker.io.ptw.hstatus.vsbe
invalidate pma_checker.io.ptw.hstatus.gva
invalidate pma_checker.io.ptw.hstatus.spv
invalidate pma_checker.io.ptw.hstatus.spvp
invalidate pma_checker.io.ptw.hstatus.hu
invalidate pma_checker.io.ptw.hstatus.zero2
invalidate pma_checker.io.ptw.hstatus.vgein
invalidate pma_checker.io.ptw.hstatus.zero3
invalidate pma_checker.io.ptw.hstatus.vtvm
invalidate pma_checker.io.ptw.hstatus.vtw
invalidate pma_checker.io.ptw.hstatus.vtsr
invalidate pma_checker.io.ptw.hstatus.zero5
invalidate pma_checker.io.ptw.hstatus.vsxl
invalidate pma_checker.io.ptw.hstatus.zero6
invalidate pma_checker.io.ptw.status.uie
invalidate pma_checker.io.ptw.status.sie
invalidate pma_checker.io.ptw.status.hie
invalidate pma_checker.io.ptw.status.mie
invalidate pma_checker.io.ptw.status.upie
invalidate pma_checker.io.ptw.status.spie
invalidate pma_checker.io.ptw.status.ube
invalidate pma_checker.io.ptw.status.mpie
invalidate pma_checker.io.ptw.status.spp
invalidate pma_checker.io.ptw.status.vs
invalidate pma_checker.io.ptw.status.mpp
invalidate pma_checker.io.ptw.status.fs
invalidate pma_checker.io.ptw.status.xs
invalidate pma_checker.io.ptw.status.mprv
invalidate pma_checker.io.ptw.status.sum
invalidate pma_checker.io.ptw.status.mxr
invalidate pma_checker.io.ptw.status.tvm
invalidate pma_checker.io.ptw.status.tw
invalidate pma_checker.io.ptw.status.tsr
invalidate pma_checker.io.ptw.status.zero1
invalidate pma_checker.io.ptw.status.sd_rv32
invalidate pma_checker.io.ptw.status.uxl
invalidate pma_checker.io.ptw.status.sxl
invalidate pma_checker.io.ptw.status.sbe
invalidate pma_checker.io.ptw.status.mbe
invalidate pma_checker.io.ptw.status.gva
invalidate pma_checker.io.ptw.status.mpv
invalidate pma_checker.io.ptw.status.zero2
invalidate pma_checker.io.ptw.status.sd
invalidate pma_checker.io.ptw.status.v
invalidate pma_checker.io.ptw.status.prv
invalidate pma_checker.io.ptw.status.dv
invalidate pma_checker.io.ptw.status.dprv
invalidate pma_checker.io.ptw.status.isa
invalidate pma_checker.io.ptw.status.wfi
invalidate pma_checker.io.ptw.status.cease
invalidate pma_checker.io.ptw.status.debug
invalidate pma_checker.io.ptw.vsatp.ppn
invalidate pma_checker.io.ptw.vsatp.asid
invalidate pma_checker.io.ptw.vsatp.mode
invalidate pma_checker.io.ptw.hgatp.ppn
invalidate pma_checker.io.ptw.hgatp.asid
invalidate pma_checker.io.ptw.hgatp.mode
invalidate pma_checker.io.ptw.ptbr.ppn
invalidate pma_checker.io.ptw.ptbr.asid
invalidate pma_checker.io.ptw.ptbr.mode
invalidate pma_checker.io.ptw.resp.bits.gpa_is_pte
invalidate pma_checker.io.ptw.resp.bits.gpa.bits
invalidate pma_checker.io.ptw.resp.bits.gpa.valid
invalidate pma_checker.io.ptw.resp.bits.homogeneous
invalidate pma_checker.io.ptw.resp.bits.fragmented_superpage
invalidate pma_checker.io.ptw.resp.bits.level
invalidate pma_checker.io.ptw.resp.bits.pte.v
invalidate pma_checker.io.ptw.resp.bits.pte.r
invalidate pma_checker.io.ptw.resp.bits.pte.w
invalidate pma_checker.io.ptw.resp.bits.pte.x
invalidate pma_checker.io.ptw.resp.bits.pte.u
invalidate pma_checker.io.ptw.resp.bits.pte.g
invalidate pma_checker.io.ptw.resp.bits.pte.a
invalidate pma_checker.io.ptw.resp.bits.pte.d
invalidate pma_checker.io.ptw.resp.bits.pte.reserved_for_software
invalidate pma_checker.io.ptw.resp.bits.pte.ppn
invalidate pma_checker.io.ptw.resp.bits.pte.reserved_for_future
invalidate pma_checker.io.ptw.resp.bits.hx
invalidate pma_checker.io.ptw.resp.bits.hw
invalidate pma_checker.io.ptw.resp.bits.hr
invalidate pma_checker.io.ptw.resp.bits.gf
invalidate pma_checker.io.ptw.resp.bits.pf
invalidate pma_checker.io.ptw.resp.bits.ae_final
invalidate pma_checker.io.ptw.resp.bits.ae_ptw
invalidate pma_checker.io.ptw.resp.valid
invalidate pma_checker.io.ptw.req.bits.bits.stage2
invalidate pma_checker.io.ptw.req.bits.bits.vstage1
invalidate pma_checker.io.ptw.req.bits.bits.need_gpa
invalidate pma_checker.io.ptw.req.bits.bits.addr
invalidate pma_checker.io.ptw.req.bits.valid
invalidate pma_checker.io.ptw.req.valid
invalidate pma_checker.io.ptw.req.ready
invalidate pma_checker.io.sfence.bits.hg
invalidate pma_checker.io.sfence.bits.hv
invalidate pma_checker.io.sfence.bits.asid
invalidate pma_checker.io.sfence.bits.addr
invalidate pma_checker.io.sfence.bits.rs2
invalidate pma_checker.io.sfence.bits.rs1
invalidate pma_checker.io.sfence.valid
invalidate pma_checker.io.resp.cmd
invalidate pma_checker.io.resp.size
invalidate pma_checker.io.resp.prefetchable
invalidate pma_checker.io.resp.must_alloc
invalidate pma_checker.io.resp.cacheable
invalidate pma_checker.io.resp.ma.inst
invalidate pma_checker.io.resp.ma.st
invalidate pma_checker.io.resp.ma.ld
invalidate pma_checker.io.resp.ae.inst
invalidate pma_checker.io.resp.ae.st
invalidate pma_checker.io.resp.ae.ld
invalidate pma_checker.io.resp.gf.inst
invalidate pma_checker.io.resp.gf.st
invalidate pma_checker.io.resp.gf.ld
invalidate pma_checker.io.resp.pf.inst
invalidate pma_checker.io.resp.pf.st
invalidate pma_checker.io.resp.pf.ld
invalidate pma_checker.io.resp.gpa_is_pte
invalidate pma_checker.io.resp.gpa
invalidate pma_checker.io.resp.paddr
invalidate pma_checker.io.resp.miss
invalidate pma_checker.io.req.bits.v
invalidate pma_checker.io.req.bits.prv
invalidate pma_checker.io.req.bits.cmd
invalidate pma_checker.io.req.bits.size
invalidate pma_checker.io.req.bits.passthrough
invalidate pma_checker.io.req.bits.vaddr
invalidate pma_checker.io.req.valid
invalidate pma_checker.io.req.ready
connect pma_checker.io.req.bits.passthrough, UInt<1>(0h1)
connect pma_checker.io.req.bits.vaddr, s1_req.addr
connect pma_checker.io.req.bits.size, s1_req.size
connect pma_checker.io.req.bits.cmd, s1_req.cmd
connect pma_checker.io.req.bits.prv, s1_req.dprv
connect pma_checker.io.req.bits.v, s1_req.dv
node _s1_paddr_T = bits(s1_req.addr, 31, 12)
node _s1_paddr_T_1 = shr(tlb.io.resp.paddr, 12)
node _s1_paddr_T_2 = mux(s1_tlb_req_valid, _s1_paddr_T, _s1_paddr_T_1)
node _s1_paddr_T_3 = bits(s1_req.addr, 11, 0)
node s1_paddr = cat(_s1_paddr_T_2, _s1_paddr_T_3)
wire s1_victim_way : UInt
node _baseAddr_T = eq(UInt<1>(0h0), hartIdSinkNodeOptIn)
node baseAddr = or(UInt<22>(0h200000), mmioAddressPrefixSinkNodeOptIn)
node _inScratchpad_T = geq(s1_paddr, baseAddr)
node _inScratchpad_T_1 = add(baseAddr, UInt<12>(0h800))
node _inScratchpad_T_2 = tail(_inScratchpad_T_1, 1)
node _inScratchpad_T_3 = lt(s1_paddr, _inScratchpad_T_2)
node s1_hit_way = and(_inScratchpad_T, _inScratchpad_T_3)
wire hitState_meta : { state : UInt<2>}
connect hitState_meta.state, UInt<2>(0h3)
wire hitState_meta_1 : { state : UInt<2>}
connect hitState_meta_1.state, UInt<2>(0h0)
node s1_hit_state = mux(s1_hit_way, hitState_meta, hitState_meta_1)
wire dummyMeta_meta : { state : UInt<2>}
connect dummyMeta_meta.state, UInt<2>(0h0)
wire dummyMeta : { coh : { state : UInt<2>}, tag : UInt<21>}
connect dummyMeta.tag, UInt<1>(0h0)
connect dummyMeta.coh, dummyMeta_meta
node s1_meta_0 = cat(dummyMeta.coh.state, dummyMeta.tag)
wire s1_data_way : UInt
connect s1_data_way, UInt<1>(0h1)
node _tl_d_data_encoded_T = bits(nodeOut.d.bits.data, 7, 0)
node _tl_d_data_encoded_T_1 = bits(nodeOut.d.bits.data, 15, 8)
node _tl_d_data_encoded_T_2 = bits(nodeOut.d.bits.data, 23, 16)
node _tl_d_data_encoded_T_3 = bits(nodeOut.d.bits.data, 31, 24)
node _tl_d_data_encoded_T_4 = bits(nodeOut.d.bits.data, 39, 32)
node _tl_d_data_encoded_T_5 = bits(nodeOut.d.bits.data, 47, 40)
node _tl_d_data_encoded_T_6 = bits(nodeOut.d.bits.data, 55, 48)
node _tl_d_data_encoded_T_7 = bits(nodeOut.d.bits.data, 63, 56)
node tl_d_data_encoded_lo_lo = cat(_tl_d_data_encoded_T_1, _tl_d_data_encoded_T)
node tl_d_data_encoded_lo_hi = cat(_tl_d_data_encoded_T_3, _tl_d_data_encoded_T_2)
node tl_d_data_encoded_lo = cat(tl_d_data_encoded_lo_hi, tl_d_data_encoded_lo_lo)
node tl_d_data_encoded_hi_lo = cat(_tl_d_data_encoded_T_5, _tl_d_data_encoded_T_4)
node tl_d_data_encoded_hi_hi = cat(_tl_d_data_encoded_T_7, _tl_d_data_encoded_T_6)
node tl_d_data_encoded_hi = cat(tl_d_data_encoded_hi_hi, tl_d_data_encoded_hi_lo)
node _tl_d_data_encoded_T_8 = cat(tl_d_data_encoded_hi, tl_d_data_encoded_lo)
wire tl_d_data_encoded : UInt<64>
wire s1_all_data_ways : UInt<64>[2]
connect s1_all_data_ways[0], data.io.resp[0]
connect s1_all_data_ways[1], tl_d_data_encoded
wire s1_mask_xwr_size : UInt<2>
connect s1_mask_xwr_size, s1_req.size
node _s1_mask_xwr_upper_T = bits(s1_req.addr, 0, 0)
node _s1_mask_xwr_upper_T_1 = mux(_s1_mask_xwr_upper_T, UInt<1>(0h1), UInt<1>(0h0))
node _s1_mask_xwr_upper_T_2 = geq(s1_mask_xwr_size, UInt<1>(0h1))
node _s1_mask_xwr_upper_T_3 = mux(_s1_mask_xwr_upper_T_2, UInt<1>(0h1), UInt<1>(0h0))
node s1_mask_xwr_upper = or(_s1_mask_xwr_upper_T_1, _s1_mask_xwr_upper_T_3)
node _s1_mask_xwr_lower_T = bits(s1_req.addr, 0, 0)
node s1_mask_xwr_lower = mux(_s1_mask_xwr_lower_T, UInt<1>(0h0), UInt<1>(0h1))
node _s1_mask_xwr_T = cat(s1_mask_xwr_upper, s1_mask_xwr_lower)
node _s1_mask_xwr_upper_T_4 = bits(s1_req.addr, 1, 1)
node _s1_mask_xwr_upper_T_5 = mux(_s1_mask_xwr_upper_T_4, _s1_mask_xwr_T, UInt<1>(0h0))
node _s1_mask_xwr_upper_T_6 = geq(s1_mask_xwr_size, UInt<2>(0h2))
node _s1_mask_xwr_upper_T_7 = mux(_s1_mask_xwr_upper_T_6, UInt<2>(0h3), UInt<1>(0h0))
node s1_mask_xwr_upper_1 = or(_s1_mask_xwr_upper_T_5, _s1_mask_xwr_upper_T_7)
node _s1_mask_xwr_lower_T_1 = bits(s1_req.addr, 1, 1)
node s1_mask_xwr_lower_1 = mux(_s1_mask_xwr_lower_T_1, UInt<1>(0h0), _s1_mask_xwr_T)
node _s1_mask_xwr_T_1 = cat(s1_mask_xwr_upper_1, s1_mask_xwr_lower_1)
node _s1_mask_xwr_upper_T_8 = bits(s1_req.addr, 2, 2)
node _s1_mask_xwr_upper_T_9 = mux(_s1_mask_xwr_upper_T_8, _s1_mask_xwr_T_1, UInt<1>(0h0))
node _s1_mask_xwr_upper_T_10 = geq(s1_mask_xwr_size, UInt<2>(0h3))
node _s1_mask_xwr_upper_T_11 = mux(_s1_mask_xwr_upper_T_10, UInt<4>(0hf), UInt<1>(0h0))
node s1_mask_xwr_upper_2 = or(_s1_mask_xwr_upper_T_9, _s1_mask_xwr_upper_T_11)
node _s1_mask_xwr_lower_T_2 = bits(s1_req.addr, 2, 2)
node s1_mask_xwr_lower_2 = mux(_s1_mask_xwr_lower_T_2, UInt<1>(0h0), _s1_mask_xwr_T_1)
node s1_mask_xwr = cat(s1_mask_xwr_upper_2, s1_mask_xwr_lower_2)
node _s1_mask_T = eq(s1_req.cmd, UInt<5>(0h11))
node s1_mask = mux(_s1_mask_T, io.cpu.s1_data.mask, s1_mask_xwr)
node _T_19 = eq(s1_req.cmd, UInt<5>(0h11))
node _T_20 = and(s1_valid_masked, _T_19)
node _T_21 = eq(_T_20, UInt<1>(0h0))
node _T_22 = not(io.cpu.s1_data.mask)
node _T_23 = or(s1_mask_xwr, _T_22)
node _T_24 = andr(_T_23)
node _T_25 = or(_T_21, _T_24)
node _T_26 = asUInt(reset)
node _T_27 = eq(_T_26, UInt<1>(0h0))
when _T_27 :
node _T_28 = eq(_T_25, UInt<1>(0h0))
when _T_28 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:329 assert(!(s1_valid_masked && s1_req.cmd === M_PWR) || (s1_mask_xwr | ~io.cpu.s1_data.mask).andR)\n") : printf
assert(clock, _T_25, UInt<1>(0h1), "") : assert
node _s2_valid_T = eq(s1_sfence, UInt<1>(0h0))
node _s2_valid_T_1 = and(s1_valid_masked, _s2_valid_T)
regreset s2_valid : UInt<1>, clock, reset, UInt<1>(0h0)
connect s2_valid, _s2_valid_T_1
node _s2_valid_no_xcpt_T = cat(io.cpu.s2_xcpt.ae.ld, io.cpu.s2_xcpt.ae.st)
node _s2_valid_no_xcpt_T_1 = cat(io.cpu.s2_xcpt.gf.ld, io.cpu.s2_xcpt.gf.st)
node _s2_valid_no_xcpt_T_2 = cat(io.cpu.s2_xcpt.pf.ld, io.cpu.s2_xcpt.pf.st)
node _s2_valid_no_xcpt_T_3 = cat(io.cpu.s2_xcpt.ma.ld, io.cpu.s2_xcpt.ma.st)
node s2_valid_no_xcpt_lo = cat(_s2_valid_no_xcpt_T_1, _s2_valid_no_xcpt_T)
node s2_valid_no_xcpt_hi = cat(_s2_valid_no_xcpt_T_3, _s2_valid_no_xcpt_T_2)
node _s2_valid_no_xcpt_T_4 = cat(s2_valid_no_xcpt_hi, s2_valid_no_xcpt_lo)
node _s2_valid_no_xcpt_T_5 = orr(_s2_valid_no_xcpt_T_4)
node _s2_valid_no_xcpt_T_6 = eq(_s2_valid_no_xcpt_T_5, UInt<1>(0h0))
node s2_valid_no_xcpt = and(s2_valid, _s2_valid_no_xcpt_T_6)
regreset s2_probe : UInt<1>, clock, reset, UInt<1>(0h0)
connect s2_probe, s1_probe
node _releaseInFlight_T = or(s1_probe, s2_probe)
node _releaseInFlight_T_1 = neq(release_state, UInt<4>(0h0))
node releaseInFlight = or(_releaseInFlight_T, _releaseInFlight_T_1)
node _s2_not_nacked_in_s1_T = eq(s1_nack, UInt<1>(0h0))
reg s2_not_nacked_in_s1 : UInt<1>, clock
connect s2_not_nacked_in_s1, _s2_not_nacked_in_s1_T
node s2_valid_not_nacked_in_s1 = and(s2_valid, s2_not_nacked_in_s1)
node s2_valid_masked = and(s2_valid_no_xcpt, s2_not_nacked_in_s1)
node _s2_valid_not_killed_T = eq(io.cpu.s2_kill, UInt<1>(0h0))
node s2_valid_not_killed = and(s2_valid_masked, _s2_valid_not_killed_T)
reg s2_req : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}, clock
node _s2_cmd_flush_all_T = eq(s2_req.cmd, UInt<3>(0h5))
node _s2_cmd_flush_all_T_1 = bits(s2_req.size, 0, 0)
node _s2_cmd_flush_all_T_2 = eq(_s2_cmd_flush_all_T_1, UInt<1>(0h0))
node s2_cmd_flush_all = and(_s2_cmd_flush_all_T, _s2_cmd_flush_all_T_2)
node _s2_cmd_flush_line_T = eq(s2_req.cmd, UInt<3>(0h5))
node _s2_cmd_flush_line_T_1 = bits(s2_req.size, 0, 0)
node s2_cmd_flush_line = and(_s2_cmd_flush_line_T, _s2_cmd_flush_line_T_1)
reg s2_tlb_xcpt : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, clock
reg s2_pma : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, clock
reg s2_uncached_resp_addr : UInt<40>, clock
node _T_29 = or(s1_valid_not_nacked, s1_flush_valid)
when _T_29 :
connect s2_req, s1_req
connect s2_req.addr, s1_paddr
connect s2_tlb_xcpt, tlb.io.resp
node _s2_pma_T = mux(s1_tlb_req_valid, pma_checker.io.resp, tlb.io.resp)
connect s2_pma, _s2_pma_T
node _s2_vaddr_T = or(s1_valid_not_nacked, s1_flush_valid)
reg s2_vaddr_r : UInt<40>, clock
when _s2_vaddr_T :
connect s2_vaddr_r, s1_vaddr
node _s2_vaddr_T_1 = shr(s2_vaddr_r, 11)
node _s2_vaddr_T_2 = bits(s2_req.addr, 10, 0)
node s2_vaddr = cat(_s2_vaddr_T_1, _s2_vaddr_T_2)
node _s2_read_T = eq(s2_req.cmd, UInt<1>(0h0))
node _s2_read_T_1 = eq(s2_req.cmd, UInt<5>(0h10))
node _s2_read_T_2 = eq(s2_req.cmd, UInt<3>(0h6))
node _s2_read_T_3 = eq(s2_req.cmd, UInt<3>(0h7))
node _s2_read_T_4 = or(_s2_read_T, _s2_read_T_1)
node _s2_read_T_5 = or(_s2_read_T_4, _s2_read_T_2)
node _s2_read_T_6 = or(_s2_read_T_5, _s2_read_T_3)
node _s2_read_T_7 = eq(s2_req.cmd, UInt<3>(0h4))
node _s2_read_T_8 = eq(s2_req.cmd, UInt<4>(0h9))
node _s2_read_T_9 = eq(s2_req.cmd, UInt<4>(0ha))
node _s2_read_T_10 = eq(s2_req.cmd, UInt<4>(0hb))
node _s2_read_T_11 = or(_s2_read_T_7, _s2_read_T_8)
node _s2_read_T_12 = or(_s2_read_T_11, _s2_read_T_9)
node _s2_read_T_13 = or(_s2_read_T_12, _s2_read_T_10)
node _s2_read_T_14 = eq(s2_req.cmd, UInt<4>(0h8))
node _s2_read_T_15 = eq(s2_req.cmd, UInt<4>(0hc))
node _s2_read_T_16 = eq(s2_req.cmd, UInt<4>(0hd))
node _s2_read_T_17 = eq(s2_req.cmd, UInt<4>(0he))
node _s2_read_T_18 = eq(s2_req.cmd, UInt<4>(0hf))
node _s2_read_T_19 = or(_s2_read_T_14, _s2_read_T_15)
node _s2_read_T_20 = or(_s2_read_T_19, _s2_read_T_16)
node _s2_read_T_21 = or(_s2_read_T_20, _s2_read_T_17)
node _s2_read_T_22 = or(_s2_read_T_21, _s2_read_T_18)
node _s2_read_T_23 = or(_s2_read_T_13, _s2_read_T_22)
node s2_read = or(_s2_read_T_6, _s2_read_T_23)
node _s2_write_T = eq(s2_req.cmd, UInt<1>(0h1))
node _s2_write_T_1 = eq(s2_req.cmd, UInt<5>(0h11))
node _s2_write_T_2 = or(_s2_write_T, _s2_write_T_1)
node _s2_write_T_3 = eq(s2_req.cmd, UInt<3>(0h7))
node _s2_write_T_4 = or(_s2_write_T_2, _s2_write_T_3)
node _s2_write_T_5 = eq(s2_req.cmd, UInt<3>(0h4))
node _s2_write_T_6 = eq(s2_req.cmd, UInt<4>(0h9))
node _s2_write_T_7 = eq(s2_req.cmd, UInt<4>(0ha))
node _s2_write_T_8 = eq(s2_req.cmd, UInt<4>(0hb))
node _s2_write_T_9 = or(_s2_write_T_5, _s2_write_T_6)
node _s2_write_T_10 = or(_s2_write_T_9, _s2_write_T_7)
node _s2_write_T_11 = or(_s2_write_T_10, _s2_write_T_8)
node _s2_write_T_12 = eq(s2_req.cmd, UInt<4>(0h8))
node _s2_write_T_13 = eq(s2_req.cmd, UInt<4>(0hc))
node _s2_write_T_14 = eq(s2_req.cmd, UInt<4>(0hd))
node _s2_write_T_15 = eq(s2_req.cmd, UInt<4>(0he))
node _s2_write_T_16 = eq(s2_req.cmd, UInt<4>(0hf))
node _s2_write_T_17 = or(_s2_write_T_12, _s2_write_T_13)
node _s2_write_T_18 = or(_s2_write_T_17, _s2_write_T_14)
node _s2_write_T_19 = or(_s2_write_T_18, _s2_write_T_15)
node _s2_write_T_20 = or(_s2_write_T_19, _s2_write_T_16)
node _s2_write_T_21 = or(_s2_write_T_11, _s2_write_T_20)
node s2_write = or(_s2_write_T_4, _s2_write_T_21)
node s2_readwrite = or(s2_read, s2_write)
reg s2_flush_valid_pre_tag_ecc : UInt<1>, clock
connect s2_flush_valid_pre_tag_ecc, s1_flush_valid
node _s1_meta_clk_en_T = or(s1_valid_not_nacked, s1_flush_valid)
node s1_meta_clk_en = or(_s1_meta_clk_en_T, s1_probe)
reg s2_meta_correctable_errors : UInt<1>, clock
when s1_meta_clk_en :
connect s2_meta_correctable_errors, UInt<1>(0h0)
reg s2_meta_uncorrectable_errors : UInt<1>, clock
when s1_meta_clk_en :
connect s2_meta_uncorrectable_errors, UInt<1>(0h0)
node s2_meta_error_uncorrectable = orr(s2_meta_uncorrectable_errors)
reg s2_meta_corrected_r : UInt<23>, clock
when s1_meta_clk_en :
connect s2_meta_corrected_r, s1_meta_0
wire s2_meta_corrected_0 : { coh : { state : UInt<2>}, tag : UInt<21>}
wire _s2_meta_corrected_WIRE : UInt<23>
connect _s2_meta_corrected_WIRE, s2_meta_corrected_r
node _s2_meta_corrected_T = bits(_s2_meta_corrected_WIRE, 20, 0)
connect s2_meta_corrected_0.tag, _s2_meta_corrected_T
node _s2_meta_corrected_T_1 = bits(_s2_meta_corrected_WIRE, 22, 21)
connect s2_meta_corrected_0.coh.state, _s2_meta_corrected_T_1
node _s2_meta_error_T = or(s2_meta_uncorrectable_errors, s2_meta_correctable_errors)
node s2_meta_error = orr(_s2_meta_error_T)
node _s2_flush_valid_T = eq(s2_meta_error, UInt<1>(0h0))
node s2_flush_valid = and(s2_flush_valid_pre_tag_ecc, _s2_flush_valid_T)
node _s2_data_en_T = or(s1_valid, inWriteback)
node s2_data_en = or(_s2_data_en_T, io.cpu.replay_next)
node _s2_data_word_en_T = mux(s1_did_read, s1_read_mask, UInt<1>(0h0))
node s2_data_word_en = mux(inWriteback, UInt<1>(0h1), _s2_data_word_en_T)
node s2_data_s1_way_words_0_0 = bits(s1_all_data_ways[0], 63, 0)
node s2_data_s1_way_words_1_0 = bits(s1_all_data_ways[1], 63, 0)
node _s2_data_s1_word_en_T = eq(io.cpu.replay_next, UInt<1>(0h0))
node s2_data_s1_word_en = mux(_s2_data_s1_word_en_T, s2_data_word_en, UInt<1>(0h1))
node _s2_data_T = bits(s2_data_s1_word_en, 0, 0)
node _s2_data_T_1 = mux(_s2_data_T, s1_data_way, UInt<1>(0h0))
node _s2_data_T_2 = bits(_s2_data_T_1, 0, 0)
node _s2_data_T_3 = bits(_s2_data_T_1, 1, 1)
node _s2_data_T_4 = mux(_s2_data_T_2, s2_data_s1_way_words_0_0, UInt<1>(0h0))
node _s2_data_T_5 = mux(_s2_data_T_3, s2_data_s1_way_words_1_0, UInt<1>(0h0))
node _s2_data_T_6 = or(_s2_data_T_4, _s2_data_T_5)
wire _s2_data_WIRE : UInt<64>
connect _s2_data_WIRE, _s2_data_T_6
reg s2_data : UInt<64>, clock
when s2_data_en :
connect s2_data, _s2_data_WIRE
reg s2_probe_way : UInt<1>, clock
when s1_probe :
connect s2_probe_way, s1_hit_way
reg s2_probe_state : { state : UInt<2>}, clock
when s1_probe :
connect s2_probe_state, s1_hit_state
reg s2_hit_way : UInt<1>, clock
when s1_valid_not_nacked :
connect s2_hit_way, s1_hit_way
node _s2_hit_state_T = or(s1_valid_not_nacked, s1_flush_valid)
reg s2_hit_state : { state : UInt<2>}, clock
when _s2_hit_state_T :
connect s2_hit_state, s1_hit_state
reg s2_waw_hazard : UInt<1>, clock
when s1_valid_not_nacked :
connect s2_waw_hazard, s1_waw_hazard
wire s2_store_merge : UInt<1>
node s2_hit_valid = gt(s2_hit_state.state, UInt<2>(0h0))
node _r_c_cat_T = eq(s2_req.cmd, UInt<1>(0h1))
node _r_c_cat_T_1 = eq(s2_req.cmd, UInt<5>(0h11))
node _r_c_cat_T_2 = or(_r_c_cat_T, _r_c_cat_T_1)
node _r_c_cat_T_3 = eq(s2_req.cmd, UInt<3>(0h7))
node _r_c_cat_T_4 = or(_r_c_cat_T_2, _r_c_cat_T_3)
node _r_c_cat_T_5 = eq(s2_req.cmd, UInt<3>(0h4))
node _r_c_cat_T_6 = eq(s2_req.cmd, UInt<4>(0h9))
node _r_c_cat_T_7 = eq(s2_req.cmd, UInt<4>(0ha))
node _r_c_cat_T_8 = eq(s2_req.cmd, UInt<4>(0hb))
node _r_c_cat_T_9 = or(_r_c_cat_T_5, _r_c_cat_T_6)
node _r_c_cat_T_10 = or(_r_c_cat_T_9, _r_c_cat_T_7)
node _r_c_cat_T_11 = or(_r_c_cat_T_10, _r_c_cat_T_8)
node _r_c_cat_T_12 = eq(s2_req.cmd, UInt<4>(0h8))
node _r_c_cat_T_13 = eq(s2_req.cmd, UInt<4>(0hc))
node _r_c_cat_T_14 = eq(s2_req.cmd, UInt<4>(0hd))
node _r_c_cat_T_15 = eq(s2_req.cmd, UInt<4>(0he))
node _r_c_cat_T_16 = eq(s2_req.cmd, UInt<4>(0hf))
node _r_c_cat_T_17 = or(_r_c_cat_T_12, _r_c_cat_T_13)
node _r_c_cat_T_18 = or(_r_c_cat_T_17, _r_c_cat_T_14)
node _r_c_cat_T_19 = or(_r_c_cat_T_18, _r_c_cat_T_15)
node _r_c_cat_T_20 = or(_r_c_cat_T_19, _r_c_cat_T_16)
node _r_c_cat_T_21 = or(_r_c_cat_T_11, _r_c_cat_T_20)
node _r_c_cat_T_22 = or(_r_c_cat_T_4, _r_c_cat_T_21)
node _r_c_cat_T_23 = eq(s2_req.cmd, UInt<1>(0h1))
node _r_c_cat_T_24 = eq(s2_req.cmd, UInt<5>(0h11))
node _r_c_cat_T_25 = or(_r_c_cat_T_23, _r_c_cat_T_24)
node _r_c_cat_T_26 = eq(s2_req.cmd, UInt<3>(0h7))
node _r_c_cat_T_27 = or(_r_c_cat_T_25, _r_c_cat_T_26)
node _r_c_cat_T_28 = eq(s2_req.cmd, UInt<3>(0h4))
node _r_c_cat_T_29 = eq(s2_req.cmd, UInt<4>(0h9))
node _r_c_cat_T_30 = eq(s2_req.cmd, UInt<4>(0ha))
node _r_c_cat_T_31 = eq(s2_req.cmd, UInt<4>(0hb))
node _r_c_cat_T_32 = or(_r_c_cat_T_28, _r_c_cat_T_29)
node _r_c_cat_T_33 = or(_r_c_cat_T_32, _r_c_cat_T_30)
node _r_c_cat_T_34 = or(_r_c_cat_T_33, _r_c_cat_T_31)
node _r_c_cat_T_35 = eq(s2_req.cmd, UInt<4>(0h8))
node _r_c_cat_T_36 = eq(s2_req.cmd, UInt<4>(0hc))
node _r_c_cat_T_37 = eq(s2_req.cmd, UInt<4>(0hd))
node _r_c_cat_T_38 = eq(s2_req.cmd, UInt<4>(0he))
node _r_c_cat_T_39 = eq(s2_req.cmd, UInt<4>(0hf))
node _r_c_cat_T_40 = or(_r_c_cat_T_35, _r_c_cat_T_36)
node _r_c_cat_T_41 = or(_r_c_cat_T_40, _r_c_cat_T_37)
node _r_c_cat_T_42 = or(_r_c_cat_T_41, _r_c_cat_T_38)
node _r_c_cat_T_43 = or(_r_c_cat_T_42, _r_c_cat_T_39)
node _r_c_cat_T_44 = or(_r_c_cat_T_34, _r_c_cat_T_43)
node _r_c_cat_T_45 = or(_r_c_cat_T_27, _r_c_cat_T_44)
node _r_c_cat_T_46 = eq(s2_req.cmd, UInt<2>(0h3))
node _r_c_cat_T_47 = or(_r_c_cat_T_45, _r_c_cat_T_46)
node _r_c_cat_T_48 = eq(s2_req.cmd, UInt<3>(0h6))
node _r_c_cat_T_49 = or(_r_c_cat_T_47, _r_c_cat_T_48)
node r_c = cat(_r_c_cat_T_22, _r_c_cat_T_49)
node _r_T = cat(r_c, s2_hit_state.state)
node _r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_2 = cat(_r_T_1, UInt<2>(0h3))
node _r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_4 = cat(_r_T_3, UInt<2>(0h2))
node _r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_6 = cat(_r_T_5, UInt<2>(0h1))
node _r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_8 = cat(_r_T_7, UInt<2>(0h3))
node _r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_10 = cat(_r_T_9, UInt<2>(0h2))
node _r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_12 = cat(_r_T_11, UInt<2>(0h3))
node _r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_14 = cat(_r_T_13, UInt<2>(0h2))
node _r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_16 = cat(_r_T_15, UInt<2>(0h0))
node _r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_18 = cat(_r_T_17, UInt<2>(0h1))
node _r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_20 = cat(_r_T_19, UInt<2>(0h0))
node _r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_22 = cat(_r_T_21, UInt<2>(0h1))
node _r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_24 = cat(_r_T_23, UInt<2>(0h0))
node _r_T_25 = eq(_r_T_24, _r_T)
node _r_T_26 = mux(_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_27 = mux(_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _r_T_28 = eq(_r_T_22, _r_T)
node _r_T_29 = mux(_r_T_28, UInt<1>(0h0), _r_T_26)
node _r_T_30 = mux(_r_T_28, UInt<2>(0h2), _r_T_27)
node _r_T_31 = eq(_r_T_20, _r_T)
node _r_T_32 = mux(_r_T_31, UInt<1>(0h0), _r_T_29)
node _r_T_33 = mux(_r_T_31, UInt<2>(0h1), _r_T_30)
node _r_T_34 = eq(_r_T_18, _r_T)
node _r_T_35 = mux(_r_T_34, UInt<1>(0h0), _r_T_32)
node _r_T_36 = mux(_r_T_34, UInt<2>(0h2), _r_T_33)
node _r_T_37 = eq(_r_T_16, _r_T)
node _r_T_38 = mux(_r_T_37, UInt<1>(0h0), _r_T_35)
node _r_T_39 = mux(_r_T_37, UInt<2>(0h0), _r_T_36)
node _r_T_40 = eq(_r_T_14, _r_T)
node _r_T_41 = mux(_r_T_40, UInt<1>(0h1), _r_T_38)
node _r_T_42 = mux(_r_T_40, UInt<2>(0h3), _r_T_39)
node _r_T_43 = eq(_r_T_12, _r_T)
node _r_T_44 = mux(_r_T_43, UInt<1>(0h1), _r_T_41)
node _r_T_45 = mux(_r_T_43, UInt<2>(0h3), _r_T_42)
node _r_T_46 = eq(_r_T_10, _r_T)
node _r_T_47 = mux(_r_T_46, UInt<1>(0h1), _r_T_44)
node _r_T_48 = mux(_r_T_46, UInt<2>(0h2), _r_T_45)
node _r_T_49 = eq(_r_T_8, _r_T)
node _r_T_50 = mux(_r_T_49, UInt<1>(0h1), _r_T_47)
node _r_T_51 = mux(_r_T_49, UInt<2>(0h3), _r_T_48)
node _r_T_52 = eq(_r_T_6, _r_T)
node _r_T_53 = mux(_r_T_52, UInt<1>(0h1), _r_T_50)
node _r_T_54 = mux(_r_T_52, UInt<2>(0h1), _r_T_51)
node _r_T_55 = eq(_r_T_4, _r_T)
node _r_T_56 = mux(_r_T_55, UInt<1>(0h1), _r_T_53)
node _r_T_57 = mux(_r_T_55, UInt<2>(0h2), _r_T_54)
node _r_T_58 = eq(_r_T_2, _r_T)
node s2_hit = mux(_r_T_58, UInt<1>(0h1), _r_T_56)
node s2_grow_param = mux(_r_T_58, UInt<2>(0h3), _r_T_57)
wire s2_new_hit_state : { state : UInt<2>}
connect s2_new_hit_state.state, s2_grow_param
node _T_30 = bits(s2_data, 7, 0)
node _T_31 = bits(s2_data, 15, 8)
node _T_32 = bits(s2_data, 23, 16)
node _T_33 = bits(s2_data, 31, 24)
node _T_34 = bits(s2_data, 39, 32)
node _T_35 = bits(s2_data, 47, 40)
node _T_36 = bits(s2_data, 55, 48)
node _T_37 = bits(s2_data, 63, 56)
node _s2_data_error_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_T_1 = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_T_2 = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_T_3 = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_T_4 = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_T_5 = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_T_6 = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_T_7 = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_T_8 = or(_s2_data_error_T, _s2_data_error_T_1)
node _s2_data_error_T_9 = or(_s2_data_error_T_8, _s2_data_error_T_2)
node _s2_data_error_T_10 = or(_s2_data_error_T_9, _s2_data_error_T_3)
node _s2_data_error_T_11 = or(_s2_data_error_T_10, _s2_data_error_T_4)
node _s2_data_error_T_12 = or(_s2_data_error_T_11, _s2_data_error_T_5)
node _s2_data_error_T_13 = or(_s2_data_error_T_12, _s2_data_error_T_6)
node s2_data_error = or(_s2_data_error_T_13, _s2_data_error_T_7)
node _s2_data_error_uncorrectable_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_uncorrectable_T_1 = or(_s2_data_error_uncorrectable_T, UInt<1>(0h0))
node _s2_data_error_uncorrectable_T_2 = or(_s2_data_error_uncorrectable_T_1, UInt<1>(0h0))
node _s2_data_error_uncorrectable_T_3 = or(_s2_data_error_uncorrectable_T_2, UInt<1>(0h0))
node _s2_data_error_uncorrectable_T_4 = or(_s2_data_error_uncorrectable_T_3, UInt<1>(0h0))
node _s2_data_error_uncorrectable_T_5 = or(_s2_data_error_uncorrectable_T_4, UInt<1>(0h0))
node s2_data_error_uncorrectable = or(_s2_data_error_uncorrectable_T_5, UInt<1>(0h0))
node s2_data_corrected_lo_lo = cat(_T_31, _T_30)
node s2_data_corrected_lo_hi = cat(_T_33, _T_32)
node s2_data_corrected_lo = cat(s2_data_corrected_lo_hi, s2_data_corrected_lo_lo)
node s2_data_corrected_hi_lo = cat(_T_35, _T_34)
node s2_data_corrected_hi_hi = cat(_T_37, _T_36)
node s2_data_corrected_hi = cat(s2_data_corrected_hi_hi, s2_data_corrected_hi_lo)
node s2_data_corrected = cat(s2_data_corrected_hi, s2_data_corrected_lo)
node s2_data_uncorrected_lo_lo = cat(_T_31, _T_30)
node s2_data_uncorrected_lo_hi = cat(_T_33, _T_32)
node s2_data_uncorrected_lo = cat(s2_data_uncorrected_lo_hi, s2_data_uncorrected_lo_lo)
node s2_data_uncorrected_hi_lo = cat(_T_35, _T_34)
node s2_data_uncorrected_hi_hi = cat(_T_37, _T_36)
node s2_data_uncorrected_hi = cat(s2_data_uncorrected_hi_hi, s2_data_uncorrected_hi_lo)
node s2_data_uncorrected = cat(s2_data_uncorrected_hi, s2_data_uncorrected_lo)
node _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T = eq(s2_meta_error, UInt<1>(0h0))
node _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1 = and(s2_valid_masked, _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T)
node s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = and(_s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1, s2_hit)
node _s2_valid_hit_pre_data_ecc_and_waw_T = and(s2_valid_hit_maybe_flush_pre_data_ecc_and_waw, s2_readwrite)
node _s2_valid_hit_pre_data_ecc_and_waw_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node s2_valid_hit_pre_data_ecc_and_waw = and(_s2_valid_hit_pre_data_ecc_and_waw_T, _s2_valid_hit_pre_data_ecc_and_waw_T_1)
node s2_valid_flush_line = and(s2_valid_hit_maybe_flush_pre_data_ecc_and_waw, s2_cmd_flush_line)
node _s2_valid_hit_pre_data_ecc_T = eq(s2_waw_hazard, UInt<1>(0h0))
node _s2_valid_hit_pre_data_ecc_T_1 = or(_s2_valid_hit_pre_data_ecc_T, s2_store_merge)
node s2_valid_hit_pre_data_ecc = and(s2_valid_hit_pre_data_ecc_and_waw, _s2_valid_hit_pre_data_ecc_T_1)
node s2_valid_data_error = and(s2_valid_hit_pre_data_ecc_and_waw, s2_data_error)
node _s2_valid_hit_T = eq(s2_data_error, UInt<1>(0h0))
node s2_valid_hit = and(s2_valid_hit_pre_data_ecc, _s2_valid_hit_T)
node _s2_valid_miss_T = and(s2_valid_masked, s2_readwrite)
node _s2_valid_miss_T_1 = eq(s2_meta_error, UInt<1>(0h0))
node _s2_valid_miss_T_2 = and(_s2_valid_miss_T, _s2_valid_miss_T_1)
node _s2_valid_miss_T_3 = eq(s2_hit, UInt<1>(0h0))
node s2_valid_miss = and(_s2_valid_miss_T_2, _s2_valid_miss_T_3)
node _s2_uncached_T = eq(s2_pma.cacheable, UInt<1>(0h0))
node _s2_uncached_T_1 = eq(s2_pma.must_alloc, UInt<1>(0h0))
node _s2_uncached_T_2 = and(s2_req.no_alloc, _s2_uncached_T_1)
node _s2_uncached_T_3 = eq(s2_hit_valid, UInt<1>(0h0))
node _s2_uncached_T_4 = and(_s2_uncached_T_2, _s2_uncached_T_3)
node s2_uncached = or(_s2_uncached_T, _s2_uncached_T_4)
node _s2_valid_cached_miss_T = eq(s2_uncached, UInt<1>(0h0))
node _s2_valid_cached_miss_T_1 = and(s2_valid_miss, _s2_valid_cached_miss_T)
node _s2_valid_cached_miss_T_2 = orr(uncachedInFlight[0])
node _s2_valid_cached_miss_T_3 = eq(_s2_valid_cached_miss_T_2, UInt<1>(0h0))
node s2_valid_cached_miss = and(_s2_valid_cached_miss_T_1, _s2_valid_cached_miss_T_3)
node _s2_want_victimize_T = or(s2_valid_cached_miss, s2_valid_flush_line)
node _s2_want_victimize_T_1 = or(_s2_want_victimize_T, s2_valid_data_error)
node _s2_want_victimize_T_2 = or(_s2_want_victimize_T_1, s2_flush_valid)
node s2_want_victimize = and(UInt<1>(0h0), _s2_want_victimize_T_2)
node _s2_cannot_victimize_T = eq(s2_flush_valid, UInt<1>(0h0))
node s2_cannot_victimize = and(_s2_cannot_victimize_T, io.cpu.s2_kill)
node _s2_victimize_T = eq(s2_cannot_victimize, UInt<1>(0h0))
node s2_victimize = and(s2_want_victimize, _s2_victimize_T)
node _s2_valid_uncached_pending_T = and(s2_valid_miss, s2_uncached)
node _s2_valid_uncached_pending_T_1 = andr(uncachedInFlight[0])
node _s2_valid_uncached_pending_T_2 = eq(_s2_valid_uncached_pending_T_1, UInt<1>(0h0))
node s2_valid_uncached_pending = and(_s2_valid_uncached_pending_T, _s2_valid_uncached_pending_T_2)
node _s2_victim_way_T = or(s1_valid_not_nacked, s1_flush_valid)
reg s2_victim_way_r : UInt, clock
when _s2_victim_way_T :
connect s2_victim_way_r, s1_victim_way
node s2_victim_way = dshl(UInt<1>(0h1), s2_victim_way_r)
node s2_victim_or_hit_way = mux(s2_hit_valid, s2_hit_way, s2_victim_way)
node _s2_victim_tag_T = or(s2_valid_data_error, s2_valid_flush_line)
node _s2_victim_tag_T_1 = bits(s2_req.addr, 31, 11)
node _s2_victim_tag_T_2 = bits(s2_victim_way, 0, 0)
node s2_victim_tag = mux(_s2_victim_tag_T, _s2_victim_tag_T_1, s2_meta_corrected_0.tag)
node _s2_victim_state_T = bits(s2_victim_way, 0, 0)
node s2_victim_state = mux(s2_hit_valid, s2_hit_state, s2_meta_corrected_0.coh)
node _r_T_59 = cat(probe_bits.param, s2_probe_state.state)
node _r_T_60 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _r_T_61 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _r_T_62 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _r_T_63 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _r_T_64 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _r_T_65 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _r_T_66 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _r_T_67 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _r_T_68 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _r_T_69 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _r_T_70 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _r_T_71 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _r_T_72 = eq(_r_T_71, _r_T_59)
node _r_T_73 = mux(_r_T_72, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_74 = mux(_r_T_72, UInt<3>(0h5), UInt<1>(0h0))
node _r_T_75 = mux(_r_T_72, UInt<2>(0h0), UInt<1>(0h0))
node _r_T_76 = eq(_r_T_70, _r_T_59)
node _r_T_77 = mux(_r_T_76, UInt<1>(0h0), _r_T_73)
node _r_T_78 = mux(_r_T_76, UInt<3>(0h2), _r_T_74)
node _r_T_79 = mux(_r_T_76, UInt<2>(0h0), _r_T_75)
node _r_T_80 = eq(_r_T_69, _r_T_59)
node _r_T_81 = mux(_r_T_80, UInt<1>(0h0), _r_T_77)
node _r_T_82 = mux(_r_T_80, UInt<3>(0h1), _r_T_78)
node _r_T_83 = mux(_r_T_80, UInt<2>(0h0), _r_T_79)
node _r_T_84 = eq(_r_T_68, _r_T_59)
node _r_T_85 = mux(_r_T_84, UInt<1>(0h1), _r_T_81)
node _r_T_86 = mux(_r_T_84, UInt<3>(0h1), _r_T_82)
node _r_T_87 = mux(_r_T_84, UInt<2>(0h0), _r_T_83)
node _r_T_88 = eq(_r_T_67, _r_T_59)
node _r_T_89 = mux(_r_T_88, UInt<1>(0h0), _r_T_85)
node _r_T_90 = mux(_r_T_88, UInt<3>(0h5), _r_T_86)
node _r_T_91 = mux(_r_T_88, UInt<2>(0h0), _r_T_87)
node _r_T_92 = eq(_r_T_66, _r_T_59)
node _r_T_93 = mux(_r_T_92, UInt<1>(0h0), _r_T_89)
node _r_T_94 = mux(_r_T_92, UInt<3>(0h4), _r_T_90)
node _r_T_95 = mux(_r_T_92, UInt<2>(0h1), _r_T_91)
node _r_T_96 = eq(_r_T_65, _r_T_59)
node _r_T_97 = mux(_r_T_96, UInt<1>(0h0), _r_T_93)
node _r_T_98 = mux(_r_T_96, UInt<3>(0h0), _r_T_94)
node _r_T_99 = mux(_r_T_96, UInt<2>(0h1), _r_T_95)
node _r_T_100 = eq(_r_T_64, _r_T_59)
node _r_T_101 = mux(_r_T_100, UInt<1>(0h1), _r_T_97)
node _r_T_102 = mux(_r_T_100, UInt<3>(0h0), _r_T_98)
node _r_T_103 = mux(_r_T_100, UInt<2>(0h1), _r_T_99)
node _r_T_104 = eq(_r_T_63, _r_T_59)
node _r_T_105 = mux(_r_T_104, UInt<1>(0h0), _r_T_101)
node _r_T_106 = mux(_r_T_104, UInt<3>(0h5), _r_T_102)
node _r_T_107 = mux(_r_T_104, UInt<2>(0h0), _r_T_103)
node _r_T_108 = eq(_r_T_62, _r_T_59)
node _r_T_109 = mux(_r_T_108, UInt<1>(0h0), _r_T_105)
node _r_T_110 = mux(_r_T_108, UInt<3>(0h4), _r_T_106)
node _r_T_111 = mux(_r_T_108, UInt<2>(0h1), _r_T_107)
node _r_T_112 = eq(_r_T_61, _r_T_59)
node _r_T_113 = mux(_r_T_112, UInt<1>(0h0), _r_T_109)
node _r_T_114 = mux(_r_T_112, UInt<3>(0h3), _r_T_110)
node _r_T_115 = mux(_r_T_112, UInt<2>(0h2), _r_T_111)
node _r_T_116 = eq(_r_T_60, _r_T_59)
node s2_prb_ack_data = mux(_r_T_116, UInt<1>(0h1), _r_T_113)
node s2_report_param = mux(_r_T_116, UInt<3>(0h3), _r_T_114)
node r_3 = mux(_r_T_116, UInt<2>(0h2), _r_T_115)
wire probeNewCoh : { state : UInt<2>}
connect probeNewCoh.state, r_3
node _r_T_117 = eq(UInt<5>(0h10), UInt<5>(0h10))
node _r_T_118 = mux(_r_T_117, UInt<2>(0h2), UInt<2>(0h2))
node _r_T_119 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _r_T_120 = mux(_r_T_119, UInt<2>(0h1), _r_T_118)
node _r_T_121 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _r_T_122 = mux(_r_T_121, UInt<2>(0h0), _r_T_120)
node _r_T_123 = cat(_r_T_122, s2_victim_state.state)
node _r_T_124 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _r_T_125 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _r_T_126 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _r_T_127 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _r_T_128 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _r_T_129 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _r_T_130 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _r_T_131 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _r_T_132 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _r_T_133 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _r_T_134 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _r_T_135 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _r_T_136 = eq(_r_T_135, _r_T_123)
node _r_T_137 = mux(_r_T_136, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_138 = mux(_r_T_136, UInt<3>(0h5), UInt<1>(0h0))
node _r_T_139 = mux(_r_T_136, UInt<2>(0h0), UInt<1>(0h0))
node _r_T_140 = eq(_r_T_134, _r_T_123)
node _r_T_141 = mux(_r_T_140, UInt<1>(0h0), _r_T_137)
node _r_T_142 = mux(_r_T_140, UInt<3>(0h2), _r_T_138)
node _r_T_143 = mux(_r_T_140, UInt<2>(0h0), _r_T_139)
node _r_T_144 = eq(_r_T_133, _r_T_123)
node _r_T_145 = mux(_r_T_144, UInt<1>(0h0), _r_T_141)
node _r_T_146 = mux(_r_T_144, UInt<3>(0h1), _r_T_142)
node _r_T_147 = mux(_r_T_144, UInt<2>(0h0), _r_T_143)
node _r_T_148 = eq(_r_T_132, _r_T_123)
node _r_T_149 = mux(_r_T_148, UInt<1>(0h1), _r_T_145)
node _r_T_150 = mux(_r_T_148, UInt<3>(0h1), _r_T_146)
node _r_T_151 = mux(_r_T_148, UInt<2>(0h0), _r_T_147)
node _r_T_152 = eq(_r_T_131, _r_T_123)
node _r_T_153 = mux(_r_T_152, UInt<1>(0h0), _r_T_149)
node _r_T_154 = mux(_r_T_152, UInt<3>(0h5), _r_T_150)
node _r_T_155 = mux(_r_T_152, UInt<2>(0h0), _r_T_151)
node _r_T_156 = eq(_r_T_130, _r_T_123)
node _r_T_157 = mux(_r_T_156, UInt<1>(0h0), _r_T_153)
node _r_T_158 = mux(_r_T_156, UInt<3>(0h4), _r_T_154)
node _r_T_159 = mux(_r_T_156, UInt<2>(0h1), _r_T_155)
node _r_T_160 = eq(_r_T_129, _r_T_123)
node _r_T_161 = mux(_r_T_160, UInt<1>(0h0), _r_T_157)
node _r_T_162 = mux(_r_T_160, UInt<3>(0h0), _r_T_158)
node _r_T_163 = mux(_r_T_160, UInt<2>(0h1), _r_T_159)
node _r_T_164 = eq(_r_T_128, _r_T_123)
node _r_T_165 = mux(_r_T_164, UInt<1>(0h1), _r_T_161)
node _r_T_166 = mux(_r_T_164, UInt<3>(0h0), _r_T_162)
node _r_T_167 = mux(_r_T_164, UInt<2>(0h1), _r_T_163)
node _r_T_168 = eq(_r_T_127, _r_T_123)
node _r_T_169 = mux(_r_T_168, UInt<1>(0h0), _r_T_165)
node _r_T_170 = mux(_r_T_168, UInt<3>(0h5), _r_T_166)
node _r_T_171 = mux(_r_T_168, UInt<2>(0h0), _r_T_167)
node _r_T_172 = eq(_r_T_126, _r_T_123)
node _r_T_173 = mux(_r_T_172, UInt<1>(0h0), _r_T_169)
node _r_T_174 = mux(_r_T_172, UInt<3>(0h4), _r_T_170)
node _r_T_175 = mux(_r_T_172, UInt<2>(0h1), _r_T_171)
node _r_T_176 = eq(_r_T_125, _r_T_123)
node _r_T_177 = mux(_r_T_176, UInt<1>(0h0), _r_T_173)
node _r_T_178 = mux(_r_T_176, UInt<3>(0h3), _r_T_174)
node _r_T_179 = mux(_r_T_176, UInt<2>(0h2), _r_T_175)
node _r_T_180 = eq(_r_T_124, _r_T_123)
node s2_victim_dirty = mux(_r_T_180, UInt<1>(0h1), _r_T_177)
node s2_shrink_param = mux(_r_T_180, UInt<3>(0h3), _r_T_178)
node r_3_1 = mux(_r_T_180, UInt<2>(0h2), _r_T_179)
wire voluntaryNewCoh : { state : UInt<2>}
connect voluntaryNewCoh.state, r_3_1
node _s2_update_meta_T = eq(s2_hit_state.state, s2_new_hit_state.state)
node s2_update_meta = eq(_s2_update_meta_T, UInt<1>(0h0))
node s2_dont_nack_uncached = and(s2_valid_uncached_pending, tl_out_a.ready)
node _s2_dont_nack_misc_T = eq(s2_meta_error, UInt<1>(0h0))
node _s2_dont_nack_misc_T_1 = and(s2_valid_masked, _s2_dont_nack_misc_T)
node _s2_dont_nack_misc_T_2 = and(UInt<1>(0h0), s2_cmd_flush_all)
node _s2_dont_nack_misc_T_3 = and(_s2_dont_nack_misc_T_2, flushed)
node _s2_dont_nack_misc_T_4 = eq(flushing, UInt<1>(0h0))
node _s2_dont_nack_misc_T_5 = and(_s2_dont_nack_misc_T_3, _s2_dont_nack_misc_T_4)
node _s2_dont_nack_misc_T_6 = and(UInt<1>(0h0), s2_cmd_flush_line)
node _s2_dont_nack_misc_T_7 = eq(s2_hit, UInt<1>(0h0))
node _s2_dont_nack_misc_T_8 = and(_s2_dont_nack_misc_T_6, _s2_dont_nack_misc_T_7)
node _s2_dont_nack_misc_T_9 = or(_s2_dont_nack_misc_T_5, _s2_dont_nack_misc_T_8)
node _s2_dont_nack_misc_T_10 = eq(s2_req.cmd, UInt<5>(0h17))
node _s2_dont_nack_misc_T_11 = or(_s2_dont_nack_misc_T_9, _s2_dont_nack_misc_T_10)
node s2_dont_nack_misc = and(_s2_dont_nack_misc_T_1, _s2_dont_nack_misc_T_11)
node _io_cpu_s2_nack_T = eq(s2_dont_nack_uncached, UInt<1>(0h0))
node _io_cpu_s2_nack_T_1 = and(s2_valid_no_xcpt, _io_cpu_s2_nack_T)
node _io_cpu_s2_nack_T_2 = eq(s2_dont_nack_misc, UInt<1>(0h0))
node _io_cpu_s2_nack_T_3 = and(_io_cpu_s2_nack_T_1, _io_cpu_s2_nack_T_2)
node _io_cpu_s2_nack_T_4 = eq(s2_valid_hit, UInt<1>(0h0))
node _io_cpu_s2_nack_T_5 = and(_io_cpu_s2_nack_T_3, _io_cpu_s2_nack_T_4)
connect io.cpu.s2_nack, _io_cpu_s2_nack_T_5
node _T_38 = and(s2_valid_hit_pre_data_ecc_and_waw, s2_update_meta)
node _T_39 = or(io.cpu.s2_nack, _T_38)
when _T_39 :
connect s1_nack, UInt<1>(0h1)
node _s2_first_meta_corrected_T = bits(s2_meta_correctable_errors, 0, 0)
node _metaArb_io_in_1_valid_T = or(s2_valid_masked, s2_flush_valid_pre_tag_ecc)
node _metaArb_io_in_1_valid_T_1 = or(_metaArb_io_in_1_valid_T, s2_probe)
node _metaArb_io_in_1_valid_T_2 = and(s2_meta_error, _metaArb_io_in_1_valid_T_1)
connect metaArb.io.in[1].valid, _metaArb_io_in_1_valid_T_2
connect metaArb.io.in[1].bits.write, UInt<1>(0h1)
node _metaArb_io_in_1_bits_way_en_T = bits(s2_meta_correctable_errors, 0, 0)
node _metaArb_io_in_1_bits_way_en_T_1 = mux(_metaArb_io_in_1_bits_way_en_T, UInt<1>(0h1), UInt<1>(0h0))
node _metaArb_io_in_1_bits_way_en_T_2 = mux(s2_meta_error_uncorrectable, UInt<1>(0h0), _metaArb_io_in_1_bits_way_en_T_1)
node _metaArb_io_in_1_bits_way_en_T_3 = or(s2_meta_uncorrectable_errors, _metaArb_io_in_1_bits_way_en_T_2)
connect metaArb.io.in[1].bits.way_en, _metaArb_io_in_1_bits_way_en_T_3
node _metaArb_io_in_1_bits_idx_T = bits(probe_bits.address, 10, 6)
node _metaArb_io_in_1_bits_idx_T_1 = bits(s2_vaddr, 10, 6)
node _metaArb_io_in_1_bits_idx_T_2 = mux(s2_probe, _metaArb_io_in_1_bits_idx_T, _metaArb_io_in_1_bits_idx_T_1)
connect metaArb.io.in[1].bits.idx, _metaArb_io_in_1_bits_idx_T_2
node _metaArb_io_in_1_bits_addr_T = shr(io.cpu.req.bits.addr, 11)
node _metaArb_io_in_1_bits_addr_T_1 = shl(metaArb.io.in[1].bits.idx, 6)
node _metaArb_io_in_1_bits_addr_T_2 = cat(_metaArb_io_in_1_bits_addr_T, _metaArb_io_in_1_bits_addr_T_1)
connect metaArb.io.in[1].bits.addr, _metaArb_io_in_1_bits_addr_T_2
wire metaArb_io_in_1_bits_data_new_meta : { coh : { state : UInt<2>}, tag : UInt<21>}
connect metaArb_io_in_1_bits_data_new_meta, s2_meta_corrected_0
when s2_meta_error_uncorrectable :
wire metaArb_io_in_1_bits_data_new_meta_coh_meta : { state : UInt<2>}
connect metaArb_io_in_1_bits_data_new_meta_coh_meta.state, UInt<2>(0h0)
connect metaArb_io_in_1_bits_data_new_meta.coh, metaArb_io_in_1_bits_data_new_meta_coh_meta
node _metaArb_io_in_1_bits_data_T = cat(metaArb_io_in_1_bits_data_new_meta.coh.state, metaArb_io_in_1_bits_data_new_meta.tag)
connect metaArb.io.in[1].bits.data, _metaArb_io_in_1_bits_data_T
node _metaArb_io_in_2_valid_T = and(s2_valid_hit_pre_data_ecc_and_waw, s2_update_meta)
connect metaArb.io.in[2].valid, _metaArb_io_in_2_valid_T
node _metaArb_io_in_2_bits_write_T = eq(io.cpu.s2_kill, UInt<1>(0h0))
connect metaArb.io.in[2].bits.write, _metaArb_io_in_2_bits_write_T
connect metaArb.io.in[2].bits.way_en, s2_victim_or_hit_way
node _metaArb_io_in_2_bits_idx_T = bits(s2_vaddr, 10, 6)
connect metaArb.io.in[2].bits.idx, _metaArb_io_in_2_bits_idx_T
node _metaArb_io_in_2_bits_addr_T = shr(io.cpu.req.bits.addr, 11)
node _metaArb_io_in_2_bits_addr_T_1 = bits(s2_vaddr, 10, 0)
node _metaArb_io_in_2_bits_addr_T_2 = cat(_metaArb_io_in_2_bits_addr_T, _metaArb_io_in_2_bits_addr_T_1)
connect metaArb.io.in[2].bits.addr, _metaArb_io_in_2_bits_addr_T_2
node _metaArb_io_in_2_bits_data_T = shr(s2_req.addr, 11)
wire metaArb_io_in_2_bits_data_meta : { coh : { state : UInt<2>}, tag : UInt<21>}
connect metaArb_io_in_2_bits_data_meta.tag, _metaArb_io_in_2_bits_data_T
connect metaArb_io_in_2_bits_data_meta.coh, s2_new_hit_state
node _metaArb_io_in_2_bits_data_T_1 = cat(metaArb_io_in_2_bits_data_meta.coh.state, metaArb_io_in_2_bits_data_meta.tag)
connect metaArb.io.in[2].bits.data, _metaArb_io_in_2_bits_data_T_1
node _s2_lr_T = eq(s2_req.cmd, UInt<3>(0h6))
node s2_lr = and(UInt<1>(0h0), _s2_lr_T)
node _s2_sc_T = eq(s2_req.cmd, UInt<3>(0h7))
node s2_sc = and(UInt<1>(0h0), _s2_sc_T)
regreset lrscCount : UInt, clock, reset, UInt<1>(0h0)
node lrscValid = gt(lrscCount, UInt<2>(0h3))
node _lrscBackingOff_T = gt(lrscCount, UInt<1>(0h0))
node _lrscBackingOff_T_1 = eq(lrscValid, UInt<1>(0h0))
node lrscBackingOff = and(_lrscBackingOff_T, _lrscBackingOff_T_1)
reg lrscAddr : UInt, clock
node _lrscAddrMatch_T = shr(s2_req.addr, 6)
node lrscAddrMatch = eq(lrscAddr, _lrscAddrMatch_T)
node _s2_sc_fail_T = and(lrscValid, lrscAddrMatch)
node _s2_sc_fail_T_1 = eq(_s2_sc_fail_T, UInt<1>(0h0))
node s2_sc_fail = and(s2_sc, _s2_sc_fail_T_1)
node _T_40 = and(s2_valid_hit, s2_lr)
node _T_41 = eq(cached_grant_wait, UInt<1>(0h0))
node _T_42 = and(_T_40, _T_41)
node _T_43 = or(_T_42, s2_valid_cached_miss)
node _T_44 = eq(io.cpu.s2_kill, UInt<1>(0h0))
node _T_45 = and(_T_43, _T_44)
when _T_45 :
node _lrscCount_T = mux(s2_hit, UInt<7>(0h4f), UInt<1>(0h0))
connect lrscCount, _lrscCount_T
node _lrscAddr_T = shr(s2_req.addr, 6)
connect lrscAddr, _lrscAddr_T
node _T_46 = gt(lrscCount, UInt<1>(0h0))
when _T_46 :
node _lrscCount_T_1 = sub(lrscCount, UInt<1>(0h1))
node _lrscCount_T_2 = tail(_lrscCount_T_1, 1)
connect lrscCount, _lrscCount_T_2
node _T_47 = and(s2_valid_not_killed, lrscValid)
when _T_47 :
connect lrscCount, UInt<2>(0h3)
when s1_probe :
connect lrscCount, UInt<1>(0h0)
node _s2_correct_T = eq(any_pstore_valid, UInt<1>(0h0))
node _s2_correct_T_1 = and(s2_data_error, _s2_correct_T)
node _s2_correct_T_2 = or(any_pstore_valid, s2_valid)
reg s2_correct_REG : UInt<1>, clock
connect s2_correct_REG, _s2_correct_T_2
node _s2_correct_T_3 = eq(s2_correct_REG, UInt<1>(0h0))
node _s2_correct_T_4 = and(_s2_correct_T_1, _s2_correct_T_3)
node s2_correct = and(_s2_correct_T_4, UInt<1>(0h1))
node _s2_valid_correct_T = and(s2_valid_hit_pre_data_ecc_and_waw, s2_correct)
node _s2_valid_correct_T_1 = eq(io.cpu.s2_kill, UInt<1>(0h0))
node s2_valid_correct = and(_s2_valid_correct_T, _s2_valid_correct_T_1)
node _pstore1_cmd_T = and(s1_valid_not_nacked, s1_write)
reg pstore1_cmd : UInt<5>, clock
when _pstore1_cmd_T :
connect pstore1_cmd, s1_req.cmd
node _pstore1_addr_T = and(s1_valid_not_nacked, s1_write)
reg pstore1_addr : UInt<40>, clock
when _pstore1_addr_T :
connect pstore1_addr, s1_vaddr
node _pstore1_data_T = and(s1_valid_not_nacked, s1_write)
reg pstore1_data : UInt<64>, clock
when _pstore1_data_T :
connect pstore1_data, io.cpu.s1_data.data
node _pstore1_way_T = and(s1_valid_not_nacked, s1_write)
reg pstore1_way : UInt<1>, clock
when _pstore1_way_T :
connect pstore1_way, s1_hit_way
node _pstore1_mask_T = and(s1_valid_not_nacked, s1_write)
reg pstore1_mask : UInt<8>, clock
when _pstore1_mask_T :
connect pstore1_mask, s1_mask
wire pstore1_storegen_data : UInt
connect pstore1_storegen_data, pstore1_data
node _pstore1_rmw_T = eq(s1_req.cmd, UInt<1>(0h0))
node _pstore1_rmw_T_1 = eq(s1_req.cmd, UInt<5>(0h10))
node _pstore1_rmw_T_2 = eq(s1_req.cmd, UInt<3>(0h6))
node _pstore1_rmw_T_3 = eq(s1_req.cmd, UInt<3>(0h7))
node _pstore1_rmw_T_4 = or(_pstore1_rmw_T, _pstore1_rmw_T_1)
node _pstore1_rmw_T_5 = or(_pstore1_rmw_T_4, _pstore1_rmw_T_2)
node _pstore1_rmw_T_6 = or(_pstore1_rmw_T_5, _pstore1_rmw_T_3)
node _pstore1_rmw_T_7 = eq(s1_req.cmd, UInt<3>(0h4))
node _pstore1_rmw_T_8 = eq(s1_req.cmd, UInt<4>(0h9))
node _pstore1_rmw_T_9 = eq(s1_req.cmd, UInt<4>(0ha))
node _pstore1_rmw_T_10 = eq(s1_req.cmd, UInt<4>(0hb))
node _pstore1_rmw_T_11 = or(_pstore1_rmw_T_7, _pstore1_rmw_T_8)
node _pstore1_rmw_T_12 = or(_pstore1_rmw_T_11, _pstore1_rmw_T_9)
node _pstore1_rmw_T_13 = or(_pstore1_rmw_T_12, _pstore1_rmw_T_10)
node _pstore1_rmw_T_14 = eq(s1_req.cmd, UInt<4>(0h8))
node _pstore1_rmw_T_15 = eq(s1_req.cmd, UInt<4>(0hc))
node _pstore1_rmw_T_16 = eq(s1_req.cmd, UInt<4>(0hd))
node _pstore1_rmw_T_17 = eq(s1_req.cmd, UInt<4>(0he))
node _pstore1_rmw_T_18 = eq(s1_req.cmd, UInt<4>(0hf))
node _pstore1_rmw_T_19 = or(_pstore1_rmw_T_14, _pstore1_rmw_T_15)
node _pstore1_rmw_T_20 = or(_pstore1_rmw_T_19, _pstore1_rmw_T_16)
node _pstore1_rmw_T_21 = or(_pstore1_rmw_T_20, _pstore1_rmw_T_17)
node _pstore1_rmw_T_22 = or(_pstore1_rmw_T_21, _pstore1_rmw_T_18)
node _pstore1_rmw_T_23 = or(_pstore1_rmw_T_13, _pstore1_rmw_T_22)
node _pstore1_rmw_T_24 = or(_pstore1_rmw_T_6, _pstore1_rmw_T_23)
node _pstore1_rmw_T_25 = eq(s1_req.cmd, UInt<1>(0h1))
node _pstore1_rmw_T_26 = eq(s1_req.cmd, UInt<5>(0h11))
node _pstore1_rmw_T_27 = or(_pstore1_rmw_T_25, _pstore1_rmw_T_26)
node _pstore1_rmw_T_28 = eq(s1_req.cmd, UInt<3>(0h7))
node _pstore1_rmw_T_29 = or(_pstore1_rmw_T_27, _pstore1_rmw_T_28)
node _pstore1_rmw_T_30 = eq(s1_req.cmd, UInt<3>(0h4))
node _pstore1_rmw_T_31 = eq(s1_req.cmd, UInt<4>(0h9))
node _pstore1_rmw_T_32 = eq(s1_req.cmd, UInt<4>(0ha))
node _pstore1_rmw_T_33 = eq(s1_req.cmd, UInt<4>(0hb))
node _pstore1_rmw_T_34 = or(_pstore1_rmw_T_30, _pstore1_rmw_T_31)
node _pstore1_rmw_T_35 = or(_pstore1_rmw_T_34, _pstore1_rmw_T_32)
node _pstore1_rmw_T_36 = or(_pstore1_rmw_T_35, _pstore1_rmw_T_33)
node _pstore1_rmw_T_37 = eq(s1_req.cmd, UInt<4>(0h8))
node _pstore1_rmw_T_38 = eq(s1_req.cmd, UInt<4>(0hc))
node _pstore1_rmw_T_39 = eq(s1_req.cmd, UInt<4>(0hd))
node _pstore1_rmw_T_40 = eq(s1_req.cmd, UInt<4>(0he))
node _pstore1_rmw_T_41 = eq(s1_req.cmd, UInt<4>(0hf))
node _pstore1_rmw_T_42 = or(_pstore1_rmw_T_37, _pstore1_rmw_T_38)
node _pstore1_rmw_T_43 = or(_pstore1_rmw_T_42, _pstore1_rmw_T_39)
node _pstore1_rmw_T_44 = or(_pstore1_rmw_T_43, _pstore1_rmw_T_40)
node _pstore1_rmw_T_45 = or(_pstore1_rmw_T_44, _pstore1_rmw_T_41)
node _pstore1_rmw_T_46 = or(_pstore1_rmw_T_36, _pstore1_rmw_T_45)
node _pstore1_rmw_T_47 = or(_pstore1_rmw_T_29, _pstore1_rmw_T_46)
node _pstore1_rmw_T_48 = eq(s1_req.cmd, UInt<5>(0h11))
node _pstore1_rmw_T_49 = lt(s1_req.size, UInt<1>(0h0))
node _pstore1_rmw_T_50 = or(_pstore1_rmw_T_48, _pstore1_rmw_T_49)
node _pstore1_rmw_T_51 = and(_pstore1_rmw_T_47, _pstore1_rmw_T_50)
node _pstore1_rmw_T_52 = or(_pstore1_rmw_T_24, _pstore1_rmw_T_51)
node _pstore1_rmw_T_53 = and(s1_valid_not_nacked, s1_write)
reg pstore1_rmw_r : UInt<1>, clock
when _pstore1_rmw_T_53 :
connect pstore1_rmw_r, _pstore1_rmw_T_52
node pstore1_rmw = and(UInt<1>(0h1), pstore1_rmw_r)
node _pstore1_merge_likely_T = and(s2_valid_not_nacked_in_s1, s2_write)
node pstore1_merge_likely = and(_pstore1_merge_likely_T, s2_store_merge)
node _pstore1_merge_T = and(s2_valid_hit, s2_write)
node _pstore1_merge_T_1 = eq(s2_sc_fail, UInt<1>(0h0))
node _pstore1_merge_T_2 = and(_pstore1_merge_T, _pstore1_merge_T_1)
node _pstore1_merge_T_3 = eq(io.cpu.s2_kill, UInt<1>(0h0))
node _pstore1_merge_T_4 = and(_pstore1_merge_T_2, _pstore1_merge_T_3)
node pstore1_merge = and(_pstore1_merge_T_4, s2_store_merge)
regreset pstore2_valid : UInt<1>, clock, reset, UInt<1>(0h0)
node _pstore_drain_opportunistic_res_T = eq(io.cpu.req.bits.cmd, UInt<1>(0h1))
node _pstore_drain_opportunistic_res_T_1 = eq(io.cpu.req.bits.cmd, UInt<2>(0h3))
node _pstore_drain_opportunistic_res_T_2 = or(_pstore_drain_opportunistic_res_T, _pstore_drain_opportunistic_res_T_1)
node _pstore_drain_opportunistic_res_T_3 = eq(_pstore_drain_opportunistic_res_T_2, UInt<1>(0h0))
node _pstore_drain_opportunistic_res_T_4 = lt(io.cpu.req.bits.size, UInt<1>(0h0))
node pstore_drain_opportunistic_res = or(_pstore_drain_opportunistic_res_T_3, _pstore_drain_opportunistic_res_T_4)
node _pstore_drain_opportunistic_T = eq(io.cpu.req.bits.cmd, UInt<1>(0h0))
node _pstore_drain_opportunistic_T_1 = eq(io.cpu.req.bits.cmd, UInt<5>(0h10))
node _pstore_drain_opportunistic_T_2 = eq(io.cpu.req.bits.cmd, UInt<3>(0h6))
node _pstore_drain_opportunistic_T_3 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7))
node _pstore_drain_opportunistic_T_4 = or(_pstore_drain_opportunistic_T, _pstore_drain_opportunistic_T_1)
node _pstore_drain_opportunistic_T_5 = or(_pstore_drain_opportunistic_T_4, _pstore_drain_opportunistic_T_2)
node _pstore_drain_opportunistic_T_6 = or(_pstore_drain_opportunistic_T_5, _pstore_drain_opportunistic_T_3)
node _pstore_drain_opportunistic_T_7 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4))
node _pstore_drain_opportunistic_T_8 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9))
node _pstore_drain_opportunistic_T_9 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha))
node _pstore_drain_opportunistic_T_10 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb))
node _pstore_drain_opportunistic_T_11 = or(_pstore_drain_opportunistic_T_7, _pstore_drain_opportunistic_T_8)
node _pstore_drain_opportunistic_T_12 = or(_pstore_drain_opportunistic_T_11, _pstore_drain_opportunistic_T_9)
node _pstore_drain_opportunistic_T_13 = or(_pstore_drain_opportunistic_T_12, _pstore_drain_opportunistic_T_10)
node _pstore_drain_opportunistic_T_14 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8))
node _pstore_drain_opportunistic_T_15 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc))
node _pstore_drain_opportunistic_T_16 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd))
node _pstore_drain_opportunistic_T_17 = eq(io.cpu.req.bits.cmd, UInt<4>(0he))
node _pstore_drain_opportunistic_T_18 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf))
node _pstore_drain_opportunistic_T_19 = or(_pstore_drain_opportunistic_T_14, _pstore_drain_opportunistic_T_15)
node _pstore_drain_opportunistic_T_20 = or(_pstore_drain_opportunistic_T_19, _pstore_drain_opportunistic_T_16)
node _pstore_drain_opportunistic_T_21 = or(_pstore_drain_opportunistic_T_20, _pstore_drain_opportunistic_T_17)
node _pstore_drain_opportunistic_T_22 = or(_pstore_drain_opportunistic_T_21, _pstore_drain_opportunistic_T_18)
node _pstore_drain_opportunistic_T_23 = or(_pstore_drain_opportunistic_T_13, _pstore_drain_opportunistic_T_22)
node _pstore_drain_opportunistic_T_24 = or(_pstore_drain_opportunistic_T_6, _pstore_drain_opportunistic_T_23)
node _pstore_drain_opportunistic_T_25 = eq(io.cpu.req.bits.cmd, UInt<1>(0h1))
node _pstore_drain_opportunistic_T_26 = eq(io.cpu.req.bits.cmd, UInt<5>(0h11))
node _pstore_drain_opportunistic_T_27 = or(_pstore_drain_opportunistic_T_25, _pstore_drain_opportunistic_T_26)
node _pstore_drain_opportunistic_T_28 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7))
node _pstore_drain_opportunistic_T_29 = or(_pstore_drain_opportunistic_T_27, _pstore_drain_opportunistic_T_28)
node _pstore_drain_opportunistic_T_30 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4))
node _pstore_drain_opportunistic_T_31 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9))
node _pstore_drain_opportunistic_T_32 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha))
node _pstore_drain_opportunistic_T_33 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb))
node _pstore_drain_opportunistic_T_34 = or(_pstore_drain_opportunistic_T_30, _pstore_drain_opportunistic_T_31)
node _pstore_drain_opportunistic_T_35 = or(_pstore_drain_opportunistic_T_34, _pstore_drain_opportunistic_T_32)
node _pstore_drain_opportunistic_T_36 = or(_pstore_drain_opportunistic_T_35, _pstore_drain_opportunistic_T_33)
node _pstore_drain_opportunistic_T_37 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8))
node _pstore_drain_opportunistic_T_38 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc))
node _pstore_drain_opportunistic_T_39 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd))
node _pstore_drain_opportunistic_T_40 = eq(io.cpu.req.bits.cmd, UInt<4>(0he))
node _pstore_drain_opportunistic_T_41 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf))
node _pstore_drain_opportunistic_T_42 = or(_pstore_drain_opportunistic_T_37, _pstore_drain_opportunistic_T_38)
node _pstore_drain_opportunistic_T_43 = or(_pstore_drain_opportunistic_T_42, _pstore_drain_opportunistic_T_39)
node _pstore_drain_opportunistic_T_44 = or(_pstore_drain_opportunistic_T_43, _pstore_drain_opportunistic_T_40)
node _pstore_drain_opportunistic_T_45 = or(_pstore_drain_opportunistic_T_44, _pstore_drain_opportunistic_T_41)
node _pstore_drain_opportunistic_T_46 = or(_pstore_drain_opportunistic_T_36, _pstore_drain_opportunistic_T_45)
node _pstore_drain_opportunistic_T_47 = or(_pstore_drain_opportunistic_T_29, _pstore_drain_opportunistic_T_46)
node _pstore_drain_opportunistic_T_48 = eq(io.cpu.req.bits.cmd, UInt<5>(0h11))
node _pstore_drain_opportunistic_T_49 = lt(io.cpu.req.bits.size, UInt<1>(0h0))
node _pstore_drain_opportunistic_T_50 = or(_pstore_drain_opportunistic_T_48, _pstore_drain_opportunistic_T_49)
node _pstore_drain_opportunistic_T_51 = and(_pstore_drain_opportunistic_T_47, _pstore_drain_opportunistic_T_50)
node _pstore_drain_opportunistic_T_52 = or(_pstore_drain_opportunistic_T_24, _pstore_drain_opportunistic_T_51)
node _pstore_drain_opportunistic_T_53 = eq(_pstore_drain_opportunistic_T_52, UInt<1>(0h0))
node _pstore_drain_opportunistic_T_54 = or(_pstore_drain_opportunistic_T_53, pstore_drain_opportunistic_res)
node _pstore_drain_opportunistic_T_55 = asUInt(reset)
node _pstore_drain_opportunistic_T_56 = eq(_pstore_drain_opportunistic_T_55, UInt<1>(0h0))
when _pstore_drain_opportunistic_T_56 :
node _pstore_drain_opportunistic_T_57 = eq(_pstore_drain_opportunistic_T_54, UInt<1>(0h0))
when _pstore_drain_opportunistic_T_57 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:1186 assert(!needsRead(req) || res)\n") : pstore_drain_opportunistic_printf
assert(clock, _pstore_drain_opportunistic_T_54, UInt<1>(0h1), "") : pstore_drain_opportunistic_assert
node _pstore_drain_opportunistic_T_58 = and(io.cpu.req.valid, pstore_drain_opportunistic_res)
node _pstore_drain_opportunistic_T_59 = eq(_pstore_drain_opportunistic_T_58, UInt<1>(0h0))
node _pstore_drain_opportunistic_T_60 = and(s1_valid, s1_waw_hazard)
node _pstore_drain_opportunistic_T_61 = eq(_pstore_drain_opportunistic_T_60, UInt<1>(0h0))
node pstore_drain_opportunistic = and(_pstore_drain_opportunistic_T_59, _pstore_drain_opportunistic_T_61)
reg pstore_drain_on_miss_REG : UInt<1>, clock
connect pstore_drain_on_miss_REG, io.cpu.s2_nack
node pstore_drain_on_miss = or(releaseInFlight, pstore_drain_on_miss_REG)
regreset pstore1_held : UInt<1>, clock, reset, UInt<1>(0h0)
node _pstore1_valid_likely_T = and(s2_valid, s2_write)
node pstore1_valid_likely = or(_pstore1_valid_likely_T, pstore1_held)
node _pstore1_valid_T = and(s2_valid_hit, s2_write)
node _pstore1_valid_T_1 = eq(s2_sc_fail, UInt<1>(0h0))
node _pstore1_valid_T_2 = and(_pstore1_valid_T, _pstore1_valid_T_1)
node _pstore1_valid_T_3 = eq(io.cpu.s2_kill, UInt<1>(0h0))
node _pstore1_valid_T_4 = and(_pstore1_valid_T_2, _pstore1_valid_T_3)
node pstore1_valid = or(_pstore1_valid_T_4, pstore1_held)
node _any_pstore_valid_T = or(pstore1_held, pstore2_valid)
connect any_pstore_valid, _any_pstore_valid_T
node _pstore_drain_structural_T = and(pstore1_valid_likely, pstore2_valid)
node _pstore_drain_structural_T_1 = and(s1_valid, s1_write)
node _pstore_drain_structural_T_2 = or(_pstore_drain_structural_T_1, pstore1_rmw)
node pstore_drain_structural = and(_pstore_drain_structural_T, _pstore_drain_structural_T_2)
node _T_48 = and(s2_valid_hit_pre_data_ecc, s2_write)
node _T_49 = eq(io.cpu.s2_kill, UInt<1>(0h0))
node _T_50 = and(_T_48, _T_49)
node _T_51 = or(_T_50, pstore1_held)
node _T_52 = eq(_T_51, pstore1_valid)
node _T_53 = or(pstore1_rmw, _T_52)
node _T_54 = asUInt(reset)
node _T_55 = eq(_T_54, UInt<1>(0h0))
when _T_55 :
node _T_56 = eq(_T_53, UInt<1>(0h0))
when _T_56 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:510 assert(pstore1_rmw || pstore1_valid_not_rmw(io.cpu.s2_kill) === pstore1_valid)\n") : printf_1
assert(clock, _T_53, UInt<1>(0h1), "") : assert_1
node _T_57 = and(pstore1_valid, pstore_drain_on_miss)
node _T_58 = and(s1_valid_not_nacked, s1_waw_hazard)
node pstore_drain_s2_kill = and(UInt<1>(0h1), io.cpu.s2_kill)
node _pstore_drain_T = eq(pstore1_merge_likely, UInt<1>(0h0))
node _pstore_drain_T_1 = and(UInt<1>(0h1), pstore_drain_structural)
node _pstore_drain_T_2 = and(s2_valid_hit_pre_data_ecc, s2_write)
node _pstore_drain_T_3 = eq(pstore_drain_s2_kill, UInt<1>(0h0))
node _pstore_drain_T_4 = and(_pstore_drain_T_2, _pstore_drain_T_3)
node _pstore_drain_T_5 = or(_pstore_drain_T_4, pstore1_held)
node _pstore_drain_T_6 = eq(pstore1_rmw, UInt<1>(0h0))
node _pstore_drain_T_7 = and(_pstore_drain_T_5, _pstore_drain_T_6)
node _pstore_drain_T_8 = or(_pstore_drain_T_7, pstore2_valid)
node _pstore_drain_T_9 = or(pstore_drain_opportunistic, pstore_drain_on_miss)
node _pstore_drain_T_10 = and(_pstore_drain_T_8, _pstore_drain_T_9)
node _pstore_drain_T_11 = or(_pstore_drain_T_1, _pstore_drain_T_10)
node pstore_drain = and(_pstore_drain_T, _pstore_drain_T_11)
node _pstore1_held_T = and(s2_valid_hit, s2_write)
node _pstore1_held_T_1 = eq(s2_sc_fail, UInt<1>(0h0))
node _pstore1_held_T_2 = and(_pstore1_held_T, _pstore1_held_T_1)
node _pstore1_held_T_3 = eq(io.cpu.s2_kill, UInt<1>(0h0))
node _pstore1_held_T_4 = and(_pstore1_held_T_2, _pstore1_held_T_3)
node _pstore1_held_T_5 = eq(s2_store_merge, UInt<1>(0h0))
node _pstore1_held_T_6 = and(_pstore1_held_T_4, _pstore1_held_T_5)
node _pstore1_held_T_7 = or(_pstore1_held_T_6, pstore1_held)
node _pstore1_held_T_8 = and(_pstore1_held_T_7, pstore2_valid)
node _pstore1_held_T_9 = eq(pstore_drain, UInt<1>(0h0))
node _pstore1_held_T_10 = and(_pstore1_held_T_8, _pstore1_held_T_9)
connect pstore1_held, _pstore1_held_T_10
node _advance_pstore1_T = or(pstore1_valid, s2_valid_correct)
node _advance_pstore1_T_1 = eq(pstore2_valid, pstore_drain)
node advance_pstore1 = and(_advance_pstore1_T, _advance_pstore1_T_1)
node _pstore2_valid_T = eq(pstore_drain, UInt<1>(0h0))
node _pstore2_valid_T_1 = and(pstore2_valid, _pstore2_valid_T)
node _pstore2_valid_T_2 = or(_pstore2_valid_T_1, advance_pstore1)
connect pstore2_valid, _pstore2_valid_T_2
node _pstore2_addr_T = mux(s2_correct, s2_vaddr, pstore1_addr)
reg pstore2_addr : UInt<40>, clock
when advance_pstore1 :
connect pstore2_addr, _pstore2_addr_T
node _pstore2_way_T = mux(s2_correct, s2_hit_way, pstore1_way)
reg pstore2_way : UInt<1>, clock
when advance_pstore1 :
connect pstore2_way, _pstore2_way_T
node _pstore2_storegen_data_T = bits(pstore1_storegen_data, 7, 0)
node _pstore2_storegen_data_T_1 = bits(pstore1_mask, 0, 0)
node _pstore2_storegen_data_T_2 = and(pstore1_merge, _pstore2_storegen_data_T_1)
node _pstore2_storegen_data_T_3 = or(advance_pstore1, _pstore2_storegen_data_T_2)
reg pstore2_storegen_data_r : UInt<8>, clock
when _pstore2_storegen_data_T_3 :
connect pstore2_storegen_data_r, _pstore2_storegen_data_T
node _pstore2_storegen_data_T_4 = bits(pstore1_storegen_data, 15, 8)
node _pstore2_storegen_data_T_5 = bits(pstore1_mask, 1, 1)
node _pstore2_storegen_data_T_6 = and(pstore1_merge, _pstore2_storegen_data_T_5)
node _pstore2_storegen_data_T_7 = or(advance_pstore1, _pstore2_storegen_data_T_6)
reg pstore2_storegen_data_r_1 : UInt<8>, clock
when _pstore2_storegen_data_T_7 :
connect pstore2_storegen_data_r_1, _pstore2_storegen_data_T_4
node _pstore2_storegen_data_T_8 = bits(pstore1_storegen_data, 23, 16)
node _pstore2_storegen_data_T_9 = bits(pstore1_mask, 2, 2)
node _pstore2_storegen_data_T_10 = and(pstore1_merge, _pstore2_storegen_data_T_9)
node _pstore2_storegen_data_T_11 = or(advance_pstore1, _pstore2_storegen_data_T_10)
reg pstore2_storegen_data_r_2 : UInt<8>, clock
when _pstore2_storegen_data_T_11 :
connect pstore2_storegen_data_r_2, _pstore2_storegen_data_T_8
node _pstore2_storegen_data_T_12 = bits(pstore1_storegen_data, 31, 24)
node _pstore2_storegen_data_T_13 = bits(pstore1_mask, 3, 3)
node _pstore2_storegen_data_T_14 = and(pstore1_merge, _pstore2_storegen_data_T_13)
node _pstore2_storegen_data_T_15 = or(advance_pstore1, _pstore2_storegen_data_T_14)
reg pstore2_storegen_data_r_3 : UInt<8>, clock
when _pstore2_storegen_data_T_15 :
connect pstore2_storegen_data_r_3, _pstore2_storegen_data_T_12
node _pstore2_storegen_data_T_16 = bits(pstore1_storegen_data, 39, 32)
node _pstore2_storegen_data_T_17 = bits(pstore1_mask, 4, 4)
node _pstore2_storegen_data_T_18 = and(pstore1_merge, _pstore2_storegen_data_T_17)
node _pstore2_storegen_data_T_19 = or(advance_pstore1, _pstore2_storegen_data_T_18)
reg pstore2_storegen_data_r_4 : UInt<8>, clock
when _pstore2_storegen_data_T_19 :
connect pstore2_storegen_data_r_4, _pstore2_storegen_data_T_16
node _pstore2_storegen_data_T_20 = bits(pstore1_storegen_data, 47, 40)
node _pstore2_storegen_data_T_21 = bits(pstore1_mask, 5, 5)
node _pstore2_storegen_data_T_22 = and(pstore1_merge, _pstore2_storegen_data_T_21)
node _pstore2_storegen_data_T_23 = or(advance_pstore1, _pstore2_storegen_data_T_22)
reg pstore2_storegen_data_r_5 : UInt<8>, clock
when _pstore2_storegen_data_T_23 :
connect pstore2_storegen_data_r_5, _pstore2_storegen_data_T_20
node _pstore2_storegen_data_T_24 = bits(pstore1_storegen_data, 55, 48)
node _pstore2_storegen_data_T_25 = bits(pstore1_mask, 6, 6)
node _pstore2_storegen_data_T_26 = and(pstore1_merge, _pstore2_storegen_data_T_25)
node _pstore2_storegen_data_T_27 = or(advance_pstore1, _pstore2_storegen_data_T_26)
reg pstore2_storegen_data_r_6 : UInt<8>, clock
when _pstore2_storegen_data_T_27 :
connect pstore2_storegen_data_r_6, _pstore2_storegen_data_T_24
node _pstore2_storegen_data_T_28 = bits(pstore1_storegen_data, 63, 56)
node _pstore2_storegen_data_T_29 = bits(pstore1_mask, 7, 7)
node _pstore2_storegen_data_T_30 = and(pstore1_merge, _pstore2_storegen_data_T_29)
node _pstore2_storegen_data_T_31 = or(advance_pstore1, _pstore2_storegen_data_T_30)
reg pstore2_storegen_data_r_7 : UInt<8>, clock
when _pstore2_storegen_data_T_31 :
connect pstore2_storegen_data_r_7, _pstore2_storegen_data_T_28
node pstore2_storegen_data_lo_lo = cat(pstore2_storegen_data_r_1, pstore2_storegen_data_r)
node pstore2_storegen_data_lo_hi = cat(pstore2_storegen_data_r_3, pstore2_storegen_data_r_2)
node pstore2_storegen_data_lo = cat(pstore2_storegen_data_lo_hi, pstore2_storegen_data_lo_lo)
node pstore2_storegen_data_hi_lo = cat(pstore2_storegen_data_r_5, pstore2_storegen_data_r_4)
node pstore2_storegen_data_hi_hi = cat(pstore2_storegen_data_r_7, pstore2_storegen_data_r_6)
node pstore2_storegen_data_hi = cat(pstore2_storegen_data_hi_hi, pstore2_storegen_data_hi_lo)
node pstore2_storegen_data = cat(pstore2_storegen_data_hi, pstore2_storegen_data_lo)
reg pstore2_storegen_mask : UInt<8>, clock
node _pstore2_storegen_mask_T = or(advance_pstore1, pstore1_merge)
when _pstore2_storegen_mask_T :
node _pstore2_storegen_mask_mergedMask_T = mux(pstore1_merge, pstore2_storegen_mask, UInt<1>(0h0))
node pstore2_storegen_mask_mergedMask = or(pstore1_mask, _pstore2_storegen_mask_mergedMask_T)
node _pstore2_storegen_mask_mask_T = not(pstore2_storegen_mask_mergedMask)
node _pstore2_storegen_mask_mask_T_1 = mux(s2_correct, UInt<1>(0h0), _pstore2_storegen_mask_mask_T)
node _pstore2_storegen_mask_mask_T_2 = not(_pstore2_storegen_mask_mask_T_1)
connect pstore2_storegen_mask, _pstore2_storegen_mask_mask_T_2
connect s2_store_merge, UInt<1>(0h0)
node dataArb_io_in_0_valid_s2_kill = and(UInt<1>(0h0), io.cpu.s2_kill)
node _dataArb_io_in_0_valid_T = eq(pstore1_merge_likely, UInt<1>(0h0))
node _dataArb_io_in_0_valid_T_1 = and(UInt<1>(0h1), pstore_drain_structural)
node _dataArb_io_in_0_valid_T_2 = and(s2_valid_hit_pre_data_ecc, s2_write)
node _dataArb_io_in_0_valid_T_3 = eq(dataArb_io_in_0_valid_s2_kill, UInt<1>(0h0))
node _dataArb_io_in_0_valid_T_4 = and(_dataArb_io_in_0_valid_T_2, _dataArb_io_in_0_valid_T_3)
node _dataArb_io_in_0_valid_T_5 = or(_dataArb_io_in_0_valid_T_4, pstore1_held)
node _dataArb_io_in_0_valid_T_6 = eq(pstore1_rmw, UInt<1>(0h0))
node _dataArb_io_in_0_valid_T_7 = and(_dataArb_io_in_0_valid_T_5, _dataArb_io_in_0_valid_T_6)
node _dataArb_io_in_0_valid_T_8 = or(_dataArb_io_in_0_valid_T_7, pstore2_valid)
node _dataArb_io_in_0_valid_T_9 = or(pstore_drain_opportunistic, pstore_drain_on_miss)
node _dataArb_io_in_0_valid_T_10 = and(_dataArb_io_in_0_valid_T_8, _dataArb_io_in_0_valid_T_9)
node _dataArb_io_in_0_valid_T_11 = or(_dataArb_io_in_0_valid_T_1, _dataArb_io_in_0_valid_T_10)
node _dataArb_io_in_0_valid_T_12 = and(_dataArb_io_in_0_valid_T, _dataArb_io_in_0_valid_T_11)
connect dataArb.io.in[0].valid, _dataArb_io_in_0_valid_T_12
connect dataArb.io.in[0].bits.write, pstore_drain
node _dataArb_io_in_0_bits_addr_T = mux(pstore2_valid, pstore2_addr, pstore1_addr)
connect dataArb.io.in[0].bits.addr, _dataArb_io_in_0_bits_addr_T
node _dataArb_io_in_0_bits_way_en_T = mux(pstore2_valid, pstore2_way, pstore1_way)
connect dataArb.io.in[0].bits.way_en, _dataArb_io_in_0_bits_way_en_T
node _dataArb_io_in_0_bits_wdata_T = mux(pstore2_valid, pstore2_storegen_data, pstore1_data)
node _dataArb_io_in_0_bits_wdata_T_1 = bits(_dataArb_io_in_0_bits_wdata_T, 7, 0)
node _dataArb_io_in_0_bits_wdata_T_2 = bits(_dataArb_io_in_0_bits_wdata_T, 15, 8)
node _dataArb_io_in_0_bits_wdata_T_3 = bits(_dataArb_io_in_0_bits_wdata_T, 23, 16)
node _dataArb_io_in_0_bits_wdata_T_4 = bits(_dataArb_io_in_0_bits_wdata_T, 31, 24)
node _dataArb_io_in_0_bits_wdata_T_5 = bits(_dataArb_io_in_0_bits_wdata_T, 39, 32)
node _dataArb_io_in_0_bits_wdata_T_6 = bits(_dataArb_io_in_0_bits_wdata_T, 47, 40)
node _dataArb_io_in_0_bits_wdata_T_7 = bits(_dataArb_io_in_0_bits_wdata_T, 55, 48)
node _dataArb_io_in_0_bits_wdata_T_8 = bits(_dataArb_io_in_0_bits_wdata_T, 63, 56)
node dataArb_io_in_0_bits_wdata_lo_lo = cat(_dataArb_io_in_0_bits_wdata_T_2, _dataArb_io_in_0_bits_wdata_T_1)
node dataArb_io_in_0_bits_wdata_lo_hi = cat(_dataArb_io_in_0_bits_wdata_T_4, _dataArb_io_in_0_bits_wdata_T_3)
node dataArb_io_in_0_bits_wdata_lo = cat(dataArb_io_in_0_bits_wdata_lo_hi, dataArb_io_in_0_bits_wdata_lo_lo)
node dataArb_io_in_0_bits_wdata_hi_lo = cat(_dataArb_io_in_0_bits_wdata_T_6, _dataArb_io_in_0_bits_wdata_T_5)
node dataArb_io_in_0_bits_wdata_hi_hi = cat(_dataArb_io_in_0_bits_wdata_T_8, _dataArb_io_in_0_bits_wdata_T_7)
node dataArb_io_in_0_bits_wdata_hi = cat(dataArb_io_in_0_bits_wdata_hi_hi, dataArb_io_in_0_bits_wdata_hi_lo)
node _dataArb_io_in_0_bits_wdata_T_9 = cat(dataArb_io_in_0_bits_wdata_hi, dataArb_io_in_0_bits_wdata_lo)
connect dataArb.io.in[0].bits.wdata, _dataArb_io_in_0_bits_wdata_T_9
node _dataArb_io_in_0_bits_wordMask_eccMask_T = bits(dataArb.io.in[0].bits.eccMask, 0, 0)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_1 = bits(dataArb.io.in[0].bits.eccMask, 1, 1)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_2 = bits(dataArb.io.in[0].bits.eccMask, 2, 2)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_3 = bits(dataArb.io.in[0].bits.eccMask, 3, 3)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_4 = bits(dataArb.io.in[0].bits.eccMask, 4, 4)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_5 = bits(dataArb.io.in[0].bits.eccMask, 5, 5)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_6 = bits(dataArb.io.in[0].bits.eccMask, 6, 6)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_7 = bits(dataArb.io.in[0].bits.eccMask, 7, 7)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_8 = or(_dataArb_io_in_0_bits_wordMask_eccMask_T, _dataArb_io_in_0_bits_wordMask_eccMask_T_1)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_9 = or(_dataArb_io_in_0_bits_wordMask_eccMask_T_8, _dataArb_io_in_0_bits_wordMask_eccMask_T_2)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_10 = or(_dataArb_io_in_0_bits_wordMask_eccMask_T_9, _dataArb_io_in_0_bits_wordMask_eccMask_T_3)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_11 = or(_dataArb_io_in_0_bits_wordMask_eccMask_T_10, _dataArb_io_in_0_bits_wordMask_eccMask_T_4)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_12 = or(_dataArb_io_in_0_bits_wordMask_eccMask_T_11, _dataArb_io_in_0_bits_wordMask_eccMask_T_5)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_13 = or(_dataArb_io_in_0_bits_wordMask_eccMask_T_12, _dataArb_io_in_0_bits_wordMask_eccMask_T_6)
node dataArb_io_in_0_bits_wordMask_eccMask = or(_dataArb_io_in_0_bits_wordMask_eccMask_T_13, _dataArb_io_in_0_bits_wordMask_eccMask_T_7)
node _dataArb_io_in_0_bits_wordMask_wordMask_T = mux(pstore2_valid, pstore2_addr, pstore1_addr)
node dataArb_io_in_0_bits_wordMask_wordMask = dshl(UInt<1>(0h1), UInt<1>(0h0))
node _dataArb_io_in_0_bits_wordMask_T = bits(dataArb_io_in_0_bits_wordMask_wordMask, 0, 0)
node _dataArb_io_in_0_bits_wordMask_T_1 = bits(dataArb_io_in_0_bits_wordMask_wordMask, 1, 1)
node _dataArb_io_in_0_bits_wordMask_T_2 = cat(_dataArb_io_in_0_bits_wordMask_T_1, _dataArb_io_in_0_bits_wordMask_T)
node _dataArb_io_in_0_bits_wordMask_T_3 = and(_dataArb_io_in_0_bits_wordMask_T_2, dataArb_io_in_0_bits_wordMask_eccMask)
connect dataArb.io.in[0].bits.wordMask, _dataArb_io_in_0_bits_wordMask_T_3
node _dataArb_io_in_0_bits_eccMask_T = mux(pstore2_valid, pstore2_storegen_mask, pstore1_mask)
node _dataArb_io_in_0_bits_eccMask_T_1 = bits(_dataArb_io_in_0_bits_eccMask_T, 0, 0)
node _dataArb_io_in_0_bits_eccMask_T_2 = bits(_dataArb_io_in_0_bits_eccMask_T, 1, 1)
node _dataArb_io_in_0_bits_eccMask_T_3 = bits(_dataArb_io_in_0_bits_eccMask_T, 2, 2)
node _dataArb_io_in_0_bits_eccMask_T_4 = bits(_dataArb_io_in_0_bits_eccMask_T, 3, 3)
node _dataArb_io_in_0_bits_eccMask_T_5 = bits(_dataArb_io_in_0_bits_eccMask_T, 4, 4)
node _dataArb_io_in_0_bits_eccMask_T_6 = bits(_dataArb_io_in_0_bits_eccMask_T, 5, 5)
node _dataArb_io_in_0_bits_eccMask_T_7 = bits(_dataArb_io_in_0_bits_eccMask_T, 6, 6)
node _dataArb_io_in_0_bits_eccMask_T_8 = bits(_dataArb_io_in_0_bits_eccMask_T, 7, 7)
node _dataArb_io_in_0_bits_eccMask_T_9 = orr(_dataArb_io_in_0_bits_eccMask_T_1)
node _dataArb_io_in_0_bits_eccMask_T_10 = orr(_dataArb_io_in_0_bits_eccMask_T_2)
node _dataArb_io_in_0_bits_eccMask_T_11 = orr(_dataArb_io_in_0_bits_eccMask_T_3)
node _dataArb_io_in_0_bits_eccMask_T_12 = orr(_dataArb_io_in_0_bits_eccMask_T_4)
node _dataArb_io_in_0_bits_eccMask_T_13 = orr(_dataArb_io_in_0_bits_eccMask_T_5)
node _dataArb_io_in_0_bits_eccMask_T_14 = orr(_dataArb_io_in_0_bits_eccMask_T_6)
node _dataArb_io_in_0_bits_eccMask_T_15 = orr(_dataArb_io_in_0_bits_eccMask_T_7)
node _dataArb_io_in_0_bits_eccMask_T_16 = orr(_dataArb_io_in_0_bits_eccMask_T_8)
node dataArb_io_in_0_bits_eccMask_lo_lo = cat(_dataArb_io_in_0_bits_eccMask_T_10, _dataArb_io_in_0_bits_eccMask_T_9)
node dataArb_io_in_0_bits_eccMask_lo_hi = cat(_dataArb_io_in_0_bits_eccMask_T_12, _dataArb_io_in_0_bits_eccMask_T_11)
node dataArb_io_in_0_bits_eccMask_lo = cat(dataArb_io_in_0_bits_eccMask_lo_hi, dataArb_io_in_0_bits_eccMask_lo_lo)
node dataArb_io_in_0_bits_eccMask_hi_lo = cat(_dataArb_io_in_0_bits_eccMask_T_14, _dataArb_io_in_0_bits_eccMask_T_13)
node dataArb_io_in_0_bits_eccMask_hi_hi = cat(_dataArb_io_in_0_bits_eccMask_T_16, _dataArb_io_in_0_bits_eccMask_T_15)
node dataArb_io_in_0_bits_eccMask_hi = cat(dataArb_io_in_0_bits_eccMask_hi_hi, dataArb_io_in_0_bits_eccMask_hi_lo)
node _dataArb_io_in_0_bits_eccMask_T_17 = cat(dataArb_io_in_0_bits_eccMask_hi, dataArb_io_in_0_bits_eccMask_lo)
connect dataArb.io.in[0].bits.eccMask, _dataArb_io_in_0_bits_eccMask_T_17
node _s1_hazard_T = bits(pstore1_addr, 10, 3)
node _s1_hazard_T_1 = bits(s1_vaddr, 10, 3)
node _s1_hazard_T_2 = eq(_s1_hazard_T, _s1_hazard_T_1)
node _s1_hazard_T_3 = bits(pstore1_mask, 0, 0)
node _s1_hazard_T_4 = bits(pstore1_mask, 1, 1)
node _s1_hazard_T_5 = bits(pstore1_mask, 2, 2)
node _s1_hazard_T_6 = bits(pstore1_mask, 3, 3)
node _s1_hazard_T_7 = bits(pstore1_mask, 4, 4)
node _s1_hazard_T_8 = bits(pstore1_mask, 5, 5)
node _s1_hazard_T_9 = bits(pstore1_mask, 6, 6)
node _s1_hazard_T_10 = bits(pstore1_mask, 7, 7)
node _s1_hazard_T_11 = orr(_s1_hazard_T_3)
node _s1_hazard_T_12 = orr(_s1_hazard_T_4)
node _s1_hazard_T_13 = orr(_s1_hazard_T_5)
node _s1_hazard_T_14 = orr(_s1_hazard_T_6)
node _s1_hazard_T_15 = orr(_s1_hazard_T_7)
node _s1_hazard_T_16 = orr(_s1_hazard_T_8)
node _s1_hazard_T_17 = orr(_s1_hazard_T_9)
node _s1_hazard_T_18 = orr(_s1_hazard_T_10)
node s1_hazard_lo_lo = cat(_s1_hazard_T_12, _s1_hazard_T_11)
node s1_hazard_lo_hi = cat(_s1_hazard_T_14, _s1_hazard_T_13)
node s1_hazard_lo = cat(s1_hazard_lo_hi, s1_hazard_lo_lo)
node s1_hazard_hi_lo = cat(_s1_hazard_T_16, _s1_hazard_T_15)
node s1_hazard_hi_hi = cat(_s1_hazard_T_18, _s1_hazard_T_17)
node s1_hazard_hi = cat(s1_hazard_hi_hi, s1_hazard_hi_lo)
node _s1_hazard_T_19 = cat(s1_hazard_hi, s1_hazard_lo)
node _s1_hazard_T_20 = bits(_s1_hazard_T_19, 0, 0)
node _s1_hazard_T_21 = bits(_s1_hazard_T_19, 1, 1)
node _s1_hazard_T_22 = bits(_s1_hazard_T_19, 2, 2)
node _s1_hazard_T_23 = bits(_s1_hazard_T_19, 3, 3)
node _s1_hazard_T_24 = bits(_s1_hazard_T_19, 4, 4)
node _s1_hazard_T_25 = bits(_s1_hazard_T_19, 5, 5)
node _s1_hazard_T_26 = bits(_s1_hazard_T_19, 6, 6)
node _s1_hazard_T_27 = bits(_s1_hazard_T_19, 7, 7)
node s1_hazard_lo_lo_1 = cat(_s1_hazard_T_21, _s1_hazard_T_20)
node s1_hazard_lo_hi_1 = cat(_s1_hazard_T_23, _s1_hazard_T_22)
node s1_hazard_lo_1 = cat(s1_hazard_lo_hi_1, s1_hazard_lo_lo_1)
node s1_hazard_hi_lo_1 = cat(_s1_hazard_T_25, _s1_hazard_T_24)
node s1_hazard_hi_hi_1 = cat(_s1_hazard_T_27, _s1_hazard_T_26)
node s1_hazard_hi_1 = cat(s1_hazard_hi_hi_1, s1_hazard_hi_lo_1)
node _s1_hazard_T_28 = cat(s1_hazard_hi_1, s1_hazard_lo_1)
node _s1_hazard_T_29 = bits(s1_mask_xwr, 0, 0)
node _s1_hazard_T_30 = bits(s1_mask_xwr, 1, 1)
node _s1_hazard_T_31 = bits(s1_mask_xwr, 2, 2)
node _s1_hazard_T_32 = bits(s1_mask_xwr, 3, 3)
node _s1_hazard_T_33 = bits(s1_mask_xwr, 4, 4)
node _s1_hazard_T_34 = bits(s1_mask_xwr, 5, 5)
node _s1_hazard_T_35 = bits(s1_mask_xwr, 6, 6)
node _s1_hazard_T_36 = bits(s1_mask_xwr, 7, 7)
node _s1_hazard_T_37 = orr(_s1_hazard_T_29)
node _s1_hazard_T_38 = orr(_s1_hazard_T_30)
node _s1_hazard_T_39 = orr(_s1_hazard_T_31)
node _s1_hazard_T_40 = orr(_s1_hazard_T_32)
node _s1_hazard_T_41 = orr(_s1_hazard_T_33)
node _s1_hazard_T_42 = orr(_s1_hazard_T_34)
node _s1_hazard_T_43 = orr(_s1_hazard_T_35)
node _s1_hazard_T_44 = orr(_s1_hazard_T_36)
node s1_hazard_lo_lo_2 = cat(_s1_hazard_T_38, _s1_hazard_T_37)
node s1_hazard_lo_hi_2 = cat(_s1_hazard_T_40, _s1_hazard_T_39)
node s1_hazard_lo_2 = cat(s1_hazard_lo_hi_2, s1_hazard_lo_lo_2)
node s1_hazard_hi_lo_2 = cat(_s1_hazard_T_42, _s1_hazard_T_41)
node s1_hazard_hi_hi_2 = cat(_s1_hazard_T_44, _s1_hazard_T_43)
node s1_hazard_hi_2 = cat(s1_hazard_hi_hi_2, s1_hazard_hi_lo_2)
node _s1_hazard_T_45 = cat(s1_hazard_hi_2, s1_hazard_lo_2)
node _s1_hazard_T_46 = bits(_s1_hazard_T_45, 0, 0)
node _s1_hazard_T_47 = bits(_s1_hazard_T_45, 1, 1)
node _s1_hazard_T_48 = bits(_s1_hazard_T_45, 2, 2)
node _s1_hazard_T_49 = bits(_s1_hazard_T_45, 3, 3)
node _s1_hazard_T_50 = bits(_s1_hazard_T_45, 4, 4)
node _s1_hazard_T_51 = bits(_s1_hazard_T_45, 5, 5)
node _s1_hazard_T_52 = bits(_s1_hazard_T_45, 6, 6)
node _s1_hazard_T_53 = bits(_s1_hazard_T_45, 7, 7)
node s1_hazard_lo_lo_3 = cat(_s1_hazard_T_47, _s1_hazard_T_46)
node s1_hazard_lo_hi_3 = cat(_s1_hazard_T_49, _s1_hazard_T_48)
node s1_hazard_lo_3 = cat(s1_hazard_lo_hi_3, s1_hazard_lo_lo_3)
node s1_hazard_hi_lo_3 = cat(_s1_hazard_T_51, _s1_hazard_T_50)
node s1_hazard_hi_hi_3 = cat(_s1_hazard_T_53, _s1_hazard_T_52)
node s1_hazard_hi_3 = cat(s1_hazard_hi_hi_3, s1_hazard_hi_lo_3)
node _s1_hazard_T_54 = cat(s1_hazard_hi_3, s1_hazard_lo_3)
node _s1_hazard_T_55 = and(_s1_hazard_T_28, _s1_hazard_T_54)
node _s1_hazard_T_56 = orr(_s1_hazard_T_55)
node _s1_hazard_T_57 = and(pstore1_mask, s1_mask_xwr)
node _s1_hazard_T_58 = orr(_s1_hazard_T_57)
node _s1_hazard_T_59 = mux(s1_write, _s1_hazard_T_56, _s1_hazard_T_58)
node _s1_hazard_T_60 = and(_s1_hazard_T_2, _s1_hazard_T_59)
node _s1_hazard_T_61 = and(pstore1_valid_likely, _s1_hazard_T_60)
node _s1_hazard_T_62 = bits(pstore2_addr, 10, 3)
node _s1_hazard_T_63 = bits(s1_vaddr, 10, 3)
node _s1_hazard_T_64 = eq(_s1_hazard_T_62, _s1_hazard_T_63)
node _s1_hazard_T_65 = bits(pstore2_storegen_mask, 0, 0)
node _s1_hazard_T_66 = bits(pstore2_storegen_mask, 1, 1)
node _s1_hazard_T_67 = bits(pstore2_storegen_mask, 2, 2)
node _s1_hazard_T_68 = bits(pstore2_storegen_mask, 3, 3)
node _s1_hazard_T_69 = bits(pstore2_storegen_mask, 4, 4)
node _s1_hazard_T_70 = bits(pstore2_storegen_mask, 5, 5)
node _s1_hazard_T_71 = bits(pstore2_storegen_mask, 6, 6)
node _s1_hazard_T_72 = bits(pstore2_storegen_mask, 7, 7)
node _s1_hazard_T_73 = orr(_s1_hazard_T_65)
node _s1_hazard_T_74 = orr(_s1_hazard_T_66)
node _s1_hazard_T_75 = orr(_s1_hazard_T_67)
node _s1_hazard_T_76 = orr(_s1_hazard_T_68)
node _s1_hazard_T_77 = orr(_s1_hazard_T_69)
node _s1_hazard_T_78 = orr(_s1_hazard_T_70)
node _s1_hazard_T_79 = orr(_s1_hazard_T_71)
node _s1_hazard_T_80 = orr(_s1_hazard_T_72)
node s1_hazard_lo_lo_4 = cat(_s1_hazard_T_74, _s1_hazard_T_73)
node s1_hazard_lo_hi_4 = cat(_s1_hazard_T_76, _s1_hazard_T_75)
node s1_hazard_lo_4 = cat(s1_hazard_lo_hi_4, s1_hazard_lo_lo_4)
node s1_hazard_hi_lo_4 = cat(_s1_hazard_T_78, _s1_hazard_T_77)
node s1_hazard_hi_hi_4 = cat(_s1_hazard_T_80, _s1_hazard_T_79)
node s1_hazard_hi_4 = cat(s1_hazard_hi_hi_4, s1_hazard_hi_lo_4)
node _s1_hazard_T_81 = cat(s1_hazard_hi_4, s1_hazard_lo_4)
node _s1_hazard_T_82 = bits(_s1_hazard_T_81, 0, 0)
node _s1_hazard_T_83 = bits(_s1_hazard_T_81, 1, 1)
node _s1_hazard_T_84 = bits(_s1_hazard_T_81, 2, 2)
node _s1_hazard_T_85 = bits(_s1_hazard_T_81, 3, 3)
node _s1_hazard_T_86 = bits(_s1_hazard_T_81, 4, 4)
node _s1_hazard_T_87 = bits(_s1_hazard_T_81, 5, 5)
node _s1_hazard_T_88 = bits(_s1_hazard_T_81, 6, 6)
node _s1_hazard_T_89 = bits(_s1_hazard_T_81, 7, 7)
node s1_hazard_lo_lo_5 = cat(_s1_hazard_T_83, _s1_hazard_T_82)
node s1_hazard_lo_hi_5 = cat(_s1_hazard_T_85, _s1_hazard_T_84)
node s1_hazard_lo_5 = cat(s1_hazard_lo_hi_5, s1_hazard_lo_lo_5)
node s1_hazard_hi_lo_5 = cat(_s1_hazard_T_87, _s1_hazard_T_86)
node s1_hazard_hi_hi_5 = cat(_s1_hazard_T_89, _s1_hazard_T_88)
node s1_hazard_hi_5 = cat(s1_hazard_hi_hi_5, s1_hazard_hi_lo_5)
node _s1_hazard_T_90 = cat(s1_hazard_hi_5, s1_hazard_lo_5)
node _s1_hazard_T_91 = bits(s1_mask_xwr, 0, 0)
node _s1_hazard_T_92 = bits(s1_mask_xwr, 1, 1)
node _s1_hazard_T_93 = bits(s1_mask_xwr, 2, 2)
node _s1_hazard_T_94 = bits(s1_mask_xwr, 3, 3)
node _s1_hazard_T_95 = bits(s1_mask_xwr, 4, 4)
node _s1_hazard_T_96 = bits(s1_mask_xwr, 5, 5)
node _s1_hazard_T_97 = bits(s1_mask_xwr, 6, 6)
node _s1_hazard_T_98 = bits(s1_mask_xwr, 7, 7)
node _s1_hazard_T_99 = orr(_s1_hazard_T_91)
node _s1_hazard_T_100 = orr(_s1_hazard_T_92)
node _s1_hazard_T_101 = orr(_s1_hazard_T_93)
node _s1_hazard_T_102 = orr(_s1_hazard_T_94)
node _s1_hazard_T_103 = orr(_s1_hazard_T_95)
node _s1_hazard_T_104 = orr(_s1_hazard_T_96)
node _s1_hazard_T_105 = orr(_s1_hazard_T_97)
node _s1_hazard_T_106 = orr(_s1_hazard_T_98)
node s1_hazard_lo_lo_6 = cat(_s1_hazard_T_100, _s1_hazard_T_99)
node s1_hazard_lo_hi_6 = cat(_s1_hazard_T_102, _s1_hazard_T_101)
node s1_hazard_lo_6 = cat(s1_hazard_lo_hi_6, s1_hazard_lo_lo_6)
node s1_hazard_hi_lo_6 = cat(_s1_hazard_T_104, _s1_hazard_T_103)
node s1_hazard_hi_hi_6 = cat(_s1_hazard_T_106, _s1_hazard_T_105)
node s1_hazard_hi_6 = cat(s1_hazard_hi_hi_6, s1_hazard_hi_lo_6)
node _s1_hazard_T_107 = cat(s1_hazard_hi_6, s1_hazard_lo_6)
node _s1_hazard_T_108 = bits(_s1_hazard_T_107, 0, 0)
node _s1_hazard_T_109 = bits(_s1_hazard_T_107, 1, 1)
node _s1_hazard_T_110 = bits(_s1_hazard_T_107, 2, 2)
node _s1_hazard_T_111 = bits(_s1_hazard_T_107, 3, 3)
node _s1_hazard_T_112 = bits(_s1_hazard_T_107, 4, 4)
node _s1_hazard_T_113 = bits(_s1_hazard_T_107, 5, 5)
node _s1_hazard_T_114 = bits(_s1_hazard_T_107, 6, 6)
node _s1_hazard_T_115 = bits(_s1_hazard_T_107, 7, 7)
node s1_hazard_lo_lo_7 = cat(_s1_hazard_T_109, _s1_hazard_T_108)
node s1_hazard_lo_hi_7 = cat(_s1_hazard_T_111, _s1_hazard_T_110)
node s1_hazard_lo_7 = cat(s1_hazard_lo_hi_7, s1_hazard_lo_lo_7)
node s1_hazard_hi_lo_7 = cat(_s1_hazard_T_113, _s1_hazard_T_112)
node s1_hazard_hi_hi_7 = cat(_s1_hazard_T_115, _s1_hazard_T_114)
node s1_hazard_hi_7 = cat(s1_hazard_hi_hi_7, s1_hazard_hi_lo_7)
node _s1_hazard_T_116 = cat(s1_hazard_hi_7, s1_hazard_lo_7)
node _s1_hazard_T_117 = and(_s1_hazard_T_90, _s1_hazard_T_116)
node _s1_hazard_T_118 = orr(_s1_hazard_T_117)
node _s1_hazard_T_119 = and(pstore2_storegen_mask, s1_mask_xwr)
node _s1_hazard_T_120 = orr(_s1_hazard_T_119)
node _s1_hazard_T_121 = mux(s1_write, _s1_hazard_T_118, _s1_hazard_T_120)
node _s1_hazard_T_122 = and(_s1_hazard_T_64, _s1_hazard_T_121)
node _s1_hazard_T_123 = and(pstore2_valid, _s1_hazard_T_122)
node s1_hazard = or(_s1_hazard_T_61, _s1_hazard_T_123)
node s1_raw_hazard = and(s1_read, s1_hazard)
connect s1_waw_hazard, UInt<1>(0h0)
node _T_59 = and(s1_valid, s1_raw_hazard)
when _T_59 :
connect s1_nack, UInt<1>(0h1)
reg io_cpu_s2_nack_cause_raw_REG : UInt<1>, clock
connect io_cpu_s2_nack_cause_raw_REG, s1_raw_hazard
node _io_cpu_s2_nack_cause_raw_T = eq(s2_waw_hazard, UInt<1>(0h0))
node _io_cpu_s2_nack_cause_raw_T_1 = or(_io_cpu_s2_nack_cause_raw_T, s2_store_merge)
node _io_cpu_s2_nack_cause_raw_T_2 = eq(_io_cpu_s2_nack_cause_raw_T_1, UInt<1>(0h0))
node _io_cpu_s2_nack_cause_raw_T_3 = or(io_cpu_s2_nack_cause_raw_REG, _io_cpu_s2_nack_cause_raw_T_2)
connect io.cpu.s2_nack_cause_raw, _io_cpu_s2_nack_cause_raw_T_3
node _a_source_T = not(uncachedInFlight[0])
node _a_source_T_1 = shl(_a_source_T, 0)
node _a_source_T_2 = bits(_a_source_T_1, 0, 0)
node _acquire_address_T = shr(s2_req.addr, 6)
node acquire_address = shl(_acquire_address_T, 6)
node _a_mask_T = shl(UInt<1>(0h0), 3)
node a_mask = dshl(pstore1_mask, _a_mask_T)
node _get_legal_T = leq(UInt<1>(0h0), s2_req.size)
node _get_legal_T_1 = leq(s2_req.size, UInt<4>(0hc))
node _get_legal_T_2 = and(_get_legal_T, _get_legal_T_1)
node _get_legal_T_3 = or(UInt<1>(0h0), _get_legal_T_2)
node _get_legal_T_4 = xor(s2_req.addr, UInt<14>(0h3000))
node _get_legal_T_5 = cvt(_get_legal_T_4)
node _get_legal_T_6 = and(_get_legal_T_5, asSInt(UInt<33>(0h9a113000)))
node _get_legal_T_7 = asSInt(_get_legal_T_6)
node _get_legal_T_8 = eq(_get_legal_T_7, asSInt(UInt<1>(0h0)))
node _get_legal_T_9 = and(_get_legal_T_3, _get_legal_T_8)
node _get_legal_T_10 = leq(UInt<1>(0h0), s2_req.size)
node _get_legal_T_11 = leq(s2_req.size, UInt<3>(0h6))
node _get_legal_T_12 = and(_get_legal_T_10, _get_legal_T_11)
node _get_legal_T_13 = or(UInt<1>(0h0), _get_legal_T_12)
node _get_legal_T_14 = xor(s2_req.addr, UInt<1>(0h0))
node _get_legal_T_15 = cvt(_get_legal_T_14)
node _get_legal_T_16 = and(_get_legal_T_15, asSInt(UInt<33>(0h9a112000)))
node _get_legal_T_17 = asSInt(_get_legal_T_16)
node _get_legal_T_18 = eq(_get_legal_T_17, asSInt(UInt<1>(0h0)))
node _get_legal_T_19 = xor(s2_req.addr, UInt<17>(0h10000))
node _get_legal_T_20 = cvt(_get_legal_T_19)
node _get_legal_T_21 = and(_get_legal_T_20, asSInt(UInt<33>(0h9a110000)))
node _get_legal_T_22 = asSInt(_get_legal_T_21)
node _get_legal_T_23 = eq(_get_legal_T_22, asSInt(UInt<1>(0h0)))
node _get_legal_T_24 = xor(s2_req.addr, UInt<21>(0h100000))
node _get_legal_T_25 = cvt(_get_legal_T_24)
node _get_legal_T_26 = and(_get_legal_T_25, asSInt(UInt<33>(0h9a103000)))
node _get_legal_T_27 = asSInt(_get_legal_T_26)
node _get_legal_T_28 = eq(_get_legal_T_27, asSInt(UInt<1>(0h0)))
node _get_legal_T_29 = xor(s2_req.addr, UInt<21>(0h100000))
node _get_legal_T_30 = cvt(_get_legal_T_29)
node _get_legal_T_31 = and(_get_legal_T_30, asSInt(UInt<33>(0h9a110000)))
node _get_legal_T_32 = asSInt(_get_legal_T_31)
node _get_legal_T_33 = eq(_get_legal_T_32, asSInt(UInt<1>(0h0)))
node _get_legal_T_34 = xor(s2_req.addr, UInt<26>(0h2000000))
node _get_legal_T_35 = cvt(_get_legal_T_34)
node _get_legal_T_36 = and(_get_legal_T_35, asSInt(UInt<33>(0h9a110000)))
node _get_legal_T_37 = asSInt(_get_legal_T_36)
node _get_legal_T_38 = eq(_get_legal_T_37, asSInt(UInt<1>(0h0)))
node _get_legal_T_39 = xor(s2_req.addr, UInt<26>(0h2010000))
node _get_legal_T_40 = cvt(_get_legal_T_39)
node _get_legal_T_41 = and(_get_legal_T_40, asSInt(UInt<33>(0h9a113000)))
node _get_legal_T_42 = asSInt(_get_legal_T_41)
node _get_legal_T_43 = eq(_get_legal_T_42, asSInt(UInt<1>(0h0)))
node _get_legal_T_44 = xor(s2_req.addr, UInt<28>(0h8000000))
node _get_legal_T_45 = cvt(_get_legal_T_44)
node _get_legal_T_46 = and(_get_legal_T_45, asSInt(UInt<33>(0h98000000)))
node _get_legal_T_47 = asSInt(_get_legal_T_46)
node _get_legal_T_48 = eq(_get_legal_T_47, asSInt(UInt<1>(0h0)))
node _get_legal_T_49 = xor(s2_req.addr, UInt<28>(0h8000000))
node _get_legal_T_50 = cvt(_get_legal_T_49)
node _get_legal_T_51 = and(_get_legal_T_50, asSInt(UInt<33>(0h9a110000)))
node _get_legal_T_52 = asSInt(_get_legal_T_51)
node _get_legal_T_53 = eq(_get_legal_T_52, asSInt(UInt<1>(0h0)))
node _get_legal_T_54 = xor(s2_req.addr, UInt<29>(0h10000000))
node _get_legal_T_55 = cvt(_get_legal_T_54)
node _get_legal_T_56 = and(_get_legal_T_55, asSInt(UInt<33>(0h9a113000)))
node _get_legal_T_57 = asSInt(_get_legal_T_56)
node _get_legal_T_58 = eq(_get_legal_T_57, asSInt(UInt<1>(0h0)))
node _get_legal_T_59 = xor(s2_req.addr, UInt<32>(0h80000000))
node _get_legal_T_60 = cvt(_get_legal_T_59)
node _get_legal_T_61 = and(_get_legal_T_60, asSInt(UInt<33>(0h90000000)))
node _get_legal_T_62 = asSInt(_get_legal_T_61)
node _get_legal_T_63 = eq(_get_legal_T_62, asSInt(UInt<1>(0h0)))
node _get_legal_T_64 = or(_get_legal_T_18, _get_legal_T_23)
node _get_legal_T_65 = or(_get_legal_T_64, _get_legal_T_28)
node _get_legal_T_66 = or(_get_legal_T_65, _get_legal_T_33)
node _get_legal_T_67 = or(_get_legal_T_66, _get_legal_T_38)
node _get_legal_T_68 = or(_get_legal_T_67, _get_legal_T_43)
node _get_legal_T_69 = or(_get_legal_T_68, _get_legal_T_48)
node _get_legal_T_70 = or(_get_legal_T_69, _get_legal_T_53)
node _get_legal_T_71 = or(_get_legal_T_70, _get_legal_T_58)
node _get_legal_T_72 = or(_get_legal_T_71, _get_legal_T_63)
node _get_legal_T_73 = and(_get_legal_T_13, _get_legal_T_72)
node _get_legal_T_74 = or(UInt<1>(0h0), _get_legal_T_9)
node get_legal = or(_get_legal_T_74, _get_legal_T_73)
wire get : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect get.opcode, UInt<3>(0h4)
connect get.param, UInt<1>(0h0)
connect get.size, s2_req.size
connect get.source, UInt<1>(0h0)
connect get.address, s2_req.addr
node _get_a_mask_sizeOH_T = or(s2_req.size, UInt<3>(0h0))
node get_a_mask_sizeOH_shiftAmount = bits(_get_a_mask_sizeOH_T, 1, 0)
node _get_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), get_a_mask_sizeOH_shiftAmount)
node _get_a_mask_sizeOH_T_2 = bits(_get_a_mask_sizeOH_T_1, 2, 0)
node get_a_mask_sizeOH = or(_get_a_mask_sizeOH_T_2, UInt<1>(0h1))
node get_a_mask_sub_sub_sub_0_1 = geq(s2_req.size, UInt<2>(0h3))
node get_a_mask_sub_sub_size = bits(get_a_mask_sizeOH, 2, 2)
node get_a_mask_sub_sub_bit = bits(s2_req.addr, 2, 2)
node get_a_mask_sub_sub_nbit = eq(get_a_mask_sub_sub_bit, UInt<1>(0h0))
node get_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), get_a_mask_sub_sub_nbit)
node _get_a_mask_sub_sub_acc_T = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_0_2)
node get_a_mask_sub_sub_0_1 = or(get_a_mask_sub_sub_sub_0_1, _get_a_mask_sub_sub_acc_T)
node get_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), get_a_mask_sub_sub_bit)
node _get_a_mask_sub_sub_acc_T_1 = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_1_2)
node get_a_mask_sub_sub_1_1 = or(get_a_mask_sub_sub_sub_0_1, _get_a_mask_sub_sub_acc_T_1)
node get_a_mask_sub_size = bits(get_a_mask_sizeOH, 1, 1)
node get_a_mask_sub_bit = bits(s2_req.addr, 1, 1)
node get_a_mask_sub_nbit = eq(get_a_mask_sub_bit, UInt<1>(0h0))
node get_a_mask_sub_0_2 = and(get_a_mask_sub_sub_0_2, get_a_mask_sub_nbit)
node _get_a_mask_sub_acc_T = and(get_a_mask_sub_size, get_a_mask_sub_0_2)
node get_a_mask_sub_0_1 = or(get_a_mask_sub_sub_0_1, _get_a_mask_sub_acc_T)
node get_a_mask_sub_1_2 = and(get_a_mask_sub_sub_0_2, get_a_mask_sub_bit)
node _get_a_mask_sub_acc_T_1 = and(get_a_mask_sub_size, get_a_mask_sub_1_2)
node get_a_mask_sub_1_1 = or(get_a_mask_sub_sub_0_1, _get_a_mask_sub_acc_T_1)
node get_a_mask_sub_2_2 = and(get_a_mask_sub_sub_1_2, get_a_mask_sub_nbit)
node _get_a_mask_sub_acc_T_2 = and(get_a_mask_sub_size, get_a_mask_sub_2_2)
node get_a_mask_sub_2_1 = or(get_a_mask_sub_sub_1_1, _get_a_mask_sub_acc_T_2)
node get_a_mask_sub_3_2 = and(get_a_mask_sub_sub_1_2, get_a_mask_sub_bit)
node _get_a_mask_sub_acc_T_3 = and(get_a_mask_sub_size, get_a_mask_sub_3_2)
node get_a_mask_sub_3_1 = or(get_a_mask_sub_sub_1_1, _get_a_mask_sub_acc_T_3)
node get_a_mask_size = bits(get_a_mask_sizeOH, 0, 0)
node get_a_mask_bit = bits(s2_req.addr, 0, 0)
node get_a_mask_nbit = eq(get_a_mask_bit, UInt<1>(0h0))
node get_a_mask_eq = and(get_a_mask_sub_0_2, get_a_mask_nbit)
node _get_a_mask_acc_T = and(get_a_mask_size, get_a_mask_eq)
node get_a_mask_acc = or(get_a_mask_sub_0_1, _get_a_mask_acc_T)
node get_a_mask_eq_1 = and(get_a_mask_sub_0_2, get_a_mask_bit)
node _get_a_mask_acc_T_1 = and(get_a_mask_size, get_a_mask_eq_1)
node get_a_mask_acc_1 = or(get_a_mask_sub_0_1, _get_a_mask_acc_T_1)
node get_a_mask_eq_2 = and(get_a_mask_sub_1_2, get_a_mask_nbit)
node _get_a_mask_acc_T_2 = and(get_a_mask_size, get_a_mask_eq_2)
node get_a_mask_acc_2 = or(get_a_mask_sub_1_1, _get_a_mask_acc_T_2)
node get_a_mask_eq_3 = and(get_a_mask_sub_1_2, get_a_mask_bit)
node _get_a_mask_acc_T_3 = and(get_a_mask_size, get_a_mask_eq_3)
node get_a_mask_acc_3 = or(get_a_mask_sub_1_1, _get_a_mask_acc_T_3)
node get_a_mask_eq_4 = and(get_a_mask_sub_2_2, get_a_mask_nbit)
node _get_a_mask_acc_T_4 = and(get_a_mask_size, get_a_mask_eq_4)
node get_a_mask_acc_4 = or(get_a_mask_sub_2_1, _get_a_mask_acc_T_4)
node get_a_mask_eq_5 = and(get_a_mask_sub_2_2, get_a_mask_bit)
node _get_a_mask_acc_T_5 = and(get_a_mask_size, get_a_mask_eq_5)
node get_a_mask_acc_5 = or(get_a_mask_sub_2_1, _get_a_mask_acc_T_5)
node get_a_mask_eq_6 = and(get_a_mask_sub_3_2, get_a_mask_nbit)
node _get_a_mask_acc_T_6 = and(get_a_mask_size, get_a_mask_eq_6)
node get_a_mask_acc_6 = or(get_a_mask_sub_3_1, _get_a_mask_acc_T_6)
node get_a_mask_eq_7 = and(get_a_mask_sub_3_2, get_a_mask_bit)
node _get_a_mask_acc_T_7 = and(get_a_mask_size, get_a_mask_eq_7)
node get_a_mask_acc_7 = or(get_a_mask_sub_3_1, _get_a_mask_acc_T_7)
node get_a_mask_lo_lo = cat(get_a_mask_acc_1, get_a_mask_acc)
node get_a_mask_lo_hi = cat(get_a_mask_acc_3, get_a_mask_acc_2)
node get_a_mask_lo = cat(get_a_mask_lo_hi, get_a_mask_lo_lo)
node get_a_mask_hi_lo = cat(get_a_mask_acc_5, get_a_mask_acc_4)
node get_a_mask_hi_hi = cat(get_a_mask_acc_7, get_a_mask_acc_6)
node get_a_mask_hi = cat(get_a_mask_hi_hi, get_a_mask_hi_lo)
node _get_a_mask_T = cat(get_a_mask_hi, get_a_mask_lo)
connect get.mask, _get_a_mask_T
invalidate get.data
connect get.corrupt, UInt<1>(0h0)
node _put_legal_T = leq(UInt<1>(0h0), s2_req.size)
node _put_legal_T_1 = leq(s2_req.size, UInt<4>(0hc))
node _put_legal_T_2 = and(_put_legal_T, _put_legal_T_1)
node _put_legal_T_3 = or(UInt<1>(0h0), _put_legal_T_2)
node _put_legal_T_4 = xor(s2_req.addr, UInt<14>(0h3000))
node _put_legal_T_5 = cvt(_put_legal_T_4)
node _put_legal_T_6 = and(_put_legal_T_5, asSInt(UInt<33>(0h9a313000)))
node _put_legal_T_7 = asSInt(_put_legal_T_6)
node _put_legal_T_8 = eq(_put_legal_T_7, asSInt(UInt<1>(0h0)))
node _put_legal_T_9 = and(_put_legal_T_3, _put_legal_T_8)
node _put_legal_T_10 = leq(UInt<1>(0h0), s2_req.size)
node _put_legal_T_11 = leq(s2_req.size, UInt<3>(0h6))
node _put_legal_T_12 = and(_put_legal_T_10, _put_legal_T_11)
node _put_legal_T_13 = or(UInt<1>(0h0), _put_legal_T_12)
node _put_legal_T_14 = xor(s2_req.addr, UInt<1>(0h0))
node _put_legal_T_15 = cvt(_put_legal_T_14)
node _put_legal_T_16 = and(_put_legal_T_15, asSInt(UInt<33>(0h9a312000)))
node _put_legal_T_17 = asSInt(_put_legal_T_16)
node _put_legal_T_18 = eq(_put_legal_T_17, asSInt(UInt<1>(0h0)))
node _put_legal_T_19 = xor(s2_req.addr, UInt<21>(0h100000))
node _put_legal_T_20 = cvt(_put_legal_T_19)
node _put_legal_T_21 = and(_put_legal_T_20, asSInt(UInt<33>(0h9a303000)))
node _put_legal_T_22 = asSInt(_put_legal_T_21)
node _put_legal_T_23 = eq(_put_legal_T_22, asSInt(UInt<1>(0h0)))
node _put_legal_T_24 = xor(s2_req.addr, UInt<22>(0h200000))
node _put_legal_T_25 = cvt(_put_legal_T_24)
node _put_legal_T_26 = and(_put_legal_T_25, asSInt(UInt<33>(0h9a313000)))
node _put_legal_T_27 = asSInt(_put_legal_T_26)
node _put_legal_T_28 = eq(_put_legal_T_27, asSInt(UInt<1>(0h0)))
node _put_legal_T_29 = xor(s2_req.addr, UInt<22>(0h300000))
node _put_legal_T_30 = cvt(_put_legal_T_29)
node _put_legal_T_31 = and(_put_legal_T_30, asSInt(UInt<33>(0h9a310000)))
node _put_legal_T_32 = asSInt(_put_legal_T_31)
node _put_legal_T_33 = eq(_put_legal_T_32, asSInt(UInt<1>(0h0)))
node _put_legal_T_34 = xor(s2_req.addr, UInt<26>(0h2000000))
node _put_legal_T_35 = cvt(_put_legal_T_34)
node _put_legal_T_36 = and(_put_legal_T_35, asSInt(UInt<33>(0h9a310000)))
node _put_legal_T_37 = asSInt(_put_legal_T_36)
node _put_legal_T_38 = eq(_put_legal_T_37, asSInt(UInt<1>(0h0)))
node _put_legal_T_39 = xor(s2_req.addr, UInt<26>(0h2010000))
node _put_legal_T_40 = cvt(_put_legal_T_39)
node _put_legal_T_41 = and(_put_legal_T_40, asSInt(UInt<33>(0h9a313000)))
node _put_legal_T_42 = asSInt(_put_legal_T_41)
node _put_legal_T_43 = eq(_put_legal_T_42, asSInt(UInt<1>(0h0)))
node _put_legal_T_44 = xor(s2_req.addr, UInt<28>(0h8000000))
node _put_legal_T_45 = cvt(_put_legal_T_44)
node _put_legal_T_46 = and(_put_legal_T_45, asSInt(UInt<33>(0h98000000)))
node _put_legal_T_47 = asSInt(_put_legal_T_46)
node _put_legal_T_48 = eq(_put_legal_T_47, asSInt(UInt<1>(0h0)))
node _put_legal_T_49 = xor(s2_req.addr, UInt<28>(0h8000000))
node _put_legal_T_50 = cvt(_put_legal_T_49)
node _put_legal_T_51 = and(_put_legal_T_50, asSInt(UInt<33>(0h9a310000)))
node _put_legal_T_52 = asSInt(_put_legal_T_51)
node _put_legal_T_53 = eq(_put_legal_T_52, asSInt(UInt<1>(0h0)))
node _put_legal_T_54 = xor(s2_req.addr, UInt<29>(0h10000000))
node _put_legal_T_55 = cvt(_put_legal_T_54)
node _put_legal_T_56 = and(_put_legal_T_55, asSInt(UInt<33>(0h9a313000)))
node _put_legal_T_57 = asSInt(_put_legal_T_56)
node _put_legal_T_58 = eq(_put_legal_T_57, asSInt(UInt<1>(0h0)))
node _put_legal_T_59 = xor(s2_req.addr, UInt<32>(0h80000000))
node _put_legal_T_60 = cvt(_put_legal_T_59)
node _put_legal_T_61 = and(_put_legal_T_60, asSInt(UInt<33>(0h90000000)))
node _put_legal_T_62 = asSInt(_put_legal_T_61)
node _put_legal_T_63 = eq(_put_legal_T_62, asSInt(UInt<1>(0h0)))
node _put_legal_T_64 = or(_put_legal_T_18, _put_legal_T_23)
node _put_legal_T_65 = or(_put_legal_T_64, _put_legal_T_28)
node _put_legal_T_66 = or(_put_legal_T_65, _put_legal_T_33)
node _put_legal_T_67 = or(_put_legal_T_66, _put_legal_T_38)
node _put_legal_T_68 = or(_put_legal_T_67, _put_legal_T_43)
node _put_legal_T_69 = or(_put_legal_T_68, _put_legal_T_48)
node _put_legal_T_70 = or(_put_legal_T_69, _put_legal_T_53)
node _put_legal_T_71 = or(_put_legal_T_70, _put_legal_T_58)
node _put_legal_T_72 = or(_put_legal_T_71, _put_legal_T_63)
node _put_legal_T_73 = and(_put_legal_T_13, _put_legal_T_72)
node _put_legal_T_74 = or(UInt<1>(0h0), UInt<1>(0h0))
node _put_legal_T_75 = xor(s2_req.addr, UInt<17>(0h10000))
node _put_legal_T_76 = cvt(_put_legal_T_75)
node _put_legal_T_77 = and(_put_legal_T_76, asSInt(UInt<33>(0h9a310000)))
node _put_legal_T_78 = asSInt(_put_legal_T_77)
node _put_legal_T_79 = eq(_put_legal_T_78, asSInt(UInt<1>(0h0)))
node _put_legal_T_80 = and(_put_legal_T_74, _put_legal_T_79)
node _put_legal_T_81 = or(UInt<1>(0h0), _put_legal_T_9)
node _put_legal_T_82 = or(_put_legal_T_81, _put_legal_T_73)
node put_legal = or(_put_legal_T_82, _put_legal_T_80)
wire put : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect put.opcode, UInt<1>(0h0)
connect put.param, UInt<1>(0h0)
connect put.size, s2_req.size
connect put.source, UInt<1>(0h0)
connect put.address, s2_req.addr
node _put_a_mask_sizeOH_T = or(s2_req.size, UInt<3>(0h0))
node put_a_mask_sizeOH_shiftAmount = bits(_put_a_mask_sizeOH_T, 1, 0)
node _put_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), put_a_mask_sizeOH_shiftAmount)
node _put_a_mask_sizeOH_T_2 = bits(_put_a_mask_sizeOH_T_1, 2, 0)
node put_a_mask_sizeOH = or(_put_a_mask_sizeOH_T_2, UInt<1>(0h1))
node put_a_mask_sub_sub_sub_0_1 = geq(s2_req.size, UInt<2>(0h3))
node put_a_mask_sub_sub_size = bits(put_a_mask_sizeOH, 2, 2)
node put_a_mask_sub_sub_bit = bits(s2_req.addr, 2, 2)
node put_a_mask_sub_sub_nbit = eq(put_a_mask_sub_sub_bit, UInt<1>(0h0))
node put_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), put_a_mask_sub_sub_nbit)
node _put_a_mask_sub_sub_acc_T = and(put_a_mask_sub_sub_size, put_a_mask_sub_sub_0_2)
node put_a_mask_sub_sub_0_1 = or(put_a_mask_sub_sub_sub_0_1, _put_a_mask_sub_sub_acc_T)
node put_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), put_a_mask_sub_sub_bit)
node _put_a_mask_sub_sub_acc_T_1 = and(put_a_mask_sub_sub_size, put_a_mask_sub_sub_1_2)
node put_a_mask_sub_sub_1_1 = or(put_a_mask_sub_sub_sub_0_1, _put_a_mask_sub_sub_acc_T_1)
node put_a_mask_sub_size = bits(put_a_mask_sizeOH, 1, 1)
node put_a_mask_sub_bit = bits(s2_req.addr, 1, 1)
node put_a_mask_sub_nbit = eq(put_a_mask_sub_bit, UInt<1>(0h0))
node put_a_mask_sub_0_2 = and(put_a_mask_sub_sub_0_2, put_a_mask_sub_nbit)
node _put_a_mask_sub_acc_T = and(put_a_mask_sub_size, put_a_mask_sub_0_2)
node put_a_mask_sub_0_1 = or(put_a_mask_sub_sub_0_1, _put_a_mask_sub_acc_T)
node put_a_mask_sub_1_2 = and(put_a_mask_sub_sub_0_2, put_a_mask_sub_bit)
node _put_a_mask_sub_acc_T_1 = and(put_a_mask_sub_size, put_a_mask_sub_1_2)
node put_a_mask_sub_1_1 = or(put_a_mask_sub_sub_0_1, _put_a_mask_sub_acc_T_1)
node put_a_mask_sub_2_2 = and(put_a_mask_sub_sub_1_2, put_a_mask_sub_nbit)
node _put_a_mask_sub_acc_T_2 = and(put_a_mask_sub_size, put_a_mask_sub_2_2)
node put_a_mask_sub_2_1 = or(put_a_mask_sub_sub_1_1, _put_a_mask_sub_acc_T_2)
node put_a_mask_sub_3_2 = and(put_a_mask_sub_sub_1_2, put_a_mask_sub_bit)
node _put_a_mask_sub_acc_T_3 = and(put_a_mask_sub_size, put_a_mask_sub_3_2)
node put_a_mask_sub_3_1 = or(put_a_mask_sub_sub_1_1, _put_a_mask_sub_acc_T_3)
node put_a_mask_size = bits(put_a_mask_sizeOH, 0, 0)
node put_a_mask_bit = bits(s2_req.addr, 0, 0)
node put_a_mask_nbit = eq(put_a_mask_bit, UInt<1>(0h0))
node put_a_mask_eq = and(put_a_mask_sub_0_2, put_a_mask_nbit)
node _put_a_mask_acc_T = and(put_a_mask_size, put_a_mask_eq)
node put_a_mask_acc = or(put_a_mask_sub_0_1, _put_a_mask_acc_T)
node put_a_mask_eq_1 = and(put_a_mask_sub_0_2, put_a_mask_bit)
node _put_a_mask_acc_T_1 = and(put_a_mask_size, put_a_mask_eq_1)
node put_a_mask_acc_1 = or(put_a_mask_sub_0_1, _put_a_mask_acc_T_1)
node put_a_mask_eq_2 = and(put_a_mask_sub_1_2, put_a_mask_nbit)
node _put_a_mask_acc_T_2 = and(put_a_mask_size, put_a_mask_eq_2)
node put_a_mask_acc_2 = or(put_a_mask_sub_1_1, _put_a_mask_acc_T_2)
node put_a_mask_eq_3 = and(put_a_mask_sub_1_2, put_a_mask_bit)
node _put_a_mask_acc_T_3 = and(put_a_mask_size, put_a_mask_eq_3)
node put_a_mask_acc_3 = or(put_a_mask_sub_1_1, _put_a_mask_acc_T_3)
node put_a_mask_eq_4 = and(put_a_mask_sub_2_2, put_a_mask_nbit)
node _put_a_mask_acc_T_4 = and(put_a_mask_size, put_a_mask_eq_4)
node put_a_mask_acc_4 = or(put_a_mask_sub_2_1, _put_a_mask_acc_T_4)
node put_a_mask_eq_5 = and(put_a_mask_sub_2_2, put_a_mask_bit)
node _put_a_mask_acc_T_5 = and(put_a_mask_size, put_a_mask_eq_5)
node put_a_mask_acc_5 = or(put_a_mask_sub_2_1, _put_a_mask_acc_T_5)
node put_a_mask_eq_6 = and(put_a_mask_sub_3_2, put_a_mask_nbit)
node _put_a_mask_acc_T_6 = and(put_a_mask_size, put_a_mask_eq_6)
node put_a_mask_acc_6 = or(put_a_mask_sub_3_1, _put_a_mask_acc_T_6)
node put_a_mask_eq_7 = and(put_a_mask_sub_3_2, put_a_mask_bit)
node _put_a_mask_acc_T_7 = and(put_a_mask_size, put_a_mask_eq_7)
node put_a_mask_acc_7 = or(put_a_mask_sub_3_1, _put_a_mask_acc_T_7)
node put_a_mask_lo_lo = cat(put_a_mask_acc_1, put_a_mask_acc)
node put_a_mask_lo_hi = cat(put_a_mask_acc_3, put_a_mask_acc_2)
node put_a_mask_lo = cat(put_a_mask_lo_hi, put_a_mask_lo_lo)
node put_a_mask_hi_lo = cat(put_a_mask_acc_5, put_a_mask_acc_4)
node put_a_mask_hi_hi = cat(put_a_mask_acc_7, put_a_mask_acc_6)
node put_a_mask_hi = cat(put_a_mask_hi_hi, put_a_mask_hi_lo)
node _put_a_mask_T = cat(put_a_mask_hi, put_a_mask_lo)
connect put.mask, _put_a_mask_T
connect put.data, pstore1_data
connect put.corrupt, UInt<1>(0h0)
node _putpartial_legal_T = leq(UInt<1>(0h0), s2_req.size)
node _putpartial_legal_T_1 = leq(s2_req.size, UInt<4>(0hc))
node _putpartial_legal_T_2 = and(_putpartial_legal_T, _putpartial_legal_T_1)
node _putpartial_legal_T_3 = or(UInt<1>(0h0), _putpartial_legal_T_2)
node _putpartial_legal_T_4 = xor(s2_req.addr, UInt<14>(0h3000))
node _putpartial_legal_T_5 = cvt(_putpartial_legal_T_4)
node _putpartial_legal_T_6 = and(_putpartial_legal_T_5, asSInt(UInt<33>(0h9a313000)))
node _putpartial_legal_T_7 = asSInt(_putpartial_legal_T_6)
node _putpartial_legal_T_8 = eq(_putpartial_legal_T_7, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_9 = and(_putpartial_legal_T_3, _putpartial_legal_T_8)
node _putpartial_legal_T_10 = leq(UInt<1>(0h0), s2_req.size)
node _putpartial_legal_T_11 = leq(s2_req.size, UInt<3>(0h6))
node _putpartial_legal_T_12 = and(_putpartial_legal_T_10, _putpartial_legal_T_11)
node _putpartial_legal_T_13 = or(UInt<1>(0h0), _putpartial_legal_T_12)
node _putpartial_legal_T_14 = xor(s2_req.addr, UInt<1>(0h0))
node _putpartial_legal_T_15 = cvt(_putpartial_legal_T_14)
node _putpartial_legal_T_16 = and(_putpartial_legal_T_15, asSInt(UInt<33>(0h9a312000)))
node _putpartial_legal_T_17 = asSInt(_putpartial_legal_T_16)
node _putpartial_legal_T_18 = eq(_putpartial_legal_T_17, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_19 = xor(s2_req.addr, UInt<21>(0h100000))
node _putpartial_legal_T_20 = cvt(_putpartial_legal_T_19)
node _putpartial_legal_T_21 = and(_putpartial_legal_T_20, asSInt(UInt<33>(0h9a303000)))
node _putpartial_legal_T_22 = asSInt(_putpartial_legal_T_21)
node _putpartial_legal_T_23 = eq(_putpartial_legal_T_22, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_24 = xor(s2_req.addr, UInt<22>(0h200000))
node _putpartial_legal_T_25 = cvt(_putpartial_legal_T_24)
node _putpartial_legal_T_26 = and(_putpartial_legal_T_25, asSInt(UInt<33>(0h9a313000)))
node _putpartial_legal_T_27 = asSInt(_putpartial_legal_T_26)
node _putpartial_legal_T_28 = eq(_putpartial_legal_T_27, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_29 = xor(s2_req.addr, UInt<22>(0h300000))
node _putpartial_legal_T_30 = cvt(_putpartial_legal_T_29)
node _putpartial_legal_T_31 = and(_putpartial_legal_T_30, asSInt(UInt<33>(0h9a310000)))
node _putpartial_legal_T_32 = asSInt(_putpartial_legal_T_31)
node _putpartial_legal_T_33 = eq(_putpartial_legal_T_32, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_34 = xor(s2_req.addr, UInt<26>(0h2000000))
node _putpartial_legal_T_35 = cvt(_putpartial_legal_T_34)
node _putpartial_legal_T_36 = and(_putpartial_legal_T_35, asSInt(UInt<33>(0h9a310000)))
node _putpartial_legal_T_37 = asSInt(_putpartial_legal_T_36)
node _putpartial_legal_T_38 = eq(_putpartial_legal_T_37, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_39 = xor(s2_req.addr, UInt<26>(0h2010000))
node _putpartial_legal_T_40 = cvt(_putpartial_legal_T_39)
node _putpartial_legal_T_41 = and(_putpartial_legal_T_40, asSInt(UInt<33>(0h9a313000)))
node _putpartial_legal_T_42 = asSInt(_putpartial_legal_T_41)
node _putpartial_legal_T_43 = eq(_putpartial_legal_T_42, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_44 = xor(s2_req.addr, UInt<28>(0h8000000))
node _putpartial_legal_T_45 = cvt(_putpartial_legal_T_44)
node _putpartial_legal_T_46 = and(_putpartial_legal_T_45, asSInt(UInt<33>(0h98000000)))
node _putpartial_legal_T_47 = asSInt(_putpartial_legal_T_46)
node _putpartial_legal_T_48 = eq(_putpartial_legal_T_47, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_49 = xor(s2_req.addr, UInt<28>(0h8000000))
node _putpartial_legal_T_50 = cvt(_putpartial_legal_T_49)
node _putpartial_legal_T_51 = and(_putpartial_legal_T_50, asSInt(UInt<33>(0h9a310000)))
node _putpartial_legal_T_52 = asSInt(_putpartial_legal_T_51)
node _putpartial_legal_T_53 = eq(_putpartial_legal_T_52, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_54 = xor(s2_req.addr, UInt<29>(0h10000000))
node _putpartial_legal_T_55 = cvt(_putpartial_legal_T_54)
node _putpartial_legal_T_56 = and(_putpartial_legal_T_55, asSInt(UInt<33>(0h9a313000)))
node _putpartial_legal_T_57 = asSInt(_putpartial_legal_T_56)
node _putpartial_legal_T_58 = eq(_putpartial_legal_T_57, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_59 = xor(s2_req.addr, UInt<32>(0h80000000))
node _putpartial_legal_T_60 = cvt(_putpartial_legal_T_59)
node _putpartial_legal_T_61 = and(_putpartial_legal_T_60, asSInt(UInt<33>(0h90000000)))
node _putpartial_legal_T_62 = asSInt(_putpartial_legal_T_61)
node _putpartial_legal_T_63 = eq(_putpartial_legal_T_62, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_64 = or(_putpartial_legal_T_18, _putpartial_legal_T_23)
node _putpartial_legal_T_65 = or(_putpartial_legal_T_64, _putpartial_legal_T_28)
node _putpartial_legal_T_66 = or(_putpartial_legal_T_65, _putpartial_legal_T_33)
node _putpartial_legal_T_67 = or(_putpartial_legal_T_66, _putpartial_legal_T_38)
node _putpartial_legal_T_68 = or(_putpartial_legal_T_67, _putpartial_legal_T_43)
node _putpartial_legal_T_69 = or(_putpartial_legal_T_68, _putpartial_legal_T_48)
node _putpartial_legal_T_70 = or(_putpartial_legal_T_69, _putpartial_legal_T_53)
node _putpartial_legal_T_71 = or(_putpartial_legal_T_70, _putpartial_legal_T_58)
node _putpartial_legal_T_72 = or(_putpartial_legal_T_71, _putpartial_legal_T_63)
node _putpartial_legal_T_73 = and(_putpartial_legal_T_13, _putpartial_legal_T_72)
node _putpartial_legal_T_74 = or(UInt<1>(0h0), UInt<1>(0h0))
node _putpartial_legal_T_75 = xor(s2_req.addr, UInt<17>(0h10000))
node _putpartial_legal_T_76 = cvt(_putpartial_legal_T_75)
node _putpartial_legal_T_77 = and(_putpartial_legal_T_76, asSInt(UInt<33>(0h9a310000)))
node _putpartial_legal_T_78 = asSInt(_putpartial_legal_T_77)
node _putpartial_legal_T_79 = eq(_putpartial_legal_T_78, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_80 = and(_putpartial_legal_T_74, _putpartial_legal_T_79)
node _putpartial_legal_T_81 = or(UInt<1>(0h0), _putpartial_legal_T_9)
node _putpartial_legal_T_82 = or(_putpartial_legal_T_81, _putpartial_legal_T_73)
node putpartial_legal = or(_putpartial_legal_T_82, _putpartial_legal_T_80)
wire putpartial : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect putpartial.opcode, UInt<1>(0h1)
connect putpartial.param, UInt<1>(0h0)
connect putpartial.size, s2_req.size
connect putpartial.source, UInt<1>(0h0)
connect putpartial.address, s2_req.addr
connect putpartial.mask, a_mask
connect putpartial.data, pstore1_data
connect putpartial.corrupt, UInt<1>(0h0)
wire _atomics_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect _atomics_WIRE.corrupt, UInt<1>(0h0)
connect _atomics_WIRE.data, UInt<64>(0h0)
connect _atomics_WIRE.mask, UInt<8>(0h0)
connect _atomics_WIRE.address, UInt<32>(0h0)
connect _atomics_WIRE.source, UInt<1>(0h0)
connect _atomics_WIRE.size, UInt<4>(0h0)
connect _atomics_WIRE.param, UInt<3>(0h0)
connect _atomics_WIRE.opcode, UInt<3>(0h0)
wire _atomics_WIRE_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect _atomics_WIRE_1, _atomics_WIRE
node _atomics_legal_T = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_1 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_2 = and(_atomics_legal_T, _atomics_legal_T_1)
node _atomics_legal_T_3 = or(UInt<1>(0h0), _atomics_legal_T_2)
node _atomics_legal_T_4 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_5 = cvt(_atomics_legal_T_4)
node _atomics_legal_T_6 = and(_atomics_legal_T_5, asSInt(UInt<33>(0h8a010000)))
node _atomics_legal_T_7 = asSInt(_atomics_legal_T_6)
node _atomics_legal_T_8 = eq(_atomics_legal_T_7, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_9 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_10 = cvt(_atomics_legal_T_9)
node _atomics_legal_T_11 = and(_atomics_legal_T_10, asSInt(UInt<33>(0h8a101000)))
node _atomics_legal_T_12 = asSInt(_atomics_legal_T_11)
node _atomics_legal_T_13 = eq(_atomics_legal_T_12, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_14 = xor(s2_req.addr, UInt<26>(0h2000000))
node _atomics_legal_T_15 = cvt(_atomics_legal_T_14)
node _atomics_legal_T_16 = and(_atomics_legal_T_15, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_17 = asSInt(_atomics_legal_T_16)
node _atomics_legal_T_18 = eq(_atomics_legal_T_17, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_19 = xor(s2_req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_20 = cvt(_atomics_legal_T_19)
node _atomics_legal_T_21 = and(_atomics_legal_T_20, asSInt(UInt<33>(0h8a111000)))
node _atomics_legal_T_22 = asSInt(_atomics_legal_T_21)
node _atomics_legal_T_23 = eq(_atomics_legal_T_22, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_24 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_25 = cvt(_atomics_legal_T_24)
node _atomics_legal_T_26 = and(_atomics_legal_T_25, asSInt(UInt<33>(0h88000000)))
node _atomics_legal_T_27 = asSInt(_atomics_legal_T_26)
node _atomics_legal_T_28 = eq(_atomics_legal_T_27, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_29 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_30 = cvt(_atomics_legal_T_29)
node _atomics_legal_T_31 = and(_atomics_legal_T_30, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_32 = asSInt(_atomics_legal_T_31)
node _atomics_legal_T_33 = eq(_atomics_legal_T_32, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_34 = xor(s2_req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_35 = cvt(_atomics_legal_T_34)
node _atomics_legal_T_36 = and(_atomics_legal_T_35, asSInt(UInt<33>(0h80000000)))
node _atomics_legal_T_37 = asSInt(_atomics_legal_T_36)
node _atomics_legal_T_38 = eq(_atomics_legal_T_37, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_39 = or(_atomics_legal_T_8, _atomics_legal_T_13)
node _atomics_legal_T_40 = or(_atomics_legal_T_39, _atomics_legal_T_18)
node _atomics_legal_T_41 = or(_atomics_legal_T_40, _atomics_legal_T_23)
node _atomics_legal_T_42 = or(_atomics_legal_T_41, _atomics_legal_T_28)
node _atomics_legal_T_43 = or(_atomics_legal_T_42, _atomics_legal_T_33)
node _atomics_legal_T_44 = or(_atomics_legal_T_43, _atomics_legal_T_38)
node _atomics_legal_T_45 = and(_atomics_legal_T_3, _atomics_legal_T_44)
node _atomics_legal_T_46 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_47 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_48 = cvt(_atomics_legal_T_47)
node _atomics_legal_T_49 = and(_atomics_legal_T_48, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_50 = asSInt(_atomics_legal_T_49)
node _atomics_legal_T_51 = eq(_atomics_legal_T_50, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_52 = and(_atomics_legal_T_46, _atomics_legal_T_51)
node _atomics_legal_T_53 = or(UInt<1>(0h0), _atomics_legal_T_45)
node atomics_legal = or(_atomics_legal_T_53, _atomics_legal_T_52)
wire atomics_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a.opcode, UInt<2>(0h3)
connect atomics_a.param, UInt<3>(0h3)
connect atomics_a.size, s2_req.size
connect atomics_a.source, UInt<1>(0h0)
connect atomics_a.address, s2_req.addr
node _atomics_a_mask_sizeOH_T = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount = bits(_atomics_a_mask_sizeOH_T, 1, 0)
node _atomics_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount)
node _atomics_a_mask_sizeOH_T_2 = bits(_atomics_a_mask_sizeOH_T_1, 2, 0)
node atomics_a_mask_sizeOH = or(_atomics_a_mask_sizeOH_T_2, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size = bits(atomics_a_mask_sizeOH, 2, 2)
node atomics_a_mask_sub_sub_bit = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit = eq(atomics_a_mask_sub_sub_bit, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit)
node _atomics_a_mask_sub_sub_acc_T = and(atomics_a_mask_sub_sub_size, atomics_a_mask_sub_sub_0_2)
node atomics_a_mask_sub_sub_0_1 = or(atomics_a_mask_sub_sub_sub_0_1, _atomics_a_mask_sub_sub_acc_T)
node atomics_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit)
node _atomics_a_mask_sub_sub_acc_T_1 = and(atomics_a_mask_sub_sub_size, atomics_a_mask_sub_sub_1_2)
node atomics_a_mask_sub_sub_1_1 = or(atomics_a_mask_sub_sub_sub_0_1, _atomics_a_mask_sub_sub_acc_T_1)
node atomics_a_mask_sub_size = bits(atomics_a_mask_sizeOH, 1, 1)
node atomics_a_mask_sub_bit = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit = eq(atomics_a_mask_sub_bit, UInt<1>(0h0))
node atomics_a_mask_sub_0_2 = and(atomics_a_mask_sub_sub_0_2, atomics_a_mask_sub_nbit)
node _atomics_a_mask_sub_acc_T = and(atomics_a_mask_sub_size, atomics_a_mask_sub_0_2)
node atomics_a_mask_sub_0_1 = or(atomics_a_mask_sub_sub_0_1, _atomics_a_mask_sub_acc_T)
node atomics_a_mask_sub_1_2 = and(atomics_a_mask_sub_sub_0_2, atomics_a_mask_sub_bit)
node _atomics_a_mask_sub_acc_T_1 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_1_2)
node atomics_a_mask_sub_1_1 = or(atomics_a_mask_sub_sub_0_1, _atomics_a_mask_sub_acc_T_1)
node atomics_a_mask_sub_2_2 = and(atomics_a_mask_sub_sub_1_2, atomics_a_mask_sub_nbit)
node _atomics_a_mask_sub_acc_T_2 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_2_2)
node atomics_a_mask_sub_2_1 = or(atomics_a_mask_sub_sub_1_1, _atomics_a_mask_sub_acc_T_2)
node atomics_a_mask_sub_3_2 = and(atomics_a_mask_sub_sub_1_2, atomics_a_mask_sub_bit)
node _atomics_a_mask_sub_acc_T_3 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_3_2)
node atomics_a_mask_sub_3_1 = or(atomics_a_mask_sub_sub_1_1, _atomics_a_mask_sub_acc_T_3)
node atomics_a_mask_size = bits(atomics_a_mask_sizeOH, 0, 0)
node atomics_a_mask_bit = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit = eq(atomics_a_mask_bit, UInt<1>(0h0))
node atomics_a_mask_eq = and(atomics_a_mask_sub_0_2, atomics_a_mask_nbit)
node _atomics_a_mask_acc_T = and(atomics_a_mask_size, atomics_a_mask_eq)
node atomics_a_mask_acc = or(atomics_a_mask_sub_0_1, _atomics_a_mask_acc_T)
node atomics_a_mask_eq_1 = and(atomics_a_mask_sub_0_2, atomics_a_mask_bit)
node _atomics_a_mask_acc_T_1 = and(atomics_a_mask_size, atomics_a_mask_eq_1)
node atomics_a_mask_acc_1 = or(atomics_a_mask_sub_0_1, _atomics_a_mask_acc_T_1)
node atomics_a_mask_eq_2 = and(atomics_a_mask_sub_1_2, atomics_a_mask_nbit)
node _atomics_a_mask_acc_T_2 = and(atomics_a_mask_size, atomics_a_mask_eq_2)
node atomics_a_mask_acc_2 = or(atomics_a_mask_sub_1_1, _atomics_a_mask_acc_T_2)
node atomics_a_mask_eq_3 = and(atomics_a_mask_sub_1_2, atomics_a_mask_bit)
node _atomics_a_mask_acc_T_3 = and(atomics_a_mask_size, atomics_a_mask_eq_3)
node atomics_a_mask_acc_3 = or(atomics_a_mask_sub_1_1, _atomics_a_mask_acc_T_3)
node atomics_a_mask_eq_4 = and(atomics_a_mask_sub_2_2, atomics_a_mask_nbit)
node _atomics_a_mask_acc_T_4 = and(atomics_a_mask_size, atomics_a_mask_eq_4)
node atomics_a_mask_acc_4 = or(atomics_a_mask_sub_2_1, _atomics_a_mask_acc_T_4)
node atomics_a_mask_eq_5 = and(atomics_a_mask_sub_2_2, atomics_a_mask_bit)
node _atomics_a_mask_acc_T_5 = and(atomics_a_mask_size, atomics_a_mask_eq_5)
node atomics_a_mask_acc_5 = or(atomics_a_mask_sub_2_1, _atomics_a_mask_acc_T_5)
node atomics_a_mask_eq_6 = and(atomics_a_mask_sub_3_2, atomics_a_mask_nbit)
node _atomics_a_mask_acc_T_6 = and(atomics_a_mask_size, atomics_a_mask_eq_6)
node atomics_a_mask_acc_6 = or(atomics_a_mask_sub_3_1, _atomics_a_mask_acc_T_6)
node atomics_a_mask_eq_7 = and(atomics_a_mask_sub_3_2, atomics_a_mask_bit)
node _atomics_a_mask_acc_T_7 = and(atomics_a_mask_size, atomics_a_mask_eq_7)
node atomics_a_mask_acc_7 = or(atomics_a_mask_sub_3_1, _atomics_a_mask_acc_T_7)
node atomics_a_mask_lo_lo = cat(atomics_a_mask_acc_1, atomics_a_mask_acc)
node atomics_a_mask_lo_hi = cat(atomics_a_mask_acc_3, atomics_a_mask_acc_2)
node atomics_a_mask_lo = cat(atomics_a_mask_lo_hi, atomics_a_mask_lo_lo)
node atomics_a_mask_hi_lo = cat(atomics_a_mask_acc_5, atomics_a_mask_acc_4)
node atomics_a_mask_hi_hi = cat(atomics_a_mask_acc_7, atomics_a_mask_acc_6)
node atomics_a_mask_hi = cat(atomics_a_mask_hi_hi, atomics_a_mask_hi_lo)
node _atomics_a_mask_T = cat(atomics_a_mask_hi, atomics_a_mask_lo)
connect atomics_a.mask, _atomics_a_mask_T
connect atomics_a.data, pstore1_data
connect atomics_a.corrupt, UInt<1>(0h0)
node _atomics_legal_T_54 = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_55 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_56 = and(_atomics_legal_T_54, _atomics_legal_T_55)
node _atomics_legal_T_57 = or(UInt<1>(0h0), _atomics_legal_T_56)
node _atomics_legal_T_58 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_59 = cvt(_atomics_legal_T_58)
node _atomics_legal_T_60 = and(_atomics_legal_T_59, asSInt(UInt<33>(0h8a010000)))
node _atomics_legal_T_61 = asSInt(_atomics_legal_T_60)
node _atomics_legal_T_62 = eq(_atomics_legal_T_61, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_63 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_64 = cvt(_atomics_legal_T_63)
node _atomics_legal_T_65 = and(_atomics_legal_T_64, asSInt(UInt<33>(0h8a101000)))
node _atomics_legal_T_66 = asSInt(_atomics_legal_T_65)
node _atomics_legal_T_67 = eq(_atomics_legal_T_66, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_68 = xor(s2_req.addr, UInt<26>(0h2000000))
node _atomics_legal_T_69 = cvt(_atomics_legal_T_68)
node _atomics_legal_T_70 = and(_atomics_legal_T_69, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_71 = asSInt(_atomics_legal_T_70)
node _atomics_legal_T_72 = eq(_atomics_legal_T_71, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_73 = xor(s2_req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_74 = cvt(_atomics_legal_T_73)
node _atomics_legal_T_75 = and(_atomics_legal_T_74, asSInt(UInt<33>(0h8a111000)))
node _atomics_legal_T_76 = asSInt(_atomics_legal_T_75)
node _atomics_legal_T_77 = eq(_atomics_legal_T_76, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_78 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_79 = cvt(_atomics_legal_T_78)
node _atomics_legal_T_80 = and(_atomics_legal_T_79, asSInt(UInt<33>(0h88000000)))
node _atomics_legal_T_81 = asSInt(_atomics_legal_T_80)
node _atomics_legal_T_82 = eq(_atomics_legal_T_81, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_83 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_84 = cvt(_atomics_legal_T_83)
node _atomics_legal_T_85 = and(_atomics_legal_T_84, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_86 = asSInt(_atomics_legal_T_85)
node _atomics_legal_T_87 = eq(_atomics_legal_T_86, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_88 = xor(s2_req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_89 = cvt(_atomics_legal_T_88)
node _atomics_legal_T_90 = and(_atomics_legal_T_89, asSInt(UInt<33>(0h80000000)))
node _atomics_legal_T_91 = asSInt(_atomics_legal_T_90)
node _atomics_legal_T_92 = eq(_atomics_legal_T_91, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_93 = or(_atomics_legal_T_62, _atomics_legal_T_67)
node _atomics_legal_T_94 = or(_atomics_legal_T_93, _atomics_legal_T_72)
node _atomics_legal_T_95 = or(_atomics_legal_T_94, _atomics_legal_T_77)
node _atomics_legal_T_96 = or(_atomics_legal_T_95, _atomics_legal_T_82)
node _atomics_legal_T_97 = or(_atomics_legal_T_96, _atomics_legal_T_87)
node _atomics_legal_T_98 = or(_atomics_legal_T_97, _atomics_legal_T_92)
node _atomics_legal_T_99 = and(_atomics_legal_T_57, _atomics_legal_T_98)
node _atomics_legal_T_100 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_101 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_102 = cvt(_atomics_legal_T_101)
node _atomics_legal_T_103 = and(_atomics_legal_T_102, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_104 = asSInt(_atomics_legal_T_103)
node _atomics_legal_T_105 = eq(_atomics_legal_T_104, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_106 = and(_atomics_legal_T_100, _atomics_legal_T_105)
node _atomics_legal_T_107 = or(UInt<1>(0h0), _atomics_legal_T_99)
node atomics_legal_1 = or(_atomics_legal_T_107, _atomics_legal_T_106)
wire atomics_a_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_1.opcode, UInt<2>(0h3)
connect atomics_a_1.param, UInt<3>(0h0)
connect atomics_a_1.size, s2_req.size
connect atomics_a_1.source, UInt<1>(0h0)
connect atomics_a_1.address, s2_req.addr
node _atomics_a_mask_sizeOH_T_3 = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_1 = bits(_atomics_a_mask_sizeOH_T_3, 1, 0)
node _atomics_a_mask_sizeOH_T_4 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_1)
node _atomics_a_mask_sizeOH_T_5 = bits(_atomics_a_mask_sizeOH_T_4, 2, 0)
node atomics_a_mask_sizeOH_1 = or(_atomics_a_mask_sizeOH_T_5, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_1 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_1 = bits(atomics_a_mask_sizeOH_1, 2, 2)
node atomics_a_mask_sub_sub_bit_1 = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_1 = eq(atomics_a_mask_sub_sub_bit_1, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_1 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_1)
node _atomics_a_mask_sub_sub_acc_T_2 = and(atomics_a_mask_sub_sub_size_1, atomics_a_mask_sub_sub_0_2_1)
node atomics_a_mask_sub_sub_0_1_1 = or(atomics_a_mask_sub_sub_sub_0_1_1, _atomics_a_mask_sub_sub_acc_T_2)
node atomics_a_mask_sub_sub_1_2_1 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_1)
node _atomics_a_mask_sub_sub_acc_T_3 = and(atomics_a_mask_sub_sub_size_1, atomics_a_mask_sub_sub_1_2_1)
node atomics_a_mask_sub_sub_1_1_1 = or(atomics_a_mask_sub_sub_sub_0_1_1, _atomics_a_mask_sub_sub_acc_T_3)
node atomics_a_mask_sub_size_1 = bits(atomics_a_mask_sizeOH_1, 1, 1)
node atomics_a_mask_sub_bit_1 = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit_1 = eq(atomics_a_mask_sub_bit_1, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_1 = and(atomics_a_mask_sub_sub_0_2_1, atomics_a_mask_sub_nbit_1)
node _atomics_a_mask_sub_acc_T_4 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_0_2_1)
node atomics_a_mask_sub_0_1_1 = or(atomics_a_mask_sub_sub_0_1_1, _atomics_a_mask_sub_acc_T_4)
node atomics_a_mask_sub_1_2_1 = and(atomics_a_mask_sub_sub_0_2_1, atomics_a_mask_sub_bit_1)
node _atomics_a_mask_sub_acc_T_5 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_1_2_1)
node atomics_a_mask_sub_1_1_1 = or(atomics_a_mask_sub_sub_0_1_1, _atomics_a_mask_sub_acc_T_5)
node atomics_a_mask_sub_2_2_1 = and(atomics_a_mask_sub_sub_1_2_1, atomics_a_mask_sub_nbit_1)
node _atomics_a_mask_sub_acc_T_6 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_2_2_1)
node atomics_a_mask_sub_2_1_1 = or(atomics_a_mask_sub_sub_1_1_1, _atomics_a_mask_sub_acc_T_6)
node atomics_a_mask_sub_3_2_1 = and(atomics_a_mask_sub_sub_1_2_1, atomics_a_mask_sub_bit_1)
node _atomics_a_mask_sub_acc_T_7 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_3_2_1)
node atomics_a_mask_sub_3_1_1 = or(atomics_a_mask_sub_sub_1_1_1, _atomics_a_mask_sub_acc_T_7)
node atomics_a_mask_size_1 = bits(atomics_a_mask_sizeOH_1, 0, 0)
node atomics_a_mask_bit_1 = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit_1 = eq(atomics_a_mask_bit_1, UInt<1>(0h0))
node atomics_a_mask_eq_8 = and(atomics_a_mask_sub_0_2_1, atomics_a_mask_nbit_1)
node _atomics_a_mask_acc_T_8 = and(atomics_a_mask_size_1, atomics_a_mask_eq_8)
node atomics_a_mask_acc_8 = or(atomics_a_mask_sub_0_1_1, _atomics_a_mask_acc_T_8)
node atomics_a_mask_eq_9 = and(atomics_a_mask_sub_0_2_1, atomics_a_mask_bit_1)
node _atomics_a_mask_acc_T_9 = and(atomics_a_mask_size_1, atomics_a_mask_eq_9)
node atomics_a_mask_acc_9 = or(atomics_a_mask_sub_0_1_1, _atomics_a_mask_acc_T_9)
node atomics_a_mask_eq_10 = and(atomics_a_mask_sub_1_2_1, atomics_a_mask_nbit_1)
node _atomics_a_mask_acc_T_10 = and(atomics_a_mask_size_1, atomics_a_mask_eq_10)
node atomics_a_mask_acc_10 = or(atomics_a_mask_sub_1_1_1, _atomics_a_mask_acc_T_10)
node atomics_a_mask_eq_11 = and(atomics_a_mask_sub_1_2_1, atomics_a_mask_bit_1)
node _atomics_a_mask_acc_T_11 = and(atomics_a_mask_size_1, atomics_a_mask_eq_11)
node atomics_a_mask_acc_11 = or(atomics_a_mask_sub_1_1_1, _atomics_a_mask_acc_T_11)
node atomics_a_mask_eq_12 = and(atomics_a_mask_sub_2_2_1, atomics_a_mask_nbit_1)
node _atomics_a_mask_acc_T_12 = and(atomics_a_mask_size_1, atomics_a_mask_eq_12)
node atomics_a_mask_acc_12 = or(atomics_a_mask_sub_2_1_1, _atomics_a_mask_acc_T_12)
node atomics_a_mask_eq_13 = and(atomics_a_mask_sub_2_2_1, atomics_a_mask_bit_1)
node _atomics_a_mask_acc_T_13 = and(atomics_a_mask_size_1, atomics_a_mask_eq_13)
node atomics_a_mask_acc_13 = or(atomics_a_mask_sub_2_1_1, _atomics_a_mask_acc_T_13)
node atomics_a_mask_eq_14 = and(atomics_a_mask_sub_3_2_1, atomics_a_mask_nbit_1)
node _atomics_a_mask_acc_T_14 = and(atomics_a_mask_size_1, atomics_a_mask_eq_14)
node atomics_a_mask_acc_14 = or(atomics_a_mask_sub_3_1_1, _atomics_a_mask_acc_T_14)
node atomics_a_mask_eq_15 = and(atomics_a_mask_sub_3_2_1, atomics_a_mask_bit_1)
node _atomics_a_mask_acc_T_15 = and(atomics_a_mask_size_1, atomics_a_mask_eq_15)
node atomics_a_mask_acc_15 = or(atomics_a_mask_sub_3_1_1, _atomics_a_mask_acc_T_15)
node atomics_a_mask_lo_lo_1 = cat(atomics_a_mask_acc_9, atomics_a_mask_acc_8)
node atomics_a_mask_lo_hi_1 = cat(atomics_a_mask_acc_11, atomics_a_mask_acc_10)
node atomics_a_mask_lo_1 = cat(atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1)
node atomics_a_mask_hi_lo_1 = cat(atomics_a_mask_acc_13, atomics_a_mask_acc_12)
node atomics_a_mask_hi_hi_1 = cat(atomics_a_mask_acc_15, atomics_a_mask_acc_14)
node atomics_a_mask_hi_1 = cat(atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1)
node _atomics_a_mask_T_1 = cat(atomics_a_mask_hi_1, atomics_a_mask_lo_1)
connect atomics_a_1.mask, _atomics_a_mask_T_1
connect atomics_a_1.data, pstore1_data
connect atomics_a_1.corrupt, UInt<1>(0h0)
node _atomics_legal_T_108 = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_109 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_110 = and(_atomics_legal_T_108, _atomics_legal_T_109)
node _atomics_legal_T_111 = or(UInt<1>(0h0), _atomics_legal_T_110)
node _atomics_legal_T_112 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_113 = cvt(_atomics_legal_T_112)
node _atomics_legal_T_114 = and(_atomics_legal_T_113, asSInt(UInt<33>(0h8a010000)))
node _atomics_legal_T_115 = asSInt(_atomics_legal_T_114)
node _atomics_legal_T_116 = eq(_atomics_legal_T_115, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_117 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_118 = cvt(_atomics_legal_T_117)
node _atomics_legal_T_119 = and(_atomics_legal_T_118, asSInt(UInt<33>(0h8a101000)))
node _atomics_legal_T_120 = asSInt(_atomics_legal_T_119)
node _atomics_legal_T_121 = eq(_atomics_legal_T_120, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_122 = xor(s2_req.addr, UInt<26>(0h2000000))
node _atomics_legal_T_123 = cvt(_atomics_legal_T_122)
node _atomics_legal_T_124 = and(_atomics_legal_T_123, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_125 = asSInt(_atomics_legal_T_124)
node _atomics_legal_T_126 = eq(_atomics_legal_T_125, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_127 = xor(s2_req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_128 = cvt(_atomics_legal_T_127)
node _atomics_legal_T_129 = and(_atomics_legal_T_128, asSInt(UInt<33>(0h8a111000)))
node _atomics_legal_T_130 = asSInt(_atomics_legal_T_129)
node _atomics_legal_T_131 = eq(_atomics_legal_T_130, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_132 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_133 = cvt(_atomics_legal_T_132)
node _atomics_legal_T_134 = and(_atomics_legal_T_133, asSInt(UInt<33>(0h88000000)))
node _atomics_legal_T_135 = asSInt(_atomics_legal_T_134)
node _atomics_legal_T_136 = eq(_atomics_legal_T_135, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_137 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_138 = cvt(_atomics_legal_T_137)
node _atomics_legal_T_139 = and(_atomics_legal_T_138, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_140 = asSInt(_atomics_legal_T_139)
node _atomics_legal_T_141 = eq(_atomics_legal_T_140, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_142 = xor(s2_req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_143 = cvt(_atomics_legal_T_142)
node _atomics_legal_T_144 = and(_atomics_legal_T_143, asSInt(UInt<33>(0h80000000)))
node _atomics_legal_T_145 = asSInt(_atomics_legal_T_144)
node _atomics_legal_T_146 = eq(_atomics_legal_T_145, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_147 = or(_atomics_legal_T_116, _atomics_legal_T_121)
node _atomics_legal_T_148 = or(_atomics_legal_T_147, _atomics_legal_T_126)
node _atomics_legal_T_149 = or(_atomics_legal_T_148, _atomics_legal_T_131)
node _atomics_legal_T_150 = or(_atomics_legal_T_149, _atomics_legal_T_136)
node _atomics_legal_T_151 = or(_atomics_legal_T_150, _atomics_legal_T_141)
node _atomics_legal_T_152 = or(_atomics_legal_T_151, _atomics_legal_T_146)
node _atomics_legal_T_153 = and(_atomics_legal_T_111, _atomics_legal_T_152)
node _atomics_legal_T_154 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_155 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_156 = cvt(_atomics_legal_T_155)
node _atomics_legal_T_157 = and(_atomics_legal_T_156, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_158 = asSInt(_atomics_legal_T_157)
node _atomics_legal_T_159 = eq(_atomics_legal_T_158, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_160 = and(_atomics_legal_T_154, _atomics_legal_T_159)
node _atomics_legal_T_161 = or(UInt<1>(0h0), _atomics_legal_T_153)
node atomics_legal_2 = or(_atomics_legal_T_161, _atomics_legal_T_160)
wire atomics_a_2 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_2.opcode, UInt<2>(0h3)
connect atomics_a_2.param, UInt<3>(0h1)
connect atomics_a_2.size, s2_req.size
connect atomics_a_2.source, UInt<1>(0h0)
connect atomics_a_2.address, s2_req.addr
node _atomics_a_mask_sizeOH_T_6 = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_2 = bits(_atomics_a_mask_sizeOH_T_6, 1, 0)
node _atomics_a_mask_sizeOH_T_7 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_2)
node _atomics_a_mask_sizeOH_T_8 = bits(_atomics_a_mask_sizeOH_T_7, 2, 0)
node atomics_a_mask_sizeOH_2 = or(_atomics_a_mask_sizeOH_T_8, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_2 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_2 = bits(atomics_a_mask_sizeOH_2, 2, 2)
node atomics_a_mask_sub_sub_bit_2 = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_2 = eq(atomics_a_mask_sub_sub_bit_2, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_2)
node _atomics_a_mask_sub_sub_acc_T_4 = and(atomics_a_mask_sub_sub_size_2, atomics_a_mask_sub_sub_0_2_2)
node atomics_a_mask_sub_sub_0_1_2 = or(atomics_a_mask_sub_sub_sub_0_1_2, _atomics_a_mask_sub_sub_acc_T_4)
node atomics_a_mask_sub_sub_1_2_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_2)
node _atomics_a_mask_sub_sub_acc_T_5 = and(atomics_a_mask_sub_sub_size_2, atomics_a_mask_sub_sub_1_2_2)
node atomics_a_mask_sub_sub_1_1_2 = or(atomics_a_mask_sub_sub_sub_0_1_2, _atomics_a_mask_sub_sub_acc_T_5)
node atomics_a_mask_sub_size_2 = bits(atomics_a_mask_sizeOH_2, 1, 1)
node atomics_a_mask_sub_bit_2 = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit_2 = eq(atomics_a_mask_sub_bit_2, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_2 = and(atomics_a_mask_sub_sub_0_2_2, atomics_a_mask_sub_nbit_2)
node _atomics_a_mask_sub_acc_T_8 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_0_2_2)
node atomics_a_mask_sub_0_1_2 = or(atomics_a_mask_sub_sub_0_1_2, _atomics_a_mask_sub_acc_T_8)
node atomics_a_mask_sub_1_2_2 = and(atomics_a_mask_sub_sub_0_2_2, atomics_a_mask_sub_bit_2)
node _atomics_a_mask_sub_acc_T_9 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_1_2_2)
node atomics_a_mask_sub_1_1_2 = or(atomics_a_mask_sub_sub_0_1_2, _atomics_a_mask_sub_acc_T_9)
node atomics_a_mask_sub_2_2_2 = and(atomics_a_mask_sub_sub_1_2_2, atomics_a_mask_sub_nbit_2)
node _atomics_a_mask_sub_acc_T_10 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_2_2_2)
node atomics_a_mask_sub_2_1_2 = or(atomics_a_mask_sub_sub_1_1_2, _atomics_a_mask_sub_acc_T_10)
node atomics_a_mask_sub_3_2_2 = and(atomics_a_mask_sub_sub_1_2_2, atomics_a_mask_sub_bit_2)
node _atomics_a_mask_sub_acc_T_11 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_3_2_2)
node atomics_a_mask_sub_3_1_2 = or(atomics_a_mask_sub_sub_1_1_2, _atomics_a_mask_sub_acc_T_11)
node atomics_a_mask_size_2 = bits(atomics_a_mask_sizeOH_2, 0, 0)
node atomics_a_mask_bit_2 = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit_2 = eq(atomics_a_mask_bit_2, UInt<1>(0h0))
node atomics_a_mask_eq_16 = and(atomics_a_mask_sub_0_2_2, atomics_a_mask_nbit_2)
node _atomics_a_mask_acc_T_16 = and(atomics_a_mask_size_2, atomics_a_mask_eq_16)
node atomics_a_mask_acc_16 = or(atomics_a_mask_sub_0_1_2, _atomics_a_mask_acc_T_16)
node atomics_a_mask_eq_17 = and(atomics_a_mask_sub_0_2_2, atomics_a_mask_bit_2)
node _atomics_a_mask_acc_T_17 = and(atomics_a_mask_size_2, atomics_a_mask_eq_17)
node atomics_a_mask_acc_17 = or(atomics_a_mask_sub_0_1_2, _atomics_a_mask_acc_T_17)
node atomics_a_mask_eq_18 = and(atomics_a_mask_sub_1_2_2, atomics_a_mask_nbit_2)
node _atomics_a_mask_acc_T_18 = and(atomics_a_mask_size_2, atomics_a_mask_eq_18)
node atomics_a_mask_acc_18 = or(atomics_a_mask_sub_1_1_2, _atomics_a_mask_acc_T_18)
node atomics_a_mask_eq_19 = and(atomics_a_mask_sub_1_2_2, atomics_a_mask_bit_2)
node _atomics_a_mask_acc_T_19 = and(atomics_a_mask_size_2, atomics_a_mask_eq_19)
node atomics_a_mask_acc_19 = or(atomics_a_mask_sub_1_1_2, _atomics_a_mask_acc_T_19)
node atomics_a_mask_eq_20 = and(atomics_a_mask_sub_2_2_2, atomics_a_mask_nbit_2)
node _atomics_a_mask_acc_T_20 = and(atomics_a_mask_size_2, atomics_a_mask_eq_20)
node atomics_a_mask_acc_20 = or(atomics_a_mask_sub_2_1_2, _atomics_a_mask_acc_T_20)
node atomics_a_mask_eq_21 = and(atomics_a_mask_sub_2_2_2, atomics_a_mask_bit_2)
node _atomics_a_mask_acc_T_21 = and(atomics_a_mask_size_2, atomics_a_mask_eq_21)
node atomics_a_mask_acc_21 = or(atomics_a_mask_sub_2_1_2, _atomics_a_mask_acc_T_21)
node atomics_a_mask_eq_22 = and(atomics_a_mask_sub_3_2_2, atomics_a_mask_nbit_2)
node _atomics_a_mask_acc_T_22 = and(atomics_a_mask_size_2, atomics_a_mask_eq_22)
node atomics_a_mask_acc_22 = or(atomics_a_mask_sub_3_1_2, _atomics_a_mask_acc_T_22)
node atomics_a_mask_eq_23 = and(atomics_a_mask_sub_3_2_2, atomics_a_mask_bit_2)
node _atomics_a_mask_acc_T_23 = and(atomics_a_mask_size_2, atomics_a_mask_eq_23)
node atomics_a_mask_acc_23 = or(atomics_a_mask_sub_3_1_2, _atomics_a_mask_acc_T_23)
node atomics_a_mask_lo_lo_2 = cat(atomics_a_mask_acc_17, atomics_a_mask_acc_16)
node atomics_a_mask_lo_hi_2 = cat(atomics_a_mask_acc_19, atomics_a_mask_acc_18)
node atomics_a_mask_lo_2 = cat(atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2)
node atomics_a_mask_hi_lo_2 = cat(atomics_a_mask_acc_21, atomics_a_mask_acc_20)
node atomics_a_mask_hi_hi_2 = cat(atomics_a_mask_acc_23, atomics_a_mask_acc_22)
node atomics_a_mask_hi_2 = cat(atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2)
node _atomics_a_mask_T_2 = cat(atomics_a_mask_hi_2, atomics_a_mask_lo_2)
connect atomics_a_2.mask, _atomics_a_mask_T_2
connect atomics_a_2.data, pstore1_data
connect atomics_a_2.corrupt, UInt<1>(0h0)
node _atomics_legal_T_162 = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_163 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_164 = and(_atomics_legal_T_162, _atomics_legal_T_163)
node _atomics_legal_T_165 = or(UInt<1>(0h0), _atomics_legal_T_164)
node _atomics_legal_T_166 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_167 = cvt(_atomics_legal_T_166)
node _atomics_legal_T_168 = and(_atomics_legal_T_167, asSInt(UInt<33>(0h8a010000)))
node _atomics_legal_T_169 = asSInt(_atomics_legal_T_168)
node _atomics_legal_T_170 = eq(_atomics_legal_T_169, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_171 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_172 = cvt(_atomics_legal_T_171)
node _atomics_legal_T_173 = and(_atomics_legal_T_172, asSInt(UInt<33>(0h8a101000)))
node _atomics_legal_T_174 = asSInt(_atomics_legal_T_173)
node _atomics_legal_T_175 = eq(_atomics_legal_T_174, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_176 = xor(s2_req.addr, UInt<26>(0h2000000))
node _atomics_legal_T_177 = cvt(_atomics_legal_T_176)
node _atomics_legal_T_178 = and(_atomics_legal_T_177, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_179 = asSInt(_atomics_legal_T_178)
node _atomics_legal_T_180 = eq(_atomics_legal_T_179, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_181 = xor(s2_req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_182 = cvt(_atomics_legal_T_181)
node _atomics_legal_T_183 = and(_atomics_legal_T_182, asSInt(UInt<33>(0h8a111000)))
node _atomics_legal_T_184 = asSInt(_atomics_legal_T_183)
node _atomics_legal_T_185 = eq(_atomics_legal_T_184, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_186 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_187 = cvt(_atomics_legal_T_186)
node _atomics_legal_T_188 = and(_atomics_legal_T_187, asSInt(UInt<33>(0h88000000)))
node _atomics_legal_T_189 = asSInt(_atomics_legal_T_188)
node _atomics_legal_T_190 = eq(_atomics_legal_T_189, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_191 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_192 = cvt(_atomics_legal_T_191)
node _atomics_legal_T_193 = and(_atomics_legal_T_192, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_194 = asSInt(_atomics_legal_T_193)
node _atomics_legal_T_195 = eq(_atomics_legal_T_194, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_196 = xor(s2_req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_197 = cvt(_atomics_legal_T_196)
node _atomics_legal_T_198 = and(_atomics_legal_T_197, asSInt(UInt<33>(0h80000000)))
node _atomics_legal_T_199 = asSInt(_atomics_legal_T_198)
node _atomics_legal_T_200 = eq(_atomics_legal_T_199, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_201 = or(_atomics_legal_T_170, _atomics_legal_T_175)
node _atomics_legal_T_202 = or(_atomics_legal_T_201, _atomics_legal_T_180)
node _atomics_legal_T_203 = or(_atomics_legal_T_202, _atomics_legal_T_185)
node _atomics_legal_T_204 = or(_atomics_legal_T_203, _atomics_legal_T_190)
node _atomics_legal_T_205 = or(_atomics_legal_T_204, _atomics_legal_T_195)
node _atomics_legal_T_206 = or(_atomics_legal_T_205, _atomics_legal_T_200)
node _atomics_legal_T_207 = and(_atomics_legal_T_165, _atomics_legal_T_206)
node _atomics_legal_T_208 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_209 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_210 = cvt(_atomics_legal_T_209)
node _atomics_legal_T_211 = and(_atomics_legal_T_210, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_212 = asSInt(_atomics_legal_T_211)
node _atomics_legal_T_213 = eq(_atomics_legal_T_212, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_214 = and(_atomics_legal_T_208, _atomics_legal_T_213)
node _atomics_legal_T_215 = or(UInt<1>(0h0), _atomics_legal_T_207)
node atomics_legal_3 = or(_atomics_legal_T_215, _atomics_legal_T_214)
wire atomics_a_3 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_3.opcode, UInt<2>(0h3)
connect atomics_a_3.param, UInt<3>(0h2)
connect atomics_a_3.size, s2_req.size
connect atomics_a_3.source, UInt<1>(0h0)
connect atomics_a_3.address, s2_req.addr
node _atomics_a_mask_sizeOH_T_9 = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_3 = bits(_atomics_a_mask_sizeOH_T_9, 1, 0)
node _atomics_a_mask_sizeOH_T_10 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_3)
node _atomics_a_mask_sizeOH_T_11 = bits(_atomics_a_mask_sizeOH_T_10, 2, 0)
node atomics_a_mask_sizeOH_3 = or(_atomics_a_mask_sizeOH_T_11, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_3 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_3 = bits(atomics_a_mask_sizeOH_3, 2, 2)
node atomics_a_mask_sub_sub_bit_3 = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_3 = eq(atomics_a_mask_sub_sub_bit_3, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_3 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_3)
node _atomics_a_mask_sub_sub_acc_T_6 = and(atomics_a_mask_sub_sub_size_3, atomics_a_mask_sub_sub_0_2_3)
node atomics_a_mask_sub_sub_0_1_3 = or(atomics_a_mask_sub_sub_sub_0_1_3, _atomics_a_mask_sub_sub_acc_T_6)
node atomics_a_mask_sub_sub_1_2_3 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_3)
node _atomics_a_mask_sub_sub_acc_T_7 = and(atomics_a_mask_sub_sub_size_3, atomics_a_mask_sub_sub_1_2_3)
node atomics_a_mask_sub_sub_1_1_3 = or(atomics_a_mask_sub_sub_sub_0_1_3, _atomics_a_mask_sub_sub_acc_T_7)
node atomics_a_mask_sub_size_3 = bits(atomics_a_mask_sizeOH_3, 1, 1)
node atomics_a_mask_sub_bit_3 = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit_3 = eq(atomics_a_mask_sub_bit_3, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_3 = and(atomics_a_mask_sub_sub_0_2_3, atomics_a_mask_sub_nbit_3)
node _atomics_a_mask_sub_acc_T_12 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_0_2_3)
node atomics_a_mask_sub_0_1_3 = or(atomics_a_mask_sub_sub_0_1_3, _atomics_a_mask_sub_acc_T_12)
node atomics_a_mask_sub_1_2_3 = and(atomics_a_mask_sub_sub_0_2_3, atomics_a_mask_sub_bit_3)
node _atomics_a_mask_sub_acc_T_13 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_1_2_3)
node atomics_a_mask_sub_1_1_3 = or(atomics_a_mask_sub_sub_0_1_3, _atomics_a_mask_sub_acc_T_13)
node atomics_a_mask_sub_2_2_3 = and(atomics_a_mask_sub_sub_1_2_3, atomics_a_mask_sub_nbit_3)
node _atomics_a_mask_sub_acc_T_14 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_2_2_3)
node atomics_a_mask_sub_2_1_3 = or(atomics_a_mask_sub_sub_1_1_3, _atomics_a_mask_sub_acc_T_14)
node atomics_a_mask_sub_3_2_3 = and(atomics_a_mask_sub_sub_1_2_3, atomics_a_mask_sub_bit_3)
node _atomics_a_mask_sub_acc_T_15 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_3_2_3)
node atomics_a_mask_sub_3_1_3 = or(atomics_a_mask_sub_sub_1_1_3, _atomics_a_mask_sub_acc_T_15)
node atomics_a_mask_size_3 = bits(atomics_a_mask_sizeOH_3, 0, 0)
node atomics_a_mask_bit_3 = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit_3 = eq(atomics_a_mask_bit_3, UInt<1>(0h0))
node atomics_a_mask_eq_24 = and(atomics_a_mask_sub_0_2_3, atomics_a_mask_nbit_3)
node _atomics_a_mask_acc_T_24 = and(atomics_a_mask_size_3, atomics_a_mask_eq_24)
node atomics_a_mask_acc_24 = or(atomics_a_mask_sub_0_1_3, _atomics_a_mask_acc_T_24)
node atomics_a_mask_eq_25 = and(atomics_a_mask_sub_0_2_3, atomics_a_mask_bit_3)
node _atomics_a_mask_acc_T_25 = and(atomics_a_mask_size_3, atomics_a_mask_eq_25)
node atomics_a_mask_acc_25 = or(atomics_a_mask_sub_0_1_3, _atomics_a_mask_acc_T_25)
node atomics_a_mask_eq_26 = and(atomics_a_mask_sub_1_2_3, atomics_a_mask_nbit_3)
node _atomics_a_mask_acc_T_26 = and(atomics_a_mask_size_3, atomics_a_mask_eq_26)
node atomics_a_mask_acc_26 = or(atomics_a_mask_sub_1_1_3, _atomics_a_mask_acc_T_26)
node atomics_a_mask_eq_27 = and(atomics_a_mask_sub_1_2_3, atomics_a_mask_bit_3)
node _atomics_a_mask_acc_T_27 = and(atomics_a_mask_size_3, atomics_a_mask_eq_27)
node atomics_a_mask_acc_27 = or(atomics_a_mask_sub_1_1_3, _atomics_a_mask_acc_T_27)
node atomics_a_mask_eq_28 = and(atomics_a_mask_sub_2_2_3, atomics_a_mask_nbit_3)
node _atomics_a_mask_acc_T_28 = and(atomics_a_mask_size_3, atomics_a_mask_eq_28)
node atomics_a_mask_acc_28 = or(atomics_a_mask_sub_2_1_3, _atomics_a_mask_acc_T_28)
node atomics_a_mask_eq_29 = and(atomics_a_mask_sub_2_2_3, atomics_a_mask_bit_3)
node _atomics_a_mask_acc_T_29 = and(atomics_a_mask_size_3, atomics_a_mask_eq_29)
node atomics_a_mask_acc_29 = or(atomics_a_mask_sub_2_1_3, _atomics_a_mask_acc_T_29)
node atomics_a_mask_eq_30 = and(atomics_a_mask_sub_3_2_3, atomics_a_mask_nbit_3)
node _atomics_a_mask_acc_T_30 = and(atomics_a_mask_size_3, atomics_a_mask_eq_30)
node atomics_a_mask_acc_30 = or(atomics_a_mask_sub_3_1_3, _atomics_a_mask_acc_T_30)
node atomics_a_mask_eq_31 = and(atomics_a_mask_sub_3_2_3, atomics_a_mask_bit_3)
node _atomics_a_mask_acc_T_31 = and(atomics_a_mask_size_3, atomics_a_mask_eq_31)
node atomics_a_mask_acc_31 = or(atomics_a_mask_sub_3_1_3, _atomics_a_mask_acc_T_31)
node atomics_a_mask_lo_lo_3 = cat(atomics_a_mask_acc_25, atomics_a_mask_acc_24)
node atomics_a_mask_lo_hi_3 = cat(atomics_a_mask_acc_27, atomics_a_mask_acc_26)
node atomics_a_mask_lo_3 = cat(atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3)
node atomics_a_mask_hi_lo_3 = cat(atomics_a_mask_acc_29, atomics_a_mask_acc_28)
node atomics_a_mask_hi_hi_3 = cat(atomics_a_mask_acc_31, atomics_a_mask_acc_30)
node atomics_a_mask_hi_3 = cat(atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3)
node _atomics_a_mask_T_3 = cat(atomics_a_mask_hi_3, atomics_a_mask_lo_3)
connect atomics_a_3.mask, _atomics_a_mask_T_3
connect atomics_a_3.data, pstore1_data
connect atomics_a_3.corrupt, UInt<1>(0h0)
node _atomics_legal_T_216 = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_217 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_218 = and(_atomics_legal_T_216, _atomics_legal_T_217)
node _atomics_legal_T_219 = or(UInt<1>(0h0), _atomics_legal_T_218)
node _atomics_legal_T_220 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_221 = cvt(_atomics_legal_T_220)
node _atomics_legal_T_222 = and(_atomics_legal_T_221, asSInt(UInt<33>(0h8a010000)))
node _atomics_legal_T_223 = asSInt(_atomics_legal_T_222)
node _atomics_legal_T_224 = eq(_atomics_legal_T_223, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_225 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_226 = cvt(_atomics_legal_T_225)
node _atomics_legal_T_227 = and(_atomics_legal_T_226, asSInt(UInt<33>(0h8a101000)))
node _atomics_legal_T_228 = asSInt(_atomics_legal_T_227)
node _atomics_legal_T_229 = eq(_atomics_legal_T_228, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_230 = xor(s2_req.addr, UInt<26>(0h2000000))
node _atomics_legal_T_231 = cvt(_atomics_legal_T_230)
node _atomics_legal_T_232 = and(_atomics_legal_T_231, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_233 = asSInt(_atomics_legal_T_232)
node _atomics_legal_T_234 = eq(_atomics_legal_T_233, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_235 = xor(s2_req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_236 = cvt(_atomics_legal_T_235)
node _atomics_legal_T_237 = and(_atomics_legal_T_236, asSInt(UInt<33>(0h8a111000)))
node _atomics_legal_T_238 = asSInt(_atomics_legal_T_237)
node _atomics_legal_T_239 = eq(_atomics_legal_T_238, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_240 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_241 = cvt(_atomics_legal_T_240)
node _atomics_legal_T_242 = and(_atomics_legal_T_241, asSInt(UInt<33>(0h88000000)))
node _atomics_legal_T_243 = asSInt(_atomics_legal_T_242)
node _atomics_legal_T_244 = eq(_atomics_legal_T_243, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_245 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_246 = cvt(_atomics_legal_T_245)
node _atomics_legal_T_247 = and(_atomics_legal_T_246, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_248 = asSInt(_atomics_legal_T_247)
node _atomics_legal_T_249 = eq(_atomics_legal_T_248, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_250 = xor(s2_req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_251 = cvt(_atomics_legal_T_250)
node _atomics_legal_T_252 = and(_atomics_legal_T_251, asSInt(UInt<33>(0h80000000)))
node _atomics_legal_T_253 = asSInt(_atomics_legal_T_252)
node _atomics_legal_T_254 = eq(_atomics_legal_T_253, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_255 = or(_atomics_legal_T_224, _atomics_legal_T_229)
node _atomics_legal_T_256 = or(_atomics_legal_T_255, _atomics_legal_T_234)
node _atomics_legal_T_257 = or(_atomics_legal_T_256, _atomics_legal_T_239)
node _atomics_legal_T_258 = or(_atomics_legal_T_257, _atomics_legal_T_244)
node _atomics_legal_T_259 = or(_atomics_legal_T_258, _atomics_legal_T_249)
node _atomics_legal_T_260 = or(_atomics_legal_T_259, _atomics_legal_T_254)
node _atomics_legal_T_261 = and(_atomics_legal_T_219, _atomics_legal_T_260)
node _atomics_legal_T_262 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_263 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_264 = cvt(_atomics_legal_T_263)
node _atomics_legal_T_265 = and(_atomics_legal_T_264, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_266 = asSInt(_atomics_legal_T_265)
node _atomics_legal_T_267 = eq(_atomics_legal_T_266, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_268 = and(_atomics_legal_T_262, _atomics_legal_T_267)
node _atomics_legal_T_269 = or(UInt<1>(0h0), _atomics_legal_T_261)
node atomics_legal_4 = or(_atomics_legal_T_269, _atomics_legal_T_268)
wire atomics_a_4 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_4.opcode, UInt<2>(0h2)
connect atomics_a_4.param, UInt<3>(0h4)
connect atomics_a_4.size, s2_req.size
connect atomics_a_4.source, UInt<1>(0h0)
connect atomics_a_4.address, s2_req.addr
node _atomics_a_mask_sizeOH_T_12 = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_4 = bits(_atomics_a_mask_sizeOH_T_12, 1, 0)
node _atomics_a_mask_sizeOH_T_13 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_4)
node _atomics_a_mask_sizeOH_T_14 = bits(_atomics_a_mask_sizeOH_T_13, 2, 0)
node atomics_a_mask_sizeOH_4 = or(_atomics_a_mask_sizeOH_T_14, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_4 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_4 = bits(atomics_a_mask_sizeOH_4, 2, 2)
node atomics_a_mask_sub_sub_bit_4 = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_4 = eq(atomics_a_mask_sub_sub_bit_4, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_4 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_4)
node _atomics_a_mask_sub_sub_acc_T_8 = and(atomics_a_mask_sub_sub_size_4, atomics_a_mask_sub_sub_0_2_4)
node atomics_a_mask_sub_sub_0_1_4 = or(atomics_a_mask_sub_sub_sub_0_1_4, _atomics_a_mask_sub_sub_acc_T_8)
node atomics_a_mask_sub_sub_1_2_4 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_4)
node _atomics_a_mask_sub_sub_acc_T_9 = and(atomics_a_mask_sub_sub_size_4, atomics_a_mask_sub_sub_1_2_4)
node atomics_a_mask_sub_sub_1_1_4 = or(atomics_a_mask_sub_sub_sub_0_1_4, _atomics_a_mask_sub_sub_acc_T_9)
node atomics_a_mask_sub_size_4 = bits(atomics_a_mask_sizeOH_4, 1, 1)
node atomics_a_mask_sub_bit_4 = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit_4 = eq(atomics_a_mask_sub_bit_4, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_4 = and(atomics_a_mask_sub_sub_0_2_4, atomics_a_mask_sub_nbit_4)
node _atomics_a_mask_sub_acc_T_16 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_0_2_4)
node atomics_a_mask_sub_0_1_4 = or(atomics_a_mask_sub_sub_0_1_4, _atomics_a_mask_sub_acc_T_16)
node atomics_a_mask_sub_1_2_4 = and(atomics_a_mask_sub_sub_0_2_4, atomics_a_mask_sub_bit_4)
node _atomics_a_mask_sub_acc_T_17 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_1_2_4)
node atomics_a_mask_sub_1_1_4 = or(atomics_a_mask_sub_sub_0_1_4, _atomics_a_mask_sub_acc_T_17)
node atomics_a_mask_sub_2_2_4 = and(atomics_a_mask_sub_sub_1_2_4, atomics_a_mask_sub_nbit_4)
node _atomics_a_mask_sub_acc_T_18 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_2_2_4)
node atomics_a_mask_sub_2_1_4 = or(atomics_a_mask_sub_sub_1_1_4, _atomics_a_mask_sub_acc_T_18)
node atomics_a_mask_sub_3_2_4 = and(atomics_a_mask_sub_sub_1_2_4, atomics_a_mask_sub_bit_4)
node _atomics_a_mask_sub_acc_T_19 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_3_2_4)
node atomics_a_mask_sub_3_1_4 = or(atomics_a_mask_sub_sub_1_1_4, _atomics_a_mask_sub_acc_T_19)
node atomics_a_mask_size_4 = bits(atomics_a_mask_sizeOH_4, 0, 0)
node atomics_a_mask_bit_4 = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit_4 = eq(atomics_a_mask_bit_4, UInt<1>(0h0))
node atomics_a_mask_eq_32 = and(atomics_a_mask_sub_0_2_4, atomics_a_mask_nbit_4)
node _atomics_a_mask_acc_T_32 = and(atomics_a_mask_size_4, atomics_a_mask_eq_32)
node atomics_a_mask_acc_32 = or(atomics_a_mask_sub_0_1_4, _atomics_a_mask_acc_T_32)
node atomics_a_mask_eq_33 = and(atomics_a_mask_sub_0_2_4, atomics_a_mask_bit_4)
node _atomics_a_mask_acc_T_33 = and(atomics_a_mask_size_4, atomics_a_mask_eq_33)
node atomics_a_mask_acc_33 = or(atomics_a_mask_sub_0_1_4, _atomics_a_mask_acc_T_33)
node atomics_a_mask_eq_34 = and(atomics_a_mask_sub_1_2_4, atomics_a_mask_nbit_4)
node _atomics_a_mask_acc_T_34 = and(atomics_a_mask_size_4, atomics_a_mask_eq_34)
node atomics_a_mask_acc_34 = or(atomics_a_mask_sub_1_1_4, _atomics_a_mask_acc_T_34)
node atomics_a_mask_eq_35 = and(atomics_a_mask_sub_1_2_4, atomics_a_mask_bit_4)
node _atomics_a_mask_acc_T_35 = and(atomics_a_mask_size_4, atomics_a_mask_eq_35)
node atomics_a_mask_acc_35 = or(atomics_a_mask_sub_1_1_4, _atomics_a_mask_acc_T_35)
node atomics_a_mask_eq_36 = and(atomics_a_mask_sub_2_2_4, atomics_a_mask_nbit_4)
node _atomics_a_mask_acc_T_36 = and(atomics_a_mask_size_4, atomics_a_mask_eq_36)
node atomics_a_mask_acc_36 = or(atomics_a_mask_sub_2_1_4, _atomics_a_mask_acc_T_36)
node atomics_a_mask_eq_37 = and(atomics_a_mask_sub_2_2_4, atomics_a_mask_bit_4)
node _atomics_a_mask_acc_T_37 = and(atomics_a_mask_size_4, atomics_a_mask_eq_37)
node atomics_a_mask_acc_37 = or(atomics_a_mask_sub_2_1_4, _atomics_a_mask_acc_T_37)
node atomics_a_mask_eq_38 = and(atomics_a_mask_sub_3_2_4, atomics_a_mask_nbit_4)
node _atomics_a_mask_acc_T_38 = and(atomics_a_mask_size_4, atomics_a_mask_eq_38)
node atomics_a_mask_acc_38 = or(atomics_a_mask_sub_3_1_4, _atomics_a_mask_acc_T_38)
node atomics_a_mask_eq_39 = and(atomics_a_mask_sub_3_2_4, atomics_a_mask_bit_4)
node _atomics_a_mask_acc_T_39 = and(atomics_a_mask_size_4, atomics_a_mask_eq_39)
node atomics_a_mask_acc_39 = or(atomics_a_mask_sub_3_1_4, _atomics_a_mask_acc_T_39)
node atomics_a_mask_lo_lo_4 = cat(atomics_a_mask_acc_33, atomics_a_mask_acc_32)
node atomics_a_mask_lo_hi_4 = cat(atomics_a_mask_acc_35, atomics_a_mask_acc_34)
node atomics_a_mask_lo_4 = cat(atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4)
node atomics_a_mask_hi_lo_4 = cat(atomics_a_mask_acc_37, atomics_a_mask_acc_36)
node atomics_a_mask_hi_hi_4 = cat(atomics_a_mask_acc_39, atomics_a_mask_acc_38)
node atomics_a_mask_hi_4 = cat(atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4)
node _atomics_a_mask_T_4 = cat(atomics_a_mask_hi_4, atomics_a_mask_lo_4)
connect atomics_a_4.mask, _atomics_a_mask_T_4
connect atomics_a_4.data, pstore1_data
connect atomics_a_4.corrupt, UInt<1>(0h0)
node _atomics_legal_T_270 = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_271 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_272 = and(_atomics_legal_T_270, _atomics_legal_T_271)
node _atomics_legal_T_273 = or(UInt<1>(0h0), _atomics_legal_T_272)
node _atomics_legal_T_274 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_275 = cvt(_atomics_legal_T_274)
node _atomics_legal_T_276 = and(_atomics_legal_T_275, asSInt(UInt<33>(0h8a010000)))
node _atomics_legal_T_277 = asSInt(_atomics_legal_T_276)
node _atomics_legal_T_278 = eq(_atomics_legal_T_277, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_279 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_280 = cvt(_atomics_legal_T_279)
node _atomics_legal_T_281 = and(_atomics_legal_T_280, asSInt(UInt<33>(0h8a101000)))
node _atomics_legal_T_282 = asSInt(_atomics_legal_T_281)
node _atomics_legal_T_283 = eq(_atomics_legal_T_282, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_284 = xor(s2_req.addr, UInt<26>(0h2000000))
node _atomics_legal_T_285 = cvt(_atomics_legal_T_284)
node _atomics_legal_T_286 = and(_atomics_legal_T_285, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_287 = asSInt(_atomics_legal_T_286)
node _atomics_legal_T_288 = eq(_atomics_legal_T_287, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_289 = xor(s2_req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_290 = cvt(_atomics_legal_T_289)
node _atomics_legal_T_291 = and(_atomics_legal_T_290, asSInt(UInt<33>(0h8a111000)))
node _atomics_legal_T_292 = asSInt(_atomics_legal_T_291)
node _atomics_legal_T_293 = eq(_atomics_legal_T_292, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_294 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_295 = cvt(_atomics_legal_T_294)
node _atomics_legal_T_296 = and(_atomics_legal_T_295, asSInt(UInt<33>(0h88000000)))
node _atomics_legal_T_297 = asSInt(_atomics_legal_T_296)
node _atomics_legal_T_298 = eq(_atomics_legal_T_297, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_299 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_300 = cvt(_atomics_legal_T_299)
node _atomics_legal_T_301 = and(_atomics_legal_T_300, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_302 = asSInt(_atomics_legal_T_301)
node _atomics_legal_T_303 = eq(_atomics_legal_T_302, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_304 = xor(s2_req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_305 = cvt(_atomics_legal_T_304)
node _atomics_legal_T_306 = and(_atomics_legal_T_305, asSInt(UInt<33>(0h80000000)))
node _atomics_legal_T_307 = asSInt(_atomics_legal_T_306)
node _atomics_legal_T_308 = eq(_atomics_legal_T_307, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_309 = or(_atomics_legal_T_278, _atomics_legal_T_283)
node _atomics_legal_T_310 = or(_atomics_legal_T_309, _atomics_legal_T_288)
node _atomics_legal_T_311 = or(_atomics_legal_T_310, _atomics_legal_T_293)
node _atomics_legal_T_312 = or(_atomics_legal_T_311, _atomics_legal_T_298)
node _atomics_legal_T_313 = or(_atomics_legal_T_312, _atomics_legal_T_303)
node _atomics_legal_T_314 = or(_atomics_legal_T_313, _atomics_legal_T_308)
node _atomics_legal_T_315 = and(_atomics_legal_T_273, _atomics_legal_T_314)
node _atomics_legal_T_316 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_317 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_318 = cvt(_atomics_legal_T_317)
node _atomics_legal_T_319 = and(_atomics_legal_T_318, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_320 = asSInt(_atomics_legal_T_319)
node _atomics_legal_T_321 = eq(_atomics_legal_T_320, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_322 = and(_atomics_legal_T_316, _atomics_legal_T_321)
node _atomics_legal_T_323 = or(UInt<1>(0h0), _atomics_legal_T_315)
node atomics_legal_5 = or(_atomics_legal_T_323, _atomics_legal_T_322)
wire atomics_a_5 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_5.opcode, UInt<2>(0h2)
connect atomics_a_5.param, UInt<3>(0h0)
connect atomics_a_5.size, s2_req.size
connect atomics_a_5.source, UInt<1>(0h0)
connect atomics_a_5.address, s2_req.addr
node _atomics_a_mask_sizeOH_T_15 = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_5 = bits(_atomics_a_mask_sizeOH_T_15, 1, 0)
node _atomics_a_mask_sizeOH_T_16 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_5)
node _atomics_a_mask_sizeOH_T_17 = bits(_atomics_a_mask_sizeOH_T_16, 2, 0)
node atomics_a_mask_sizeOH_5 = or(_atomics_a_mask_sizeOH_T_17, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_5 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_5 = bits(atomics_a_mask_sizeOH_5, 2, 2)
node atomics_a_mask_sub_sub_bit_5 = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_5 = eq(atomics_a_mask_sub_sub_bit_5, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_5 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_5)
node _atomics_a_mask_sub_sub_acc_T_10 = and(atomics_a_mask_sub_sub_size_5, atomics_a_mask_sub_sub_0_2_5)
node atomics_a_mask_sub_sub_0_1_5 = or(atomics_a_mask_sub_sub_sub_0_1_5, _atomics_a_mask_sub_sub_acc_T_10)
node atomics_a_mask_sub_sub_1_2_5 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_5)
node _atomics_a_mask_sub_sub_acc_T_11 = and(atomics_a_mask_sub_sub_size_5, atomics_a_mask_sub_sub_1_2_5)
node atomics_a_mask_sub_sub_1_1_5 = or(atomics_a_mask_sub_sub_sub_0_1_5, _atomics_a_mask_sub_sub_acc_T_11)
node atomics_a_mask_sub_size_5 = bits(atomics_a_mask_sizeOH_5, 1, 1)
node atomics_a_mask_sub_bit_5 = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit_5 = eq(atomics_a_mask_sub_bit_5, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_5 = and(atomics_a_mask_sub_sub_0_2_5, atomics_a_mask_sub_nbit_5)
node _atomics_a_mask_sub_acc_T_20 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_0_2_5)
node atomics_a_mask_sub_0_1_5 = or(atomics_a_mask_sub_sub_0_1_5, _atomics_a_mask_sub_acc_T_20)
node atomics_a_mask_sub_1_2_5 = and(atomics_a_mask_sub_sub_0_2_5, atomics_a_mask_sub_bit_5)
node _atomics_a_mask_sub_acc_T_21 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_1_2_5)
node atomics_a_mask_sub_1_1_5 = or(atomics_a_mask_sub_sub_0_1_5, _atomics_a_mask_sub_acc_T_21)
node atomics_a_mask_sub_2_2_5 = and(atomics_a_mask_sub_sub_1_2_5, atomics_a_mask_sub_nbit_5)
node _atomics_a_mask_sub_acc_T_22 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_2_2_5)
node atomics_a_mask_sub_2_1_5 = or(atomics_a_mask_sub_sub_1_1_5, _atomics_a_mask_sub_acc_T_22)
node atomics_a_mask_sub_3_2_5 = and(atomics_a_mask_sub_sub_1_2_5, atomics_a_mask_sub_bit_5)
node _atomics_a_mask_sub_acc_T_23 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_3_2_5)
node atomics_a_mask_sub_3_1_5 = or(atomics_a_mask_sub_sub_1_1_5, _atomics_a_mask_sub_acc_T_23)
node atomics_a_mask_size_5 = bits(atomics_a_mask_sizeOH_5, 0, 0)
node atomics_a_mask_bit_5 = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit_5 = eq(atomics_a_mask_bit_5, UInt<1>(0h0))
node atomics_a_mask_eq_40 = and(atomics_a_mask_sub_0_2_5, atomics_a_mask_nbit_5)
node _atomics_a_mask_acc_T_40 = and(atomics_a_mask_size_5, atomics_a_mask_eq_40)
node atomics_a_mask_acc_40 = or(atomics_a_mask_sub_0_1_5, _atomics_a_mask_acc_T_40)
node atomics_a_mask_eq_41 = and(atomics_a_mask_sub_0_2_5, atomics_a_mask_bit_5)
node _atomics_a_mask_acc_T_41 = and(atomics_a_mask_size_5, atomics_a_mask_eq_41)
node atomics_a_mask_acc_41 = or(atomics_a_mask_sub_0_1_5, _atomics_a_mask_acc_T_41)
node atomics_a_mask_eq_42 = and(atomics_a_mask_sub_1_2_5, atomics_a_mask_nbit_5)
node _atomics_a_mask_acc_T_42 = and(atomics_a_mask_size_5, atomics_a_mask_eq_42)
node atomics_a_mask_acc_42 = or(atomics_a_mask_sub_1_1_5, _atomics_a_mask_acc_T_42)
node atomics_a_mask_eq_43 = and(atomics_a_mask_sub_1_2_5, atomics_a_mask_bit_5)
node _atomics_a_mask_acc_T_43 = and(atomics_a_mask_size_5, atomics_a_mask_eq_43)
node atomics_a_mask_acc_43 = or(atomics_a_mask_sub_1_1_5, _atomics_a_mask_acc_T_43)
node atomics_a_mask_eq_44 = and(atomics_a_mask_sub_2_2_5, atomics_a_mask_nbit_5)
node _atomics_a_mask_acc_T_44 = and(atomics_a_mask_size_5, atomics_a_mask_eq_44)
node atomics_a_mask_acc_44 = or(atomics_a_mask_sub_2_1_5, _atomics_a_mask_acc_T_44)
node atomics_a_mask_eq_45 = and(atomics_a_mask_sub_2_2_5, atomics_a_mask_bit_5)
node _atomics_a_mask_acc_T_45 = and(atomics_a_mask_size_5, atomics_a_mask_eq_45)
node atomics_a_mask_acc_45 = or(atomics_a_mask_sub_2_1_5, _atomics_a_mask_acc_T_45)
node atomics_a_mask_eq_46 = and(atomics_a_mask_sub_3_2_5, atomics_a_mask_nbit_5)
node _atomics_a_mask_acc_T_46 = and(atomics_a_mask_size_5, atomics_a_mask_eq_46)
node atomics_a_mask_acc_46 = or(atomics_a_mask_sub_3_1_5, _atomics_a_mask_acc_T_46)
node atomics_a_mask_eq_47 = and(atomics_a_mask_sub_3_2_5, atomics_a_mask_bit_5)
node _atomics_a_mask_acc_T_47 = and(atomics_a_mask_size_5, atomics_a_mask_eq_47)
node atomics_a_mask_acc_47 = or(atomics_a_mask_sub_3_1_5, _atomics_a_mask_acc_T_47)
node atomics_a_mask_lo_lo_5 = cat(atomics_a_mask_acc_41, atomics_a_mask_acc_40)
node atomics_a_mask_lo_hi_5 = cat(atomics_a_mask_acc_43, atomics_a_mask_acc_42)
node atomics_a_mask_lo_5 = cat(atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5)
node atomics_a_mask_hi_lo_5 = cat(atomics_a_mask_acc_45, atomics_a_mask_acc_44)
node atomics_a_mask_hi_hi_5 = cat(atomics_a_mask_acc_47, atomics_a_mask_acc_46)
node atomics_a_mask_hi_5 = cat(atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5)
node _atomics_a_mask_T_5 = cat(atomics_a_mask_hi_5, atomics_a_mask_lo_5)
connect atomics_a_5.mask, _atomics_a_mask_T_5
connect atomics_a_5.data, pstore1_data
connect atomics_a_5.corrupt, UInt<1>(0h0)
node _atomics_legal_T_324 = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_325 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_326 = and(_atomics_legal_T_324, _atomics_legal_T_325)
node _atomics_legal_T_327 = or(UInt<1>(0h0), _atomics_legal_T_326)
node _atomics_legal_T_328 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_329 = cvt(_atomics_legal_T_328)
node _atomics_legal_T_330 = and(_atomics_legal_T_329, asSInt(UInt<33>(0h8a010000)))
node _atomics_legal_T_331 = asSInt(_atomics_legal_T_330)
node _atomics_legal_T_332 = eq(_atomics_legal_T_331, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_333 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_334 = cvt(_atomics_legal_T_333)
node _atomics_legal_T_335 = and(_atomics_legal_T_334, asSInt(UInt<33>(0h8a101000)))
node _atomics_legal_T_336 = asSInt(_atomics_legal_T_335)
node _atomics_legal_T_337 = eq(_atomics_legal_T_336, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_338 = xor(s2_req.addr, UInt<26>(0h2000000))
node _atomics_legal_T_339 = cvt(_atomics_legal_T_338)
node _atomics_legal_T_340 = and(_atomics_legal_T_339, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_341 = asSInt(_atomics_legal_T_340)
node _atomics_legal_T_342 = eq(_atomics_legal_T_341, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_343 = xor(s2_req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_344 = cvt(_atomics_legal_T_343)
node _atomics_legal_T_345 = and(_atomics_legal_T_344, asSInt(UInt<33>(0h8a111000)))
node _atomics_legal_T_346 = asSInt(_atomics_legal_T_345)
node _atomics_legal_T_347 = eq(_atomics_legal_T_346, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_348 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_349 = cvt(_atomics_legal_T_348)
node _atomics_legal_T_350 = and(_atomics_legal_T_349, asSInt(UInt<33>(0h88000000)))
node _atomics_legal_T_351 = asSInt(_atomics_legal_T_350)
node _atomics_legal_T_352 = eq(_atomics_legal_T_351, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_353 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_354 = cvt(_atomics_legal_T_353)
node _atomics_legal_T_355 = and(_atomics_legal_T_354, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_356 = asSInt(_atomics_legal_T_355)
node _atomics_legal_T_357 = eq(_atomics_legal_T_356, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_358 = xor(s2_req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_359 = cvt(_atomics_legal_T_358)
node _atomics_legal_T_360 = and(_atomics_legal_T_359, asSInt(UInt<33>(0h80000000)))
node _atomics_legal_T_361 = asSInt(_atomics_legal_T_360)
node _atomics_legal_T_362 = eq(_atomics_legal_T_361, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_363 = or(_atomics_legal_T_332, _atomics_legal_T_337)
node _atomics_legal_T_364 = or(_atomics_legal_T_363, _atomics_legal_T_342)
node _atomics_legal_T_365 = or(_atomics_legal_T_364, _atomics_legal_T_347)
node _atomics_legal_T_366 = or(_atomics_legal_T_365, _atomics_legal_T_352)
node _atomics_legal_T_367 = or(_atomics_legal_T_366, _atomics_legal_T_357)
node _atomics_legal_T_368 = or(_atomics_legal_T_367, _atomics_legal_T_362)
node _atomics_legal_T_369 = and(_atomics_legal_T_327, _atomics_legal_T_368)
node _atomics_legal_T_370 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_371 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_372 = cvt(_atomics_legal_T_371)
node _atomics_legal_T_373 = and(_atomics_legal_T_372, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_374 = asSInt(_atomics_legal_T_373)
node _atomics_legal_T_375 = eq(_atomics_legal_T_374, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_376 = and(_atomics_legal_T_370, _atomics_legal_T_375)
node _atomics_legal_T_377 = or(UInt<1>(0h0), _atomics_legal_T_369)
node atomics_legal_6 = or(_atomics_legal_T_377, _atomics_legal_T_376)
wire atomics_a_6 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_6.opcode, UInt<2>(0h2)
connect atomics_a_6.param, UInt<3>(0h1)
connect atomics_a_6.size, s2_req.size
connect atomics_a_6.source, UInt<1>(0h0)
connect atomics_a_6.address, s2_req.addr
node _atomics_a_mask_sizeOH_T_18 = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_6 = bits(_atomics_a_mask_sizeOH_T_18, 1, 0)
node _atomics_a_mask_sizeOH_T_19 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_6)
node _atomics_a_mask_sizeOH_T_20 = bits(_atomics_a_mask_sizeOH_T_19, 2, 0)
node atomics_a_mask_sizeOH_6 = or(_atomics_a_mask_sizeOH_T_20, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_6 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_6 = bits(atomics_a_mask_sizeOH_6, 2, 2)
node atomics_a_mask_sub_sub_bit_6 = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_6 = eq(atomics_a_mask_sub_sub_bit_6, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_6 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_6)
node _atomics_a_mask_sub_sub_acc_T_12 = and(atomics_a_mask_sub_sub_size_6, atomics_a_mask_sub_sub_0_2_6)
node atomics_a_mask_sub_sub_0_1_6 = or(atomics_a_mask_sub_sub_sub_0_1_6, _atomics_a_mask_sub_sub_acc_T_12)
node atomics_a_mask_sub_sub_1_2_6 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_6)
node _atomics_a_mask_sub_sub_acc_T_13 = and(atomics_a_mask_sub_sub_size_6, atomics_a_mask_sub_sub_1_2_6)
node atomics_a_mask_sub_sub_1_1_6 = or(atomics_a_mask_sub_sub_sub_0_1_6, _atomics_a_mask_sub_sub_acc_T_13)
node atomics_a_mask_sub_size_6 = bits(atomics_a_mask_sizeOH_6, 1, 1)
node atomics_a_mask_sub_bit_6 = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit_6 = eq(atomics_a_mask_sub_bit_6, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_6 = and(atomics_a_mask_sub_sub_0_2_6, atomics_a_mask_sub_nbit_6)
node _atomics_a_mask_sub_acc_T_24 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_0_2_6)
node atomics_a_mask_sub_0_1_6 = or(atomics_a_mask_sub_sub_0_1_6, _atomics_a_mask_sub_acc_T_24)
node atomics_a_mask_sub_1_2_6 = and(atomics_a_mask_sub_sub_0_2_6, atomics_a_mask_sub_bit_6)
node _atomics_a_mask_sub_acc_T_25 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_1_2_6)
node atomics_a_mask_sub_1_1_6 = or(atomics_a_mask_sub_sub_0_1_6, _atomics_a_mask_sub_acc_T_25)
node atomics_a_mask_sub_2_2_6 = and(atomics_a_mask_sub_sub_1_2_6, atomics_a_mask_sub_nbit_6)
node _atomics_a_mask_sub_acc_T_26 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_2_2_6)
node atomics_a_mask_sub_2_1_6 = or(atomics_a_mask_sub_sub_1_1_6, _atomics_a_mask_sub_acc_T_26)
node atomics_a_mask_sub_3_2_6 = and(atomics_a_mask_sub_sub_1_2_6, atomics_a_mask_sub_bit_6)
node _atomics_a_mask_sub_acc_T_27 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_3_2_6)
node atomics_a_mask_sub_3_1_6 = or(atomics_a_mask_sub_sub_1_1_6, _atomics_a_mask_sub_acc_T_27)
node atomics_a_mask_size_6 = bits(atomics_a_mask_sizeOH_6, 0, 0)
node atomics_a_mask_bit_6 = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit_6 = eq(atomics_a_mask_bit_6, UInt<1>(0h0))
node atomics_a_mask_eq_48 = and(atomics_a_mask_sub_0_2_6, atomics_a_mask_nbit_6)
node _atomics_a_mask_acc_T_48 = and(atomics_a_mask_size_6, atomics_a_mask_eq_48)
node atomics_a_mask_acc_48 = or(atomics_a_mask_sub_0_1_6, _atomics_a_mask_acc_T_48)
node atomics_a_mask_eq_49 = and(atomics_a_mask_sub_0_2_6, atomics_a_mask_bit_6)
node _atomics_a_mask_acc_T_49 = and(atomics_a_mask_size_6, atomics_a_mask_eq_49)
node atomics_a_mask_acc_49 = or(atomics_a_mask_sub_0_1_6, _atomics_a_mask_acc_T_49)
node atomics_a_mask_eq_50 = and(atomics_a_mask_sub_1_2_6, atomics_a_mask_nbit_6)
node _atomics_a_mask_acc_T_50 = and(atomics_a_mask_size_6, atomics_a_mask_eq_50)
node atomics_a_mask_acc_50 = or(atomics_a_mask_sub_1_1_6, _atomics_a_mask_acc_T_50)
node atomics_a_mask_eq_51 = and(atomics_a_mask_sub_1_2_6, atomics_a_mask_bit_6)
node _atomics_a_mask_acc_T_51 = and(atomics_a_mask_size_6, atomics_a_mask_eq_51)
node atomics_a_mask_acc_51 = or(atomics_a_mask_sub_1_1_6, _atomics_a_mask_acc_T_51)
node atomics_a_mask_eq_52 = and(atomics_a_mask_sub_2_2_6, atomics_a_mask_nbit_6)
node _atomics_a_mask_acc_T_52 = and(atomics_a_mask_size_6, atomics_a_mask_eq_52)
node atomics_a_mask_acc_52 = or(atomics_a_mask_sub_2_1_6, _atomics_a_mask_acc_T_52)
node atomics_a_mask_eq_53 = and(atomics_a_mask_sub_2_2_6, atomics_a_mask_bit_6)
node _atomics_a_mask_acc_T_53 = and(atomics_a_mask_size_6, atomics_a_mask_eq_53)
node atomics_a_mask_acc_53 = or(atomics_a_mask_sub_2_1_6, _atomics_a_mask_acc_T_53)
node atomics_a_mask_eq_54 = and(atomics_a_mask_sub_3_2_6, atomics_a_mask_nbit_6)
node _atomics_a_mask_acc_T_54 = and(atomics_a_mask_size_6, atomics_a_mask_eq_54)
node atomics_a_mask_acc_54 = or(atomics_a_mask_sub_3_1_6, _atomics_a_mask_acc_T_54)
node atomics_a_mask_eq_55 = and(atomics_a_mask_sub_3_2_6, atomics_a_mask_bit_6)
node _atomics_a_mask_acc_T_55 = and(atomics_a_mask_size_6, atomics_a_mask_eq_55)
node atomics_a_mask_acc_55 = or(atomics_a_mask_sub_3_1_6, _atomics_a_mask_acc_T_55)
node atomics_a_mask_lo_lo_6 = cat(atomics_a_mask_acc_49, atomics_a_mask_acc_48)
node atomics_a_mask_lo_hi_6 = cat(atomics_a_mask_acc_51, atomics_a_mask_acc_50)
node atomics_a_mask_lo_6 = cat(atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6)
node atomics_a_mask_hi_lo_6 = cat(atomics_a_mask_acc_53, atomics_a_mask_acc_52)
node atomics_a_mask_hi_hi_6 = cat(atomics_a_mask_acc_55, atomics_a_mask_acc_54)
node atomics_a_mask_hi_6 = cat(atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6)
node _atomics_a_mask_T_6 = cat(atomics_a_mask_hi_6, atomics_a_mask_lo_6)
connect atomics_a_6.mask, _atomics_a_mask_T_6
connect atomics_a_6.data, pstore1_data
connect atomics_a_6.corrupt, UInt<1>(0h0)
node _atomics_legal_T_378 = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_379 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_380 = and(_atomics_legal_T_378, _atomics_legal_T_379)
node _atomics_legal_T_381 = or(UInt<1>(0h0), _atomics_legal_T_380)
node _atomics_legal_T_382 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_383 = cvt(_atomics_legal_T_382)
node _atomics_legal_T_384 = and(_atomics_legal_T_383, asSInt(UInt<33>(0h8a010000)))
node _atomics_legal_T_385 = asSInt(_atomics_legal_T_384)
node _atomics_legal_T_386 = eq(_atomics_legal_T_385, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_387 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_388 = cvt(_atomics_legal_T_387)
node _atomics_legal_T_389 = and(_atomics_legal_T_388, asSInt(UInt<33>(0h8a101000)))
node _atomics_legal_T_390 = asSInt(_atomics_legal_T_389)
node _atomics_legal_T_391 = eq(_atomics_legal_T_390, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_392 = xor(s2_req.addr, UInt<26>(0h2000000))
node _atomics_legal_T_393 = cvt(_atomics_legal_T_392)
node _atomics_legal_T_394 = and(_atomics_legal_T_393, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_395 = asSInt(_atomics_legal_T_394)
node _atomics_legal_T_396 = eq(_atomics_legal_T_395, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_397 = xor(s2_req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_398 = cvt(_atomics_legal_T_397)
node _atomics_legal_T_399 = and(_atomics_legal_T_398, asSInt(UInt<33>(0h8a111000)))
node _atomics_legal_T_400 = asSInt(_atomics_legal_T_399)
node _atomics_legal_T_401 = eq(_atomics_legal_T_400, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_402 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_403 = cvt(_atomics_legal_T_402)
node _atomics_legal_T_404 = and(_atomics_legal_T_403, asSInt(UInt<33>(0h88000000)))
node _atomics_legal_T_405 = asSInt(_atomics_legal_T_404)
node _atomics_legal_T_406 = eq(_atomics_legal_T_405, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_407 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_408 = cvt(_atomics_legal_T_407)
node _atomics_legal_T_409 = and(_atomics_legal_T_408, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_410 = asSInt(_atomics_legal_T_409)
node _atomics_legal_T_411 = eq(_atomics_legal_T_410, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_412 = xor(s2_req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_413 = cvt(_atomics_legal_T_412)
node _atomics_legal_T_414 = and(_atomics_legal_T_413, asSInt(UInt<33>(0h80000000)))
node _atomics_legal_T_415 = asSInt(_atomics_legal_T_414)
node _atomics_legal_T_416 = eq(_atomics_legal_T_415, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_417 = or(_atomics_legal_T_386, _atomics_legal_T_391)
node _atomics_legal_T_418 = or(_atomics_legal_T_417, _atomics_legal_T_396)
node _atomics_legal_T_419 = or(_atomics_legal_T_418, _atomics_legal_T_401)
node _atomics_legal_T_420 = or(_atomics_legal_T_419, _atomics_legal_T_406)
node _atomics_legal_T_421 = or(_atomics_legal_T_420, _atomics_legal_T_411)
node _atomics_legal_T_422 = or(_atomics_legal_T_421, _atomics_legal_T_416)
node _atomics_legal_T_423 = and(_atomics_legal_T_381, _atomics_legal_T_422)
node _atomics_legal_T_424 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_425 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_426 = cvt(_atomics_legal_T_425)
node _atomics_legal_T_427 = and(_atomics_legal_T_426, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_428 = asSInt(_atomics_legal_T_427)
node _atomics_legal_T_429 = eq(_atomics_legal_T_428, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_430 = and(_atomics_legal_T_424, _atomics_legal_T_429)
node _atomics_legal_T_431 = or(UInt<1>(0h0), _atomics_legal_T_423)
node atomics_legal_7 = or(_atomics_legal_T_431, _atomics_legal_T_430)
wire atomics_a_7 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_7.opcode, UInt<2>(0h2)
connect atomics_a_7.param, UInt<3>(0h2)
connect atomics_a_7.size, s2_req.size
connect atomics_a_7.source, UInt<1>(0h0)
connect atomics_a_7.address, s2_req.addr
node _atomics_a_mask_sizeOH_T_21 = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_7 = bits(_atomics_a_mask_sizeOH_T_21, 1, 0)
node _atomics_a_mask_sizeOH_T_22 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_7)
node _atomics_a_mask_sizeOH_T_23 = bits(_atomics_a_mask_sizeOH_T_22, 2, 0)
node atomics_a_mask_sizeOH_7 = or(_atomics_a_mask_sizeOH_T_23, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_7 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_7 = bits(atomics_a_mask_sizeOH_7, 2, 2)
node atomics_a_mask_sub_sub_bit_7 = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_7 = eq(atomics_a_mask_sub_sub_bit_7, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_7 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_7)
node _atomics_a_mask_sub_sub_acc_T_14 = and(atomics_a_mask_sub_sub_size_7, atomics_a_mask_sub_sub_0_2_7)
node atomics_a_mask_sub_sub_0_1_7 = or(atomics_a_mask_sub_sub_sub_0_1_7, _atomics_a_mask_sub_sub_acc_T_14)
node atomics_a_mask_sub_sub_1_2_7 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_7)
node _atomics_a_mask_sub_sub_acc_T_15 = and(atomics_a_mask_sub_sub_size_7, atomics_a_mask_sub_sub_1_2_7)
node atomics_a_mask_sub_sub_1_1_7 = or(atomics_a_mask_sub_sub_sub_0_1_7, _atomics_a_mask_sub_sub_acc_T_15)
node atomics_a_mask_sub_size_7 = bits(atomics_a_mask_sizeOH_7, 1, 1)
node atomics_a_mask_sub_bit_7 = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit_7 = eq(atomics_a_mask_sub_bit_7, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_7 = and(atomics_a_mask_sub_sub_0_2_7, atomics_a_mask_sub_nbit_7)
node _atomics_a_mask_sub_acc_T_28 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_0_2_7)
node atomics_a_mask_sub_0_1_7 = or(atomics_a_mask_sub_sub_0_1_7, _atomics_a_mask_sub_acc_T_28)
node atomics_a_mask_sub_1_2_7 = and(atomics_a_mask_sub_sub_0_2_7, atomics_a_mask_sub_bit_7)
node _atomics_a_mask_sub_acc_T_29 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_1_2_7)
node atomics_a_mask_sub_1_1_7 = or(atomics_a_mask_sub_sub_0_1_7, _atomics_a_mask_sub_acc_T_29)
node atomics_a_mask_sub_2_2_7 = and(atomics_a_mask_sub_sub_1_2_7, atomics_a_mask_sub_nbit_7)
node _atomics_a_mask_sub_acc_T_30 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_2_2_7)
node atomics_a_mask_sub_2_1_7 = or(atomics_a_mask_sub_sub_1_1_7, _atomics_a_mask_sub_acc_T_30)
node atomics_a_mask_sub_3_2_7 = and(atomics_a_mask_sub_sub_1_2_7, atomics_a_mask_sub_bit_7)
node _atomics_a_mask_sub_acc_T_31 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_3_2_7)
node atomics_a_mask_sub_3_1_7 = or(atomics_a_mask_sub_sub_1_1_7, _atomics_a_mask_sub_acc_T_31)
node atomics_a_mask_size_7 = bits(atomics_a_mask_sizeOH_7, 0, 0)
node atomics_a_mask_bit_7 = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit_7 = eq(atomics_a_mask_bit_7, UInt<1>(0h0))
node atomics_a_mask_eq_56 = and(atomics_a_mask_sub_0_2_7, atomics_a_mask_nbit_7)
node _atomics_a_mask_acc_T_56 = and(atomics_a_mask_size_7, atomics_a_mask_eq_56)
node atomics_a_mask_acc_56 = or(atomics_a_mask_sub_0_1_7, _atomics_a_mask_acc_T_56)
node atomics_a_mask_eq_57 = and(atomics_a_mask_sub_0_2_7, atomics_a_mask_bit_7)
node _atomics_a_mask_acc_T_57 = and(atomics_a_mask_size_7, atomics_a_mask_eq_57)
node atomics_a_mask_acc_57 = or(atomics_a_mask_sub_0_1_7, _atomics_a_mask_acc_T_57)
node atomics_a_mask_eq_58 = and(atomics_a_mask_sub_1_2_7, atomics_a_mask_nbit_7)
node _atomics_a_mask_acc_T_58 = and(atomics_a_mask_size_7, atomics_a_mask_eq_58)
node atomics_a_mask_acc_58 = or(atomics_a_mask_sub_1_1_7, _atomics_a_mask_acc_T_58)
node atomics_a_mask_eq_59 = and(atomics_a_mask_sub_1_2_7, atomics_a_mask_bit_7)
node _atomics_a_mask_acc_T_59 = and(atomics_a_mask_size_7, atomics_a_mask_eq_59)
node atomics_a_mask_acc_59 = or(atomics_a_mask_sub_1_1_7, _atomics_a_mask_acc_T_59)
node atomics_a_mask_eq_60 = and(atomics_a_mask_sub_2_2_7, atomics_a_mask_nbit_7)
node _atomics_a_mask_acc_T_60 = and(atomics_a_mask_size_7, atomics_a_mask_eq_60)
node atomics_a_mask_acc_60 = or(atomics_a_mask_sub_2_1_7, _atomics_a_mask_acc_T_60)
node atomics_a_mask_eq_61 = and(atomics_a_mask_sub_2_2_7, atomics_a_mask_bit_7)
node _atomics_a_mask_acc_T_61 = and(atomics_a_mask_size_7, atomics_a_mask_eq_61)
node atomics_a_mask_acc_61 = or(atomics_a_mask_sub_2_1_7, _atomics_a_mask_acc_T_61)
node atomics_a_mask_eq_62 = and(atomics_a_mask_sub_3_2_7, atomics_a_mask_nbit_7)
node _atomics_a_mask_acc_T_62 = and(atomics_a_mask_size_7, atomics_a_mask_eq_62)
node atomics_a_mask_acc_62 = or(atomics_a_mask_sub_3_1_7, _atomics_a_mask_acc_T_62)
node atomics_a_mask_eq_63 = and(atomics_a_mask_sub_3_2_7, atomics_a_mask_bit_7)
node _atomics_a_mask_acc_T_63 = and(atomics_a_mask_size_7, atomics_a_mask_eq_63)
node atomics_a_mask_acc_63 = or(atomics_a_mask_sub_3_1_7, _atomics_a_mask_acc_T_63)
node atomics_a_mask_lo_lo_7 = cat(atomics_a_mask_acc_57, atomics_a_mask_acc_56)
node atomics_a_mask_lo_hi_7 = cat(atomics_a_mask_acc_59, atomics_a_mask_acc_58)
node atomics_a_mask_lo_7 = cat(atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7)
node atomics_a_mask_hi_lo_7 = cat(atomics_a_mask_acc_61, atomics_a_mask_acc_60)
node atomics_a_mask_hi_hi_7 = cat(atomics_a_mask_acc_63, atomics_a_mask_acc_62)
node atomics_a_mask_hi_7 = cat(atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7)
node _atomics_a_mask_T_7 = cat(atomics_a_mask_hi_7, atomics_a_mask_lo_7)
connect atomics_a_7.mask, _atomics_a_mask_T_7
connect atomics_a_7.data, pstore1_data
connect atomics_a_7.corrupt, UInt<1>(0h0)
node _atomics_legal_T_432 = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_433 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_434 = and(_atomics_legal_T_432, _atomics_legal_T_433)
node _atomics_legal_T_435 = or(UInt<1>(0h0), _atomics_legal_T_434)
node _atomics_legal_T_436 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_437 = cvt(_atomics_legal_T_436)
node _atomics_legal_T_438 = and(_atomics_legal_T_437, asSInt(UInt<33>(0h8a010000)))
node _atomics_legal_T_439 = asSInt(_atomics_legal_T_438)
node _atomics_legal_T_440 = eq(_atomics_legal_T_439, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_441 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_442 = cvt(_atomics_legal_T_441)
node _atomics_legal_T_443 = and(_atomics_legal_T_442, asSInt(UInt<33>(0h8a101000)))
node _atomics_legal_T_444 = asSInt(_atomics_legal_T_443)
node _atomics_legal_T_445 = eq(_atomics_legal_T_444, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_446 = xor(s2_req.addr, UInt<26>(0h2000000))
node _atomics_legal_T_447 = cvt(_atomics_legal_T_446)
node _atomics_legal_T_448 = and(_atomics_legal_T_447, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_449 = asSInt(_atomics_legal_T_448)
node _atomics_legal_T_450 = eq(_atomics_legal_T_449, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_451 = xor(s2_req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_452 = cvt(_atomics_legal_T_451)
node _atomics_legal_T_453 = and(_atomics_legal_T_452, asSInt(UInt<33>(0h8a111000)))
node _atomics_legal_T_454 = asSInt(_atomics_legal_T_453)
node _atomics_legal_T_455 = eq(_atomics_legal_T_454, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_456 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_457 = cvt(_atomics_legal_T_456)
node _atomics_legal_T_458 = and(_atomics_legal_T_457, asSInt(UInt<33>(0h88000000)))
node _atomics_legal_T_459 = asSInt(_atomics_legal_T_458)
node _atomics_legal_T_460 = eq(_atomics_legal_T_459, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_461 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_462 = cvt(_atomics_legal_T_461)
node _atomics_legal_T_463 = and(_atomics_legal_T_462, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_464 = asSInt(_atomics_legal_T_463)
node _atomics_legal_T_465 = eq(_atomics_legal_T_464, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_466 = xor(s2_req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_467 = cvt(_atomics_legal_T_466)
node _atomics_legal_T_468 = and(_atomics_legal_T_467, asSInt(UInt<33>(0h80000000)))
node _atomics_legal_T_469 = asSInt(_atomics_legal_T_468)
node _atomics_legal_T_470 = eq(_atomics_legal_T_469, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_471 = or(_atomics_legal_T_440, _atomics_legal_T_445)
node _atomics_legal_T_472 = or(_atomics_legal_T_471, _atomics_legal_T_450)
node _atomics_legal_T_473 = or(_atomics_legal_T_472, _atomics_legal_T_455)
node _atomics_legal_T_474 = or(_atomics_legal_T_473, _atomics_legal_T_460)
node _atomics_legal_T_475 = or(_atomics_legal_T_474, _atomics_legal_T_465)
node _atomics_legal_T_476 = or(_atomics_legal_T_475, _atomics_legal_T_470)
node _atomics_legal_T_477 = and(_atomics_legal_T_435, _atomics_legal_T_476)
node _atomics_legal_T_478 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_479 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_480 = cvt(_atomics_legal_T_479)
node _atomics_legal_T_481 = and(_atomics_legal_T_480, asSInt(UInt<33>(0h8a110000)))
node _atomics_legal_T_482 = asSInt(_atomics_legal_T_481)
node _atomics_legal_T_483 = eq(_atomics_legal_T_482, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_484 = and(_atomics_legal_T_478, _atomics_legal_T_483)
node _atomics_legal_T_485 = or(UInt<1>(0h0), _atomics_legal_T_477)
node atomics_legal_8 = or(_atomics_legal_T_485, _atomics_legal_T_484)
wire atomics_a_8 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_8.opcode, UInt<2>(0h2)
connect atomics_a_8.param, UInt<3>(0h3)
connect atomics_a_8.size, s2_req.size
connect atomics_a_8.source, UInt<1>(0h0)
connect atomics_a_8.address, s2_req.addr
node _atomics_a_mask_sizeOH_T_24 = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_8 = bits(_atomics_a_mask_sizeOH_T_24, 1, 0)
node _atomics_a_mask_sizeOH_T_25 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_8)
node _atomics_a_mask_sizeOH_T_26 = bits(_atomics_a_mask_sizeOH_T_25, 2, 0)
node atomics_a_mask_sizeOH_8 = or(_atomics_a_mask_sizeOH_T_26, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_8 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_8 = bits(atomics_a_mask_sizeOH_8, 2, 2)
node atomics_a_mask_sub_sub_bit_8 = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_8 = eq(atomics_a_mask_sub_sub_bit_8, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_8 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_8)
node _atomics_a_mask_sub_sub_acc_T_16 = and(atomics_a_mask_sub_sub_size_8, atomics_a_mask_sub_sub_0_2_8)
node atomics_a_mask_sub_sub_0_1_8 = or(atomics_a_mask_sub_sub_sub_0_1_8, _atomics_a_mask_sub_sub_acc_T_16)
node atomics_a_mask_sub_sub_1_2_8 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_8)
node _atomics_a_mask_sub_sub_acc_T_17 = and(atomics_a_mask_sub_sub_size_8, atomics_a_mask_sub_sub_1_2_8)
node atomics_a_mask_sub_sub_1_1_8 = or(atomics_a_mask_sub_sub_sub_0_1_8, _atomics_a_mask_sub_sub_acc_T_17)
node atomics_a_mask_sub_size_8 = bits(atomics_a_mask_sizeOH_8, 1, 1)
node atomics_a_mask_sub_bit_8 = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit_8 = eq(atomics_a_mask_sub_bit_8, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_8 = and(atomics_a_mask_sub_sub_0_2_8, atomics_a_mask_sub_nbit_8)
node _atomics_a_mask_sub_acc_T_32 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_0_2_8)
node atomics_a_mask_sub_0_1_8 = or(atomics_a_mask_sub_sub_0_1_8, _atomics_a_mask_sub_acc_T_32)
node atomics_a_mask_sub_1_2_8 = and(atomics_a_mask_sub_sub_0_2_8, atomics_a_mask_sub_bit_8)
node _atomics_a_mask_sub_acc_T_33 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_1_2_8)
node atomics_a_mask_sub_1_1_8 = or(atomics_a_mask_sub_sub_0_1_8, _atomics_a_mask_sub_acc_T_33)
node atomics_a_mask_sub_2_2_8 = and(atomics_a_mask_sub_sub_1_2_8, atomics_a_mask_sub_nbit_8)
node _atomics_a_mask_sub_acc_T_34 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_2_2_8)
node atomics_a_mask_sub_2_1_8 = or(atomics_a_mask_sub_sub_1_1_8, _atomics_a_mask_sub_acc_T_34)
node atomics_a_mask_sub_3_2_8 = and(atomics_a_mask_sub_sub_1_2_8, atomics_a_mask_sub_bit_8)
node _atomics_a_mask_sub_acc_T_35 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_3_2_8)
node atomics_a_mask_sub_3_1_8 = or(atomics_a_mask_sub_sub_1_1_8, _atomics_a_mask_sub_acc_T_35)
node atomics_a_mask_size_8 = bits(atomics_a_mask_sizeOH_8, 0, 0)
node atomics_a_mask_bit_8 = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit_8 = eq(atomics_a_mask_bit_8, UInt<1>(0h0))
node atomics_a_mask_eq_64 = and(atomics_a_mask_sub_0_2_8, atomics_a_mask_nbit_8)
node _atomics_a_mask_acc_T_64 = and(atomics_a_mask_size_8, atomics_a_mask_eq_64)
node atomics_a_mask_acc_64 = or(atomics_a_mask_sub_0_1_8, _atomics_a_mask_acc_T_64)
node atomics_a_mask_eq_65 = and(atomics_a_mask_sub_0_2_8, atomics_a_mask_bit_8)
node _atomics_a_mask_acc_T_65 = and(atomics_a_mask_size_8, atomics_a_mask_eq_65)
node atomics_a_mask_acc_65 = or(atomics_a_mask_sub_0_1_8, _atomics_a_mask_acc_T_65)
node atomics_a_mask_eq_66 = and(atomics_a_mask_sub_1_2_8, atomics_a_mask_nbit_8)
node _atomics_a_mask_acc_T_66 = and(atomics_a_mask_size_8, atomics_a_mask_eq_66)
node atomics_a_mask_acc_66 = or(atomics_a_mask_sub_1_1_8, _atomics_a_mask_acc_T_66)
node atomics_a_mask_eq_67 = and(atomics_a_mask_sub_1_2_8, atomics_a_mask_bit_8)
node _atomics_a_mask_acc_T_67 = and(atomics_a_mask_size_8, atomics_a_mask_eq_67)
node atomics_a_mask_acc_67 = or(atomics_a_mask_sub_1_1_8, _atomics_a_mask_acc_T_67)
node atomics_a_mask_eq_68 = and(atomics_a_mask_sub_2_2_8, atomics_a_mask_nbit_8)
node _atomics_a_mask_acc_T_68 = and(atomics_a_mask_size_8, atomics_a_mask_eq_68)
node atomics_a_mask_acc_68 = or(atomics_a_mask_sub_2_1_8, _atomics_a_mask_acc_T_68)
node atomics_a_mask_eq_69 = and(atomics_a_mask_sub_2_2_8, atomics_a_mask_bit_8)
node _atomics_a_mask_acc_T_69 = and(atomics_a_mask_size_8, atomics_a_mask_eq_69)
node atomics_a_mask_acc_69 = or(atomics_a_mask_sub_2_1_8, _atomics_a_mask_acc_T_69)
node atomics_a_mask_eq_70 = and(atomics_a_mask_sub_3_2_8, atomics_a_mask_nbit_8)
node _atomics_a_mask_acc_T_70 = and(atomics_a_mask_size_8, atomics_a_mask_eq_70)
node atomics_a_mask_acc_70 = or(atomics_a_mask_sub_3_1_8, _atomics_a_mask_acc_T_70)
node atomics_a_mask_eq_71 = and(atomics_a_mask_sub_3_2_8, atomics_a_mask_bit_8)
node _atomics_a_mask_acc_T_71 = and(atomics_a_mask_size_8, atomics_a_mask_eq_71)
node atomics_a_mask_acc_71 = or(atomics_a_mask_sub_3_1_8, _atomics_a_mask_acc_T_71)
node atomics_a_mask_lo_lo_8 = cat(atomics_a_mask_acc_65, atomics_a_mask_acc_64)
node atomics_a_mask_lo_hi_8 = cat(atomics_a_mask_acc_67, atomics_a_mask_acc_66)
node atomics_a_mask_lo_8 = cat(atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8)
node atomics_a_mask_hi_lo_8 = cat(atomics_a_mask_acc_69, atomics_a_mask_acc_68)
node atomics_a_mask_hi_hi_8 = cat(atomics_a_mask_acc_71, atomics_a_mask_acc_70)
node atomics_a_mask_hi_8 = cat(atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8)
node _atomics_a_mask_T_8 = cat(atomics_a_mask_hi_8, atomics_a_mask_lo_8)
connect atomics_a_8.mask, _atomics_a_mask_T_8
connect atomics_a_8.data, pstore1_data
connect atomics_a_8.corrupt, UInt<1>(0h0)
node _atomics_T = eq(UInt<3>(0h4), s2_req.cmd)
node _atomics_T_1 = mux(_atomics_T, atomics_a, _atomics_WIRE_1)
node _atomics_T_2 = eq(UInt<4>(0h9), s2_req.cmd)
node _atomics_T_3 = mux(_atomics_T_2, atomics_a_1, _atomics_T_1)
node _atomics_T_4 = eq(UInt<4>(0ha), s2_req.cmd)
node _atomics_T_5 = mux(_atomics_T_4, atomics_a_2, _atomics_T_3)
node _atomics_T_6 = eq(UInt<4>(0hb), s2_req.cmd)
node _atomics_T_7 = mux(_atomics_T_6, atomics_a_3, _atomics_T_5)
node _atomics_T_8 = eq(UInt<4>(0h8), s2_req.cmd)
node _atomics_T_9 = mux(_atomics_T_8, atomics_a_4, _atomics_T_7)
node _atomics_T_10 = eq(UInt<4>(0hc), s2_req.cmd)
node _atomics_T_11 = mux(_atomics_T_10, atomics_a_5, _atomics_T_9)
node _atomics_T_12 = eq(UInt<4>(0hd), s2_req.cmd)
node _atomics_T_13 = mux(_atomics_T_12, atomics_a_6, _atomics_T_11)
node _atomics_T_14 = eq(UInt<4>(0he), s2_req.cmd)
node _atomics_T_15 = mux(_atomics_T_14, atomics_a_7, _atomics_T_13)
node _atomics_T_16 = eq(UInt<4>(0hf), s2_req.cmd)
node atomics = mux(_atomics_T_16, atomics_a_8, _atomics_T_15)
node _tl_out_a_valid_T = eq(io.cpu.s2_kill, UInt<1>(0h0))
node _tl_out_a_valid_T_1 = xor(s2_req.addr, release_ack_addr)
node _tl_out_a_valid_T_2 = bits(_tl_out_a_valid_T_1, 20, 6)
node _tl_out_a_valid_T_3 = eq(_tl_out_a_valid_T_2, UInt<1>(0h0))
node _tl_out_a_valid_T_4 = and(release_ack_wait, _tl_out_a_valid_T_3)
node _tl_out_a_valid_T_5 = eq(_tl_out_a_valid_T_4, UInt<1>(0h0))
node _tl_out_a_valid_T_6 = and(s2_valid_cached_miss, _tl_out_a_valid_T_5)
node _tl_out_a_valid_T_7 = eq(release_ack_wait, UInt<1>(0h0))
node _tl_out_a_valid_T_8 = and(UInt<1>(0h0), _tl_out_a_valid_T_7)
node _tl_out_a_valid_T_9 = and(_tl_out_a_valid_T_8, UInt<1>(0h1))
node _tl_out_a_valid_T_10 = eq(s2_victim_dirty, UInt<1>(0h0))
node _tl_out_a_valid_T_11 = or(_tl_out_a_valid_T_9, _tl_out_a_valid_T_10)
node _tl_out_a_valid_T_12 = and(_tl_out_a_valid_T_6, _tl_out_a_valid_T_11)
node _tl_out_a_valid_T_13 = or(s2_valid_uncached_pending, _tl_out_a_valid_T_12)
node _tl_out_a_valid_T_14 = and(_tl_out_a_valid_T, _tl_out_a_valid_T_13)
connect tl_out_a.valid, _tl_out_a_valid_T_14
node _tl_out_a_bits_T = eq(s2_uncached, UInt<1>(0h0))
node _tl_out_a_bits_T_1 = shr(s2_req.addr, 6)
node _tl_out_a_bits_T_2 = shl(_tl_out_a_bits_T_1, 6)
node _tl_out_a_bits_legal_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _tl_out_a_bits_legal_T_1 = xor(_tl_out_a_bits_T_2, UInt<1>(0h0))
node _tl_out_a_bits_legal_T_2 = cvt(_tl_out_a_bits_legal_T_1)
node _tl_out_a_bits_legal_T_3 = and(_tl_out_a_bits_legal_T_2, asSInt(UInt<33>(0h8e000000)))
node _tl_out_a_bits_legal_T_4 = asSInt(_tl_out_a_bits_legal_T_3)
node _tl_out_a_bits_legal_T_5 = eq(_tl_out_a_bits_legal_T_4, asSInt(UInt<1>(0h0)))
node _tl_out_a_bits_legal_T_6 = xor(_tl_out_a_bits_T_2, UInt<21>(0h100000))
node _tl_out_a_bits_legal_T_7 = cvt(_tl_out_a_bits_legal_T_6)
node _tl_out_a_bits_legal_T_8 = and(_tl_out_a_bits_legal_T_7, asSInt(UInt<33>(0h8e101000)))
node _tl_out_a_bits_legal_T_9 = asSInt(_tl_out_a_bits_legal_T_8)
node _tl_out_a_bits_legal_T_10 = eq(_tl_out_a_bits_legal_T_9, asSInt(UInt<1>(0h0)))
node _tl_out_a_bits_legal_T_11 = xor(_tl_out_a_bits_T_2, UInt<26>(0h2000000))
node _tl_out_a_bits_legal_T_12 = cvt(_tl_out_a_bits_legal_T_11)
node _tl_out_a_bits_legal_T_13 = and(_tl_out_a_bits_legal_T_12, asSInt(UInt<33>(0h8e100000)))
node _tl_out_a_bits_legal_T_14 = asSInt(_tl_out_a_bits_legal_T_13)
node _tl_out_a_bits_legal_T_15 = eq(_tl_out_a_bits_legal_T_14, asSInt(UInt<1>(0h0)))
node _tl_out_a_bits_legal_T_16 = xor(_tl_out_a_bits_T_2, UInt<26>(0h2000000))
node _tl_out_a_bits_legal_T_17 = cvt(_tl_out_a_bits_legal_T_16)
node _tl_out_a_bits_legal_T_18 = and(_tl_out_a_bits_legal_T_17, asSInt(UInt<33>(0h8e101000)))
node _tl_out_a_bits_legal_T_19 = asSInt(_tl_out_a_bits_legal_T_18)
node _tl_out_a_bits_legal_T_20 = eq(_tl_out_a_bits_legal_T_19, asSInt(UInt<1>(0h0)))
node _tl_out_a_bits_legal_T_21 = xor(_tl_out_a_bits_T_2, UInt<28>(0hc000000))
node _tl_out_a_bits_legal_T_22 = cvt(_tl_out_a_bits_legal_T_21)
node _tl_out_a_bits_legal_T_23 = and(_tl_out_a_bits_legal_T_22, asSInt(UInt<33>(0h8c000000)))
node _tl_out_a_bits_legal_T_24 = asSInt(_tl_out_a_bits_legal_T_23)
node _tl_out_a_bits_legal_T_25 = eq(_tl_out_a_bits_legal_T_24, asSInt(UInt<1>(0h0)))
node _tl_out_a_bits_legal_T_26 = or(_tl_out_a_bits_legal_T_5, _tl_out_a_bits_legal_T_10)
node _tl_out_a_bits_legal_T_27 = or(_tl_out_a_bits_legal_T_26, _tl_out_a_bits_legal_T_15)
node _tl_out_a_bits_legal_T_28 = or(_tl_out_a_bits_legal_T_27, _tl_out_a_bits_legal_T_20)
node _tl_out_a_bits_legal_T_29 = or(_tl_out_a_bits_legal_T_28, _tl_out_a_bits_legal_T_25)
node _tl_out_a_bits_legal_T_30 = and(_tl_out_a_bits_legal_T, _tl_out_a_bits_legal_T_29)
node _tl_out_a_bits_legal_T_31 = eq(UInt<3>(0h6), UInt<3>(0h6))
node _tl_out_a_bits_legal_T_32 = or(UInt<1>(0h0), _tl_out_a_bits_legal_T_31)
node _tl_out_a_bits_legal_T_33 = xor(_tl_out_a_bits_T_2, UInt<28>(0h8000000))
node _tl_out_a_bits_legal_T_34 = cvt(_tl_out_a_bits_legal_T_33)
node _tl_out_a_bits_legal_T_35 = and(_tl_out_a_bits_legal_T_34, asSInt(UInt<33>(0h8e100000)))
node _tl_out_a_bits_legal_T_36 = asSInt(_tl_out_a_bits_legal_T_35)
node _tl_out_a_bits_legal_T_37 = eq(_tl_out_a_bits_legal_T_36, asSInt(UInt<1>(0h0)))
node _tl_out_a_bits_legal_T_38 = xor(_tl_out_a_bits_T_2, UInt<32>(0h80000000))
node _tl_out_a_bits_legal_T_39 = cvt(_tl_out_a_bits_legal_T_38)
node _tl_out_a_bits_legal_T_40 = and(_tl_out_a_bits_legal_T_39, asSInt(UInt<33>(0h80000000)))
node _tl_out_a_bits_legal_T_41 = asSInt(_tl_out_a_bits_legal_T_40)
node _tl_out_a_bits_legal_T_42 = eq(_tl_out_a_bits_legal_T_41, asSInt(UInt<1>(0h0)))
node _tl_out_a_bits_legal_T_43 = or(_tl_out_a_bits_legal_T_37, _tl_out_a_bits_legal_T_42)
node _tl_out_a_bits_legal_T_44 = and(_tl_out_a_bits_legal_T_32, _tl_out_a_bits_legal_T_43)
node _tl_out_a_bits_legal_T_45 = or(UInt<1>(0h0), _tl_out_a_bits_legal_T_30)
node tl_out_a_bits_legal = or(_tl_out_a_bits_legal_T_45, _tl_out_a_bits_legal_T_44)
wire tl_out_a_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect tl_out_a_bits_a.opcode, UInt<3>(0h6)
connect tl_out_a_bits_a.param, s2_grow_param
connect tl_out_a_bits_a.size, UInt<3>(0h6)
connect tl_out_a_bits_a.source, UInt<1>(0h0)
connect tl_out_a_bits_a.address, _tl_out_a_bits_T_2
node _tl_out_a_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<3>(0h0))
node tl_out_a_bits_a_mask_sizeOH_shiftAmount = bits(_tl_out_a_bits_a_mask_sizeOH_T, 1, 0)
node _tl_out_a_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), tl_out_a_bits_a_mask_sizeOH_shiftAmount)
node _tl_out_a_bits_a_mask_sizeOH_T_2 = bits(_tl_out_a_bits_a_mask_sizeOH_T_1, 2, 0)
node tl_out_a_bits_a_mask_sizeOH = or(_tl_out_a_bits_a_mask_sizeOH_T_2, UInt<1>(0h1))
node tl_out_a_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<2>(0h3))
node tl_out_a_bits_a_mask_sub_sub_size = bits(tl_out_a_bits_a_mask_sizeOH, 2, 2)
node tl_out_a_bits_a_mask_sub_sub_bit = bits(_tl_out_a_bits_T_2, 2, 2)
node tl_out_a_bits_a_mask_sub_sub_nbit = eq(tl_out_a_bits_a_mask_sub_sub_bit, UInt<1>(0h0))
node tl_out_a_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), tl_out_a_bits_a_mask_sub_sub_nbit)
node _tl_out_a_bits_a_mask_sub_sub_acc_T = and(tl_out_a_bits_a_mask_sub_sub_size, tl_out_a_bits_a_mask_sub_sub_0_2)
node tl_out_a_bits_a_mask_sub_sub_0_1 = or(tl_out_a_bits_a_mask_sub_sub_sub_0_1, _tl_out_a_bits_a_mask_sub_sub_acc_T)
node tl_out_a_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), tl_out_a_bits_a_mask_sub_sub_bit)
node _tl_out_a_bits_a_mask_sub_sub_acc_T_1 = and(tl_out_a_bits_a_mask_sub_sub_size, tl_out_a_bits_a_mask_sub_sub_1_2)
node tl_out_a_bits_a_mask_sub_sub_1_1 = or(tl_out_a_bits_a_mask_sub_sub_sub_0_1, _tl_out_a_bits_a_mask_sub_sub_acc_T_1)
node tl_out_a_bits_a_mask_sub_size = bits(tl_out_a_bits_a_mask_sizeOH, 1, 1)
node tl_out_a_bits_a_mask_sub_bit = bits(_tl_out_a_bits_T_2, 1, 1)
node tl_out_a_bits_a_mask_sub_nbit = eq(tl_out_a_bits_a_mask_sub_bit, UInt<1>(0h0))
node tl_out_a_bits_a_mask_sub_0_2 = and(tl_out_a_bits_a_mask_sub_sub_0_2, tl_out_a_bits_a_mask_sub_nbit)
node _tl_out_a_bits_a_mask_sub_acc_T = and(tl_out_a_bits_a_mask_sub_size, tl_out_a_bits_a_mask_sub_0_2)
node tl_out_a_bits_a_mask_sub_0_1 = or(tl_out_a_bits_a_mask_sub_sub_0_1, _tl_out_a_bits_a_mask_sub_acc_T)
node tl_out_a_bits_a_mask_sub_1_2 = and(tl_out_a_bits_a_mask_sub_sub_0_2, tl_out_a_bits_a_mask_sub_bit)
node _tl_out_a_bits_a_mask_sub_acc_T_1 = and(tl_out_a_bits_a_mask_sub_size, tl_out_a_bits_a_mask_sub_1_2)
node tl_out_a_bits_a_mask_sub_1_1 = or(tl_out_a_bits_a_mask_sub_sub_0_1, _tl_out_a_bits_a_mask_sub_acc_T_1)
node tl_out_a_bits_a_mask_sub_2_2 = and(tl_out_a_bits_a_mask_sub_sub_1_2, tl_out_a_bits_a_mask_sub_nbit)
node _tl_out_a_bits_a_mask_sub_acc_T_2 = and(tl_out_a_bits_a_mask_sub_size, tl_out_a_bits_a_mask_sub_2_2)
node tl_out_a_bits_a_mask_sub_2_1 = or(tl_out_a_bits_a_mask_sub_sub_1_1, _tl_out_a_bits_a_mask_sub_acc_T_2)
node tl_out_a_bits_a_mask_sub_3_2 = and(tl_out_a_bits_a_mask_sub_sub_1_2, tl_out_a_bits_a_mask_sub_bit)
node _tl_out_a_bits_a_mask_sub_acc_T_3 = and(tl_out_a_bits_a_mask_sub_size, tl_out_a_bits_a_mask_sub_3_2)
node tl_out_a_bits_a_mask_sub_3_1 = or(tl_out_a_bits_a_mask_sub_sub_1_1, _tl_out_a_bits_a_mask_sub_acc_T_3)
node tl_out_a_bits_a_mask_size = bits(tl_out_a_bits_a_mask_sizeOH, 0, 0)
node tl_out_a_bits_a_mask_bit = bits(_tl_out_a_bits_T_2, 0, 0)
node tl_out_a_bits_a_mask_nbit = eq(tl_out_a_bits_a_mask_bit, UInt<1>(0h0))
node tl_out_a_bits_a_mask_eq = and(tl_out_a_bits_a_mask_sub_0_2, tl_out_a_bits_a_mask_nbit)
node _tl_out_a_bits_a_mask_acc_T = and(tl_out_a_bits_a_mask_size, tl_out_a_bits_a_mask_eq)
node tl_out_a_bits_a_mask_acc = or(tl_out_a_bits_a_mask_sub_0_1, _tl_out_a_bits_a_mask_acc_T)
node tl_out_a_bits_a_mask_eq_1 = and(tl_out_a_bits_a_mask_sub_0_2, tl_out_a_bits_a_mask_bit)
node _tl_out_a_bits_a_mask_acc_T_1 = and(tl_out_a_bits_a_mask_size, tl_out_a_bits_a_mask_eq_1)
node tl_out_a_bits_a_mask_acc_1 = or(tl_out_a_bits_a_mask_sub_0_1, _tl_out_a_bits_a_mask_acc_T_1)
node tl_out_a_bits_a_mask_eq_2 = and(tl_out_a_bits_a_mask_sub_1_2, tl_out_a_bits_a_mask_nbit)
node _tl_out_a_bits_a_mask_acc_T_2 = and(tl_out_a_bits_a_mask_size, tl_out_a_bits_a_mask_eq_2)
node tl_out_a_bits_a_mask_acc_2 = or(tl_out_a_bits_a_mask_sub_1_1, _tl_out_a_bits_a_mask_acc_T_2)
node tl_out_a_bits_a_mask_eq_3 = and(tl_out_a_bits_a_mask_sub_1_2, tl_out_a_bits_a_mask_bit)
node _tl_out_a_bits_a_mask_acc_T_3 = and(tl_out_a_bits_a_mask_size, tl_out_a_bits_a_mask_eq_3)
node tl_out_a_bits_a_mask_acc_3 = or(tl_out_a_bits_a_mask_sub_1_1, _tl_out_a_bits_a_mask_acc_T_3)
node tl_out_a_bits_a_mask_eq_4 = and(tl_out_a_bits_a_mask_sub_2_2, tl_out_a_bits_a_mask_nbit)
node _tl_out_a_bits_a_mask_acc_T_4 = and(tl_out_a_bits_a_mask_size, tl_out_a_bits_a_mask_eq_4)
node tl_out_a_bits_a_mask_acc_4 = or(tl_out_a_bits_a_mask_sub_2_1, _tl_out_a_bits_a_mask_acc_T_4)
node tl_out_a_bits_a_mask_eq_5 = and(tl_out_a_bits_a_mask_sub_2_2, tl_out_a_bits_a_mask_bit)
node _tl_out_a_bits_a_mask_acc_T_5 = and(tl_out_a_bits_a_mask_size, tl_out_a_bits_a_mask_eq_5)
node tl_out_a_bits_a_mask_acc_5 = or(tl_out_a_bits_a_mask_sub_2_1, _tl_out_a_bits_a_mask_acc_T_5)
node tl_out_a_bits_a_mask_eq_6 = and(tl_out_a_bits_a_mask_sub_3_2, tl_out_a_bits_a_mask_nbit)
node _tl_out_a_bits_a_mask_acc_T_6 = and(tl_out_a_bits_a_mask_size, tl_out_a_bits_a_mask_eq_6)
node tl_out_a_bits_a_mask_acc_6 = or(tl_out_a_bits_a_mask_sub_3_1, _tl_out_a_bits_a_mask_acc_T_6)
node tl_out_a_bits_a_mask_eq_7 = and(tl_out_a_bits_a_mask_sub_3_2, tl_out_a_bits_a_mask_bit)
node _tl_out_a_bits_a_mask_acc_T_7 = and(tl_out_a_bits_a_mask_size, tl_out_a_bits_a_mask_eq_7)
node tl_out_a_bits_a_mask_acc_7 = or(tl_out_a_bits_a_mask_sub_3_1, _tl_out_a_bits_a_mask_acc_T_7)
node tl_out_a_bits_a_mask_lo_lo = cat(tl_out_a_bits_a_mask_acc_1, tl_out_a_bits_a_mask_acc)
node tl_out_a_bits_a_mask_lo_hi = cat(tl_out_a_bits_a_mask_acc_3, tl_out_a_bits_a_mask_acc_2)
node tl_out_a_bits_a_mask_lo = cat(tl_out_a_bits_a_mask_lo_hi, tl_out_a_bits_a_mask_lo_lo)
node tl_out_a_bits_a_mask_hi_lo = cat(tl_out_a_bits_a_mask_acc_5, tl_out_a_bits_a_mask_acc_4)
node tl_out_a_bits_a_mask_hi_hi = cat(tl_out_a_bits_a_mask_acc_7, tl_out_a_bits_a_mask_acc_6)
node tl_out_a_bits_a_mask_hi = cat(tl_out_a_bits_a_mask_hi_hi, tl_out_a_bits_a_mask_hi_lo)
node _tl_out_a_bits_a_mask_T = cat(tl_out_a_bits_a_mask_hi, tl_out_a_bits_a_mask_lo)
connect tl_out_a_bits_a.mask, _tl_out_a_bits_a_mask_T
invalidate tl_out_a_bits_a.data
connect tl_out_a_bits_a.corrupt, UInt<1>(0h0)
node _tl_out_a_bits_T_3 = eq(s2_write, UInt<1>(0h0))
node _tl_out_a_bits_T_4 = eq(s2_req.cmd, UInt<5>(0h11))
node _tl_out_a_bits_T_5 = eq(s2_read, UInt<1>(0h0))
node _tl_out_a_bits_T_6 = mux(_tl_out_a_bits_T_5, put, atomics)
node _tl_out_a_bits_T_7 = mux(_tl_out_a_bits_T_4, putpartial, _tl_out_a_bits_T_6)
node _tl_out_a_bits_T_8 = mux(_tl_out_a_bits_T_3, get, _tl_out_a_bits_T_7)
node _tl_out_a_bits_T_9 = mux(_tl_out_a_bits_T, tl_out_a_bits_a, _tl_out_a_bits_T_8)
connect tl_out_a.bits, _tl_out_a_bits_T_9
node a_sel = shr(UInt<1>(0h1), 0)
node _T_60 = and(tl_out_a.ready, tl_out_a.valid)
when _T_60 :
when s2_uncached :
node _T_61 = bits(a_sel, 0, 0)
when _T_61 :
connect uncachedInFlight[0], UInt<1>(0h1)
connect uncachedReqs[0], s2_req
node _uncachedReqs_0_cmd_T = eq(s2_req.cmd, UInt<5>(0h11))
node _uncachedReqs_0_cmd_T_1 = mux(_uncachedReqs_0_cmd_T, UInt<5>(0h11), UInt<1>(0h1))
node _uncachedReqs_0_cmd_T_2 = mux(s2_write, _uncachedReqs_0_cmd_T_1, UInt<1>(0h0))
connect uncachedReqs[0].cmd, _uncachedReqs_0_cmd_T_2
else :
connect cached_grant_wait, UInt<1>(0h1)
connect refill_way, s2_victim_or_hit_way
node _T_62 = and(nodeOut.d.ready, nodeOut.d.valid)
node _r_beats1_decode_T = dshl(UInt<12>(0hfff), nodeOut.d.bits.size)
node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0)
node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1)
node r_beats1_decode = shr(_r_beats1_decode_T_2, 3)
node r_beats1_opdata = bits(nodeOut.d.bits.opcode, 0, 0)
node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0))
regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _r_counter1_T = sub(r_counter, UInt<1>(0h1))
node r_counter1 = tail(_r_counter1_T, 1)
node d_first = eq(r_counter, UInt<1>(0h0))
node _r_last_T = eq(r_counter, UInt<1>(0h1))
node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0))
node d_last = or(_r_last_T, _r_last_T_1)
node d_done = and(d_last, _T_62)
node _r_count_T = not(r_counter1)
node r_4 = and(r_beats1, _r_count_T)
when _T_62 :
node _r_counter_T = mux(d_first, r_beats1, r_counter1)
connect r_counter, _r_counter_T
node d_address_inc = shl(r_4, 3)
node _T_63 = eq(nodeOut.d.valid, UInt<1>(0h0))
node _T_64 = eq(nodeOut.d.bits.opcode, UInt<1>(0h1))
node _T_65 = eq(nodeOut.d.bits.opcode, UInt<1>(0h0))
node _T_66 = eq(nodeOut.d.bits.opcode, UInt<2>(0h2))
node _T_67 = or(_T_64, _T_65)
node _T_68 = or(_T_67, _T_66)
node _T_69 = or(_T_63, _T_68)
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:654 assert(!tl_out.d.valid || whole_opc.isOneOf(uncachedGrantOpcodes))\n") : printf_2
assert(clock, _T_69, UInt<1>(0h1), "") : assert_2
node d_opc = bits(nodeOut.d.bits.opcode, 1, 0)
wire data_plaInput : UInt<2>
node data_invInputs = not(data_plaInput)
wire data_plaOutput : UInt<1>
node data_andMatrixOutputs_andMatrixInput_0 = bits(data_plaInput, 0, 0)
node data_andMatrixOutputs_andMatrixInput_1 = bits(data_invInputs, 1, 1)
node _data_andMatrixOutputs_T = cat(data_andMatrixOutputs_andMatrixInput_0, data_andMatrixOutputs_andMatrixInput_1)
node data_andMatrixOutputs_0_2 = andr(_data_andMatrixOutputs_T)
node data_orMatrixOutputs = orr(data_andMatrixOutputs_0_2)
node data_invMatrixOutputs = bits(data_orMatrixOutputs, 0, 0)
connect data_plaOutput, data_invMatrixOutputs
connect data_plaInput, d_opc
node grantIsUncachedData = bits(data_plaOutput, 0, 0)
node _tl_d_data_encoded_T_9 = bits(io.ptw.customCSRs.csrs[0].value, 9, 9)
node _tl_d_data_encoded_T_10 = eq(_tl_d_data_encoded_T_9, UInt<1>(0h0))
node _tl_d_data_encoded_T_11 = and(nodeOut.d.bits.corrupt, _tl_d_data_encoded_T_10)
node _tl_d_data_encoded_T_12 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _tl_d_data_encoded_T_13 = and(_tl_d_data_encoded_T_11, _tl_d_data_encoded_T_12)
node _tl_d_data_encoded_T_14 = bits(nodeOut.d.bits.data, 7, 0)
node _tl_d_data_encoded_T_15 = bits(nodeOut.d.bits.data, 15, 8)
node _tl_d_data_encoded_T_16 = bits(nodeOut.d.bits.data, 23, 16)
node _tl_d_data_encoded_T_17 = bits(nodeOut.d.bits.data, 31, 24)
node _tl_d_data_encoded_T_18 = bits(nodeOut.d.bits.data, 39, 32)
node _tl_d_data_encoded_T_19 = bits(nodeOut.d.bits.data, 47, 40)
node _tl_d_data_encoded_T_20 = bits(nodeOut.d.bits.data, 55, 48)
node _tl_d_data_encoded_T_21 = bits(nodeOut.d.bits.data, 63, 56)
node tl_d_data_encoded_lo_lo_1 = cat(_tl_d_data_encoded_T_15, _tl_d_data_encoded_T_14)
node tl_d_data_encoded_lo_hi_1 = cat(_tl_d_data_encoded_T_17, _tl_d_data_encoded_T_16)
node tl_d_data_encoded_lo_1 = cat(tl_d_data_encoded_lo_hi_1, tl_d_data_encoded_lo_lo_1)
node tl_d_data_encoded_hi_lo_1 = cat(_tl_d_data_encoded_T_19, _tl_d_data_encoded_T_18)
node tl_d_data_encoded_hi_hi_1 = cat(_tl_d_data_encoded_T_21, _tl_d_data_encoded_T_20)
node tl_d_data_encoded_hi_1 = cat(tl_d_data_encoded_hi_hi_1, tl_d_data_encoded_hi_lo_1)
node _tl_d_data_encoded_T_22 = cat(tl_d_data_encoded_hi_1, tl_d_data_encoded_lo_1)
connect tl_d_data_encoded, _tl_d_data_encoded_T_22
node _grantIsCached_T = eq(d_opc, UInt<3>(0h4))
node _grantIsCached_T_1 = eq(d_opc, UInt<3>(0h5))
node grantIsCached = or(_grantIsCached_T, _grantIsCached_T_1)
node grantIsVoluntary = eq(d_opc, UInt<3>(0h6))
node grantIsRefill = eq(d_opc, UInt<3>(0h5))
regreset grantInProgress : UInt<1>, clock, reset, UInt<1>(0h0)
regreset blockProbeAfterGrantCount : UInt, clock, reset, UInt<1>(0h0)
node _T_73 = gt(blockProbeAfterGrantCount, UInt<1>(0h0))
when _T_73 :
node _blockProbeAfterGrantCount_T = sub(blockProbeAfterGrantCount, UInt<1>(0h1))
node _blockProbeAfterGrantCount_T_1 = tail(_blockProbeAfterGrantCount_T, 1)
connect blockProbeAfterGrantCount, _blockProbeAfterGrantCount_T_1
node _canAcceptCachedGrant_T = eq(release_state, UInt<4>(0h1))
node _canAcceptCachedGrant_T_1 = eq(release_state, UInt<4>(0h6))
node _canAcceptCachedGrant_T_2 = eq(release_state, UInt<4>(0h9))
node _canAcceptCachedGrant_T_3 = or(_canAcceptCachedGrant_T, _canAcceptCachedGrant_T_1)
node _canAcceptCachedGrant_T_4 = or(_canAcceptCachedGrant_T_3, _canAcceptCachedGrant_T_2)
node canAcceptCachedGrant = eq(_canAcceptCachedGrant_T_4, UInt<1>(0h0))
node _nodeOut_d_ready_T = eq(d_first, UInt<1>(0h0))
wire _nodeOut_d_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _nodeOut_d_ready_WIRE.bits.sink, UInt<3>(0h0)
connect _nodeOut_d_ready_WIRE.valid, UInt<1>(0h0)
connect _nodeOut_d_ready_WIRE.ready, UInt<1>(0h0)
wire _nodeOut_d_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _nodeOut_d_ready_WIRE_1.bits, _nodeOut_d_ready_WIRE.bits
connect _nodeOut_d_ready_WIRE_1.valid, _nodeOut_d_ready_WIRE.valid
connect _nodeOut_d_ready_WIRE_1.ready, _nodeOut_d_ready_WIRE.ready
node _nodeOut_d_ready_T_1 = or(_nodeOut_d_ready_T, _nodeOut_d_ready_WIRE_1.ready)
node _nodeOut_d_ready_T_2 = and(_nodeOut_d_ready_T_1, canAcceptCachedGrant)
node _nodeOut_d_ready_T_3 = mux(grantIsCached, _nodeOut_d_ready_T_2, UInt<1>(0h1))
connect nodeOut.d.ready, _nodeOut_d_ready_T_3
node uncachedRespIdxOH = shr(UInt<1>(0h1), 0)
node _uncachedResp_T = bits(uncachedRespIdxOH, 0, 0)
connect uncachedResp, uncachedReqs[0]
node _T_74 = and(nodeOut.d.ready, nodeOut.d.valid)
when _T_74 :
when grantIsCached :
connect grantInProgress, UInt<1>(0h1)
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(cached_grant_wait, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: A GrantData was unexpected by the dcache.\n at DCache.scala:677 assert(cached_grant_wait, \"A GrantData was unexpected by the dcache.\")\n") : printf_3
assert(clock, cached_grant_wait, UInt<1>(0h1), "") : assert_3
when d_last :
connect cached_grant_wait, UInt<1>(0h0)
connect grantInProgress, UInt<1>(0h0)
connect blockProbeAfterGrantCount, UInt<3>(0h7)
connect replace, UInt<1>(0h1)
else :
when UInt<1>(0h1) :
node _T_78 = bits(uncachedRespIdxOH, 0, 0)
node _T_79 = and(_T_78, d_last)
when _T_79 :
node _T_80 = asUInt(reset)
node _T_81 = eq(_T_80, UInt<1>(0h0))
when _T_81 :
node _T_82 = eq(uncachedInFlight[0], UInt<1>(0h0))
when _T_82 :
printf(clock, UInt<1>(0h1), "Assertion failed: An AccessAck was unexpected by the dcache.\n at DCache.scala:687 assert(f, \"An AccessAck was unexpected by the dcache.\") // TODO must handle Ack coming back on same cycle!\n") : printf_4
assert(clock, uncachedInFlight[0], UInt<1>(0h1), "") : assert_4
connect uncachedInFlight[0], UInt<1>(0h0)
when grantIsUncachedData :
node _s1_data_way_T = shl(UInt<1>(0h1), 1)
connect s1_data_way, _s1_data_way_T
connect s2_req.cmd, UInt<1>(0h0)
connect s2_req.size, uncachedResp.size
connect s2_req.signed, uncachedResp.signed
connect s2_req.tag, uncachedResp.tag
node _s2_req_addr_dontCareBits_T = shr(s1_paddr, 3)
node s2_req_addr_dontCareBits = shl(_s2_req_addr_dontCareBits_T, 3)
node _s2_req_addr_T = bits(uncachedResp.addr, 2, 0)
node _s2_req_addr_T_1 = or(s2_req_addr_dontCareBits, _s2_req_addr_T)
connect s2_req.addr, _s2_req_addr_T_1
connect s2_uncached_resp_addr, uncachedResp.addr
else :
when grantIsVoluntary :
node _T_83 = asUInt(reset)
node _T_84 = eq(_T_83, UInt<1>(0h0))
when _T_84 :
node _T_85 = eq(release_ack_wait, UInt<1>(0h0))
when _T_85 :
printf(clock, UInt<1>(0h1), "Assertion failed: A ReleaseAck was unexpected by the dcache.\n at DCache.scala:708 assert(release_ack_wait, \"A ReleaseAck was unexpected by the dcache.\") // TODO should handle Ack coming back on same cycle!\n") : printf_5
assert(clock, release_ack_wait, UInt<1>(0h1), "") : assert_5
connect release_ack_wait, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_1.bits.sink, UInt<3>(0h0)
connect _WIRE_1.valid, UInt<1>(0h0)
connect _WIRE_1.ready, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_2.bits, _WIRE_1.bits
connect _WIRE_2.valid, _WIRE_1.valid
connect _WIRE_2.ready, _WIRE_1.ready
node _T_86 = and(nodeOut.d.valid, d_first)
node _T_87 = and(_T_86, grantIsCached)
node _T_88 = and(_T_87, canAcceptCachedGrant)
connect _WIRE_2.valid, _T_88
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_3.bits.sink, UInt<3>(0h0)
connect _WIRE_3.valid, UInt<1>(0h0)
connect _WIRE_3.ready, UInt<1>(0h0)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits, _WIRE_3.bits
connect _WIRE_4.valid, _WIRE_3.valid
connect _WIRE_4.ready, _WIRE_3.ready
wire e : { sink : UInt<3>}
connect e.sink, nodeOut.d.bits.sink
connect _WIRE_4.bits, e
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits.sink, UInt<3>(0h0)
connect _WIRE_5.valid, UInt<1>(0h0)
connect _WIRE_5.ready, UInt<1>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_6.bits, _WIRE_5.bits
connect _WIRE_6.valid, _WIRE_5.valid
connect _WIRE_6.ready, _WIRE_5.ready
node _T_89 = and(_WIRE_6.ready, _WIRE_6.valid)
node _T_90 = and(nodeOut.d.ready, nodeOut.d.valid)
node _T_91 = and(_T_90, d_first)
node _T_92 = and(_T_91, grantIsCached)
node _T_93 = eq(_T_89, _T_92)
node _T_94 = asUInt(reset)
node _T_95 = eq(_T_94, UInt<1>(0h0))
when _T_95 :
node _T_96 = eq(_T_93, UInt<1>(0h0))
when _T_96 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:716 assert(tl_out.e.fire === (tl_out.d.fire && d_first && grantIsCached))\n") : printf_6
assert(clock, _T_93, UInt<1>(0h1), "") : assert_6
node _dataArb_io_in_1_valid_T = and(nodeOut.d.valid, grantIsRefill)
node _dataArb_io_in_1_valid_T_1 = and(_dataArb_io_in_1_valid_T, canAcceptCachedGrant)
connect dataArb.io.in[1].valid, _dataArb_io_in_1_valid_T_1
node _T_97 = eq(dataArb.io.in[1].ready, UInt<1>(0h0))
node _T_98 = and(grantIsRefill, _T_97)
when _T_98 :
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_7.bits.sink, UInt<3>(0h0)
connect _WIRE_7.valid, UInt<1>(0h0)
connect _WIRE_7.ready, UInt<1>(0h0)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_8.bits, _WIRE_7.bits
connect _WIRE_8.valid, _WIRE_7.valid
connect _WIRE_8.ready, _WIRE_7.ready
connect _WIRE_8.valid, UInt<1>(0h0)
connect nodeOut.d.ready, UInt<1>(0h0)
connect dataArb.io.in[1].bits.way_en, dataArb.io.in[0].bits.way_en
connect dataArb.io.in[1].bits.eccMask, dataArb.io.in[0].bits.eccMask
connect dataArb.io.in[1].bits.wordMask, dataArb.io.in[0].bits.wordMask
connect dataArb.io.in[1].bits.wdata, dataArb.io.in[0].bits.wdata
connect dataArb.io.in[1].bits.write, dataArb.io.in[0].bits.write
connect dataArb.io.in[1].bits.addr, dataArb.io.in[0].bits.addr
node _metaArb_io_in_3_valid_T = and(grantIsCached, d_done)
node _metaArb_io_in_3_valid_T_1 = eq(nodeOut.d.bits.denied, UInt<1>(0h0))
node _metaArb_io_in_3_valid_T_2 = and(_metaArb_io_in_3_valid_T, _metaArb_io_in_3_valid_T_1)
connect metaArb.io.in[3].valid, _metaArb_io_in_3_valid_T_2
connect metaArb.io.in[3].bits.write, UInt<1>(0h1)
connect metaArb.io.in[3].bits.way_en, refill_way
node _metaArb_io_in_3_bits_idx_T = bits(s2_vaddr, 10, 6)
connect metaArb.io.in[3].bits.idx, _metaArb_io_in_3_bits_idx_T
node _metaArb_io_in_3_bits_addr_T = shr(io.cpu.req.bits.addr, 11)
node _metaArb_io_in_3_bits_addr_T_1 = bits(s2_vaddr, 10, 0)
node _metaArb_io_in_3_bits_addr_T_2 = cat(_metaArb_io_in_3_bits_addr_T, _metaArb_io_in_3_bits_addr_T_1)
connect metaArb.io.in[3].bits.addr, _metaArb_io_in_3_bits_addr_T_2
node _metaArb_io_in_3_bits_data_T = shr(s2_req.addr, 11)
node _metaArb_io_in_3_bits_data_c_cat_T = eq(s2_req.cmd, UInt<1>(0h1))
node _metaArb_io_in_3_bits_data_c_cat_T_1 = eq(s2_req.cmd, UInt<5>(0h11))
node _metaArb_io_in_3_bits_data_c_cat_T_2 = or(_metaArb_io_in_3_bits_data_c_cat_T, _metaArb_io_in_3_bits_data_c_cat_T_1)
node _metaArb_io_in_3_bits_data_c_cat_T_3 = eq(s2_req.cmd, UInt<3>(0h7))
node _metaArb_io_in_3_bits_data_c_cat_T_4 = or(_metaArb_io_in_3_bits_data_c_cat_T_2, _metaArb_io_in_3_bits_data_c_cat_T_3)
node _metaArb_io_in_3_bits_data_c_cat_T_5 = eq(s2_req.cmd, UInt<3>(0h4))
node _metaArb_io_in_3_bits_data_c_cat_T_6 = eq(s2_req.cmd, UInt<4>(0h9))
node _metaArb_io_in_3_bits_data_c_cat_T_7 = eq(s2_req.cmd, UInt<4>(0ha))
node _metaArb_io_in_3_bits_data_c_cat_T_8 = eq(s2_req.cmd, UInt<4>(0hb))
node _metaArb_io_in_3_bits_data_c_cat_T_9 = or(_metaArb_io_in_3_bits_data_c_cat_T_5, _metaArb_io_in_3_bits_data_c_cat_T_6)
node _metaArb_io_in_3_bits_data_c_cat_T_10 = or(_metaArb_io_in_3_bits_data_c_cat_T_9, _metaArb_io_in_3_bits_data_c_cat_T_7)
node _metaArb_io_in_3_bits_data_c_cat_T_11 = or(_metaArb_io_in_3_bits_data_c_cat_T_10, _metaArb_io_in_3_bits_data_c_cat_T_8)
node _metaArb_io_in_3_bits_data_c_cat_T_12 = eq(s2_req.cmd, UInt<4>(0h8))
node _metaArb_io_in_3_bits_data_c_cat_T_13 = eq(s2_req.cmd, UInt<4>(0hc))
node _metaArb_io_in_3_bits_data_c_cat_T_14 = eq(s2_req.cmd, UInt<4>(0hd))
node _metaArb_io_in_3_bits_data_c_cat_T_15 = eq(s2_req.cmd, UInt<4>(0he))
node _metaArb_io_in_3_bits_data_c_cat_T_16 = eq(s2_req.cmd, UInt<4>(0hf))
node _metaArb_io_in_3_bits_data_c_cat_T_17 = or(_metaArb_io_in_3_bits_data_c_cat_T_12, _metaArb_io_in_3_bits_data_c_cat_T_13)
node _metaArb_io_in_3_bits_data_c_cat_T_18 = or(_metaArb_io_in_3_bits_data_c_cat_T_17, _metaArb_io_in_3_bits_data_c_cat_T_14)
node _metaArb_io_in_3_bits_data_c_cat_T_19 = or(_metaArb_io_in_3_bits_data_c_cat_T_18, _metaArb_io_in_3_bits_data_c_cat_T_15)
node _metaArb_io_in_3_bits_data_c_cat_T_20 = or(_metaArb_io_in_3_bits_data_c_cat_T_19, _metaArb_io_in_3_bits_data_c_cat_T_16)
node _metaArb_io_in_3_bits_data_c_cat_T_21 = or(_metaArb_io_in_3_bits_data_c_cat_T_11, _metaArb_io_in_3_bits_data_c_cat_T_20)
node _metaArb_io_in_3_bits_data_c_cat_T_22 = or(_metaArb_io_in_3_bits_data_c_cat_T_4, _metaArb_io_in_3_bits_data_c_cat_T_21)
node _metaArb_io_in_3_bits_data_c_cat_T_23 = eq(s2_req.cmd, UInt<1>(0h1))
node _metaArb_io_in_3_bits_data_c_cat_T_24 = eq(s2_req.cmd, UInt<5>(0h11))
node _metaArb_io_in_3_bits_data_c_cat_T_25 = or(_metaArb_io_in_3_bits_data_c_cat_T_23, _metaArb_io_in_3_bits_data_c_cat_T_24)
node _metaArb_io_in_3_bits_data_c_cat_T_26 = eq(s2_req.cmd, UInt<3>(0h7))
node _metaArb_io_in_3_bits_data_c_cat_T_27 = or(_metaArb_io_in_3_bits_data_c_cat_T_25, _metaArb_io_in_3_bits_data_c_cat_T_26)
node _metaArb_io_in_3_bits_data_c_cat_T_28 = eq(s2_req.cmd, UInt<3>(0h4))
node _metaArb_io_in_3_bits_data_c_cat_T_29 = eq(s2_req.cmd, UInt<4>(0h9))
node _metaArb_io_in_3_bits_data_c_cat_T_30 = eq(s2_req.cmd, UInt<4>(0ha))
node _metaArb_io_in_3_bits_data_c_cat_T_31 = eq(s2_req.cmd, UInt<4>(0hb))
node _metaArb_io_in_3_bits_data_c_cat_T_32 = or(_metaArb_io_in_3_bits_data_c_cat_T_28, _metaArb_io_in_3_bits_data_c_cat_T_29)
node _metaArb_io_in_3_bits_data_c_cat_T_33 = or(_metaArb_io_in_3_bits_data_c_cat_T_32, _metaArb_io_in_3_bits_data_c_cat_T_30)
node _metaArb_io_in_3_bits_data_c_cat_T_34 = or(_metaArb_io_in_3_bits_data_c_cat_T_33, _metaArb_io_in_3_bits_data_c_cat_T_31)
node _metaArb_io_in_3_bits_data_c_cat_T_35 = eq(s2_req.cmd, UInt<4>(0h8))
node _metaArb_io_in_3_bits_data_c_cat_T_36 = eq(s2_req.cmd, UInt<4>(0hc))
node _metaArb_io_in_3_bits_data_c_cat_T_37 = eq(s2_req.cmd, UInt<4>(0hd))
node _metaArb_io_in_3_bits_data_c_cat_T_38 = eq(s2_req.cmd, UInt<4>(0he))
node _metaArb_io_in_3_bits_data_c_cat_T_39 = eq(s2_req.cmd, UInt<4>(0hf))
node _metaArb_io_in_3_bits_data_c_cat_T_40 = or(_metaArb_io_in_3_bits_data_c_cat_T_35, _metaArb_io_in_3_bits_data_c_cat_T_36)
node _metaArb_io_in_3_bits_data_c_cat_T_41 = or(_metaArb_io_in_3_bits_data_c_cat_T_40, _metaArb_io_in_3_bits_data_c_cat_T_37)
node _metaArb_io_in_3_bits_data_c_cat_T_42 = or(_metaArb_io_in_3_bits_data_c_cat_T_41, _metaArb_io_in_3_bits_data_c_cat_T_38)
node _metaArb_io_in_3_bits_data_c_cat_T_43 = or(_metaArb_io_in_3_bits_data_c_cat_T_42, _metaArb_io_in_3_bits_data_c_cat_T_39)
node _metaArb_io_in_3_bits_data_c_cat_T_44 = or(_metaArb_io_in_3_bits_data_c_cat_T_34, _metaArb_io_in_3_bits_data_c_cat_T_43)
node _metaArb_io_in_3_bits_data_c_cat_T_45 = or(_metaArb_io_in_3_bits_data_c_cat_T_27, _metaArb_io_in_3_bits_data_c_cat_T_44)
node _metaArb_io_in_3_bits_data_c_cat_T_46 = eq(s2_req.cmd, UInt<2>(0h3))
node _metaArb_io_in_3_bits_data_c_cat_T_47 = or(_metaArb_io_in_3_bits_data_c_cat_T_45, _metaArb_io_in_3_bits_data_c_cat_T_46)
node _metaArb_io_in_3_bits_data_c_cat_T_48 = eq(s2_req.cmd, UInt<3>(0h6))
node _metaArb_io_in_3_bits_data_c_cat_T_49 = or(_metaArb_io_in_3_bits_data_c_cat_T_47, _metaArb_io_in_3_bits_data_c_cat_T_48)
node metaArb_io_in_3_bits_data_c = cat(_metaArb_io_in_3_bits_data_c_cat_T_22, _metaArb_io_in_3_bits_data_c_cat_T_49)
node _metaArb_io_in_3_bits_data_T_1 = cat(metaArb_io_in_3_bits_data_c, nodeOut.d.bits.param)
node _metaArb_io_in_3_bits_data_T_2 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _metaArb_io_in_3_bits_data_T_3 = cat(_metaArb_io_in_3_bits_data_T_2, UInt<2>(0h1))
node _metaArb_io_in_3_bits_data_T_4 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _metaArb_io_in_3_bits_data_T_5 = cat(_metaArb_io_in_3_bits_data_T_4, UInt<2>(0h0))
node _metaArb_io_in_3_bits_data_T_6 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _metaArb_io_in_3_bits_data_T_7 = cat(_metaArb_io_in_3_bits_data_T_6, UInt<2>(0h0))
node _metaArb_io_in_3_bits_data_T_8 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _metaArb_io_in_3_bits_data_T_9 = cat(_metaArb_io_in_3_bits_data_T_8, UInt<2>(0h0))
node _metaArb_io_in_3_bits_data_T_10 = eq(_metaArb_io_in_3_bits_data_T_3, _metaArb_io_in_3_bits_data_T_1)
node _metaArb_io_in_3_bits_data_T_11 = mux(_metaArb_io_in_3_bits_data_T_10, UInt<2>(0h1), UInt<2>(0h0))
node _metaArb_io_in_3_bits_data_T_12 = eq(_metaArb_io_in_3_bits_data_T_5, _metaArb_io_in_3_bits_data_T_1)
node _metaArb_io_in_3_bits_data_T_13 = mux(_metaArb_io_in_3_bits_data_T_12, UInt<2>(0h2), _metaArb_io_in_3_bits_data_T_11)
node _metaArb_io_in_3_bits_data_T_14 = eq(_metaArb_io_in_3_bits_data_T_7, _metaArb_io_in_3_bits_data_T_1)
node _metaArb_io_in_3_bits_data_T_15 = mux(_metaArb_io_in_3_bits_data_T_14, UInt<2>(0h2), _metaArb_io_in_3_bits_data_T_13)
node _metaArb_io_in_3_bits_data_T_16 = eq(_metaArb_io_in_3_bits_data_T_9, _metaArb_io_in_3_bits_data_T_1)
node _metaArb_io_in_3_bits_data_T_17 = mux(_metaArb_io_in_3_bits_data_T_16, UInt<2>(0h3), _metaArb_io_in_3_bits_data_T_15)
wire metaArb_io_in_3_bits_data_meta : { state : UInt<2>}
connect metaArb_io_in_3_bits_data_meta.state, _metaArb_io_in_3_bits_data_T_17
wire metaArb_io_in_3_bits_data_meta_1 : { coh : { state : UInt<2>}, tag : UInt<21>}
connect metaArb_io_in_3_bits_data_meta_1.tag, _metaArb_io_in_3_bits_data_T
connect metaArb_io_in_3_bits_data_meta_1.coh, metaArb_io_in_3_bits_data_meta
node _metaArb_io_in_3_bits_data_T_18 = cat(metaArb_io_in_3_bits_data_meta_1.coh.state, metaArb_io_in_3_bits_data_meta_1.tag)
connect metaArb.io.in[3].bits.data, _metaArb_io_in_3_bits_data_T_18
reg blockUncachedGrant : UInt<1>, clock
connect blockUncachedGrant, dataArb.io.out.valid
node _T_99 = or(blockUncachedGrant, s1_valid)
node _T_100 = and(grantIsUncachedData, _T_99)
when _T_100 :
connect nodeOut.d.ready, UInt<1>(0h0)
when nodeOut.d.valid :
connect io.cpu.req.ready, UInt<1>(0h0)
connect dataArb.io.in[1].valid, UInt<1>(0h1)
connect dataArb.io.in[1].bits.write, UInt<1>(0h0)
node _blockUncachedGrant_T = eq(dataArb.io.in[1].ready, UInt<1>(0h0))
connect blockUncachedGrant, _blockUncachedGrant_T
node _T_101 = eq(nodeOut.d.ready, UInt<1>(0h0))
node _T_102 = and(nodeOut.d.valid, _T_101)
node _block_probe_for_core_progress_T = gt(blockProbeAfterGrantCount, UInt<1>(0h0))
node block_probe_for_core_progress = or(_block_probe_for_core_progress_T, lrscValid)
wire _block_probe_for_pending_release_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _block_probe_for_pending_release_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _block_probe_for_pending_release_ack_WIRE.bits.data, UInt<64>(0h0)
connect _block_probe_for_pending_release_ack_WIRE.bits.mask, UInt<8>(0h0)
connect _block_probe_for_pending_release_ack_WIRE.bits.address, UInt<32>(0h0)
connect _block_probe_for_pending_release_ack_WIRE.bits.source, UInt<1>(0h0)
connect _block_probe_for_pending_release_ack_WIRE.bits.size, UInt<4>(0h0)
connect _block_probe_for_pending_release_ack_WIRE.bits.param, UInt<2>(0h0)
connect _block_probe_for_pending_release_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _block_probe_for_pending_release_ack_WIRE.valid, UInt<1>(0h0)
connect _block_probe_for_pending_release_ack_WIRE.ready, UInt<1>(0h0)
wire _block_probe_for_pending_release_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _block_probe_for_pending_release_ack_WIRE_1.bits, _block_probe_for_pending_release_ack_WIRE.bits
connect _block_probe_for_pending_release_ack_WIRE_1.valid, _block_probe_for_pending_release_ack_WIRE.valid
connect _block_probe_for_pending_release_ack_WIRE_1.ready, _block_probe_for_pending_release_ack_WIRE.ready
node _block_probe_for_pending_release_ack_T = xor(_block_probe_for_pending_release_ack_WIRE_1.bits.address, release_ack_addr)
node _block_probe_for_pending_release_ack_T_1 = bits(_block_probe_for_pending_release_ack_T, 20, 6)
node _block_probe_for_pending_release_ack_T_2 = eq(_block_probe_for_pending_release_ack_T_1, UInt<1>(0h0))
node block_probe_for_pending_release_ack = and(release_ack_wait, _block_probe_for_pending_release_ack_T_2)
node _block_probe_for_ordering_T = or(releaseInFlight, block_probe_for_pending_release_ack)
node block_probe_for_ordering = or(_block_probe_for_ordering_T, grantInProgress)
wire _metaArb_io_in_6_valid_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _metaArb_io_in_6_valid_WIRE.bits.corrupt, UInt<1>(0h0)
connect _metaArb_io_in_6_valid_WIRE.bits.data, UInt<64>(0h0)
connect _metaArb_io_in_6_valid_WIRE.bits.mask, UInt<8>(0h0)
connect _metaArb_io_in_6_valid_WIRE.bits.address, UInt<32>(0h0)
connect _metaArb_io_in_6_valid_WIRE.bits.source, UInt<1>(0h0)
connect _metaArb_io_in_6_valid_WIRE.bits.size, UInt<4>(0h0)
connect _metaArb_io_in_6_valid_WIRE.bits.param, UInt<2>(0h0)
connect _metaArb_io_in_6_valid_WIRE.bits.opcode, UInt<3>(0h0)
connect _metaArb_io_in_6_valid_WIRE.valid, UInt<1>(0h0)
connect _metaArb_io_in_6_valid_WIRE.ready, UInt<1>(0h0)
wire _metaArb_io_in_6_valid_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _metaArb_io_in_6_valid_WIRE_1.bits, _metaArb_io_in_6_valid_WIRE.bits
connect _metaArb_io_in_6_valid_WIRE_1.valid, _metaArb_io_in_6_valid_WIRE.valid
connect _metaArb_io_in_6_valid_WIRE_1.ready, _metaArb_io_in_6_valid_WIRE.ready
node _metaArb_io_in_6_valid_T = eq(block_probe_for_core_progress, UInt<1>(0h0))
node _metaArb_io_in_6_valid_T_1 = or(_metaArb_io_in_6_valid_T, lrscBackingOff)
node _metaArb_io_in_6_valid_T_2 = and(_metaArb_io_in_6_valid_WIRE_1.valid, _metaArb_io_in_6_valid_T_1)
connect metaArb.io.in[6].valid, _metaArb_io_in_6_valid_T_2
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits.corrupt, UInt<1>(0h0)
connect _WIRE_9.bits.data, UInt<64>(0h0)
connect _WIRE_9.bits.mask, UInt<8>(0h0)
connect _WIRE_9.bits.address, UInt<32>(0h0)
connect _WIRE_9.bits.source, UInt<1>(0h0)
connect _WIRE_9.bits.size, UInt<4>(0h0)
connect _WIRE_9.bits.param, UInt<2>(0h0)
connect _WIRE_9.bits.opcode, UInt<3>(0h0)
connect _WIRE_9.valid, UInt<1>(0h0)
connect _WIRE_9.ready, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits, _WIRE_9.bits
connect _WIRE_10.valid, _WIRE_9.valid
connect _WIRE_10.ready, _WIRE_9.ready
node _T_103 = or(block_probe_for_core_progress, block_probe_for_ordering)
node _T_104 = or(_T_103, s1_valid)
node _T_105 = or(_T_104, s2_valid)
node _T_106 = eq(_T_105, UInt<1>(0h0))
node _T_107 = and(metaArb.io.in[6].ready, _T_106)
connect _WIRE_10.ready, _T_107
connect metaArb.io.in[6].bits.write, UInt<1>(0h0)
wire _metaArb_io_in_6_bits_idx_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _metaArb_io_in_6_bits_idx_WIRE.bits.corrupt, UInt<1>(0h0)
connect _metaArb_io_in_6_bits_idx_WIRE.bits.data, UInt<64>(0h0)
connect _metaArb_io_in_6_bits_idx_WIRE.bits.mask, UInt<8>(0h0)
connect _metaArb_io_in_6_bits_idx_WIRE.bits.address, UInt<32>(0h0)
connect _metaArb_io_in_6_bits_idx_WIRE.bits.source, UInt<1>(0h0)
connect _metaArb_io_in_6_bits_idx_WIRE.bits.size, UInt<4>(0h0)
connect _metaArb_io_in_6_bits_idx_WIRE.bits.param, UInt<2>(0h0)
connect _metaArb_io_in_6_bits_idx_WIRE.bits.opcode, UInt<3>(0h0)
connect _metaArb_io_in_6_bits_idx_WIRE.valid, UInt<1>(0h0)
connect _metaArb_io_in_6_bits_idx_WIRE.ready, UInt<1>(0h0)
wire _metaArb_io_in_6_bits_idx_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _metaArb_io_in_6_bits_idx_WIRE_1.bits, _metaArb_io_in_6_bits_idx_WIRE.bits
connect _metaArb_io_in_6_bits_idx_WIRE_1.valid, _metaArb_io_in_6_bits_idx_WIRE.valid
connect _metaArb_io_in_6_bits_idx_WIRE_1.ready, _metaArb_io_in_6_bits_idx_WIRE.ready
node _metaArb_io_in_6_bits_idx_T = bits(_metaArb_io_in_6_bits_idx_WIRE_1.bits.address, 10, 6)
connect metaArb.io.in[6].bits.idx, _metaArb_io_in_6_bits_idx_T
node _metaArb_io_in_6_bits_addr_T = shr(io.cpu.req.bits.addr, 32)
wire _metaArb_io_in_6_bits_addr_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _metaArb_io_in_6_bits_addr_WIRE.bits.corrupt, UInt<1>(0h0)
connect _metaArb_io_in_6_bits_addr_WIRE.bits.data, UInt<64>(0h0)
connect _metaArb_io_in_6_bits_addr_WIRE.bits.mask, UInt<8>(0h0)
connect _metaArb_io_in_6_bits_addr_WIRE.bits.address, UInt<32>(0h0)
connect _metaArb_io_in_6_bits_addr_WIRE.bits.source, UInt<1>(0h0)
connect _metaArb_io_in_6_bits_addr_WIRE.bits.size, UInt<4>(0h0)
connect _metaArb_io_in_6_bits_addr_WIRE.bits.param, UInt<2>(0h0)
connect _metaArb_io_in_6_bits_addr_WIRE.bits.opcode, UInt<3>(0h0)
connect _metaArb_io_in_6_bits_addr_WIRE.valid, UInt<1>(0h0)
connect _metaArb_io_in_6_bits_addr_WIRE.ready, UInt<1>(0h0)
wire _metaArb_io_in_6_bits_addr_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _metaArb_io_in_6_bits_addr_WIRE_1.bits, _metaArb_io_in_6_bits_addr_WIRE.bits
connect _metaArb_io_in_6_bits_addr_WIRE_1.valid, _metaArb_io_in_6_bits_addr_WIRE.valid
connect _metaArb_io_in_6_bits_addr_WIRE_1.ready, _metaArb_io_in_6_bits_addr_WIRE.ready
node _metaArb_io_in_6_bits_addr_T_1 = cat(_metaArb_io_in_6_bits_addr_T, _metaArb_io_in_6_bits_addr_WIRE_1.bits.address)
connect metaArb.io.in[6].bits.addr, _metaArb_io_in_6_bits_addr_T_1
connect metaArb.io.in[6].bits.way_en, metaArb.io.in[4].bits.way_en
connect metaArb.io.in[6].bits.data, metaArb.io.in[4].bits.data
connect s1_victim_way, UInt<1>(0h0)
node _T_108 = and(tl_out_c.ready, tl_out_c.valid)
node _r_beats1_decode_T_3 = dshl(UInt<12>(0hfff), tl_out_c.bits.size)
node _r_beats1_decode_T_4 = bits(_r_beats1_decode_T_3, 11, 0)
node _r_beats1_decode_T_5 = not(_r_beats1_decode_T_4)
node r_beats1_decode_1 = shr(_r_beats1_decode_T_5, 3)
node r_beats1_opdata_1 = bits(tl_out_c.bits.opcode, 0, 0)
node r_beats1_1 = mux(UInt<1>(0h0), r_beats1_decode_1, UInt<1>(0h0))
regreset r_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _r_counter1_T_1 = sub(r_counter_1, UInt<1>(0h1))
node r_counter1_1 = tail(_r_counter1_T_1, 1)
node c_first = eq(r_counter_1, UInt<1>(0h0))
node _r_last_T_2 = eq(r_counter_1, UInt<1>(0h1))
node _r_last_T_3 = eq(r_beats1_1, UInt<1>(0h0))
node c_last = or(_r_last_T_2, _r_last_T_3)
node releaseDone = and(c_last, _T_108)
node _r_count_T_1 = not(r_counter1_1)
node c_count = and(r_beats1_1, _r_count_T_1)
when _T_108 :
node _r_counter_T_1 = mux(c_first, r_beats1_1, r_counter1_1)
connect r_counter_1, _r_counter_T_1
wire releaseRejected : UInt<1>
node _s1_release_data_valid_T = and(dataArb.io.in[2].ready, dataArb.io.in[2].valid)
reg s1_release_data_valid : UInt<1>, clock
connect s1_release_data_valid, _s1_release_data_valid_T
node _s2_release_data_valid_T = eq(releaseRejected, UInt<1>(0h0))
node _s2_release_data_valid_T_1 = and(s1_release_data_valid, _s2_release_data_valid_T)
reg s2_release_data_valid : UInt<1>, clock
connect s2_release_data_valid, _s2_release_data_valid_T_1
node _releaseRejected_T = and(tl_out_c.ready, tl_out_c.valid)
node _releaseRejected_T_1 = eq(_releaseRejected_T, UInt<1>(0h0))
node _releaseRejected_T_2 = and(s2_release_data_valid, _releaseRejected_T_1)
connect releaseRejected, _releaseRejected_T_2
node _releaseDataBeat_T = cat(UInt<1>(0h0), c_count)
node _releaseDataBeat_T_1 = cat(UInt<1>(0h0), s2_release_data_valid)
node _releaseDataBeat_T_2 = add(s1_release_data_valid, _releaseDataBeat_T_1)
node _releaseDataBeat_T_3 = tail(_releaseDataBeat_T_2, 1)
node _releaseDataBeat_T_4 = mux(releaseRejected, UInt<1>(0h0), _releaseDataBeat_T_3)
node _releaseDataBeat_T_5 = add(_releaseDataBeat_T, _releaseDataBeat_T_4)
node releaseDataBeat = tail(_releaseDataBeat_T_5, 1)
wire nackResponseMessage : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect nackResponseMessage.opcode, UInt<3>(0h4)
connect nackResponseMessage.param, UInt<3>(0h5)
connect nackResponseMessage.size, probe_bits.size
connect nackResponseMessage.source, probe_bits.source
connect nackResponseMessage.address, probe_bits.address
invalidate nackResponseMessage.data
connect nackResponseMessage.corrupt, UInt<1>(0h0)
wire cleanReleaseMessage : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect cleanReleaseMessage.opcode, UInt<3>(0h4)
connect cleanReleaseMessage.param, s2_report_param
connect cleanReleaseMessage.size, probe_bits.size
connect cleanReleaseMessage.source, probe_bits.source
connect cleanReleaseMessage.address, probe_bits.address
invalidate cleanReleaseMessage.data
connect cleanReleaseMessage.corrupt, UInt<1>(0h0)
wire dirtyReleaseMessage : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect dirtyReleaseMessage.opcode, UInt<3>(0h5)
connect dirtyReleaseMessage.param, s2_report_param
connect dirtyReleaseMessage.size, probe_bits.size
connect dirtyReleaseMessage.source, probe_bits.source
connect dirtyReleaseMessage.address, probe_bits.address
connect dirtyReleaseMessage.data, UInt<1>(0h0)
connect dirtyReleaseMessage.corrupt, UInt<1>(0h0)
node _tl_out_c_valid_T = eq(UInt<1>(0h1), UInt<1>(0h0))
node _tl_out_c_valid_T_1 = eq(release_state, UInt<4>(0h9))
node _tl_out_c_valid_T_2 = and(_tl_out_c_valid_T, _tl_out_c_valid_T_1)
node _tl_out_c_valid_T_3 = or(s2_release_data_valid, _tl_out_c_valid_T_2)
node _tl_out_c_valid_T_4 = and(c_first, release_ack_wait)
node _tl_out_c_valid_T_5 = eq(_tl_out_c_valid_T_4, UInt<1>(0h0))
node _tl_out_c_valid_T_6 = and(_tl_out_c_valid_T_3, _tl_out_c_valid_T_5)
connect tl_out_c.valid, _tl_out_c_valid_T_6
connect tl_out_c.bits, nackResponseMessage
wire newCoh : { state : UInt<2>}
connect newCoh, probeNewCoh
connect releaseWay, s2_probe_way
node _dataArb_io_in_2_valid_T = lt(releaseDataBeat, UInt<4>(0h8))
node _dataArb_io_in_2_valid_T_1 = and(inWriteback, _dataArb_io_in_2_valid_T)
connect dataArb.io.in[2].valid, _dataArb_io_in_2_valid_T_1
connect dataArb.io.in[2].bits.way_en, dataArb.io.in[1].bits.way_en
connect dataArb.io.in[2].bits.eccMask, dataArb.io.in[1].bits.eccMask
connect dataArb.io.in[2].bits.wordMask, dataArb.io.in[1].bits.wordMask
connect dataArb.io.in[2].bits.wdata, dataArb.io.in[1].bits.wdata
connect dataArb.io.in[2].bits.write, dataArb.io.in[1].bits.write
connect dataArb.io.in[2].bits.addr, dataArb.io.in[1].bits.addr
connect dataArb.io.in[2].bits.write, UInt<1>(0h0)
node _dataArb_io_in_2_bits_addr_T = bits(probe_bits.address, 10, 6)
node _dataArb_io_in_2_bits_addr_T_1 = shl(_dataArb_io_in_2_bits_addr_T, 6)
node _dataArb_io_in_2_bits_addr_T_2 = bits(releaseDataBeat, 2, 0)
node _dataArb_io_in_2_bits_addr_T_3 = shl(_dataArb_io_in_2_bits_addr_T_2, 3)
node _dataArb_io_in_2_bits_addr_T_4 = or(_dataArb_io_in_2_bits_addr_T_1, _dataArb_io_in_2_bits_addr_T_3)
connect dataArb.io.in[2].bits.addr, _dataArb_io_in_2_bits_addr_T_4
node _dataArb_io_in_2_bits_wordMask_T = not(UInt<1>(0h0))
connect dataArb.io.in[2].bits.wordMask, _dataArb_io_in_2_bits_wordMask_T
node _dataArb_io_in_2_bits_eccMask_T = not(UInt<8>(0h0))
connect dataArb.io.in[2].bits.eccMask, _dataArb_io_in_2_bits_eccMask_T
node _dataArb_io_in_2_bits_way_en_T = not(UInt<1>(0h0))
connect dataArb.io.in[2].bits.way_en, _dataArb_io_in_2_bits_way_en_T
node _metaArb_io_in_4_valid_T = eq(release_state, UInt<4>(0h6))
node _metaArb_io_in_4_valid_T_1 = eq(release_state, UInt<4>(0h7))
node _metaArb_io_in_4_valid_T_2 = or(_metaArb_io_in_4_valid_T, _metaArb_io_in_4_valid_T_1)
connect metaArb.io.in[4].valid, _metaArb_io_in_4_valid_T_2
connect metaArb.io.in[4].bits.write, UInt<1>(0h1)
connect metaArb.io.in[4].bits.way_en, releaseWay
node _metaArb_io_in_4_bits_idx_T = bits(probe_bits.address, 10, 6)
connect metaArb.io.in[4].bits.idx, _metaArb_io_in_4_bits_idx_T
node _metaArb_io_in_4_bits_addr_T = shr(io.cpu.req.bits.addr, 11)
node _metaArb_io_in_4_bits_addr_T_1 = bits(probe_bits.address, 10, 0)
node _metaArb_io_in_4_bits_addr_T_2 = cat(_metaArb_io_in_4_bits_addr_T, _metaArb_io_in_4_bits_addr_T_1)
connect metaArb.io.in[4].bits.addr, _metaArb_io_in_4_bits_addr_T_2
node _metaArb_io_in_4_bits_data_T = shr(tl_out_c.bits.address, 11)
wire metaArb_io_in_4_bits_data_meta : { coh : { state : UInt<2>}, tag : UInt<21>}
connect metaArb_io_in_4_bits_data_meta.tag, _metaArb_io_in_4_bits_data_T
connect metaArb_io_in_4_bits_data_meta.coh, newCoh
node _metaArb_io_in_4_bits_data_T_1 = cat(metaArb_io_in_4_bits_data_meta.coh.state, metaArb_io_in_4_bits_data_meta.tag)
connect metaArb.io.in[4].bits.data, _metaArb_io_in_4_bits_data_T_1
node _T_109 = and(metaArb.io.in[4].ready, metaArb.io.in[4].valid)
when _T_109 :
connect release_state, UInt<4>(0h0)
connect io.cpu.resp.bits.mask, s2_req.mask
connect io.cpu.resp.bits.data, s2_req.data
connect io.cpu.resp.bits.dv, s2_req.dv
connect io.cpu.resp.bits.dprv, s2_req.dprv
connect io.cpu.resp.bits.signed, s2_req.signed
connect io.cpu.resp.bits.size, s2_req.size
connect io.cpu.resp.bits.cmd, s2_req.cmd
connect io.cpu.resp.bits.tag, s2_req.tag
connect io.cpu.resp.bits.addr, s2_req.addr
connect io.cpu.resp.bits.has_data, s2_read
connect io.cpu.resp.bits.replay, UInt<1>(0h0)
node _io_cpu_s2_uncached_T = eq(s2_hit, UInt<1>(0h0))
node _io_cpu_s2_uncached_T_1 = and(s2_uncached, _io_cpu_s2_uncached_T)
connect io.cpu.s2_uncached, _io_cpu_s2_uncached_T_1
connect io.cpu.s2_paddr, s2_req.addr
connect io.cpu.s2_gpa, s2_tlb_xcpt.gpa
connect io.cpu.s2_gpa_is_pte, s2_tlb_xcpt.gpa_is_pte
node _io_cpu_ordered_T = eq(s1_req.no_xcpt, UInt<1>(0h0))
node _io_cpu_ordered_T_1 = and(s1_valid, _io_cpu_ordered_T)
node _io_cpu_ordered_T_2 = eq(s2_req.no_xcpt, UInt<1>(0h0))
node _io_cpu_ordered_T_3 = and(s2_valid, _io_cpu_ordered_T_2)
node _io_cpu_ordered_T_4 = or(_io_cpu_ordered_T_1, _io_cpu_ordered_T_3)
node _io_cpu_ordered_T_5 = or(_io_cpu_ordered_T_4, cached_grant_wait)
node _io_cpu_ordered_T_6 = orr(uncachedInFlight[0])
node _io_cpu_ordered_T_7 = or(_io_cpu_ordered_T_5, _io_cpu_ordered_T_6)
node _io_cpu_ordered_T_8 = eq(_io_cpu_ordered_T_7, UInt<1>(0h0))
connect io.cpu.ordered, _io_cpu_ordered_T_8
node _io_cpu_store_pending_T = eq(s2_req.cmd, UInt<1>(0h1))
node _io_cpu_store_pending_T_1 = eq(s2_req.cmd, UInt<5>(0h11))
node _io_cpu_store_pending_T_2 = or(_io_cpu_store_pending_T, _io_cpu_store_pending_T_1)
node _io_cpu_store_pending_T_3 = eq(s2_req.cmd, UInt<3>(0h7))
node _io_cpu_store_pending_T_4 = or(_io_cpu_store_pending_T_2, _io_cpu_store_pending_T_3)
node _io_cpu_store_pending_T_5 = eq(s2_req.cmd, UInt<3>(0h4))
node _io_cpu_store_pending_T_6 = eq(s2_req.cmd, UInt<4>(0h9))
node _io_cpu_store_pending_T_7 = eq(s2_req.cmd, UInt<4>(0ha))
node _io_cpu_store_pending_T_8 = eq(s2_req.cmd, UInt<4>(0hb))
node _io_cpu_store_pending_T_9 = or(_io_cpu_store_pending_T_5, _io_cpu_store_pending_T_6)
node _io_cpu_store_pending_T_10 = or(_io_cpu_store_pending_T_9, _io_cpu_store_pending_T_7)
node _io_cpu_store_pending_T_11 = or(_io_cpu_store_pending_T_10, _io_cpu_store_pending_T_8)
node _io_cpu_store_pending_T_12 = eq(s2_req.cmd, UInt<4>(0h8))
node _io_cpu_store_pending_T_13 = eq(s2_req.cmd, UInt<4>(0hc))
node _io_cpu_store_pending_T_14 = eq(s2_req.cmd, UInt<4>(0hd))
node _io_cpu_store_pending_T_15 = eq(s2_req.cmd, UInt<4>(0he))
node _io_cpu_store_pending_T_16 = eq(s2_req.cmd, UInt<4>(0hf))
node _io_cpu_store_pending_T_17 = or(_io_cpu_store_pending_T_12, _io_cpu_store_pending_T_13)
node _io_cpu_store_pending_T_18 = or(_io_cpu_store_pending_T_17, _io_cpu_store_pending_T_14)
node _io_cpu_store_pending_T_19 = or(_io_cpu_store_pending_T_18, _io_cpu_store_pending_T_15)
node _io_cpu_store_pending_T_20 = or(_io_cpu_store_pending_T_19, _io_cpu_store_pending_T_16)
node _io_cpu_store_pending_T_21 = or(_io_cpu_store_pending_T_11, _io_cpu_store_pending_T_20)
node _io_cpu_store_pending_T_22 = or(_io_cpu_store_pending_T_4, _io_cpu_store_pending_T_21)
node _io_cpu_store_pending_T_23 = and(cached_grant_wait, _io_cpu_store_pending_T_22)
node _io_cpu_store_pending_T_24 = orr(uncachedInFlight[0])
node _io_cpu_store_pending_T_25 = or(_io_cpu_store_pending_T_23, _io_cpu_store_pending_T_24)
connect io.cpu.store_pending, _io_cpu_store_pending_T_25
node _s1_xcpt_valid_T = eq(s1_req.no_xcpt, UInt<1>(0h0))
node _s1_xcpt_valid_T_1 = and(tlb.io.req.valid, _s1_xcpt_valid_T)
node _s1_xcpt_valid_T_2 = eq(s1_nack, UInt<1>(0h0))
node s1_xcpt_valid = and(_s1_xcpt_valid_T_1, _s1_xcpt_valid_T_2)
reg io_cpu_s2_xcpt_REG : UInt<1>, clock
connect io_cpu_s2_xcpt_REG, s1_xcpt_valid
wire _io_cpu_s2_xcpt_WIRE : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}
connect _io_cpu_s2_xcpt_WIRE.cmd, UInt<5>(0h0)
connect _io_cpu_s2_xcpt_WIRE.size, UInt<2>(0h0)
connect _io_cpu_s2_xcpt_WIRE.prefetchable, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.must_alloc, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.cacheable, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.ma.inst, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.ma.st, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.ma.ld, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.ae.inst, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.ae.st, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.ae.ld, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.gf.inst, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.gf.st, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.gf.ld, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.pf.inst, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.pf.st, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.pf.ld, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.gpa_is_pte, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.gpa, UInt<40>(0h0)
connect _io_cpu_s2_xcpt_WIRE.paddr, UInt<32>(0h0)
connect _io_cpu_s2_xcpt_WIRE.miss, UInt<1>(0h0)
node _io_cpu_s2_xcpt_T = mux(io_cpu_s2_xcpt_REG, s2_tlb_xcpt, _io_cpu_s2_xcpt_WIRE)
connect io.cpu.s2_xcpt.ae.st, _io_cpu_s2_xcpt_T.ae.st
connect io.cpu.s2_xcpt.ae.ld, _io_cpu_s2_xcpt_T.ae.ld
connect io.cpu.s2_xcpt.gf.st, _io_cpu_s2_xcpt_T.gf.st
connect io.cpu.s2_xcpt.gf.ld, _io_cpu_s2_xcpt_T.gf.ld
connect io.cpu.s2_xcpt.pf.st, _io_cpu_s2_xcpt_T.pf.st
connect io.cpu.s2_xcpt.pf.ld, _io_cpu_s2_xcpt_T.pf.ld
connect io.cpu.s2_xcpt.ma.st, _io_cpu_s2_xcpt_T.ma.st
connect io.cpu.s2_xcpt.ma.ld, _io_cpu_s2_xcpt_T.ma.ld
node _T_110 = eq(s2_req.cmd, UInt<3>(0h6))
node _T_111 = eq(s2_req.cmd, UInt<3>(0h7))
node _T_112 = or(_T_110, _T_111)
node _T_113 = and(s2_valid_masked, _T_112)
node _T_114 = eq(_T_113, UInt<1>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:936 assert(!(s2_valid_masked && s2_req.cmd.isOneOf(M_XLR, M_XSC)))\n") : printf_7
assert(clock, _T_114, UInt<1>(0h1), "") : assert_7
node s1_uncached_data_word = bits(nodeOut.d.bits.data, 63, 0)
reg s2_uncached_data_word : UInt<64>, clock
when io.cpu.replay_next :
connect s2_uncached_data_word, s1_uncached_data_word
reg doUncachedResp : UInt<1>, clock
connect doUncachedResp, io.cpu.replay_next
node _io_cpu_resp_valid_T = or(s2_valid_hit_pre_data_ecc, doUncachedResp)
node _io_cpu_resp_valid_T_1 = eq(s2_data_error, UInt<1>(0h0))
node _io_cpu_resp_valid_T_2 = and(_io_cpu_resp_valid_T, _io_cpu_resp_valid_T_1)
connect io.cpu.resp.valid, _io_cpu_resp_valid_T_2
node _io_cpu_replay_next_T = and(nodeOut.d.ready, nodeOut.d.valid)
node _io_cpu_replay_next_T_1 = and(_io_cpu_replay_next_T, grantIsUncachedData)
node _io_cpu_replay_next_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _io_cpu_replay_next_T_3 = and(_io_cpu_replay_next_T_1, _io_cpu_replay_next_T_2)
connect io.cpu.replay_next, _io_cpu_replay_next_T_3
when doUncachedResp :
node _T_118 = eq(s2_valid_hit, UInt<1>(0h0))
node _T_119 = asUInt(reset)
node _T_120 = eq(_T_119, UInt<1>(0h0))
when _T_120 :
node _T_121 = eq(_T_118, UInt<1>(0h0))
when _T_121 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:952 assert(!s2_valid_hit)\n") : printf_8
assert(clock, _T_118, UInt<1>(0h1), "") : assert_8
connect io.cpu.resp.bits.replay, UInt<1>(0h1)
connect io.cpu.resp.bits.addr, s2_uncached_resp_addr
node s2_data_word = bits(s2_data_uncorrected, 63, 0)
node s2_data_word_corrected = bits(s2_data_corrected, 63, 0)
node _s2_data_word_possibly_uncached_T = and(UInt<1>(0h0), doUncachedResp)
node _s2_data_word_possibly_uncached_T_1 = mux(_s2_data_word_possibly_uncached_T, s2_uncached_data_word, UInt<1>(0h0))
node s2_data_word_possibly_uncached = or(_s2_data_word_possibly_uncached_T_1, s2_data_word)
wire size : UInt<2>
connect size, s2_req.size
node _io_cpu_resp_bits_data_shifted_T = bits(s2_req.addr, 2, 2)
node _io_cpu_resp_bits_data_shifted_T_1 = bits(s2_data_word_possibly_uncached, 63, 32)
node _io_cpu_resp_bits_data_shifted_T_2 = bits(s2_data_word_possibly_uncached, 31, 0)
node io_cpu_resp_bits_data_shifted = mux(_io_cpu_resp_bits_data_shifted_T, _io_cpu_resp_bits_data_shifted_T_1, _io_cpu_resp_bits_data_shifted_T_2)
node io_cpu_resp_bits_data_doZero = and(UInt<1>(0h0), s2_sc)
node io_cpu_resp_bits_data_zeroed = mux(io_cpu_resp_bits_data_doZero, UInt<1>(0h0), io_cpu_resp_bits_data_shifted)
node _io_cpu_resp_bits_data_T = eq(size, UInt<2>(0h2))
node _io_cpu_resp_bits_data_T_1 = or(_io_cpu_resp_bits_data_T, io_cpu_resp_bits_data_doZero)
node _io_cpu_resp_bits_data_T_2 = bits(io_cpu_resp_bits_data_zeroed, 31, 31)
node _io_cpu_resp_bits_data_T_3 = and(s2_req.signed, _io_cpu_resp_bits_data_T_2)
node _io_cpu_resp_bits_data_T_4 = mux(_io_cpu_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0))
node _io_cpu_resp_bits_data_T_5 = bits(s2_data_word_possibly_uncached, 63, 32)
node _io_cpu_resp_bits_data_T_6 = mux(_io_cpu_resp_bits_data_T_1, _io_cpu_resp_bits_data_T_4, _io_cpu_resp_bits_data_T_5)
node _io_cpu_resp_bits_data_T_7 = cat(_io_cpu_resp_bits_data_T_6, io_cpu_resp_bits_data_zeroed)
node _io_cpu_resp_bits_data_shifted_T_3 = bits(s2_req.addr, 1, 1)
node _io_cpu_resp_bits_data_shifted_T_4 = bits(_io_cpu_resp_bits_data_T_7, 31, 16)
node _io_cpu_resp_bits_data_shifted_T_5 = bits(_io_cpu_resp_bits_data_T_7, 15, 0)
node io_cpu_resp_bits_data_shifted_1 = mux(_io_cpu_resp_bits_data_shifted_T_3, _io_cpu_resp_bits_data_shifted_T_4, _io_cpu_resp_bits_data_shifted_T_5)
node io_cpu_resp_bits_data_doZero_1 = and(UInt<1>(0h0), s2_sc)
node io_cpu_resp_bits_data_zeroed_1 = mux(io_cpu_resp_bits_data_doZero_1, UInt<1>(0h0), io_cpu_resp_bits_data_shifted_1)
node _io_cpu_resp_bits_data_T_8 = eq(size, UInt<1>(0h1))
node _io_cpu_resp_bits_data_T_9 = or(_io_cpu_resp_bits_data_T_8, io_cpu_resp_bits_data_doZero_1)
node _io_cpu_resp_bits_data_T_10 = bits(io_cpu_resp_bits_data_zeroed_1, 15, 15)
node _io_cpu_resp_bits_data_T_11 = and(s2_req.signed, _io_cpu_resp_bits_data_T_10)
node _io_cpu_resp_bits_data_T_12 = mux(_io_cpu_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0))
node _io_cpu_resp_bits_data_T_13 = bits(_io_cpu_resp_bits_data_T_7, 63, 16)
node _io_cpu_resp_bits_data_T_14 = mux(_io_cpu_resp_bits_data_T_9, _io_cpu_resp_bits_data_T_12, _io_cpu_resp_bits_data_T_13)
node _io_cpu_resp_bits_data_T_15 = cat(_io_cpu_resp_bits_data_T_14, io_cpu_resp_bits_data_zeroed_1)
node _io_cpu_resp_bits_data_shifted_T_6 = bits(s2_req.addr, 0, 0)
node _io_cpu_resp_bits_data_shifted_T_7 = bits(_io_cpu_resp_bits_data_T_15, 15, 8)
node _io_cpu_resp_bits_data_shifted_T_8 = bits(_io_cpu_resp_bits_data_T_15, 7, 0)
node io_cpu_resp_bits_data_shifted_2 = mux(_io_cpu_resp_bits_data_shifted_T_6, _io_cpu_resp_bits_data_shifted_T_7, _io_cpu_resp_bits_data_shifted_T_8)
node io_cpu_resp_bits_data_doZero_2 = and(UInt<1>(0h1), s2_sc)
node io_cpu_resp_bits_data_zeroed_2 = mux(io_cpu_resp_bits_data_doZero_2, UInt<1>(0h0), io_cpu_resp_bits_data_shifted_2)
node _io_cpu_resp_bits_data_T_16 = eq(size, UInt<1>(0h0))
node _io_cpu_resp_bits_data_T_17 = or(_io_cpu_resp_bits_data_T_16, io_cpu_resp_bits_data_doZero_2)
node _io_cpu_resp_bits_data_T_18 = bits(io_cpu_resp_bits_data_zeroed_2, 7, 7)
node _io_cpu_resp_bits_data_T_19 = and(s2_req.signed, _io_cpu_resp_bits_data_T_18)
node _io_cpu_resp_bits_data_T_20 = mux(_io_cpu_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0))
node _io_cpu_resp_bits_data_T_21 = bits(_io_cpu_resp_bits_data_T_15, 63, 8)
node _io_cpu_resp_bits_data_T_22 = mux(_io_cpu_resp_bits_data_T_17, _io_cpu_resp_bits_data_T_20, _io_cpu_resp_bits_data_T_21)
node _io_cpu_resp_bits_data_T_23 = cat(_io_cpu_resp_bits_data_T_22, io_cpu_resp_bits_data_zeroed_2)
node _io_cpu_resp_bits_data_T_24 = or(_io_cpu_resp_bits_data_T_23, s2_sc_fail)
connect io.cpu.resp.bits.data, _io_cpu_resp_bits_data_T_24
node _io_cpu_resp_bits_data_word_bypass_shifted_T = bits(s2_req.addr, 2, 2)
node _io_cpu_resp_bits_data_word_bypass_shifted_T_1 = bits(s2_data_word_possibly_uncached, 63, 32)
node _io_cpu_resp_bits_data_word_bypass_shifted_T_2 = bits(s2_data_word_possibly_uncached, 31, 0)
node io_cpu_resp_bits_data_word_bypass_shifted = mux(_io_cpu_resp_bits_data_word_bypass_shifted_T, _io_cpu_resp_bits_data_word_bypass_shifted_T_1, _io_cpu_resp_bits_data_word_bypass_shifted_T_2)
node io_cpu_resp_bits_data_word_bypass_doZero = and(UInt<1>(0h0), s2_sc)
node io_cpu_resp_bits_data_word_bypass_zeroed = mux(io_cpu_resp_bits_data_word_bypass_doZero, UInt<1>(0h0), io_cpu_resp_bits_data_word_bypass_shifted)
node _io_cpu_resp_bits_data_word_bypass_T = eq(size, UInt<2>(0h2))
node _io_cpu_resp_bits_data_word_bypass_T_1 = or(_io_cpu_resp_bits_data_word_bypass_T, io_cpu_resp_bits_data_word_bypass_doZero)
node _io_cpu_resp_bits_data_word_bypass_T_2 = bits(io_cpu_resp_bits_data_word_bypass_zeroed, 31, 31)
node _io_cpu_resp_bits_data_word_bypass_T_3 = and(s2_req.signed, _io_cpu_resp_bits_data_word_bypass_T_2)
node _io_cpu_resp_bits_data_word_bypass_T_4 = mux(_io_cpu_resp_bits_data_word_bypass_T_3, UInt<32>(0hffffffff), UInt<32>(0h0))
node _io_cpu_resp_bits_data_word_bypass_T_5 = bits(s2_data_word_possibly_uncached, 63, 32)
node _io_cpu_resp_bits_data_word_bypass_T_6 = mux(_io_cpu_resp_bits_data_word_bypass_T_1, _io_cpu_resp_bits_data_word_bypass_T_4, _io_cpu_resp_bits_data_word_bypass_T_5)
node _io_cpu_resp_bits_data_word_bypass_T_7 = cat(_io_cpu_resp_bits_data_word_bypass_T_6, io_cpu_resp_bits_data_word_bypass_zeroed)
connect io.cpu.resp.bits.data_word_bypass, _io_cpu_resp_bits_data_word_bypass_T_7
connect io.cpu.resp.bits.data_raw, s2_data_word
connect io.cpu.resp.bits.store_data, pstore1_data
inst amoalus_0 of AMOALU
connect amoalus_0.clock, clock
connect amoalus_0.reset, reset
node _amoalu_io_mask_T = shr(pstore1_mask, 0)
connect amoalus_0.io.mask, _amoalu_io_mask_T
connect amoalus_0.io.cmd, pstore1_cmd
node _amoalu_io_lhs_T = shr(s2_data_word, 0)
connect amoalus_0.io.lhs, _amoalu_io_lhs_T
node _amoalu_io_rhs_T = shr(pstore1_data, 0)
connect amoalus_0.io.rhs, _amoalu_io_rhs_T
node _pstore1_storegen_data_mask_T = mux(s2_correct, UInt<1>(0h0), pstore1_mask)
node _pstore1_storegen_data_mask_T_1 = bits(_pstore1_storegen_data_mask_T, 0, 0)
node _pstore1_storegen_data_mask_T_2 = bits(_pstore1_storegen_data_mask_T, 1, 1)
node _pstore1_storegen_data_mask_T_3 = bits(_pstore1_storegen_data_mask_T, 2, 2)
node _pstore1_storegen_data_mask_T_4 = bits(_pstore1_storegen_data_mask_T, 3, 3)
node _pstore1_storegen_data_mask_T_5 = bits(_pstore1_storegen_data_mask_T, 4, 4)
node _pstore1_storegen_data_mask_T_6 = bits(_pstore1_storegen_data_mask_T, 5, 5)
node _pstore1_storegen_data_mask_T_7 = bits(_pstore1_storegen_data_mask_T, 6, 6)
node _pstore1_storegen_data_mask_T_8 = bits(_pstore1_storegen_data_mask_T, 7, 7)
node _pstore1_storegen_data_mask_T_9 = mux(_pstore1_storegen_data_mask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _pstore1_storegen_data_mask_T_10 = mux(_pstore1_storegen_data_mask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _pstore1_storegen_data_mask_T_11 = mux(_pstore1_storegen_data_mask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _pstore1_storegen_data_mask_T_12 = mux(_pstore1_storegen_data_mask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _pstore1_storegen_data_mask_T_13 = mux(_pstore1_storegen_data_mask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _pstore1_storegen_data_mask_T_14 = mux(_pstore1_storegen_data_mask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _pstore1_storegen_data_mask_T_15 = mux(_pstore1_storegen_data_mask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node _pstore1_storegen_data_mask_T_16 = mux(_pstore1_storegen_data_mask_T_8, UInt<8>(0hff), UInt<8>(0h0))
node pstore1_storegen_data_mask_lo_lo = cat(_pstore1_storegen_data_mask_T_10, _pstore1_storegen_data_mask_T_9)
node pstore1_storegen_data_mask_lo_hi = cat(_pstore1_storegen_data_mask_T_12, _pstore1_storegen_data_mask_T_11)
node pstore1_storegen_data_mask_lo = cat(pstore1_storegen_data_mask_lo_hi, pstore1_storegen_data_mask_lo_lo)
node pstore1_storegen_data_mask_hi_lo = cat(_pstore1_storegen_data_mask_T_14, _pstore1_storegen_data_mask_T_13)
node pstore1_storegen_data_mask_hi_hi = cat(_pstore1_storegen_data_mask_T_16, _pstore1_storegen_data_mask_T_15)
node pstore1_storegen_data_mask_hi = cat(pstore1_storegen_data_mask_hi_hi, pstore1_storegen_data_mask_hi_lo)
node pstore1_storegen_data_mask = cat(pstore1_storegen_data_mask_hi, pstore1_storegen_data_mask_lo)
node _pstore1_storegen_data_T = and(amoalus_0.io.out_unmasked, pstore1_storegen_data_mask)
node _pstore1_storegen_data_T_1 = not(pstore1_storegen_data_mask)
node _pstore1_storegen_data_T_2 = and(s2_data_word_corrected, _pstore1_storegen_data_T_1)
node _pstore1_storegen_data_T_3 = or(_pstore1_storegen_data_T, _pstore1_storegen_data_T_2)
connect pstore1_storegen_data, _pstore1_storegen_data_T_3
node flushCounterNext = add(flushCounter, UInt<1>(0h1))
node _flushDone_T = shr(flushCounterNext, 5)
node flushDone = eq(_flushDone_T, UInt<1>(0h1))
node flushCounterWrap = bits(flushCounterNext, 4, 0)
node _T_122 = and(s2_valid_masked, s2_cmd_flush_all)
node _T_123 = and(_T_122, s2_meta_error)
node _T_124 = and(s2_valid_masked, s2_cmd_flush_all)
node _T_125 = and(_T_124, s2_data_error)
node _s1_flush_valid_T = and(metaArb.io.in[5].ready, metaArb.io.in[5].valid)
node _s1_flush_valid_T_1 = eq(s1_flush_valid, UInt<1>(0h0))
node _s1_flush_valid_T_2 = and(_s1_flush_valid_T, _s1_flush_valid_T_1)
node _s1_flush_valid_T_3 = eq(s2_flush_valid_pre_tag_ecc, UInt<1>(0h0))
node _s1_flush_valid_T_4 = and(_s1_flush_valid_T_2, _s1_flush_valid_T_3)
node _s1_flush_valid_T_5 = eq(release_state, UInt<4>(0h0))
node _s1_flush_valid_T_6 = and(_s1_flush_valid_T_4, _s1_flush_valid_T_5)
node _s1_flush_valid_T_7 = eq(release_ack_wait, UInt<1>(0h0))
node _s1_flush_valid_T_8 = and(_s1_flush_valid_T_6, _s1_flush_valid_T_7)
connect s1_flush_valid, _s1_flush_valid_T_8
node _metaArb_io_in_5_valid_T = eq(flushed, UInt<1>(0h0))
node _metaArb_io_in_5_valid_T_1 = and(flushing, _metaArb_io_in_5_valid_T)
connect metaArb.io.in[5].valid, _metaArb_io_in_5_valid_T_1
connect metaArb.io.in[5].bits.write, UInt<1>(0h0)
node _metaArb_io_in_5_bits_idx_T = bits(flushCounter, 4, 0)
connect metaArb.io.in[5].bits.idx, _metaArb_io_in_5_bits_idx_T
node _metaArb_io_in_5_bits_addr_T = shr(io.cpu.req.bits.addr, 11)
node _metaArb_io_in_5_bits_addr_T_1 = shl(metaArb.io.in[5].bits.idx, 6)
node _metaArb_io_in_5_bits_addr_T_2 = cat(_metaArb_io_in_5_bits_addr_T, _metaArb_io_in_5_bits_addr_T_1)
connect metaArb.io.in[5].bits.addr, _metaArb_io_in_5_bits_addr_T_2
connect metaArb.io.in[5].bits.way_en, metaArb.io.in[4].bits.way_en
connect metaArb.io.in[5].bits.data, metaArb.io.in[4].bits.data
connect metaArb.io.in[0].valid, resetting
connect metaArb.io.in[0].bits.data, metaArb.io.in[5].bits.data
connect metaArb.io.in[0].bits.way_en, metaArb.io.in[5].bits.way_en
connect metaArb.io.in[0].bits.idx, metaArb.io.in[5].bits.idx
connect metaArb.io.in[0].bits.addr, metaArb.io.in[5].bits.addr
connect metaArb.io.in[0].bits.write, metaArb.io.in[5].bits.write
connect metaArb.io.in[0].bits.write, UInt<1>(0h1)
node _metaArb_io_in_0_bits_way_en_T = not(UInt<1>(0h0))
connect metaArb.io.in[0].bits.way_en, _metaArb_io_in_0_bits_way_en_T
wire metaArb_io_in_0_bits_data_meta : { state : UInt<2>}
connect metaArb_io_in_0_bits_data_meta.state, UInt<2>(0h0)
wire metaArb_io_in_0_bits_data_meta_1 : { coh : { state : UInt<2>}, tag : UInt<21>}
connect metaArb_io_in_0_bits_data_meta_1.tag, UInt<1>(0h0)
connect metaArb_io_in_0_bits_data_meta_1.coh, metaArb_io_in_0_bits_data_meta
node _metaArb_io_in_0_bits_data_T = cat(metaArb_io_in_0_bits_data_meta_1.coh.state, metaArb_io_in_0_bits_data_meta_1.tag)
connect metaArb.io.in[0].bits.data, _metaArb_io_in_0_bits_data_T
when resetting :
connect flushCounter, flushCounterNext
when flushDone :
connect resetting, UInt<1>(0h0)
node _clock_en_reg_T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _clock_en_reg_T_1 = bits(io.ptw.customCSRs.csrs[0].value, 0, 0)
node _clock_en_reg_T_2 = or(_clock_en_reg_T, _clock_en_reg_T_1)
node _clock_en_reg_T_3 = or(_clock_en_reg_T_2, io.cpu.keep_clock_enabled)
node _clock_en_reg_T_4 = or(_clock_en_reg_T_3, metaArb.io.out.valid)
node _clock_en_reg_T_5 = or(_clock_en_reg_T_4, s1_probe)
node _clock_en_reg_T_6 = or(_clock_en_reg_T_5, s2_probe)
node _clock_en_reg_T_7 = or(_clock_en_reg_T_6, s1_valid)
node _clock_en_reg_T_8 = or(_clock_en_reg_T_7, s2_valid)
node _clock_en_reg_T_9 = or(_clock_en_reg_T_8, io.tlb_port.req.valid)
node _clock_en_reg_T_10 = or(_clock_en_reg_T_9, s1_tlb_req_valid)
node _clock_en_reg_T_11 = or(_clock_en_reg_T_10, s2_tlb_req_valid)
node _clock_en_reg_T_12 = or(_clock_en_reg_T_11, pstore1_held)
node _clock_en_reg_T_13 = or(_clock_en_reg_T_12, pstore2_valid)
node _clock_en_reg_T_14 = neq(release_state, UInt<4>(0h0))
node _clock_en_reg_T_15 = or(_clock_en_reg_T_13, _clock_en_reg_T_14)
node _clock_en_reg_T_16 = or(_clock_en_reg_T_15, release_ack_wait)
node _clock_en_reg_T_17 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _clock_en_reg_T_18 = or(_clock_en_reg_T_16, _clock_en_reg_T_17)
node _clock_en_reg_T_19 = eq(tlb.io.req.ready, UInt<1>(0h0))
node _clock_en_reg_T_20 = or(_clock_en_reg_T_18, _clock_en_reg_T_19)
node _clock_en_reg_T_21 = or(_clock_en_reg_T_20, cached_grant_wait)
node _clock_en_reg_T_22 = orr(uncachedInFlight[0])
node _clock_en_reg_T_23 = or(_clock_en_reg_T_21, _clock_en_reg_T_22)
node _clock_en_reg_T_24 = gt(lrscCount, UInt<1>(0h0))
node _clock_en_reg_T_25 = or(_clock_en_reg_T_23, _clock_en_reg_T_24)
node _clock_en_reg_T_26 = gt(blockProbeAfterGrantCount, UInt<1>(0h0))
node _clock_en_reg_T_27 = or(_clock_en_reg_T_25, _clock_en_reg_T_26)
connect clock_en_reg, _clock_en_reg_T_27
node _io_cpu_perf_acquire_T = and(tl_out_a.ready, tl_out_a.valid)
node _io_cpu_perf_acquire_beats1_decode_T = dshl(UInt<12>(0hfff), tl_out_a.bits.size)
node _io_cpu_perf_acquire_beats1_decode_T_1 = bits(_io_cpu_perf_acquire_beats1_decode_T, 11, 0)
node _io_cpu_perf_acquire_beats1_decode_T_2 = not(_io_cpu_perf_acquire_beats1_decode_T_1)
node io_cpu_perf_acquire_beats1_decode = shr(_io_cpu_perf_acquire_beats1_decode_T_2, 3)
node _io_cpu_perf_acquire_beats1_opdata_T = bits(tl_out_a.bits.opcode, 2, 2)
node io_cpu_perf_acquire_beats1_opdata = eq(_io_cpu_perf_acquire_beats1_opdata_T, UInt<1>(0h0))
node io_cpu_perf_acquire_beats1 = mux(io_cpu_perf_acquire_beats1_opdata, io_cpu_perf_acquire_beats1_decode, UInt<1>(0h0))
regreset io_cpu_perf_acquire_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _io_cpu_perf_acquire_counter1_T = sub(io_cpu_perf_acquire_counter, UInt<1>(0h1))
node io_cpu_perf_acquire_counter1 = tail(_io_cpu_perf_acquire_counter1_T, 1)
node io_cpu_perf_acquire_first = eq(io_cpu_perf_acquire_counter, UInt<1>(0h0))
node _io_cpu_perf_acquire_last_T = eq(io_cpu_perf_acquire_counter, UInt<1>(0h1))
node _io_cpu_perf_acquire_last_T_1 = eq(io_cpu_perf_acquire_beats1, UInt<1>(0h0))
node io_cpu_perf_acquire_last = or(_io_cpu_perf_acquire_last_T, _io_cpu_perf_acquire_last_T_1)
node io_cpu_perf_acquire_done = and(io_cpu_perf_acquire_last, _io_cpu_perf_acquire_T)
node _io_cpu_perf_acquire_count_T = not(io_cpu_perf_acquire_counter1)
node io_cpu_perf_acquire_count = and(io_cpu_perf_acquire_beats1, _io_cpu_perf_acquire_count_T)
when _io_cpu_perf_acquire_T :
node _io_cpu_perf_acquire_counter_T = mux(io_cpu_perf_acquire_first, io_cpu_perf_acquire_beats1, io_cpu_perf_acquire_counter1)
connect io_cpu_perf_acquire_counter, _io_cpu_perf_acquire_counter_T
connect io.cpu.perf.acquire, io_cpu_perf_acquire_done
node _io_cpu_perf_release_T = and(tl_out_c.ready, tl_out_c.valid)
node _io_cpu_perf_release_beats1_decode_T = dshl(UInt<12>(0hfff), tl_out_c.bits.size)
node _io_cpu_perf_release_beats1_decode_T_1 = bits(_io_cpu_perf_release_beats1_decode_T, 11, 0)
node _io_cpu_perf_release_beats1_decode_T_2 = not(_io_cpu_perf_release_beats1_decode_T_1)
node io_cpu_perf_release_beats1_decode = shr(_io_cpu_perf_release_beats1_decode_T_2, 3)
node io_cpu_perf_release_beats1_opdata = bits(tl_out_c.bits.opcode, 0, 0)
node io_cpu_perf_release_beats1 = mux(UInt<1>(0h0), io_cpu_perf_release_beats1_decode, UInt<1>(0h0))
regreset io_cpu_perf_release_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _io_cpu_perf_release_counter1_T = sub(io_cpu_perf_release_counter, UInt<1>(0h1))
node io_cpu_perf_release_counter1 = tail(_io_cpu_perf_release_counter1_T, 1)
node io_cpu_perf_release_first = eq(io_cpu_perf_release_counter, UInt<1>(0h0))
node _io_cpu_perf_release_last_T = eq(io_cpu_perf_release_counter, UInt<1>(0h1))
node _io_cpu_perf_release_last_T_1 = eq(io_cpu_perf_release_beats1, UInt<1>(0h0))
node io_cpu_perf_release_last = or(_io_cpu_perf_release_last_T, _io_cpu_perf_release_last_T_1)
node io_cpu_perf_release_done = and(io_cpu_perf_release_last, _io_cpu_perf_release_T)
node _io_cpu_perf_release_count_T = not(io_cpu_perf_release_counter1)
node io_cpu_perf_release_count = and(io_cpu_perf_release_beats1, _io_cpu_perf_release_count_T)
when _io_cpu_perf_release_T :
node _io_cpu_perf_release_counter_T = mux(io_cpu_perf_release_first, io_cpu_perf_release_beats1, io_cpu_perf_release_counter1)
connect io_cpu_perf_release_counter, _io_cpu_perf_release_counter_T
connect io.cpu.perf.release, io_cpu_perf_release_done
node _io_cpu_perf_grant_T = and(nodeOut.d.valid, d_last)
connect io.cpu.perf.grant, _io_cpu_perf_grant_T
node _io_cpu_perf_tlbMiss_T = and(io.ptw.req.ready, io.ptw.req.valid)
connect io.cpu.perf.tlbMiss, _io_cpu_perf_tlbMiss_T
node _io_cpu_perf_storeBufferEmptyAfterLoad_T = and(s1_valid, s1_write)
node _io_cpu_perf_storeBufferEmptyAfterLoad_T_1 = and(s2_valid, s2_write)
node _io_cpu_perf_storeBufferEmptyAfterLoad_T_2 = eq(s2_waw_hazard, UInt<1>(0h0))
node _io_cpu_perf_storeBufferEmptyAfterLoad_T_3 = and(_io_cpu_perf_storeBufferEmptyAfterLoad_T_1, _io_cpu_perf_storeBufferEmptyAfterLoad_T_2)
node _io_cpu_perf_storeBufferEmptyAfterLoad_T_4 = or(_io_cpu_perf_storeBufferEmptyAfterLoad_T_3, pstore1_held)
node _io_cpu_perf_storeBufferEmptyAfterLoad_T_5 = or(_io_cpu_perf_storeBufferEmptyAfterLoad_T, _io_cpu_perf_storeBufferEmptyAfterLoad_T_4)
node _io_cpu_perf_storeBufferEmptyAfterLoad_T_6 = or(_io_cpu_perf_storeBufferEmptyAfterLoad_T_5, pstore2_valid)
node _io_cpu_perf_storeBufferEmptyAfterLoad_T_7 = eq(_io_cpu_perf_storeBufferEmptyAfterLoad_T_6, UInt<1>(0h0))
connect io.cpu.perf.storeBufferEmptyAfterLoad, _io_cpu_perf_storeBufferEmptyAfterLoad_T_7
node _io_cpu_perf_storeBufferEmptyAfterStore_T = and(s1_valid, s1_write)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_1 = and(s2_valid, s2_write)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_2 = and(_io_cpu_perf_storeBufferEmptyAfterStore_T_1, pstore1_rmw)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_3 = or(_io_cpu_perf_storeBufferEmptyAfterStore_T, _io_cpu_perf_storeBufferEmptyAfterStore_T_2)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_4 = and(s2_valid, s2_write)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_5 = eq(s2_waw_hazard, UInt<1>(0h0))
node _io_cpu_perf_storeBufferEmptyAfterStore_T_6 = and(_io_cpu_perf_storeBufferEmptyAfterStore_T_4, _io_cpu_perf_storeBufferEmptyAfterStore_T_5)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_7 = or(_io_cpu_perf_storeBufferEmptyAfterStore_T_6, pstore1_held)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_8 = and(_io_cpu_perf_storeBufferEmptyAfterStore_T_7, pstore2_valid)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_9 = or(_io_cpu_perf_storeBufferEmptyAfterStore_T_3, _io_cpu_perf_storeBufferEmptyAfterStore_T_8)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_10 = eq(_io_cpu_perf_storeBufferEmptyAfterStore_T_9, UInt<1>(0h0))
connect io.cpu.perf.storeBufferEmptyAfterStore, _io_cpu_perf_storeBufferEmptyAfterStore_T_10
node _io_cpu_perf_canAcceptStoreThenLoad_T = and(s2_valid, s2_write)
node _io_cpu_perf_canAcceptStoreThenLoad_T_1 = and(_io_cpu_perf_canAcceptStoreThenLoad_T, pstore1_rmw)
node _io_cpu_perf_canAcceptStoreThenLoad_T_2 = and(s1_valid, s1_write)
node _io_cpu_perf_canAcceptStoreThenLoad_T_3 = eq(s1_waw_hazard, UInt<1>(0h0))
node _io_cpu_perf_canAcceptStoreThenLoad_T_4 = and(_io_cpu_perf_canAcceptStoreThenLoad_T_2, _io_cpu_perf_canAcceptStoreThenLoad_T_3)
node _io_cpu_perf_canAcceptStoreThenLoad_T_5 = and(_io_cpu_perf_canAcceptStoreThenLoad_T_1, _io_cpu_perf_canAcceptStoreThenLoad_T_4)
node _io_cpu_perf_canAcceptStoreThenLoad_T_6 = and(pstore2_valid, pstore1_valid_likely)
node _io_cpu_perf_canAcceptStoreThenLoad_T_7 = and(s1_valid, s1_write)
node _io_cpu_perf_canAcceptStoreThenLoad_T_8 = and(_io_cpu_perf_canAcceptStoreThenLoad_T_6, _io_cpu_perf_canAcceptStoreThenLoad_T_7)
node _io_cpu_perf_canAcceptStoreThenLoad_T_9 = or(_io_cpu_perf_canAcceptStoreThenLoad_T_5, _io_cpu_perf_canAcceptStoreThenLoad_T_8)
node _io_cpu_perf_canAcceptStoreThenLoad_T_10 = eq(_io_cpu_perf_canAcceptStoreThenLoad_T_9, UInt<1>(0h0))
connect io.cpu.perf.canAcceptStoreThenLoad, _io_cpu_perf_canAcceptStoreThenLoad_T_10
node _io_cpu_perf_canAcceptStoreThenRMW_T = eq(pstore2_valid, UInt<1>(0h0))
node _io_cpu_perf_canAcceptStoreThenRMW_T_1 = and(io.cpu.perf.canAcceptStoreThenLoad, _io_cpu_perf_canAcceptStoreThenRMW_T)
connect io.cpu.perf.canAcceptStoreThenRMW, _io_cpu_perf_canAcceptStoreThenRMW_T_1
node _io_cpu_perf_canAcceptLoadThenLoad_T = and(s1_valid, s1_write)
node _io_cpu_perf_canAcceptLoadThenLoad_T_1 = eq(s1_req.cmd, UInt<1>(0h0))
node _io_cpu_perf_canAcceptLoadThenLoad_T_2 = eq(s1_req.cmd, UInt<5>(0h10))
node _io_cpu_perf_canAcceptLoadThenLoad_T_3 = eq(s1_req.cmd, UInt<3>(0h6))
node _io_cpu_perf_canAcceptLoadThenLoad_T_4 = eq(s1_req.cmd, UInt<3>(0h7))
node _io_cpu_perf_canAcceptLoadThenLoad_T_5 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_1, _io_cpu_perf_canAcceptLoadThenLoad_T_2)
node _io_cpu_perf_canAcceptLoadThenLoad_T_6 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_5, _io_cpu_perf_canAcceptLoadThenLoad_T_3)
node _io_cpu_perf_canAcceptLoadThenLoad_T_7 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_6, _io_cpu_perf_canAcceptLoadThenLoad_T_4)
node _io_cpu_perf_canAcceptLoadThenLoad_T_8 = eq(s1_req.cmd, UInt<3>(0h4))
node _io_cpu_perf_canAcceptLoadThenLoad_T_9 = eq(s1_req.cmd, UInt<4>(0h9))
node _io_cpu_perf_canAcceptLoadThenLoad_T_10 = eq(s1_req.cmd, UInt<4>(0ha))
node _io_cpu_perf_canAcceptLoadThenLoad_T_11 = eq(s1_req.cmd, UInt<4>(0hb))
node _io_cpu_perf_canAcceptLoadThenLoad_T_12 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_8, _io_cpu_perf_canAcceptLoadThenLoad_T_9)
node _io_cpu_perf_canAcceptLoadThenLoad_T_13 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_12, _io_cpu_perf_canAcceptLoadThenLoad_T_10)
node _io_cpu_perf_canAcceptLoadThenLoad_T_14 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_13, _io_cpu_perf_canAcceptLoadThenLoad_T_11)
node _io_cpu_perf_canAcceptLoadThenLoad_T_15 = eq(s1_req.cmd, UInt<4>(0h8))
node _io_cpu_perf_canAcceptLoadThenLoad_T_16 = eq(s1_req.cmd, UInt<4>(0hc))
node _io_cpu_perf_canAcceptLoadThenLoad_T_17 = eq(s1_req.cmd, UInt<4>(0hd))
node _io_cpu_perf_canAcceptLoadThenLoad_T_18 = eq(s1_req.cmd, UInt<4>(0he))
node _io_cpu_perf_canAcceptLoadThenLoad_T_19 = eq(s1_req.cmd, UInt<4>(0hf))
node _io_cpu_perf_canAcceptLoadThenLoad_T_20 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_15, _io_cpu_perf_canAcceptLoadThenLoad_T_16)
node _io_cpu_perf_canAcceptLoadThenLoad_T_21 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_20, _io_cpu_perf_canAcceptLoadThenLoad_T_17)
node _io_cpu_perf_canAcceptLoadThenLoad_T_22 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_21, _io_cpu_perf_canAcceptLoadThenLoad_T_18)
node _io_cpu_perf_canAcceptLoadThenLoad_T_23 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_22, _io_cpu_perf_canAcceptLoadThenLoad_T_19)
node _io_cpu_perf_canAcceptLoadThenLoad_T_24 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_14, _io_cpu_perf_canAcceptLoadThenLoad_T_23)
node _io_cpu_perf_canAcceptLoadThenLoad_T_25 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_7, _io_cpu_perf_canAcceptLoadThenLoad_T_24)
node _io_cpu_perf_canAcceptLoadThenLoad_T_26 = eq(s1_req.cmd, UInt<1>(0h1))
node _io_cpu_perf_canAcceptLoadThenLoad_T_27 = eq(s1_req.cmd, UInt<5>(0h11))
node _io_cpu_perf_canAcceptLoadThenLoad_T_28 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_26, _io_cpu_perf_canAcceptLoadThenLoad_T_27)
node _io_cpu_perf_canAcceptLoadThenLoad_T_29 = eq(s1_req.cmd, UInt<3>(0h7))
node _io_cpu_perf_canAcceptLoadThenLoad_T_30 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_28, _io_cpu_perf_canAcceptLoadThenLoad_T_29)
node _io_cpu_perf_canAcceptLoadThenLoad_T_31 = eq(s1_req.cmd, UInt<3>(0h4))
node _io_cpu_perf_canAcceptLoadThenLoad_T_32 = eq(s1_req.cmd, UInt<4>(0h9))
node _io_cpu_perf_canAcceptLoadThenLoad_T_33 = eq(s1_req.cmd, UInt<4>(0ha))
node _io_cpu_perf_canAcceptLoadThenLoad_T_34 = eq(s1_req.cmd, UInt<4>(0hb))
node _io_cpu_perf_canAcceptLoadThenLoad_T_35 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_31, _io_cpu_perf_canAcceptLoadThenLoad_T_32)
node _io_cpu_perf_canAcceptLoadThenLoad_T_36 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_35, _io_cpu_perf_canAcceptLoadThenLoad_T_33)
node _io_cpu_perf_canAcceptLoadThenLoad_T_37 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_36, _io_cpu_perf_canAcceptLoadThenLoad_T_34)
node _io_cpu_perf_canAcceptLoadThenLoad_T_38 = eq(s1_req.cmd, UInt<4>(0h8))
node _io_cpu_perf_canAcceptLoadThenLoad_T_39 = eq(s1_req.cmd, UInt<4>(0hc))
node _io_cpu_perf_canAcceptLoadThenLoad_T_40 = eq(s1_req.cmd, UInt<4>(0hd))
node _io_cpu_perf_canAcceptLoadThenLoad_T_41 = eq(s1_req.cmd, UInt<4>(0he))
node _io_cpu_perf_canAcceptLoadThenLoad_T_42 = eq(s1_req.cmd, UInt<4>(0hf))
node _io_cpu_perf_canAcceptLoadThenLoad_T_43 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_38, _io_cpu_perf_canAcceptLoadThenLoad_T_39)
node _io_cpu_perf_canAcceptLoadThenLoad_T_44 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_43, _io_cpu_perf_canAcceptLoadThenLoad_T_40)
node _io_cpu_perf_canAcceptLoadThenLoad_T_45 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_44, _io_cpu_perf_canAcceptLoadThenLoad_T_41)
node _io_cpu_perf_canAcceptLoadThenLoad_T_46 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_45, _io_cpu_perf_canAcceptLoadThenLoad_T_42)
node _io_cpu_perf_canAcceptLoadThenLoad_T_47 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_37, _io_cpu_perf_canAcceptLoadThenLoad_T_46)
node _io_cpu_perf_canAcceptLoadThenLoad_T_48 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_30, _io_cpu_perf_canAcceptLoadThenLoad_T_47)
node _io_cpu_perf_canAcceptLoadThenLoad_T_49 = eq(s1_req.cmd, UInt<5>(0h11))
node _io_cpu_perf_canAcceptLoadThenLoad_T_50 = lt(s1_req.size, UInt<1>(0h0))
node _io_cpu_perf_canAcceptLoadThenLoad_T_51 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_49, _io_cpu_perf_canAcceptLoadThenLoad_T_50)
node _io_cpu_perf_canAcceptLoadThenLoad_T_52 = and(_io_cpu_perf_canAcceptLoadThenLoad_T_48, _io_cpu_perf_canAcceptLoadThenLoad_T_51)
node _io_cpu_perf_canAcceptLoadThenLoad_T_53 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_25, _io_cpu_perf_canAcceptLoadThenLoad_T_52)
node _io_cpu_perf_canAcceptLoadThenLoad_T_54 = and(_io_cpu_perf_canAcceptLoadThenLoad_T, _io_cpu_perf_canAcceptLoadThenLoad_T_53)
node _io_cpu_perf_canAcceptLoadThenLoad_T_55 = and(s2_valid, s2_write)
node _io_cpu_perf_canAcceptLoadThenLoad_T_56 = eq(s2_waw_hazard, UInt<1>(0h0))
node _io_cpu_perf_canAcceptLoadThenLoad_T_57 = and(_io_cpu_perf_canAcceptLoadThenLoad_T_55, _io_cpu_perf_canAcceptLoadThenLoad_T_56)
node _io_cpu_perf_canAcceptLoadThenLoad_T_58 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_57, pstore1_held)
node _io_cpu_perf_canAcceptLoadThenLoad_T_59 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_58, pstore2_valid)
node _io_cpu_perf_canAcceptLoadThenLoad_T_60 = and(_io_cpu_perf_canAcceptLoadThenLoad_T_54, _io_cpu_perf_canAcceptLoadThenLoad_T_59)
node _io_cpu_perf_canAcceptLoadThenLoad_T_61 = eq(_io_cpu_perf_canAcceptLoadThenLoad_T_60, UInt<1>(0h0))
connect io.cpu.perf.canAcceptLoadThenLoad, _io_cpu_perf_canAcceptLoadThenLoad_T_61
regreset io_cpu_perf_blocked_near_end_of_refill_refill_count : UInt<3>, clock, reset, UInt<3>(0h0)
node _io_cpu_perf_blocked_near_end_of_refill_T = and(nodeOut.d.ready, nodeOut.d.valid)
node _io_cpu_perf_blocked_near_end_of_refill_T_1 = and(_io_cpu_perf_blocked_near_end_of_refill_T, grantIsRefill)
when _io_cpu_perf_blocked_near_end_of_refill_T_1 :
node _io_cpu_perf_blocked_near_end_of_refill_refill_count_T = add(io_cpu_perf_blocked_near_end_of_refill_refill_count, UInt<1>(0h1))
node _io_cpu_perf_blocked_near_end_of_refill_refill_count_T_1 = tail(_io_cpu_perf_blocked_near_end_of_refill_refill_count_T, 1)
connect io_cpu_perf_blocked_near_end_of_refill_refill_count, _io_cpu_perf_blocked_near_end_of_refill_refill_count_T_1
node io_cpu_perf_blocked_near_end_of_refill = geq(io_cpu_perf_blocked_near_end_of_refill_refill_count, UInt<3>(0h6))
node _io_cpu_perf_blocked_T = eq(io_cpu_perf_blocked_near_end_of_refill, UInt<1>(0h0))
node _io_cpu_perf_blocked_T_1 = and(cached_grant_wait, _io_cpu_perf_blocked_T)
connect io.cpu.perf.blocked, _io_cpu_perf_blocked_T_1
node _error_addr_T = bits(metaArb.io.in[1].bits.addr, 10, 6)
node _error_addr_T_1 = cat(s2_meta_corrected_0.tag, _error_addr_T)
node _error_addr_T_2 = shr(s2_req.addr, 6)
node _error_addr_T_3 = mux(metaArb.io.in[1].valid, _error_addr_T_1, _error_addr_T_2)
node error_addr = shl(_error_addr_T_3, 6)
node _io_errors_bus_valid_T = and(nodeOut.d.ready, nodeOut.d.valid)
node _io_errors_bus_valid_T_1 = or(nodeOut.d.bits.denied, nodeOut.d.bits.corrupt)
node _io_errors_bus_valid_T_2 = and(_io_errors_bus_valid_T, _io_errors_bus_valid_T_1)
connect io.errors.bus.valid, _io_errors_bus_valid_T_2
node _io_errors_bus_bits_T = shr(s2_req.addr, 6)
node _io_errors_bus_bits_T_1 = shl(_io_errors_bus_bits_T, 6)
node _io_errors_bus_bits_T_2 = mux(grantIsCached, _io_errors_bus_bits_T_1, UInt<1>(0h0))
connect io.errors.bus.bits, _io_errors_bus_bits_T_2
node _T_126 = and(io.errors.bus.valid, grantIsCached)
node _T_127 = eq(grantIsCached, UInt<1>(0h0))
node _T_128 = and(io.errors.bus.valid, _T_127)
node _T_129 = eq(s2_valid_data_error, UInt<1>(0h0))
node _T_130 = eq(s2_data_error_uncorrectable, UInt<1>(0h0))
node _T_131 = and(s2_valid_data_error, _T_130)
node _T_132 = and(s2_valid_data_error, s2_data_error_uncorrectable)
node _T_133 = eq(s2_req.no_xcpt, UInt<1>(0h0))
node _T_134 = and(_T_129, s2_req.no_xcpt)
node _T_135 = and(_T_129, _T_133)
node _T_136 = and(_T_131, s2_req.no_xcpt)
node _T_137 = and(_T_131, _T_133)
node _T_138 = and(_T_132, s2_req.no_xcpt)
node _T_139 = and(_T_132, _T_133) | module DCache( // @[DCache.scala:101:7]
input clock, // @[DCache.scala:101:7]
input reset, // @[DCache.scala:101:7]
input auto_hart_id_sink_in, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output io_cpu_req_ready, // @[HellaCache.scala:243:14]
input io_cpu_req_valid, // @[HellaCache.scala:243:14]
input [39:0] io_cpu_req_bits_addr, // @[HellaCache.scala:243:14]
input [7:0] io_cpu_req_bits_tag, // @[HellaCache.scala:243:14]
input [4:0] io_cpu_req_bits_cmd, // @[HellaCache.scala:243:14]
input [1:0] io_cpu_req_bits_size, // @[HellaCache.scala:243:14]
input io_cpu_req_bits_signed, // @[HellaCache.scala:243:14]
input [1:0] io_cpu_req_bits_dprv, // @[HellaCache.scala:243:14]
input io_cpu_req_bits_dv, // @[HellaCache.scala:243:14]
input io_cpu_req_bits_phys, // @[HellaCache.scala:243:14]
input io_cpu_req_bits_no_resp, // @[HellaCache.scala:243:14]
input io_cpu_req_bits_no_xcpt, // @[HellaCache.scala:243:14]
input io_cpu_s1_kill, // @[HellaCache.scala:243:14]
input [63:0] io_cpu_s1_data_data, // @[HellaCache.scala:243:14]
input [7:0] io_cpu_s1_data_mask, // @[HellaCache.scala:243:14]
output io_cpu_s2_nack, // @[HellaCache.scala:243:14]
output io_cpu_s2_nack_cause_raw, // @[HellaCache.scala:243:14]
output io_cpu_s2_uncached, // @[HellaCache.scala:243:14]
output [31:0] io_cpu_s2_paddr, // @[HellaCache.scala:243:14]
output io_cpu_resp_valid, // @[HellaCache.scala:243:14]
output [39:0] io_cpu_resp_bits_addr, // @[HellaCache.scala:243:14]
output [7:0] io_cpu_resp_bits_tag, // @[HellaCache.scala:243:14]
output [4:0] io_cpu_resp_bits_cmd, // @[HellaCache.scala:243:14]
output [1:0] io_cpu_resp_bits_size, // @[HellaCache.scala:243:14]
output io_cpu_resp_bits_signed, // @[HellaCache.scala:243:14]
output [1:0] io_cpu_resp_bits_dprv, // @[HellaCache.scala:243:14]
output io_cpu_resp_bits_dv, // @[HellaCache.scala:243:14]
output [63:0] io_cpu_resp_bits_data, // @[HellaCache.scala:243:14]
output [7:0] io_cpu_resp_bits_mask, // @[HellaCache.scala:243:14]
output io_cpu_resp_bits_replay, // @[HellaCache.scala:243:14]
output io_cpu_resp_bits_has_data, // @[HellaCache.scala:243:14]
output [63:0] io_cpu_resp_bits_data_word_bypass, // @[HellaCache.scala:243:14]
output [63:0] io_cpu_resp_bits_data_raw, // @[HellaCache.scala:243:14]
output [63:0] io_cpu_resp_bits_store_data, // @[HellaCache.scala:243:14]
output io_cpu_replay_next, // @[HellaCache.scala:243:14]
output io_cpu_s2_xcpt_ma_ld, // @[HellaCache.scala:243:14]
output io_cpu_s2_xcpt_ma_st, // @[HellaCache.scala:243:14]
output io_cpu_s2_xcpt_pf_ld, // @[HellaCache.scala:243:14]
output io_cpu_s2_xcpt_pf_st, // @[HellaCache.scala:243:14]
output io_cpu_s2_xcpt_ae_ld, // @[HellaCache.scala:243:14]
output io_cpu_s2_xcpt_ae_st, // @[HellaCache.scala:243:14]
output [39:0] io_cpu_s2_gpa, // @[HellaCache.scala:243:14]
output io_cpu_ordered, // @[HellaCache.scala:243:14]
output io_cpu_store_pending, // @[HellaCache.scala:243:14]
output io_cpu_perf_acquire, // @[HellaCache.scala:243:14]
output io_cpu_perf_grant, // @[HellaCache.scala:243:14]
output io_cpu_perf_tlbMiss, // @[HellaCache.scala:243:14]
output io_cpu_perf_blocked, // @[HellaCache.scala:243:14]
output io_cpu_perf_canAcceptStoreThenLoad, // @[HellaCache.scala:243:14]
output io_cpu_perf_canAcceptStoreThenRMW, // @[HellaCache.scala:243:14]
output io_cpu_perf_canAcceptLoadThenLoad, // @[HellaCache.scala:243:14]
output io_cpu_perf_storeBufferEmptyAfterLoad, // @[HellaCache.scala:243:14]
output io_cpu_perf_storeBufferEmptyAfterStore, // @[HellaCache.scala:243:14]
input io_cpu_keep_clock_enabled, // @[HellaCache.scala:243:14]
input io_ptw_req_ready, // @[HellaCache.scala:243:14]
output io_ptw_req_valid, // @[HellaCache.scala:243:14]
output [26:0] io_ptw_req_bits_bits_addr, // @[HellaCache.scala:243:14]
output io_ptw_req_bits_bits_need_gpa, // @[HellaCache.scala:243:14]
input io_ptw_resp_valid, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_ae_ptw, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_ae_final, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pf, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_gf, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_hr, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_hw, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_hx, // @[HellaCache.scala:243:14]
input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[HellaCache.scala:243:14]
input [43:0] io_ptw_resp_bits_pte_ppn, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pte_d, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pte_a, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pte_g, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pte_u, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pte_x, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pte_w, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pte_r, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pte_v, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_resp_bits_level, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_homogeneous, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_gpa_valid, // @[HellaCache.scala:243:14]
input [38:0] io_ptw_resp_bits_gpa_bits, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_gpa_is_pte, // @[HellaCache.scala:243:14]
input [3:0] io_ptw_ptbr_mode, // @[HellaCache.scala:243:14]
input [43:0] io_ptw_ptbr_ppn, // @[HellaCache.scala:243:14]
input io_ptw_status_debug, // @[HellaCache.scala:243:14]
input io_ptw_status_cease, // @[HellaCache.scala:243:14]
input io_ptw_status_wfi, // @[HellaCache.scala:243:14]
input [31:0] io_ptw_status_isa, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_status_dprv, // @[HellaCache.scala:243:14]
input io_ptw_status_dv, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_status_prv, // @[HellaCache.scala:243:14]
input io_ptw_status_v, // @[HellaCache.scala:243:14]
input io_ptw_status_sd, // @[HellaCache.scala:243:14]
input io_ptw_status_mpv, // @[HellaCache.scala:243:14]
input io_ptw_status_gva, // @[HellaCache.scala:243:14]
input io_ptw_status_tsr, // @[HellaCache.scala:243:14]
input io_ptw_status_tw, // @[HellaCache.scala:243:14]
input io_ptw_status_tvm, // @[HellaCache.scala:243:14]
input io_ptw_status_mxr, // @[HellaCache.scala:243:14]
input io_ptw_status_sum, // @[HellaCache.scala:243:14]
input io_ptw_status_mprv, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_status_fs, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_status_mpp, // @[HellaCache.scala:243:14]
input io_ptw_status_spp, // @[HellaCache.scala:243:14]
input io_ptw_status_mpie, // @[HellaCache.scala:243:14]
input io_ptw_status_spie, // @[HellaCache.scala:243:14]
input io_ptw_status_mie, // @[HellaCache.scala:243:14]
input io_ptw_status_sie, // @[HellaCache.scala:243:14]
input io_ptw_hstatus_spvp, // @[HellaCache.scala:243:14]
input io_ptw_hstatus_spv, // @[HellaCache.scala:243:14]
input io_ptw_hstatus_gva, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_debug, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_cease, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_wfi, // @[HellaCache.scala:243:14]
input [31:0] io_ptw_gstatus_isa, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_gstatus_dprv, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_dv, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_gstatus_prv, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_v, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_sd, // @[HellaCache.scala:243:14]
input [22:0] io_ptw_gstatus_zero2, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_mpv, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_gva, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_mbe, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_sbe, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_gstatus_sxl, // @[HellaCache.scala:243:14]
input [7:0] io_ptw_gstatus_zero1, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_tsr, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_tw, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_tvm, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_mxr, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_sum, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_mprv, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_gstatus_fs, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_gstatus_mpp, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_gstatus_vs, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_spp, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_mpie, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_ube, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_spie, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_upie, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_mie, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_hie, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_sie, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_uie, // @[HellaCache.scala:243:14]
input io_ptw_pmp_0_cfg_l, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_pmp_0_cfg_a, // @[HellaCache.scala:243:14]
input io_ptw_pmp_0_cfg_x, // @[HellaCache.scala:243:14]
input io_ptw_pmp_0_cfg_w, // @[HellaCache.scala:243:14]
input io_ptw_pmp_0_cfg_r, // @[HellaCache.scala:243:14]
input [29:0] io_ptw_pmp_0_addr, // @[HellaCache.scala:243:14]
input [31:0] io_ptw_pmp_0_mask, // @[HellaCache.scala:243:14]
input io_ptw_pmp_1_cfg_l, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_pmp_1_cfg_a, // @[HellaCache.scala:243:14]
input io_ptw_pmp_1_cfg_x, // @[HellaCache.scala:243:14]
input io_ptw_pmp_1_cfg_w, // @[HellaCache.scala:243:14]
input io_ptw_pmp_1_cfg_r, // @[HellaCache.scala:243:14]
input [29:0] io_ptw_pmp_1_addr, // @[HellaCache.scala:243:14]
input [31:0] io_ptw_pmp_1_mask, // @[HellaCache.scala:243:14]
input io_ptw_pmp_2_cfg_l, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_pmp_2_cfg_a, // @[HellaCache.scala:243:14]
input io_ptw_pmp_2_cfg_x, // @[HellaCache.scala:243:14]
input io_ptw_pmp_2_cfg_w, // @[HellaCache.scala:243:14]
input io_ptw_pmp_2_cfg_r, // @[HellaCache.scala:243:14]
input [29:0] io_ptw_pmp_2_addr, // @[HellaCache.scala:243:14]
input [31:0] io_ptw_pmp_2_mask, // @[HellaCache.scala:243:14]
input io_ptw_pmp_3_cfg_l, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_pmp_3_cfg_a, // @[HellaCache.scala:243:14]
input io_ptw_pmp_3_cfg_x, // @[HellaCache.scala:243:14]
input io_ptw_pmp_3_cfg_w, // @[HellaCache.scala:243:14]
input io_ptw_pmp_3_cfg_r, // @[HellaCache.scala:243:14]
input [29:0] io_ptw_pmp_3_addr, // @[HellaCache.scala:243:14]
input [31:0] io_ptw_pmp_3_mask, // @[HellaCache.scala:243:14]
input io_ptw_pmp_4_cfg_l, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_pmp_4_cfg_a, // @[HellaCache.scala:243:14]
input io_ptw_pmp_4_cfg_x, // @[HellaCache.scala:243:14]
input io_ptw_pmp_4_cfg_w, // @[HellaCache.scala:243:14]
input io_ptw_pmp_4_cfg_r, // @[HellaCache.scala:243:14]
input [29:0] io_ptw_pmp_4_addr, // @[HellaCache.scala:243:14]
input [31:0] io_ptw_pmp_4_mask, // @[HellaCache.scala:243:14]
input io_ptw_pmp_5_cfg_l, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_pmp_5_cfg_a, // @[HellaCache.scala:243:14]
input io_ptw_pmp_5_cfg_x, // @[HellaCache.scala:243:14]
input io_ptw_pmp_5_cfg_w, // @[HellaCache.scala:243:14]
input io_ptw_pmp_5_cfg_r, // @[HellaCache.scala:243:14]
input [29:0] io_ptw_pmp_5_addr, // @[HellaCache.scala:243:14]
input [31:0] io_ptw_pmp_5_mask, // @[HellaCache.scala:243:14]
input io_ptw_pmp_6_cfg_l, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_pmp_6_cfg_a, // @[HellaCache.scala:243:14]
input io_ptw_pmp_6_cfg_x, // @[HellaCache.scala:243:14]
input io_ptw_pmp_6_cfg_w, // @[HellaCache.scala:243:14]
input io_ptw_pmp_6_cfg_r, // @[HellaCache.scala:243:14]
input [29:0] io_ptw_pmp_6_addr, // @[HellaCache.scala:243:14]
input [31:0] io_ptw_pmp_6_mask, // @[HellaCache.scala:243:14]
input io_ptw_pmp_7_cfg_l, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_pmp_7_cfg_a, // @[HellaCache.scala:243:14]
input io_ptw_pmp_7_cfg_x, // @[HellaCache.scala:243:14]
input io_ptw_pmp_7_cfg_w, // @[HellaCache.scala:243:14]
input io_ptw_pmp_7_cfg_r, // @[HellaCache.scala:243:14]
input [29:0] io_ptw_pmp_7_addr, // @[HellaCache.scala:243:14]
input [31:0] io_ptw_pmp_7_mask, // @[HellaCache.scala:243:14]
input io_ptw_customCSRs_csrs_0_ren, // @[HellaCache.scala:243:14]
input io_ptw_customCSRs_csrs_0_wen, // @[HellaCache.scala:243:14]
input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[HellaCache.scala:243:14]
input [63:0] io_ptw_customCSRs_csrs_0_value, // @[HellaCache.scala:243:14]
input io_ptw_customCSRs_csrs_1_ren, // @[HellaCache.scala:243:14]
input io_ptw_customCSRs_csrs_1_wen, // @[HellaCache.scala:243:14]
input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[HellaCache.scala:243:14]
input [63:0] io_ptw_customCSRs_csrs_1_value, // @[HellaCache.scala:243:14]
input io_ptw_customCSRs_csrs_2_ren, // @[HellaCache.scala:243:14]
input io_ptw_customCSRs_csrs_2_wen, // @[HellaCache.scala:243:14]
input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[HellaCache.scala:243:14]
input [63:0] io_ptw_customCSRs_csrs_2_value, // @[HellaCache.scala:243:14]
input io_ptw_customCSRs_csrs_3_ren, // @[HellaCache.scala:243:14]
input io_ptw_customCSRs_csrs_3_wen, // @[HellaCache.scala:243:14]
input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[HellaCache.scala:243:14]
input [63:0] io_ptw_customCSRs_csrs_3_value // @[HellaCache.scala:243:14]
);
wire [63:0] s1_all_data_ways_0; // @[DCache.scala:325:33]
wire s0_req_phys; // @[DCache.scala:192:24]
wire [39:0] s0_req_addr; // @[DCache.scala:192:24]
wire tl_out_a_valid; // @[DCache.scala:159:22]
wire [63:0] tl_out_a_bits_data; // @[DCache.scala:159:22]
wire [7:0] tl_out_a_bits_mask; // @[DCache.scala:159:22]
wire [31:0] tl_out_a_bits_address; // @[DCache.scala:159:22]
wire [3:0] tl_out_a_bits_size; // @[DCache.scala:159:22]
wire [2:0] tl_out_a_bits_param; // @[DCache.scala:159:22]
wire [2:0] tl_out_a_bits_opcode; // @[DCache.scala:159:22]
wire metaArb_io_in_2_valid; // @[DCache.scala:135:28]
wire [4:0] pma_checker_io_req_bits_cmd; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_req_bits_size; // @[DCache.scala:120:32]
wire [63:0] _amoalus_0_io_out_unmasked; // @[DCache.scala:982:26]
wire _lfsr_prng_io_out_0; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_1; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_2; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_3; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_4; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_5; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_6; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_7; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_8; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_9; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_10; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_11; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_12; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_13; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_14; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_15; // @[PRNG.scala:91:22]
wire [19:0] _pma_checker_entries_barrier_12_io_y_ppn; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_hr; // @[package.scala:267:25]
wire [19:0] _pma_checker_entries_barrier_11_io_y_ppn; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_c; // @[package.scala:267:25]
wire [19:0] _pma_checker_entries_barrier_10_io_y_ppn; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_c; // @[package.scala:267:25]
wire [19:0] _pma_checker_entries_barrier_9_io_y_ppn; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_c; // @[package.scala:267:25]
wire [19:0] _pma_checker_entries_barrier_8_io_y_ppn; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_c; // @[package.scala:267:25]
wire _pma_checker_pma_io_resp_r; // @[TLB.scala:422:19]
wire _pma_checker_pma_io_resp_w; // @[TLB.scala:422:19]
wire _pma_checker_pma_io_resp_pp; // @[TLB.scala:422:19]
wire _pma_checker_pma_io_resp_al; // @[TLB.scala:422:19]
wire _pma_checker_pma_io_resp_aa; // @[TLB.scala:422:19]
wire _pma_checker_pma_io_resp_x; // @[TLB.scala:422:19]
wire _pma_checker_pma_io_resp_eff; // @[TLB.scala:422:19]
wire [19:0] _pma_checker_mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25]
wire _tlb_io_req_ready; // @[DCache.scala:119:19]
wire _tlb_io_resp_miss; // @[DCache.scala:119:19]
wire [31:0] _tlb_io_resp_paddr; // @[DCache.scala:119:19]
wire [39:0] _tlb_io_resp_gpa; // @[DCache.scala:119:19]
wire _tlb_io_resp_pf_ld; // @[DCache.scala:119:19]
wire _tlb_io_resp_pf_st; // @[DCache.scala:119:19]
wire _tlb_io_resp_pf_inst; // @[DCache.scala:119:19]
wire _tlb_io_resp_ae_ld; // @[DCache.scala:119:19]
wire _tlb_io_resp_ae_st; // @[DCache.scala:119:19]
wire _tlb_io_resp_ae_inst; // @[DCache.scala:119:19]
wire _tlb_io_resp_ma_ld; // @[DCache.scala:119:19]
wire _tlb_io_resp_ma_st; // @[DCache.scala:119:19]
wire _tlb_io_resp_cacheable; // @[DCache.scala:119:19]
wire _tlb_io_resp_must_alloc; // @[DCache.scala:119:19]
wire _tlb_io_resp_prefetchable; // @[DCache.scala:119:19]
wire [1:0] _tlb_io_resp_size; // @[DCache.scala:119:19]
wire [4:0] _tlb_io_resp_cmd; // @[DCache.scala:119:19]
wire auto_hart_id_sink_in_0 = auto_hart_id_sink_in; // @[DCache.scala:101:7]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[DCache.scala:101:7]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[DCache.scala:101:7]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[DCache.scala:101:7]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[DCache.scala:101:7]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[DCache.scala:101:7]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[DCache.scala:101:7]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[DCache.scala:101:7]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[DCache.scala:101:7]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[DCache.scala:101:7]
wire io_cpu_req_valid_0 = io_cpu_req_valid; // @[DCache.scala:101:7]
wire [39:0] io_cpu_req_bits_addr_0 = io_cpu_req_bits_addr; // @[DCache.scala:101:7]
wire [7:0] io_cpu_req_bits_tag_0 = io_cpu_req_bits_tag; // @[DCache.scala:101:7]
wire [4:0] io_cpu_req_bits_cmd_0 = io_cpu_req_bits_cmd; // @[DCache.scala:101:7]
wire [1:0] io_cpu_req_bits_size_0 = io_cpu_req_bits_size; // @[DCache.scala:101:7]
wire io_cpu_req_bits_signed_0 = io_cpu_req_bits_signed; // @[DCache.scala:101:7]
wire [1:0] io_cpu_req_bits_dprv_0 = io_cpu_req_bits_dprv; // @[DCache.scala:101:7]
wire io_cpu_req_bits_dv_0 = io_cpu_req_bits_dv; // @[DCache.scala:101:7]
wire io_cpu_req_bits_phys_0 = io_cpu_req_bits_phys; // @[DCache.scala:101:7]
wire io_cpu_req_bits_no_resp_0 = io_cpu_req_bits_no_resp; // @[DCache.scala:101:7]
wire io_cpu_req_bits_no_xcpt_0 = io_cpu_req_bits_no_xcpt; // @[DCache.scala:101:7]
wire io_cpu_s1_kill_0 = io_cpu_s1_kill; // @[DCache.scala:101:7]
wire [63:0] io_cpu_s1_data_data_0 = io_cpu_s1_data_data; // @[DCache.scala:101:7]
wire [7:0] io_cpu_s1_data_mask_0 = io_cpu_s1_data_mask; // @[DCache.scala:101:7]
wire io_cpu_keep_clock_enabled_0 = io_cpu_keep_clock_enabled; // @[DCache.scala:101:7]
wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[DCache.scala:101:7]
wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[DCache.scala:101:7]
wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[DCache.scala:101:7]
wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[DCache.scala:101:7]
wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[DCache.scala:101:7]
wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[DCache.scala:101:7]
wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[DCache.scala:101:7]
wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[DCache.scala:101:7]
wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[DCache.scala:101:7]
wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[DCache.scala:101:7]
wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[DCache.scala:101:7]
wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[DCache.scala:101:7]
wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[DCache.scala:101:7]
wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[DCache.scala:101:7]
wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[DCache.scala:101:7]
wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[DCache.scala:101:7]
wire io_ptw_status_v_0 = io_ptw_status_v; // @[DCache.scala:101:7]
wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[DCache.scala:101:7]
wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[DCache.scala:101:7]
wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[DCache.scala:101:7]
wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[DCache.scala:101:7]
wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[DCache.scala:101:7]
wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[DCache.scala:101:7]
wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[DCache.scala:101:7]
wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[DCache.scala:101:7]
wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[DCache.scala:101:7]
wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[DCache.scala:101:7]
wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[DCache.scala:101:7]
wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[DCache.scala:101:7]
wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[DCache.scala:101:7]
wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[DCache.scala:101:7]
wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[DCache.scala:101:7]
wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[DCache.scala:101:7]
wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[DCache.scala:101:7]
wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[DCache.scala:101:7]
wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[DCache.scala:101:7]
wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[DCache.scala:101:7]
wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[DCache.scala:101:7]
wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[DCache.scala:101:7]
wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[DCache.scala:101:7]
wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[DCache.scala:101:7]
wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[DCache.scala:101:7]
wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[DCache.scala:101:7]
wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[DCache.scala:101:7]
wire io_ptw_gstatus_sd_0 = io_ptw_gstatus_sd; // @[DCache.scala:101:7]
wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[DCache.scala:101:7]
wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[DCache.scala:101:7]
wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[DCache.scala:101:7]
wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[DCache.scala:101:7]
wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[DCache.scala:101:7]
wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[DCache.scala:101:7]
wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[DCache.scala:101:7]
wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[DCache.scala:101:7]
wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[DCache.scala:101:7]
wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[DCache.scala:101:7]
wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[DCache.scala:101:7]
wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[DCache.scala:101:7]
wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[DCache.scala:101:7]
wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[DCache.scala:101:7]
wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[DCache.scala:101:7]
wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[DCache.scala:101:7]
wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[DCache.scala:101:7]
wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[DCache.scala:101:7]
wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[DCache.scala:101:7]
wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[DCache.scala:101:7]
wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[DCache.scala:101:7]
wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[DCache.scala:101:7]
wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[DCache.scala:101:7]
wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[DCache.scala:101:7]
wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[DCache.scala:101:7]
wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[DCache.scala:101:7]
wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[DCache.scala:101:7]
wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[DCache.scala:101:7]
wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[DCache.scala:101:7]
wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[DCache.scala:101:7]
wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[DCache.scala:101:7]
wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[DCache.scala:101:7]
wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[DCache.scala:101:7]
wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[DCache.scala:101:7]
wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[DCache.scala:101:7]
wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[DCache.scala:101:7]
wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[DCache.scala:101:7]
wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[DCache.scala:101:7]
wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[DCache.scala:101:7]
wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[DCache.scala:101:7]
wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[DCache.scala:101:7]
wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[DCache.scala:101:7]
wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[DCache.scala:101:7]
wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[DCache.scala:101:7]
wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[DCache.scala:101:7]
wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[DCache.scala:101:7]
wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[DCache.scala:101:7]
wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[DCache.scala:101:7]
wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[DCache.scala:101:7]
wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[DCache.scala:101:7]
wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[DCache.scala:101:7]
wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[DCache.scala:101:7]
wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[DCache.scala:101:7]
wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[DCache.scala:101:7]
wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[DCache.scala:101:7]
wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[DCache.scala:101:7]
wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[DCache.scala:101:7]
wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[DCache.scala:101:7]
wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[DCache.scala:101:7]
wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[DCache.scala:101:7]
wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[DCache.scala:101:7]
wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[DCache.scala:101:7]
wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[DCache.scala:101:7]
wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[DCache.scala:101:7]
wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[DCache.scala:101:7]
wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[DCache.scala:101:7]
wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[DCache.scala:101:7]
wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[DCache.scala:101:7]
wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[DCache.scala:101:7]
wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[DCache.scala:101:7]
wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[DCache.scala:101:7]
wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[DCache.scala:101:7]
wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[DCache.scala:101:7]
wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[DCache.scala:101:7]
wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[DCache.scala:101:7]
wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[DCache.scala:101:7]
wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[DCache.scala:101:7]
wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[DCache.scala:101:7]
wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[DCache.scala:101:7]
wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[DCache.scala:101:7]
wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[DCache.scala:101:7]
wire _dataArb_io_in_3_valid_T_55 = reset; // @[DCache.scala:1186:11]
wire _pstore_drain_opportunistic_T_55 = reset; // @[DCache.scala:1186:11]
wire auto_mmio_address_prefix_sink_in = 1'h0; // @[DCache.scala:101:7]
wire auto_out_a_bits_source = 1'h0; // @[DCache.scala:101:7]
wire auto_out_a_bits_corrupt = 1'h0; // @[DCache.scala:101:7]
wire auto_out_d_bits_source = 1'h0; // @[DCache.scala:101:7]
wire io_cpu_req_bits_no_alloc = 1'h0; // @[DCache.scala:101:7]
wire io_cpu_s2_kill = 1'h0; // @[DCache.scala:101:7]
wire io_cpu_s2_xcpt_gf_ld = 1'h0; // @[DCache.scala:101:7]
wire io_cpu_s2_xcpt_gf_st = 1'h0; // @[DCache.scala:101:7]
wire io_cpu_s2_gpa_is_pte = 1'h0; // @[DCache.scala:101:7]
wire io_cpu_perf_release = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_status_mbe = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_status_sbe = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_status_sd_rv32 = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_status_ube = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_status_upie = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_status_hie = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_status_uie = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_hstatus_vtsr = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_hstatus_vtw = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_hstatus_vtvm = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_hstatus_hu = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_hstatus_vsbe = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_req_valid = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_req_bits_passthrough = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_req_bits_v = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_gpa_is_pte = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_gf_ld = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_gf_st = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_gf_inst = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_ma_inst = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_s2_kill = 1'h0; // @[DCache.scala:101:7]
wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire mmioAddressPrefixSinkNodeOptIn = 1'h0; // @[MixedNode.scala:551:17]
wire pma_checker_io_req_valid = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_resp_miss = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_resp_gpa_is_pte = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_resp_gf_ld = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_resp_gf_st = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_resp_gf_inst = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_resp_ma_inst = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_sfence_valid = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_sfence_bits_rs1 = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_sfence_bits_rs2 = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_sfence_bits_asid = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_sfence_bits_hv = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_sfence_bits_hg = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_req_ready = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_req_valid = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_req_bits_bits_need_gpa = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_req_bits_bits_vstage1 = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_req_bits_bits_stage2 = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_valid = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_ae_ptw = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_ae_final = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pf = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_gf = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_hr = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_hw = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_hx = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pte_d = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pte_a = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pte_g = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pte_u = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pte_x = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pte_w = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pte_r = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pte_v = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_homogeneous = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_gpa_valid = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_gpa_is_pte = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_debug = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_cease = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_wfi = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_dv = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_v = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_sd = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_mpv = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_gva = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_mbe = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_sbe = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_sd_rv32 = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_tsr = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_tw = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_tvm = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_mxr = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_sum = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_mprv = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_spp = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_mpie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_ube = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_spie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_upie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_mie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_hie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_sie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_uie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_hstatus_vtsr = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_hstatus_vtw = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_hstatus_vtvm = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_hstatus_hu = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_hstatus_spvp = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_hstatus_spv = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_hstatus_gva = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_hstatus_vsbe = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_debug = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_cease = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_wfi = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_dv = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_v = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_sd = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_mpv = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_gva = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_mbe = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_sbe = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_sd_rv32 = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_tsr = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_tw = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_tvm = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_mxr = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_sum = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_mprv = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_spp = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_mpie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_ube = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_spie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_upie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_mie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_hie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_sie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_uie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_0_cfg_l = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_0_cfg_x = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_0_cfg_w = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_0_cfg_r = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_1_cfg_l = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_1_cfg_x = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_1_cfg_w = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_1_cfg_r = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_2_cfg_l = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_2_cfg_x = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_2_cfg_w = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_2_cfg_r = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_3_cfg_l = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_3_cfg_x = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_3_cfg_w = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_3_cfg_r = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_4_cfg_l = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_4_cfg_x = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_4_cfg_w = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_4_cfg_r = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_5_cfg_l = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_5_cfg_x = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_5_cfg_w = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_5_cfg_r = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_6_cfg_l = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_6_cfg_x = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_6_cfg_w = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_6_cfg_r = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_7_cfg_l = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_7_cfg_x = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_7_cfg_w = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_7_cfg_r = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_0_set = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_1_set = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_2_ren = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_2_wen = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_2_set = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_3_ren = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_3_wen = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_3_set = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_kill = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_priv_v = 1'h0; // @[TLB.scala:369:34]
wire pma_checker__stage1_en_T = 1'h0; // @[TLB.scala:374:41]
wire pma_checker_stage1_en = 1'h0; // @[TLB.scala:374:29]
wire pma_checker__vstage1_en_T = 1'h0; // @[TLB.scala:376:38]
wire pma_checker__vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68]
wire pma_checker_vstage1_en = 1'h0; // @[TLB.scala:376:48]
wire pma_checker__stage2_en_T = 1'h0; // @[TLB.scala:378:38]
wire pma_checker__stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68]
wire pma_checker_stage2_en = 1'h0; // @[TLB.scala:378:48]
wire pma_checker__vm_enabled_T = 1'h0; // @[TLB.scala:399:31]
wire pma_checker__vm_enabled_T_1 = 1'h0; // @[TLB.scala:399:45]
wire pma_checker__vm_enabled_T_2 = 1'h0; // @[TLB.scala:399:64]
wire pma_checker_vm_enabled = 1'h0; // @[TLB.scala:399:61]
wire pma_checker__vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52]
wire pma_checker__vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37]
wire pma_checker__vsatp_mode_mismatch_T_2 = 1'h0; // @[TLB.scala:403:81]
wire pma_checker_vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78]
wire pma_checker_do_refill = 1'h0; // @[TLB.scala:408:29]
wire pma_checker__invalidate_refill_T = 1'h0; // @[package.scala:16:47]
wire pma_checker__invalidate_refill_T_1 = 1'h0; // @[package.scala:16:47]
wire pma_checker__invalidate_refill_T_2 = 1'h0; // @[package.scala:81:59]
wire pma_checker_invalidate_refill = 1'h0; // @[TLB.scala:410:88]
wire pma_checker__mpu_ppn_T = 1'h0; // @[TLB.scala:413:32]
wire pma_checker_cacheable = 1'h0; // @[TLB.scala:425:41]
wire pma_checker_prot_r = 1'h0; // @[TLB.scala:429:55]
wire pma_checker_prot_w = 1'h0; // @[TLB.scala:430:55]
wire pma_checker_prot_x = 1'h0; // @[TLB.scala:434:55]
wire pma_checker__sector_hits_T = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_1 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_2 = 1'h0; // @[package.scala:81:59]
wire pma_checker_sector_hits_0 = 1'h0; // @[TLB.scala:172:55]
wire pma_checker__sector_hits_T_8 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_9 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_10 = 1'h0; // @[package.scala:81:59]
wire pma_checker_sector_hits_1 = 1'h0; // @[TLB.scala:172:55]
wire pma_checker__sector_hits_T_16 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_17 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_18 = 1'h0; // @[package.scala:81:59]
wire pma_checker_sector_hits_2 = 1'h0; // @[TLB.scala:172:55]
wire pma_checker__sector_hits_T_24 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_25 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_26 = 1'h0; // @[package.scala:81:59]
wire pma_checker_sector_hits_3 = 1'h0; // @[TLB.scala:172:55]
wire pma_checker__sector_hits_T_32 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_33 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_34 = 1'h0; // @[package.scala:81:59]
wire pma_checker_sector_hits_4 = 1'h0; // @[TLB.scala:172:55]
wire pma_checker__sector_hits_T_40 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_41 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_42 = 1'h0; // @[package.scala:81:59]
wire pma_checker_sector_hits_5 = 1'h0; // @[TLB.scala:172:55]
wire pma_checker__sector_hits_T_48 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_49 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_50 = 1'h0; // @[package.scala:81:59]
wire pma_checker_sector_hits_6 = 1'h0; // @[TLB.scala:172:55]
wire pma_checker__sector_hits_T_56 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_57 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_58 = 1'h0; // @[package.scala:81:59]
wire pma_checker_sector_hits_7 = 1'h0; // @[TLB.scala:172:55]
wire pma_checker_superpage_hits_tagMatch = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34]
wire pma_checker__superpage_hits_T_4 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__superpage_hits_T_9 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker_superpage_hits_0 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker_superpage_hits_tagMatch_1 = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__superpage_hits_ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_superpage_hits_ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire pma_checker__superpage_hits_T_18 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__superpage_hits_T_23 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker_superpage_hits_1 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker_superpage_hits_tagMatch_2 = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__superpage_hits_ignore_T_6 = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_superpage_hits_ignore_6 = 1'h0; // @[TLB.scala:182:34]
wire pma_checker__superpage_hits_T_32 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__superpage_hits_T_37 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker_superpage_hits_2 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker_superpage_hits_tagMatch_3 = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__superpage_hits_ignore_T_9 = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_superpage_hits_ignore_9 = 1'h0; // @[TLB.scala:182:34]
wire pma_checker__superpage_hits_T_46 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__superpage_hits_T_51 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker_superpage_hits_3 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__hitsVec_T_5 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_0 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker__hitsVec_T_11 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_1 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker__hitsVec_T_17 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_2 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker__hitsVec_T_23 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_3 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker__hitsVec_T_29 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_4 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker__hitsVec_T_35 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_5 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker__hitsVec_T_41 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_6 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker__hitsVec_T_47 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_7 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker_hitsVec_tagMatch = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_hitsVec_ignore = 1'h0; // @[TLB.scala:182:34]
wire pma_checker__hitsVec_T_52 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__hitsVec_T_57 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__hitsVec_T_62 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker_hitsVec_8 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker_hitsVec_tagMatch_1 = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire pma_checker__hitsVec_T_67 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__hitsVec_T_72 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__hitsVec_T_77 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker_hitsVec_9 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker_hitsVec_tagMatch_2 = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__hitsVec_ignore_T_6 = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_hitsVec_ignore_6 = 1'h0; // @[TLB.scala:182:34]
wire pma_checker__hitsVec_T_82 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__hitsVec_T_87 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__hitsVec_T_92 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker_hitsVec_10 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker_hitsVec_tagMatch_3 = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__hitsVec_ignore_T_9 = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_hitsVec_ignore_9 = 1'h0; // @[TLB.scala:182:34]
wire pma_checker__hitsVec_T_97 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__hitsVec_T_102 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__hitsVec_T_107 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker_hitsVec_11 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker_hitsVec_tagMatch_4 = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__hitsVec_ignore_T_12 = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_hitsVec_ignore_12 = 1'h0; // @[TLB.scala:182:34]
wire pma_checker__hitsVec_T_112 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__hitsVec_T_117 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__hitsVec_T_122 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker_hitsVec_12 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker_refill_v = 1'h0; // @[TLB.scala:448:33]
wire pma_checker_newEntry_u = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_g = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_ae_ptw = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_ae_final = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_pf = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_gf = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_sw = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_sx = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_sr = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_hw = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_hx = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_hr = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_pw = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_px = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_pr = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_c = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24]
wire pma_checker__newEntry_g_T = 1'h0; // @[TLB.scala:453:25]
wire pma_checker__newEntry_ae_stage2_T = 1'h0; // @[TLB.scala:456:53]
wire pma_checker__newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84]
wire pma_checker__newEntry_sr_T_1 = 1'h0; // @[PTW.scala:141:44]
wire pma_checker__newEntry_sr_T_2 = 1'h0; // @[PTW.scala:141:38]
wire pma_checker__newEntry_sr_T_3 = 1'h0; // @[PTW.scala:141:32]
wire pma_checker__newEntry_sr_T_4 = 1'h0; // @[PTW.scala:141:52]
wire pma_checker__newEntry_sr_T_5 = 1'h0; // @[PTW.scala:149:35]
wire pma_checker__newEntry_sw_T_1 = 1'h0; // @[PTW.scala:141:44]
wire pma_checker__newEntry_sw_T_2 = 1'h0; // @[PTW.scala:141:38]
wire pma_checker__newEntry_sw_T_3 = 1'h0; // @[PTW.scala:141:32]
wire pma_checker__newEntry_sw_T_4 = 1'h0; // @[PTW.scala:141:52]
wire pma_checker__newEntry_sw_T_5 = 1'h0; // @[PTW.scala:151:35]
wire pma_checker__newEntry_sw_T_6 = 1'h0; // @[PTW.scala:151:40]
wire pma_checker__newEntry_sx_T_1 = 1'h0; // @[PTW.scala:141:44]
wire pma_checker__newEntry_sx_T_2 = 1'h0; // @[PTW.scala:141:38]
wire pma_checker__newEntry_sx_T_3 = 1'h0; // @[PTW.scala:141:32]
wire pma_checker__newEntry_sx_T_4 = 1'h0; // @[PTW.scala:141:52]
wire pma_checker__newEntry_sx_T_5 = 1'h0; // @[PTW.scala:153:35]
wire pma_checker__waddr_T = 1'h0; // @[TLB.scala:477:45]
wire pma_checker__superpage_entries_0_level_T = 1'h0; // @[package.scala:163:13]
wire pma_checker__superpage_entries_1_level_T = 1'h0; // @[package.scala:163:13]
wire pma_checker__superpage_entries_2_level_T = 1'h0; // @[package.scala:163:13]
wire pma_checker__superpage_entries_3_level_T = 1'h0; // @[package.scala:163:13]
wire pma_checker_sum = 1'h0; // @[TLB.scala:510:16]
wire pma_checker__mxr_T = 1'h0; // @[TLB.scala:518:36]
wire pma_checker_mxr = 1'h0; // @[TLB.scala:518:31]
wire pma_checker__prefetchable_array_T = 1'h0; // @[TLB.scala:547:43]
wire pma_checker__bad_va_T = 1'h0; // @[TLB.scala:568:21]
wire pma_checker_bad_va = 1'h0; // @[TLB.scala:568:34]
wire pma_checker_cmd_readx = 1'h0; // @[TLB.scala:575:37]
wire pma_checker__gf_ld_array_T = 1'h0; // @[TLB.scala:600:32]
wire pma_checker__gf_st_array_T = 1'h0; // @[TLB.scala:601:32]
wire pma_checker__gpa_hits_hit_mask_T_1 = 1'h0; // @[TLB.scala:606:60]
wire pma_checker_tlb_hit_if_not_gpa_miss = 1'h0; // @[TLB.scala:610:43]
wire pma_checker_tlb_hit = 1'h0; // @[TLB.scala:611:40]
wire pma_checker__tlb_miss_T_1 = 1'h0; // @[TLB.scala:613:29]
wire pma_checker__tlb_miss_T_3 = 1'h0; // @[TLB.scala:613:53]
wire pma_checker_tlb_miss = 1'h0; // @[TLB.scala:613:64]
wire pma_checker__state_vec_0_set_left_older_T = 1'h0; // @[Replacement.scala:196:43]
wire pma_checker__state_vec_0_set_left_older_T_1 = 1'h0; // @[Replacement.scala:196:43]
wire pma_checker_state_vec_0_left_subtree_state_1 = 1'h0; // @[package.scala:163:13]
wire pma_checker_state_vec_0_right_subtree_state_1 = 1'h0; // @[Replacement.scala:198:38]
wire pma_checker__state_vec_0_T_1 = 1'h0; // @[package.scala:163:13]
wire pma_checker__state_vec_0_T_2 = 1'h0; // @[Replacement.scala:218:17]
wire pma_checker__state_vec_0_T_4 = 1'h0; // @[Replacement.scala:203:16]
wire pma_checker__state_vec_0_T_5 = 1'h0; // @[Replacement.scala:207:62]
wire pma_checker__state_vec_0_T_6 = 1'h0; // @[Replacement.scala:218:17]
wire pma_checker__state_vec_0_set_left_older_T_2 = 1'h0; // @[Replacement.scala:196:43]
wire pma_checker_state_vec_0_left_subtree_state_2 = 1'h0; // @[package.scala:163:13]
wire pma_checker_state_vec_0_right_subtree_state_2 = 1'h0; // @[Replacement.scala:198:38]
wire pma_checker__state_vec_0_T_12 = 1'h0; // @[package.scala:163:13]
wire pma_checker__state_vec_0_T_13 = 1'h0; // @[Replacement.scala:218:17]
wire pma_checker__state_vec_0_T_15 = 1'h0; // @[Replacement.scala:203:16]
wire pma_checker__state_vec_0_T_16 = 1'h0; // @[Replacement.scala:207:62]
wire pma_checker__state_vec_0_T_17 = 1'h0; // @[Replacement.scala:218:17]
wire pma_checker__state_reg_set_left_older_T = 1'h0; // @[Replacement.scala:196:43]
wire pma_checker_state_reg_left_subtree_state = 1'h0; // @[package.scala:163:13]
wire pma_checker_state_reg_right_subtree_state = 1'h0; // @[Replacement.scala:198:38]
wire pma_checker__state_reg_T = 1'h0; // @[package.scala:163:13]
wire pma_checker__state_reg_T_1 = 1'h0; // @[Replacement.scala:218:17]
wire pma_checker__state_reg_T_3 = 1'h0; // @[Replacement.scala:203:16]
wire pma_checker__state_reg_T_4 = 1'h0; // @[Replacement.scala:207:62]
wire pma_checker__state_reg_T_5 = 1'h0; // @[Replacement.scala:218:17]
wire pma_checker__multipleHits_T_2 = 1'h0; // @[Misc.scala:181:37]
wire pma_checker_multipleHits_leftOne = 1'h0; // @[Misc.scala:178:18]
wire pma_checker__multipleHits_T_4 = 1'h0; // @[Misc.scala:181:37]
wire pma_checker_multipleHits_leftOne_1 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker__multipleHits_T_5 = 1'h0; // @[Misc.scala:182:39]
wire pma_checker_multipleHits_rightOne = 1'h0; // @[Misc.scala:178:18]
wire pma_checker_multipleHits_rightOne_1 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_7 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_rightTwo = 1'h0; // @[Misc.scala:183:49]
wire pma_checker_multipleHits_leftOne_2 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_8 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_9 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_leftTwo = 1'h0; // @[Misc.scala:183:49]
wire pma_checker__multipleHits_T_11 = 1'h0; // @[Misc.scala:181:37]
wire pma_checker_multipleHits_leftOne_3 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker__multipleHits_T_13 = 1'h0; // @[Misc.scala:181:37]
wire pma_checker_multipleHits_leftOne_4 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker__multipleHits_T_14 = 1'h0; // @[Misc.scala:182:39]
wire pma_checker_multipleHits_rightOne_2 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker_multipleHits_rightOne_3 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_16 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_rightTwo_1 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker_multipleHits_rightOne_4 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_17 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_18 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_rightTwo_2 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker_multipleHits_leftOne_5 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_19 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_20 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_leftTwo_1 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker__multipleHits_T_23 = 1'h0; // @[Misc.scala:181:37]
wire pma_checker_multipleHits_leftOne_6 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker__multipleHits_T_25 = 1'h0; // @[Misc.scala:181:37]
wire pma_checker_multipleHits_leftOne_7 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker__multipleHits_T_26 = 1'h0; // @[Misc.scala:182:39]
wire pma_checker_multipleHits_rightOne_5 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker_multipleHits_rightOne_6 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_28 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_rightTwo_3 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker_multipleHits_leftOne_8 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_29 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_30 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_leftTwo_2 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker__multipleHits_T_33 = 1'h0; // @[Misc.scala:181:37]
wire pma_checker_multipleHits_leftOne_9 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker__multipleHits_T_34 = 1'h0; // @[Misc.scala:182:39]
wire pma_checker_multipleHits_rightOne_7 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker_multipleHits_leftOne_10 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_36 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_leftTwo_3 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker__multipleHits_T_38 = 1'h0; // @[Misc.scala:181:37]
wire pma_checker_multipleHits_leftOne_11 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker__multipleHits_T_39 = 1'h0; // @[Misc.scala:182:39]
wire pma_checker_multipleHits_rightOne_8 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker_multipleHits_rightOne_9 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_41 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_rightTwo_4 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker_multipleHits_rightOne_10 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_42 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_43 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_rightTwo_5 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker_multipleHits_rightOne_11 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_44 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_45 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_rightTwo_6 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker__multipleHits_T_46 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_47 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_48 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits = 1'h0; // @[Misc.scala:183:49]
wire pma_checker__io_resp_pf_ld_T = 1'h0; // @[TLB.scala:633:28]
wire pma_checker__io_resp_pf_st_T = 1'h0; // @[TLB.scala:634:28]
wire pma_checker__io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29]
wire pma_checker__io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66]
wire pma_checker__io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42]
wire pma_checker__io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29]
wire pma_checker__io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73]
wire pma_checker__io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49]
wire pma_checker__io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56]
wire pma_checker__io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30]
wire pma_checker__io_resp_miss_T = 1'h0; // @[TLB.scala:651:29]
wire pma_checker__io_resp_miss_T_1 = 1'h0; // @[TLB.scala:651:52]
wire pma_checker__io_resp_miss_T_2 = 1'h0; // @[TLB.scala:651:64]
wire pma_checker__io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36]
wire pma_checker__io_ptw_req_valid_T = 1'h0; // @[TLB.scala:662:29]
wire pma_checker_r_superpage_repl_addr_left_subtree_older = 1'h0; // @[Replacement.scala:243:38]
wire pma_checker_r_superpage_repl_addr_left_subtree_state = 1'h0; // @[package.scala:163:13]
wire pma_checker_r_superpage_repl_addr_right_subtree_state = 1'h0; // @[Replacement.scala:245:38]
wire pma_checker__r_superpage_repl_addr_T = 1'h0; // @[Replacement.scala:262:12]
wire pma_checker__r_superpage_repl_addr_T_1 = 1'h0; // @[Replacement.scala:262:12]
wire pma_checker__r_superpage_repl_addr_T_2 = 1'h0; // @[Replacement.scala:250:16]
wire pma_checker__r_superpage_repl_addr_T_4 = 1'h0; // @[TLB.scala:757:16]
wire pma_checker_r_sectored_repl_addr_left_subtree_older = 1'h0; // @[Replacement.scala:243:38]
wire pma_checker_r_sectored_repl_addr_left_subtree_older_1 = 1'h0; // @[Replacement.scala:243:38]
wire pma_checker_r_sectored_repl_addr_left_subtree_state_1 = 1'h0; // @[package.scala:163:13]
wire pma_checker_r_sectored_repl_addr_right_subtree_state_1 = 1'h0; // @[Replacement.scala:245:38]
wire pma_checker__r_sectored_repl_addr_T = 1'h0; // @[Replacement.scala:262:12]
wire pma_checker__r_sectored_repl_addr_T_1 = 1'h0; // @[Replacement.scala:262:12]
wire pma_checker__r_sectored_repl_addr_T_2 = 1'h0; // @[Replacement.scala:250:16]
wire pma_checker_r_sectored_repl_addr_left_subtree_older_2 = 1'h0; // @[Replacement.scala:243:38]
wire pma_checker_r_sectored_repl_addr_left_subtree_state_2 = 1'h0; // @[package.scala:163:13]
wire pma_checker_r_sectored_repl_addr_right_subtree_state_2 = 1'h0; // @[Replacement.scala:245:38]
wire pma_checker__r_sectored_repl_addr_T_4 = 1'h0; // @[Replacement.scala:262:12]
wire pma_checker__r_sectored_repl_addr_T_5 = 1'h0; // @[Replacement.scala:262:12]
wire pma_checker__r_sectored_repl_addr_T_6 = 1'h0; // @[Replacement.scala:250:16]
wire pma_checker__r_sectored_repl_addr_valids_T = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_1 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_2 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_3 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_4 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_5 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_6 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_7 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_8 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_9 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_10 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_11 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_12 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_13 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_14 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_15 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_16 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_17 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_18 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_19 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_20 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_21 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_22 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_23 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_T_10 = 1'h0; // @[TLB.scala:757:16]
wire pma_checker__r_sectored_hit_valid_T = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_hit_valid_T_1 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_hit_valid_T_2 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_hit_valid_T_3 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_hit_valid_T_4 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_hit_valid_T_5 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_hit_valid_T_6 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_hit_bits_T_1 = 1'h0; // @[OneHot.scala:32:14]
wire pma_checker__r_sectored_hit_bits_T_3 = 1'h0; // @[OneHot.scala:32:14]
wire pma_checker__r_sectored_hit_bits_T_5 = 1'h0; // @[CircuitMath.scala:28:8]
wire pma_checker__r_superpage_hit_valid_T = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_superpage_hit_valid_T_1 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_superpage_hit_valid_T_2 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_superpage_hit_bits_T_1 = 1'h0; // @[OneHot.scala:32:14]
wire pma_checker__r_superpage_hit_bits_T_3 = 1'h0; // @[CircuitMath.scala:28:8]
wire pma_checker_hv = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_hv_1 = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg_1 = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_hv_2 = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg_2 = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_hv_3 = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg_3 = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_hv_4 = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg_4 = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_hv_5 = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg_5 = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_hv_6 = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg_6 = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_hv_7 = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg_7 = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_hv_8 = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg_8 = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_tagMatch = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__ignore_T = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_ignore = 1'h0; // @[TLB.scala:182:34]
wire pma_checker_hv_9 = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg_9 = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_tagMatch_1 = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire pma_checker_hv_10 = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg_10 = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_tagMatch_2 = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__ignore_T_6 = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_ignore_6 = 1'h0; // @[TLB.scala:182:34]
wire pma_checker_hv_11 = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg_11 = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_tagMatch_3 = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__ignore_T_9 = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_ignore_9 = 1'h0; // @[TLB.scala:182:34]
wire pma_checker_hv_12 = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg_12 = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_tagMatch_4 = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__ignore_T_12 = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_ignore_12 = 1'h0; // @[TLB.scala:182:34]
wire metaArb_io_in_0_valid = 1'h0; // @[DCache.scala:135:28]
wire metaArb_io_in_1_valid = 1'h0; // @[DCache.scala:135:28]
wire metaArb_io_in_1_bits_way_en = 1'h0; // @[DCache.scala:135:28]
wire metaArb_io_in_4_valid = 1'h0; // @[DCache.scala:135:28]
wire metaArb_io_in_5_valid = 1'h0; // @[DCache.scala:135:28]
wire metaArb_io_in_5_bits_write = 1'h0; // @[DCache.scala:135:28]
wire metaArb_io_in_6_valid = 1'h0; // @[DCache.scala:135:28]
wire metaArb_io_in_6_bits_write = 1'h0; // @[DCache.scala:135:28]
wire metaArb_io_in_7_bits_write = 1'h0; // @[DCache.scala:135:28]
wire metaArb__grant_T = 1'h0; // @[Arbiter.scala:45:68]
wire dataArb_io_in_2_valid = 1'h0; // @[DCache.scala:152:28]
wire dataArb_io_in_2_bits_write = 1'h0; // @[DCache.scala:152:28]
wire dataArb_io_in_3_bits_write = 1'h0; // @[DCache.scala:152:28]
wire tl_out_a_bits_source = 1'h0; // @[DCache.scala:159:22]
wire tl_out_a_bits_corrupt = 1'h0; // @[DCache.scala:159:22]
wire nodeOut_a_deq_bits_source = 1'h0; // @[Decoupled.scala:356:21]
wire nodeOut_a_deq_bits_corrupt = 1'h0; // @[Decoupled.scala:356:21]
wire tl_out_c_ready = 1'h0; // @[Bundles.scala:265:61]
wire tl_out_c_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire tl_out_c_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _s1_probe_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _s1_probe_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _s1_probe_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _s1_probe_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _s1_probe_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _s1_probe_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _s1_probe_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61]
wire _s1_probe_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _s1_probe_T = 1'h0; // @[Decoupled.scala:51:35]
wire _probe_bits_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _probe_bits_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _probe_bits_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _probe_bits_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _probe_bits_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _probe_bits_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _probe_bits_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61]
wire _probe_bits_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _probe_bits_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74]
wire _probe_bits_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74]
wire _probe_bits_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _probe_bits_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _probe_bits_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61]
wire _probe_bits_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61]
wire _probe_bits_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:264:61]
wire _probe_bits_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _probe_bits_T = 1'h0; // @[Decoupled.scala:51:35]
wire _s1_tlb_req_valid_T = 1'h0; // @[Decoupled.scala:51:35]
wire s0_req_no_alloc = 1'h0; // @[DCache.scala:192:24]
wire s1_waw_hazard = 1'h0; // @[DCache.scala:216:27]
wire _inWriteback_T = 1'h0; // @[package.scala:16:47]
wire _inWriteback_T_1 = 1'h0; // @[package.scala:16:47]
wire inWriteback = 1'h0; // @[package.scala:81:59]
wire _uncachedInFlight_WIRE_0 = 1'h0; // @[DCache.scala:236:41]
wire _dataArb_io_in_3_valid_res_T_4 = 1'h0; // @[DCache.scala:1185:58]
wire _dataArb_io_in_3_valid_T_49 = 1'h0; // @[DCache.scala:1191:57]
wire _s1_did_read_T_49 = 1'h0; // @[DCache.scala:1191:57]
wire _tlb_io_kill_T = 1'h0; // @[DCache.scala:272:53]
wire _tlb_io_kill_T_1 = 1'h0; // @[DCache.scala:272:33]
wire s1_victim_way = 1'h0; // @[DCache.scala:299:27]
wire _releaseInFlight_T = 1'h0; // @[DCache.scala:334:34]
wire _releaseInFlight_T_1 = 1'h0; // @[DCache.scala:334:63]
wire releaseInFlight = 1'h0; // @[DCache.scala:334:46]
wire _s2_pma_T_gpa_is_pte = 1'h0; // @[DCache.scala:349:18]
wire _s2_pma_T_gf_ld = 1'h0; // @[DCache.scala:349:18]
wire _s2_pma_T_gf_st = 1'h0; // @[DCache.scala:349:18]
wire _s2_pma_T_gf_inst = 1'h0; // @[DCache.scala:349:18]
wire _s2_pma_T_ma_inst = 1'h0; // @[DCache.scala:349:18]
wire s2_meta_error_uncorrectable = 1'h0; // @[DCache.scala:360:66]
wire _s2_meta_error_T = 1'h0; // @[DCache.scala:362:53]
wire s2_meta_error = 1'h0; // @[DCache.scala:362:83]
wire s2_store_merge = 1'h0; // @[DCache.scala:388:28]
wire _r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _s2_data_error_T = 1'h0; // @[ECC.scala:15:27]
wire _s2_data_error_T_1 = 1'h0; // @[ECC.scala:15:27]
wire _s2_data_error_T_2 = 1'h0; // @[ECC.scala:15:27]
wire _s2_data_error_T_3 = 1'h0; // @[ECC.scala:15:27]
wire _s2_data_error_T_4 = 1'h0; // @[ECC.scala:15:27]
wire _s2_data_error_T_5 = 1'h0; // @[ECC.scala:15:27]
wire _s2_data_error_T_6 = 1'h0; // @[ECC.scala:15:27]
wire _s2_data_error_T_7 = 1'h0; // @[ECC.scala:15:27]
wire _s2_data_error_T_8 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_T_9 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_T_10 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_T_11 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_T_12 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_T_13 = 1'h0; // @[package.scala:81:59]
wire s2_data_error = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_uncorrectable_T = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_uncorrectable_T_1 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_uncorrectable_T_2 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_uncorrectable_T_3 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_uncorrectable_T_4 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_uncorrectable_T_5 = 1'h0; // @[package.scala:81:59]
wire s2_data_error_uncorrectable = 1'h0; // @[package.scala:81:59]
wire s2_valid_data_error = 1'h0; // @[DCache.scala:421:63]
wire s2_want_victimize = 1'h0; // @[DCache.scala:427:52]
wire s2_cannot_victimize = 1'h0; // @[DCache.scala:428:45]
wire s2_victimize = 1'h0; // @[DCache.scala:429:40]
wire _r_T_73 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_77 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_81 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_119 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_121 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_137 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_141 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_145 = 1'h0; // @[Misc.scala:38:9]
wire _s2_dont_nack_misc_T_2 = 1'h0; // @[DCache.scala:442:23]
wire _s2_dont_nack_misc_T_3 = 1'h0; // @[DCache.scala:442:43]
wire _s2_dont_nack_misc_T_5 = 1'h0; // @[DCache.scala:442:54]
wire _s2_dont_nack_misc_T_6 = 1'h0; // @[DCache.scala:443:23]
wire _s2_dont_nack_misc_T_8 = 1'h0; // @[DCache.scala:443:44]
wire _s2_dont_nack_misc_T_9 = 1'h0; // @[DCache.scala:442:67]
wire _s2_first_meta_corrected_T = 1'h0; // @[Mux.scala:52:83]
wire _metaArb_io_in_1_valid_T_2 = 1'h0; // @[DCache.scala:450:43]
wire _metaArb_io_in_1_bits_way_en_T = 1'h0; // @[OneHot.scala:85:71]
wire _metaArb_io_in_1_bits_way_en_T_1 = 1'h0; // @[Mux.scala:50:70]
wire _metaArb_io_in_1_bits_way_en_T_2 = 1'h0; // @[DCache.scala:452:69]
wire _metaArb_io_in_1_bits_way_en_T_3 = 1'h0; // @[DCache.scala:452:64]
wire s2_lr = 1'h0; // @[DCache.scala:470:56]
wire s2_sc = 1'h0; // @[DCache.scala:471:56]
wire s2_sc_fail = 1'h0; // @[DCache.scala:477:26]
wire _s2_correct_T_1 = 1'h0; // @[DCache.scala:487:34]
wire _s2_correct_T_4 = 1'h0; // @[DCache.scala:487:55]
wire s2_correct = 1'h0; // @[DCache.scala:487:97]
wire _s2_valid_correct_T = 1'h0; // @[DCache.scala:489:60]
wire s2_valid_correct = 1'h0; // @[DCache.scala:489:74]
wire _pstore1_rmw_T_49 = 1'h0; // @[DCache.scala:1191:57]
wire pstore1_merge_likely = 1'h0; // @[DCache.scala:499:68]
wire pstore1_merge = 1'h0; // @[DCache.scala:500:38]
wire _pstore_drain_opportunistic_res_T_4 = 1'h0; // @[DCache.scala:1185:58]
wire _pstore_drain_opportunistic_T_49 = 1'h0; // @[DCache.scala:1191:57]
wire _pstore_drain_opportunistic_T_60 = 1'h0; // @[DCache.scala:502:106]
wire pstore_drain_s2_kill = 1'h0; // @[DCache.scala:515:25]
wire _pstore2_storegen_data_T_2 = 1'h0; // @[DCache.scala:528:95]
wire _pstore2_storegen_data_T_6 = 1'h0; // @[DCache.scala:528:95]
wire _pstore2_storegen_data_T_10 = 1'h0; // @[DCache.scala:528:95]
wire _pstore2_storegen_data_T_14 = 1'h0; // @[DCache.scala:528:95]
wire _pstore2_storegen_data_T_18 = 1'h0; // @[DCache.scala:528:95]
wire _pstore2_storegen_data_T_22 = 1'h0; // @[DCache.scala:528:95]
wire _pstore2_storegen_data_T_26 = 1'h0; // @[DCache.scala:528:95]
wire _pstore2_storegen_data_T_30 = 1'h0; // @[DCache.scala:528:95]
wire dataArb_io_in_0_valid_s2_kill = 1'h0; // @[DCache.scala:515:25]
wire _dataArb_io_in_0_bits_wordMask_T_1 = 1'h0; // @[DCache.scala:555:20]
wire _io_cpu_s2_nack_cause_raw_T_2 = 1'h0; // @[DCache.scala:574:57]
wire get_source = 1'h0; // @[Edges.scala:460:17]
wire get_corrupt = 1'h0; // @[Edges.scala:460:17]
wire _put_legal_T_74 = 1'h0; // @[Parameters.scala:684:29]
wire _put_legal_T_80 = 1'h0; // @[Parameters.scala:684:54]
wire put_source = 1'h0; // @[Edges.scala:480:17]
wire put_corrupt = 1'h0; // @[Edges.scala:480:17]
wire _putpartial_legal_T_74 = 1'h0; // @[Parameters.scala:684:29]
wire _putpartial_legal_T_80 = 1'h0; // @[Parameters.scala:684:54]
wire putpartial_source = 1'h0; // @[Edges.scala:500:17]
wire putpartial_corrupt = 1'h0; // @[Edges.scala:500:17]
wire _atomics_WIRE_source = 1'h0; // @[DCache.scala:587:51]
wire _atomics_WIRE_corrupt = 1'h0; // @[DCache.scala:587:51]
wire _atomics_WIRE_1_source = 1'h0; // @[DCache.scala:587:38]
wire _atomics_WIRE_1_corrupt = 1'h0; // @[DCache.scala:587:38]
wire _atomics_legal_T_46 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_52 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_source = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_corrupt = 1'h0; // @[Edges.scala:534:17]
wire _atomics_legal_T_100 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_106 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_1_source = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_1_corrupt = 1'h0; // @[Edges.scala:534:17]
wire _atomics_legal_T_154 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_160 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_2_source = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_2_corrupt = 1'h0; // @[Edges.scala:534:17]
wire _atomics_legal_T_208 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_214 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_3_source = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_3_corrupt = 1'h0; // @[Edges.scala:534:17]
wire _atomics_legal_T_262 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_268 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_4_source = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_4_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_legal_T_316 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_322 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_5_source = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_5_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_legal_T_370 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_376 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_6_source = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_6_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_legal_T_424 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_430 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_7_source = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_7_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_legal_T_478 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_484 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_8_source = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_8_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_T_1_source = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_1_corrupt = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_3_source = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_3_corrupt = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_5_source = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_5_corrupt = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_7_source = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_7_corrupt = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_9_source = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_9_corrupt = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_11_source = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_11_corrupt = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_13_source = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_13_corrupt = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_15_source = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_15_corrupt = 1'h0; // @[DCache.scala:587:81]
wire atomics_source = 1'h0; // @[DCache.scala:587:81]
wire atomics_corrupt = 1'h0; // @[DCache.scala:587:81]
wire _tl_out_a_valid_T_4 = 1'h0; // @[DCache.scala:606:27]
wire _tl_out_a_valid_T_8 = 1'h0; // @[DCache.scala:607:44]
wire _tl_out_a_valid_T_9 = 1'h0; // @[DCache.scala:607:65]
wire _tl_out_a_bits_legal_T = 1'h0; // @[Parameters.scala:684:29]
wire _tl_out_a_bits_legal_T_30 = 1'h0; // @[Parameters.scala:684:54]
wire _tl_out_a_bits_legal_T_45 = 1'h0; // @[Parameters.scala:686:26]
wire tl_out_a_bits_a_source = 1'h0; // @[Edges.scala:346:17]
wire tl_out_a_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17]
wire tl_out_a_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _tl_out_a_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _tl_out_a_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire _tl_out_a_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire _tl_out_a_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire _tl_out_a_bits_T_6_source = 1'h0; // @[DCache.scala:611:8]
wire _tl_out_a_bits_T_6_corrupt = 1'h0; // @[DCache.scala:611:8]
wire _tl_out_a_bits_T_7_source = 1'h0; // @[DCache.scala:610:8]
wire _tl_out_a_bits_T_7_corrupt = 1'h0; // @[DCache.scala:610:8]
wire _tl_out_a_bits_T_8_source = 1'h0; // @[DCache.scala:609:8]
wire _tl_out_a_bits_T_8_corrupt = 1'h0; // @[DCache.scala:609:8]
wire _tl_out_a_bits_T_9_source = 1'h0; // @[DCache.scala:608:23]
wire _tl_out_a_bits_T_9_corrupt = 1'h0; // @[DCache.scala:608:23]
wire _tl_d_data_encoded_T_12 = 1'h0; // @[DCache.scala:663:129]
wire _tl_d_data_encoded_T_13 = 1'h0; // @[DCache.scala:663:126]
wire _grantIsCached_T = 1'h0; // @[package.scala:16:47]
wire _grantIsCached_T_1 = 1'h0; // @[package.scala:16:47]
wire grantIsVoluntary = 1'h0; // @[DCache.scala:665:32]
wire grantIsRefill = 1'h0; // @[DCache.scala:666:29]
wire _canAcceptCachedGrant_T = 1'h0; // @[package.scala:16:47]
wire _canAcceptCachedGrant_T_1 = 1'h0; // @[package.scala:16:47]
wire _canAcceptCachedGrant_T_2 = 1'h0; // @[package.scala:16:47]
wire _canAcceptCachedGrant_T_3 = 1'h0; // @[package.scala:81:59]
wire _canAcceptCachedGrant_T_4 = 1'h0; // @[package.scala:81:59]
wire _nodeOut_d_ready_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _nodeOut_d_ready_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _nodeOut_d_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _nodeOut_d_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _block_probe_for_pending_release_ack_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _block_probe_for_pending_release_ack_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _block_probe_for_pending_release_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _block_probe_for_pending_release_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _block_probe_for_pending_release_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _block_probe_for_pending_release_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _block_probe_for_pending_release_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61]
wire _block_probe_for_pending_release_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire block_probe_for_pending_release_ack = 1'h0; // @[DCache.scala:767:62]
wire _block_probe_for_ordering_T = 1'h0; // @[DCache.scala:768:50]
wire _metaArb_io_in_6_valid_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _metaArb_io_in_6_valid_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _metaArb_io_in_6_valid_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _metaArb_io_in_6_valid_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _metaArb_io_in_6_valid_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _metaArb_io_in_6_valid_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _metaArb_io_in_6_valid_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61]
wire _metaArb_io_in_6_valid_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _metaArb_io_in_6_valid_T_2 = 1'h0; // @[DCache.scala:769:44]
wire _metaArb_io_in_6_bits_idx_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _metaArb_io_in_6_bits_idx_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _metaArb_io_in_6_bits_idx_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _metaArb_io_in_6_bits_idx_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _metaArb_io_in_6_bits_idx_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _metaArb_io_in_6_bits_idx_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _metaArb_io_in_6_bits_idx_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61]
wire _metaArb_io_in_6_bits_idx_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _metaArb_io_in_6_bits_addr_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _metaArb_io_in_6_bits_addr_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _metaArb_io_in_6_bits_addr_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _metaArb_io_in_6_bits_addr_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _metaArb_io_in_6_bits_addr_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _metaArb_io_in_6_bits_addr_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _metaArb_io_in_6_bits_addr_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61]
wire _metaArb_io_in_6_bits_addr_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire r_beats1_opdata_1 = 1'h0; // @[Edges.scala:102:36]
wire _r_last_T_2 = 1'h0; // @[Edges.scala:232:25]
wire releaseDone = 1'h0; // @[Edges.scala:233:22]
wire _s1_release_data_valid_T = 1'h0; // @[Decoupled.scala:51:35]
wire _s2_release_data_valid_T_1 = 1'h0; // @[DCache.scala:802:61]
wire _releaseRejected_T = 1'h0; // @[Decoupled.scala:51:35]
wire nackResponseMessage_source = 1'h0; // @[Edges.scala:416:17]
wire nackResponseMessage_corrupt = 1'h0; // @[Edges.scala:416:17]
wire cleanReleaseMessage_source = 1'h0; // @[Edges.scala:416:17]
wire cleanReleaseMessage_corrupt = 1'h0; // @[Edges.scala:416:17]
wire dirtyReleaseMessage_source = 1'h0; // @[Edges.scala:433:17]
wire dirtyReleaseMessage_corrupt = 1'h0; // @[Edges.scala:433:17]
wire _tl_out_c_valid_T = 1'h0; // @[DCache.scala:810:48]
wire _tl_out_c_valid_T_1 = 1'h0; // @[DCache.scala:810:91]
wire _tl_out_c_valid_T_2 = 1'h0; // @[DCache.scala:810:74]
wire _tl_out_c_valid_T_4 = 1'h0; // @[DCache.scala:810:130]
wire _dataArb_io_in_2_valid_T_1 = 1'h0; // @[DCache.scala:900:41]
wire _metaArb_io_in_4_valid_T = 1'h0; // @[package.scala:16:47]
wire _metaArb_io_in_4_valid_T_1 = 1'h0; // @[package.scala:16:47]
wire _metaArb_io_in_4_valid_T_2 = 1'h0; // @[package.scala:81:59]
wire _io_cpu_s2_xcpt_WIRE_miss = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_gpa_is_pte = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_pf_ld = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_pf_st = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_pf_inst = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_gf_ld = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_gf_st = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_gf_inst = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_ae_ld = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_ae_st = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_ae_inst = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_ma_ld = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_ma_st = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_ma_inst = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_cacheable = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_must_alloc = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_prefetchable = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_T_gpa_is_pte = 1'h0; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_gf_ld = 1'h0; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_gf_st = 1'h0; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_gf_inst = 1'h0; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_ma_inst = 1'h0; // @[DCache.scala:933:24]
wire _s2_data_word_possibly_uncached_T = 1'h0; // @[DCache.scala:972:73]
wire io_cpu_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire io_cpu_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31]
wire io_cpu_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31]
wire io_cpu_resp_bits_data_word_bypass_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire _flushDone_T = 1'h0; // @[DCache.scala:1010:37]
wire flushDone = 1'h0; // @[DCache.scala:1010:57]
wire _s1_flush_valid_T = 1'h0; // @[Decoupled.scala:51:35]
wire _s1_flush_valid_T_2 = 1'h0; // @[DCache.scala:1014:43]
wire _s1_flush_valid_T_4 = 1'h0; // @[DCache.scala:1014:62]
wire _s1_flush_valid_T_6 = 1'h0; // @[DCache.scala:1014:93]
wire _s1_flush_valid_T_8 = 1'h0; // @[DCache.scala:1014:122]
wire _metaArb_io_in_5_valid_T = 1'h0; // @[DCache.scala:1015:41]
wire _metaArb_io_in_5_valid_T_1 = 1'h0; // @[DCache.scala:1015:38]
wire _clock_en_reg_T_14 = 1'h0; // @[DCache.scala:1069:19]
wire _clock_en_reg_T_17 = 1'h0; // @[DCache.scala:1070:25]
wire _io_cpu_perf_release_T = 1'h0; // @[Decoupled.scala:51:35]
wire io_cpu_perf_release_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _io_cpu_perf_release_last_T = 1'h0; // @[Edges.scala:232:25]
wire io_cpu_perf_release_done = 1'h0; // @[Edges.scala:233:22]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_50 = 1'h0; // @[DCache.scala:1191:57]
wire io_cpu_clock_enabled = 1'h1; // @[DCache.scala:101:7]
wire io_ptw_req_bits_valid = 1'h1; // @[DCache.scala:101:7]
wire io_tlb_port_req_ready = 1'h1; // @[DCache.scala:101:7]
wire pma_checker_io_req_ready = 1'h1; // @[DCache.scala:120:32]
wire pma_checker_io_req_bits_passthrough = 1'h1; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_req_bits_valid = 1'h1; // @[DCache.scala:120:32]
wire pma_checker__mpu_ppn_ignore_T = 1'h1; // @[TLB.scala:197:28]
wire pma_checker_mpu_ppn_ignore = 1'h1; // @[TLB.scala:197:34]
wire pma_checker__mpu_ppn_ignore_T_1 = 1'h1; // @[TLB.scala:197:28]
wire pma_checker_mpu_ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34]
wire pma_checker__mpu_priv_T = 1'h1; // @[TLB.scala:415:52]
wire pma_checker__mpu_priv_T_1 = 1'h1; // @[TLB.scala:415:38]
wire pma_checker__homogeneous_T_65 = 1'h1; // @[TLBPermissions.scala:87:22]
wire pma_checker__deny_access_to_debug_T = 1'h1; // @[TLB.scala:428:39]
wire pma_checker__sector_hits_T_6 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__sector_hits_T_14 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__sector_hits_T_22 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__sector_hits_T_30 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__sector_hits_T_38 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__sector_hits_T_46 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__sector_hits_T_54 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__sector_hits_T_62 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__superpage_hits_tagMatch_T = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__superpage_hits_ignore_T_1 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker__superpage_hits_ignore_T_2 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40]
wire pma_checker__superpage_hits_tagMatch_T_1 = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__superpage_hits_ignore_T_4 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker__superpage_hits_ignore_T_5 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_superpage_hits_ignore_5 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__superpage_hits_T_27 = 1'h1; // @[TLB.scala:183:40]
wire pma_checker__superpage_hits_tagMatch_T_2 = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__superpage_hits_ignore_T_7 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker__superpage_hits_ignore_T_8 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_superpage_hits_ignore_8 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__superpage_hits_T_41 = 1'h1; // @[TLB.scala:183:40]
wire pma_checker__superpage_hits_tagMatch_T_3 = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__superpage_hits_ignore_T_10 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker__superpage_hits_ignore_T_11 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_superpage_hits_ignore_11 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__superpage_hits_T_55 = 1'h1; // @[TLB.scala:183:40]
wire pma_checker__hitsVec_T_3 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_9 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_15 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_21 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_27 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_33 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_39 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_45 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_tagMatch_T = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__hitsVec_ignore_T_1 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker__hitsVec_ignore_T_2 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__hitsVec_T_61 = 1'h1; // @[TLB.scala:183:40]
wire pma_checker__hitsVec_tagMatch_T_1 = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__hitsVec_ignore_T_4 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker__hitsVec_ignore_T_5 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_hitsVec_ignore_5 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__hitsVec_T_76 = 1'h1; // @[TLB.scala:183:40]
wire pma_checker__hitsVec_tagMatch_T_2 = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__hitsVec_ignore_T_7 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker__hitsVec_ignore_T_8 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_hitsVec_ignore_8 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__hitsVec_T_91 = 1'h1; // @[TLB.scala:183:40]
wire pma_checker__hitsVec_tagMatch_T_3 = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__hitsVec_ignore_T_10 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker__hitsVec_ignore_T_11 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_hitsVec_ignore_11 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__hitsVec_T_106 = 1'h1; // @[TLB.scala:183:40]
wire pma_checker__hitsVec_tagMatch_T_4 = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__hitsVec_ignore_T_13 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_hitsVec_ignore_13 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__hitsVec_T_116 = 1'h1; // @[TLB.scala:183:40]
wire pma_checker__hitsVec_ignore_T_14 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_hitsVec_ignore_14 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__hitsVec_T_121 = 1'h1; // @[TLB.scala:183:40]
wire pma_checker__hits_T = 1'h1; // @[TLB.scala:442:18]
wire pma_checker__newEntry_sr_T = 1'h1; // @[PTW.scala:141:47]
wire pma_checker__newEntry_sw_T = 1'h1; // @[PTW.scala:141:47]
wire pma_checker__newEntry_sx_T = 1'h1; // @[PTW.scala:141:47]
wire pma_checker__ppn_T = 1'h1; // @[TLB.scala:502:30]
wire pma_checker__ppn_ignore_T = 1'h1; // @[TLB.scala:197:28]
wire pma_checker__ppn_ignore_T_1 = 1'h1; // @[TLB.scala:197:28]
wire pma_checker_ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34]
wire pma_checker__ppn_ignore_T_2 = 1'h1; // @[TLB.scala:197:28]
wire pma_checker__ppn_ignore_T_3 = 1'h1; // @[TLB.scala:197:28]
wire pma_checker_ppn_ignore_3 = 1'h1; // @[TLB.scala:197:34]
wire pma_checker__ppn_ignore_T_4 = 1'h1; // @[TLB.scala:197:28]
wire pma_checker__ppn_ignore_T_5 = 1'h1; // @[TLB.scala:197:28]
wire pma_checker_ppn_ignore_5 = 1'h1; // @[TLB.scala:197:34]
wire pma_checker__ppn_ignore_T_6 = 1'h1; // @[TLB.scala:197:28]
wire pma_checker__ppn_ignore_T_7 = 1'h1; // @[TLB.scala:197:28]
wire pma_checker_ppn_ignore_7 = 1'h1; // @[TLB.scala:197:34]
wire pma_checker__ppn_ignore_T_8 = 1'h1; // @[TLB.scala:197:28]
wire pma_checker_ppn_ignore_8 = 1'h1; // @[TLB.scala:197:34]
wire pma_checker__ppn_ignore_T_9 = 1'h1; // @[TLB.scala:197:28]
wire pma_checker_ppn_ignore_9 = 1'h1; // @[TLB.scala:197:34]
wire pma_checker__stage1_bypass_T_1 = 1'h1; // @[TLB.scala:517:83]
wire pma_checker__stage2_bypass_T = 1'h1; // @[TLB.scala:523:42]
wire pma_checker__bad_va_T_1 = 1'h1; // @[TLB.scala:560:26]
wire pma_checker__gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107]
wire pma_checker__tlb_miss_T = 1'h1; // @[TLB.scala:613:32]
wire pma_checker__tlb_miss_T_2 = 1'h1; // @[TLB.scala:613:56]
wire pma_checker__tlb_miss_T_4 = 1'h1; // @[TLB.scala:613:67]
wire pma_checker_state_vec_0_set_left_older = 1'h1; // @[Replacement.scala:196:33]
wire pma_checker_state_vec_0_set_left_older_1 = 1'h1; // @[Replacement.scala:196:33]
wire pma_checker__state_vec_0_T_3 = 1'h1; // @[Replacement.scala:218:7]
wire pma_checker__state_vec_0_T_7 = 1'h1; // @[Replacement.scala:218:7]
wire pma_checker__state_vec_0_T_8 = 1'h1; // @[Replacement.scala:206:16]
wire pma_checker_state_vec_0_set_left_older_2 = 1'h1; // @[Replacement.scala:196:33]
wire pma_checker__state_vec_0_T_14 = 1'h1; // @[Replacement.scala:218:7]
wire pma_checker__state_vec_0_T_18 = 1'h1; // @[Replacement.scala:218:7]
wire pma_checker__state_vec_0_T_19 = 1'h1; // @[Replacement.scala:206:16]
wire pma_checker_state_reg_set_left_older = 1'h1; // @[Replacement.scala:196:33]
wire pma_checker__state_reg_T_2 = 1'h1; // @[Replacement.scala:218:7]
wire pma_checker__state_reg_T_6 = 1'h1; // @[Replacement.scala:218:7]
wire pma_checker__state_reg_T_7 = 1'h1; // @[Replacement.scala:206:16]
wire pma_checker__io_req_ready_T = 1'h1; // @[TLB.scala:631:25]
wire pma_checker__io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20]
wire pma_checker__io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28]
wire pma_checker__r_superpage_repl_addr_T_6 = 1'h1; // @[OneHot.scala:48:45]
wire pma_checker__r_superpage_repl_addr_T_7 = 1'h1; // @[OneHot.scala:48:45]
wire pma_checker__r_superpage_repl_addr_T_8 = 1'h1; // @[OneHot.scala:48:45]
wire pma_checker__r_superpage_repl_addr_T_9 = 1'h1; // @[OneHot.scala:48:45]
wire pma_checker__r_sectored_repl_addr_T_12 = 1'h1; // @[OneHot.scala:48:45]
wire pma_checker__r_sectored_repl_addr_T_13 = 1'h1; // @[OneHot.scala:48:45]
wire pma_checker__r_sectored_repl_addr_T_14 = 1'h1; // @[OneHot.scala:48:45]
wire pma_checker__r_sectored_repl_addr_T_15 = 1'h1; // @[OneHot.scala:48:45]
wire pma_checker__r_sectored_repl_addr_T_16 = 1'h1; // @[OneHot.scala:48:45]
wire pma_checker__r_sectored_repl_addr_T_17 = 1'h1; // @[OneHot.scala:48:45]
wire pma_checker__r_sectored_repl_addr_T_18 = 1'h1; // @[OneHot.scala:48:45]
wire pma_checker__r_sectored_repl_addr_T_19 = 1'h1; // @[OneHot.scala:48:45]
wire pma_checker__tagMatch_T = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__ignore_T_1 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker__ignore_T_2 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__tagMatch_T_1 = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__ignore_T_4 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker__ignore_T_5 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_ignore_5 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__tagMatch_T_2 = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__ignore_T_7 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker__ignore_T_8 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_ignore_8 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__tagMatch_T_3 = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__ignore_T_10 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker__ignore_T_11 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_ignore_11 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__tagMatch_T_4 = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__ignore_T_13 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_ignore_13 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__ignore_T_14 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_ignore_14 = 1'h1; // @[TLB.scala:182:34]
wire metaArb_io_in_0_ready = 1'h1; // @[DCache.scala:135:28]
wire metaArb_io_in_0_bits_write = 1'h1; // @[DCache.scala:135:28]
wire metaArb_io_in_0_bits_way_en = 1'h1; // @[DCache.scala:135:28]
wire metaArb_io_in_1_ready = 1'h1; // @[DCache.scala:135:28]
wire metaArb_io_in_1_bits_write = 1'h1; // @[DCache.scala:135:28]
wire metaArb_io_in_2_ready = 1'h1; // @[DCache.scala:135:28]
wire metaArb_io_in_2_bits_write = 1'h1; // @[DCache.scala:135:28]
wire metaArb_io_in_3_bits_write = 1'h1; // @[DCache.scala:135:28]
wire metaArb_io_in_4_bits_write = 1'h1; // @[DCache.scala:135:28]
wire metaArb_io_out_ready = 1'h1; // @[DCache.scala:135:28]
wire metaArb_grant_1 = 1'h1; // @[Arbiter.scala:45:78]
wire metaArb_grant_2 = 1'h1; // @[Arbiter.scala:45:78]
wire metaArb__io_in_0_ready_T = 1'h1; // @[Arbiter.scala:153:19]
wire metaArb__io_in_1_ready_T = 1'h1; // @[Arbiter.scala:153:19]
wire metaArb__io_in_2_ready_T = 1'h1; // @[Arbiter.scala:153:19]
wire dataArb_io_in_0_ready = 1'h1; // @[DCache.scala:152:28]
wire dataArb_io_in_2_bits_wordMask = 1'h1; // @[DCache.scala:152:28]
wire dataArb_io_in_2_bits_way_en = 1'h1; // @[DCache.scala:152:28]
wire dataArb_io_in_3_bits_wordMask = 1'h1; // @[DCache.scala:152:28]
wire dataArb_io_in_3_bits_way_en = 1'h1; // @[DCache.scala:152:28]
wire dataArb_io_out_ready = 1'h1; // @[DCache.scala:152:28]
wire dataArb__io_in_0_ready_T = 1'h1; // @[Arbiter.scala:153:19]
wire _io_cpu_req_ready_T = 1'h1; // @[DCache.scala:233:38]
wire _dataArb_io_in_3_bits_way_en_T = 1'h1; // @[DCache.scala:257:35]
wire _s2_valid_not_killed_T = 1'h1; // @[DCache.scala:338:48]
wire _s2_flush_valid_T = 1'h1; // @[DCache.scala:363:54]
wire _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T = 1'h1; // @[DCache.scala:397:74]
wire _s2_valid_hit_pre_data_ecc_and_waw_T_1 = 1'h1; // @[DCache.scala:418:108]
wire _s2_valid_hit_pre_data_ecc_T = 1'h1; // @[DCache.scala:420:73]
wire _s2_valid_hit_pre_data_ecc_T_1 = 1'h1; // @[DCache.scala:420:88]
wire _s2_valid_hit_T = 1'h1; // @[DCache.scala:422:51]
wire _s2_valid_miss_T_1 = 1'h1; // @[DCache.scala:423:58]
wire _s2_victimize_T = 1'h1; // @[DCache.scala:429:43]
wire _s2_victim_tag_T_2 = 1'h1; // @[Mux.scala:32:36]
wire _s2_victim_state_T = 1'h1; // @[Mux.scala:32:36]
wire _r_T_117 = 1'h1; // @[Metadata.scala:140:24]
wire _s2_dont_nack_misc_T = 1'h1; // @[DCache.scala:441:46]
wire _s2_dont_nack_misc_T_4 = 1'h1; // @[DCache.scala:442:57]
wire _metaArb_io_in_2_bits_write_T = 1'h1; // @[DCache.scala:463:34]
wire _s2_valid_correct_T_1 = 1'h1; // @[DCache.scala:489:77]
wire _pstore1_merge_T_1 = 1'h1; // @[DCache.scala:490:61]
wire _pstore1_merge_T_3 = 1'h1; // @[DCache.scala:491:51]
wire _pstore_drain_opportunistic_T_61 = 1'h1; // @[DCache.scala:502:95]
wire _pstore1_valid_T_1 = 1'h1; // @[DCache.scala:490:61]
wire _pstore1_valid_T_3 = 1'h1; // @[DCache.scala:491:51]
wire _pstore_drain_T = 1'h1; // @[DCache.scala:516:5]
wire _pstore_drain_T_3 = 1'h1; // @[DCache.scala:506:87]
wire _pstore1_held_T_1 = 1'h1; // @[DCache.scala:490:61]
wire _pstore1_held_T_3 = 1'h1; // @[DCache.scala:491:51]
wire _pstore1_held_T_5 = 1'h1; // @[DCache.scala:521:38]
wire _dataArb_io_in_0_valid_T = 1'h1; // @[DCache.scala:516:5]
wire _dataArb_io_in_0_valid_T_3 = 1'h1; // @[DCache.scala:506:87]
wire _dataArb_io_in_0_bits_wordMask_T = 1'h1; // @[DCache.scala:555:20]
wire _io_cpu_s2_nack_cause_raw_T = 1'h1; // @[DCache.scala:574:59]
wire _io_cpu_s2_nack_cause_raw_T_1 = 1'h1; // @[DCache.scala:574:74]
wire _get_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _get_legal_T_11 = 1'h1; // @[Parameters.scala:92:38]
wire _get_legal_T_12 = 1'h1; // @[Parameters.scala:92:33]
wire _get_legal_T_13 = 1'h1; // @[Parameters.scala:684:29]
wire _put_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _put_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _put_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _put_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _put_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _put_legal_T_11 = 1'h1; // @[Parameters.scala:92:38]
wire _put_legal_T_12 = 1'h1; // @[Parameters.scala:92:33]
wire _put_legal_T_13 = 1'h1; // @[Parameters.scala:684:29]
wire _putpartial_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _putpartial_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _putpartial_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _putpartial_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _putpartial_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _putpartial_legal_T_11 = 1'h1; // @[Parameters.scala:92:38]
wire _putpartial_legal_T_12 = 1'h1; // @[Parameters.scala:92:33]
wire _putpartial_legal_T_13 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_54 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_55 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_56 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_57 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_108 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_109 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_110 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_111 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_162 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_163 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_164 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_165 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_216 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_217 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_218 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_219 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_270 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_271 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_272 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_273 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_324 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_325 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_326 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_327 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_378 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_379 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_380 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_381 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_432 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_433 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_434 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_435 = 1'h1; // @[Parameters.scala:684:29]
wire _tl_out_a_valid_T = 1'h1; // @[DCache.scala:603:21]
wire _tl_out_a_valid_T_5 = 1'h1; // @[DCache.scala:606:8]
wire _tl_out_a_valid_T_7 = 1'h1; // @[DCache.scala:607:47]
wire _tl_out_a_bits_legal_T_31 = 1'h1; // @[Parameters.scala:91:44]
wire _tl_out_a_bits_legal_T_32 = 1'h1; // @[Parameters.scala:684:29]
wire tl_out_a_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire tl_out_a_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26]
wire tl_out_a_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26]
wire tl_out_a_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29]
wire a_sel = 1'h1; // @[DCache.scala:630:66]
wire canAcceptCachedGrant = 1'h1; // @[DCache.scala:670:30]
wire uncachedRespIdxOH = 1'h1; // @[DCache.scala:672:90]
wire _uncachedResp_T = 1'h1; // @[Mux.scala:32:36]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _r_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire c_last = 1'h1; // @[Edges.scala:232:33]
wire _releaseRejected_T_1 = 1'h1; // @[DCache.scala:803:47]
wire _tl_out_c_valid_T_5 = 1'h1; // @[DCache.scala:810:120]
wire _dataArb_io_in_2_bits_wordMask_T = 1'h1; // @[DCache.scala:904:37]
wire _dataArb_io_in_2_bits_way_en_T = 1'h1; // @[DCache.scala:906:35]
wire _io_cpu_resp_valid_T_1 = 1'h1; // @[DCache.scala:949:73]
wire _io_cpu_replay_next_T_2 = 1'h1; // @[DCache.scala:950:65]
wire _s1_flush_valid_T_5 = 1'h1; // @[DCache.scala:1014:110]
wire _s1_flush_valid_T_7 = 1'h1; // @[DCache.scala:1014:125]
wire _metaArb_io_in_0_bits_way_en_T = 1'h1; // @[DCache.scala:1049:35]
wire _clock_en_reg_T = 1'h1; // @[DCache.scala:1060:19]
wire _clock_en_reg_T_2 = 1'h1; // @[DCache.scala:1060:44]
wire _clock_en_reg_T_3 = 1'h1; // @[DCache.scala:1061:46]
wire _clock_en_reg_T_4 = 1'h1; // @[DCache.scala:1062:31]
wire _clock_en_reg_T_5 = 1'h1; // @[DCache.scala:1063:26]
wire _clock_en_reg_T_6 = 1'h1; // @[DCache.scala:1064:14]
wire _clock_en_reg_T_7 = 1'h1; // @[DCache.scala:1064:26]
wire _clock_en_reg_T_8 = 1'h1; // @[DCache.scala:1065:14]
wire _clock_en_reg_T_9 = 1'h1; // @[DCache.scala:1065:26]
wire _clock_en_reg_T_10 = 1'h1; // @[DCache.scala:1066:27]
wire _clock_en_reg_T_11 = 1'h1; // @[DCache.scala:1067:22]
wire _clock_en_reg_T_12 = 1'h1; // @[DCache.scala:1067:42]
wire _clock_en_reg_T_13 = 1'h1; // @[DCache.scala:1068:18]
wire _clock_en_reg_T_15 = 1'h1; // @[DCache.scala:1068:35]
wire _clock_en_reg_T_16 = 1'h1; // @[DCache.scala:1069:31]
wire _clock_en_reg_T_18 = 1'h1; // @[DCache.scala:1070:22]
wire _clock_en_reg_T_20 = 1'h1; // @[DCache.scala:1070:46]
wire _clock_en_reg_T_21 = 1'h1; // @[DCache.scala:1071:23]
wire _clock_en_reg_T_23 = 1'h1; // @[DCache.scala:1072:23]
wire _clock_en_reg_T_25 = 1'h1; // @[DCache.scala:1072:54]
wire _clock_en_reg_T_27 = 1'h1; // @[DCache.scala:1073:21]
wire io_cpu_perf_release_first = 1'h1; // @[Edges.scala:231:25]
wire _io_cpu_perf_release_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire io_cpu_perf_release_last = 1'h1; // @[Edges.scala:232:33]
wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_2 = 1'h1; // @[DCache.scala:1082:31]
wire _io_cpu_perf_storeBufferEmptyAfterStore_T_5 = 1'h1; // @[DCache.scala:1087:31]
wire _io_cpu_perf_canAcceptStoreThenLoad_T_3 = 1'h1; // @[DCache.scala:1089:72]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_56 = 1'h1; // @[DCache.scala:1092:115]
wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[DCache.scala:101:7]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[DCache.scala:101:7]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[DCache.scala:101:7]
wire [15:0] pma_checker_io_ptw_ptbr_asid = 16'h0; // @[DCache.scala:120:32]
wire [15:0] pma_checker_io_ptw_hgatp_asid = 16'h0; // @[DCache.scala:120:32]
wire [15:0] pma_checker_io_ptw_vsatp_asid = 16'h0; // @[DCache.scala:120:32]
wire [15:0] pma_checker_satp_asid = 16'h0; // @[TLB.scala:373:17]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[DCache.scala:101:7]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[DCache.scala:101:7]
wire [3:0] pma_checker_io_ptw_ptbr_mode = 4'h0; // @[DCache.scala:120:32]
wire [3:0] pma_checker_io_ptw_hgatp_mode = 4'h0; // @[DCache.scala:120:32]
wire [3:0] pma_checker_io_ptw_vsatp_mode = 4'h0; // @[DCache.scala:120:32]
wire [3:0] pma_checker_satp_mode = 4'h0; // @[TLB.scala:373:17]
wire [3:0] pma_checker_real_hits_hi_hi = 4'h0; // @[package.scala:45:27]
wire [3:0] pma_checker_lo = 4'h0; // @[OneHot.scala:21:45]
wire [3:0] pma_checker_hi = 4'h0; // @[OneHot.scala:21:45]
wire [3:0] pma_checker_hi_1 = 4'h0; // @[OneHot.scala:30:18]
wire [3:0] pma_checker_lo_1 = 4'h0; // @[OneHot.scala:31:18]
wire [3:0] pma_checker__multipleHits_T_31 = 4'h0; // @[Misc.scala:182:39]
wire [3:0] pma_checker_r_superpage_repl_addr_valids = 4'h0; // @[package.scala:45:27]
wire [3:0] pma_checker_r_sectored_repl_addr_valids_lo = 4'h0; // @[package.scala:45:27]
wire [3:0] pma_checker_r_sectored_repl_addr_valids_hi = 4'h0; // @[package.scala:45:27]
wire [3:0] pma_checker_r_sectored_hit_bits_lo = 4'h0; // @[OneHot.scala:21:45]
wire [3:0] pma_checker_r_sectored_hit_bits_hi = 4'h0; // @[OneHot.scala:21:45]
wire [3:0] pma_checker_r_sectored_hit_bits_hi_1 = 4'h0; // @[OneHot.scala:30:18]
wire [3:0] pma_checker_r_sectored_hit_bits_lo_1 = 4'h0; // @[OneHot.scala:31:18]
wire [3:0] pma_checker__r_sectored_hit_bits_T_2 = 4'h0; // @[OneHot.scala:32:28]
wire [3:0] pma_checker__r_superpage_hit_bits_T = 4'h0; // @[OneHot.scala:21:45]
wire [3:0] tl_out_c_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _s1_probe_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _s1_probe_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _probe_bits_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _probe_bits_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _probe_bits_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _probe_bits_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _r_T_63 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _r_T_127 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _a_mask_T = 4'h0; // @[DCache.scala:582:90]
wire [3:0] _atomics_WIRE_size = 4'h0; // @[DCache.scala:587:51]
wire [3:0] _atomics_WIRE_1_size = 4'h0; // @[DCache.scala:587:38]
wire [3:0] _metaArb_io_in_3_bits_data_T_5 = 4'h0; // @[Metadata.scala:87:10]
wire [3:0] _block_probe_for_pending_release_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _block_probe_for_pending_release_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _metaArb_io_in_6_valid_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _metaArb_io_in_6_valid_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _metaArb_io_in_6_bits_idx_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _metaArb_io_in_6_bits_idx_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _metaArb_io_in_6_bits_addr_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _metaArb_io_in_6_bits_addr_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] nackResponseMessage_size = 4'h0; // @[Edges.scala:416:17]
wire [3:0] cleanReleaseMessage_size = 4'h0; // @[Edges.scala:416:17]
wire [3:0] dirtyReleaseMessage_size = 4'h0; // @[Edges.scala:433:17]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[DCache.scala:101:7]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[DCache.scala:101:7]
wire [43:0] pma_checker_io_ptw_resp_bits_pte_ppn = 44'h0; // @[DCache.scala:120:32]
wire [43:0] pma_checker_io_ptw_ptbr_ppn = 44'h0; // @[DCache.scala:120:32]
wire [43:0] pma_checker_io_ptw_hgatp_ppn = 44'h0; // @[DCache.scala:120:32]
wire [43:0] pma_checker_io_ptw_vsatp_ppn = 44'h0; // @[DCache.scala:120:32]
wire [43:0] pma_checker_satp_ppn = 44'h0; // @[TLB.scala:373:17]
wire [22:0] io_ptw_status_zero2 = 23'h0; // @[DCache.scala:101:7]
wire [22:0] pma_checker_io_ptw_status_zero2 = 23'h0; // @[DCache.scala:120:32]
wire [22:0] pma_checker_io_ptw_gstatus_zero2 = 23'h0; // @[DCache.scala:120:32]
wire [22:0] metaArb_io_in_0_bits_data = 23'h0; // @[DCache.scala:135:28]
wire [22:0] metaArb_io_in_1_bits_data = 23'h0; // @[DCache.scala:135:28]
wire [22:0] s1_meta_0 = 23'h0; // @[DCache.scala:306:58]
wire [22:0] _s2_meta_corrected_WIRE = 23'h0; // @[DCache.scala:361:99]
wire [22:0] _metaArb_io_in_1_bits_data_T = 23'h0; // @[DCache.scala:458:14]
wire [22:0] _metaArb_io_in_0_bits_data_T = 23'h0; // @[DCache.scala:1050:85]
wire [7:0] io_cpu_req_bits_mask = 8'h0; // @[DCache.scala:101:7]
wire [7:0] io_ptw_status_zero1 = 8'h0; // @[DCache.scala:101:7]
wire [7:0] pma_checker_io_ptw_status_zero1 = 8'h0; // @[DCache.scala:120:32]
wire [7:0] pma_checker_io_ptw_gstatus_zero1 = 8'h0; // @[DCache.scala:120:32]
wire [7:0] pma_checker_r_sectored_repl_addr_valids = 8'h0; // @[package.scala:45:27]
wire [7:0] pma_checker__r_sectored_hit_bits_T = 8'h0; // @[OneHot.scala:21:45]
wire [7:0] _s1_probe_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _s1_probe_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _probe_bits_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _probe_bits_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _probe_bits_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _probe_bits_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] s0_req_mask = 8'h0; // @[DCache.scala:192:24]
wire [7:0] _pstore2_storegen_mask_mergedMask_T = 8'h0; // @[DCache.scala:533:42]
wire [7:0] _atomics_WIRE_mask = 8'h0; // @[DCache.scala:587:51]
wire [7:0] _atomics_WIRE_1_mask = 8'h0; // @[DCache.scala:587:38]
wire [7:0] _block_probe_for_pending_release_ack_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _block_probe_for_pending_release_ack_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _metaArb_io_in_6_valid_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _metaArb_io_in_6_valid_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _metaArb_io_in_6_bits_idx_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _metaArb_io_in_6_bits_idx_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _metaArb_io_in_6_bits_addr_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _metaArb_io_in_6_bits_addr_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [1:0] io_ptw_status_xs = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_status_vs = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_tlb_port_req_bits_size = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_tlb_port_req_bits_prv = 2'h0; // @[DCache.scala:101:7]
wire [1:0] pma_checker_io_ptw_resp_bits_pte_reserved_for_software = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_resp_bits_level = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_status_dprv = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_status_prv = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_status_sxl = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_status_uxl = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_status_xs = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_status_fs = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_status_mpp = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_status_vs = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_hstatus_vsxl = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_hstatus_zero3 = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_hstatus_zero2 = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_gstatus_dprv = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_gstatus_prv = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_gstatus_sxl = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_gstatus_uxl = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_gstatus_xs = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_gstatus_fs = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_gstatus_mpp = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_gstatus_vs = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_0_cfg_res = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_0_cfg_a = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_1_cfg_res = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_1_cfg_a = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_2_cfg_res = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_2_cfg_a = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_3_cfg_res = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_3_cfg_a = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_4_cfg_res = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_4_cfg_a = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_5_cfg_res = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_5_cfg_a = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_6_cfg_res = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_6_cfg_a = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_7_cfg_res = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_7_cfg_a = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_real_hits_lo_lo_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker_real_hits_lo_hi_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker_real_hits_hi_lo_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker_real_hits_hi_hi_lo = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker_real_hits_hi_hi_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker__special_entry_level_T = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_special_entry_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_special_entry_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_special_entry_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_special_entry_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_special_entry_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_special_entry_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_waddr = 2'h0; // @[TLB.scala:477:22]
wire [1:0] pma_checker_superpage_entries_0_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_0_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_0_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_0_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_0_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_0_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_1_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_1_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_1_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_1_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_1_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_1_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_2_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_2_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_2_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_2_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_2_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_2_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_3_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_3_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_3_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_3_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_3_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_3_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_idx = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_sectored_entries_0_0_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_0_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_0_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_0_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_0_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_0_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_idx_1 = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_sectored_entries_0_1_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_1_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_1_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_1_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_1_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_1_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_idx_2 = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_sectored_entries_0_2_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_2_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_2_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_2_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_2_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_2_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_idx_3 = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_sectored_entries_0_3_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_3_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_3_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_3_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_3_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_3_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_idx_4 = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_sectored_entries_0_4_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_4_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_4_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_4_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_4_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_4_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_idx_5 = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_sectored_entries_0_5_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_5_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_5_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_5_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_5_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_5_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_idx_6 = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_sectored_entries_0_6_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_6_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_6_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_6_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_6_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_6_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_idx_7 = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_sectored_entries_0_7_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_7_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_7_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_7_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_7_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_7_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker__pr_array_T = 2'h0; // @[TLB.scala:529:26]
wire [1:0] pma_checker__pw_array_T = 2'h0; // @[TLB.scala:531:26]
wire [1:0] pma_checker__px_array_T = 2'h0; // @[TLB.scala:533:26]
wire [1:0] pma_checker__c_array_T = 2'h0; // @[TLB.scala:537:25]
wire [1:0] pma_checker__prefetchable_array_T_1 = 2'h0; // @[TLB.scala:547:59]
wire [1:0] pma_checker_lo_lo = 2'h0; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_lo_hi = 2'h0; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_hi_lo = 2'h0; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_hi_hi = 2'h0; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_hi_2 = 2'h0; // @[OneHot.scala:30:18]
wire [1:0] pma_checker_lo_2 = 2'h0; // @[OneHot.scala:31:18]
wire [1:0] pma_checker__state_vec_0_T = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker__state_vec_0_T_11 = 2'h0; // @[Replacement.scala:207:62]
wire [1:0] pma_checker_lo_3 = 2'h0; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_hi_3 = 2'h0; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_hi_4 = 2'h0; // @[OneHot.scala:30:18]
wire [1:0] pma_checker_lo_4 = 2'h0; // @[OneHot.scala:31:18]
wire [1:0] pma_checker_state_reg_touch_way_sized = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker__multipleHits_T_3 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] pma_checker__multipleHits_T_12 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] pma_checker__multipleHits_T_24 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] pma_checker__multipleHits_T_32 = 2'h0; // @[Misc.scala:181:37]
wire [1:0] pma_checker__multipleHits_T_37 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] pma_checker__r_superpage_repl_addr_T_3 = 2'h0; // @[Replacement.scala:249:12]
wire [1:0] pma_checker_r_superpage_repl_addr_valids_lo = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker_r_superpage_repl_addr_valids_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker__r_superpage_repl_addr_T_12 = 2'h0; // @[Mux.scala:50:70]
wire [1:0] pma_checker__r_superpage_repl_addr_T_13 = 2'h0; // @[TLB.scala:757:8]
wire [1:0] pma_checker__r_sectored_repl_addr_T_3 = 2'h0; // @[Replacement.scala:249:12]
wire [1:0] pma_checker__r_sectored_repl_addr_T_7 = 2'h0; // @[Replacement.scala:249:12]
wire [1:0] pma_checker__r_sectored_repl_addr_T_8 = 2'h0; // @[Replacement.scala:250:16]
wire [1:0] pma_checker_r_sectored_repl_addr_valids_lo_lo = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker_r_sectored_repl_addr_valids_lo_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker_r_sectored_repl_addr_valids_hi_lo = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker_r_sectored_repl_addr_valids_hi_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker_r_sectored_hit_bits_lo_lo = 2'h0; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_r_sectored_hit_bits_lo_hi = 2'h0; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_r_sectored_hit_bits_hi_lo = 2'h0; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_r_sectored_hit_bits_hi_hi = 2'h0; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_r_sectored_hit_bits_hi_2 = 2'h0; // @[OneHot.scala:30:18]
wire [1:0] pma_checker_r_sectored_hit_bits_lo_2 = 2'h0; // @[OneHot.scala:31:18]
wire [1:0] pma_checker__r_sectored_hit_bits_T_4 = 2'h0; // @[OneHot.scala:32:28]
wire [1:0] pma_checker__r_sectored_hit_bits_T_6 = 2'h0; // @[OneHot.scala:32:10]
wire [1:0] pma_checker_r_superpage_hit_bits_lo = 2'h0; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_r_superpage_hit_bits_hi = 2'h0; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_r_superpage_hit_bits_hi_1 = 2'h0; // @[OneHot.scala:30:18]
wire [1:0] pma_checker_r_superpage_hit_bits_lo_1 = 2'h0; // @[OneHot.scala:31:18]
wire [1:0] pma_checker__r_superpage_hit_bits_T_2 = 2'h0; // @[OneHot.scala:32:28]
wire [1:0] pma_checker__r_superpage_hit_bits_T_4 = 2'h0; // @[OneHot.scala:32:10]
wire [1:0] _s1_probe_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _s1_probe_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _probe_bits_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _probe_bits_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _probe_bits_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _probe_bits_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] hitState_meta_1_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] dummyMeta_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] dummyMeta_coh_state = 2'h0; // @[HellaCache.scala:305:20]
wire [1:0] _s2_valid_no_xcpt_T_1 = 2'h0; // @[DCache.scala:332:54]
wire [1:0] s2_meta_corrected_0_coh_state = 2'h0; // @[DCache.scala:361:99]
wire [1:0] _s2_meta_corrected_T_1 = 2'h0; // @[DCache.scala:361:99]
wire [1:0] _r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_75 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_79 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_83 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_87 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_91 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_139 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_143 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_147 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_151 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_155 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] metaArb_io_in_1_bits_data_new_meta_coh_state = 2'h0; // @[DCache.scala:456:31]
wire [1:0] metaArb_io_in_1_bits_data_new_meta_coh_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _metaArb_io_in_3_bits_data_T_2 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _metaArb_io_in_3_bits_data_T_4 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _block_probe_for_pending_release_ack_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _block_probe_for_pending_release_ack_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _metaArb_io_in_6_valid_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _metaArb_io_in_6_valid_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _metaArb_io_in_6_bits_idx_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _metaArb_io_in_6_bits_idx_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _metaArb_io_in_6_bits_addr_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _metaArb_io_in_6_bits_addr_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _io_cpu_s2_xcpt_WIRE_size = 2'h0; // @[DCache.scala:933:74]
wire [1:0] metaArb_io_in_0_bits_data_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] metaArb_io_in_0_bits_data_meta_1_coh_state = 2'h0; // @[HellaCache.scala:305:20]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[DCache.scala:101:7]
wire [29:0] pma_checker_io_ptw_hstatus_zero6 = 30'h0; // @[DCache.scala:120:32]
wire [29:0] pma_checker_io_ptw_pmp_0_addr = 30'h0; // @[DCache.scala:120:32]
wire [29:0] pma_checker_io_ptw_pmp_1_addr = 30'h0; // @[DCache.scala:120:32]
wire [29:0] pma_checker_io_ptw_pmp_2_addr = 30'h0; // @[DCache.scala:120:32]
wire [29:0] pma_checker_io_ptw_pmp_3_addr = 30'h0; // @[DCache.scala:120:32]
wire [29:0] pma_checker_io_ptw_pmp_4_addr = 30'h0; // @[DCache.scala:120:32]
wire [29:0] pma_checker_io_ptw_pmp_5_addr = 30'h0; // @[DCache.scala:120:32]
wire [29:0] pma_checker_io_ptw_pmp_6_addr = 30'h0; // @[DCache.scala:120:32]
wire [29:0] pma_checker_io_ptw_pmp_7_addr = 30'h0; // @[DCache.scala:120:32]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[DCache.scala:101:7]
wire [8:0] pma_checker_io_ptw_hstatus_zero5 = 9'h0; // @[DCache.scala:120:32]
wire [8:0] r_beats1_decode_1 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] r_beats1_1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _r_count_T_1 = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _r_counter_T_1 = 9'h0; // @[Edges.scala:236:21]
wire [8:0] io_cpu_perf_release_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] io_cpu_perf_release_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _io_cpu_perf_release_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] io_cpu_perf_release_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _io_cpu_perf_release_counter_T = 9'h0; // @[Edges.scala:236:21]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[DCache.scala:101:7]
wire [5:0] pma_checker_io_ptw_hstatus_vgein = 6'h0; // @[DCache.scala:120:32]
wire [5:0] pma_checker_real_hits_lo = 6'h0; // @[package.scala:45:27]
wire [5:0] pma_checker_special_entry_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_superpage_entries_0_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_superpage_entries_1_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_superpage_entries_2_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_superpage_entries_3_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_0_data_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_1_data_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_2_data_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_3_data_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_4_data_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_5_data_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_6_data_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_7_data_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker__multipleHits_T = 6'h0; // @[Misc.scala:181:37]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[DCache.scala:101:7]
wire [4:0] io_tlb_port_req_bits_cmd = 5'h0; // @[DCache.scala:101:7]
wire [4:0] pma_checker_io_ptw_hstatus_zero1 = 5'h0; // @[DCache.scala:120:32]
wire [4:0] metaArb_io_in_0_bits_idx = 5'h0; // @[DCache.scala:135:28]
wire [4:0] metaArb_io_in_4_bits_idx = 5'h0; // @[DCache.scala:135:28]
wire [4:0] metaArb_io_in_5_bits_idx = 5'h0; // @[DCache.scala:135:28]
wire [4:0] metaArb_io_in_6_bits_idx = 5'h0; // @[DCache.scala:135:28]
wire [4:0] _metaArb_io_in_1_bits_idx_T = 5'h0; // @[DCache.scala:1200:47]
wire [4:0] _metaArb_io_in_6_bits_idx_T = 5'h0; // @[DCache.scala:1200:47]
wire [4:0] _dataArb_io_in_2_bits_addr_T = 5'h0; // @[DCache.scala:1200:47]
wire [4:0] _metaArb_io_in_4_bits_idx_T = 5'h0; // @[DCache.scala:1200:47]
wire [4:0] _io_cpu_s2_xcpt_WIRE_cmd = 5'h0; // @[DCache.scala:933:74]
wire [4:0] _metaArb_io_in_5_bits_idx_T = 5'h0; // @[DCache.scala:1017:44]
wire [8:0] r_counter1_1 = 9'h1FF; // @[Edges.scala:230:28]
wire [8:0] io_cpu_perf_release_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _r_counter1_T_1 = 10'h3FF; // @[Edges.scala:230:28]
wire [9:0] _io_cpu_perf_release_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [11:0] pma_checker__gpa_hits_hit_mask_T_2 = 12'h0; // @[TLB.scala:606:24]
wire [11:0] pma_checker__io_resp_gpa_offset_T = 12'h0; // @[TLB.scala:658:47]
wire [11:0] _r_beats1_decode_T_5 = 12'h0; // @[package.scala:243:46]
wire [11:0] _io_cpu_perf_release_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _r_beats1_decode_T_4 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _io_cpu_perf_release_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _r_beats1_decode_T_3 = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _io_cpu_perf_release_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [20:0] pma_checker_special_entry_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_superpage_entries_0_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_superpage_entries_1_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_superpage_entries_2_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_superpage_entries_3_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_sectored_entries_0_0_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_sectored_entries_0_1_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_sectored_entries_0_2_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_sectored_entries_0_3_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_sectored_entries_0_4_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_sectored_entries_0_5_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_sectored_entries_0_6_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_sectored_entries_0_7_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] dummyMeta_tag = 21'h0; // @[HellaCache.scala:305:20]
wire [20:0] s2_meta_corrected_0_tag = 21'h0; // @[DCache.scala:361:99]
wire [20:0] _s2_meta_corrected_T = 21'h0; // @[DCache.scala:361:99]
wire [20:0] metaArb_io_in_1_bits_data_new_meta_tag = 21'h0; // @[DCache.scala:456:31]
wire [20:0] _metaArb_io_in_4_bits_data_T = 21'h0; // @[DCache.scala:913:78]
wire [20:0] metaArb_io_in_4_bits_data_meta_tag = 21'h0; // @[HellaCache.scala:305:20]
wire [20:0] metaArb_io_in_0_bits_data_meta_1_tag = 21'h0; // @[HellaCache.scala:305:20]
wire [10:0] _dataArb_io_in_2_bits_addr_T_1 = 11'h0; // @[DCache.scala:903:55]
wire [10:0] _metaArb_io_in_4_bits_addr_T_1 = 11'h0; // @[DCache.scala:912:90]
wire [10:0] _metaArb_io_in_5_bits_addr_T_1 = 11'h0; // @[DCache.scala:1018:98]
wire [4:0] flushCounterWrap = 5'h1; // @[DCache.scala:1011:42]
wire [5:0] flushCounterNext = 6'h1; // @[DCache.scala:1009:39]
wire [31:0] pma_checker_io_ptw_status_isa = 32'h0; // @[DCache.scala:120:32]
wire [31:0] pma_checker_io_ptw_gstatus_isa = 32'h0; // @[DCache.scala:120:32]
wire [31:0] pma_checker_io_ptw_pmp_0_mask = 32'h0; // @[DCache.scala:120:32]
wire [31:0] pma_checker_io_ptw_pmp_1_mask = 32'h0; // @[DCache.scala:120:32]
wire [31:0] pma_checker_io_ptw_pmp_2_mask = 32'h0; // @[DCache.scala:120:32]
wire [31:0] pma_checker_io_ptw_pmp_3_mask = 32'h0; // @[DCache.scala:120:32]
wire [31:0] pma_checker_io_ptw_pmp_4_mask = 32'h0; // @[DCache.scala:120:32]
wire [31:0] pma_checker_io_ptw_pmp_5_mask = 32'h0; // @[DCache.scala:120:32]
wire [31:0] pma_checker_io_ptw_pmp_6_mask = 32'h0; // @[DCache.scala:120:32]
wire [31:0] pma_checker_io_ptw_pmp_7_mask = 32'h0; // @[DCache.scala:120:32]
wire [31:0] tl_out_c_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _s1_probe_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _s1_probe_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _probe_bits_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _probe_bits_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _probe_bits_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _probe_bits_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _atomics_WIRE_address = 32'h0; // @[DCache.scala:587:51]
wire [31:0] _atomics_WIRE_1_address = 32'h0; // @[DCache.scala:587:38]
wire [31:0] _block_probe_for_pending_release_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _block_probe_for_pending_release_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _block_probe_for_pending_release_ack_T = 32'h0; // @[DCache.scala:767:88]
wire [31:0] _metaArb_io_in_6_valid_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _metaArb_io_in_6_valid_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _metaArb_io_in_6_bits_idx_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _metaArb_io_in_6_bits_idx_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _metaArb_io_in_6_bits_addr_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _metaArb_io_in_6_bits_addr_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] nackResponseMessage_address = 32'h0; // @[Edges.scala:416:17]
wire [31:0] cleanReleaseMessage_address = 32'h0; // @[Edges.scala:416:17]
wire [31:0] dirtyReleaseMessage_address = 32'h0; // @[Edges.scala:433:17]
wire [31:0] _io_cpu_s2_xcpt_WIRE_paddr = 32'h0; // @[DCache.scala:933:74]
wire [7:0] pma_checker__r_sectored_repl_addr_T_11 = 8'hFF; // @[TLB.scala:757:43]
wire [7:0] dataArb_io_in_2_bits_eccMask = 8'hFF; // @[DCache.scala:152:28]
wire [7:0] dataArb_io_in_3_bits_eccMask = 8'hFF; // @[DCache.scala:152:28]
wire [7:0] _dataArb_io_in_3_bits_wordMask_T = 8'hFF; // @[DCache.scala:254:9]
wire [7:0] _dataArb_io_in_3_bits_eccMask_T = 8'hFF; // @[DCache.scala:256:36]
wire [7:0] tl_out_a_bits_a_mask = 8'hFF; // @[Edges.scala:346:17]
wire [7:0] _tl_out_a_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10]
wire [7:0] _dataArb_io_in_2_bits_eccMask_T = 8'hFF; // @[DCache.scala:905:36]
wire [2:0] pma_checker__state_vec_0_T_9 = 3'h5; // @[Replacement.scala:202:12]
wire [2:0] pma_checker__state_vec_0_T_20 = 3'h5; // @[Replacement.scala:202:12]
wire [2:0] pma_checker__state_vec_0_T_21 = 3'h5; // @[Replacement.scala:206:16]
wire [2:0] pma_checker__state_reg_T_8 = 3'h5; // @[Replacement.scala:202:12]
wire [2:0] pma_checker__r_sectored_repl_addr_T_21 = 3'h5; // @[Mux.scala:50:70]
wire [2:0] tl_out_c_bits_param = 3'h5; // @[Bundles.scala:265:61]
wire [2:0] tl_out_a_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81]
wire [2:0] nackResponseMessage_param = 3'h5; // @[Edges.scala:416:17]
wire [2:0] dirtyReleaseMessage_opcode = 3'h5; // @[Edges.scala:433:17]
wire [2:0] pma_checker__r_sectored_repl_addr_T_22 = 3'h4; // @[Mux.scala:50:70]
wire [2:0] tl_out_c_bits_opcode = 3'h4; // @[Bundles.scala:265:61]
wire [2:0] get_opcode = 3'h4; // @[Edges.scala:460:17]
wire [2:0] atomics_a_4_param = 3'h4; // @[Edges.scala:517:17]
wire [2:0] _tl_out_a_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27]
wire [2:0] nackResponseMessage_opcode = 3'h4; // @[Edges.scala:416:17]
wire [2:0] cleanReleaseMessage_opcode = 3'h4; // @[Edges.scala:416:17]
wire [2:0] pma_checker_real_hits_lo_lo = 3'h0; // @[package.scala:45:27]
wire [2:0] pma_checker_real_hits_lo_hi = 3'h0; // @[package.scala:45:27]
wire [2:0] pma_checker_real_hits_hi_lo = 3'h0; // @[package.scala:45:27]
wire [2:0] pma_checker_special_entry_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_special_entry_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_special_entry_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_special_entry_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_0_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_0_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_0_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_0_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_1_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_1_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_1_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_1_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_2_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_2_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_2_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_2_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_3_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_3_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_3_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_3_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_waddr_1 = 3'h0; // @[TLB.scala:485:22]
wire [2:0] pma_checker_sectored_entries_0_0_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_0_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_0_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_0_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_1_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_1_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_1_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_1_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_2_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_2_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_2_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_2_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_3_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_3_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_3_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_3_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_4_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_4_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_4_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_4_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_5_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_5_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_5_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_5_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_6_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_6_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_6_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_6_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_7_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_7_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_7_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_7_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_state_vec_0_touch_way_sized = 3'h0; // @[package.scala:163:13]
wire [2:0] pma_checker_state_vec_0_left_subtree_state = 3'h0; // @[package.scala:163:13]
wire [2:0] pma_checker_state_vec_0_right_subtree_state = 3'h0; // @[Replacement.scala:198:38]
wire [2:0] pma_checker__state_vec_0_T_10 = 3'h0; // @[Replacement.scala:203:16]
wire [2:0] pma_checker__multipleHits_T_1 = 3'h0; // @[Misc.scala:181:37]
wire [2:0] pma_checker__multipleHits_T_10 = 3'h0; // @[Misc.scala:182:39]
wire [2:0] pma_checker__multipleHits_T_22 = 3'h0; // @[Misc.scala:181:37]
wire [2:0] pma_checker_r_sectored_repl_addr_left_subtree_state = 3'h0; // @[package.scala:163:13]
wire [2:0] pma_checker_r_sectored_repl_addr_right_subtree_state = 3'h0; // @[Replacement.scala:245:38]
wire [2:0] pma_checker__r_sectored_repl_addr_T_9 = 3'h0; // @[Replacement.scala:249:12]
wire [2:0] pma_checker__r_sectored_repl_addr_T_26 = 3'h0; // @[Mux.scala:50:70]
wire [2:0] pma_checker__r_sectored_repl_addr_T_27 = 3'h0; // @[TLB.scala:757:8]
wire [2:0] pma_checker__r_sectored_hit_bits_T_7 = 3'h0; // @[OneHot.scala:32:10]
wire [2:0] _s1_probe_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _s1_probe_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _probe_bits_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _probe_bits_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _probe_bits_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _probe_bits_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] get_param = 3'h0; // @[Edges.scala:460:17]
wire [2:0] put_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] put_param = 3'h0; // @[Edges.scala:480:17]
wire [2:0] putpartial_param = 3'h0; // @[Edges.scala:500:17]
wire [2:0] _atomics_WIRE_opcode = 3'h0; // @[DCache.scala:587:51]
wire [2:0] _atomics_WIRE_param = 3'h0; // @[DCache.scala:587:51]
wire [2:0] _atomics_WIRE_1_opcode = 3'h0; // @[DCache.scala:587:38]
wire [2:0] _atomics_WIRE_1_param = 3'h0; // @[DCache.scala:587:38]
wire [2:0] atomics_a_1_param = 3'h0; // @[Edges.scala:534:17]
wire [2:0] atomics_a_5_param = 3'h0; // @[Edges.scala:517:17]
wire [2:0] _nodeOut_d_ready_WIRE_bits_sink = 3'h0; // @[Bundles.scala:267:74]
wire [2:0] _nodeOut_d_ready_WIRE_1_bits_sink = 3'h0; // @[Bundles.scala:267:61]
wire [2:0] _block_probe_for_pending_release_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _block_probe_for_pending_release_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _metaArb_io_in_6_valid_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _metaArb_io_in_6_valid_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _metaArb_io_in_6_bits_idx_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _metaArb_io_in_6_bits_idx_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _metaArb_io_in_6_bits_addr_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _metaArb_io_in_6_bits_addr_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [1:0] pma_checker__r_superpage_repl_addr_T_11 = 2'h1; // @[Mux.scala:50:70]
wire [1:0] _r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] s2_victim_way = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] dataArb_io_in_0_bits_wordMask_wordMask = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _dataArb_io_in_0_bits_wordMask_T_2 = 2'h1; // @[DCache.scala:555:20]
wire [1:0] _metaArb_io_in_3_bits_data_T_6 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] io_ptw_status_sxl = 2'h2; // @[DCache.scala:101:7]
wire [1:0] io_ptw_status_uxl = 2'h2; // @[DCache.scala:101:7]
wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[DCache.scala:101:7]
wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[DCache.scala:101:7]
wire [1:0] pma_checker_state_vec_0_hi = 2'h2; // @[Replacement.scala:202:12]
wire [1:0] pma_checker_state_vec_0_hi_1 = 2'h2; // @[Replacement.scala:202:12]
wire [1:0] pma_checker_state_reg_hi = 2'h2; // @[Replacement.scala:202:12]
wire [1:0] pma_checker__r_superpage_repl_addr_T_10 = 2'h2; // @[Mux.scala:50:70]
wire [1:0] pma_checker__state_T = 2'h2; // @[TLB.scala:704:45]
wire [1:0] _r_T_118 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_120 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_122 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] tl_out_a_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49]
wire [1:0] _s1_data_way_T = 2'h2; // @[DCache.scala:694:32]
wire [3:0] pma_checker__r_superpage_repl_addr_T_5 = 4'hF; // @[TLB.scala:757:43]
wire [3:0] _r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] tl_out_a_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10]
wire [3:0] tl_out_a_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10]
wire [2:0] pma_checker__r_sectored_repl_addr_T_20 = 3'h6; // @[Mux.scala:50:70]
wire [2:0] tl_out_a_bits_a_opcode = 3'h6; // @[Edges.scala:346:17]
wire [2:0] _tl_out_a_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34]
wire [2:0] pma_checker__r_sectored_repl_addr_T_23 = 3'h3; // @[Mux.scala:50:70]
wire [2:0] atomics_a_opcode = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_param = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_1_opcode = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_2_opcode = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_3_opcode = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_8_param = 3'h3; // @[Edges.scala:517:17]
wire [2:0] pma_checker__r_sectored_repl_addr_T_24 = 3'h2; // @[Mux.scala:50:70]
wire [2:0] atomics_a_3_param = 3'h2; // @[Edges.scala:534:17]
wire [2:0] atomics_a_4_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_5_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_6_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_7_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_7_param = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_8_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] pma_checker_mpu_priv = 3'h1; // @[TLB.scala:415:27]
wire [2:0] pma_checker__r_sectored_repl_addr_T_25 = 3'h1; // @[Mux.scala:50:70]
wire [2:0] putpartial_opcode = 3'h1; // @[Edges.scala:500:17]
wire [2:0] atomics_a_2_param = 3'h1; // @[Edges.scala:534:17]
wire [2:0] atomics_a_6_param = 3'h1; // @[Edges.scala:517:17]
wire [3:0] pma_checker_state_vec_0_hi_2 = 4'h8; // @[Replacement.scala:202:12]
wire [3:0] _r_T_71 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _r_T_135 = 4'h8; // @[Metadata.scala:133:10]
wire [26:0] pma_checker_io_ptw_req_bits_bits_addr = 27'h0; // @[DCache.scala:120:32]
wire [26:0] pma_checker__io_resp_gpa_page_T_2 = 27'h0; // @[TLB.scala:657:58]
wire [6:0] pma_checker__state_vec_0_T_22 = 7'h45; // @[Replacement.scala:202:12]
wire [63:0] io_cpu_req_bits_data = 64'h0; // @[DCache.scala:101:7]
wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[DCache.scala:101:7]
wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[DCache.scala:101:7]
wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[DCache.scala:101:7]
wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[DCache.scala:101:7]
wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[DCache.scala:120:32]
wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_value = 64'h0; // @[DCache.scala:120:32]
wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[DCache.scala:120:32]
wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[DCache.scala:120:32]
wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_value = 64'h0; // @[DCache.scala:120:32]
wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[DCache.scala:120:32]
wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_wdata = 64'h0; // @[DCache.scala:120:32]
wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_value = 64'h0; // @[DCache.scala:120:32]
wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[DCache.scala:120:32]
wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_wdata = 64'h0; // @[DCache.scala:120:32]
wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_value = 64'h0; // @[DCache.scala:120:32]
wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[DCache.scala:120:32]
wire [63:0] tl_out_c_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _s1_probe_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _s1_probe_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _probe_bits_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _probe_bits_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _probe_bits_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _probe_bits_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] s0_req_data = 64'h0; // @[DCache.scala:192:24]
wire [63:0] get_data = 64'h0; // @[Edges.scala:460:17]
wire [63:0] _atomics_WIRE_data = 64'h0; // @[DCache.scala:587:51]
wire [63:0] _atomics_WIRE_1_data = 64'h0; // @[DCache.scala:587:38]
wire [63:0] tl_out_a_bits_a_data = 64'h0; // @[Edges.scala:346:17]
wire [63:0] _block_probe_for_pending_release_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _block_probe_for_pending_release_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _metaArb_io_in_6_valid_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _metaArb_io_in_6_valid_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _metaArb_io_in_6_bits_idx_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _metaArb_io_in_6_bits_idx_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _metaArb_io_in_6_bits_addr_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _metaArb_io_in_6_bits_addr_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] nackResponseMessage_data = 64'h0; // @[Edges.scala:416:17]
wire [63:0] cleanReleaseMessage_data = 64'h0; // @[Edges.scala:416:17]
wire [63:0] dirtyReleaseMessage_data = 64'h0; // @[Edges.scala:433:17]
wire [63:0] _s2_data_word_possibly_uncached_T_1 = 64'h0; // @[DCache.scala:972:43]
wire [38:0] pma_checker_io_sfence_bits_addr = 39'h0; // @[DCache.scala:120:32]
wire [38:0] pma_checker_io_ptw_resp_bits_gpa_bits = 39'h0; // @[DCache.scala:120:32]
wire [39:0] io_tlb_port_req_bits_vaddr = 40'h0; // @[DCache.scala:101:7]
wire [39:0] _io_cpu_s2_xcpt_WIRE_gpa = 40'h0; // @[DCache.scala:933:74]
wire [9:0] pma_checker_io_ptw_resp_bits_pte_reserved_for_future = 10'h0; // @[DCache.scala:120:32]
wire [9:0] _releaseDataBeat_T = 10'h0; // @[DCache.scala:804:28]
wire [3:0] _r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _metaArb_io_in_3_bits_data_T_9 = 4'hC; // @[Metadata.scala:89:10]
wire [1:0] hitState_meta_state = 2'h3; // @[Metadata.scala:160:20]
wire [1:0] _r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] tl_out_a_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] tl_out_a_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] tl_out_a_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] tl_out_a_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _metaArb_io_in_3_bits_data_T_8 = 2'h3; // @[Metadata.scala:24:15]
wire [3:0] _r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r_T_67 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _r_T_131 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _tl_out_a_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _metaArb_io_in_3_bits_data_T_7 = 4'h4; // @[Metadata.scala:88:10]
wire [3:0] _r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r_T_62 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _r_T_126 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _metaArb_io_in_3_bits_data_T_3 = 4'h1; // @[Metadata.scala:86:10]
wire [3:0] _r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r_T_65 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _r_T_129 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] tl_out_a_bits_a_size = 4'h6; // @[Edges.scala:346:17]
wire [3:0] _r_T_70 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _r_T_134 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _r_T_69 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _r_T_133 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _r_T_68 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _r_T_132 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r_T_66 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _r_T_130 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r_T_64 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _r_T_128 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r_T_61 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _r_T_125 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r_T_60 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _r_T_124 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [21:0] _inScratchpad_T_2 = 22'h200800; // @[DCache.scala:303:70]
wire [22:0] _inScratchpad_T_1 = 23'h200800; // @[DCache.scala:303:70]
wire [21:0] baseAddr = 22'h200000; // @[DCache.scala:302:93]
wire [13:0] pma_checker_lrscAllowed = 14'h0; // @[TLB.scala:580:24]
wire [13:0] pma_checker__gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46]
wire [13:0] pma_checker_gf_ld_array = 14'h0; // @[TLB.scala:600:24]
wire [13:0] pma_checker__gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53]
wire [13:0] pma_checker_gf_st_array = 14'h0; // @[TLB.scala:601:24]
wire [13:0] pma_checker__gf_inst_array_T = 14'h0; // @[TLB.scala:602:36]
wire [13:0] pma_checker_gf_inst_array = 14'h0; // @[TLB.scala:602:26]
wire [13:0] pma_checker_gpa_hits_need_gpa_mask = 14'h0; // @[TLB.scala:605:73]
wire [13:0] pma_checker__io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58]
wire [13:0] pma_checker__io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65]
wire [13:0] pma_checker__io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48]
wire [6:0] pma_checker_real_hits_hi = 7'h0; // @[package.scala:45:27]
wire [6:0] pma_checker__state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25]
wire [6:0] pma_checker__multipleHits_T_21 = 7'h0; // @[Misc.scala:182:39]
wire [12:0] pma_checker_real_hits = 13'h0; // @[package.scala:45:27]
wire [12:0] pma_checker__stage1_bypass_T = 13'h0; // @[TLB.scala:517:27]
wire [12:0] pma_checker_stage1_bypass = 13'h0; // @[TLB.scala:517:61]
wire [12:0] pma_checker__r_array_T_2 = 13'h0; // @[TLB.scala:520:74]
wire [12:0] pma_checker__hr_array_T_2 = 13'h0; // @[TLB.scala:524:60]
wire [12:0] pma_checker__gpa_hits_T = 13'h0; // @[TLB.scala:607:30]
wire [12:0] pma_checker__tlb_hit_T = 13'h0; // @[TLB.scala:611:28]
wire [12:0] pma_checker__stage1_bypass_T_2 = 13'h1FFF; // @[TLB.scala:517:68]
wire [12:0] pma_checker__stage1_bypass_T_4 = 13'h1FFF; // @[TLB.scala:517:95]
wire [12:0] pma_checker_stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27]
wire [12:0] pma_checker__hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111]
wire [12:0] pma_checker__hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55]
wire [12:0] pma_checker__hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55]
wire [12:0] pma_checker__gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88]
wire [12:0] pma_checker_gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82]
wire [12:0] pma_checker__gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16]
wire [12:0] pma_checker_gpa_hits = 13'h1FFF; // @[TLB.scala:607:14]
wire [13:0] pma_checker_hr_array = 14'h3FFF; // @[TLB.scala:524:21]
wire [13:0] pma_checker_hw_array = 14'h3FFF; // @[TLB.scala:525:21]
wire [13:0] pma_checker_hx_array = 14'h3FFF; // @[TLB.scala:526:21]
wire [13:0] pma_checker__ae_array_T_1 = 14'h3FFF; // @[TLB.scala:583:19]
wire [13:0] pma_checker__must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19]
wire [13:0] pma_checker__gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50]
wire [19:0] pma_checker_refill_ppn = 20'h0; // @[TLB.scala:406:44]
wire [19:0] pma_checker_newEntry_ppn = 20'h0; // @[TLB.scala:449:24]
wire [19:0] pma_checker__ppn_T_42 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_43 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_44 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_45 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_46 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_47 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_48 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_49 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_50 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_51 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_52 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_53 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_54 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_56 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_57 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_58 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_59 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_60 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_61 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_62 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_63 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_64 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_65 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_66 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_67 = 20'h0; // @[Mux.scala:30:73]
wire [30:0] pma_checker_special_entry_data_0_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_superpage_entries_0_data_0_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_superpage_entries_1_data_0_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_superpage_entries_2_data_0_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_superpage_entries_3_data_0_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_sectored_entries_0_0_data_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_sectored_entries_0_1_data_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_sectored_entries_0_2_data_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_sectored_entries_0_3_data_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_sectored_entries_0_4_data_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_sectored_entries_0_5_data_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_sectored_entries_0_6_data_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_sectored_entries_0_7_data_hi = 31'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_special_entry_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_superpage_entries_0_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_superpage_entries_1_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_superpage_entries_2_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_superpage_entries_3_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_sectored_entries_0_0_data_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_sectored_entries_0_1_data_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_sectored_entries_0_2_data_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_sectored_entries_0_3_data_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_sectored_entries_0_4_data_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_sectored_entries_0_5_data_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_sectored_entries_0_6_data_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_sectored_entries_0_7_data_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_special_entry_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_superpage_entries_0_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_superpage_entries_1_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_superpage_entries_2_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_superpage_entries_3_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_sectored_entries_0_0_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_sectored_entries_0_1_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_sectored_entries_0_2_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_sectored_entries_0_3_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_sectored_entries_0_4_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_sectored_entries_0_5_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_sectored_entries_0_6_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_sectored_entries_0_7_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [13:0] pma_checker_hits = 14'h2000; // @[TLB.scala:442:17]
wire [41:0] pma_checker__mpu_ppn_WIRE_1 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_1 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_3 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_5 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_7 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_9 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_11 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_13 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_15 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_17 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_19 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_21 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_23 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_25 = 42'h0; // @[TLB.scala:170:77]
wire hartIdSinkNodeOptIn = auto_hart_id_sink_in_0; // @[DCache.scala:101:7]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[DCache.scala:101:7]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[DCache.scala:101:7]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[DCache.scala:101:7]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[DCache.scala:101:7]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[DCache.scala:101:7]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[DCache.scala:101:7]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[DCache.scala:101:7]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[DCache.scala:101:7]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[DCache.scala:101:7]
wire metaArb_io_in_7_valid = io_cpu_req_valid_0; // @[DCache.scala:101:7, :135:28]
wire [39:0] metaArb_io_in_7_bits_addr = io_cpu_req_bits_addr_0; // @[DCache.scala:101:7, :135:28]
wire [7:0] s0_req_tag = io_cpu_req_bits_tag_0; // @[DCache.scala:101:7, :192:24]
wire [4:0] s0_req_cmd = io_cpu_req_bits_cmd_0; // @[DCache.scala:101:7, :192:24]
wire [1:0] s0_req_size = io_cpu_req_bits_size_0; // @[DCache.scala:101:7, :192:24]
wire s0_req_signed = io_cpu_req_bits_signed_0; // @[DCache.scala:101:7, :192:24]
wire [1:0] s0_req_dprv = io_cpu_req_bits_dprv_0; // @[DCache.scala:101:7, :192:24]
wire s0_req_dv = io_cpu_req_bits_dv_0; // @[DCache.scala:101:7, :192:24]
wire s0_req_no_resp = io_cpu_req_bits_no_resp_0; // @[DCache.scala:101:7, :192:24]
wire s0_req_no_xcpt = io_cpu_req_bits_no_xcpt_0; // @[DCache.scala:101:7, :192:24]
wire _io_cpu_s2_nack_T_5; // @[DCache.scala:445:86]
wire _io_cpu_s2_nack_cause_raw_T_3; // @[DCache.scala:574:54]
wire _io_cpu_s2_uncached_T_1; // @[DCache.scala:920:37]
wire _io_cpu_resp_valid_T_2; // @[DCache.scala:949:70]
wire [63:0] _io_cpu_resp_bits_data_T_24; // @[DCache.scala:974:41]
wire s2_read; // @[Consts.scala:89:68]
wire [63:0] _io_cpu_resp_bits_data_word_bypass_T_7; // @[AMOALU.scala:45:16]
wire [63:0] s2_data_word; // @[DCache.scala:970:80]
wire _io_cpu_replay_next_T_3; // @[DCache.scala:950:62]
wire _io_cpu_s2_xcpt_T_ma_ld; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_ma_st; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_pf_ld; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_pf_st; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_ae_ld; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_ae_st; // @[DCache.scala:933:24]
wire _io_cpu_ordered_T_8; // @[DCache.scala:929:21]
wire _io_cpu_store_pending_T_25; // @[DCache.scala:930:70]
wire io_cpu_perf_acquire_done; // @[Edges.scala:233:22]
wire _io_cpu_perf_grant_T; // @[DCache.scala:1078:39]
wire _io_cpu_perf_tlbMiss_T; // @[Decoupled.scala:51:35]
wire _io_cpu_perf_blocked_T_1; // @[DCache.scala:1106:23]
wire _io_cpu_perf_canAcceptStoreThenLoad_T_10; // @[DCache.scala:1088:41]
wire _io_cpu_perf_canAcceptStoreThenRMW_T_1; // @[DCache.scala:1091:75]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_61; // @[DCache.scala:1092:40]
wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_7; // @[DCache.scala:1080:44]
wire _io_cpu_perf_storeBufferEmptyAfterStore_T_10; // @[DCache.scala:1084:45]
wire _io_errors_bus_valid_T_2; // @[DCache.scala:1129:42]
wire [2:0] auto_out_a_bits_opcode_0; // @[DCache.scala:101:7]
wire [2:0] auto_out_a_bits_param_0; // @[DCache.scala:101:7]
wire [3:0] auto_out_a_bits_size_0; // @[DCache.scala:101:7]
wire [31:0] auto_out_a_bits_address_0; // @[DCache.scala:101:7]
wire [7:0] auto_out_a_bits_mask_0; // @[DCache.scala:101:7]
wire [63:0] auto_out_a_bits_data_0; // @[DCache.scala:101:7]
wire auto_out_a_valid_0; // @[DCache.scala:101:7]
wire auto_out_d_ready_0; // @[DCache.scala:101:7]
wire io_cpu_req_ready_0; // @[DCache.scala:101:7]
wire [39:0] io_cpu_resp_bits_addr_0; // @[DCache.scala:101:7]
wire [7:0] io_cpu_resp_bits_tag_0; // @[DCache.scala:101:7]
wire [4:0] io_cpu_resp_bits_cmd_0; // @[DCache.scala:101:7]
wire [1:0] io_cpu_resp_bits_size_0; // @[DCache.scala:101:7]
wire io_cpu_resp_bits_signed_0; // @[DCache.scala:101:7]
wire [1:0] io_cpu_resp_bits_dprv_0; // @[DCache.scala:101:7]
wire io_cpu_resp_bits_dv_0; // @[DCache.scala:101:7]
wire [63:0] io_cpu_resp_bits_data_0; // @[DCache.scala:101:7]
wire [7:0] io_cpu_resp_bits_mask_0; // @[DCache.scala:101:7]
wire io_cpu_resp_bits_replay_0; // @[DCache.scala:101:7]
wire io_cpu_resp_bits_has_data_0; // @[DCache.scala:101:7]
wire [63:0] io_cpu_resp_bits_data_word_bypass_0; // @[DCache.scala:101:7]
wire [63:0] io_cpu_resp_bits_data_raw_0; // @[DCache.scala:101:7]
wire [63:0] io_cpu_resp_bits_store_data_0; // @[DCache.scala:101:7]
wire io_cpu_resp_valid_0; // @[DCache.scala:101:7]
wire io_cpu_s2_xcpt_ma_ld_0; // @[DCache.scala:101:7]
wire io_cpu_s2_xcpt_ma_st_0; // @[DCache.scala:101:7]
wire io_cpu_s2_xcpt_pf_ld_0; // @[DCache.scala:101:7]
wire io_cpu_s2_xcpt_pf_st_0; // @[DCache.scala:101:7]
wire io_cpu_s2_xcpt_ae_ld_0; // @[DCache.scala:101:7]
wire io_cpu_s2_xcpt_ae_st_0; // @[DCache.scala:101:7]
wire io_cpu_perf_acquire_0; // @[DCache.scala:101:7]
wire io_cpu_perf_grant_0; // @[DCache.scala:101:7]
wire io_cpu_perf_tlbMiss_0; // @[DCache.scala:101:7]
wire io_cpu_perf_blocked_0; // @[DCache.scala:101:7]
wire io_cpu_perf_canAcceptStoreThenLoad_0; // @[DCache.scala:101:7]
wire io_cpu_perf_canAcceptStoreThenRMW_0; // @[DCache.scala:101:7]
wire io_cpu_perf_canAcceptLoadThenLoad_0; // @[DCache.scala:101:7]
wire io_cpu_perf_storeBufferEmptyAfterLoad_0; // @[DCache.scala:101:7]
wire io_cpu_perf_storeBufferEmptyAfterStore_0; // @[DCache.scala:101:7]
wire io_cpu_s2_nack_0; // @[DCache.scala:101:7]
wire io_cpu_s2_nack_cause_raw_0; // @[DCache.scala:101:7]
wire io_cpu_s2_uncached_0; // @[DCache.scala:101:7]
wire [31:0] io_cpu_s2_paddr_0; // @[DCache.scala:101:7]
wire io_cpu_replay_next_0; // @[DCache.scala:101:7]
wire [39:0] io_cpu_s2_gpa_0; // @[DCache.scala:101:7]
wire io_cpu_ordered_0; // @[DCache.scala:101:7]
wire io_cpu_store_pending_0; // @[DCache.scala:101:7]
wire [26:0] io_ptw_req_bits_bits_addr_0; // @[DCache.scala:101:7]
wire io_ptw_req_bits_bits_need_gpa_0; // @[DCache.scala:101:7]
wire io_ptw_req_valid_0; // @[DCache.scala:101:7]
wire io_errors_bus_valid; // @[DCache.scala:101:7]
wire [31:0] io_errors_bus_bits; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_pf_ld; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_pf_st; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_pf_inst; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_ae_ld; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_ae_st; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_ae_inst; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_ma_ld; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_ma_st; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_miss; // @[DCache.scala:101:7]
wire [31:0] io_tlb_port_s1_resp_paddr; // @[DCache.scala:101:7]
wire [39:0] io_tlb_port_s1_resp_gpa; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_cacheable; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_must_alloc; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_prefetchable; // @[DCache.scala:101:7]
wire [1:0] io_tlb_port_s1_resp_size; // @[DCache.scala:101:7]
wire [4:0] io_tlb_port_s1_resp_cmd; // @[DCache.scala:101:7]
wire nodeOut_a_deq_ready = nodeOut_a_ready; // @[Decoupled.scala:356:21]
wire nodeOut_a_deq_valid; // @[Decoupled.scala:356:21]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[DCache.scala:101:7]
wire [2:0] nodeOut_a_deq_bits_opcode; // @[Decoupled.scala:356:21]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[DCache.scala:101:7]
wire [2:0] nodeOut_a_deq_bits_param; // @[Decoupled.scala:356:21]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[DCache.scala:101:7]
wire [3:0] nodeOut_a_deq_bits_size; // @[Decoupled.scala:356:21]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[DCache.scala:101:7]
wire [31:0] nodeOut_a_deq_bits_address; // @[Decoupled.scala:356:21]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[DCache.scala:101:7]
wire [7:0] nodeOut_a_deq_bits_mask; // @[Decoupled.scala:356:21]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[DCache.scala:101:7]
wire [63:0] nodeOut_a_deq_bits_data; // @[Decoupled.scala:356:21]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[DCache.scala:101:7]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[DCache.scala:101:7]
wire [2:0] e_sink = nodeOut_d_bits_sink; // @[Edges.scala:451:17]
wire [63:0] s1_uncached_data_word = nodeOut_d_bits_data; // @[package.scala:211:50]
wire [1:0] pma_checker_io_resp_size = pma_checker_io_req_bits_size; // @[DCache.scala:120:32]
wire [4:0] pma_checker_io_resp_cmd = pma_checker_io_req_bits_cmd; // @[DCache.scala:120:32]
wire [31:0] pma_checker__io_resp_paddr_T_1; // @[TLB.scala:652:23]
wire [39:0] pma_checker__io_resp_gpa_T; // @[TLB.scala:659:8]
wire pma_checker__io_resp_pf_ld_T_3; // @[TLB.scala:633:41]
wire pma_checker__io_resp_pf_st_T_3; // @[TLB.scala:634:48]
wire pma_checker__io_resp_pf_inst_T_2; // @[TLB.scala:635:29]
wire pma_checker__io_resp_ae_ld_T_1; // @[TLB.scala:641:41]
wire pma_checker__io_resp_ae_st_T_1; // @[TLB.scala:642:41]
wire pma_checker__io_resp_ae_inst_T_2; // @[TLB.scala:643:41]
wire pma_checker__io_resp_ma_ld_T; // @[TLB.scala:645:31]
wire pma_checker__io_resp_ma_st_T; // @[TLB.scala:646:31]
wire pma_checker__io_resp_cacheable_T_1; // @[TLB.scala:648:41]
wire pma_checker__io_resp_must_alloc_T_1; // @[TLB.scala:649:51]
wire pma_checker__io_resp_prefetchable_T_2; // @[TLB.scala:650:59]
wire [39:0] pma_checker_io_req_bits_vaddr; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_req_bits_prv; // @[DCache.scala:120:32]
wire pma_checker_io_req_bits_v; // @[DCache.scala:120:32]
wire pma_checker_io_resp_pf_ld; // @[DCache.scala:120:32]
wire pma_checker_io_resp_pf_st; // @[DCache.scala:120:32]
wire pma_checker_io_resp_pf_inst; // @[DCache.scala:120:32]
wire pma_checker_io_resp_ae_ld; // @[DCache.scala:120:32]
wire pma_checker_io_resp_ae_st; // @[DCache.scala:120:32]
wire pma_checker_io_resp_ae_inst; // @[DCache.scala:120:32]
wire pma_checker_io_resp_ma_ld; // @[DCache.scala:120:32]
wire pma_checker_io_resp_ma_st; // @[DCache.scala:120:32]
wire [31:0] pma_checker_io_resp_paddr; // @[DCache.scala:120:32]
wire [39:0] pma_checker_io_resp_gpa; // @[DCache.scala:120:32]
wire pma_checker_io_resp_cacheable; // @[DCache.scala:120:32]
wire pma_checker_io_resp_must_alloc; // @[DCache.scala:120:32]
wire pma_checker_io_resp_prefetchable; // @[DCache.scala:120:32]
wire [26:0] pma_checker_vpn = pma_checker_io_req_bits_vaddr[38:12]; // @[TLB.scala:335:30]
wire [26:0] pma_checker__mpu_ppn_T_24 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] pma_checker__mpu_ppn_T_28 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] pma_checker__sector_hits_T_3 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__sector_hits_T_11 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__sector_hits_T_19 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__sector_hits_T_27 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__sector_hits_T_35 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__sector_hits_T_43 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__sector_hits_T_51 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__sector_hits_T_59 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__superpage_hits_T = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__superpage_hits_T_5 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__superpage_hits_T_10 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__superpage_hits_T_14 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__superpage_hits_T_19 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__superpage_hits_T_24 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__superpage_hits_T_28 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__superpage_hits_T_33 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__superpage_hits_T_38 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__superpage_hits_T_42 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__superpage_hits_T_47 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__superpage_hits_T_52 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__hitsVec_T_6 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__hitsVec_T_12 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__hitsVec_T_18 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__hitsVec_T_24 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__hitsVec_T_30 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__hitsVec_T_36 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__hitsVec_T_42 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__hitsVec_T_48 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_53 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_58 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_63 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_68 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_73 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_78 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_83 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_88 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_93 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_98 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_103 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_108 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_113 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_118 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__ppn_T_5 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] pma_checker__ppn_T_13 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] pma_checker__ppn_T_21 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] pma_checker__ppn_T_29 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] pma_checker__ppn_T_33 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] pma_checker__ppn_T_37 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30]
wire pma_checker_priv_s = pma_checker_io_req_bits_prv[0]; // @[TLB.scala:370:20]
wire pma_checker_priv_uses_vm = ~(pma_checker_io_req_bits_prv[1]); // @[TLB.scala:372:27]
wire [19:0] pma_checker__mpu_ppn_T_23; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_22; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_21; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_20; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_19; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_18; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_17; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_16; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_15; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_14; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_13; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_12; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_11; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_10; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_9; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_8; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_7; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_6; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_5; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_4; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_3; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_2; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_1; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_1 = pma_checker__mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_fragmented_superpage = pma_checker__mpu_ppn_T_1; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_2 = pma_checker__mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_c = pma_checker__mpu_ppn_T_2; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_3 = pma_checker__mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_eff = pma_checker__mpu_ppn_T_3; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_4 = pma_checker__mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_paa = pma_checker__mpu_ppn_T_4; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_5 = pma_checker__mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_pal = pma_checker__mpu_ppn_T_5; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_6 = pma_checker__mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_ppp = pma_checker__mpu_ppn_T_6; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_7 = pma_checker__mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_pr = pma_checker__mpu_ppn_T_7; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_8 = pma_checker__mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_px = pma_checker__mpu_ppn_T_8; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_9 = pma_checker__mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_pw = pma_checker__mpu_ppn_T_9; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_10 = pma_checker__mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_hr = pma_checker__mpu_ppn_T_10; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_11 = pma_checker__mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_hx = pma_checker__mpu_ppn_T_11; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_12 = pma_checker__mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_hw = pma_checker__mpu_ppn_T_12; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_13 = pma_checker__mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_sr = pma_checker__mpu_ppn_T_13; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_14 = pma_checker__mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_sx = pma_checker__mpu_ppn_T_14; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_15 = pma_checker__mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_sw = pma_checker__mpu_ppn_T_15; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_16 = pma_checker__mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_gf = pma_checker__mpu_ppn_T_16; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_17 = pma_checker__mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_pf = pma_checker__mpu_ppn_T_17; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_18 = pma_checker__mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_ae_stage2 = pma_checker__mpu_ppn_T_18; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_19 = pma_checker__mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_ae_final = pma_checker__mpu_ppn_T_19; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_20 = pma_checker__mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_ae_ptw = pma_checker__mpu_ppn_T_20; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_21 = pma_checker__mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_g = pma_checker__mpu_ppn_T_21; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_22 = pma_checker__mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_u = pma_checker__mpu_ppn_T_22; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_23 = pma_checker__mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__mpu_ppn_WIRE_ppn = pma_checker__mpu_ppn_T_23; // @[TLB.scala:170:77]
wire [1:0] pma_checker_mpu_ppn_res = _pma_checker_mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25]
wire [26:0] pma_checker__mpu_ppn_T_25 = {pma_checker__mpu_ppn_T_24[26:20], pma_checker__mpu_ppn_T_24[19:0] | _pma_checker_mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] pma_checker__mpu_ppn_T_26 = pma_checker__mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] pma_checker__mpu_ppn_T_27 = {pma_checker_mpu_ppn_res, pma_checker__mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}]
wire [26:0] pma_checker__mpu_ppn_T_29 = {pma_checker__mpu_ppn_T_28[26:20], pma_checker__mpu_ppn_T_28[19:0] | _pma_checker_mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] pma_checker__mpu_ppn_T_30 = pma_checker__mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] pma_checker__mpu_ppn_T_31 = {pma_checker__mpu_ppn_T_27, pma_checker__mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}]
wire [27:0] pma_checker__mpu_ppn_T_32 = pma_checker_io_req_bits_vaddr[39:12]; // @[TLB.scala:413:146]
wire [27:0] pma_checker__mpu_ppn_T_33 = pma_checker__mpu_ppn_T_32; // @[TLB.scala:413:{20,146}]
wire [27:0] pma_checker_mpu_ppn = pma_checker__mpu_ppn_T_33; // @[TLB.scala:412:20, :413:20]
wire [11:0] pma_checker__mpu_physaddr_T = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52]
wire [11:0] pma_checker__io_resp_paddr_T = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52, :652:46]
wire [11:0] pma_checker__io_resp_gpa_offset_T_1 = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52, :658:82]
wire [39:0] pma_checker_mpu_physaddr = {pma_checker_mpu_ppn, pma_checker__mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}]
wire [39:0] pma_checker__homogeneous_T = pma_checker_mpu_physaddr; // @[TLB.scala:414:25]
wire [39:0] pma_checker__deny_access_to_debug_T_1 = pma_checker_mpu_physaddr; // @[TLB.scala:414:25]
wire [2:0] pma_checker__mpu_priv_T_2 = {1'h0, pma_checker_io_req_bits_prv}; // @[TLB.scala:415:103]
wire [40:0] pma_checker__homogeneous_T_1 = {1'h0, pma_checker__homogeneous_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_2 = pma_checker__homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_3 = pma_checker__homogeneous_T_2; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_4 = pma_checker__homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_55 = pma_checker__homogeneous_T_4; // @[TLBPermissions.scala:101:65]
wire [39:0] pma_checker__homogeneous_T_5 = {pma_checker_mpu_physaddr[39:14], pma_checker_mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25]
wire [40:0] pma_checker__homogeneous_T_6 = {1'h0, pma_checker__homogeneous_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_7 = pma_checker__homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_8 = pma_checker__homogeneous_T_7; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_9 = pma_checker__homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN = {pma_checker_mpu_physaddr[39:17], pma_checker_mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25]
wire [39:0] pma_checker__homogeneous_T_10; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_10 = _GEN; // @[Parameters.scala:137:31]
wire [39:0] pma_checker__homogeneous_T_66; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_66 = _GEN; // @[Parameters.scala:137:31]
wire [39:0] pma_checker__homogeneous_T_122; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_122 = _GEN; // @[Parameters.scala:137:31]
wire [39:0] pma_checker__homogeneous_T_129; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_129 = _GEN; // @[Parameters.scala:137:31]
wire [40:0] pma_checker__homogeneous_T_11 = {1'h0, pma_checker__homogeneous_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_12 = pma_checker__homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_13 = pma_checker__homogeneous_T_12; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_14 = pma_checker__homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_0 = {pma_checker_mpu_physaddr[39:21], pma_checker_mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25]
wire [39:0] pma_checker__homogeneous_T_15; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_15 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] pma_checker__homogeneous_T_78; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_78 = _GEN_0; // @[Parameters.scala:137:31]
wire [40:0] pma_checker__homogeneous_T_16 = {1'h0, pma_checker__homogeneous_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_17 = pma_checker__homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_18 = pma_checker__homogeneous_T_17; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_19 = pma_checker__homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] pma_checker__homogeneous_T_20 = {pma_checker_mpu_physaddr[39:22], pma_checker_mpu_physaddr[21:0] ^ 22'h300000}; // @[TLB.scala:414:25]
wire [40:0] pma_checker__homogeneous_T_21 = {1'h0, pma_checker__homogeneous_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_22 = pma_checker__homogeneous_T_21 & 41'h1FFFFFF8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_23 = pma_checker__homogeneous_T_22; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_24 = pma_checker__homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_1 = {pma_checker_mpu_physaddr[39:26], pma_checker_mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25]
wire [39:0] pma_checker__homogeneous_T_25; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_25 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] pma_checker__homogeneous_T_83; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_83 = _GEN_1; // @[Parameters.scala:137:31]
wire [40:0] pma_checker__homogeneous_T_26 = {1'h0, pma_checker__homogeneous_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_27 = pma_checker__homogeneous_T_26 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_28 = pma_checker__homogeneous_T_27; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_29 = pma_checker__homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_2 = {pma_checker_mpu_physaddr[39:26], pma_checker_mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25]
wire [39:0] pma_checker__homogeneous_T_30; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_30 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] pma_checker__homogeneous_T_88; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_88 = _GEN_2; // @[Parameters.scala:137:31]
wire [40:0] pma_checker__homogeneous_T_31 = {1'h0, pma_checker__homogeneous_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_32 = pma_checker__homogeneous_T_31 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_33 = pma_checker__homogeneous_T_32; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_34 = pma_checker__homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_3 = {pma_checker_mpu_physaddr[39:28], pma_checker_mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25]
wire [39:0] pma_checker__homogeneous_T_35; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_35 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] pma_checker__homogeneous_T_110; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_110 = _GEN_3; // @[Parameters.scala:137:31]
wire [40:0] pma_checker__homogeneous_T_36 = {1'h0, pma_checker__homogeneous_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_37 = pma_checker__homogeneous_T_36 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_38 = pma_checker__homogeneous_T_37; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_39 = pma_checker__homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_4 = {pma_checker_mpu_physaddr[39:28], pma_checker_mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25]
wire [39:0] pma_checker__homogeneous_T_40; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_40 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] pma_checker__homogeneous_T_93; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_93 = _GEN_4; // @[Parameters.scala:137:31]
wire [40:0] pma_checker__homogeneous_T_41 = {1'h0, pma_checker__homogeneous_T_40}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_42 = pma_checker__homogeneous_T_41 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_43 = pma_checker__homogeneous_T_42; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_44 = pma_checker__homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] pma_checker__homogeneous_T_45 = {pma_checker_mpu_physaddr[39:29], pma_checker_mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25]
wire [40:0] pma_checker__homogeneous_T_46 = {1'h0, pma_checker__homogeneous_T_45}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_47 = pma_checker__homogeneous_T_46 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_48 = pma_checker__homogeneous_T_47; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_49 = pma_checker__homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_5 = {pma_checker_mpu_physaddr[39:32], pma_checker_mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15]
wire [39:0] pma_checker__homogeneous_T_50; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_50 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] pma_checker__homogeneous_T_115; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_115 = _GEN_5; // @[Parameters.scala:137:31]
wire [40:0] pma_checker__homogeneous_T_51 = {1'h0, pma_checker__homogeneous_T_50}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_52 = pma_checker__homogeneous_T_51 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_53 = pma_checker__homogeneous_T_52; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_54 = pma_checker__homogeneous_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_56 = pma_checker__homogeneous_T_55 | pma_checker__homogeneous_T_9; // @[TLBPermissions.scala:101:65]
wire pma_checker__homogeneous_T_57 = pma_checker__homogeneous_T_56 | pma_checker__homogeneous_T_14; // @[TLBPermissions.scala:101:65]
wire pma_checker__homogeneous_T_58 = pma_checker__homogeneous_T_57 | pma_checker__homogeneous_T_19; // @[TLBPermissions.scala:101:65]
wire pma_checker__homogeneous_T_59 = pma_checker__homogeneous_T_58 | pma_checker__homogeneous_T_24; // @[TLBPermissions.scala:101:65]
wire pma_checker__homogeneous_T_60 = pma_checker__homogeneous_T_59 | pma_checker__homogeneous_T_29; // @[TLBPermissions.scala:101:65]
wire pma_checker__homogeneous_T_61 = pma_checker__homogeneous_T_60 | pma_checker__homogeneous_T_34; // @[TLBPermissions.scala:101:65]
wire pma_checker__homogeneous_T_62 = pma_checker__homogeneous_T_61 | pma_checker__homogeneous_T_39; // @[TLBPermissions.scala:101:65]
wire pma_checker__homogeneous_T_63 = pma_checker__homogeneous_T_62 | pma_checker__homogeneous_T_44; // @[TLBPermissions.scala:101:65]
wire pma_checker__homogeneous_T_64 = pma_checker__homogeneous_T_63 | pma_checker__homogeneous_T_49; // @[TLBPermissions.scala:101:65]
wire pma_checker_homogeneous = pma_checker__homogeneous_T_64 | pma_checker__homogeneous_T_54; // @[TLBPermissions.scala:101:65]
wire [40:0] pma_checker__homogeneous_T_67 = {1'h0, pma_checker__homogeneous_T_66}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_68 = pma_checker__homogeneous_T_67 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_69 = pma_checker__homogeneous_T_68; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_70 = pma_checker__homogeneous_T_69 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_71 = pma_checker__homogeneous_T_70; // @[TLBPermissions.scala:87:66]
wire pma_checker__homogeneous_T_72 = ~pma_checker__homogeneous_T_71; // @[TLBPermissions.scala:87:{22,66}]
wire [39:0] pma_checker__homogeneous_T_73 = {pma_checker_mpu_physaddr[39:13], pma_checker_mpu_physaddr[12:0] ^ 13'h1000}; // @[TLB.scala:414:25]
wire [40:0] pma_checker__homogeneous_T_74 = {1'h0, pma_checker__homogeneous_T_73}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_75 = pma_checker__homogeneous_T_74 & 41'h9E313000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_76 = pma_checker__homogeneous_T_75; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_77 = pma_checker__homogeneous_T_76 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_103 = pma_checker__homogeneous_T_77; // @[TLBPermissions.scala:87:66]
wire [40:0] pma_checker__homogeneous_T_79 = {1'h0, pma_checker__homogeneous_T_78}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_80 = pma_checker__homogeneous_T_79 & 41'h9E303000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_81 = pma_checker__homogeneous_T_80; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_82 = pma_checker__homogeneous_T_81 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] pma_checker__homogeneous_T_84 = {1'h0, pma_checker__homogeneous_T_83}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_85 = pma_checker__homogeneous_T_84 & 41'h9E310000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_86 = pma_checker__homogeneous_T_85; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_87 = pma_checker__homogeneous_T_86 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] pma_checker__homogeneous_T_89 = {1'h0, pma_checker__homogeneous_T_88}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_90 = pma_checker__homogeneous_T_89 & 41'h9E313000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_91 = pma_checker__homogeneous_T_90; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_92 = pma_checker__homogeneous_T_91 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] pma_checker__homogeneous_T_94 = {1'h0, pma_checker__homogeneous_T_93}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_95 = pma_checker__homogeneous_T_94 & 41'h9C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_96 = pma_checker__homogeneous_T_95; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_97 = pma_checker__homogeneous_T_96 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] pma_checker__homogeneous_T_98 = {pma_checker_mpu_physaddr[39:29], pma_checker_mpu_physaddr[28:0] ^ 29'h10000000}; // @[TLB.scala:414:25]
wire [40:0] pma_checker__homogeneous_T_99 = {1'h0, pma_checker__homogeneous_T_98}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_100 = pma_checker__homogeneous_T_99 & 41'h9E313000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_101 = pma_checker__homogeneous_T_100; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_102 = pma_checker__homogeneous_T_101 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_104 = pma_checker__homogeneous_T_103 | pma_checker__homogeneous_T_82; // @[TLBPermissions.scala:87:66]
wire pma_checker__homogeneous_T_105 = pma_checker__homogeneous_T_104 | pma_checker__homogeneous_T_87; // @[TLBPermissions.scala:87:66]
wire pma_checker__homogeneous_T_106 = pma_checker__homogeneous_T_105 | pma_checker__homogeneous_T_92; // @[TLBPermissions.scala:87:66]
wire pma_checker__homogeneous_T_107 = pma_checker__homogeneous_T_106 | pma_checker__homogeneous_T_97; // @[TLBPermissions.scala:87:66]
wire pma_checker__homogeneous_T_108 = pma_checker__homogeneous_T_107 | pma_checker__homogeneous_T_102; // @[TLBPermissions.scala:87:66]
wire pma_checker__homogeneous_T_109 = ~pma_checker__homogeneous_T_108; // @[TLBPermissions.scala:87:{22,66}]
wire [40:0] pma_checker__homogeneous_T_111 = {1'h0, pma_checker__homogeneous_T_110}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_112 = pma_checker__homogeneous_T_111 & 41'h8E100000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_113 = pma_checker__homogeneous_T_112; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_114 = pma_checker__homogeneous_T_113 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_120 = pma_checker__homogeneous_T_114; // @[TLBPermissions.scala:85:66]
wire [40:0] pma_checker__homogeneous_T_116 = {1'h0, pma_checker__homogeneous_T_115}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_117 = pma_checker__homogeneous_T_116 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_118 = pma_checker__homogeneous_T_117; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_119 = pma_checker__homogeneous_T_118 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_121 = pma_checker__homogeneous_T_120 | pma_checker__homogeneous_T_119; // @[TLBPermissions.scala:85:66]
wire [40:0] pma_checker__homogeneous_T_123 = {1'h0, pma_checker__homogeneous_T_122}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_124 = pma_checker__homogeneous_T_123 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_125 = pma_checker__homogeneous_T_124; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_126 = pma_checker__homogeneous_T_125 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_127 = pma_checker__homogeneous_T_126; // @[TLBPermissions.scala:87:66]
wire pma_checker__homogeneous_T_128 = ~pma_checker__homogeneous_T_127; // @[TLBPermissions.scala:87:{22,66}]
wire [40:0] pma_checker__homogeneous_T_130 = {1'h0, pma_checker__homogeneous_T_129}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_131 = pma_checker__homogeneous_T_130 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_132 = pma_checker__homogeneous_T_131; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_133 = pma_checker__homogeneous_T_132 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_134 = pma_checker__homogeneous_T_133; // @[TLBPermissions.scala:87:66]
wire pma_checker__homogeneous_T_135 = ~pma_checker__homogeneous_T_134; // @[TLBPermissions.scala:87:{22,66}]
wire [40:0] pma_checker__deny_access_to_debug_T_2 = {1'h0, pma_checker__deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__deny_access_to_debug_T_3 = pma_checker__deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__deny_access_to_debug_T_4 = pma_checker__deny_access_to_debug_T_3; // @[Parameters.scala:137:46]
wire pma_checker__deny_access_to_debug_T_5 = pma_checker__deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker_deny_access_to_debug = pma_checker__deny_access_to_debug_T_5; // @[TLB.scala:428:50]
wire pma_checker__prot_r_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33]
wire pma_checker__prot_r_T_1 = _pma_checker_pma_io_resp_r & pma_checker__prot_r_T; // @[TLB.scala:422:19, :429:{30,33}]
wire pma_checker__prot_w_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33]
wire pma_checker__prot_w_T_1 = _pma_checker_pma_io_resp_w & pma_checker__prot_w_T; // @[TLB.scala:422:19, :430:{30,33}]
wire pma_checker__prot_x_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33]
wire pma_checker__prot_x_T_1 = _pma_checker_pma_io_resp_x & pma_checker__prot_x_T; // @[TLB.scala:422:19, :434:{30,33}]
wire [24:0] pma_checker__sector_hits_T_4 = pma_checker__sector_hits_T_3[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__sector_hits_T_5 = pma_checker__sector_hits_T_4 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__sector_hits_T_7 = pma_checker__sector_hits_T_5 & pma_checker__sector_hits_T_6; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__sector_hits_T_12 = pma_checker__sector_hits_T_11[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__sector_hits_T_13 = pma_checker__sector_hits_T_12 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__sector_hits_T_15 = pma_checker__sector_hits_T_13 & pma_checker__sector_hits_T_14; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__sector_hits_T_20 = pma_checker__sector_hits_T_19[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__sector_hits_T_21 = pma_checker__sector_hits_T_20 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__sector_hits_T_23 = pma_checker__sector_hits_T_21 & pma_checker__sector_hits_T_22; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__sector_hits_T_28 = pma_checker__sector_hits_T_27[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__sector_hits_T_29 = pma_checker__sector_hits_T_28 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__sector_hits_T_31 = pma_checker__sector_hits_T_29 & pma_checker__sector_hits_T_30; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__sector_hits_T_36 = pma_checker__sector_hits_T_35[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__sector_hits_T_37 = pma_checker__sector_hits_T_36 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__sector_hits_T_39 = pma_checker__sector_hits_T_37 & pma_checker__sector_hits_T_38; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__sector_hits_T_44 = pma_checker__sector_hits_T_43[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__sector_hits_T_45 = pma_checker__sector_hits_T_44 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__sector_hits_T_47 = pma_checker__sector_hits_T_45 & pma_checker__sector_hits_T_46; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__sector_hits_T_52 = pma_checker__sector_hits_T_51[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__sector_hits_T_53 = pma_checker__sector_hits_T_52 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__sector_hits_T_55 = pma_checker__sector_hits_T_53 & pma_checker__sector_hits_T_54; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__sector_hits_T_60 = pma_checker__sector_hits_T_59[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__sector_hits_T_61 = pma_checker__sector_hits_T_60 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__sector_hits_T_63 = pma_checker__sector_hits_T_61 & pma_checker__sector_hits_T_62; // @[TLB.scala:174:{86,95,105}]
wire [8:0] pma_checker__superpage_hits_T_1 = pma_checker__superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}]
wire pma_checker__superpage_hits_T_2 = pma_checker__superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__superpage_hits_T_3 = pma_checker__superpage_hits_T_2; // @[TLB.scala:183:{40,79}]
wire pma_checker_superpage_hits_ignore_1 = pma_checker__superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}]
wire [8:0] pma_checker__superpage_hits_T_6 = pma_checker__superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}]
wire pma_checker__superpage_hits_T_7 = pma_checker__superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__superpage_hits_T_8 = pma_checker_superpage_hits_ignore_1 | pma_checker__superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}]
wire [8:0] pma_checker__superpage_hits_T_11 = pma_checker__superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}]
wire pma_checker__superpage_hits_T_12 = pma_checker__superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}]
wire [8:0] pma_checker__superpage_hits_T_15 = pma_checker__superpage_hits_T_14[26:18]; // @[TLB.scala:183:{52,58}]
wire pma_checker__superpage_hits_T_16 = pma_checker__superpage_hits_T_15 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__superpage_hits_T_17 = pma_checker__superpage_hits_T_16; // @[TLB.scala:183:{40,79}]
wire pma_checker_superpage_hits_ignore_4 = pma_checker__superpage_hits_ignore_T_4; // @[TLB.scala:182:{28,34}]
wire [8:0] pma_checker__superpage_hits_T_20 = pma_checker__superpage_hits_T_19[17:9]; // @[TLB.scala:183:{52,58}]
wire pma_checker__superpage_hits_T_21 = pma_checker__superpage_hits_T_20 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__superpage_hits_T_22 = pma_checker_superpage_hits_ignore_4 | pma_checker__superpage_hits_T_21; // @[TLB.scala:182:34, :183:{40,79}]
wire [8:0] pma_checker__superpage_hits_T_25 = pma_checker__superpage_hits_T_24[8:0]; // @[TLB.scala:183:{52,58}]
wire pma_checker__superpage_hits_T_26 = pma_checker__superpage_hits_T_25 == 9'h0; // @[TLB.scala:183:{58,79}]
wire [8:0] pma_checker__superpage_hits_T_29 = pma_checker__superpage_hits_T_28[26:18]; // @[TLB.scala:183:{52,58}]
wire pma_checker__superpage_hits_T_30 = pma_checker__superpage_hits_T_29 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__superpage_hits_T_31 = pma_checker__superpage_hits_T_30; // @[TLB.scala:183:{40,79}]
wire pma_checker_superpage_hits_ignore_7 = pma_checker__superpage_hits_ignore_T_7; // @[TLB.scala:182:{28,34}]
wire [8:0] pma_checker__superpage_hits_T_34 = pma_checker__superpage_hits_T_33[17:9]; // @[TLB.scala:183:{52,58}]
wire pma_checker__superpage_hits_T_35 = pma_checker__superpage_hits_T_34 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__superpage_hits_T_36 = pma_checker_superpage_hits_ignore_7 | pma_checker__superpage_hits_T_35; // @[TLB.scala:182:34, :183:{40,79}]
wire [8:0] pma_checker__superpage_hits_T_39 = pma_checker__superpage_hits_T_38[8:0]; // @[TLB.scala:183:{52,58}]
wire pma_checker__superpage_hits_T_40 = pma_checker__superpage_hits_T_39 == 9'h0; // @[TLB.scala:183:{58,79}]
wire [8:0] pma_checker__superpage_hits_T_43 = pma_checker__superpage_hits_T_42[26:18]; // @[TLB.scala:183:{52,58}]
wire pma_checker__superpage_hits_T_44 = pma_checker__superpage_hits_T_43 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__superpage_hits_T_45 = pma_checker__superpage_hits_T_44; // @[TLB.scala:183:{40,79}]
wire pma_checker_superpage_hits_ignore_10 = pma_checker__superpage_hits_ignore_T_10; // @[TLB.scala:182:{28,34}]
wire [8:0] pma_checker__superpage_hits_T_48 = pma_checker__superpage_hits_T_47[17:9]; // @[TLB.scala:183:{52,58}]
wire pma_checker__superpage_hits_T_49 = pma_checker__superpage_hits_T_48 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__superpage_hits_T_50 = pma_checker_superpage_hits_ignore_10 | pma_checker__superpage_hits_T_49; // @[TLB.scala:182:34, :183:{40,79}]
wire [8:0] pma_checker__superpage_hits_T_53 = pma_checker__superpage_hits_T_52[8:0]; // @[TLB.scala:183:{52,58}]
wire pma_checker__superpage_hits_T_54 = pma_checker__superpage_hits_T_53 == 9'h0; // @[TLB.scala:183:{58,79}]
wire [1:0] pma_checker_hitsVec_idx = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker_hitsVec_idx_1 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker_hitsVec_idx_2 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker_hitsVec_idx_3 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker_hitsVec_idx_4 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker_hitsVec_idx_5 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker_hitsVec_idx_6 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker_hitsVec_idx_7 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker__entries_T = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker__entries_T_24 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker__entries_T_48 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker__entries_T_72 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker__entries_T_96 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker__entries_T_120 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker__entries_T_144 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker__entries_T_168 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [24:0] pma_checker__hitsVec_T_1 = pma_checker__hitsVec_T[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_2 = pma_checker__hitsVec_T_1 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_4 = pma_checker__hitsVec_T_2 & pma_checker__hitsVec_T_3; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__hitsVec_T_7 = pma_checker__hitsVec_T_6[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_8 = pma_checker__hitsVec_T_7 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_10 = pma_checker__hitsVec_T_8 & pma_checker__hitsVec_T_9; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__hitsVec_T_13 = pma_checker__hitsVec_T_12[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_14 = pma_checker__hitsVec_T_13 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_16 = pma_checker__hitsVec_T_14 & pma_checker__hitsVec_T_15; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__hitsVec_T_19 = pma_checker__hitsVec_T_18[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_20 = pma_checker__hitsVec_T_19 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_22 = pma_checker__hitsVec_T_20 & pma_checker__hitsVec_T_21; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__hitsVec_T_25 = pma_checker__hitsVec_T_24[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_26 = pma_checker__hitsVec_T_25 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_28 = pma_checker__hitsVec_T_26 & pma_checker__hitsVec_T_27; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__hitsVec_T_31 = pma_checker__hitsVec_T_30[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_32 = pma_checker__hitsVec_T_31 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_34 = pma_checker__hitsVec_T_32 & pma_checker__hitsVec_T_33; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__hitsVec_T_37 = pma_checker__hitsVec_T_36[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_38 = pma_checker__hitsVec_T_37 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_40 = pma_checker__hitsVec_T_38 & pma_checker__hitsVec_T_39; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__hitsVec_T_43 = pma_checker__hitsVec_T_42[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_44 = pma_checker__hitsVec_T_43 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_46 = pma_checker__hitsVec_T_44 & pma_checker__hitsVec_T_45; // @[TLB.scala:174:{86,95,105}]
wire [8:0] pma_checker__hitsVec_T_49 = pma_checker__hitsVec_T_48[26:18]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_50 = pma_checker__hitsVec_T_49 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__hitsVec_T_51 = pma_checker__hitsVec_T_50; // @[TLB.scala:183:{40,79}]
wire pma_checker_hitsVec_ignore_1 = pma_checker__hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}]
wire [8:0] pma_checker__hitsVec_T_54 = pma_checker__hitsVec_T_53[17:9]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_55 = pma_checker__hitsVec_T_54 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__hitsVec_T_56 = pma_checker_hitsVec_ignore_1 | pma_checker__hitsVec_T_55; // @[TLB.scala:182:34, :183:{40,79}]
wire [8:0] pma_checker__hitsVec_T_59 = pma_checker__hitsVec_T_58[8:0]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_60 = pma_checker__hitsVec_T_59 == 9'h0; // @[TLB.scala:183:{58,79}]
wire [8:0] pma_checker__hitsVec_T_64 = pma_checker__hitsVec_T_63[26:18]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_65 = pma_checker__hitsVec_T_64 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__hitsVec_T_66 = pma_checker__hitsVec_T_65; // @[TLB.scala:183:{40,79}]
wire pma_checker_hitsVec_ignore_4 = pma_checker__hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}]
wire [8:0] pma_checker__hitsVec_T_69 = pma_checker__hitsVec_T_68[17:9]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_70 = pma_checker__hitsVec_T_69 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__hitsVec_T_71 = pma_checker_hitsVec_ignore_4 | pma_checker__hitsVec_T_70; // @[TLB.scala:182:34, :183:{40,79}]
wire [8:0] pma_checker__hitsVec_T_74 = pma_checker__hitsVec_T_73[8:0]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_75 = pma_checker__hitsVec_T_74 == 9'h0; // @[TLB.scala:183:{58,79}]
wire [8:0] pma_checker__hitsVec_T_79 = pma_checker__hitsVec_T_78[26:18]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_80 = pma_checker__hitsVec_T_79 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__hitsVec_T_81 = pma_checker__hitsVec_T_80; // @[TLB.scala:183:{40,79}]
wire pma_checker_hitsVec_ignore_7 = pma_checker__hitsVec_ignore_T_7; // @[TLB.scala:182:{28,34}]
wire [8:0] pma_checker__hitsVec_T_84 = pma_checker__hitsVec_T_83[17:9]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_85 = pma_checker__hitsVec_T_84 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__hitsVec_T_86 = pma_checker_hitsVec_ignore_7 | pma_checker__hitsVec_T_85; // @[TLB.scala:182:34, :183:{40,79}]
wire [8:0] pma_checker__hitsVec_T_89 = pma_checker__hitsVec_T_88[8:0]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_90 = pma_checker__hitsVec_T_89 == 9'h0; // @[TLB.scala:183:{58,79}]
wire [8:0] pma_checker__hitsVec_T_94 = pma_checker__hitsVec_T_93[26:18]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_95 = pma_checker__hitsVec_T_94 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__hitsVec_T_96 = pma_checker__hitsVec_T_95; // @[TLB.scala:183:{40,79}]
wire pma_checker_hitsVec_ignore_10 = pma_checker__hitsVec_ignore_T_10; // @[TLB.scala:182:{28,34}]
wire [8:0] pma_checker__hitsVec_T_99 = pma_checker__hitsVec_T_98[17:9]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_100 = pma_checker__hitsVec_T_99 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__hitsVec_T_101 = pma_checker_hitsVec_ignore_10 | pma_checker__hitsVec_T_100; // @[TLB.scala:182:34, :183:{40,79}]
wire [8:0] pma_checker__hitsVec_T_104 = pma_checker__hitsVec_T_103[8:0]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_105 = pma_checker__hitsVec_T_104 == 9'h0; // @[TLB.scala:183:{58,79}]
wire [8:0] pma_checker__hitsVec_T_109 = pma_checker__hitsVec_T_108[26:18]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_110 = pma_checker__hitsVec_T_109 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__hitsVec_T_111 = pma_checker__hitsVec_T_110; // @[TLB.scala:183:{40,79}]
wire [8:0] pma_checker__hitsVec_T_114 = pma_checker__hitsVec_T_113[17:9]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_115 = pma_checker__hitsVec_T_114 == 9'h0; // @[TLB.scala:183:{58,79}]
wire [8:0] pma_checker__hitsVec_T_119 = pma_checker__hitsVec_T_118[8:0]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_120 = pma_checker__hitsVec_T_119 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker_newEntry_ppp; // @[TLB.scala:449:24]
wire pma_checker_newEntry_pal; // @[TLB.scala:449:24]
wire pma_checker_newEntry_paa; // @[TLB.scala:449:24]
wire pma_checker_newEntry_eff; // @[TLB.scala:449:24]
wire [1:0] _GEN_6 = {pma_checker_newEntry_pal, pma_checker_newEntry_paa}; // @[TLB.scala:217:24, :449:24]
wire [1:0] pma_checker_special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_special_entry_data_0_lo_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [2:0] pma_checker_special_entry_data_0_lo_lo_hi = {pma_checker_special_entry_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_special_entry_data_0_lo_lo = {pma_checker_special_entry_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] _GEN_7 = {2'h0, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] pma_checker_special_entry_data_0_lo_hi_lo; // @[TLB.scala:217:24]
assign pma_checker_special_entry_data_0_lo_hi_lo = _GEN_7; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_0_data_0_lo_hi_lo; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_0_data_0_lo_hi_lo = _GEN_7; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_1_data_0_lo_hi_lo; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_1_data_0_lo_hi_lo = _GEN_7; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_2_data_0_lo_hi_lo; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_2_data_0_lo_hi_lo = _GEN_7; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_3_data_0_lo_hi_lo; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_3_data_0_lo_hi_lo = _GEN_7; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_0_data_lo_hi_lo; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_0_data_lo_hi_lo = _GEN_7; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_1_data_lo_hi_lo; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_1_data_lo_hi_lo = _GEN_7; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_2_data_lo_hi_lo; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_2_data_lo_hi_lo = _GEN_7; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_3_data_lo_hi_lo; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_3_data_lo_hi_lo = _GEN_7; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_4_data_lo_hi_lo; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_4_data_lo_hi_lo = _GEN_7; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_5_data_lo_hi_lo; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_5_data_lo_hi_lo = _GEN_7; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_6_data_lo_hi_lo; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_6_data_lo_hi_lo = _GEN_7; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_7_data_lo_hi_lo; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_7_data_lo_hi_lo = _GEN_7; // @[TLB.scala:217:24]
wire [5:0] pma_checker_special_entry_data_0_lo_hi = {3'h0, pma_checker_special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_special_entry_data_0_lo = {pma_checker_special_entry_data_0_lo_hi, pma_checker_special_entry_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__special_entry_data_0_T = {31'h0, pma_checker_special_entry_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_0_data_0_lo_lo_hi = {pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_superpage_entries_0_data_0_lo_lo = {pma_checker_superpage_entries_0_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [5:0] pma_checker_superpage_entries_0_data_0_lo_hi = {3'h0, pma_checker_superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_superpage_entries_0_data_0_lo = {pma_checker_superpage_entries_0_data_0_lo_hi, pma_checker_superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__superpage_entries_0_data_0_T = {31'h0, pma_checker_superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_1_data_0_lo_lo_hi = {pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_superpage_entries_1_data_0_lo_lo = {pma_checker_superpage_entries_1_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [5:0] pma_checker_superpage_entries_1_data_0_lo_hi = {3'h0, pma_checker_superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_superpage_entries_1_data_0_lo = {pma_checker_superpage_entries_1_data_0_lo_hi, pma_checker_superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__superpage_entries_1_data_0_T = {31'h0, pma_checker_superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_2_data_0_lo_lo_hi = {pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_superpage_entries_2_data_0_lo_lo = {pma_checker_superpage_entries_2_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [5:0] pma_checker_superpage_entries_2_data_0_lo_hi = {3'h0, pma_checker_superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_superpage_entries_2_data_0_lo = {pma_checker_superpage_entries_2_data_0_lo_hi, pma_checker_superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__superpage_entries_2_data_0_T = {31'h0, pma_checker_superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_3_data_0_lo_lo_hi = {pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_superpage_entries_3_data_0_lo_lo = {pma_checker_superpage_entries_3_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [5:0] pma_checker_superpage_entries_3_data_0_lo_hi = {3'h0, pma_checker_superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_superpage_entries_3_data_0_lo = {pma_checker_superpage_entries_3_data_0_lo_hi, pma_checker_superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__superpage_entries_3_data_0_T = {31'h0, pma_checker_superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_0_data_lo_lo_hi = {pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_sectored_entries_0_0_data_lo_lo = {pma_checker_sectored_entries_0_0_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_0_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_sectored_entries_0_0_data_lo = {pma_checker_sectored_entries_0_0_data_lo_hi, pma_checker_sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__sectored_entries_0_0_data_T = {31'h0, pma_checker_sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_1_data_lo_lo_hi = {pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_sectored_entries_0_1_data_lo_lo = {pma_checker_sectored_entries_0_1_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_1_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_sectored_entries_0_1_data_lo = {pma_checker_sectored_entries_0_1_data_lo_hi, pma_checker_sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__sectored_entries_0_1_data_T = {31'h0, pma_checker_sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_2_data_lo_lo_hi = {pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_sectored_entries_0_2_data_lo_lo = {pma_checker_sectored_entries_0_2_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_2_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_sectored_entries_0_2_data_lo = {pma_checker_sectored_entries_0_2_data_lo_hi, pma_checker_sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__sectored_entries_0_2_data_T = {31'h0, pma_checker_sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_3_data_lo_lo_hi = {pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_sectored_entries_0_3_data_lo_lo = {pma_checker_sectored_entries_0_3_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_3_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_sectored_entries_0_3_data_lo = {pma_checker_sectored_entries_0_3_data_lo_hi, pma_checker_sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__sectored_entries_0_3_data_T = {31'h0, pma_checker_sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_4_data_lo_lo_hi = {pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_sectored_entries_0_4_data_lo_lo = {pma_checker_sectored_entries_0_4_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_4_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_sectored_entries_0_4_data_lo = {pma_checker_sectored_entries_0_4_data_lo_hi, pma_checker_sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__sectored_entries_0_4_data_T = {31'h0, pma_checker_sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_5_data_lo_lo_hi = {pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_sectored_entries_0_5_data_lo_lo = {pma_checker_sectored_entries_0_5_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_5_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_sectored_entries_0_5_data_lo = {pma_checker_sectored_entries_0_5_data_lo_hi, pma_checker_sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__sectored_entries_0_5_data_T = {31'h0, pma_checker_sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_6_data_lo_lo_hi = {pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_sectored_entries_0_6_data_lo_lo = {pma_checker_sectored_entries_0_6_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_6_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_sectored_entries_0_6_data_lo = {pma_checker_sectored_entries_0_6_data_lo_hi, pma_checker_sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__sectored_entries_0_6_data_T = {31'h0, pma_checker_sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_7_data_lo_lo_hi = {pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_sectored_entries_0_7_data_lo_lo = {pma_checker_sectored_entries_0_7_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_7_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_sectored_entries_0_7_data_lo = {pma_checker_sectored_entries_0_7_data_lo_hi, pma_checker_sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__sectored_entries_0_7_data_T = {31'h0, pma_checker_sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24]
wire [19:0] pma_checker__entries_T_23; // @[TLB.scala:170:77]
wire pma_checker__entries_T_22; // @[TLB.scala:170:77]
wire pma_checker__entries_T_21; // @[TLB.scala:170:77]
wire pma_checker__entries_T_20; // @[TLB.scala:170:77]
wire pma_checker__entries_T_19; // @[TLB.scala:170:77]
wire pma_checker__entries_T_18; // @[TLB.scala:170:77]
wire pma_checker__entries_T_17; // @[TLB.scala:170:77]
wire pma_checker__entries_T_16; // @[TLB.scala:170:77]
wire pma_checker__entries_T_15; // @[TLB.scala:170:77]
wire pma_checker__entries_T_14; // @[TLB.scala:170:77]
wire pma_checker__entries_T_13; // @[TLB.scala:170:77]
wire pma_checker__entries_T_12; // @[TLB.scala:170:77]
wire pma_checker__entries_T_11; // @[TLB.scala:170:77]
wire pma_checker__entries_T_10; // @[TLB.scala:170:77]
wire pma_checker__entries_T_9; // @[TLB.scala:170:77]
wire pma_checker__entries_T_8; // @[TLB.scala:170:77]
wire pma_checker__entries_T_7; // @[TLB.scala:170:77]
wire pma_checker__entries_T_6; // @[TLB.scala:170:77]
wire pma_checker__entries_T_5; // @[TLB.scala:170:77]
wire pma_checker__entries_T_4; // @[TLB.scala:170:77]
wire pma_checker__entries_T_3; // @[TLB.scala:170:77]
wire pma_checker__entries_T_2; // @[TLB.scala:170:77]
wire pma_checker__entries_T_1; // @[TLB.scala:170:77]
assign pma_checker__entries_T_1 = pma_checker__entries_WIRE_1[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_fragmented_superpage = pma_checker__entries_T_1; // @[TLB.scala:170:77]
assign pma_checker__entries_T_2 = pma_checker__entries_WIRE_1[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_c = pma_checker__entries_T_2; // @[TLB.scala:170:77]
assign pma_checker__entries_T_3 = pma_checker__entries_WIRE_1[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_eff = pma_checker__entries_T_3; // @[TLB.scala:170:77]
assign pma_checker__entries_T_4 = pma_checker__entries_WIRE_1[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_paa = pma_checker__entries_T_4; // @[TLB.scala:170:77]
assign pma_checker__entries_T_5 = pma_checker__entries_WIRE_1[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_pal = pma_checker__entries_T_5; // @[TLB.scala:170:77]
assign pma_checker__entries_T_6 = pma_checker__entries_WIRE_1[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_ppp = pma_checker__entries_T_6; // @[TLB.scala:170:77]
assign pma_checker__entries_T_7 = pma_checker__entries_WIRE_1[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_pr = pma_checker__entries_T_7; // @[TLB.scala:170:77]
assign pma_checker__entries_T_8 = pma_checker__entries_WIRE_1[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_px = pma_checker__entries_T_8; // @[TLB.scala:170:77]
assign pma_checker__entries_T_9 = pma_checker__entries_WIRE_1[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_pw = pma_checker__entries_T_9; // @[TLB.scala:170:77]
assign pma_checker__entries_T_10 = pma_checker__entries_WIRE_1[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_hr = pma_checker__entries_T_10; // @[TLB.scala:170:77]
assign pma_checker__entries_T_11 = pma_checker__entries_WIRE_1[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_hx = pma_checker__entries_T_11; // @[TLB.scala:170:77]
assign pma_checker__entries_T_12 = pma_checker__entries_WIRE_1[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_hw = pma_checker__entries_T_12; // @[TLB.scala:170:77]
assign pma_checker__entries_T_13 = pma_checker__entries_WIRE_1[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_sr = pma_checker__entries_T_13; // @[TLB.scala:170:77]
assign pma_checker__entries_T_14 = pma_checker__entries_WIRE_1[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_sx = pma_checker__entries_T_14; // @[TLB.scala:170:77]
assign pma_checker__entries_T_15 = pma_checker__entries_WIRE_1[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_sw = pma_checker__entries_T_15; // @[TLB.scala:170:77]
assign pma_checker__entries_T_16 = pma_checker__entries_WIRE_1[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_gf = pma_checker__entries_T_16; // @[TLB.scala:170:77]
assign pma_checker__entries_T_17 = pma_checker__entries_WIRE_1[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_pf = pma_checker__entries_T_17; // @[TLB.scala:170:77]
assign pma_checker__entries_T_18 = pma_checker__entries_WIRE_1[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_ae_stage2 = pma_checker__entries_T_18; // @[TLB.scala:170:77]
assign pma_checker__entries_T_19 = pma_checker__entries_WIRE_1[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_ae_final = pma_checker__entries_T_19; // @[TLB.scala:170:77]
assign pma_checker__entries_T_20 = pma_checker__entries_WIRE_1[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_ae_ptw = pma_checker__entries_T_20; // @[TLB.scala:170:77]
assign pma_checker__entries_T_21 = pma_checker__entries_WIRE_1[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_g = pma_checker__entries_T_21; // @[TLB.scala:170:77]
assign pma_checker__entries_T_22 = pma_checker__entries_WIRE_1[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_u = pma_checker__entries_T_22; // @[TLB.scala:170:77]
assign pma_checker__entries_T_23 = pma_checker__entries_WIRE_1[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_ppn = pma_checker__entries_T_23; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_47; // @[TLB.scala:170:77]
wire pma_checker__entries_T_46; // @[TLB.scala:170:77]
wire pma_checker__entries_T_45; // @[TLB.scala:170:77]
wire pma_checker__entries_T_44; // @[TLB.scala:170:77]
wire pma_checker__entries_T_43; // @[TLB.scala:170:77]
wire pma_checker__entries_T_42; // @[TLB.scala:170:77]
wire pma_checker__entries_T_41; // @[TLB.scala:170:77]
wire pma_checker__entries_T_40; // @[TLB.scala:170:77]
wire pma_checker__entries_T_39; // @[TLB.scala:170:77]
wire pma_checker__entries_T_38; // @[TLB.scala:170:77]
wire pma_checker__entries_T_37; // @[TLB.scala:170:77]
wire pma_checker__entries_T_36; // @[TLB.scala:170:77]
wire pma_checker__entries_T_35; // @[TLB.scala:170:77]
wire pma_checker__entries_T_34; // @[TLB.scala:170:77]
wire pma_checker__entries_T_33; // @[TLB.scala:170:77]
wire pma_checker__entries_T_32; // @[TLB.scala:170:77]
wire pma_checker__entries_T_31; // @[TLB.scala:170:77]
wire pma_checker__entries_T_30; // @[TLB.scala:170:77]
wire pma_checker__entries_T_29; // @[TLB.scala:170:77]
wire pma_checker__entries_T_28; // @[TLB.scala:170:77]
wire pma_checker__entries_T_27; // @[TLB.scala:170:77]
wire pma_checker__entries_T_26; // @[TLB.scala:170:77]
wire pma_checker__entries_T_25; // @[TLB.scala:170:77]
assign pma_checker__entries_T_25 = pma_checker__entries_WIRE_3[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_fragmented_superpage = pma_checker__entries_T_25; // @[TLB.scala:170:77]
assign pma_checker__entries_T_26 = pma_checker__entries_WIRE_3[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_c = pma_checker__entries_T_26; // @[TLB.scala:170:77]
assign pma_checker__entries_T_27 = pma_checker__entries_WIRE_3[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_eff = pma_checker__entries_T_27; // @[TLB.scala:170:77]
assign pma_checker__entries_T_28 = pma_checker__entries_WIRE_3[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_paa = pma_checker__entries_T_28; // @[TLB.scala:170:77]
assign pma_checker__entries_T_29 = pma_checker__entries_WIRE_3[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_pal = pma_checker__entries_T_29; // @[TLB.scala:170:77]
assign pma_checker__entries_T_30 = pma_checker__entries_WIRE_3[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_ppp = pma_checker__entries_T_30; // @[TLB.scala:170:77]
assign pma_checker__entries_T_31 = pma_checker__entries_WIRE_3[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_pr = pma_checker__entries_T_31; // @[TLB.scala:170:77]
assign pma_checker__entries_T_32 = pma_checker__entries_WIRE_3[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_px = pma_checker__entries_T_32; // @[TLB.scala:170:77]
assign pma_checker__entries_T_33 = pma_checker__entries_WIRE_3[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_pw = pma_checker__entries_T_33; // @[TLB.scala:170:77]
assign pma_checker__entries_T_34 = pma_checker__entries_WIRE_3[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_hr = pma_checker__entries_T_34; // @[TLB.scala:170:77]
assign pma_checker__entries_T_35 = pma_checker__entries_WIRE_3[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_hx = pma_checker__entries_T_35; // @[TLB.scala:170:77]
assign pma_checker__entries_T_36 = pma_checker__entries_WIRE_3[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_hw = pma_checker__entries_T_36; // @[TLB.scala:170:77]
assign pma_checker__entries_T_37 = pma_checker__entries_WIRE_3[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_sr = pma_checker__entries_T_37; // @[TLB.scala:170:77]
assign pma_checker__entries_T_38 = pma_checker__entries_WIRE_3[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_sx = pma_checker__entries_T_38; // @[TLB.scala:170:77]
assign pma_checker__entries_T_39 = pma_checker__entries_WIRE_3[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_sw = pma_checker__entries_T_39; // @[TLB.scala:170:77]
assign pma_checker__entries_T_40 = pma_checker__entries_WIRE_3[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_gf = pma_checker__entries_T_40; // @[TLB.scala:170:77]
assign pma_checker__entries_T_41 = pma_checker__entries_WIRE_3[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_pf = pma_checker__entries_T_41; // @[TLB.scala:170:77]
assign pma_checker__entries_T_42 = pma_checker__entries_WIRE_3[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_ae_stage2 = pma_checker__entries_T_42; // @[TLB.scala:170:77]
assign pma_checker__entries_T_43 = pma_checker__entries_WIRE_3[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_ae_final = pma_checker__entries_T_43; // @[TLB.scala:170:77]
assign pma_checker__entries_T_44 = pma_checker__entries_WIRE_3[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_ae_ptw = pma_checker__entries_T_44; // @[TLB.scala:170:77]
assign pma_checker__entries_T_45 = pma_checker__entries_WIRE_3[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_g = pma_checker__entries_T_45; // @[TLB.scala:170:77]
assign pma_checker__entries_T_46 = pma_checker__entries_WIRE_3[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_u = pma_checker__entries_T_46; // @[TLB.scala:170:77]
assign pma_checker__entries_T_47 = pma_checker__entries_WIRE_3[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_2_ppn = pma_checker__entries_T_47; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_71; // @[TLB.scala:170:77]
wire pma_checker__entries_T_70; // @[TLB.scala:170:77]
wire pma_checker__entries_T_69; // @[TLB.scala:170:77]
wire pma_checker__entries_T_68; // @[TLB.scala:170:77]
wire pma_checker__entries_T_67; // @[TLB.scala:170:77]
wire pma_checker__entries_T_66; // @[TLB.scala:170:77]
wire pma_checker__entries_T_65; // @[TLB.scala:170:77]
wire pma_checker__entries_T_64; // @[TLB.scala:170:77]
wire pma_checker__entries_T_63; // @[TLB.scala:170:77]
wire pma_checker__entries_T_62; // @[TLB.scala:170:77]
wire pma_checker__entries_T_61; // @[TLB.scala:170:77]
wire pma_checker__entries_T_60; // @[TLB.scala:170:77]
wire pma_checker__entries_T_59; // @[TLB.scala:170:77]
wire pma_checker__entries_T_58; // @[TLB.scala:170:77]
wire pma_checker__entries_T_57; // @[TLB.scala:170:77]
wire pma_checker__entries_T_56; // @[TLB.scala:170:77]
wire pma_checker__entries_T_55; // @[TLB.scala:170:77]
wire pma_checker__entries_T_54; // @[TLB.scala:170:77]
wire pma_checker__entries_T_53; // @[TLB.scala:170:77]
wire pma_checker__entries_T_52; // @[TLB.scala:170:77]
wire pma_checker__entries_T_51; // @[TLB.scala:170:77]
wire pma_checker__entries_T_50; // @[TLB.scala:170:77]
wire pma_checker__entries_T_49; // @[TLB.scala:170:77]
assign pma_checker__entries_T_49 = pma_checker__entries_WIRE_5[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_fragmented_superpage = pma_checker__entries_T_49; // @[TLB.scala:170:77]
assign pma_checker__entries_T_50 = pma_checker__entries_WIRE_5[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_c = pma_checker__entries_T_50; // @[TLB.scala:170:77]
assign pma_checker__entries_T_51 = pma_checker__entries_WIRE_5[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_eff = pma_checker__entries_T_51; // @[TLB.scala:170:77]
assign pma_checker__entries_T_52 = pma_checker__entries_WIRE_5[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_paa = pma_checker__entries_T_52; // @[TLB.scala:170:77]
assign pma_checker__entries_T_53 = pma_checker__entries_WIRE_5[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_pal = pma_checker__entries_T_53; // @[TLB.scala:170:77]
assign pma_checker__entries_T_54 = pma_checker__entries_WIRE_5[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_ppp = pma_checker__entries_T_54; // @[TLB.scala:170:77]
assign pma_checker__entries_T_55 = pma_checker__entries_WIRE_5[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_pr = pma_checker__entries_T_55; // @[TLB.scala:170:77]
assign pma_checker__entries_T_56 = pma_checker__entries_WIRE_5[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_px = pma_checker__entries_T_56; // @[TLB.scala:170:77]
assign pma_checker__entries_T_57 = pma_checker__entries_WIRE_5[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_pw = pma_checker__entries_T_57; // @[TLB.scala:170:77]
assign pma_checker__entries_T_58 = pma_checker__entries_WIRE_5[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_hr = pma_checker__entries_T_58; // @[TLB.scala:170:77]
assign pma_checker__entries_T_59 = pma_checker__entries_WIRE_5[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_hx = pma_checker__entries_T_59; // @[TLB.scala:170:77]
assign pma_checker__entries_T_60 = pma_checker__entries_WIRE_5[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_hw = pma_checker__entries_T_60; // @[TLB.scala:170:77]
assign pma_checker__entries_T_61 = pma_checker__entries_WIRE_5[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_sr = pma_checker__entries_T_61; // @[TLB.scala:170:77]
assign pma_checker__entries_T_62 = pma_checker__entries_WIRE_5[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_sx = pma_checker__entries_T_62; // @[TLB.scala:170:77]
assign pma_checker__entries_T_63 = pma_checker__entries_WIRE_5[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_sw = pma_checker__entries_T_63; // @[TLB.scala:170:77]
assign pma_checker__entries_T_64 = pma_checker__entries_WIRE_5[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_gf = pma_checker__entries_T_64; // @[TLB.scala:170:77]
assign pma_checker__entries_T_65 = pma_checker__entries_WIRE_5[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_pf = pma_checker__entries_T_65; // @[TLB.scala:170:77]
assign pma_checker__entries_T_66 = pma_checker__entries_WIRE_5[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_ae_stage2 = pma_checker__entries_T_66; // @[TLB.scala:170:77]
assign pma_checker__entries_T_67 = pma_checker__entries_WIRE_5[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_ae_final = pma_checker__entries_T_67; // @[TLB.scala:170:77]
assign pma_checker__entries_T_68 = pma_checker__entries_WIRE_5[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_ae_ptw = pma_checker__entries_T_68; // @[TLB.scala:170:77]
assign pma_checker__entries_T_69 = pma_checker__entries_WIRE_5[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_g = pma_checker__entries_T_69; // @[TLB.scala:170:77]
assign pma_checker__entries_T_70 = pma_checker__entries_WIRE_5[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_u = pma_checker__entries_T_70; // @[TLB.scala:170:77]
assign pma_checker__entries_T_71 = pma_checker__entries_WIRE_5[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_4_ppn = pma_checker__entries_T_71; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_95; // @[TLB.scala:170:77]
wire pma_checker__entries_T_94; // @[TLB.scala:170:77]
wire pma_checker__entries_T_93; // @[TLB.scala:170:77]
wire pma_checker__entries_T_92; // @[TLB.scala:170:77]
wire pma_checker__entries_T_91; // @[TLB.scala:170:77]
wire pma_checker__entries_T_90; // @[TLB.scala:170:77]
wire pma_checker__entries_T_89; // @[TLB.scala:170:77]
wire pma_checker__entries_T_88; // @[TLB.scala:170:77]
wire pma_checker__entries_T_87; // @[TLB.scala:170:77]
wire pma_checker__entries_T_86; // @[TLB.scala:170:77]
wire pma_checker__entries_T_85; // @[TLB.scala:170:77]
wire pma_checker__entries_T_84; // @[TLB.scala:170:77]
wire pma_checker__entries_T_83; // @[TLB.scala:170:77]
wire pma_checker__entries_T_82; // @[TLB.scala:170:77]
wire pma_checker__entries_T_81; // @[TLB.scala:170:77]
wire pma_checker__entries_T_80; // @[TLB.scala:170:77]
wire pma_checker__entries_T_79; // @[TLB.scala:170:77]
wire pma_checker__entries_T_78; // @[TLB.scala:170:77]
wire pma_checker__entries_T_77; // @[TLB.scala:170:77]
wire pma_checker__entries_T_76; // @[TLB.scala:170:77]
wire pma_checker__entries_T_75; // @[TLB.scala:170:77]
wire pma_checker__entries_T_74; // @[TLB.scala:170:77]
wire pma_checker__entries_T_73; // @[TLB.scala:170:77]
assign pma_checker__entries_T_73 = pma_checker__entries_WIRE_7[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_fragmented_superpage = pma_checker__entries_T_73; // @[TLB.scala:170:77]
assign pma_checker__entries_T_74 = pma_checker__entries_WIRE_7[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_c = pma_checker__entries_T_74; // @[TLB.scala:170:77]
assign pma_checker__entries_T_75 = pma_checker__entries_WIRE_7[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_eff = pma_checker__entries_T_75; // @[TLB.scala:170:77]
assign pma_checker__entries_T_76 = pma_checker__entries_WIRE_7[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_paa = pma_checker__entries_T_76; // @[TLB.scala:170:77]
assign pma_checker__entries_T_77 = pma_checker__entries_WIRE_7[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_pal = pma_checker__entries_T_77; // @[TLB.scala:170:77]
assign pma_checker__entries_T_78 = pma_checker__entries_WIRE_7[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_ppp = pma_checker__entries_T_78; // @[TLB.scala:170:77]
assign pma_checker__entries_T_79 = pma_checker__entries_WIRE_7[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_pr = pma_checker__entries_T_79; // @[TLB.scala:170:77]
assign pma_checker__entries_T_80 = pma_checker__entries_WIRE_7[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_px = pma_checker__entries_T_80; // @[TLB.scala:170:77]
assign pma_checker__entries_T_81 = pma_checker__entries_WIRE_7[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_pw = pma_checker__entries_T_81; // @[TLB.scala:170:77]
assign pma_checker__entries_T_82 = pma_checker__entries_WIRE_7[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_hr = pma_checker__entries_T_82; // @[TLB.scala:170:77]
assign pma_checker__entries_T_83 = pma_checker__entries_WIRE_7[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_hx = pma_checker__entries_T_83; // @[TLB.scala:170:77]
assign pma_checker__entries_T_84 = pma_checker__entries_WIRE_7[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_hw = pma_checker__entries_T_84; // @[TLB.scala:170:77]
assign pma_checker__entries_T_85 = pma_checker__entries_WIRE_7[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_sr = pma_checker__entries_T_85; // @[TLB.scala:170:77]
assign pma_checker__entries_T_86 = pma_checker__entries_WIRE_7[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_sx = pma_checker__entries_T_86; // @[TLB.scala:170:77]
assign pma_checker__entries_T_87 = pma_checker__entries_WIRE_7[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_sw = pma_checker__entries_T_87; // @[TLB.scala:170:77]
assign pma_checker__entries_T_88 = pma_checker__entries_WIRE_7[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_gf = pma_checker__entries_T_88; // @[TLB.scala:170:77]
assign pma_checker__entries_T_89 = pma_checker__entries_WIRE_7[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_pf = pma_checker__entries_T_89; // @[TLB.scala:170:77]
assign pma_checker__entries_T_90 = pma_checker__entries_WIRE_7[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_ae_stage2 = pma_checker__entries_T_90; // @[TLB.scala:170:77]
assign pma_checker__entries_T_91 = pma_checker__entries_WIRE_7[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_ae_final = pma_checker__entries_T_91; // @[TLB.scala:170:77]
assign pma_checker__entries_T_92 = pma_checker__entries_WIRE_7[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_ae_ptw = pma_checker__entries_T_92; // @[TLB.scala:170:77]
assign pma_checker__entries_T_93 = pma_checker__entries_WIRE_7[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_g = pma_checker__entries_T_93; // @[TLB.scala:170:77]
assign pma_checker__entries_T_94 = pma_checker__entries_WIRE_7[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_u = pma_checker__entries_T_94; // @[TLB.scala:170:77]
assign pma_checker__entries_T_95 = pma_checker__entries_WIRE_7[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_6_ppn = pma_checker__entries_T_95; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_119; // @[TLB.scala:170:77]
wire pma_checker__entries_T_118; // @[TLB.scala:170:77]
wire pma_checker__entries_T_117; // @[TLB.scala:170:77]
wire pma_checker__entries_T_116; // @[TLB.scala:170:77]
wire pma_checker__entries_T_115; // @[TLB.scala:170:77]
wire pma_checker__entries_T_114; // @[TLB.scala:170:77]
wire pma_checker__entries_T_113; // @[TLB.scala:170:77]
wire pma_checker__entries_T_112; // @[TLB.scala:170:77]
wire pma_checker__entries_T_111; // @[TLB.scala:170:77]
wire pma_checker__entries_T_110; // @[TLB.scala:170:77]
wire pma_checker__entries_T_109; // @[TLB.scala:170:77]
wire pma_checker__entries_T_108; // @[TLB.scala:170:77]
wire pma_checker__entries_T_107; // @[TLB.scala:170:77]
wire pma_checker__entries_T_106; // @[TLB.scala:170:77]
wire pma_checker__entries_T_105; // @[TLB.scala:170:77]
wire pma_checker__entries_T_104; // @[TLB.scala:170:77]
wire pma_checker__entries_T_103; // @[TLB.scala:170:77]
wire pma_checker__entries_T_102; // @[TLB.scala:170:77]
wire pma_checker__entries_T_101; // @[TLB.scala:170:77]
wire pma_checker__entries_T_100; // @[TLB.scala:170:77]
wire pma_checker__entries_T_99; // @[TLB.scala:170:77]
wire pma_checker__entries_T_98; // @[TLB.scala:170:77]
wire pma_checker__entries_T_97; // @[TLB.scala:170:77]
assign pma_checker__entries_T_97 = pma_checker__entries_WIRE_9[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_fragmented_superpage = pma_checker__entries_T_97; // @[TLB.scala:170:77]
assign pma_checker__entries_T_98 = pma_checker__entries_WIRE_9[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_c = pma_checker__entries_T_98; // @[TLB.scala:170:77]
assign pma_checker__entries_T_99 = pma_checker__entries_WIRE_9[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_eff = pma_checker__entries_T_99; // @[TLB.scala:170:77]
assign pma_checker__entries_T_100 = pma_checker__entries_WIRE_9[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_paa = pma_checker__entries_T_100; // @[TLB.scala:170:77]
assign pma_checker__entries_T_101 = pma_checker__entries_WIRE_9[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_pal = pma_checker__entries_T_101; // @[TLB.scala:170:77]
assign pma_checker__entries_T_102 = pma_checker__entries_WIRE_9[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_ppp = pma_checker__entries_T_102; // @[TLB.scala:170:77]
assign pma_checker__entries_T_103 = pma_checker__entries_WIRE_9[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_pr = pma_checker__entries_T_103; // @[TLB.scala:170:77]
assign pma_checker__entries_T_104 = pma_checker__entries_WIRE_9[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_px = pma_checker__entries_T_104; // @[TLB.scala:170:77]
assign pma_checker__entries_T_105 = pma_checker__entries_WIRE_9[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_pw = pma_checker__entries_T_105; // @[TLB.scala:170:77]
assign pma_checker__entries_T_106 = pma_checker__entries_WIRE_9[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_hr = pma_checker__entries_T_106; // @[TLB.scala:170:77]
assign pma_checker__entries_T_107 = pma_checker__entries_WIRE_9[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_hx = pma_checker__entries_T_107; // @[TLB.scala:170:77]
assign pma_checker__entries_T_108 = pma_checker__entries_WIRE_9[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_hw = pma_checker__entries_T_108; // @[TLB.scala:170:77]
assign pma_checker__entries_T_109 = pma_checker__entries_WIRE_9[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_sr = pma_checker__entries_T_109; // @[TLB.scala:170:77]
assign pma_checker__entries_T_110 = pma_checker__entries_WIRE_9[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_sx = pma_checker__entries_T_110; // @[TLB.scala:170:77]
assign pma_checker__entries_T_111 = pma_checker__entries_WIRE_9[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_sw = pma_checker__entries_T_111; // @[TLB.scala:170:77]
assign pma_checker__entries_T_112 = pma_checker__entries_WIRE_9[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_gf = pma_checker__entries_T_112; // @[TLB.scala:170:77]
assign pma_checker__entries_T_113 = pma_checker__entries_WIRE_9[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_pf = pma_checker__entries_T_113; // @[TLB.scala:170:77]
assign pma_checker__entries_T_114 = pma_checker__entries_WIRE_9[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_ae_stage2 = pma_checker__entries_T_114; // @[TLB.scala:170:77]
assign pma_checker__entries_T_115 = pma_checker__entries_WIRE_9[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_ae_final = pma_checker__entries_T_115; // @[TLB.scala:170:77]
assign pma_checker__entries_T_116 = pma_checker__entries_WIRE_9[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_ae_ptw = pma_checker__entries_T_116; // @[TLB.scala:170:77]
assign pma_checker__entries_T_117 = pma_checker__entries_WIRE_9[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_g = pma_checker__entries_T_117; // @[TLB.scala:170:77]
assign pma_checker__entries_T_118 = pma_checker__entries_WIRE_9[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_u = pma_checker__entries_T_118; // @[TLB.scala:170:77]
assign pma_checker__entries_T_119 = pma_checker__entries_WIRE_9[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_8_ppn = pma_checker__entries_T_119; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_143; // @[TLB.scala:170:77]
wire pma_checker__entries_T_142; // @[TLB.scala:170:77]
wire pma_checker__entries_T_141; // @[TLB.scala:170:77]
wire pma_checker__entries_T_140; // @[TLB.scala:170:77]
wire pma_checker__entries_T_139; // @[TLB.scala:170:77]
wire pma_checker__entries_T_138; // @[TLB.scala:170:77]
wire pma_checker__entries_T_137; // @[TLB.scala:170:77]
wire pma_checker__entries_T_136; // @[TLB.scala:170:77]
wire pma_checker__entries_T_135; // @[TLB.scala:170:77]
wire pma_checker__entries_T_134; // @[TLB.scala:170:77]
wire pma_checker__entries_T_133; // @[TLB.scala:170:77]
wire pma_checker__entries_T_132; // @[TLB.scala:170:77]
wire pma_checker__entries_T_131; // @[TLB.scala:170:77]
wire pma_checker__entries_T_130; // @[TLB.scala:170:77]
wire pma_checker__entries_T_129; // @[TLB.scala:170:77]
wire pma_checker__entries_T_128; // @[TLB.scala:170:77]
wire pma_checker__entries_T_127; // @[TLB.scala:170:77]
wire pma_checker__entries_T_126; // @[TLB.scala:170:77]
wire pma_checker__entries_T_125; // @[TLB.scala:170:77]
wire pma_checker__entries_T_124; // @[TLB.scala:170:77]
wire pma_checker__entries_T_123; // @[TLB.scala:170:77]
wire pma_checker__entries_T_122; // @[TLB.scala:170:77]
wire pma_checker__entries_T_121; // @[TLB.scala:170:77]
assign pma_checker__entries_T_121 = pma_checker__entries_WIRE_11[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_fragmented_superpage = pma_checker__entries_T_121; // @[TLB.scala:170:77]
assign pma_checker__entries_T_122 = pma_checker__entries_WIRE_11[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_c = pma_checker__entries_T_122; // @[TLB.scala:170:77]
assign pma_checker__entries_T_123 = pma_checker__entries_WIRE_11[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_eff = pma_checker__entries_T_123; // @[TLB.scala:170:77]
assign pma_checker__entries_T_124 = pma_checker__entries_WIRE_11[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_paa = pma_checker__entries_T_124; // @[TLB.scala:170:77]
assign pma_checker__entries_T_125 = pma_checker__entries_WIRE_11[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_pal = pma_checker__entries_T_125; // @[TLB.scala:170:77]
assign pma_checker__entries_T_126 = pma_checker__entries_WIRE_11[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_ppp = pma_checker__entries_T_126; // @[TLB.scala:170:77]
assign pma_checker__entries_T_127 = pma_checker__entries_WIRE_11[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_pr = pma_checker__entries_T_127; // @[TLB.scala:170:77]
assign pma_checker__entries_T_128 = pma_checker__entries_WIRE_11[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_px = pma_checker__entries_T_128; // @[TLB.scala:170:77]
assign pma_checker__entries_T_129 = pma_checker__entries_WIRE_11[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_pw = pma_checker__entries_T_129; // @[TLB.scala:170:77]
assign pma_checker__entries_T_130 = pma_checker__entries_WIRE_11[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_hr = pma_checker__entries_T_130; // @[TLB.scala:170:77]
assign pma_checker__entries_T_131 = pma_checker__entries_WIRE_11[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_hx = pma_checker__entries_T_131; // @[TLB.scala:170:77]
assign pma_checker__entries_T_132 = pma_checker__entries_WIRE_11[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_hw = pma_checker__entries_T_132; // @[TLB.scala:170:77]
assign pma_checker__entries_T_133 = pma_checker__entries_WIRE_11[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_sr = pma_checker__entries_T_133; // @[TLB.scala:170:77]
assign pma_checker__entries_T_134 = pma_checker__entries_WIRE_11[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_sx = pma_checker__entries_T_134; // @[TLB.scala:170:77]
assign pma_checker__entries_T_135 = pma_checker__entries_WIRE_11[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_sw = pma_checker__entries_T_135; // @[TLB.scala:170:77]
assign pma_checker__entries_T_136 = pma_checker__entries_WIRE_11[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_gf = pma_checker__entries_T_136; // @[TLB.scala:170:77]
assign pma_checker__entries_T_137 = pma_checker__entries_WIRE_11[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_pf = pma_checker__entries_T_137; // @[TLB.scala:170:77]
assign pma_checker__entries_T_138 = pma_checker__entries_WIRE_11[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_ae_stage2 = pma_checker__entries_T_138; // @[TLB.scala:170:77]
assign pma_checker__entries_T_139 = pma_checker__entries_WIRE_11[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_ae_final = pma_checker__entries_T_139; // @[TLB.scala:170:77]
assign pma_checker__entries_T_140 = pma_checker__entries_WIRE_11[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_ae_ptw = pma_checker__entries_T_140; // @[TLB.scala:170:77]
assign pma_checker__entries_T_141 = pma_checker__entries_WIRE_11[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_g = pma_checker__entries_T_141; // @[TLB.scala:170:77]
assign pma_checker__entries_T_142 = pma_checker__entries_WIRE_11[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_u = pma_checker__entries_T_142; // @[TLB.scala:170:77]
assign pma_checker__entries_T_143 = pma_checker__entries_WIRE_11[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_10_ppn = pma_checker__entries_T_143; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_167; // @[TLB.scala:170:77]
wire pma_checker__entries_T_166; // @[TLB.scala:170:77]
wire pma_checker__entries_T_165; // @[TLB.scala:170:77]
wire pma_checker__entries_T_164; // @[TLB.scala:170:77]
wire pma_checker__entries_T_163; // @[TLB.scala:170:77]
wire pma_checker__entries_T_162; // @[TLB.scala:170:77]
wire pma_checker__entries_T_161; // @[TLB.scala:170:77]
wire pma_checker__entries_T_160; // @[TLB.scala:170:77]
wire pma_checker__entries_T_159; // @[TLB.scala:170:77]
wire pma_checker__entries_T_158; // @[TLB.scala:170:77]
wire pma_checker__entries_T_157; // @[TLB.scala:170:77]
wire pma_checker__entries_T_156; // @[TLB.scala:170:77]
wire pma_checker__entries_T_155; // @[TLB.scala:170:77]
wire pma_checker__entries_T_154; // @[TLB.scala:170:77]
wire pma_checker__entries_T_153; // @[TLB.scala:170:77]
wire pma_checker__entries_T_152; // @[TLB.scala:170:77]
wire pma_checker__entries_T_151; // @[TLB.scala:170:77]
wire pma_checker__entries_T_150; // @[TLB.scala:170:77]
wire pma_checker__entries_T_149; // @[TLB.scala:170:77]
wire pma_checker__entries_T_148; // @[TLB.scala:170:77]
wire pma_checker__entries_T_147; // @[TLB.scala:170:77]
wire pma_checker__entries_T_146; // @[TLB.scala:170:77]
wire pma_checker__entries_T_145; // @[TLB.scala:170:77]
assign pma_checker__entries_T_145 = pma_checker__entries_WIRE_13[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_fragmented_superpage = pma_checker__entries_T_145; // @[TLB.scala:170:77]
assign pma_checker__entries_T_146 = pma_checker__entries_WIRE_13[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_c = pma_checker__entries_T_146; // @[TLB.scala:170:77]
assign pma_checker__entries_T_147 = pma_checker__entries_WIRE_13[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_eff = pma_checker__entries_T_147; // @[TLB.scala:170:77]
assign pma_checker__entries_T_148 = pma_checker__entries_WIRE_13[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_paa = pma_checker__entries_T_148; // @[TLB.scala:170:77]
assign pma_checker__entries_T_149 = pma_checker__entries_WIRE_13[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_pal = pma_checker__entries_T_149; // @[TLB.scala:170:77]
assign pma_checker__entries_T_150 = pma_checker__entries_WIRE_13[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_ppp = pma_checker__entries_T_150; // @[TLB.scala:170:77]
assign pma_checker__entries_T_151 = pma_checker__entries_WIRE_13[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_pr = pma_checker__entries_T_151; // @[TLB.scala:170:77]
assign pma_checker__entries_T_152 = pma_checker__entries_WIRE_13[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_px = pma_checker__entries_T_152; // @[TLB.scala:170:77]
assign pma_checker__entries_T_153 = pma_checker__entries_WIRE_13[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_pw = pma_checker__entries_T_153; // @[TLB.scala:170:77]
assign pma_checker__entries_T_154 = pma_checker__entries_WIRE_13[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_hr = pma_checker__entries_T_154; // @[TLB.scala:170:77]
assign pma_checker__entries_T_155 = pma_checker__entries_WIRE_13[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_hx = pma_checker__entries_T_155; // @[TLB.scala:170:77]
assign pma_checker__entries_T_156 = pma_checker__entries_WIRE_13[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_hw = pma_checker__entries_T_156; // @[TLB.scala:170:77]
assign pma_checker__entries_T_157 = pma_checker__entries_WIRE_13[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_sr = pma_checker__entries_T_157; // @[TLB.scala:170:77]
assign pma_checker__entries_T_158 = pma_checker__entries_WIRE_13[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_sx = pma_checker__entries_T_158; // @[TLB.scala:170:77]
assign pma_checker__entries_T_159 = pma_checker__entries_WIRE_13[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_sw = pma_checker__entries_T_159; // @[TLB.scala:170:77]
assign pma_checker__entries_T_160 = pma_checker__entries_WIRE_13[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_gf = pma_checker__entries_T_160; // @[TLB.scala:170:77]
assign pma_checker__entries_T_161 = pma_checker__entries_WIRE_13[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_pf = pma_checker__entries_T_161; // @[TLB.scala:170:77]
assign pma_checker__entries_T_162 = pma_checker__entries_WIRE_13[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_ae_stage2 = pma_checker__entries_T_162; // @[TLB.scala:170:77]
assign pma_checker__entries_T_163 = pma_checker__entries_WIRE_13[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_ae_final = pma_checker__entries_T_163; // @[TLB.scala:170:77]
assign pma_checker__entries_T_164 = pma_checker__entries_WIRE_13[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_ae_ptw = pma_checker__entries_T_164; // @[TLB.scala:170:77]
assign pma_checker__entries_T_165 = pma_checker__entries_WIRE_13[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_g = pma_checker__entries_T_165; // @[TLB.scala:170:77]
assign pma_checker__entries_T_166 = pma_checker__entries_WIRE_13[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_u = pma_checker__entries_T_166; // @[TLB.scala:170:77]
assign pma_checker__entries_T_167 = pma_checker__entries_WIRE_13[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_12_ppn = pma_checker__entries_T_167; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_191; // @[TLB.scala:170:77]
wire pma_checker__entries_T_190; // @[TLB.scala:170:77]
wire pma_checker__entries_T_189; // @[TLB.scala:170:77]
wire pma_checker__entries_T_188; // @[TLB.scala:170:77]
wire pma_checker__entries_T_187; // @[TLB.scala:170:77]
wire pma_checker__entries_T_186; // @[TLB.scala:170:77]
wire pma_checker__entries_T_185; // @[TLB.scala:170:77]
wire pma_checker__entries_T_184; // @[TLB.scala:170:77]
wire pma_checker__entries_T_183; // @[TLB.scala:170:77]
wire pma_checker__entries_T_182; // @[TLB.scala:170:77]
wire pma_checker__entries_T_181; // @[TLB.scala:170:77]
wire pma_checker__entries_T_180; // @[TLB.scala:170:77]
wire pma_checker__entries_T_179; // @[TLB.scala:170:77]
wire pma_checker__entries_T_178; // @[TLB.scala:170:77]
wire pma_checker__entries_T_177; // @[TLB.scala:170:77]
wire pma_checker__entries_T_176; // @[TLB.scala:170:77]
wire pma_checker__entries_T_175; // @[TLB.scala:170:77]
wire pma_checker__entries_T_174; // @[TLB.scala:170:77]
wire pma_checker__entries_T_173; // @[TLB.scala:170:77]
wire pma_checker__entries_T_172; // @[TLB.scala:170:77]
wire pma_checker__entries_T_171; // @[TLB.scala:170:77]
wire pma_checker__entries_T_170; // @[TLB.scala:170:77]
wire pma_checker__entries_T_169; // @[TLB.scala:170:77]
assign pma_checker__entries_T_169 = pma_checker__entries_WIRE_15[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_fragmented_superpage = pma_checker__entries_T_169; // @[TLB.scala:170:77]
assign pma_checker__entries_T_170 = pma_checker__entries_WIRE_15[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_c = pma_checker__entries_T_170; // @[TLB.scala:170:77]
assign pma_checker__entries_T_171 = pma_checker__entries_WIRE_15[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_eff = pma_checker__entries_T_171; // @[TLB.scala:170:77]
assign pma_checker__entries_T_172 = pma_checker__entries_WIRE_15[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_paa = pma_checker__entries_T_172; // @[TLB.scala:170:77]
assign pma_checker__entries_T_173 = pma_checker__entries_WIRE_15[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_pal = pma_checker__entries_T_173; // @[TLB.scala:170:77]
assign pma_checker__entries_T_174 = pma_checker__entries_WIRE_15[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_ppp = pma_checker__entries_T_174; // @[TLB.scala:170:77]
assign pma_checker__entries_T_175 = pma_checker__entries_WIRE_15[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_pr = pma_checker__entries_T_175; // @[TLB.scala:170:77]
assign pma_checker__entries_T_176 = pma_checker__entries_WIRE_15[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_px = pma_checker__entries_T_176; // @[TLB.scala:170:77]
assign pma_checker__entries_T_177 = pma_checker__entries_WIRE_15[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_pw = pma_checker__entries_T_177; // @[TLB.scala:170:77]
assign pma_checker__entries_T_178 = pma_checker__entries_WIRE_15[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_hr = pma_checker__entries_T_178; // @[TLB.scala:170:77]
assign pma_checker__entries_T_179 = pma_checker__entries_WIRE_15[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_hx = pma_checker__entries_T_179; // @[TLB.scala:170:77]
assign pma_checker__entries_T_180 = pma_checker__entries_WIRE_15[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_hw = pma_checker__entries_T_180; // @[TLB.scala:170:77]
assign pma_checker__entries_T_181 = pma_checker__entries_WIRE_15[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_sr = pma_checker__entries_T_181; // @[TLB.scala:170:77]
assign pma_checker__entries_T_182 = pma_checker__entries_WIRE_15[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_sx = pma_checker__entries_T_182; // @[TLB.scala:170:77]
assign pma_checker__entries_T_183 = pma_checker__entries_WIRE_15[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_sw = pma_checker__entries_T_183; // @[TLB.scala:170:77]
assign pma_checker__entries_T_184 = pma_checker__entries_WIRE_15[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_gf = pma_checker__entries_T_184; // @[TLB.scala:170:77]
assign pma_checker__entries_T_185 = pma_checker__entries_WIRE_15[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_pf = pma_checker__entries_T_185; // @[TLB.scala:170:77]
assign pma_checker__entries_T_186 = pma_checker__entries_WIRE_15[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_ae_stage2 = pma_checker__entries_T_186; // @[TLB.scala:170:77]
assign pma_checker__entries_T_187 = pma_checker__entries_WIRE_15[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_ae_final = pma_checker__entries_T_187; // @[TLB.scala:170:77]
assign pma_checker__entries_T_188 = pma_checker__entries_WIRE_15[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_ae_ptw = pma_checker__entries_T_188; // @[TLB.scala:170:77]
assign pma_checker__entries_T_189 = pma_checker__entries_WIRE_15[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_g = pma_checker__entries_T_189; // @[TLB.scala:170:77]
assign pma_checker__entries_T_190 = pma_checker__entries_WIRE_15[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_u = pma_checker__entries_T_190; // @[TLB.scala:170:77]
assign pma_checker__entries_T_191 = pma_checker__entries_WIRE_15[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_14_ppn = pma_checker__entries_T_191; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_214; // @[TLB.scala:170:77]
wire pma_checker__entries_T_213; // @[TLB.scala:170:77]
wire pma_checker__entries_T_212; // @[TLB.scala:170:77]
wire pma_checker__entries_T_211; // @[TLB.scala:170:77]
wire pma_checker__entries_T_210; // @[TLB.scala:170:77]
wire pma_checker__entries_T_209; // @[TLB.scala:170:77]
wire pma_checker__entries_T_208; // @[TLB.scala:170:77]
wire pma_checker__entries_T_207; // @[TLB.scala:170:77]
wire pma_checker__entries_T_206; // @[TLB.scala:170:77]
wire pma_checker__entries_T_205; // @[TLB.scala:170:77]
wire pma_checker__entries_T_204; // @[TLB.scala:170:77]
wire pma_checker__entries_T_203; // @[TLB.scala:170:77]
wire pma_checker__entries_T_202; // @[TLB.scala:170:77]
wire pma_checker__entries_T_201; // @[TLB.scala:170:77]
wire pma_checker__entries_T_200; // @[TLB.scala:170:77]
wire pma_checker__entries_T_199; // @[TLB.scala:170:77]
wire pma_checker__entries_T_198; // @[TLB.scala:170:77]
wire pma_checker__entries_T_197; // @[TLB.scala:170:77]
wire pma_checker__entries_T_196; // @[TLB.scala:170:77]
wire pma_checker__entries_T_195; // @[TLB.scala:170:77]
wire pma_checker__entries_T_194; // @[TLB.scala:170:77]
wire pma_checker__entries_T_193; // @[TLB.scala:170:77]
wire pma_checker__entries_T_192; // @[TLB.scala:170:77]
assign pma_checker__entries_T_192 = pma_checker__entries_WIRE_17[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_fragmented_superpage = pma_checker__entries_T_192; // @[TLB.scala:170:77]
assign pma_checker__entries_T_193 = pma_checker__entries_WIRE_17[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_c = pma_checker__entries_T_193; // @[TLB.scala:170:77]
assign pma_checker__entries_T_194 = pma_checker__entries_WIRE_17[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_eff = pma_checker__entries_T_194; // @[TLB.scala:170:77]
assign pma_checker__entries_T_195 = pma_checker__entries_WIRE_17[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_paa = pma_checker__entries_T_195; // @[TLB.scala:170:77]
assign pma_checker__entries_T_196 = pma_checker__entries_WIRE_17[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_pal = pma_checker__entries_T_196; // @[TLB.scala:170:77]
assign pma_checker__entries_T_197 = pma_checker__entries_WIRE_17[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_ppp = pma_checker__entries_T_197; // @[TLB.scala:170:77]
assign pma_checker__entries_T_198 = pma_checker__entries_WIRE_17[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_pr = pma_checker__entries_T_198; // @[TLB.scala:170:77]
assign pma_checker__entries_T_199 = pma_checker__entries_WIRE_17[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_px = pma_checker__entries_T_199; // @[TLB.scala:170:77]
assign pma_checker__entries_T_200 = pma_checker__entries_WIRE_17[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_pw = pma_checker__entries_T_200; // @[TLB.scala:170:77]
assign pma_checker__entries_T_201 = pma_checker__entries_WIRE_17[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_hr = pma_checker__entries_T_201; // @[TLB.scala:170:77]
assign pma_checker__entries_T_202 = pma_checker__entries_WIRE_17[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_hx = pma_checker__entries_T_202; // @[TLB.scala:170:77]
assign pma_checker__entries_T_203 = pma_checker__entries_WIRE_17[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_hw = pma_checker__entries_T_203; // @[TLB.scala:170:77]
assign pma_checker__entries_T_204 = pma_checker__entries_WIRE_17[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_sr = pma_checker__entries_T_204; // @[TLB.scala:170:77]
assign pma_checker__entries_T_205 = pma_checker__entries_WIRE_17[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_sx = pma_checker__entries_T_205; // @[TLB.scala:170:77]
assign pma_checker__entries_T_206 = pma_checker__entries_WIRE_17[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_sw = pma_checker__entries_T_206; // @[TLB.scala:170:77]
assign pma_checker__entries_T_207 = pma_checker__entries_WIRE_17[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_gf = pma_checker__entries_T_207; // @[TLB.scala:170:77]
assign pma_checker__entries_T_208 = pma_checker__entries_WIRE_17[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_pf = pma_checker__entries_T_208; // @[TLB.scala:170:77]
assign pma_checker__entries_T_209 = pma_checker__entries_WIRE_17[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_ae_stage2 = pma_checker__entries_T_209; // @[TLB.scala:170:77]
assign pma_checker__entries_T_210 = pma_checker__entries_WIRE_17[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_ae_final = pma_checker__entries_T_210; // @[TLB.scala:170:77]
assign pma_checker__entries_T_211 = pma_checker__entries_WIRE_17[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_ae_ptw = pma_checker__entries_T_211; // @[TLB.scala:170:77]
assign pma_checker__entries_T_212 = pma_checker__entries_WIRE_17[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_g = pma_checker__entries_T_212; // @[TLB.scala:170:77]
assign pma_checker__entries_T_213 = pma_checker__entries_WIRE_17[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_u = pma_checker__entries_T_213; // @[TLB.scala:170:77]
assign pma_checker__entries_T_214 = pma_checker__entries_WIRE_17[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_16_ppn = pma_checker__entries_T_214; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_237; // @[TLB.scala:170:77]
wire pma_checker__entries_T_236; // @[TLB.scala:170:77]
wire pma_checker__entries_T_235; // @[TLB.scala:170:77]
wire pma_checker__entries_T_234; // @[TLB.scala:170:77]
wire pma_checker__entries_T_233; // @[TLB.scala:170:77]
wire pma_checker__entries_T_232; // @[TLB.scala:170:77]
wire pma_checker__entries_T_231; // @[TLB.scala:170:77]
wire pma_checker__entries_T_230; // @[TLB.scala:170:77]
wire pma_checker__entries_T_229; // @[TLB.scala:170:77]
wire pma_checker__entries_T_228; // @[TLB.scala:170:77]
wire pma_checker__entries_T_227; // @[TLB.scala:170:77]
wire pma_checker__entries_T_226; // @[TLB.scala:170:77]
wire pma_checker__entries_T_225; // @[TLB.scala:170:77]
wire pma_checker__entries_T_224; // @[TLB.scala:170:77]
wire pma_checker__entries_T_223; // @[TLB.scala:170:77]
wire pma_checker__entries_T_222; // @[TLB.scala:170:77]
wire pma_checker__entries_T_221; // @[TLB.scala:170:77]
wire pma_checker__entries_T_220; // @[TLB.scala:170:77]
wire pma_checker__entries_T_219; // @[TLB.scala:170:77]
wire pma_checker__entries_T_218; // @[TLB.scala:170:77]
wire pma_checker__entries_T_217; // @[TLB.scala:170:77]
wire pma_checker__entries_T_216; // @[TLB.scala:170:77]
wire pma_checker__entries_T_215; // @[TLB.scala:170:77]
assign pma_checker__entries_T_215 = pma_checker__entries_WIRE_19[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_fragmented_superpage = pma_checker__entries_T_215; // @[TLB.scala:170:77]
assign pma_checker__entries_T_216 = pma_checker__entries_WIRE_19[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_c = pma_checker__entries_T_216; // @[TLB.scala:170:77]
assign pma_checker__entries_T_217 = pma_checker__entries_WIRE_19[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_eff = pma_checker__entries_T_217; // @[TLB.scala:170:77]
assign pma_checker__entries_T_218 = pma_checker__entries_WIRE_19[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_paa = pma_checker__entries_T_218; // @[TLB.scala:170:77]
assign pma_checker__entries_T_219 = pma_checker__entries_WIRE_19[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_pal = pma_checker__entries_T_219; // @[TLB.scala:170:77]
assign pma_checker__entries_T_220 = pma_checker__entries_WIRE_19[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_ppp = pma_checker__entries_T_220; // @[TLB.scala:170:77]
assign pma_checker__entries_T_221 = pma_checker__entries_WIRE_19[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_pr = pma_checker__entries_T_221; // @[TLB.scala:170:77]
assign pma_checker__entries_T_222 = pma_checker__entries_WIRE_19[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_px = pma_checker__entries_T_222; // @[TLB.scala:170:77]
assign pma_checker__entries_T_223 = pma_checker__entries_WIRE_19[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_pw = pma_checker__entries_T_223; // @[TLB.scala:170:77]
assign pma_checker__entries_T_224 = pma_checker__entries_WIRE_19[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_hr = pma_checker__entries_T_224; // @[TLB.scala:170:77]
assign pma_checker__entries_T_225 = pma_checker__entries_WIRE_19[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_hx = pma_checker__entries_T_225; // @[TLB.scala:170:77]
assign pma_checker__entries_T_226 = pma_checker__entries_WIRE_19[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_hw = pma_checker__entries_T_226; // @[TLB.scala:170:77]
assign pma_checker__entries_T_227 = pma_checker__entries_WIRE_19[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_sr = pma_checker__entries_T_227; // @[TLB.scala:170:77]
assign pma_checker__entries_T_228 = pma_checker__entries_WIRE_19[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_sx = pma_checker__entries_T_228; // @[TLB.scala:170:77]
assign pma_checker__entries_T_229 = pma_checker__entries_WIRE_19[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_sw = pma_checker__entries_T_229; // @[TLB.scala:170:77]
assign pma_checker__entries_T_230 = pma_checker__entries_WIRE_19[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_gf = pma_checker__entries_T_230; // @[TLB.scala:170:77]
assign pma_checker__entries_T_231 = pma_checker__entries_WIRE_19[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_pf = pma_checker__entries_T_231; // @[TLB.scala:170:77]
assign pma_checker__entries_T_232 = pma_checker__entries_WIRE_19[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_ae_stage2 = pma_checker__entries_T_232; // @[TLB.scala:170:77]
assign pma_checker__entries_T_233 = pma_checker__entries_WIRE_19[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_ae_final = pma_checker__entries_T_233; // @[TLB.scala:170:77]
assign pma_checker__entries_T_234 = pma_checker__entries_WIRE_19[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_ae_ptw = pma_checker__entries_T_234; // @[TLB.scala:170:77]
assign pma_checker__entries_T_235 = pma_checker__entries_WIRE_19[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_g = pma_checker__entries_T_235; // @[TLB.scala:170:77]
assign pma_checker__entries_T_236 = pma_checker__entries_WIRE_19[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_u = pma_checker__entries_T_236; // @[TLB.scala:170:77]
assign pma_checker__entries_T_237 = pma_checker__entries_WIRE_19[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_18_ppn = pma_checker__entries_T_237; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_260; // @[TLB.scala:170:77]
wire pma_checker__entries_T_259; // @[TLB.scala:170:77]
wire pma_checker__entries_T_258; // @[TLB.scala:170:77]
wire pma_checker__entries_T_257; // @[TLB.scala:170:77]
wire pma_checker__entries_T_256; // @[TLB.scala:170:77]
wire pma_checker__entries_T_255; // @[TLB.scala:170:77]
wire pma_checker__entries_T_254; // @[TLB.scala:170:77]
wire pma_checker__entries_T_253; // @[TLB.scala:170:77]
wire pma_checker__entries_T_252; // @[TLB.scala:170:77]
wire pma_checker__entries_T_251; // @[TLB.scala:170:77]
wire pma_checker__entries_T_250; // @[TLB.scala:170:77]
wire pma_checker__entries_T_249; // @[TLB.scala:170:77]
wire pma_checker__entries_T_248; // @[TLB.scala:170:77]
wire pma_checker__entries_T_247; // @[TLB.scala:170:77]
wire pma_checker__entries_T_246; // @[TLB.scala:170:77]
wire pma_checker__entries_T_245; // @[TLB.scala:170:77]
wire pma_checker__entries_T_244; // @[TLB.scala:170:77]
wire pma_checker__entries_T_243; // @[TLB.scala:170:77]
wire pma_checker__entries_T_242; // @[TLB.scala:170:77]
wire pma_checker__entries_T_241; // @[TLB.scala:170:77]
wire pma_checker__entries_T_240; // @[TLB.scala:170:77]
wire pma_checker__entries_T_239; // @[TLB.scala:170:77]
wire pma_checker__entries_T_238; // @[TLB.scala:170:77]
assign pma_checker__entries_T_238 = pma_checker__entries_WIRE_21[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_fragmented_superpage = pma_checker__entries_T_238; // @[TLB.scala:170:77]
assign pma_checker__entries_T_239 = pma_checker__entries_WIRE_21[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_c = pma_checker__entries_T_239; // @[TLB.scala:170:77]
assign pma_checker__entries_T_240 = pma_checker__entries_WIRE_21[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_eff = pma_checker__entries_T_240; // @[TLB.scala:170:77]
assign pma_checker__entries_T_241 = pma_checker__entries_WIRE_21[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_paa = pma_checker__entries_T_241; // @[TLB.scala:170:77]
assign pma_checker__entries_T_242 = pma_checker__entries_WIRE_21[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_pal = pma_checker__entries_T_242; // @[TLB.scala:170:77]
assign pma_checker__entries_T_243 = pma_checker__entries_WIRE_21[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_ppp = pma_checker__entries_T_243; // @[TLB.scala:170:77]
assign pma_checker__entries_T_244 = pma_checker__entries_WIRE_21[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_pr = pma_checker__entries_T_244; // @[TLB.scala:170:77]
assign pma_checker__entries_T_245 = pma_checker__entries_WIRE_21[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_px = pma_checker__entries_T_245; // @[TLB.scala:170:77]
assign pma_checker__entries_T_246 = pma_checker__entries_WIRE_21[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_pw = pma_checker__entries_T_246; // @[TLB.scala:170:77]
assign pma_checker__entries_T_247 = pma_checker__entries_WIRE_21[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_hr = pma_checker__entries_T_247; // @[TLB.scala:170:77]
assign pma_checker__entries_T_248 = pma_checker__entries_WIRE_21[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_hx = pma_checker__entries_T_248; // @[TLB.scala:170:77]
assign pma_checker__entries_T_249 = pma_checker__entries_WIRE_21[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_hw = pma_checker__entries_T_249; // @[TLB.scala:170:77]
assign pma_checker__entries_T_250 = pma_checker__entries_WIRE_21[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_sr = pma_checker__entries_T_250; // @[TLB.scala:170:77]
assign pma_checker__entries_T_251 = pma_checker__entries_WIRE_21[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_sx = pma_checker__entries_T_251; // @[TLB.scala:170:77]
assign pma_checker__entries_T_252 = pma_checker__entries_WIRE_21[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_sw = pma_checker__entries_T_252; // @[TLB.scala:170:77]
assign pma_checker__entries_T_253 = pma_checker__entries_WIRE_21[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_gf = pma_checker__entries_T_253; // @[TLB.scala:170:77]
assign pma_checker__entries_T_254 = pma_checker__entries_WIRE_21[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_pf = pma_checker__entries_T_254; // @[TLB.scala:170:77]
assign pma_checker__entries_T_255 = pma_checker__entries_WIRE_21[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_ae_stage2 = pma_checker__entries_T_255; // @[TLB.scala:170:77]
assign pma_checker__entries_T_256 = pma_checker__entries_WIRE_21[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_ae_final = pma_checker__entries_T_256; // @[TLB.scala:170:77]
assign pma_checker__entries_T_257 = pma_checker__entries_WIRE_21[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_ae_ptw = pma_checker__entries_T_257; // @[TLB.scala:170:77]
assign pma_checker__entries_T_258 = pma_checker__entries_WIRE_21[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_g = pma_checker__entries_T_258; // @[TLB.scala:170:77]
assign pma_checker__entries_T_259 = pma_checker__entries_WIRE_21[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_u = pma_checker__entries_T_259; // @[TLB.scala:170:77]
assign pma_checker__entries_T_260 = pma_checker__entries_WIRE_21[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_20_ppn = pma_checker__entries_T_260; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_283; // @[TLB.scala:170:77]
wire pma_checker__entries_T_282; // @[TLB.scala:170:77]
wire pma_checker__entries_T_281; // @[TLB.scala:170:77]
wire pma_checker__entries_T_280; // @[TLB.scala:170:77]
wire pma_checker__entries_T_279; // @[TLB.scala:170:77]
wire pma_checker__entries_T_278; // @[TLB.scala:170:77]
wire pma_checker__entries_T_277; // @[TLB.scala:170:77]
wire pma_checker__entries_T_276; // @[TLB.scala:170:77]
wire pma_checker__entries_T_275; // @[TLB.scala:170:77]
wire pma_checker__entries_T_274; // @[TLB.scala:170:77]
wire pma_checker__entries_T_273; // @[TLB.scala:170:77]
wire pma_checker__entries_T_272; // @[TLB.scala:170:77]
wire pma_checker__entries_T_271; // @[TLB.scala:170:77]
wire pma_checker__entries_T_270; // @[TLB.scala:170:77]
wire pma_checker__entries_T_269; // @[TLB.scala:170:77]
wire pma_checker__entries_T_268; // @[TLB.scala:170:77]
wire pma_checker__entries_T_267; // @[TLB.scala:170:77]
wire pma_checker__entries_T_266; // @[TLB.scala:170:77]
wire pma_checker__entries_T_265; // @[TLB.scala:170:77]
wire pma_checker__entries_T_264; // @[TLB.scala:170:77]
wire pma_checker__entries_T_263; // @[TLB.scala:170:77]
wire pma_checker__entries_T_262; // @[TLB.scala:170:77]
wire pma_checker__entries_T_261; // @[TLB.scala:170:77]
assign pma_checker__entries_T_261 = pma_checker__entries_WIRE_23[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_fragmented_superpage = pma_checker__entries_T_261; // @[TLB.scala:170:77]
assign pma_checker__entries_T_262 = pma_checker__entries_WIRE_23[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_c = pma_checker__entries_T_262; // @[TLB.scala:170:77]
assign pma_checker__entries_T_263 = pma_checker__entries_WIRE_23[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_eff = pma_checker__entries_T_263; // @[TLB.scala:170:77]
assign pma_checker__entries_T_264 = pma_checker__entries_WIRE_23[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_paa = pma_checker__entries_T_264; // @[TLB.scala:170:77]
assign pma_checker__entries_T_265 = pma_checker__entries_WIRE_23[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_pal = pma_checker__entries_T_265; // @[TLB.scala:170:77]
assign pma_checker__entries_T_266 = pma_checker__entries_WIRE_23[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_ppp = pma_checker__entries_T_266; // @[TLB.scala:170:77]
assign pma_checker__entries_T_267 = pma_checker__entries_WIRE_23[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_pr = pma_checker__entries_T_267; // @[TLB.scala:170:77]
assign pma_checker__entries_T_268 = pma_checker__entries_WIRE_23[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_px = pma_checker__entries_T_268; // @[TLB.scala:170:77]
assign pma_checker__entries_T_269 = pma_checker__entries_WIRE_23[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_pw = pma_checker__entries_T_269; // @[TLB.scala:170:77]
assign pma_checker__entries_T_270 = pma_checker__entries_WIRE_23[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_hr = pma_checker__entries_T_270; // @[TLB.scala:170:77]
assign pma_checker__entries_T_271 = pma_checker__entries_WIRE_23[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_hx = pma_checker__entries_T_271; // @[TLB.scala:170:77]
assign pma_checker__entries_T_272 = pma_checker__entries_WIRE_23[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_hw = pma_checker__entries_T_272; // @[TLB.scala:170:77]
assign pma_checker__entries_T_273 = pma_checker__entries_WIRE_23[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_sr = pma_checker__entries_T_273; // @[TLB.scala:170:77]
assign pma_checker__entries_T_274 = pma_checker__entries_WIRE_23[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_sx = pma_checker__entries_T_274; // @[TLB.scala:170:77]
assign pma_checker__entries_T_275 = pma_checker__entries_WIRE_23[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_sw = pma_checker__entries_T_275; // @[TLB.scala:170:77]
assign pma_checker__entries_T_276 = pma_checker__entries_WIRE_23[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_gf = pma_checker__entries_T_276; // @[TLB.scala:170:77]
assign pma_checker__entries_T_277 = pma_checker__entries_WIRE_23[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_pf = pma_checker__entries_T_277; // @[TLB.scala:170:77]
assign pma_checker__entries_T_278 = pma_checker__entries_WIRE_23[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_ae_stage2 = pma_checker__entries_T_278; // @[TLB.scala:170:77]
assign pma_checker__entries_T_279 = pma_checker__entries_WIRE_23[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_ae_final = pma_checker__entries_T_279; // @[TLB.scala:170:77]
assign pma_checker__entries_T_280 = pma_checker__entries_WIRE_23[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_ae_ptw = pma_checker__entries_T_280; // @[TLB.scala:170:77]
assign pma_checker__entries_T_281 = pma_checker__entries_WIRE_23[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_g = pma_checker__entries_T_281; // @[TLB.scala:170:77]
assign pma_checker__entries_T_282 = pma_checker__entries_WIRE_23[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_u = pma_checker__entries_T_282; // @[TLB.scala:170:77]
assign pma_checker__entries_T_283 = pma_checker__entries_WIRE_23[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_22_ppn = pma_checker__entries_T_283; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_306; // @[TLB.scala:170:77]
wire pma_checker__entries_T_305; // @[TLB.scala:170:77]
wire pma_checker__entries_T_304; // @[TLB.scala:170:77]
wire pma_checker__entries_T_303; // @[TLB.scala:170:77]
wire pma_checker__entries_T_302; // @[TLB.scala:170:77]
wire pma_checker__entries_T_301; // @[TLB.scala:170:77]
wire pma_checker__entries_T_300; // @[TLB.scala:170:77]
wire pma_checker__entries_T_299; // @[TLB.scala:170:77]
wire pma_checker__entries_T_298; // @[TLB.scala:170:77]
wire pma_checker__entries_T_297; // @[TLB.scala:170:77]
wire pma_checker__entries_T_296; // @[TLB.scala:170:77]
wire pma_checker__entries_T_295; // @[TLB.scala:170:77]
wire pma_checker__entries_T_294; // @[TLB.scala:170:77]
wire pma_checker__entries_T_293; // @[TLB.scala:170:77]
wire pma_checker__entries_T_292; // @[TLB.scala:170:77]
wire pma_checker__entries_T_291; // @[TLB.scala:170:77]
wire pma_checker__entries_T_290; // @[TLB.scala:170:77]
wire pma_checker__entries_T_289; // @[TLB.scala:170:77]
wire pma_checker__entries_T_288; // @[TLB.scala:170:77]
wire pma_checker__entries_T_287; // @[TLB.scala:170:77]
wire pma_checker__entries_T_286; // @[TLB.scala:170:77]
wire pma_checker__entries_T_285; // @[TLB.scala:170:77]
wire pma_checker__entries_T_284; // @[TLB.scala:170:77]
assign pma_checker__entries_T_284 = pma_checker__entries_WIRE_25[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_fragmented_superpage = pma_checker__entries_T_284; // @[TLB.scala:170:77]
assign pma_checker__entries_T_285 = pma_checker__entries_WIRE_25[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_c = pma_checker__entries_T_285; // @[TLB.scala:170:77]
assign pma_checker__entries_T_286 = pma_checker__entries_WIRE_25[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_eff = pma_checker__entries_T_286; // @[TLB.scala:170:77]
assign pma_checker__entries_T_287 = pma_checker__entries_WIRE_25[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_paa = pma_checker__entries_T_287; // @[TLB.scala:170:77]
assign pma_checker__entries_T_288 = pma_checker__entries_WIRE_25[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_pal = pma_checker__entries_T_288; // @[TLB.scala:170:77]
assign pma_checker__entries_T_289 = pma_checker__entries_WIRE_25[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_ppp = pma_checker__entries_T_289; // @[TLB.scala:170:77]
assign pma_checker__entries_T_290 = pma_checker__entries_WIRE_25[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_pr = pma_checker__entries_T_290; // @[TLB.scala:170:77]
assign pma_checker__entries_T_291 = pma_checker__entries_WIRE_25[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_px = pma_checker__entries_T_291; // @[TLB.scala:170:77]
assign pma_checker__entries_T_292 = pma_checker__entries_WIRE_25[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_pw = pma_checker__entries_T_292; // @[TLB.scala:170:77]
assign pma_checker__entries_T_293 = pma_checker__entries_WIRE_25[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_hr = pma_checker__entries_T_293; // @[TLB.scala:170:77]
assign pma_checker__entries_T_294 = pma_checker__entries_WIRE_25[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_hx = pma_checker__entries_T_294; // @[TLB.scala:170:77]
assign pma_checker__entries_T_295 = pma_checker__entries_WIRE_25[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_hw = pma_checker__entries_T_295; // @[TLB.scala:170:77]
assign pma_checker__entries_T_296 = pma_checker__entries_WIRE_25[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_sr = pma_checker__entries_T_296; // @[TLB.scala:170:77]
assign pma_checker__entries_T_297 = pma_checker__entries_WIRE_25[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_sx = pma_checker__entries_T_297; // @[TLB.scala:170:77]
assign pma_checker__entries_T_298 = pma_checker__entries_WIRE_25[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_sw = pma_checker__entries_T_298; // @[TLB.scala:170:77]
assign pma_checker__entries_T_299 = pma_checker__entries_WIRE_25[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_gf = pma_checker__entries_T_299; // @[TLB.scala:170:77]
assign pma_checker__entries_T_300 = pma_checker__entries_WIRE_25[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_pf = pma_checker__entries_T_300; // @[TLB.scala:170:77]
assign pma_checker__entries_T_301 = pma_checker__entries_WIRE_25[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_ae_stage2 = pma_checker__entries_T_301; // @[TLB.scala:170:77]
assign pma_checker__entries_T_302 = pma_checker__entries_WIRE_25[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_ae_final = pma_checker__entries_T_302; // @[TLB.scala:170:77]
assign pma_checker__entries_T_303 = pma_checker__entries_WIRE_25[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_ae_ptw = pma_checker__entries_T_303; // @[TLB.scala:170:77]
assign pma_checker__entries_T_304 = pma_checker__entries_WIRE_25[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_g = pma_checker__entries_T_304; // @[TLB.scala:170:77]
assign pma_checker__entries_T_305 = pma_checker__entries_WIRE_25[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_u = pma_checker__entries_T_305; // @[TLB.scala:170:77]
assign pma_checker__entries_T_306 = pma_checker__entries_WIRE_25[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_24_ppn = pma_checker__entries_T_306; // @[TLB.scala:170:77]
wire [1:0] pma_checker_ppn_res = _pma_checker_entries_barrier_8_io_y_ppn[19:18]; // @[package.scala:267:25]
wire pma_checker_ppn_ignore = pma_checker__ppn_ignore_T; // @[TLB.scala:197:{28,34}]
wire [26:0] pma_checker__ppn_T_1 = pma_checker_ppn_ignore ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] pma_checker__ppn_T_2 = {pma_checker__ppn_T_1[26:20], pma_checker__ppn_T_1[19:0] | _pma_checker_entries_barrier_8_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] pma_checker__ppn_T_3 = pma_checker__ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] pma_checker__ppn_T_4 = {pma_checker_ppn_res, pma_checker__ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}]
wire [26:0] pma_checker__ppn_T_6 = {pma_checker__ppn_T_5[26:20], pma_checker__ppn_T_5[19:0] | _pma_checker_entries_barrier_8_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] pma_checker__ppn_T_7 = pma_checker__ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] pma_checker__ppn_T_8 = {pma_checker__ppn_T_4, pma_checker__ppn_T_7}; // @[TLB.scala:198:{18,58}]
wire [1:0] pma_checker_ppn_res_1 = _pma_checker_entries_barrier_9_io_y_ppn[19:18]; // @[package.scala:267:25]
wire pma_checker_ppn_ignore_2 = pma_checker__ppn_ignore_T_2; // @[TLB.scala:197:{28,34}]
wire [26:0] pma_checker__ppn_T_9 = pma_checker_ppn_ignore_2 ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] pma_checker__ppn_T_10 = {pma_checker__ppn_T_9[26:20], pma_checker__ppn_T_9[19:0] | _pma_checker_entries_barrier_9_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] pma_checker__ppn_T_11 = pma_checker__ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] pma_checker__ppn_T_12 = {pma_checker_ppn_res_1, pma_checker__ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}]
wire [26:0] pma_checker__ppn_T_14 = {pma_checker__ppn_T_13[26:20], pma_checker__ppn_T_13[19:0] | _pma_checker_entries_barrier_9_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] pma_checker__ppn_T_15 = pma_checker__ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] pma_checker__ppn_T_16 = {pma_checker__ppn_T_12, pma_checker__ppn_T_15}; // @[TLB.scala:198:{18,58}]
wire [1:0] pma_checker_ppn_res_2 = _pma_checker_entries_barrier_10_io_y_ppn[19:18]; // @[package.scala:267:25]
wire pma_checker_ppn_ignore_4 = pma_checker__ppn_ignore_T_4; // @[TLB.scala:197:{28,34}]
wire [26:0] pma_checker__ppn_T_17 = pma_checker_ppn_ignore_4 ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] pma_checker__ppn_T_18 = {pma_checker__ppn_T_17[26:20], pma_checker__ppn_T_17[19:0] | _pma_checker_entries_barrier_10_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] pma_checker__ppn_T_19 = pma_checker__ppn_T_18[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] pma_checker__ppn_T_20 = {pma_checker_ppn_res_2, pma_checker__ppn_T_19}; // @[TLB.scala:195:26, :198:{18,58}]
wire [26:0] pma_checker__ppn_T_22 = {pma_checker__ppn_T_21[26:20], pma_checker__ppn_T_21[19:0] | _pma_checker_entries_barrier_10_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] pma_checker__ppn_T_23 = pma_checker__ppn_T_22[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] pma_checker__ppn_T_24 = {pma_checker__ppn_T_20, pma_checker__ppn_T_23}; // @[TLB.scala:198:{18,58}]
wire [1:0] pma_checker_ppn_res_3 = _pma_checker_entries_barrier_11_io_y_ppn[19:18]; // @[package.scala:267:25]
wire pma_checker_ppn_ignore_6 = pma_checker__ppn_ignore_T_6; // @[TLB.scala:197:{28,34}]
wire [26:0] pma_checker__ppn_T_25 = pma_checker_ppn_ignore_6 ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] pma_checker__ppn_T_26 = {pma_checker__ppn_T_25[26:20], pma_checker__ppn_T_25[19:0] | _pma_checker_entries_barrier_11_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] pma_checker__ppn_T_27 = pma_checker__ppn_T_26[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] pma_checker__ppn_T_28 = {pma_checker_ppn_res_3, pma_checker__ppn_T_27}; // @[TLB.scala:195:26, :198:{18,58}]
wire [26:0] pma_checker__ppn_T_30 = {pma_checker__ppn_T_29[26:20], pma_checker__ppn_T_29[19:0] | _pma_checker_entries_barrier_11_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] pma_checker__ppn_T_31 = pma_checker__ppn_T_30[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] pma_checker__ppn_T_32 = {pma_checker__ppn_T_28, pma_checker__ppn_T_31}; // @[TLB.scala:198:{18,58}]
wire [1:0] pma_checker_ppn_res_4 = _pma_checker_entries_barrier_12_io_y_ppn[19:18]; // @[package.scala:267:25]
wire [26:0] pma_checker__ppn_T_34 = {pma_checker__ppn_T_33[26:20], pma_checker__ppn_T_33[19:0] | _pma_checker_entries_barrier_12_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] pma_checker__ppn_T_35 = pma_checker__ppn_T_34[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] pma_checker__ppn_T_36 = {pma_checker_ppn_res_4, pma_checker__ppn_T_35}; // @[TLB.scala:195:26, :198:{18,58}]
wire [26:0] pma_checker__ppn_T_38 = {pma_checker__ppn_T_37[26:20], pma_checker__ppn_T_37[19:0] | _pma_checker_entries_barrier_12_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] pma_checker__ppn_T_39 = pma_checker__ppn_T_38[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] pma_checker__ppn_T_40 = {pma_checker__ppn_T_36, pma_checker__ppn_T_39}; // @[TLB.scala:198:{18,58}]
wire [19:0] pma_checker__ppn_T_41 = pma_checker_vpn[19:0]; // @[TLB.scala:335:30, :502:125]
wire [19:0] pma_checker__ppn_T_55 = pma_checker__ppn_T_41; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_68 = pma_checker__ppn_T_55; // @[Mux.scala:30:73]
wire [19:0] pma_checker_ppn = pma_checker__ppn_T_68; // @[Mux.scala:30:73]
wire [1:0] pma_checker_ptw_ae_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_ptw, _pma_checker_entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_ae_array_lo_lo = {pma_checker_ptw_ae_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_ae_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_ptw, _pma_checker_entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_ae_array_lo_hi = {pma_checker_ptw_ae_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_ptw_ae_array_lo = {pma_checker_ptw_ae_array_lo_hi, pma_checker_ptw_ae_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_ptw_ae_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_ptw, _pma_checker_entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_ae_array_hi_lo = {pma_checker_ptw_ae_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_ae_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_ptw, _pma_checker_entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_ae_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_ptw, _pma_checker_entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_ptw_ae_array_hi_hi = {pma_checker_ptw_ae_array_hi_hi_hi, pma_checker_ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_ptw_ae_array_hi = {pma_checker_ptw_ae_array_hi_hi, pma_checker_ptw_ae_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__ptw_ae_array_T = {pma_checker_ptw_ae_array_hi, pma_checker_ptw_ae_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_ptw_ae_array = {1'h0, pma_checker__ptw_ae_array_T}; // @[package.scala:45:27]
wire [1:0] pma_checker_final_ae_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_final, _pma_checker_entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_final_ae_array_lo_lo = {pma_checker_final_ae_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_final_ae_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_final, _pma_checker_entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_final_ae_array_lo_hi = {pma_checker_final_ae_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_final_ae_array_lo = {pma_checker_final_ae_array_lo_hi, pma_checker_final_ae_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_final_ae_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_final, _pma_checker_entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_final_ae_array_hi_lo = {pma_checker_final_ae_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_final_ae_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_final, _pma_checker_entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_final_ae_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_final, _pma_checker_entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_final_ae_array_hi_hi = {pma_checker_final_ae_array_hi_hi_hi, pma_checker_final_ae_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_final_ae_array_hi = {pma_checker_final_ae_array_hi_hi, pma_checker_final_ae_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__final_ae_array_T = {pma_checker_final_ae_array_hi, pma_checker_final_ae_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_final_ae_array = {1'h0, pma_checker__final_ae_array_T}; // @[package.scala:45:27]
wire [1:0] pma_checker_ptw_pf_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pf, _pma_checker_entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_pf_array_lo_lo = {pma_checker_ptw_pf_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_pf_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pf, _pma_checker_entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_pf_array_lo_hi = {pma_checker_ptw_pf_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_ptw_pf_array_lo = {pma_checker_ptw_pf_array_lo_hi, pma_checker_ptw_pf_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_ptw_pf_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pf, _pma_checker_entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_pf_array_hi_lo = {pma_checker_ptw_pf_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_pf_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_pf, _pma_checker_entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_pf_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_pf, _pma_checker_entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_ptw_pf_array_hi_hi = {pma_checker_ptw_pf_array_hi_hi_hi, pma_checker_ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_ptw_pf_array_hi = {pma_checker_ptw_pf_array_hi_hi, pma_checker_ptw_pf_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__ptw_pf_array_T = {pma_checker_ptw_pf_array_hi, pma_checker_ptw_pf_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_ptw_pf_array = {1'h0, pma_checker__ptw_pf_array_T}; // @[package.scala:45:27]
wire [1:0] pma_checker_ptw_gf_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_gf, _pma_checker_entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_gf_array_lo_lo = {pma_checker_ptw_gf_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_gf_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_gf, _pma_checker_entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_gf_array_lo_hi = {pma_checker_ptw_gf_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_ptw_gf_array_lo = {pma_checker_ptw_gf_array_lo_hi, pma_checker_ptw_gf_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_ptw_gf_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_gf, _pma_checker_entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_gf_array_hi_lo = {pma_checker_ptw_gf_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_gf_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_gf, _pma_checker_entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_gf_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_gf, _pma_checker_entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_ptw_gf_array_hi_hi = {pma_checker_ptw_gf_array_hi_hi_hi, pma_checker_ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_ptw_gf_array_hi = {pma_checker_ptw_gf_array_hi_hi, pma_checker_ptw_gf_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__ptw_gf_array_T = {pma_checker_ptw_gf_array_hi, pma_checker_ptw_gf_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_ptw_gf_array = {1'h0, pma_checker__ptw_gf_array_T}; // @[package.scala:45:27]
wire [13:0] pma_checker__gf_ld_array_T_3 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :600:82]
wire [13:0] pma_checker__gf_st_array_T_2 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :601:63]
wire [13:0] pma_checker__gf_inst_array_T_1 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :602:46]
wire pma_checker__priv_rw_ok_T = ~pma_checker_priv_s; // @[TLB.scala:370:20, :513:24]
wire pma_checker__priv_rw_ok_T_1 = pma_checker__priv_rw_ok_T; // @[TLB.scala:513:{24,32}]
wire [1:0] _GEN_8 = {_pma_checker_entries_barrier_2_io_y_u, _pma_checker_entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_priv_rw_ok_lo_lo_hi; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_lo_lo_hi = _GEN_8; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_lo_lo_hi_1 = _GEN_8; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_lo_lo_hi; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_lo_lo_hi = _GEN_8; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_lo_lo_hi_1 = _GEN_8; // @[package.scala:45:27]
wire [2:0] pma_checker_priv_rw_ok_lo_lo = {pma_checker_priv_rw_ok_lo_lo_hi, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_9 = {_pma_checker_entries_barrier_5_io_y_u, _pma_checker_entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_priv_rw_ok_lo_hi_hi; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_lo_hi_hi = _GEN_9; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_lo_hi_hi_1 = _GEN_9; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_lo_hi_hi; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_lo_hi_hi = _GEN_9; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_lo_hi_hi_1 = _GEN_9; // @[package.scala:45:27]
wire [2:0] pma_checker_priv_rw_ok_lo_hi = {pma_checker_priv_rw_ok_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_priv_rw_ok_lo = {pma_checker_priv_rw_ok_lo_hi, pma_checker_priv_rw_ok_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_10 = {_pma_checker_entries_barrier_8_io_y_u, _pma_checker_entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_priv_rw_ok_hi_lo_hi; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_hi_lo_hi = _GEN_10; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_hi_lo_hi_1 = _GEN_10; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_hi_lo_hi; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_hi_lo_hi = _GEN_10; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_hi_lo_hi_1 = _GEN_10; // @[package.scala:45:27]
wire [2:0] pma_checker_priv_rw_ok_hi_lo = {pma_checker_priv_rw_ok_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_11 = {_pma_checker_entries_barrier_10_io_y_u, _pma_checker_entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_priv_rw_ok_hi_hi_lo; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_hi_hi_lo = _GEN_11; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_hi_hi_lo_1 = _GEN_11; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_hi_hi_lo; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_hi_hi_lo = _GEN_11; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_hi_hi_lo_1 = _GEN_11; // @[package.scala:45:27]
wire [1:0] _GEN_12 = {_pma_checker_entries_barrier_12_io_y_u, _pma_checker_entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_priv_rw_ok_hi_hi_hi; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_hi_hi_hi = _GEN_12; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_hi_hi_hi_1 = _GEN_12; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_hi_hi_hi; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_hi_hi_hi = _GEN_12; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_hi_hi_hi_1 = _GEN_12; // @[package.scala:45:27]
wire [3:0] pma_checker_priv_rw_ok_hi_hi = {pma_checker_priv_rw_ok_hi_hi_hi, pma_checker_priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_priv_rw_ok_hi = {pma_checker_priv_rw_ok_hi_hi, pma_checker_priv_rw_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__priv_rw_ok_T_2 = {pma_checker_priv_rw_ok_hi, pma_checker_priv_rw_ok_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__priv_rw_ok_T_3 = pma_checker__priv_rw_ok_T_1 ? pma_checker__priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27]
wire [2:0] pma_checker_priv_rw_ok_lo_lo_1 = {pma_checker_priv_rw_ok_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_priv_rw_ok_lo_hi_1 = {pma_checker_priv_rw_ok_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_priv_rw_ok_lo_1 = {pma_checker_priv_rw_ok_lo_hi_1, pma_checker_priv_rw_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] pma_checker_priv_rw_ok_hi_lo_1 = {pma_checker_priv_rw_ok_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_priv_rw_ok_hi_hi_1 = {pma_checker_priv_rw_ok_hi_hi_hi_1, pma_checker_priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] pma_checker_priv_rw_ok_hi_1 = {pma_checker_priv_rw_ok_hi_hi_1, pma_checker_priv_rw_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] pma_checker__priv_rw_ok_T_4 = {pma_checker_priv_rw_ok_hi_1, pma_checker_priv_rw_ok_lo_1}; // @[package.scala:45:27]
wire [12:0] pma_checker__priv_rw_ok_T_5 = ~pma_checker__priv_rw_ok_T_4; // @[package.scala:45:27]
wire [12:0] pma_checker__priv_rw_ok_T_6 = pma_checker_priv_s ? pma_checker__priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}]
wire [12:0] pma_checker_priv_rw_ok = pma_checker__priv_rw_ok_T_3 | pma_checker__priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}]
wire [2:0] pma_checker_priv_x_ok_lo_lo = {pma_checker_priv_x_ok_lo_lo_hi, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_priv_x_ok_lo_hi = {pma_checker_priv_x_ok_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_priv_x_ok_lo = {pma_checker_priv_x_ok_lo_hi, pma_checker_priv_x_ok_lo_lo}; // @[package.scala:45:27]
wire [2:0] pma_checker_priv_x_ok_hi_lo = {pma_checker_priv_x_ok_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_priv_x_ok_hi_hi = {pma_checker_priv_x_ok_hi_hi_hi, pma_checker_priv_x_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_priv_x_ok_hi = {pma_checker_priv_x_ok_hi_hi, pma_checker_priv_x_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__priv_x_ok_T = {pma_checker_priv_x_ok_hi, pma_checker_priv_x_ok_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__priv_x_ok_T_1 = ~pma_checker__priv_x_ok_T; // @[package.scala:45:27]
wire [2:0] pma_checker_priv_x_ok_lo_lo_1 = {pma_checker_priv_x_ok_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_priv_x_ok_lo_hi_1 = {pma_checker_priv_x_ok_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_priv_x_ok_lo_1 = {pma_checker_priv_x_ok_lo_hi_1, pma_checker_priv_x_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] pma_checker_priv_x_ok_hi_lo_1 = {pma_checker_priv_x_ok_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_priv_x_ok_hi_hi_1 = {pma_checker_priv_x_ok_hi_hi_hi_1, pma_checker_priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] pma_checker_priv_x_ok_hi_1 = {pma_checker_priv_x_ok_hi_hi_1, pma_checker_priv_x_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] pma_checker__priv_x_ok_T_2 = {pma_checker_priv_x_ok_hi_1, pma_checker_priv_x_ok_lo_1}; // @[package.scala:45:27]
wire [12:0] pma_checker_priv_x_ok = pma_checker_priv_s ? pma_checker__priv_x_ok_T_1 : pma_checker__priv_x_ok_T_2; // @[package.scala:45:27]
wire [1:0] pma_checker_stage1_bypass_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_stage2, _pma_checker_entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_stage1_bypass_lo_lo = {pma_checker_stage1_bypass_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_stage1_bypass_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_stage2, _pma_checker_entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_stage1_bypass_lo_hi = {pma_checker_stage1_bypass_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_stage1_bypass_lo = {pma_checker_stage1_bypass_lo_hi, pma_checker_stage1_bypass_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_stage1_bypass_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_stage2, _pma_checker_entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_stage1_bypass_hi_lo = {pma_checker_stage1_bypass_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_stage1_bypass_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_stage2, _pma_checker_entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_stage1_bypass_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_stage2, _pma_checker_entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_stage1_bypass_hi_hi = {pma_checker_stage1_bypass_hi_hi_hi, pma_checker_stage1_bypass_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_stage1_bypass_hi = {pma_checker_stage1_bypass_hi_hi, pma_checker_stage1_bypass_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__stage1_bypass_T_3 = {pma_checker_stage1_bypass_hi, pma_checker_stage1_bypass_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_r_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_sr, _pma_checker_entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_r_array_lo_lo = {pma_checker_r_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_r_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_sr, _pma_checker_entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_r_array_lo_hi = {pma_checker_r_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_r_array_lo = {pma_checker_r_array_lo_hi, pma_checker_r_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_r_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_sr, _pma_checker_entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_r_array_hi_lo = {pma_checker_r_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_r_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_sr, _pma_checker_entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_r_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_sr, _pma_checker_entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_r_array_hi_hi = {pma_checker_r_array_hi_hi_hi, pma_checker_r_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_r_array_hi = {pma_checker_r_array_hi_hi, pma_checker_r_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__r_array_T = {pma_checker_r_array_hi, pma_checker_r_array_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__r_array_T_3 = pma_checker__r_array_T; // @[package.scala:45:27]
wire [1:0] _GEN_13 = {_pma_checker_entries_barrier_2_io_y_sx, _pma_checker_entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_r_array_lo_lo_hi_1; // @[package.scala:45:27]
assign pma_checker_r_array_lo_lo_hi_1 = _GEN_13; // @[package.scala:45:27]
wire [1:0] pma_checker_x_array_lo_lo_hi; // @[package.scala:45:27]
assign pma_checker_x_array_lo_lo_hi = _GEN_13; // @[package.scala:45:27]
wire [2:0] pma_checker_r_array_lo_lo_1 = {pma_checker_r_array_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_14 = {_pma_checker_entries_barrier_5_io_y_sx, _pma_checker_entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_r_array_lo_hi_hi_1; // @[package.scala:45:27]
assign pma_checker_r_array_lo_hi_hi_1 = _GEN_14; // @[package.scala:45:27]
wire [1:0] pma_checker_x_array_lo_hi_hi; // @[package.scala:45:27]
assign pma_checker_x_array_lo_hi_hi = _GEN_14; // @[package.scala:45:27]
wire [2:0] pma_checker_r_array_lo_hi_1 = {pma_checker_r_array_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_r_array_lo_1 = {pma_checker_r_array_lo_hi_1, pma_checker_r_array_lo_lo_1}; // @[package.scala:45:27]
wire [1:0] _GEN_15 = {_pma_checker_entries_barrier_8_io_y_sx, _pma_checker_entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_r_array_hi_lo_hi_1; // @[package.scala:45:27]
assign pma_checker_r_array_hi_lo_hi_1 = _GEN_15; // @[package.scala:45:27]
wire [1:0] pma_checker_x_array_hi_lo_hi; // @[package.scala:45:27]
assign pma_checker_x_array_hi_lo_hi = _GEN_15; // @[package.scala:45:27]
wire [2:0] pma_checker_r_array_hi_lo_1 = {pma_checker_r_array_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_16 = {_pma_checker_entries_barrier_10_io_y_sx, _pma_checker_entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_r_array_hi_hi_lo_1; // @[package.scala:45:27]
assign pma_checker_r_array_hi_hi_lo_1 = _GEN_16; // @[package.scala:45:27]
wire [1:0] pma_checker_x_array_hi_hi_lo; // @[package.scala:45:27]
assign pma_checker_x_array_hi_hi_lo = _GEN_16; // @[package.scala:45:27]
wire [1:0] _GEN_17 = {_pma_checker_entries_barrier_12_io_y_sx, _pma_checker_entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_r_array_hi_hi_hi_1; // @[package.scala:45:27]
assign pma_checker_r_array_hi_hi_hi_1 = _GEN_17; // @[package.scala:45:27]
wire [1:0] pma_checker_x_array_hi_hi_hi; // @[package.scala:45:27]
assign pma_checker_x_array_hi_hi_hi = _GEN_17; // @[package.scala:45:27]
wire [3:0] pma_checker_r_array_hi_hi_1 = {pma_checker_r_array_hi_hi_hi_1, pma_checker_r_array_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] pma_checker_r_array_hi_1 = {pma_checker_r_array_hi_hi_1, pma_checker_r_array_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] pma_checker__r_array_T_1 = {pma_checker_r_array_hi_1, pma_checker_r_array_lo_1}; // @[package.scala:45:27]
wire [12:0] pma_checker__r_array_T_4 = pma_checker_priv_rw_ok & pma_checker__r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}]
wire [12:0] pma_checker__r_array_T_5 = pma_checker__r_array_T_4; // @[TLB.scala:520:{41,113}]
wire [13:0] pma_checker_r_array = {1'h1, pma_checker__r_array_T_5}; // @[TLB.scala:520:{20,113}]
wire [13:0] pma_checker__pf_ld_array_T = pma_checker_r_array; // @[TLB.scala:520:20, :597:41]
wire [1:0] pma_checker_w_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_sw, _pma_checker_entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_w_array_lo_lo = {pma_checker_w_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_w_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_sw, _pma_checker_entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_w_array_lo_hi = {pma_checker_w_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_w_array_lo = {pma_checker_w_array_lo_hi, pma_checker_w_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_w_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_sw, _pma_checker_entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_w_array_hi_lo = {pma_checker_w_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_w_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_sw, _pma_checker_entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_w_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_sw, _pma_checker_entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_w_array_hi_hi = {pma_checker_w_array_hi_hi_hi, pma_checker_w_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_w_array_hi = {pma_checker_w_array_hi_hi, pma_checker_w_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__w_array_T = {pma_checker_w_array_hi, pma_checker_w_array_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__w_array_T_1 = pma_checker_priv_rw_ok & pma_checker__w_array_T; // @[package.scala:45:27]
wire [12:0] pma_checker__w_array_T_2 = pma_checker__w_array_T_1; // @[TLB.scala:521:{41,69}]
wire [13:0] pma_checker_w_array = {1'h1, pma_checker__w_array_T_2}; // @[TLB.scala:521:{20,69}]
wire [2:0] pma_checker_x_array_lo_lo = {pma_checker_x_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_x_array_lo_hi = {pma_checker_x_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_x_array_lo = {pma_checker_x_array_lo_hi, pma_checker_x_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] pma_checker_x_array_hi_lo = {pma_checker_x_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_x_array_hi_hi = {pma_checker_x_array_hi_hi_hi, pma_checker_x_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_x_array_hi = {pma_checker_x_array_hi_hi, pma_checker_x_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__x_array_T = {pma_checker_x_array_hi, pma_checker_x_array_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__x_array_T_1 = pma_checker_priv_x_ok & pma_checker__x_array_T; // @[package.scala:45:27]
wire [12:0] pma_checker__x_array_T_2 = pma_checker__x_array_T_1; // @[TLB.scala:522:{40,68}]
wire [13:0] pma_checker_x_array = {1'h1, pma_checker__x_array_T_2}; // @[TLB.scala:522:{20,68}]
wire [1:0] pma_checker_hr_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_hr, _pma_checker_entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_hr_array_lo_lo = {pma_checker_hr_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hr_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_hr, _pma_checker_entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_hr_array_lo_hi = {pma_checker_hr_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_hr_array_lo = {pma_checker_hr_array_lo_hi, pma_checker_hr_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_hr_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_hr, _pma_checker_entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_hr_array_hi_lo = {pma_checker_hr_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hr_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_hr, _pma_checker_entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hr_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_hr, _pma_checker_entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_hr_array_hi_hi = {pma_checker_hr_array_hi_hi_hi, pma_checker_hr_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_hr_array_hi = {pma_checker_hr_array_hi_hi, pma_checker_hr_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__hr_array_T = {pma_checker_hr_array_hi, pma_checker_hr_array_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__hr_array_T_3 = pma_checker__hr_array_T; // @[package.scala:45:27]
wire [1:0] _GEN_18 = {_pma_checker_entries_barrier_2_io_y_hx, _pma_checker_entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hr_array_lo_lo_hi_1; // @[package.scala:45:27]
assign pma_checker_hr_array_lo_lo_hi_1 = _GEN_18; // @[package.scala:45:27]
wire [1:0] pma_checker_hx_array_lo_lo_hi; // @[package.scala:45:27]
assign pma_checker_hx_array_lo_lo_hi = _GEN_18; // @[package.scala:45:27]
wire [2:0] pma_checker_hr_array_lo_lo_1 = {pma_checker_hr_array_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_19 = {_pma_checker_entries_barrier_5_io_y_hx, _pma_checker_entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hr_array_lo_hi_hi_1; // @[package.scala:45:27]
assign pma_checker_hr_array_lo_hi_hi_1 = _GEN_19; // @[package.scala:45:27]
wire [1:0] pma_checker_hx_array_lo_hi_hi; // @[package.scala:45:27]
assign pma_checker_hx_array_lo_hi_hi = _GEN_19; // @[package.scala:45:27]
wire [2:0] pma_checker_hr_array_lo_hi_1 = {pma_checker_hr_array_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_hr_array_lo_1 = {pma_checker_hr_array_lo_hi_1, pma_checker_hr_array_lo_lo_1}; // @[package.scala:45:27]
wire [1:0] _GEN_20 = {_pma_checker_entries_barrier_8_io_y_hx, _pma_checker_entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hr_array_hi_lo_hi_1; // @[package.scala:45:27]
assign pma_checker_hr_array_hi_lo_hi_1 = _GEN_20; // @[package.scala:45:27]
wire [1:0] pma_checker_hx_array_hi_lo_hi; // @[package.scala:45:27]
assign pma_checker_hx_array_hi_lo_hi = _GEN_20; // @[package.scala:45:27]
wire [2:0] pma_checker_hr_array_hi_lo_1 = {pma_checker_hr_array_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_21 = {_pma_checker_entries_barrier_10_io_y_hx, _pma_checker_entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hr_array_hi_hi_lo_1; // @[package.scala:45:27]
assign pma_checker_hr_array_hi_hi_lo_1 = _GEN_21; // @[package.scala:45:27]
wire [1:0] pma_checker_hx_array_hi_hi_lo; // @[package.scala:45:27]
assign pma_checker_hx_array_hi_hi_lo = _GEN_21; // @[package.scala:45:27]
wire [1:0] _GEN_22 = {_pma_checker_entries_barrier_12_io_y_hx, _pma_checker_entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hr_array_hi_hi_hi_1; // @[package.scala:45:27]
assign pma_checker_hr_array_hi_hi_hi_1 = _GEN_22; // @[package.scala:45:27]
wire [1:0] pma_checker_hx_array_hi_hi_hi; // @[package.scala:45:27]
assign pma_checker_hx_array_hi_hi_hi = _GEN_22; // @[package.scala:45:27]
wire [3:0] pma_checker_hr_array_hi_hi_1 = {pma_checker_hr_array_hi_hi_hi_1, pma_checker_hr_array_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] pma_checker_hr_array_hi_1 = {pma_checker_hr_array_hi_hi_1, pma_checker_hr_array_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] pma_checker__hr_array_T_1 = {pma_checker_hr_array_hi_1, pma_checker_hr_array_lo_1}; // @[package.scala:45:27]
wire [1:0] pma_checker_hw_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_hw, _pma_checker_entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_hw_array_lo_lo = {pma_checker_hw_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hw_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_hw, _pma_checker_entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_hw_array_lo_hi = {pma_checker_hw_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_hw_array_lo = {pma_checker_hw_array_lo_hi, pma_checker_hw_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_hw_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_hw, _pma_checker_entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_hw_array_hi_lo = {pma_checker_hw_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hw_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_hw, _pma_checker_entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hw_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_hw, _pma_checker_entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_hw_array_hi_hi = {pma_checker_hw_array_hi_hi_hi, pma_checker_hw_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_hw_array_hi = {pma_checker_hw_array_hi_hi, pma_checker_hw_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__hw_array_T = {pma_checker_hw_array_hi, pma_checker_hw_array_lo}; // @[package.scala:45:27]
wire [2:0] pma_checker_hx_array_lo_lo = {pma_checker_hx_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_hx_array_lo_hi = {pma_checker_hx_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_hx_array_lo = {pma_checker_hx_array_lo_hi, pma_checker_hx_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] pma_checker_hx_array_hi_lo = {pma_checker_hx_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_hx_array_hi_hi = {pma_checker_hx_array_hi_hi_hi, pma_checker_hx_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_hx_array_hi = {pma_checker_hx_array_hi_hi, pma_checker_hx_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__hx_array_T = {pma_checker_hx_array_hi, pma_checker_hx_array_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_pr_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pr, _pma_checker_entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pr_array_lo_lo = {pma_checker_pr_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_pr_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pr, _pma_checker_entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pr_array_lo_hi = {pma_checker_pr_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_pr_array_lo = {pma_checker_pr_array_lo_hi, pma_checker_pr_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_pr_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pr, _pma_checker_entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pr_array_hi_lo = {pma_checker_pr_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_pr_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pr, _pma_checker_entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pr_array_hi_hi = {pma_checker_pr_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_pr_array_hi = {pma_checker_pr_array_hi_hi, pma_checker_pr_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__pr_array_T_1 = {pma_checker_pr_array_hi, pma_checker_pr_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker__pr_array_T_2 = {2'h0, pma_checker__pr_array_T_1}; // @[package.scala:45:27]
wire [13:0] _GEN_23 = pma_checker_ptw_ae_array | pma_checker_final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104]
wire [13:0] pma_checker__pr_array_T_3; // @[TLB.scala:529:104]
assign pma_checker__pr_array_T_3 = _GEN_23; // @[TLB.scala:529:104]
wire [13:0] pma_checker__pw_array_T_3; // @[TLB.scala:531:104]
assign pma_checker__pw_array_T_3 = _GEN_23; // @[TLB.scala:529:104, :531:104]
wire [13:0] pma_checker__px_array_T_3; // @[TLB.scala:533:104]
assign pma_checker__px_array_T_3 = _GEN_23; // @[TLB.scala:529:104, :533:104]
wire [13:0] pma_checker__pr_array_T_4 = ~pma_checker__pr_array_T_3; // @[TLB.scala:529:{89,104}]
wire [13:0] pma_checker_pr_array = pma_checker__pr_array_T_2 & pma_checker__pr_array_T_4; // @[TLB.scala:529:{21,87,89}]
wire [1:0] pma_checker_pw_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pw, _pma_checker_entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pw_array_lo_lo = {pma_checker_pw_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_pw_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pw, _pma_checker_entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pw_array_lo_hi = {pma_checker_pw_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_pw_array_lo = {pma_checker_pw_array_lo_hi, pma_checker_pw_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_pw_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pw, _pma_checker_entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pw_array_hi_lo = {pma_checker_pw_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_pw_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pw, _pma_checker_entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pw_array_hi_hi = {pma_checker_pw_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_pw_array_hi = {pma_checker_pw_array_hi_hi, pma_checker_pw_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__pw_array_T_1 = {pma_checker_pw_array_hi, pma_checker_pw_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker__pw_array_T_2 = {2'h0, pma_checker__pw_array_T_1}; // @[package.scala:45:27]
wire [13:0] pma_checker__pw_array_T_4 = ~pma_checker__pw_array_T_3; // @[TLB.scala:531:{89,104}]
wire [13:0] pma_checker_pw_array = pma_checker__pw_array_T_2 & pma_checker__pw_array_T_4; // @[TLB.scala:531:{21,87,89}]
wire [1:0] pma_checker_px_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_px, _pma_checker_entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_px_array_lo_lo = {pma_checker_px_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_px_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_px, _pma_checker_entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_px_array_lo_hi = {pma_checker_px_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_px_array_lo = {pma_checker_px_array_lo_hi, pma_checker_px_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_px_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_px, _pma_checker_entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_px_array_hi_lo = {pma_checker_px_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_px_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_px, _pma_checker_entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_px_array_hi_hi = {pma_checker_px_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_px_array_hi = {pma_checker_px_array_hi_hi, pma_checker_px_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__px_array_T_1 = {pma_checker_px_array_hi, pma_checker_px_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker__px_array_T_2 = {2'h0, pma_checker__px_array_T_1}; // @[package.scala:45:27]
wire [13:0] pma_checker__px_array_T_4 = ~pma_checker__px_array_T_3; // @[TLB.scala:533:{89,104}]
wire [13:0] pma_checker_px_array = pma_checker__px_array_T_2 & pma_checker__px_array_T_4; // @[TLB.scala:533:{21,87,89}]
wire [1:0] pma_checker__eff_array_T = {2{_pma_checker_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27]
wire [1:0] pma_checker_eff_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_eff, _pma_checker_entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_eff_array_lo_lo = {pma_checker_eff_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_eff_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_eff, _pma_checker_entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_eff_array_lo_hi = {pma_checker_eff_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_eff_array_lo = {pma_checker_eff_array_lo_hi, pma_checker_eff_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_eff_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_eff, _pma_checker_entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_eff_array_hi_lo = {pma_checker_eff_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_eff_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_eff, _pma_checker_entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_eff_array_hi_hi = {pma_checker_eff_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_eff_array_hi = {pma_checker_eff_array_hi_hi, pma_checker_eff_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__eff_array_T_1 = {pma_checker_eff_array_hi, pma_checker_eff_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_eff_array = {pma_checker__eff_array_T, pma_checker__eff_array_T_1}; // @[package.scala:45:27]
wire [1:0] _GEN_24 = {_pma_checker_entries_barrier_2_io_y_c, _pma_checker_entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_c_array_lo_lo_hi; // @[package.scala:45:27]
assign pma_checker_c_array_lo_lo_hi = _GEN_24; // @[package.scala:45:27]
wire [1:0] pma_checker_prefetchable_array_lo_lo_hi; // @[package.scala:45:27]
assign pma_checker_prefetchable_array_lo_lo_hi = _GEN_24; // @[package.scala:45:27]
wire [2:0] pma_checker_c_array_lo_lo = {pma_checker_c_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_25 = {_pma_checker_entries_barrier_5_io_y_c, _pma_checker_entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_c_array_lo_hi_hi; // @[package.scala:45:27]
assign pma_checker_c_array_lo_hi_hi = _GEN_25; // @[package.scala:45:27]
wire [1:0] pma_checker_prefetchable_array_lo_hi_hi; // @[package.scala:45:27]
assign pma_checker_prefetchable_array_lo_hi_hi = _GEN_25; // @[package.scala:45:27]
wire [2:0] pma_checker_c_array_lo_hi = {pma_checker_c_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_c_array_lo = {pma_checker_c_array_lo_hi, pma_checker_c_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_26 = {_pma_checker_entries_barrier_8_io_y_c, _pma_checker_entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_c_array_hi_lo_hi; // @[package.scala:45:27]
assign pma_checker_c_array_hi_lo_hi = _GEN_26; // @[package.scala:45:27]
wire [1:0] pma_checker_prefetchable_array_hi_lo_hi; // @[package.scala:45:27]
assign pma_checker_prefetchable_array_hi_lo_hi = _GEN_26; // @[package.scala:45:27]
wire [2:0] pma_checker_c_array_hi_lo = {pma_checker_c_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_27 = {_pma_checker_entries_barrier_11_io_y_c, _pma_checker_entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_c_array_hi_hi_hi; // @[package.scala:45:27]
assign pma_checker_c_array_hi_hi_hi = _GEN_27; // @[package.scala:45:27]
wire [1:0] pma_checker_prefetchable_array_hi_hi_hi; // @[package.scala:45:27]
assign pma_checker_prefetchable_array_hi_hi_hi = _GEN_27; // @[package.scala:45:27]
wire [2:0] pma_checker_c_array_hi_hi = {pma_checker_c_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_c_array_hi = {pma_checker_c_array_hi_hi, pma_checker_c_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__c_array_T_1 = {pma_checker_c_array_hi, pma_checker_c_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_c_array = {2'h0, pma_checker__c_array_T_1}; // @[package.scala:45:27]
wire [1:0] pma_checker__ppp_array_T = {2{_pma_checker_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27]
wire [1:0] pma_checker_ppp_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ppp, _pma_checker_entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ppp_array_lo_lo = {pma_checker_ppp_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ppp_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ppp, _pma_checker_entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ppp_array_lo_hi = {pma_checker_ppp_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_ppp_array_lo = {pma_checker_ppp_array_lo_hi, pma_checker_ppp_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_ppp_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ppp, _pma_checker_entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ppp_array_hi_lo = {pma_checker_ppp_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ppp_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_ppp, _pma_checker_entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ppp_array_hi_hi = {pma_checker_ppp_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_ppp_array_hi = {pma_checker_ppp_array_hi_hi, pma_checker_ppp_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__ppp_array_T_1 = {pma_checker_ppp_array_hi, pma_checker_ppp_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_ppp_array = {pma_checker__ppp_array_T, pma_checker__ppp_array_T_1}; // @[package.scala:45:27]
wire [1:0] pma_checker__paa_array_T = {2{_pma_checker_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27]
wire [1:0] pma_checker_paa_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_paa, _pma_checker_entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_paa_array_lo_lo = {pma_checker_paa_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_paa_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_paa, _pma_checker_entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_paa_array_lo_hi = {pma_checker_paa_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_paa_array_lo = {pma_checker_paa_array_lo_hi, pma_checker_paa_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_paa_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_paa, _pma_checker_entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_paa_array_hi_lo = {pma_checker_paa_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_paa_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_paa, _pma_checker_entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_paa_array_hi_hi = {pma_checker_paa_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_paa_array_hi = {pma_checker_paa_array_hi_hi, pma_checker_paa_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__paa_array_T_1 = {pma_checker_paa_array_hi, pma_checker_paa_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_paa_array = {pma_checker__paa_array_T, pma_checker__paa_array_T_1}; // @[package.scala:45:27]
wire [1:0] pma_checker__pal_array_T = {2{_pma_checker_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27]
wire [1:0] pma_checker_pal_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pal, _pma_checker_entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pal_array_lo_lo = {pma_checker_pal_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_pal_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pal, _pma_checker_entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pal_array_lo_hi = {pma_checker_pal_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_pal_array_lo = {pma_checker_pal_array_lo_hi, pma_checker_pal_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_pal_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pal, _pma_checker_entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pal_array_hi_lo = {pma_checker_pal_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_pal_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pal, _pma_checker_entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pal_array_hi_hi = {pma_checker_pal_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_pal_array_hi = {pma_checker_pal_array_hi_hi, pma_checker_pal_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__pal_array_T_1 = {pma_checker_pal_array_hi, pma_checker_pal_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_pal_array = {pma_checker__pal_array_T, pma_checker__pal_array_T_1}; // @[package.scala:45:27]
wire [13:0] pma_checker_ppp_array_if_cached = pma_checker_ppp_array | pma_checker_c_array; // @[TLB.scala:537:20, :539:22, :544:39]
wire [13:0] pma_checker_paa_array_if_cached = pma_checker_paa_array | pma_checker_c_array; // @[TLB.scala:537:20, :541:22, :545:39]
wire [13:0] pma_checker_pal_array_if_cached = pma_checker_pal_array | pma_checker_c_array; // @[TLB.scala:537:20, :543:22, :546:39]
wire [2:0] pma_checker_prefetchable_array_lo_lo = {pma_checker_prefetchable_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_prefetchable_array_lo_hi = {pma_checker_prefetchable_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_prefetchable_array_lo = {pma_checker_prefetchable_array_lo_hi, pma_checker_prefetchable_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] pma_checker_prefetchable_array_hi_lo = {pma_checker_prefetchable_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_prefetchable_array_hi_hi = {pma_checker_prefetchable_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_prefetchable_array_hi = {pma_checker_prefetchable_array_hi_hi, pma_checker_prefetchable_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__prefetchable_array_T_2 = {pma_checker_prefetchable_array_hi, pma_checker_prefetchable_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_prefetchable_array = {2'h0, pma_checker__prefetchable_array_T_2}; // @[package.scala:45:27]
wire [3:0] pma_checker__misaligned_T = 4'h1 << pma_checker_io_req_bits_size; // @[OneHot.scala:58:35]
wire [4:0] pma_checker__misaligned_T_1 = {1'h0, pma_checker__misaligned_T} - 5'h1; // @[OneHot.scala:58:35]
wire [3:0] pma_checker__misaligned_T_2 = pma_checker__misaligned_T_1[3:0]; // @[TLB.scala:550:69]
wire [39:0] pma_checker__misaligned_T_3 = {36'h0, pma_checker_io_req_bits_vaddr[3:0] & pma_checker__misaligned_T_2}; // @[TLB.scala:550:{39,69}]
wire pma_checker_misaligned = |pma_checker__misaligned_T_3; // @[TLB.scala:550:{39,77}]
wire [39:0] pma_checker_bad_va_maskedVAddr = pma_checker_io_req_bits_vaddr & 40'hC000000000; // @[TLB.scala:559:43]
wire pma_checker__bad_va_T_2 = pma_checker_bad_va_maskedVAddr == 40'h0; // @[TLB.scala:559:43, :560:51]
wire pma_checker__bad_va_T_3 = pma_checker_bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86]
wire pma_checker__bad_va_T_4 = pma_checker__bad_va_T_3; // @[TLB.scala:560:{71,86}]
wire pma_checker__bad_va_T_5 = pma_checker__bad_va_T_2 | pma_checker__bad_va_T_4; // @[TLB.scala:560:{51,59,71}]
wire pma_checker__bad_va_T_6 = ~pma_checker__bad_va_T_5; // @[TLB.scala:560:{37,59}]
wire pma_checker__bad_va_T_7 = pma_checker__bad_va_T_6; // @[TLB.scala:560:{34,37}]
wire _GEN_28 = pma_checker_io_req_bits_cmd == 5'h6; // @[package.scala:16:47]
wire pma_checker__cmd_lrsc_T; // @[package.scala:16:47]
assign pma_checker__cmd_lrsc_T = _GEN_28; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_2; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_2 = _GEN_28; // @[package.scala:16:47]
wire _GEN_29 = pma_checker_io_req_bits_cmd == 5'h7; // @[package.scala:16:47]
wire pma_checker__cmd_lrsc_T_1; // @[package.scala:16:47]
assign pma_checker__cmd_lrsc_T_1 = _GEN_29; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_3; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_3 = _GEN_29; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_3; // @[Consts.scala:90:66]
assign pma_checker__cmd_write_T_3 = _GEN_29; // @[package.scala:16:47]
wire pma_checker__cmd_lrsc_T_2 = pma_checker__cmd_lrsc_T | pma_checker__cmd_lrsc_T_1; // @[package.scala:16:47, :81:59]
wire pma_checker_cmd_lrsc = pma_checker__cmd_lrsc_T_2; // @[package.scala:81:59]
wire _GEN_30 = pma_checker_io_req_bits_cmd == 5'h4; // @[package.scala:16:47]
wire pma_checker__cmd_amo_logical_T; // @[package.scala:16:47]
assign pma_checker__cmd_amo_logical_T = _GEN_30; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_7; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_7 = _GEN_30; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_5; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_5 = _GEN_30; // @[package.scala:16:47]
wire _GEN_31 = pma_checker_io_req_bits_cmd == 5'h9; // @[package.scala:16:47]
wire pma_checker__cmd_amo_logical_T_1; // @[package.scala:16:47]
assign pma_checker__cmd_amo_logical_T_1 = _GEN_31; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_8; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_8 = _GEN_31; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_6; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_6 = _GEN_31; // @[package.scala:16:47]
wire _GEN_32 = pma_checker_io_req_bits_cmd == 5'hA; // @[package.scala:16:47]
wire pma_checker__cmd_amo_logical_T_2; // @[package.scala:16:47]
assign pma_checker__cmd_amo_logical_T_2 = _GEN_32; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_9; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_9 = _GEN_32; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_7; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_7 = _GEN_32; // @[package.scala:16:47]
wire _GEN_33 = pma_checker_io_req_bits_cmd == 5'hB; // @[package.scala:16:47]
wire pma_checker__cmd_amo_logical_T_3; // @[package.scala:16:47]
assign pma_checker__cmd_amo_logical_T_3 = _GEN_33; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_10; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_10 = _GEN_33; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_8; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_8 = _GEN_33; // @[package.scala:16:47]
wire pma_checker__cmd_amo_logical_T_4 = pma_checker__cmd_amo_logical_T | pma_checker__cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_amo_logical_T_5 = pma_checker__cmd_amo_logical_T_4 | pma_checker__cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_amo_logical_T_6 = pma_checker__cmd_amo_logical_T_5 | pma_checker__cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59]
wire pma_checker_cmd_amo_logical = pma_checker__cmd_amo_logical_T_6; // @[package.scala:81:59]
wire _GEN_34 = pma_checker_io_req_bits_cmd == 5'h8; // @[package.scala:16:47]
wire pma_checker__cmd_amo_arithmetic_T; // @[package.scala:16:47]
assign pma_checker__cmd_amo_arithmetic_T = _GEN_34; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_14; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_14 = _GEN_34; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_12; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_12 = _GEN_34; // @[package.scala:16:47]
wire _GEN_35 = pma_checker_io_req_bits_cmd == 5'hC; // @[package.scala:16:47]
wire pma_checker__cmd_amo_arithmetic_T_1; // @[package.scala:16:47]
assign pma_checker__cmd_amo_arithmetic_T_1 = _GEN_35; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_15; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_15 = _GEN_35; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_13; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_13 = _GEN_35; // @[package.scala:16:47]
wire _GEN_36 = pma_checker_io_req_bits_cmd == 5'hD; // @[package.scala:16:47]
wire pma_checker__cmd_amo_arithmetic_T_2; // @[package.scala:16:47]
assign pma_checker__cmd_amo_arithmetic_T_2 = _GEN_36; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_16; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_16 = _GEN_36; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_14; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_14 = _GEN_36; // @[package.scala:16:47]
wire _GEN_37 = pma_checker_io_req_bits_cmd == 5'hE; // @[package.scala:16:47]
wire pma_checker__cmd_amo_arithmetic_T_3; // @[package.scala:16:47]
assign pma_checker__cmd_amo_arithmetic_T_3 = _GEN_37; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_17; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_17 = _GEN_37; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_15; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_15 = _GEN_37; // @[package.scala:16:47]
wire _GEN_38 = pma_checker_io_req_bits_cmd == 5'hF; // @[package.scala:16:47]
wire pma_checker__cmd_amo_arithmetic_T_4; // @[package.scala:16:47]
assign pma_checker__cmd_amo_arithmetic_T_4 = _GEN_38; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_18; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_18 = _GEN_38; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_16; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_16 = _GEN_38; // @[package.scala:16:47]
wire pma_checker__cmd_amo_arithmetic_T_5 = pma_checker__cmd_amo_arithmetic_T | pma_checker__cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_amo_arithmetic_T_6 = pma_checker__cmd_amo_arithmetic_T_5 | pma_checker__cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_amo_arithmetic_T_7 = pma_checker__cmd_amo_arithmetic_T_6 | pma_checker__cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_amo_arithmetic_T_8 = pma_checker__cmd_amo_arithmetic_T_7 | pma_checker__cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59]
wire pma_checker_cmd_amo_arithmetic = pma_checker__cmd_amo_arithmetic_T_8; // @[package.scala:81:59]
wire _GEN_39 = pma_checker_io_req_bits_cmd == 5'h11; // @[TLB.scala:573:41]
wire pma_checker_cmd_put_partial; // @[TLB.scala:573:41]
assign pma_checker_cmd_put_partial = _GEN_39; // @[TLB.scala:573:41]
wire pma_checker__cmd_write_T_1; // @[Consts.scala:90:49]
assign pma_checker__cmd_write_T_1 = _GEN_39; // @[TLB.scala:573:41]
wire pma_checker__cmd_read_T = pma_checker_io_req_bits_cmd == 5'h0; // @[package.scala:16:47]
wire _GEN_40 = pma_checker_io_req_bits_cmd == 5'h10; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_1; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_1 = _GEN_40; // @[package.scala:16:47]
wire pma_checker__cmd_readx_T; // @[TLB.scala:575:56]
assign pma_checker__cmd_readx_T = _GEN_40; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_4 = pma_checker__cmd_read_T | pma_checker__cmd_read_T_1; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_5 = pma_checker__cmd_read_T_4 | pma_checker__cmd_read_T_2; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_6 = pma_checker__cmd_read_T_5 | pma_checker__cmd_read_T_3; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_11 = pma_checker__cmd_read_T_7 | pma_checker__cmd_read_T_8; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_12 = pma_checker__cmd_read_T_11 | pma_checker__cmd_read_T_9; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_13 = pma_checker__cmd_read_T_12 | pma_checker__cmd_read_T_10; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_19 = pma_checker__cmd_read_T_14 | pma_checker__cmd_read_T_15; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_20 = pma_checker__cmd_read_T_19 | pma_checker__cmd_read_T_16; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_21 = pma_checker__cmd_read_T_20 | pma_checker__cmd_read_T_17; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_22 = pma_checker__cmd_read_T_21 | pma_checker__cmd_read_T_18; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_23 = pma_checker__cmd_read_T_13 | pma_checker__cmd_read_T_22; // @[package.scala:81:59]
wire pma_checker_cmd_read = pma_checker__cmd_read_T_6 | pma_checker__cmd_read_T_23; // @[package.scala:81:59]
wire pma_checker__cmd_write_T = pma_checker_io_req_bits_cmd == 5'h1; // @[DCache.scala:120:32]
wire pma_checker__cmd_write_T_2 = pma_checker__cmd_write_T | pma_checker__cmd_write_T_1; // @[Consts.scala:90:{32,42,49}]
wire pma_checker__cmd_write_T_4 = pma_checker__cmd_write_T_2 | pma_checker__cmd_write_T_3; // @[Consts.scala:90:{42,59,66}]
wire pma_checker__cmd_write_T_9 = pma_checker__cmd_write_T_5 | pma_checker__cmd_write_T_6; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_write_T_10 = pma_checker__cmd_write_T_9 | pma_checker__cmd_write_T_7; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_write_T_11 = pma_checker__cmd_write_T_10 | pma_checker__cmd_write_T_8; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_write_T_17 = pma_checker__cmd_write_T_12 | pma_checker__cmd_write_T_13; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_write_T_18 = pma_checker__cmd_write_T_17 | pma_checker__cmd_write_T_14; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_write_T_19 = pma_checker__cmd_write_T_18 | pma_checker__cmd_write_T_15; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_write_T_20 = pma_checker__cmd_write_T_19 | pma_checker__cmd_write_T_16; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_write_T_21 = pma_checker__cmd_write_T_11 | pma_checker__cmd_write_T_20; // @[package.scala:81:59]
wire pma_checker_cmd_write = pma_checker__cmd_write_T_4 | pma_checker__cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire pma_checker__cmd_write_perms_T = pma_checker_io_req_bits_cmd == 5'h5; // @[package.scala:16:47]
wire pma_checker__cmd_write_perms_T_1 = pma_checker_io_req_bits_cmd == 5'h17; // @[package.scala:16:47]
wire pma_checker__cmd_write_perms_T_2 = pma_checker__cmd_write_perms_T | pma_checker__cmd_write_perms_T_1; // @[package.scala:16:47, :81:59]
wire pma_checker_cmd_write_perms = pma_checker_cmd_write | pma_checker__cmd_write_perms_T_2; // @[package.scala:81:59]
wire [13:0] pma_checker__ae_array_T = pma_checker_misaligned ? pma_checker_eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8]
wire [13:0] _GEN_41 = {14{pma_checker_cmd_lrsc}}; // @[TLB.scala:570:33, :583:8]
wire [13:0] pma_checker__ae_array_T_2; // @[TLB.scala:583:8]
assign pma_checker__ae_array_T_2 = _GEN_41; // @[TLB.scala:583:8]
wire [13:0] pma_checker__must_alloc_array_T_9; // @[TLB.scala:596:8]
assign pma_checker__must_alloc_array_T_9 = _GEN_41; // @[TLB.scala:583:8, :596:8]
wire [13:0] pma_checker_ae_array = pma_checker__ae_array_T | pma_checker__ae_array_T_2; // @[TLB.scala:582:{8,37}, :583:8]
wire [13:0] pma_checker__ae_ld_array_T = ~pma_checker_pr_array; // @[TLB.scala:529:87, :586:46]
wire [13:0] pma_checker__ae_ld_array_T_1 = pma_checker_ae_array | pma_checker__ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}]
wire [13:0] pma_checker_ae_ld_array = pma_checker_cmd_read ? pma_checker__ae_ld_array_T_1 : 14'h0; // @[TLB.scala:586:{24,44}]
wire [13:0] pma_checker__ae_st_array_T = ~pma_checker_pw_array; // @[TLB.scala:531:87, :588:37]
wire [13:0] pma_checker__ae_st_array_T_1 = pma_checker_ae_array | pma_checker__ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}]
wire [13:0] pma_checker__ae_st_array_T_2 = pma_checker_cmd_write_perms ? pma_checker__ae_st_array_T_1 : 14'h0; // @[TLB.scala:577:35, :588:{8,35}]
wire [13:0] pma_checker__ae_st_array_T_3 = ~pma_checker_ppp_array_if_cached; // @[TLB.scala:544:39, :589:26]
wire [13:0] pma_checker__ae_st_array_T_4 = pma_checker_cmd_put_partial ? pma_checker__ae_st_array_T_3 : 14'h0; // @[TLB.scala:573:41, :589:{8,26}]
wire [13:0] pma_checker__ae_st_array_T_5 = pma_checker__ae_st_array_T_2 | pma_checker__ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8]
wire [13:0] pma_checker__ae_st_array_T_6 = ~pma_checker_pal_array_if_cached; // @[TLB.scala:546:39, :590:26]
wire [13:0] pma_checker__ae_st_array_T_7 = pma_checker_cmd_amo_logical ? pma_checker__ae_st_array_T_6 : 14'h0; // @[TLB.scala:571:40, :590:{8,26}]
wire [13:0] pma_checker__ae_st_array_T_8 = pma_checker__ae_st_array_T_5 | pma_checker__ae_st_array_T_7; // @[TLB.scala:588:53, :589:53, :590:8]
wire [13:0] pma_checker__ae_st_array_T_9 = ~pma_checker_paa_array_if_cached; // @[TLB.scala:545:39, :591:29]
wire [13:0] pma_checker__ae_st_array_T_10 = pma_checker_cmd_amo_arithmetic ? pma_checker__ae_st_array_T_9 : 14'h0; // @[TLB.scala:572:43, :591:{8,29}]
wire [13:0] pma_checker_ae_st_array = pma_checker__ae_st_array_T_8 | pma_checker__ae_st_array_T_10; // @[TLB.scala:589:53, :590:53, :591:8]
wire [13:0] pma_checker__must_alloc_array_T = ~pma_checker_ppp_array; // @[TLB.scala:539:22, :593:26]
wire [13:0] pma_checker__must_alloc_array_T_1 = pma_checker_cmd_put_partial ? pma_checker__must_alloc_array_T : 14'h0; // @[TLB.scala:573:41, :593:{8,26}]
wire [13:0] pma_checker__must_alloc_array_T_2 = ~pma_checker_pal_array; // @[TLB.scala:543:22, :594:26]
wire [13:0] pma_checker__must_alloc_array_T_3 = pma_checker_cmd_amo_logical ? pma_checker__must_alloc_array_T_2 : 14'h0; // @[TLB.scala:571:40, :594:{8,26}]
wire [13:0] pma_checker__must_alloc_array_T_4 = pma_checker__must_alloc_array_T_1 | pma_checker__must_alloc_array_T_3; // @[TLB.scala:593:{8,43}, :594:8]
wire [13:0] pma_checker__must_alloc_array_T_5 = ~pma_checker_paa_array; // @[TLB.scala:541:22, :595:29]
wire [13:0] pma_checker__must_alloc_array_T_6 = pma_checker_cmd_amo_arithmetic ? pma_checker__must_alloc_array_T_5 : 14'h0; // @[TLB.scala:572:43, :595:{8,29}]
wire [13:0] pma_checker__must_alloc_array_T_7 = pma_checker__must_alloc_array_T_4 | pma_checker__must_alloc_array_T_6; // @[TLB.scala:593:43, :594:43, :595:8]
wire [13:0] pma_checker_must_alloc_array = pma_checker__must_alloc_array_T_7 | pma_checker__must_alloc_array_T_9; // @[TLB.scala:594:43, :595:46, :596:8]
wire [13:0] pma_checker__pf_ld_array_T_1 = ~pma_checker__pf_ld_array_T; // @[TLB.scala:597:{37,41}]
wire [13:0] pma_checker__pf_ld_array_T_2 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73]
wire [13:0] pma_checker__pf_ld_array_T_3 = pma_checker__pf_ld_array_T_1 & pma_checker__pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}]
wire [13:0] pma_checker__pf_ld_array_T_4 = pma_checker__pf_ld_array_T_3 | pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}]
wire [13:0] pma_checker__pf_ld_array_T_5 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106]
wire [13:0] pma_checker__pf_ld_array_T_6 = pma_checker__pf_ld_array_T_4 & pma_checker__pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}]
wire [13:0] pma_checker_pf_ld_array = pma_checker_cmd_read ? pma_checker__pf_ld_array_T_6 : 14'h0; // @[TLB.scala:597:{24,104}]
wire [13:0] pma_checker__pf_st_array_T = ~pma_checker_w_array; // @[TLB.scala:521:20, :598:44]
wire [13:0] pma_checker__pf_st_array_T_1 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55]
wire [13:0] pma_checker__pf_st_array_T_2 = pma_checker__pf_st_array_T & pma_checker__pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}]
wire [13:0] pma_checker__pf_st_array_T_3 = pma_checker__pf_st_array_T_2 | pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}]
wire [13:0] pma_checker__pf_st_array_T_4 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88]
wire [13:0] pma_checker__pf_st_array_T_5 = pma_checker__pf_st_array_T_3 & pma_checker__pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}]
wire [13:0] pma_checker_pf_st_array = pma_checker_cmd_write_perms ? pma_checker__pf_st_array_T_5 : 14'h0; // @[TLB.scala:577:35, :598:{24,86}]
wire [13:0] pma_checker__pf_inst_array_T = ~pma_checker_x_array; // @[TLB.scala:522:20, :599:25]
wire [13:0] pma_checker__pf_inst_array_T_1 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36]
wire [13:0] pma_checker__pf_inst_array_T_2 = pma_checker__pf_inst_array_T & pma_checker__pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}]
wire [13:0] pma_checker__pf_inst_array_T_3 = pma_checker__pf_inst_array_T_2 | pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}]
wire [13:0] pma_checker__pf_inst_array_T_4 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69]
wire [13:0] pma_checker_pf_inst_array = pma_checker__pf_inst_array_T_3 & pma_checker__pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}]
wire [13:0] pma_checker__gf_ld_array_T_4 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100]
wire [13:0] pma_checker__gf_ld_array_T_5 = pma_checker__gf_ld_array_T_3 & pma_checker__gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}]
wire [13:0] pma_checker__gf_st_array_T_3 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81]
wire [13:0] pma_checker__gf_st_array_T_4 = pma_checker__gf_st_array_T_2 & pma_checker__gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}]
wire [13:0] pma_checker__gf_inst_array_T_2 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64]
wire [13:0] pma_checker__gf_inst_array_T_3 = pma_checker__gf_inst_array_T_1 & pma_checker__gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}]
wire pma_checker__gpa_hits_hit_mask_T = pma_checker_vpn == 27'h0; // @[TLB.scala:335:30, :606:73]
wire [13:0] pma_checker__io_resp_pf_ld_T_1 = pma_checker_pf_ld_array & 14'h2000; // @[TLB.scala:597:24, :633:57]
wire pma_checker__io_resp_pf_ld_T_2 = |pma_checker__io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}]
assign pma_checker__io_resp_pf_ld_T_3 = pma_checker__io_resp_pf_ld_T_2; // @[TLB.scala:633:{41,65}]
assign pma_checker_io_resp_pf_ld = pma_checker__io_resp_pf_ld_T_3; // @[TLB.scala:633:41]
wire [13:0] pma_checker__io_resp_pf_st_T_1 = pma_checker_pf_st_array & 14'h2000; // @[TLB.scala:598:24, :634:64]
wire pma_checker__io_resp_pf_st_T_2 = |pma_checker__io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}]
assign pma_checker__io_resp_pf_st_T_3 = pma_checker__io_resp_pf_st_T_2; // @[TLB.scala:634:{48,72}]
assign pma_checker_io_resp_pf_st = pma_checker__io_resp_pf_st_T_3; // @[TLB.scala:634:48]
wire [13:0] pma_checker__io_resp_pf_inst_T = pma_checker_pf_inst_array & 14'h2000; // @[TLB.scala:599:67, :635:47]
wire pma_checker__io_resp_pf_inst_T_1 = |pma_checker__io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}]
assign pma_checker__io_resp_pf_inst_T_2 = pma_checker__io_resp_pf_inst_T_1; // @[TLB.scala:635:{29,55}]
assign pma_checker_io_resp_pf_inst = pma_checker__io_resp_pf_inst_T_2; // @[TLB.scala:635:29]
wire [13:0] pma_checker__io_resp_ae_ld_T = pma_checker_ae_ld_array & 14'h2000; // @[TLB.scala:586:24, :641:33]
assign pma_checker__io_resp_ae_ld_T_1 = |pma_checker__io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}]
assign pma_checker_io_resp_ae_ld = pma_checker__io_resp_ae_ld_T_1; // @[TLB.scala:641:41]
wire [13:0] pma_checker__io_resp_ae_st_T = pma_checker_ae_st_array & 14'h2000; // @[TLB.scala:590:53, :642:33]
assign pma_checker__io_resp_ae_st_T_1 = |pma_checker__io_resp_ae_st_T; // @[TLB.scala:642:{33,41}]
assign pma_checker_io_resp_ae_st = pma_checker__io_resp_ae_st_T_1; // @[TLB.scala:642:41]
wire [13:0] pma_checker__io_resp_ae_inst_T = ~pma_checker_px_array; // @[TLB.scala:533:87, :643:23]
wire [13:0] pma_checker__io_resp_ae_inst_T_1 = pma_checker__io_resp_ae_inst_T & 14'h2000; // @[TLB.scala:643:{23,33}]
assign pma_checker__io_resp_ae_inst_T_2 = |pma_checker__io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}]
assign pma_checker_io_resp_ae_inst = pma_checker__io_resp_ae_inst_T_2; // @[TLB.scala:643:41]
assign pma_checker__io_resp_ma_ld_T = pma_checker_misaligned & pma_checker_cmd_read; // @[TLB.scala:550:77, :645:31]
assign pma_checker_io_resp_ma_ld = pma_checker__io_resp_ma_ld_T; // @[TLB.scala:645:31]
assign pma_checker__io_resp_ma_st_T = pma_checker_misaligned & pma_checker_cmd_write; // @[TLB.scala:550:77, :646:31]
assign pma_checker_io_resp_ma_st = pma_checker__io_resp_ma_st_T; // @[TLB.scala:646:31]
wire [13:0] pma_checker__io_resp_cacheable_T = pma_checker_c_array & 14'h2000; // @[TLB.scala:537:20, :648:33]
assign pma_checker__io_resp_cacheable_T_1 = |pma_checker__io_resp_cacheable_T; // @[TLB.scala:648:{33,41}]
assign pma_checker_io_resp_cacheable = pma_checker__io_resp_cacheable_T_1; // @[TLB.scala:648:41]
wire [13:0] pma_checker__io_resp_must_alloc_T = pma_checker_must_alloc_array & 14'h2000; // @[TLB.scala:595:46, :649:43]
assign pma_checker__io_resp_must_alloc_T_1 = |pma_checker__io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}]
assign pma_checker_io_resp_must_alloc = pma_checker__io_resp_must_alloc_T_1; // @[TLB.scala:649:51]
wire [13:0] pma_checker__io_resp_prefetchable_T = pma_checker_prefetchable_array & 14'h2000; // @[TLB.scala:547:31, :650:47]
wire pma_checker__io_resp_prefetchable_T_1 = |pma_checker__io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}]
assign pma_checker__io_resp_prefetchable_T_2 = pma_checker__io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}]
assign pma_checker_io_resp_prefetchable = pma_checker__io_resp_prefetchable_T_2; // @[TLB.scala:650:59]
assign pma_checker__io_resp_paddr_T_1 = {pma_checker_ppn, pma_checker__io_resp_paddr_T}; // @[Mux.scala:30:73]
assign pma_checker_io_resp_paddr = pma_checker__io_resp_paddr_T_1; // @[TLB.scala:652:23]
wire [27:0] pma_checker__io_resp_gpa_page_T_1 = {1'h0, pma_checker_vpn}; // @[TLB.scala:335:30, :657:36]
wire [27:0] pma_checker_io_resp_gpa_page = pma_checker__io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}]
wire [11:0] pma_checker_io_resp_gpa_offset = pma_checker__io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}]
assign pma_checker__io_resp_gpa_T = {pma_checker_io_resp_gpa_page, pma_checker_io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8]
assign pma_checker_io_resp_gpa = pma_checker__io_resp_gpa_T; // @[TLB.scala:659:8]
wire pma_checker_ignore_1 = pma_checker__ignore_T_1; // @[TLB.scala:182:{28,34}]
wire pma_checker_ignore_4 = pma_checker__ignore_T_4; // @[TLB.scala:182:{28,34}]
wire pma_checker_ignore_7 = pma_checker__ignore_T_7; // @[TLB.scala:182:{28,34}]
wire pma_checker_ignore_10 = pma_checker__ignore_T_10; // @[TLB.scala:182:{28,34}]
wire replace; // @[Replacement.scala:37:29]
wire [1:0] lfsr_lo_lo_lo = {_lfsr_prng_io_out_1, _lfsr_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_lo_lo_hi = {_lfsr_prng_io_out_3, _lfsr_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_lo_lo = {lfsr_lo_lo_hi, lfsr_lo_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] lfsr_lo_hi_lo = {_lfsr_prng_io_out_5, _lfsr_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_lo_hi_hi = {_lfsr_prng_io_out_7, _lfsr_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_lo_hi = {lfsr_lo_hi_hi, lfsr_lo_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] lfsr_lo = {lfsr_lo_hi, lfsr_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] lfsr_hi_lo_lo = {_lfsr_prng_io_out_9, _lfsr_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_hi_lo_hi = {_lfsr_prng_io_out_11, _lfsr_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_hi_lo = {lfsr_hi_lo_hi, lfsr_hi_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] lfsr_hi_hi_lo = {_lfsr_prng_io_out_13, _lfsr_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_hi_hi_hi = {_lfsr_prng_io_out_15, _lfsr_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_hi_hi = {lfsr_hi_hi_hi, lfsr_hi_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] lfsr_hi = {lfsr_hi_hi, lfsr_hi_lo}; // @[PRNG.scala:95:17]
wire [15:0] lfsr = {lfsr_hi, lfsr_lo}; // @[PRNG.scala:95:17]
wire [39:0] _metaArb_io_in_5_bits_addr_T_2; // @[DCache.scala:1018:36]
wire [39:0] _metaArb_io_in_1_bits_addr_T_2; // @[DCache.scala:454:36]
wire [4:0] _metaArb_io_in_1_bits_idx_T_2; // @[DCache.scala:453:35]
wire _metaArb_io_in_2_valid_T; // @[DCache.scala:462:63]
wire metaArb__grant_T_1 = metaArb_io_in_2_valid; // @[Arbiter.scala:45:68]
wire [39:0] _metaArb_io_in_2_bits_addr_T_2; // @[DCache.scala:466:36]
wire [4:0] _metaArb_io_in_2_bits_idx_T; // @[DCache.scala:465:40]
wire [22:0] _metaArb_io_in_2_bits_data_T_1; // @[DCache.scala:467:97]
wire metaArb__io_in_3_ready_T; // @[Arbiter.scala:153:19]
wire _metaArb_io_in_3_valid_T_2; // @[DCache.scala:741:53]
wire [39:0] _metaArb_io_in_3_bits_addr_T_2; // @[DCache.scala:745:36]
wire [4:0] _metaArb_io_in_3_bits_idx_T; // @[DCache.scala:744:40]
wire [22:0] _metaArb_io_in_3_bits_data_T_18; // @[DCache.scala:746:134]
wire metaArb__io_in_4_ready_T; // @[Arbiter.scala:153:19]
wire [39:0] _metaArb_io_in_4_bits_addr_T_2; // @[DCache.scala:912:36]
wire releaseWay; // @[DCache.scala:232:24]
wire [22:0] _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:913:97]
wire metaArb__io_in_5_ready_T; // @[Arbiter.scala:153:19]
wire metaArb__io_in_6_ready_T; // @[Arbiter.scala:153:19]
wire [39:0] _metaArb_io_in_6_bits_addr_T_1; // @[DCache.scala:773:36]
wire metaArb__io_in_7_ready_T; // @[Arbiter.scala:153:19]
wire [4:0] _metaArb_io_in_7_bits_idx_T; // @[DCache.scala:263:58]
wire metaArb__io_out_valid_T_1; // @[Arbiter.scala:154:31]
wire [39:0] metaArb_io_in_0_bits_addr; // @[DCache.scala:135:28]
wire [39:0] metaArb_io_in_1_bits_addr; // @[DCache.scala:135:28]
wire [4:0] metaArb_io_in_1_bits_idx; // @[DCache.scala:135:28]
wire [39:0] metaArb_io_in_2_bits_addr; // @[DCache.scala:135:28]
wire [4:0] metaArb_io_in_2_bits_idx; // @[DCache.scala:135:28]
wire metaArb_io_in_2_bits_way_en; // @[DCache.scala:135:28]
wire [22:0] metaArb_io_in_2_bits_data; // @[DCache.scala:135:28]
wire [39:0] metaArb_io_in_3_bits_addr; // @[DCache.scala:135:28]
wire [4:0] metaArb_io_in_3_bits_idx; // @[DCache.scala:135:28]
wire metaArb_io_in_3_bits_way_en; // @[DCache.scala:135:28]
wire [22:0] metaArb_io_in_3_bits_data; // @[DCache.scala:135:28]
wire metaArb_io_in_3_ready; // @[DCache.scala:135:28]
wire metaArb_io_in_3_valid; // @[DCache.scala:135:28]
wire [39:0] metaArb_io_in_4_bits_addr; // @[DCache.scala:135:28]
wire metaArb_io_in_4_bits_way_en; // @[DCache.scala:135:28]
wire [22:0] metaArb_io_in_4_bits_data; // @[DCache.scala:135:28]
wire metaArb_io_in_4_ready; // @[DCache.scala:135:28]
wire [39:0] metaArb_io_in_5_bits_addr; // @[DCache.scala:135:28]
wire metaArb_io_in_5_bits_way_en; // @[DCache.scala:135:28]
wire [22:0] metaArb_io_in_5_bits_data; // @[DCache.scala:135:28]
wire metaArb_io_in_5_ready; // @[DCache.scala:135:28]
wire [39:0] metaArb_io_in_6_bits_addr; // @[DCache.scala:135:28]
wire metaArb_io_in_6_bits_way_en; // @[DCache.scala:135:28]
wire [22:0] metaArb_io_in_6_bits_data; // @[DCache.scala:135:28]
wire metaArb_io_in_6_ready; // @[DCache.scala:135:28]
wire [4:0] metaArb_io_in_7_bits_idx; // @[DCache.scala:135:28]
wire metaArb_io_in_7_bits_way_en; // @[DCache.scala:135:28]
wire [22:0] metaArb_io_in_7_bits_data; // @[DCache.scala:135:28]
wire metaArb_io_in_7_ready; // @[DCache.scala:135:28]
wire metaArb_io_out_bits_write; // @[DCache.scala:135:28]
wire [39:0] metaArb_io_out_bits_addr; // @[DCache.scala:135:28]
wire [4:0] metaArb_io_out_bits_idx; // @[DCache.scala:135:28]
wire metaArb_io_out_bits_way_en; // @[DCache.scala:135:28]
wire [22:0] metaArb_io_out_bits_data; // @[DCache.scala:135:28]
wire metaArb_io_out_valid; // @[DCache.scala:135:28]
wire [2:0] metaArb_io_chosen; // @[DCache.scala:135:28]
assign metaArb_io_chosen = metaArb_io_in_2_valid ? 3'h2 : {~metaArb_io_in_3_valid, 2'h3}; // @[Arbiter.scala:145:26, :146:17]
assign metaArb_io_out_bits_addr = metaArb_io_in_2_valid ? metaArb_io_in_2_bits_addr : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_addr : metaArb_io_in_7_bits_addr; // @[Arbiter.scala:145:26, :147:19]
assign metaArb_io_out_bits_idx = metaArb_io_in_2_valid ? metaArb_io_in_2_bits_idx : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_idx : metaArb_io_in_7_bits_idx; // @[Arbiter.scala:145:26, :147:19]
assign metaArb_io_out_bits_way_en = metaArb_io_in_2_valid ? metaArb_io_in_2_bits_way_en : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_way_en : metaArb_io_in_7_bits_way_en; // @[Arbiter.scala:145:26, :147:19]
assign metaArb_io_out_bits_data = metaArb_io_in_2_valid ? metaArb_io_in_2_bits_data : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_data : metaArb_io_in_7_bits_data; // @[Arbiter.scala:145:26, :147:19]
assign metaArb_io_out_bits_write = metaArb_io_in_2_valid | metaArb_io_in_3_valid; // @[Arbiter.scala:145:26, :147:19]
wire metaArb__grant_T_2 = metaArb__grant_T_1 | metaArb_io_in_3_valid; // @[Arbiter.scala:45:68]
wire metaArb__grant_T_3 = metaArb__grant_T_2; // @[Arbiter.scala:45:68]
wire metaArb__grant_T_4 = metaArb__grant_T_3; // @[Arbiter.scala:45:68]
wire metaArb__grant_T_5 = metaArb__grant_T_4; // @[Arbiter.scala:45:68]
wire metaArb_grant_3 = ~metaArb__grant_T_1; // @[Arbiter.scala:45:{68,78}]
assign metaArb__io_in_3_ready_T = metaArb_grant_3; // @[Arbiter.scala:45:78, :153:19]
wire metaArb_grant_4 = ~metaArb__grant_T_2; // @[Arbiter.scala:45:{68,78}]
assign metaArb__io_in_4_ready_T = metaArb_grant_4; // @[Arbiter.scala:45:78, :153:19]
wire metaArb_grant_5 = ~metaArb__grant_T_3; // @[Arbiter.scala:45:{68,78}]
assign metaArb__io_in_5_ready_T = metaArb_grant_5; // @[Arbiter.scala:45:78, :153:19]
wire metaArb_grant_6 = ~metaArb__grant_T_4; // @[Arbiter.scala:45:{68,78}]
assign metaArb__io_in_6_ready_T = metaArb_grant_6; // @[Arbiter.scala:45:78, :153:19]
wire metaArb_grant_7 = ~metaArb__grant_T_5; // @[Arbiter.scala:45:{68,78}]
assign metaArb__io_in_7_ready_T = metaArb_grant_7; // @[Arbiter.scala:45:78, :153:19]
assign metaArb_io_in_3_ready = metaArb__io_in_3_ready_T; // @[Arbiter.scala:153:19]
assign metaArb_io_in_4_ready = metaArb__io_in_4_ready_T; // @[Arbiter.scala:153:19]
assign metaArb_io_in_5_ready = metaArb__io_in_5_ready_T; // @[Arbiter.scala:153:19]
assign metaArb_io_in_6_ready = metaArb__io_in_6_ready_T; // @[Arbiter.scala:153:19]
assign metaArb_io_in_7_ready = metaArb__io_in_7_ready_T; // @[Arbiter.scala:153:19]
wire metaArb__io_out_valid_T = ~metaArb_grant_7; // @[Arbiter.scala:45:78, :154:19]
assign metaArb__io_out_valid_T_1 = metaArb__io_out_valid_T | metaArb_io_in_7_valid; // @[Arbiter.scala:154:{19,31}]
assign metaArb_io_out_valid = metaArb__io_out_valid_T_1; // @[Arbiter.scala:154:31]
wire _dataArb_io_in_0_valid_T_12; // @[DCache.scala:516:27]
wire pstore_drain; // @[DCache.scala:516:27]
wire [63:0] _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27]
wire [7:0] _dataArb_io_in_0_bits_eccMask_T_17; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_way_en_T; // @[DCache.scala:550:38]
wire dataArb__io_in_1_ready_T; // @[Arbiter.scala:153:19]
wire dataArb__io_in_2_ready_T; // @[Arbiter.scala:153:19]
wire [10:0] _dataArb_io_in_2_bits_addr_T_4; // @[DCache.scala:903:72]
wire dataArb__io_in_3_ready_T; // @[Arbiter.scala:153:19]
wire _dataArb_io_in_3_valid_T_58; // @[DCache.scala:242:46]
wire dataArb__io_out_valid_T_1; // @[Arbiter.scala:154:31]
wire [10:0] dataArb_io_in_0_bits_addr; // @[DCache.scala:152:28]
wire dataArb_io_in_0_bits_write; // @[DCache.scala:152:28]
wire [63:0] dataArb_io_in_0_bits_wdata; // @[DCache.scala:152:28]
wire dataArb_io_in_0_bits_wordMask; // @[DCache.scala:152:28]
wire [7:0] dataArb_io_in_0_bits_eccMask; // @[DCache.scala:152:28]
wire dataArb_io_in_0_bits_way_en; // @[DCache.scala:152:28]
wire dataArb_io_in_0_valid; // @[DCache.scala:152:28]
wire [10:0] dataArb_io_in_1_bits_addr; // @[DCache.scala:152:28]
wire dataArb_io_in_1_bits_write; // @[DCache.scala:152:28]
wire [63:0] dataArb_io_in_1_bits_wdata; // @[DCache.scala:152:28]
wire dataArb_io_in_1_bits_wordMask; // @[DCache.scala:152:28]
wire [7:0] dataArb_io_in_1_bits_eccMask; // @[DCache.scala:152:28]
wire dataArb_io_in_1_bits_way_en; // @[DCache.scala:152:28]
wire dataArb_io_in_1_ready; // @[DCache.scala:152:28]
wire dataArb_io_in_1_valid; // @[DCache.scala:152:28]
wire [10:0] dataArb_io_in_2_bits_addr; // @[DCache.scala:152:28]
wire [63:0] dataArb_io_in_2_bits_wdata; // @[DCache.scala:152:28]
wire dataArb_io_in_2_ready; // @[DCache.scala:152:28]
wire [10:0] dataArb_io_in_3_bits_addr; // @[DCache.scala:152:28]
wire [63:0] dataArb_io_in_3_bits_wdata; // @[DCache.scala:152:28]
wire dataArb_io_in_3_ready; // @[DCache.scala:152:28]
wire dataArb_io_in_3_valid; // @[DCache.scala:152:28]
wire [10:0] dataArb_io_out_bits_addr; // @[DCache.scala:152:28]
wire dataArb_io_out_bits_write; // @[DCache.scala:152:28]
wire [63:0] dataArb_io_out_bits_wdata; // @[DCache.scala:152:28]
wire dataArb_io_out_bits_wordMask; // @[DCache.scala:152:28]
wire [7:0] dataArb_io_out_bits_eccMask; // @[DCache.scala:152:28]
wire dataArb_io_out_bits_way_en; // @[DCache.scala:152:28]
wire dataArb_io_out_valid; // @[DCache.scala:152:28]
wire [1:0] dataArb_io_chosen; // @[DCache.scala:152:28]
assign dataArb_io_chosen = dataArb_io_in_0_valid ? 2'h0 : {~dataArb_io_in_1_valid, 1'h1}; // @[Arbiter.scala:145:26, :146:17]
assign dataArb_io_out_bits_addr = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_addr : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_addr : dataArb_io_in_3_bits_addr; // @[Arbiter.scala:145:26, :147:19]
assign dataArb_io_out_bits_write = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_write : dataArb_io_in_1_valid & dataArb_io_in_1_bits_write; // @[Arbiter.scala:145:26, :147:19]
assign dataArb_io_out_bits_wdata = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_wdata : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_wdata : dataArb_io_in_3_bits_wdata; // @[Arbiter.scala:145:26, :147:19]
assign dataArb_io_out_bits_wordMask = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_wordMask : ~dataArb_io_in_1_valid | dataArb_io_in_1_bits_wordMask; // @[Arbiter.scala:145:26, :146:17, :147:19]
assign dataArb_io_out_bits_eccMask = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_eccMask : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_eccMask : 8'hFF; // @[Arbiter.scala:145:26, :147:19]
assign dataArb_io_out_bits_way_en = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_way_en : ~dataArb_io_in_1_valid | dataArb_io_in_1_bits_way_en; // @[Arbiter.scala:145:26, :146:17, :147:19]
wire dataArb__grant_T = dataArb_io_in_0_valid | dataArb_io_in_1_valid; // @[Arbiter.scala:45:68]
wire dataArb__grant_T_1 = dataArb__grant_T; // @[Arbiter.scala:45:68]
wire dataArb_grant_1 = ~dataArb_io_in_0_valid; // @[Arbiter.scala:45:78]
assign dataArb__io_in_1_ready_T = dataArb_grant_1; // @[Arbiter.scala:45:78, :153:19]
wire dataArb_grant_2 = ~dataArb__grant_T; // @[Arbiter.scala:45:{68,78}]
assign dataArb__io_in_2_ready_T = dataArb_grant_2; // @[Arbiter.scala:45:78, :153:19]
wire dataArb_grant_3 = ~dataArb__grant_T_1; // @[Arbiter.scala:45:{68,78}]
assign dataArb__io_in_3_ready_T = dataArb_grant_3; // @[Arbiter.scala:45:78, :153:19]
assign dataArb_io_in_1_ready = dataArb__io_in_1_ready_T; // @[Arbiter.scala:153:19]
assign dataArb_io_in_2_ready = dataArb__io_in_2_ready_T; // @[Arbiter.scala:153:19]
assign dataArb_io_in_3_ready = dataArb__io_in_3_ready_T; // @[Arbiter.scala:153:19]
wire dataArb__io_out_valid_T = ~dataArb_grant_3; // @[Arbiter.scala:45:78, :154:19]
assign dataArb__io_out_valid_T_1 = dataArb__io_out_valid_T | dataArb_io_in_3_valid; // @[Arbiter.scala:154:{19,31}]
assign dataArb_io_out_valid = dataArb__io_out_valid_T_1; // @[Arbiter.scala:154:31]
wire _tl_out_a_valid_T_14; // @[DCache.scala:603:37]
assign nodeOut_a_deq_valid = tl_out_a_valid; // @[Decoupled.scala:356:21]
wire [2:0] _tl_out_a_bits_T_9_opcode; // @[DCache.scala:608:23]
assign nodeOut_a_deq_bits_opcode = tl_out_a_bits_opcode; // @[Decoupled.scala:356:21]
wire [2:0] _tl_out_a_bits_T_9_param; // @[DCache.scala:608:23]
assign nodeOut_a_deq_bits_param = tl_out_a_bits_param; // @[Decoupled.scala:356:21]
wire [3:0] _tl_out_a_bits_T_9_size; // @[DCache.scala:608:23]
assign nodeOut_a_deq_bits_size = tl_out_a_bits_size; // @[Decoupled.scala:356:21]
wire [31:0] _tl_out_a_bits_T_9_address; // @[DCache.scala:608:23]
assign nodeOut_a_deq_bits_address = tl_out_a_bits_address; // @[Decoupled.scala:356:21]
wire [7:0] _tl_out_a_bits_T_9_mask; // @[DCache.scala:608:23]
assign nodeOut_a_deq_bits_mask = tl_out_a_bits_mask; // @[Decoupled.scala:356:21]
wire [63:0] _tl_out_a_bits_T_9_data; // @[DCache.scala:608:23]
assign nodeOut_a_deq_bits_data = tl_out_a_bits_data; // @[Decoupled.scala:356:21]
wire tl_out_a_ready; // @[DCache.scala:159:22]
assign tl_out_a_ready = nodeOut_a_deq_ready; // @[Decoupled.scala:356:21]
assign nodeOut_a_valid = nodeOut_a_deq_valid; // @[Decoupled.scala:356:21]
assign nodeOut_a_bits_opcode = nodeOut_a_deq_bits_opcode; // @[Decoupled.scala:356:21]
assign nodeOut_a_bits_param = nodeOut_a_deq_bits_param; // @[Decoupled.scala:356:21]
assign nodeOut_a_bits_size = nodeOut_a_deq_bits_size; // @[Decoupled.scala:356:21]
assign nodeOut_a_bits_address = nodeOut_a_deq_bits_address; // @[Decoupled.scala:356:21]
assign nodeOut_a_bits_mask = nodeOut_a_deq_bits_mask; // @[Decoupled.scala:356:21]
assign nodeOut_a_bits_data = nodeOut_a_deq_bits_data; // @[Decoupled.scala:356:21]
wire _tl_out_c_valid_T_6; // @[DCache.scala:810:117]
wire tl_out_c_valid; // @[Bundles.scala:265:61]
wire _s1_valid_T = io_cpu_req_ready_0 & io_cpu_req_valid_0; // @[Decoupled.scala:51:35]
reg s1_valid; // @[DCache.scala:182:25]
wire _s2_data_en_T = s1_valid; // @[DCache.scala:182:25, :366:23]
wire s1_nack; // @[DCache.scala:185:28]
wire _s1_valid_masked_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37]
wire s1_valid_masked = s1_valid & _s1_valid_masked_T; // @[DCache.scala:182:25, :186:{34,37}]
wire _s1_valid_not_nacked_T = ~s1_nack; // @[DCache.scala:185:28, :187:41]
wire s1_valid_not_nacked = s1_valid & _s1_valid_not_nacked_T; // @[DCache.scala:182:25, :187:{38,41}]
wire _s0_clk_en_T = ~metaArb_io_out_bits_write; // @[DCache.scala:135:28, :190:43]
wire s0_clk_en = metaArb_io_out_valid & _s0_clk_en_T; // @[DCache.scala:135:28, :190:{40,43}]
wire _s1_tlb_req_T = s0_clk_en; // @[DCache.scala:190:40, :208:52]
wire [39:0] _s0_req_addr_T_2; // @[DCache.scala:193:21]
wire [39:0] s0_tlb_req_vaddr = s0_req_addr; // @[DCache.scala:192:24, :199:28]
wire [4:0] s0_tlb_req_cmd = s0_req_cmd; // @[DCache.scala:192:24, :199:28]
wire [1:0] s0_tlb_req_size = s0_req_size; // @[DCache.scala:192:24, :199:28]
wire [1:0] s0_tlb_req_prv = s0_req_dprv; // @[DCache.scala:192:24, :199:28]
wire s0_tlb_req_v = s0_req_dv; // @[DCache.scala:192:24, :199:28]
wire s0_tlb_req_passthrough = s0_req_phys; // @[DCache.scala:192:24, :199:28]
wire [33:0] _s0_req_addr_T = metaArb_io_out_bits_addr[39:6]; // @[DCache.scala:135:28, :193:47]
wire [5:0] _s0_req_addr_T_1 = io_cpu_req_bits_addr_0[5:0]; // @[DCache.scala:101:7, :193:84]
assign _s0_req_addr_T_2 = {_s0_req_addr_T, _s0_req_addr_T_1}; // @[DCache.scala:193:{21,47,84}]
assign s0_req_addr = _s0_req_addr_T_2; // @[DCache.scala:192:24, :193:21]
assign s0_req_phys = ~metaArb_io_in_7_ready | io_cpu_req_bits_phys_0; // @[DCache.scala:101:7, :135:28, :192:24, :195:{9,34,48}]
reg [39:0] s1_req_addr; // @[DCache.scala:196:25]
assign pma_checker_io_req_bits_vaddr = s1_req_addr; // @[DCache.scala:120:32, :196:25]
reg [7:0] s1_req_tag; // @[DCache.scala:196:25]
reg [4:0] s1_req_cmd; // @[DCache.scala:196:25]
assign pma_checker_io_req_bits_cmd = s1_req_cmd; // @[DCache.scala:120:32, :196:25]
reg [1:0] s1_req_size; // @[DCache.scala:196:25]
assign pma_checker_io_req_bits_size = s1_req_size; // @[DCache.scala:120:32, :196:25]
wire [1:0] s1_mask_xwr_size = s1_req_size; // @[DCache.scala:196:25]
reg s1_req_signed; // @[DCache.scala:196:25]
reg [1:0] s1_req_dprv; // @[DCache.scala:196:25]
assign pma_checker_io_req_bits_prv = s1_req_dprv; // @[DCache.scala:120:32, :196:25]
reg s1_req_dv; // @[DCache.scala:196:25]
assign pma_checker_io_req_bits_v = s1_req_dv; // @[DCache.scala:120:32, :196:25]
reg s1_req_phys; // @[DCache.scala:196:25]
reg s1_req_no_resp; // @[DCache.scala:196:25]
reg s1_req_no_xcpt; // @[DCache.scala:196:25]
wire [28:0] _s1_vaddr_T = s1_req_addr[39:11]; // @[DCache.scala:196:25, :197:56]
wire [10:0] _s1_vaddr_T_1 = s1_req_addr[10:0]; // @[DCache.scala:196:25, :197:78]
wire [39:0] s1_vaddr = {_s1_vaddr_T, _s1_vaddr_T_1}; // @[DCache.scala:197:{21,56,78}]
reg [39:0] s1_tlb_req_vaddr; // @[DCache.scala:208:29]
reg s1_tlb_req_passthrough; // @[DCache.scala:208:29]
reg [1:0] s1_tlb_req_size; // @[DCache.scala:208:29]
reg [4:0] s1_tlb_req_cmd; // @[DCache.scala:208:29]
reg [1:0] s1_tlb_req_prv; // @[DCache.scala:208:29]
reg s1_tlb_req_v; // @[DCache.scala:208:29]
wire _GEN_42 = s1_req_cmd == 5'h0; // @[package.scala:16:47]
wire _s1_read_T; // @[package.scala:16:47]
assign _s1_read_T = _GEN_42; // @[package.scala:16:47]
wire _pstore1_rmw_T; // @[package.scala:16:47]
assign _pstore1_rmw_T = _GEN_42; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_1; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_1 = _GEN_42; // @[package.scala:16:47]
wire _GEN_43 = s1_req_cmd == 5'h10; // @[package.scala:16:47]
wire _s1_read_T_1; // @[package.scala:16:47]
assign _s1_read_T_1 = _GEN_43; // @[package.scala:16:47]
wire _pstore1_rmw_T_1; // @[package.scala:16:47]
assign _pstore1_rmw_T_1 = _GEN_43; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_2; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_2 = _GEN_43; // @[package.scala:16:47]
wire _GEN_44 = s1_req_cmd == 5'h6; // @[package.scala:16:47]
wire _s1_read_T_2; // @[package.scala:16:47]
assign _s1_read_T_2 = _GEN_44; // @[package.scala:16:47]
wire _pstore1_rmw_T_2; // @[package.scala:16:47]
assign _pstore1_rmw_T_2 = _GEN_44; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_3; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_3 = _GEN_44; // @[package.scala:16:47]
wire _GEN_45 = s1_req_cmd == 5'h7; // @[package.scala:16:47]
wire _s1_read_T_3; // @[package.scala:16:47]
assign _s1_read_T_3 = _GEN_45; // @[package.scala:16:47]
wire _s1_write_T_3; // @[Consts.scala:90:66]
assign _s1_write_T_3 = _GEN_45; // @[package.scala:16:47]
wire _pstore1_rmw_T_3; // @[package.scala:16:47]
assign _pstore1_rmw_T_3 = _GEN_45; // @[package.scala:16:47]
wire _pstore1_rmw_T_28; // @[Consts.scala:90:66]
assign _pstore1_rmw_T_28 = _GEN_45; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_4; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_4 = _GEN_45; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_29; // @[Consts.scala:90:66]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_29 = _GEN_45; // @[package.scala:16:47]
wire _s1_read_T_4 = _s1_read_T | _s1_read_T_1; // @[package.scala:16:47, :81:59]
wire _s1_read_T_5 = _s1_read_T_4 | _s1_read_T_2; // @[package.scala:16:47, :81:59]
wire _s1_read_T_6 = _s1_read_T_5 | _s1_read_T_3; // @[package.scala:16:47, :81:59]
wire _GEN_46 = s1_req_cmd == 5'h4; // @[package.scala:16:47]
wire _s1_read_T_7; // @[package.scala:16:47]
assign _s1_read_T_7 = _GEN_46; // @[package.scala:16:47]
wire _s1_write_T_5; // @[package.scala:16:47]
assign _s1_write_T_5 = _GEN_46; // @[package.scala:16:47]
wire _pstore1_rmw_T_7; // @[package.scala:16:47]
assign _pstore1_rmw_T_7 = _GEN_46; // @[package.scala:16:47]
wire _pstore1_rmw_T_30; // @[package.scala:16:47]
assign _pstore1_rmw_T_30 = _GEN_46; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_8; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_8 = _GEN_46; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_31; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_31 = _GEN_46; // @[package.scala:16:47]
wire _GEN_47 = s1_req_cmd == 5'h9; // @[package.scala:16:47]
wire _s1_read_T_8; // @[package.scala:16:47]
assign _s1_read_T_8 = _GEN_47; // @[package.scala:16:47]
wire _s1_write_T_6; // @[package.scala:16:47]
assign _s1_write_T_6 = _GEN_47; // @[package.scala:16:47]
wire _pstore1_rmw_T_8; // @[package.scala:16:47]
assign _pstore1_rmw_T_8 = _GEN_47; // @[package.scala:16:47]
wire _pstore1_rmw_T_31; // @[package.scala:16:47]
assign _pstore1_rmw_T_31 = _GEN_47; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_9; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_9 = _GEN_47; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_32; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_32 = _GEN_47; // @[package.scala:16:47]
wire _GEN_48 = s1_req_cmd == 5'hA; // @[package.scala:16:47]
wire _s1_read_T_9; // @[package.scala:16:47]
assign _s1_read_T_9 = _GEN_48; // @[package.scala:16:47]
wire _s1_write_T_7; // @[package.scala:16:47]
assign _s1_write_T_7 = _GEN_48; // @[package.scala:16:47]
wire _pstore1_rmw_T_9; // @[package.scala:16:47]
assign _pstore1_rmw_T_9 = _GEN_48; // @[package.scala:16:47]
wire _pstore1_rmw_T_32; // @[package.scala:16:47]
assign _pstore1_rmw_T_32 = _GEN_48; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_10; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_10 = _GEN_48; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_33; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_33 = _GEN_48; // @[package.scala:16:47]
wire _GEN_49 = s1_req_cmd == 5'hB; // @[package.scala:16:47]
wire _s1_read_T_10; // @[package.scala:16:47]
assign _s1_read_T_10 = _GEN_49; // @[package.scala:16:47]
wire _s1_write_T_8; // @[package.scala:16:47]
assign _s1_write_T_8 = _GEN_49; // @[package.scala:16:47]
wire _pstore1_rmw_T_10; // @[package.scala:16:47]
assign _pstore1_rmw_T_10 = _GEN_49; // @[package.scala:16:47]
wire _pstore1_rmw_T_33; // @[package.scala:16:47]
assign _pstore1_rmw_T_33 = _GEN_49; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_11; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_11 = _GEN_49; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_34; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_34 = _GEN_49; // @[package.scala:16:47]
wire _s1_read_T_11 = _s1_read_T_7 | _s1_read_T_8; // @[package.scala:16:47, :81:59]
wire _s1_read_T_12 = _s1_read_T_11 | _s1_read_T_9; // @[package.scala:16:47, :81:59]
wire _s1_read_T_13 = _s1_read_T_12 | _s1_read_T_10; // @[package.scala:16:47, :81:59]
wire _GEN_50 = s1_req_cmd == 5'h8; // @[package.scala:16:47]
wire _s1_read_T_14; // @[package.scala:16:47]
assign _s1_read_T_14 = _GEN_50; // @[package.scala:16:47]
wire _s1_write_T_12; // @[package.scala:16:47]
assign _s1_write_T_12 = _GEN_50; // @[package.scala:16:47]
wire _pstore1_rmw_T_14; // @[package.scala:16:47]
assign _pstore1_rmw_T_14 = _GEN_50; // @[package.scala:16:47]
wire _pstore1_rmw_T_37; // @[package.scala:16:47]
assign _pstore1_rmw_T_37 = _GEN_50; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_15; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_15 = _GEN_50; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_38; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_38 = _GEN_50; // @[package.scala:16:47]
wire _GEN_51 = s1_req_cmd == 5'hC; // @[package.scala:16:47]
wire _s1_read_T_15; // @[package.scala:16:47]
assign _s1_read_T_15 = _GEN_51; // @[package.scala:16:47]
wire _s1_write_T_13; // @[package.scala:16:47]
assign _s1_write_T_13 = _GEN_51; // @[package.scala:16:47]
wire _pstore1_rmw_T_15; // @[package.scala:16:47]
assign _pstore1_rmw_T_15 = _GEN_51; // @[package.scala:16:47]
wire _pstore1_rmw_T_38; // @[package.scala:16:47]
assign _pstore1_rmw_T_38 = _GEN_51; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_16; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_16 = _GEN_51; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_39; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_39 = _GEN_51; // @[package.scala:16:47]
wire _GEN_52 = s1_req_cmd == 5'hD; // @[package.scala:16:47]
wire _s1_read_T_16; // @[package.scala:16:47]
assign _s1_read_T_16 = _GEN_52; // @[package.scala:16:47]
wire _s1_write_T_14; // @[package.scala:16:47]
assign _s1_write_T_14 = _GEN_52; // @[package.scala:16:47]
wire _pstore1_rmw_T_16; // @[package.scala:16:47]
assign _pstore1_rmw_T_16 = _GEN_52; // @[package.scala:16:47]
wire _pstore1_rmw_T_39; // @[package.scala:16:47]
assign _pstore1_rmw_T_39 = _GEN_52; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_17; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_17 = _GEN_52; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_40; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_40 = _GEN_52; // @[package.scala:16:47]
wire _GEN_53 = s1_req_cmd == 5'hE; // @[package.scala:16:47]
wire _s1_read_T_17; // @[package.scala:16:47]
assign _s1_read_T_17 = _GEN_53; // @[package.scala:16:47]
wire _s1_write_T_15; // @[package.scala:16:47]
assign _s1_write_T_15 = _GEN_53; // @[package.scala:16:47]
wire _pstore1_rmw_T_17; // @[package.scala:16:47]
assign _pstore1_rmw_T_17 = _GEN_53; // @[package.scala:16:47]
wire _pstore1_rmw_T_40; // @[package.scala:16:47]
assign _pstore1_rmw_T_40 = _GEN_53; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_18; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_18 = _GEN_53; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_41; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_41 = _GEN_53; // @[package.scala:16:47]
wire _GEN_54 = s1_req_cmd == 5'hF; // @[package.scala:16:47]
wire _s1_read_T_18; // @[package.scala:16:47]
assign _s1_read_T_18 = _GEN_54; // @[package.scala:16:47]
wire _s1_write_T_16; // @[package.scala:16:47]
assign _s1_write_T_16 = _GEN_54; // @[package.scala:16:47]
wire _pstore1_rmw_T_18; // @[package.scala:16:47]
assign _pstore1_rmw_T_18 = _GEN_54; // @[package.scala:16:47]
wire _pstore1_rmw_T_41; // @[package.scala:16:47]
assign _pstore1_rmw_T_41 = _GEN_54; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_19; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_19 = _GEN_54; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_42; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_42 = _GEN_54; // @[package.scala:16:47]
wire _s1_read_T_19 = _s1_read_T_14 | _s1_read_T_15; // @[package.scala:16:47, :81:59]
wire _s1_read_T_20 = _s1_read_T_19 | _s1_read_T_16; // @[package.scala:16:47, :81:59]
wire _s1_read_T_21 = _s1_read_T_20 | _s1_read_T_17; // @[package.scala:16:47, :81:59]
wire _s1_read_T_22 = _s1_read_T_21 | _s1_read_T_18; // @[package.scala:16:47, :81:59]
wire _s1_read_T_23 = _s1_read_T_13 | _s1_read_T_22; // @[package.scala:81:59]
wire s1_read = _s1_read_T_6 | _s1_read_T_23; // @[package.scala:81:59]
wire _GEN_55 = s1_req_cmd == 5'h1; // @[DCache.scala:196:25]
wire _s1_write_T; // @[Consts.scala:90:32]
assign _s1_write_T = _GEN_55; // @[Consts.scala:90:32]
wire _pstore1_rmw_T_25; // @[Consts.scala:90:32]
assign _pstore1_rmw_T_25 = _GEN_55; // @[Consts.scala:90:32]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_26; // @[Consts.scala:90:32]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_26 = _GEN_55; // @[Consts.scala:90:32]
wire _T_19 = s1_req_cmd == 5'h11; // @[DCache.scala:196:25]
wire _s1_write_T_1; // @[Consts.scala:90:49]
assign _s1_write_T_1 = _T_19; // @[Consts.scala:90:49]
wire _s1_mask_T; // @[DCache.scala:327:32]
assign _s1_mask_T = _T_19; // @[DCache.scala:327:32]
wire _pstore1_rmw_T_26; // @[Consts.scala:90:49]
assign _pstore1_rmw_T_26 = _T_19; // @[Consts.scala:90:49]
wire _pstore1_rmw_T_48; // @[DCache.scala:1191:35]
assign _pstore1_rmw_T_48 = _T_19; // @[DCache.scala:1191:35]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_27; // @[Consts.scala:90:49]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_27 = _T_19; // @[Consts.scala:90:49]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_49; // @[DCache.scala:1191:35]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_49 = _T_19; // @[DCache.scala:1191:35]
wire _s1_write_T_2 = _s1_write_T | _s1_write_T_1; // @[Consts.scala:90:{32,42,49}]
wire _s1_write_T_4 = _s1_write_T_2 | _s1_write_T_3; // @[Consts.scala:90:{42,59,66}]
wire _s1_write_T_9 = _s1_write_T_5 | _s1_write_T_6; // @[package.scala:16:47, :81:59]
wire _s1_write_T_10 = _s1_write_T_9 | _s1_write_T_7; // @[package.scala:16:47, :81:59]
wire _s1_write_T_11 = _s1_write_T_10 | _s1_write_T_8; // @[package.scala:16:47, :81:59]
wire _s1_write_T_17 = _s1_write_T_12 | _s1_write_T_13; // @[package.scala:16:47, :81:59]
wire _s1_write_T_18 = _s1_write_T_17 | _s1_write_T_14; // @[package.scala:16:47, :81:59]
wire _s1_write_T_19 = _s1_write_T_18 | _s1_write_T_15; // @[package.scala:16:47, :81:59]
wire _s1_write_T_20 = _s1_write_T_19 | _s1_write_T_16; // @[package.scala:16:47, :81:59]
wire _s1_write_T_21 = _s1_write_T_11 | _s1_write_T_20; // @[package.scala:81:59]
wire s1_write = _s1_write_T_4 | _s1_write_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire s1_readwrite = s1_read | s1_write; // @[DCache.scala:212:30]
wire _s1_sfence_T = s1_req_cmd == 5'h14; // @[DCache.scala:196:25, :213:30]
wire _GEN_56 = s1_req_cmd == 5'h15; // @[DCache.scala:196:25, :213:57]
wire _s1_sfence_T_1; // @[DCache.scala:213:57]
assign _s1_sfence_T_1 = _GEN_56; // @[DCache.scala:213:57]
wire _tlb_io_sfence_bits_hv_T; // @[DCache.scala:283:39]
assign _tlb_io_sfence_bits_hv_T = _GEN_56; // @[DCache.scala:213:57, :283:39]
wire _s1_sfence_T_2 = _s1_sfence_T | _s1_sfence_T_1; // @[DCache.scala:213:{30,43,57}]
wire _GEN_57 = s1_req_cmd == 5'h16; // @[DCache.scala:196:25, :213:85]
wire _s1_sfence_T_3; // @[DCache.scala:213:85]
assign _s1_sfence_T_3 = _GEN_57; // @[DCache.scala:213:85]
wire _tlb_io_sfence_bits_hg_T; // @[DCache.scala:284:39]
assign _tlb_io_sfence_bits_hg_T = _GEN_57; // @[DCache.scala:213:85, :284:39]
wire s1_sfence = _s1_sfence_T_2 | _s1_sfence_T_3; // @[DCache.scala:213:{43,71,85}]
wire _s1_flush_line_T = s1_req_cmd == 5'h5; // @[DCache.scala:196:25, :214:34]
wire _s1_flush_line_T_1 = s1_req_size[0]; // @[DCache.scala:196:25, :214:64]
wire _tlb_io_sfence_bits_rs1_T = s1_req_size[0]; // @[DCache.scala:196:25, :214:64, :279:40]
wire s1_flush_line = _s1_flush_line_T & _s1_flush_line_T_1; // @[DCache.scala:214:{34,50,64}]
reg s1_flush_valid; // @[DCache.scala:215:27]
reg cached_grant_wait; // @[DCache.scala:223:34]
reg [1:0] refill_way; // @[DCache.scala:229:23]
wire _any_pstore_valid_T; // @[DCache.scala:508:36]
wire any_pstore_valid; // @[DCache.scala:230:30]
assign metaArb_io_in_4_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24]
assign metaArb_io_in_5_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24]
assign metaArb_io_in_6_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24]
assign metaArb_io_in_7_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24]
wire _io_cpu_req_ready_T_1 = ~cached_grant_wait; // @[DCache.scala:223:34, :233:54]
wire _io_cpu_req_ready_T_2 = _io_cpu_req_ready_T_1; // @[DCache.scala:233:{51,54}]
wire _io_cpu_req_ready_T_3 = ~s1_nack; // @[DCache.scala:185:28, :187:41, :233:76]
wire _io_cpu_req_ready_T_4 = _io_cpu_req_ready_T_2 & _io_cpu_req_ready_T_3; // @[DCache.scala:233:{51,73,76}]
reg uncachedInFlight_0; // @[DCache.scala:236:33]
wire _s2_valid_cached_miss_T_2 = uncachedInFlight_0; // @[DCache.scala:236:33, :425:88]
wire _s2_valid_uncached_pending_T_1 = uncachedInFlight_0; // @[DCache.scala:236:33, :430:92]
wire _io_cpu_ordered_T_6 = uncachedInFlight_0; // @[DCache.scala:236:33, :929:142]
wire _io_cpu_store_pending_T_24 = uncachedInFlight_0; // @[DCache.scala:236:33, :930:97]
wire _clock_en_reg_T_22 = uncachedInFlight_0; // @[DCache.scala:236:33, :1072:50]
reg [39:0] uncachedReqs_0_addr; // @[DCache.scala:237:25]
wire [39:0] uncachedResp_addr = uncachedReqs_0_addr; // @[DCache.scala:237:25, :238:30]
reg [7:0] uncachedReqs_0_tag; // @[DCache.scala:237:25]
wire [7:0] uncachedResp_tag = uncachedReqs_0_tag; // @[DCache.scala:237:25, :238:30]
reg [4:0] uncachedReqs_0_cmd; // @[DCache.scala:237:25]
wire [4:0] uncachedResp_cmd = uncachedReqs_0_cmd; // @[DCache.scala:237:25, :238:30]
reg [1:0] uncachedReqs_0_size; // @[DCache.scala:237:25]
wire [1:0] uncachedResp_size = uncachedReqs_0_size; // @[DCache.scala:237:25, :238:30]
reg uncachedReqs_0_signed; // @[DCache.scala:237:25]
wire uncachedResp_signed = uncachedReqs_0_signed; // @[DCache.scala:237:25, :238:30]
reg [1:0] uncachedReqs_0_dprv; // @[DCache.scala:237:25]
wire [1:0] uncachedResp_dprv = uncachedReqs_0_dprv; // @[DCache.scala:237:25, :238:30]
reg uncachedReqs_0_dv; // @[DCache.scala:237:25]
wire uncachedResp_dv = uncachedReqs_0_dv; // @[DCache.scala:237:25, :238:30]
reg uncachedReqs_0_phys; // @[DCache.scala:237:25]
wire uncachedResp_phys = uncachedReqs_0_phys; // @[DCache.scala:237:25, :238:30]
reg uncachedReqs_0_no_resp; // @[DCache.scala:237:25]
wire uncachedResp_no_resp = uncachedReqs_0_no_resp; // @[DCache.scala:237:25, :238:30]
reg uncachedReqs_0_no_alloc; // @[DCache.scala:237:25]
wire uncachedResp_no_alloc = uncachedReqs_0_no_alloc; // @[DCache.scala:237:25, :238:30]
reg uncachedReqs_0_no_xcpt; // @[DCache.scala:237:25]
wire uncachedResp_no_xcpt = uncachedReqs_0_no_xcpt; // @[DCache.scala:237:25, :238:30]
reg [63:0] uncachedReqs_0_data; // @[DCache.scala:237:25]
wire [63:0] uncachedResp_data = uncachedReqs_0_data; // @[DCache.scala:237:25, :238:30]
reg [7:0] uncachedReqs_0_mask; // @[DCache.scala:237:25]
wire [7:0] uncachedResp_mask = uncachedReqs_0_mask; // @[DCache.scala:237:25, :238:30]
wire _GEN_58 = io_cpu_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47]
wire _s0_read_T; // @[package.scala:16:47]
assign _s0_read_T = _GEN_58; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T = _GEN_58; // @[package.scala:16:47]
wire _s1_did_read_T; // @[package.scala:16:47]
assign _s1_did_read_T = _GEN_58; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T = _GEN_58; // @[package.scala:16:47]
wire _GEN_59 = io_cpu_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47]
wire _s0_read_T_1; // @[package.scala:16:47]
assign _s0_read_T_1 = _GEN_59; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_1; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_1 = _GEN_59; // @[package.scala:16:47]
wire _s1_did_read_T_1; // @[package.scala:16:47]
assign _s1_did_read_T_1 = _GEN_59; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_1; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_1 = _GEN_59; // @[package.scala:16:47]
wire _GEN_60 = io_cpu_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47]
wire _s0_read_T_2; // @[package.scala:16:47]
assign _s0_read_T_2 = _GEN_60; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_2; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_2 = _GEN_60; // @[package.scala:16:47]
wire _s1_did_read_T_2; // @[package.scala:16:47]
assign _s1_did_read_T_2 = _GEN_60; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_2; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_2 = _GEN_60; // @[package.scala:16:47]
wire _GEN_61 = io_cpu_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47]
wire _s0_read_T_3; // @[package.scala:16:47]
assign _s0_read_T_3 = _GEN_61; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_3; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_3 = _GEN_61; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_28; // @[Consts.scala:90:66]
assign _dataArb_io_in_3_valid_T_28 = _GEN_61; // @[package.scala:16:47]
wire _s1_did_read_T_3; // @[package.scala:16:47]
assign _s1_did_read_T_3 = _GEN_61; // @[package.scala:16:47]
wire _s1_did_read_T_28; // @[Consts.scala:90:66]
assign _s1_did_read_T_28 = _GEN_61; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_3; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_3 = _GEN_61; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_28; // @[Consts.scala:90:66]
assign _pstore_drain_opportunistic_T_28 = _GEN_61; // @[package.scala:16:47]
wire _s0_read_T_4 = _s0_read_T | _s0_read_T_1; // @[package.scala:16:47, :81:59]
wire _s0_read_T_5 = _s0_read_T_4 | _s0_read_T_2; // @[package.scala:16:47, :81:59]
wire _s0_read_T_6 = _s0_read_T_5 | _s0_read_T_3; // @[package.scala:16:47, :81:59]
wire _GEN_62 = io_cpu_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47]
wire _s0_read_T_7; // @[package.scala:16:47]
assign _s0_read_T_7 = _GEN_62; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_7; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_7 = _GEN_62; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_30; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_30 = _GEN_62; // @[package.scala:16:47]
wire _s1_did_read_T_7; // @[package.scala:16:47]
assign _s1_did_read_T_7 = _GEN_62; // @[package.scala:16:47]
wire _s1_did_read_T_30; // @[package.scala:16:47]
assign _s1_did_read_T_30 = _GEN_62; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_7; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_7 = _GEN_62; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_30; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_30 = _GEN_62; // @[package.scala:16:47]
wire _GEN_63 = io_cpu_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47]
wire _s0_read_T_8; // @[package.scala:16:47]
assign _s0_read_T_8 = _GEN_63; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_8; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_8 = _GEN_63; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_31; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_31 = _GEN_63; // @[package.scala:16:47]
wire _s1_did_read_T_8; // @[package.scala:16:47]
assign _s1_did_read_T_8 = _GEN_63; // @[package.scala:16:47]
wire _s1_did_read_T_31; // @[package.scala:16:47]
assign _s1_did_read_T_31 = _GEN_63; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_8; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_8 = _GEN_63; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_31; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_31 = _GEN_63; // @[package.scala:16:47]
wire _GEN_64 = io_cpu_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47]
wire _s0_read_T_9; // @[package.scala:16:47]
assign _s0_read_T_9 = _GEN_64; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_9; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_9 = _GEN_64; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_32; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_32 = _GEN_64; // @[package.scala:16:47]
wire _s1_did_read_T_9; // @[package.scala:16:47]
assign _s1_did_read_T_9 = _GEN_64; // @[package.scala:16:47]
wire _s1_did_read_T_32; // @[package.scala:16:47]
assign _s1_did_read_T_32 = _GEN_64; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_9; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_9 = _GEN_64; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_32; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_32 = _GEN_64; // @[package.scala:16:47]
wire _GEN_65 = io_cpu_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47]
wire _s0_read_T_10; // @[package.scala:16:47]
assign _s0_read_T_10 = _GEN_65; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_10; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_10 = _GEN_65; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_33; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_33 = _GEN_65; // @[package.scala:16:47]
wire _s1_did_read_T_10; // @[package.scala:16:47]
assign _s1_did_read_T_10 = _GEN_65; // @[package.scala:16:47]
wire _s1_did_read_T_33; // @[package.scala:16:47]
assign _s1_did_read_T_33 = _GEN_65; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_10; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_10 = _GEN_65; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_33; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_33 = _GEN_65; // @[package.scala:16:47]
wire _s0_read_T_11 = _s0_read_T_7 | _s0_read_T_8; // @[package.scala:16:47, :81:59]
wire _s0_read_T_12 = _s0_read_T_11 | _s0_read_T_9; // @[package.scala:16:47, :81:59]
wire _s0_read_T_13 = _s0_read_T_12 | _s0_read_T_10; // @[package.scala:16:47, :81:59]
wire _GEN_66 = io_cpu_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47]
wire _s0_read_T_14; // @[package.scala:16:47]
assign _s0_read_T_14 = _GEN_66; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_14; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_14 = _GEN_66; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_37; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_37 = _GEN_66; // @[package.scala:16:47]
wire _s1_did_read_T_14; // @[package.scala:16:47]
assign _s1_did_read_T_14 = _GEN_66; // @[package.scala:16:47]
wire _s1_did_read_T_37; // @[package.scala:16:47]
assign _s1_did_read_T_37 = _GEN_66; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_14; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_14 = _GEN_66; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_37; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_37 = _GEN_66; // @[package.scala:16:47]
wire _GEN_67 = io_cpu_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47]
wire _s0_read_T_15; // @[package.scala:16:47]
assign _s0_read_T_15 = _GEN_67; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_15; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_15 = _GEN_67; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_38; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_38 = _GEN_67; // @[package.scala:16:47]
wire _s1_did_read_T_15; // @[package.scala:16:47]
assign _s1_did_read_T_15 = _GEN_67; // @[package.scala:16:47]
wire _s1_did_read_T_38; // @[package.scala:16:47]
assign _s1_did_read_T_38 = _GEN_67; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_15; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_15 = _GEN_67; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_38; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_38 = _GEN_67; // @[package.scala:16:47]
wire _GEN_68 = io_cpu_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47]
wire _s0_read_T_16; // @[package.scala:16:47]
assign _s0_read_T_16 = _GEN_68; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_16; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_16 = _GEN_68; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_39; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_39 = _GEN_68; // @[package.scala:16:47]
wire _s1_did_read_T_16; // @[package.scala:16:47]
assign _s1_did_read_T_16 = _GEN_68; // @[package.scala:16:47]
wire _s1_did_read_T_39; // @[package.scala:16:47]
assign _s1_did_read_T_39 = _GEN_68; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_16; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_16 = _GEN_68; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_39; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_39 = _GEN_68; // @[package.scala:16:47]
wire _GEN_69 = io_cpu_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47]
wire _s0_read_T_17; // @[package.scala:16:47]
assign _s0_read_T_17 = _GEN_69; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_17; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_17 = _GEN_69; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_40; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_40 = _GEN_69; // @[package.scala:16:47]
wire _s1_did_read_T_17; // @[package.scala:16:47]
assign _s1_did_read_T_17 = _GEN_69; // @[package.scala:16:47]
wire _s1_did_read_T_40; // @[package.scala:16:47]
assign _s1_did_read_T_40 = _GEN_69; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_17; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_17 = _GEN_69; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_40; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_40 = _GEN_69; // @[package.scala:16:47]
wire _GEN_70 = io_cpu_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47]
wire _s0_read_T_18; // @[package.scala:16:47]
assign _s0_read_T_18 = _GEN_70; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_18; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_18 = _GEN_70; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_41; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_41 = _GEN_70; // @[package.scala:16:47]
wire _s1_did_read_T_18; // @[package.scala:16:47]
assign _s1_did_read_T_18 = _GEN_70; // @[package.scala:16:47]
wire _s1_did_read_T_41; // @[package.scala:16:47]
assign _s1_did_read_T_41 = _GEN_70; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_18; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_18 = _GEN_70; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_41; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_41 = _GEN_70; // @[package.scala:16:47]
wire _s0_read_T_19 = _s0_read_T_14 | _s0_read_T_15; // @[package.scala:16:47, :81:59]
wire _s0_read_T_20 = _s0_read_T_19 | _s0_read_T_16; // @[package.scala:16:47, :81:59]
wire _s0_read_T_21 = _s0_read_T_20 | _s0_read_T_17; // @[package.scala:16:47, :81:59]
wire _s0_read_T_22 = _s0_read_T_21 | _s0_read_T_18; // @[package.scala:16:47, :81:59]
wire _s0_read_T_23 = _s0_read_T_13 | _s0_read_T_22; // @[package.scala:81:59]
wire s0_read = _s0_read_T_6 | _s0_read_T_23; // @[package.scala:81:59]
wire _GEN_71 = io_cpu_req_bits_cmd_0 == 5'h1; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_res_T; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_res_T = _GEN_71; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_25; // @[Consts.scala:90:32]
assign _dataArb_io_in_3_valid_T_25 = _GEN_71; // @[package.scala:16:47]
wire _s1_did_read_T_25; // @[Consts.scala:90:32]
assign _s1_did_read_T_25 = _GEN_71; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_res_T; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_res_T = _GEN_71; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_25; // @[Consts.scala:90:32]
assign _pstore_drain_opportunistic_T_25 = _GEN_71; // @[package.scala:16:47]
wire _GEN_72 = io_cpu_req_bits_cmd_0 == 5'h3; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_res_T_1; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_res_T_1 = _GEN_72; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_res_T_1; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_res_T_1 = _GEN_72; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_res_T_2 = _dataArb_io_in_3_valid_res_T | _dataArb_io_in_3_valid_res_T_1; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_res_T_3 = ~_dataArb_io_in_3_valid_res_T_2; // @[package.scala:81:59]
wire dataArb_io_in_3_valid_res = _dataArb_io_in_3_valid_res_T_3; // @[DCache.scala:1185:{15,46}]
wire _dataArb_io_in_3_valid_T_4 = _dataArb_io_in_3_valid_T | _dataArb_io_in_3_valid_T_1; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_5 = _dataArb_io_in_3_valid_T_4 | _dataArb_io_in_3_valid_T_2; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_6 = _dataArb_io_in_3_valid_T_5 | _dataArb_io_in_3_valid_T_3; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_11 = _dataArb_io_in_3_valid_T_7 | _dataArb_io_in_3_valid_T_8; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_12 = _dataArb_io_in_3_valid_T_11 | _dataArb_io_in_3_valid_T_9; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_13 = _dataArb_io_in_3_valid_T_12 | _dataArb_io_in_3_valid_T_10; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_19 = _dataArb_io_in_3_valid_T_14 | _dataArb_io_in_3_valid_T_15; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_20 = _dataArb_io_in_3_valid_T_19 | _dataArb_io_in_3_valid_T_16; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_21 = _dataArb_io_in_3_valid_T_20 | _dataArb_io_in_3_valid_T_17; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_22 = _dataArb_io_in_3_valid_T_21 | _dataArb_io_in_3_valid_T_18; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_23 = _dataArb_io_in_3_valid_T_13 | _dataArb_io_in_3_valid_T_22; // @[package.scala:81:59]
wire _dataArb_io_in_3_valid_T_24 = _dataArb_io_in_3_valid_T_6 | _dataArb_io_in_3_valid_T_23; // @[package.scala:81:59]
wire _GEN_73 = io_cpu_req_bits_cmd_0 == 5'h11; // @[DCache.scala:101:7]
wire _dataArb_io_in_3_valid_T_26; // @[Consts.scala:90:49]
assign _dataArb_io_in_3_valid_T_26 = _GEN_73; // @[Consts.scala:90:49]
wire _dataArb_io_in_3_valid_T_48; // @[DCache.scala:1191:35]
assign _dataArb_io_in_3_valid_T_48 = _GEN_73; // @[DCache.scala:1191:35]
wire _s1_did_read_T_26; // @[Consts.scala:90:49]
assign _s1_did_read_T_26 = _GEN_73; // @[Consts.scala:90:49]
wire _s1_did_read_T_48; // @[DCache.scala:1191:35]
assign _s1_did_read_T_48 = _GEN_73; // @[DCache.scala:1191:35]
wire _pstore_drain_opportunistic_T_26; // @[Consts.scala:90:49]
assign _pstore_drain_opportunistic_T_26 = _GEN_73; // @[Consts.scala:90:49]
wire _pstore_drain_opportunistic_T_48; // @[DCache.scala:1191:35]
assign _pstore_drain_opportunistic_T_48 = _GEN_73; // @[DCache.scala:1191:35]
wire _dataArb_io_in_3_valid_T_27 = _dataArb_io_in_3_valid_T_25 | _dataArb_io_in_3_valid_T_26; // @[Consts.scala:90:{32,42,49}]
wire _dataArb_io_in_3_valid_T_29 = _dataArb_io_in_3_valid_T_27 | _dataArb_io_in_3_valid_T_28; // @[Consts.scala:90:{42,59,66}]
wire _dataArb_io_in_3_valid_T_34 = _dataArb_io_in_3_valid_T_30 | _dataArb_io_in_3_valid_T_31; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_35 = _dataArb_io_in_3_valid_T_34 | _dataArb_io_in_3_valid_T_32; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_36 = _dataArb_io_in_3_valid_T_35 | _dataArb_io_in_3_valid_T_33; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_42 = _dataArb_io_in_3_valid_T_37 | _dataArb_io_in_3_valid_T_38; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_43 = _dataArb_io_in_3_valid_T_42 | _dataArb_io_in_3_valid_T_39; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_44 = _dataArb_io_in_3_valid_T_43 | _dataArb_io_in_3_valid_T_40; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_45 = _dataArb_io_in_3_valid_T_44 | _dataArb_io_in_3_valid_T_41; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_46 = _dataArb_io_in_3_valid_T_36 | _dataArb_io_in_3_valid_T_45; // @[package.scala:81:59]
wire _dataArb_io_in_3_valid_T_47 = _dataArb_io_in_3_valid_T_29 | _dataArb_io_in_3_valid_T_46; // @[Consts.scala:87:44, :90:{59,76}]
wire _dataArb_io_in_3_valid_T_50 = _dataArb_io_in_3_valid_T_48; // @[DCache.scala:1191:{35,45}]
wire _dataArb_io_in_3_valid_T_51 = _dataArb_io_in_3_valid_T_47 & _dataArb_io_in_3_valid_T_50; // @[DCache.scala:1191:{23,45}]
wire _dataArb_io_in_3_valid_T_52 = _dataArb_io_in_3_valid_T_24 | _dataArb_io_in_3_valid_T_51; // @[DCache.scala:1190:21, :1191:23]
wire _dataArb_io_in_3_valid_T_53 = ~_dataArb_io_in_3_valid_T_52; // @[DCache.scala:1186:12, :1190:21]
wire _dataArb_io_in_3_valid_T_54 = _dataArb_io_in_3_valid_T_53 | dataArb_io_in_3_valid_res; // @[DCache.scala:1185:46, :1186:{12,28}]
wire _dataArb_io_in_3_valid_T_56 = ~_dataArb_io_in_3_valid_T_55; // @[DCache.scala:1186:11]
wire _dataArb_io_in_3_valid_T_57 = ~_dataArb_io_in_3_valid_T_54; // @[DCache.scala:1186:{11,28}]
assign _dataArb_io_in_3_valid_T_58 = io_cpu_req_valid_0 & dataArb_io_in_3_valid_res; // @[DCache.scala:101:7, :242:46, :1185:46]
assign dataArb_io_in_3_valid = _dataArb_io_in_3_valid_T_58; // @[DCache.scala:152:28, :242:46]
wire [28:0] _dataArb_io_in_3_bits_addr_T = io_cpu_req_bits_addr_0[39:11]; // @[DCache.scala:101:7, :245:89]
wire [28:0] _metaArb_io_in_1_bits_addr_T = io_cpu_req_bits_addr_0[39:11]; // @[DCache.scala:101:7, :245:89, :454:58]
wire [28:0] _metaArb_io_in_2_bits_addr_T = io_cpu_req_bits_addr_0[39:11]; // @[DCache.scala:101:7, :245:89, :466:58]
wire [28:0] _metaArb_io_in_3_bits_addr_T = io_cpu_req_bits_addr_0[39:11]; // @[DCache.scala:101:7, :245:89, :745:58]
wire [28:0] _metaArb_io_in_4_bits_addr_T = io_cpu_req_bits_addr_0[39:11]; // @[DCache.scala:101:7, :245:89, :912:58]
wire [28:0] _metaArb_io_in_5_bits_addr_T = io_cpu_req_bits_addr_0[39:11]; // @[DCache.scala:101:7, :245:89, :1018:58]
wire [10:0] _dataArb_io_in_3_bits_addr_T_1 = io_cpu_req_bits_addr_0[10:0]; // @[DCache.scala:101:7, :245:120]
wire [39:0] _dataArb_io_in_3_bits_addr_T_2 = {_dataArb_io_in_3_bits_addr_T, _dataArb_io_in_3_bits_addr_T_1}; // @[DCache.scala:245:{36,89,120}]
assign dataArb_io_in_3_bits_addr = _dataArb_io_in_3_bits_addr_T_2[10:0]; // @[DCache.scala:152:28, :245:{30,36}]
wire _T_4 = ~dataArb_io_in_3_ready & s0_read; // @[DCache.scala:152:28, :258:{9,33}]
wire _s1_did_read_T_4 = _s1_did_read_T | _s1_did_read_T_1; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_5 = _s1_did_read_T_4 | _s1_did_read_T_2; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_6 = _s1_did_read_T_5 | _s1_did_read_T_3; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_11 = _s1_did_read_T_7 | _s1_did_read_T_8; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_12 = _s1_did_read_T_11 | _s1_did_read_T_9; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_13 = _s1_did_read_T_12 | _s1_did_read_T_10; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_19 = _s1_did_read_T_14 | _s1_did_read_T_15; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_20 = _s1_did_read_T_19 | _s1_did_read_T_16; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_21 = _s1_did_read_T_20 | _s1_did_read_T_17; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_22 = _s1_did_read_T_21 | _s1_did_read_T_18; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_23 = _s1_did_read_T_13 | _s1_did_read_T_22; // @[package.scala:81:59]
wire _s1_did_read_T_24 = _s1_did_read_T_6 | _s1_did_read_T_23; // @[package.scala:81:59]
wire _s1_did_read_T_27 = _s1_did_read_T_25 | _s1_did_read_T_26; // @[Consts.scala:90:{32,42,49}]
wire _s1_did_read_T_29 = _s1_did_read_T_27 | _s1_did_read_T_28; // @[Consts.scala:90:{42,59,66}]
wire _s1_did_read_T_34 = _s1_did_read_T_30 | _s1_did_read_T_31; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_35 = _s1_did_read_T_34 | _s1_did_read_T_32; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_36 = _s1_did_read_T_35 | _s1_did_read_T_33; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_42 = _s1_did_read_T_37 | _s1_did_read_T_38; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_43 = _s1_did_read_T_42 | _s1_did_read_T_39; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_44 = _s1_did_read_T_43 | _s1_did_read_T_40; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_45 = _s1_did_read_T_44 | _s1_did_read_T_41; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_46 = _s1_did_read_T_36 | _s1_did_read_T_45; // @[package.scala:81:59]
wire _s1_did_read_T_47 = _s1_did_read_T_29 | _s1_did_read_T_46; // @[Consts.scala:87:44, :90:{59,76}]
wire _s1_did_read_T_50 = _s1_did_read_T_48; // @[DCache.scala:1191:{35,45}]
wire _s1_did_read_T_51 = _s1_did_read_T_47 & _s1_did_read_T_50; // @[DCache.scala:1191:{23,45}]
wire _s1_did_read_T_52 = _s1_did_read_T_24 | _s1_did_read_T_51; // @[DCache.scala:1190:21, :1191:23]
wire _s1_did_read_T_53 = io_cpu_req_valid_0 & _s1_did_read_T_52; // @[DCache.scala:101:7, :259:75, :1190:21]
wire _s1_did_read_T_54 = dataArb_io_in_3_ready & _s1_did_read_T_53; // @[DCache.scala:152:28, :259:{54,75}]
reg s1_did_read; // @[DCache.scala:259:30]
wire _s2_data_word_en_T = s1_did_read; // @[DCache.scala:259:30, :367:63]
assign _metaArb_io_in_7_bits_idx_T = _dataArb_io_in_3_bits_addr_T_2[10:6]; // @[DCache.scala:245:36, :263:58]
assign metaArb_io_in_7_bits_idx = _metaArb_io_in_7_bits_idx_T; // @[DCache.scala:135:28, :263:58]
wire _s1_cmd_uses_tlb_T = s1_readwrite | s1_flush_line; // @[DCache.scala:212:30, :214:50, :270:38]
wire _s1_cmd_uses_tlb_T_1 = s1_req_cmd == 5'h17; // @[DCache.scala:196:25, :270:69]
wire s1_cmd_uses_tlb = _s1_cmd_uses_tlb_T | _s1_cmd_uses_tlb_T_1; // @[DCache.scala:270:{38,55,69}]
wire _tlb_io_req_valid_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37, :273:55]
wire _tlb_io_req_valid_T_1 = s1_valid & _tlb_io_req_valid_T; // @[DCache.scala:182:25, :273:{52,55}]
wire _tlb_io_req_valid_T_2 = _tlb_io_req_valid_T_1 & s1_cmd_uses_tlb; // @[DCache.scala:270:55, :273:{52,71}]
wire _tlb_io_req_valid_T_3 = _tlb_io_req_valid_T_2; // @[DCache.scala:273:{40,71}]
wire _T_10 = ~_tlb_io_req_ready & ~io_ptw_resp_valid_0 & ~io_cpu_req_bits_phys_0; // @[DCache.scala:101:7, :119:19, :275:{9,27,30,53,56}]
wire _tlb_io_sfence_valid_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37, :278:38]
wire _tlb_io_sfence_valid_T_1 = s1_valid & _tlb_io_sfence_valid_T; // @[DCache.scala:182:25, :278:{35,38}]
wire _tlb_io_sfence_valid_T_2 = _tlb_io_sfence_valid_T_1 & s1_sfence; // @[DCache.scala:213:71, :278:{35,54}]
wire _tlb_io_sfence_bits_rs2_T = s1_req_size[1]; // @[DCache.scala:196:25, :280:40]
wire [19:0] _s1_paddr_T = s1_req_addr[31:12]; // @[DCache.scala:196:25, :298:55]
wire [19:0] _s1_paddr_T_1 = _tlb_io_resp_paddr[31:12]; // @[DCache.scala:119:19, :298:99]
wire [19:0] _s1_paddr_T_2 = _s1_paddr_T_1; // @[DCache.scala:298:{25,99}]
wire [11:0] _s1_paddr_T_3 = s1_req_addr[11:0]; // @[DCache.scala:196:25, :298:125]
wire [31:0] s1_paddr = {_s1_paddr_T_2, _s1_paddr_T_3}; // @[DCache.scala:298:{21,25,125}]
wire _baseAddr_T = ~hartIdSinkNodeOptIn; // @[LookupByHartId.scala:18:71]
wire _inScratchpad_T = |(s1_paddr[31:21]); // @[DCache.scala:298:21, :303:35]
wire _inScratchpad_T_3 = s1_paddr < 32'h200800; // @[DCache.scala:298:21, :303:59]
wire s1_hit_way = _inScratchpad_T & _inScratchpad_T_3; // @[DCache.scala:303:{35,47,59}]
wire [1:0] s1_hit_state_state = {2{s1_hit_way}}; // @[DCache.scala:303:47, :304:25]
wire [1:0] s1_data_way; // @[DCache.scala:323:32]
wire [7:0] _tl_d_data_encoded_T = nodeOut_d_bits_data[7:0]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_14 = nodeOut_d_bits_data[7:0]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_1 = nodeOut_d_bits_data[15:8]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_15 = nodeOut_d_bits_data[15:8]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_2 = nodeOut_d_bits_data[23:16]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_16 = nodeOut_d_bits_data[23:16]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_3 = nodeOut_d_bits_data[31:24]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_17 = nodeOut_d_bits_data[31:24]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_4 = nodeOut_d_bits_data[39:32]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_18 = nodeOut_d_bits_data[39:32]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_5 = nodeOut_d_bits_data[47:40]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_19 = nodeOut_d_bits_data[47:40]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_6 = nodeOut_d_bits_data[55:48]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_20 = nodeOut_d_bits_data[55:48]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_7 = nodeOut_d_bits_data[63:56]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_21 = nodeOut_d_bits_data[63:56]; // @[package.scala:211:50]
wire [15:0] tl_d_data_encoded_lo_lo = {_tl_d_data_encoded_T_1, _tl_d_data_encoded_T}; // @[package.scala:45:27, :211:50]
wire [15:0] tl_d_data_encoded_lo_hi = {_tl_d_data_encoded_T_3, _tl_d_data_encoded_T_2}; // @[package.scala:45:27, :211:50]
wire [31:0] tl_d_data_encoded_lo = {tl_d_data_encoded_lo_hi, tl_d_data_encoded_lo_lo}; // @[package.scala:45:27]
wire [15:0] tl_d_data_encoded_hi_lo = {_tl_d_data_encoded_T_5, _tl_d_data_encoded_T_4}; // @[package.scala:45:27, :211:50]
wire [15:0] tl_d_data_encoded_hi_hi = {_tl_d_data_encoded_T_7, _tl_d_data_encoded_T_6}; // @[package.scala:45:27, :211:50]
wire [31:0] tl_d_data_encoded_hi = {tl_d_data_encoded_hi_hi, tl_d_data_encoded_hi_lo}; // @[package.scala:45:27]
wire [63:0] _tl_d_data_encoded_T_8 = {tl_d_data_encoded_hi, tl_d_data_encoded_lo}; // @[package.scala:45:27]
wire [63:0] _tl_d_data_encoded_T_22; // @[package.scala:45:27]
wire [63:0] tl_d_data_encoded; // @[DCache.scala:324:31]
wire [63:0] s1_all_data_ways_1 = tl_d_data_encoded; // @[DCache.scala:324:31, :325:33]
wire [63:0] s2_data_s1_way_words_0_0 = s1_all_data_ways_0; // @[package.scala:211:50]
wire [63:0] s2_data_s1_way_words_1_0 = s1_all_data_ways_1; // @[package.scala:211:50]
wire _s1_mask_xwr_upper_T = s1_req_addr[0]; // @[DCache.scala:196:25]
wire _s1_mask_xwr_lower_T = s1_req_addr[0]; // @[DCache.scala:196:25]
wire _s1_mask_xwr_upper_T_1 = _s1_mask_xwr_upper_T; // @[AMOALU.scala:20:{22,27}]
wire _s1_mask_xwr_upper_T_2 = |s1_mask_xwr_size; // @[AMOALU.scala:11:18, :20:53]
wire _s1_mask_xwr_upper_T_3 = _s1_mask_xwr_upper_T_2; // @[AMOALU.scala:20:{47,53}]
wire s1_mask_xwr_upper = _s1_mask_xwr_upper_T_1 | _s1_mask_xwr_upper_T_3; // @[AMOALU.scala:20:{22,42,47}]
wire s1_mask_xwr_lower = ~_s1_mask_xwr_lower_T; // @[AMOALU.scala:21:{22,27}]
wire [1:0] _s1_mask_xwr_T = {s1_mask_xwr_upper, s1_mask_xwr_lower}; // @[AMOALU.scala:20:42, :21:22, :22:16]
wire _s1_mask_xwr_upper_T_4 = s1_req_addr[1]; // @[DCache.scala:196:25]
wire _s1_mask_xwr_lower_T_1 = s1_req_addr[1]; // @[DCache.scala:196:25]
wire [1:0] _s1_mask_xwr_upper_T_5 = _s1_mask_xwr_upper_T_4 ? _s1_mask_xwr_T : 2'h0; // @[AMOALU.scala:20:{22,27}, :22:16]
wire _s1_mask_xwr_upper_T_6 = s1_mask_xwr_size[1]; // @[AMOALU.scala:11:18, :20:53]
wire [1:0] _s1_mask_xwr_upper_T_7 = {2{_s1_mask_xwr_upper_T_6}}; // @[AMOALU.scala:20:{47,53}]
wire [1:0] s1_mask_xwr_upper_1 = _s1_mask_xwr_upper_T_5 | _s1_mask_xwr_upper_T_7; // @[AMOALU.scala:20:{22,42,47}]
wire [1:0] s1_mask_xwr_lower_1 = _s1_mask_xwr_lower_T_1 ? 2'h0 : _s1_mask_xwr_T; // @[AMOALU.scala:21:{22,27}, :22:16]
wire [3:0] _s1_mask_xwr_T_1 = {s1_mask_xwr_upper_1, s1_mask_xwr_lower_1}; // @[AMOALU.scala:20:42, :21:22, :22:16]
wire _s1_mask_xwr_upper_T_8 = s1_req_addr[2]; // @[DCache.scala:196:25]
wire _s1_mask_xwr_lower_T_2 = s1_req_addr[2]; // @[DCache.scala:196:25]
wire [3:0] _s1_mask_xwr_upper_T_9 = _s1_mask_xwr_upper_T_8 ? _s1_mask_xwr_T_1 : 4'h0; // @[AMOALU.scala:20:{22,27}, :22:16]
wire _s1_mask_xwr_upper_T_10 = &s1_mask_xwr_size; // @[AMOALU.scala:11:18, :20:53]
wire [3:0] _s1_mask_xwr_upper_T_11 = {4{_s1_mask_xwr_upper_T_10}}; // @[AMOALU.scala:20:{47,53}]
wire [3:0] s1_mask_xwr_upper_2 = _s1_mask_xwr_upper_T_9 | _s1_mask_xwr_upper_T_11; // @[AMOALU.scala:20:{22,42,47}]
wire [3:0] s1_mask_xwr_lower_2 = _s1_mask_xwr_lower_T_2 ? 4'h0 : _s1_mask_xwr_T_1; // @[AMOALU.scala:21:{22,27}, :22:16]
wire [7:0] s1_mask_xwr = {s1_mask_xwr_upper_2, s1_mask_xwr_lower_2}; // @[AMOALU.scala:20:42, :21:22, :22:16]
wire [7:0] s1_mask = _s1_mask_T ? io_cpu_s1_data_mask_0 : s1_mask_xwr; // @[DCache.scala:101:7, :327:{20,32}]
wire _s2_valid_T = ~s1_sfence; // @[DCache.scala:213:71, :331:45]
wire _s2_valid_T_1 = s1_valid_masked & _s2_valid_T; // @[DCache.scala:186:34, :331:{42,45}]
reg s2_valid; // @[DCache.scala:331:25]
wire [1:0] _s2_valid_no_xcpt_T = {io_cpu_s2_xcpt_ae_ld_0, io_cpu_s2_xcpt_ae_st_0}; // @[DCache.scala:101:7, :332:54]
wire [1:0] _s2_valid_no_xcpt_T_2 = {io_cpu_s2_xcpt_pf_ld_0, io_cpu_s2_xcpt_pf_st_0}; // @[DCache.scala:101:7, :332:54]
wire [1:0] _s2_valid_no_xcpt_T_3 = {io_cpu_s2_xcpt_ma_ld_0, io_cpu_s2_xcpt_ma_st_0}; // @[DCache.scala:101:7, :332:54]
wire [3:0] s2_valid_no_xcpt_lo = {2'h0, _s2_valid_no_xcpt_T}; // @[DCache.scala:332:54]
wire [3:0] s2_valid_no_xcpt_hi = {_s2_valid_no_xcpt_T_3, _s2_valid_no_xcpt_T_2}; // @[DCache.scala:332:54]
wire [7:0] _s2_valid_no_xcpt_T_4 = {s2_valid_no_xcpt_hi, s2_valid_no_xcpt_lo}; // @[DCache.scala:332:54]
wire _s2_valid_no_xcpt_T_5 = |_s2_valid_no_xcpt_T_4; // @[DCache.scala:332:{54,61}]
wire _s2_valid_no_xcpt_T_6 = ~_s2_valid_no_xcpt_T_5; // @[DCache.scala:332:{38,61}]
wire s2_valid_no_xcpt = s2_valid & _s2_valid_no_xcpt_T_6; // @[DCache.scala:331:25, :332:{35,38}]
wire _s2_not_nacked_in_s1_T = ~s1_nack; // @[DCache.scala:185:28, :187:41, :335:37]
reg s2_not_nacked_in_s1; // @[DCache.scala:335:36]
wire s2_valid_not_nacked_in_s1 = s2_valid & s2_not_nacked_in_s1; // @[DCache.scala:331:25, :335:36, :336:44]
wire s2_valid_masked = s2_valid_no_xcpt & s2_not_nacked_in_s1; // @[DCache.scala:332:35, :335:36, :337:42]
wire s2_valid_not_killed = s2_valid_masked; // @[DCache.scala:337:42, :338:45]
wire _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1 = s2_valid_masked; // @[DCache.scala:337:42, :397:71]
wire _s2_dont_nack_misc_T_1 = s2_valid_masked; // @[DCache.scala:337:42, :441:43]
reg [39:0] s2_req_addr; // @[DCache.scala:339:19]
wire [39:0] _get_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19]
wire [39:0] _put_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19]
wire [39:0] _putpartial_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19]
wire [39:0] _atomics_legal_T_4 = s2_req_addr; // @[DCache.scala:339:19]
wire [39:0] _atomics_legal_T_58 = s2_req_addr; // @[DCache.scala:339:19]
wire [39:0] _atomics_legal_T_112 = s2_req_addr; // @[DCache.scala:339:19]
wire [39:0] _atomics_legal_T_166 = s2_req_addr; // @[DCache.scala:339:19]
wire [39:0] _atomics_legal_T_220 = s2_req_addr; // @[DCache.scala:339:19]
wire [39:0] _atomics_legal_T_274 = s2_req_addr; // @[DCache.scala:339:19]
wire [39:0] _atomics_legal_T_328 = s2_req_addr; // @[DCache.scala:339:19]
wire [39:0] _atomics_legal_T_382 = s2_req_addr; // @[DCache.scala:339:19]
wire [39:0] _atomics_legal_T_436 = s2_req_addr; // @[DCache.scala:339:19]
wire [39:0] _tl_out_a_valid_T_1 = s2_req_addr; // @[DCache.scala:339:19, :606:43]
reg [7:0] s2_req_tag; // @[DCache.scala:339:19]
assign io_cpu_resp_bits_tag_0 = s2_req_tag; // @[DCache.scala:101:7, :339:19]
reg [4:0] s2_req_cmd; // @[DCache.scala:339:19]
assign io_cpu_resp_bits_cmd_0 = s2_req_cmd; // @[DCache.scala:101:7, :339:19]
reg [1:0] s2_req_size; // @[DCache.scala:339:19]
assign io_cpu_resp_bits_size_0 = s2_req_size; // @[DCache.scala:101:7, :339:19]
wire [1:0] size = s2_req_size; // @[DCache.scala:339:19]
reg s2_req_signed; // @[DCache.scala:339:19]
assign io_cpu_resp_bits_signed_0 = s2_req_signed; // @[DCache.scala:101:7, :339:19]
reg [1:0] s2_req_dprv; // @[DCache.scala:339:19]
assign io_cpu_resp_bits_dprv_0 = s2_req_dprv; // @[DCache.scala:101:7, :339:19]
reg s2_req_dv; // @[DCache.scala:339:19]
assign io_cpu_resp_bits_dv_0 = s2_req_dv; // @[DCache.scala:101:7, :339:19]
reg s2_req_phys; // @[DCache.scala:339:19]
reg s2_req_no_resp; // @[DCache.scala:339:19]
reg s2_req_no_alloc; // @[DCache.scala:339:19]
reg s2_req_no_xcpt; // @[DCache.scala:339:19]
reg [63:0] s2_req_data; // @[DCache.scala:339:19]
reg [7:0] s2_req_mask; // @[DCache.scala:339:19]
assign io_cpu_resp_bits_mask_0 = s2_req_mask; // @[DCache.scala:101:7, :339:19]
wire _GEN_74 = s2_req_cmd == 5'h5; // @[DCache.scala:339:19, :340:37]
wire _s2_cmd_flush_all_T; // @[DCache.scala:340:37]
assign _s2_cmd_flush_all_T = _GEN_74; // @[DCache.scala:340:37]
wire _s2_cmd_flush_line_T; // @[DCache.scala:341:38]
assign _s2_cmd_flush_line_T = _GEN_74; // @[DCache.scala:340:37, :341:38]
wire _s2_cmd_flush_all_T_1 = s2_req_size[0]; // @[DCache.scala:339:19, :340:68]
wire _s2_cmd_flush_line_T_1 = s2_req_size[0]; // @[DCache.scala:339:19, :340:68, :341:68]
wire _s2_cmd_flush_all_T_2 = ~_s2_cmd_flush_all_T_1; // @[DCache.scala:340:{56,68}]
wire s2_cmd_flush_all = _s2_cmd_flush_all_T & _s2_cmd_flush_all_T_2; // @[DCache.scala:340:{37,53,56}]
wire s2_cmd_flush_line = _s2_cmd_flush_line_T & _s2_cmd_flush_line_T_1; // @[DCache.scala:341:{38,54,68}]
reg s2_tlb_xcpt_miss; // @[DCache.scala:342:24]
reg [31:0] s2_tlb_xcpt_paddr; // @[DCache.scala:342:24]
reg [39:0] s2_tlb_xcpt_gpa; // @[DCache.scala:342:24]
assign io_cpu_s2_gpa_0 = s2_tlb_xcpt_gpa; // @[DCache.scala:101:7, :342:24]
reg s2_tlb_xcpt_pf_ld; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_pf_st; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_pf_inst; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_ae_ld; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_ae_st; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_ae_inst; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_ma_ld; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_ma_st; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_cacheable; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_must_alloc; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_prefetchable; // @[DCache.scala:342:24]
reg [1:0] s2_tlb_xcpt_size; // @[DCache.scala:342:24]
reg [4:0] s2_tlb_xcpt_cmd; // @[DCache.scala:342:24]
reg s2_pma_miss; // @[DCache.scala:343:19]
reg [31:0] s2_pma_paddr; // @[DCache.scala:343:19]
reg [39:0] s2_pma_gpa; // @[DCache.scala:343:19]
reg s2_pma_pf_ld; // @[DCache.scala:343:19]
reg s2_pma_pf_st; // @[DCache.scala:343:19]
reg s2_pma_pf_inst; // @[DCache.scala:343:19]
reg s2_pma_ae_ld; // @[DCache.scala:343:19]
reg s2_pma_ae_st; // @[DCache.scala:343:19]
reg s2_pma_ae_inst; // @[DCache.scala:343:19]
reg s2_pma_ma_ld; // @[DCache.scala:343:19]
reg s2_pma_ma_st; // @[DCache.scala:343:19]
reg s2_pma_cacheable; // @[DCache.scala:343:19]
reg s2_pma_must_alloc; // @[DCache.scala:343:19]
reg s2_pma_prefetchable; // @[DCache.scala:343:19]
reg [1:0] s2_pma_size; // @[DCache.scala:343:19]
reg [4:0] s2_pma_cmd; // @[DCache.scala:343:19]
reg [39:0] s2_uncached_resp_addr; // @[DCache.scala:344:34]
wire _T_29 = s1_valid_not_nacked | s1_flush_valid; // @[DCache.scala:187:38, :215:27, :345:29]
wire _s2_vaddr_T; // @[DCache.scala:351:62]
assign _s2_vaddr_T = _T_29; // @[DCache.scala:345:29, :351:62]
wire _s1_meta_clk_en_T; // @[DCache.scala:357:44]
assign _s1_meta_clk_en_T = _T_29; // @[DCache.scala:345:29, :357:44]
wire _s2_hit_state_T; // @[DCache.scala:386:66]
assign _s2_hit_state_T = _T_29; // @[DCache.scala:345:29, :386:66]
wire _s2_victim_way_T; // @[DCache.scala:431:77]
assign _s2_victim_way_T = _T_29; // @[DCache.scala:345:29, :431:77]
reg [39:0] s2_vaddr_r; // @[DCache.scala:351:31]
wire [28:0] _s2_vaddr_T_1 = s2_vaddr_r[39:11]; // @[DCache.scala:351:{31,81}]
wire [10:0] _s2_vaddr_T_2 = s2_req_addr[10:0]; // @[DCache.scala:339:19, :351:103]
wire [39:0] s2_vaddr = {_s2_vaddr_T_1, _s2_vaddr_T_2}; // @[DCache.scala:351:{21,81,103}]
wire _s2_read_T = s2_req_cmd == 5'h0; // @[package.scala:16:47]
wire _s2_read_T_1 = s2_req_cmd == 5'h10; // @[package.scala:16:47]
wire _T_110 = s2_req_cmd == 5'h6; // @[package.scala:16:47]
wire _s2_read_T_2; // @[package.scala:16:47]
assign _s2_read_T_2 = _T_110; // @[package.scala:16:47]
wire _r_c_cat_T_48; // @[Consts.scala:91:71]
assign _r_c_cat_T_48 = _T_110; // @[package.scala:16:47]
wire _s2_lr_T; // @[DCache.scala:470:70]
assign _s2_lr_T = _T_110; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_48; // @[Consts.scala:91:71]
assign _metaArb_io_in_3_bits_data_c_cat_T_48 = _T_110; // @[package.scala:16:47]
wire _T_111 = s2_req_cmd == 5'h7; // @[package.scala:16:47]
wire _s2_read_T_3; // @[package.scala:16:47]
assign _s2_read_T_3 = _T_111; // @[package.scala:16:47]
wire _s2_write_T_3; // @[Consts.scala:90:66]
assign _s2_write_T_3 = _T_111; // @[package.scala:16:47]
wire _r_c_cat_T_3; // @[Consts.scala:90:66]
assign _r_c_cat_T_3 = _T_111; // @[package.scala:16:47]
wire _r_c_cat_T_26; // @[Consts.scala:90:66]
assign _r_c_cat_T_26 = _T_111; // @[package.scala:16:47]
wire _s2_sc_T; // @[DCache.scala:471:70]
assign _s2_sc_T = _T_111; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_3; // @[Consts.scala:90:66]
assign _metaArb_io_in_3_bits_data_c_cat_T_3 = _T_111; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_26; // @[Consts.scala:90:66]
assign _metaArb_io_in_3_bits_data_c_cat_T_26 = _T_111; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_3; // @[Consts.scala:90:66]
assign _io_cpu_store_pending_T_3 = _T_111; // @[package.scala:16:47]
wire _s2_read_T_4 = _s2_read_T | _s2_read_T_1; // @[package.scala:16:47, :81:59]
wire _s2_read_T_5 = _s2_read_T_4 | _s2_read_T_2; // @[package.scala:16:47, :81:59]
wire _s2_read_T_6 = _s2_read_T_5 | _s2_read_T_3; // @[package.scala:16:47, :81:59]
wire _GEN_75 = s2_req_cmd == 5'h4; // @[package.scala:16:47]
wire _s2_read_T_7; // @[package.scala:16:47]
assign _s2_read_T_7 = _GEN_75; // @[package.scala:16:47]
wire _s2_write_T_5; // @[package.scala:16:47]
assign _s2_write_T_5 = _GEN_75; // @[package.scala:16:47]
wire _r_c_cat_T_5; // @[package.scala:16:47]
assign _r_c_cat_T_5 = _GEN_75; // @[package.scala:16:47]
wire _r_c_cat_T_28; // @[package.scala:16:47]
assign _r_c_cat_T_28 = _GEN_75; // @[package.scala:16:47]
wire _atomics_T; // @[DCache.scala:587:81]
assign _atomics_T = _GEN_75; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_5; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_5 = _GEN_75; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_28; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_28 = _GEN_75; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_5; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_5 = _GEN_75; // @[package.scala:16:47]
wire _GEN_76 = s2_req_cmd == 5'h9; // @[package.scala:16:47]
wire _s2_read_T_8; // @[package.scala:16:47]
assign _s2_read_T_8 = _GEN_76; // @[package.scala:16:47]
wire _s2_write_T_6; // @[package.scala:16:47]
assign _s2_write_T_6 = _GEN_76; // @[package.scala:16:47]
wire _r_c_cat_T_6; // @[package.scala:16:47]
assign _r_c_cat_T_6 = _GEN_76; // @[package.scala:16:47]
wire _r_c_cat_T_29; // @[package.scala:16:47]
assign _r_c_cat_T_29 = _GEN_76; // @[package.scala:16:47]
wire _atomics_T_2; // @[DCache.scala:587:81]
assign _atomics_T_2 = _GEN_76; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_6; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_6 = _GEN_76; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_29; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_29 = _GEN_76; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_6; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_6 = _GEN_76; // @[package.scala:16:47]
wire _GEN_77 = s2_req_cmd == 5'hA; // @[package.scala:16:47]
wire _s2_read_T_9; // @[package.scala:16:47]
assign _s2_read_T_9 = _GEN_77; // @[package.scala:16:47]
wire _s2_write_T_7; // @[package.scala:16:47]
assign _s2_write_T_7 = _GEN_77; // @[package.scala:16:47]
wire _r_c_cat_T_7; // @[package.scala:16:47]
assign _r_c_cat_T_7 = _GEN_77; // @[package.scala:16:47]
wire _r_c_cat_T_30; // @[package.scala:16:47]
assign _r_c_cat_T_30 = _GEN_77; // @[package.scala:16:47]
wire _atomics_T_4; // @[DCache.scala:587:81]
assign _atomics_T_4 = _GEN_77; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_7; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_7 = _GEN_77; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_30; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_30 = _GEN_77; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_7; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_7 = _GEN_77; // @[package.scala:16:47]
wire _GEN_78 = s2_req_cmd == 5'hB; // @[package.scala:16:47]
wire _s2_read_T_10; // @[package.scala:16:47]
assign _s2_read_T_10 = _GEN_78; // @[package.scala:16:47]
wire _s2_write_T_8; // @[package.scala:16:47]
assign _s2_write_T_8 = _GEN_78; // @[package.scala:16:47]
wire _r_c_cat_T_8; // @[package.scala:16:47]
assign _r_c_cat_T_8 = _GEN_78; // @[package.scala:16:47]
wire _r_c_cat_T_31; // @[package.scala:16:47]
assign _r_c_cat_T_31 = _GEN_78; // @[package.scala:16:47]
wire _atomics_T_6; // @[DCache.scala:587:81]
assign _atomics_T_6 = _GEN_78; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_8; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_8 = _GEN_78; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_31; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_31 = _GEN_78; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_8; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_8 = _GEN_78; // @[package.scala:16:47]
wire _s2_read_T_11 = _s2_read_T_7 | _s2_read_T_8; // @[package.scala:16:47, :81:59]
wire _s2_read_T_12 = _s2_read_T_11 | _s2_read_T_9; // @[package.scala:16:47, :81:59]
wire _s2_read_T_13 = _s2_read_T_12 | _s2_read_T_10; // @[package.scala:16:47, :81:59]
wire _GEN_79 = s2_req_cmd == 5'h8; // @[package.scala:16:47]
wire _s2_read_T_14; // @[package.scala:16:47]
assign _s2_read_T_14 = _GEN_79; // @[package.scala:16:47]
wire _s2_write_T_12; // @[package.scala:16:47]
assign _s2_write_T_12 = _GEN_79; // @[package.scala:16:47]
wire _r_c_cat_T_12; // @[package.scala:16:47]
assign _r_c_cat_T_12 = _GEN_79; // @[package.scala:16:47]
wire _r_c_cat_T_35; // @[package.scala:16:47]
assign _r_c_cat_T_35 = _GEN_79; // @[package.scala:16:47]
wire _atomics_T_8; // @[DCache.scala:587:81]
assign _atomics_T_8 = _GEN_79; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_12; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_12 = _GEN_79; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_35; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_35 = _GEN_79; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_12; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_12 = _GEN_79; // @[package.scala:16:47]
wire _GEN_80 = s2_req_cmd == 5'hC; // @[package.scala:16:47]
wire _s2_read_T_15; // @[package.scala:16:47]
assign _s2_read_T_15 = _GEN_80; // @[package.scala:16:47]
wire _s2_write_T_13; // @[package.scala:16:47]
assign _s2_write_T_13 = _GEN_80; // @[package.scala:16:47]
wire _r_c_cat_T_13; // @[package.scala:16:47]
assign _r_c_cat_T_13 = _GEN_80; // @[package.scala:16:47]
wire _r_c_cat_T_36; // @[package.scala:16:47]
assign _r_c_cat_T_36 = _GEN_80; // @[package.scala:16:47]
wire _atomics_T_10; // @[DCache.scala:587:81]
assign _atomics_T_10 = _GEN_80; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_13; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_13 = _GEN_80; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_36; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_36 = _GEN_80; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_13; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_13 = _GEN_80; // @[package.scala:16:47]
wire _GEN_81 = s2_req_cmd == 5'hD; // @[package.scala:16:47]
wire _s2_read_T_16; // @[package.scala:16:47]
assign _s2_read_T_16 = _GEN_81; // @[package.scala:16:47]
wire _s2_write_T_14; // @[package.scala:16:47]
assign _s2_write_T_14 = _GEN_81; // @[package.scala:16:47]
wire _r_c_cat_T_14; // @[package.scala:16:47]
assign _r_c_cat_T_14 = _GEN_81; // @[package.scala:16:47]
wire _r_c_cat_T_37; // @[package.scala:16:47]
assign _r_c_cat_T_37 = _GEN_81; // @[package.scala:16:47]
wire _atomics_T_12; // @[DCache.scala:587:81]
assign _atomics_T_12 = _GEN_81; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_14; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_14 = _GEN_81; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_37; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_37 = _GEN_81; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_14; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_14 = _GEN_81; // @[package.scala:16:47]
wire _GEN_82 = s2_req_cmd == 5'hE; // @[package.scala:16:47]
wire _s2_read_T_17; // @[package.scala:16:47]
assign _s2_read_T_17 = _GEN_82; // @[package.scala:16:47]
wire _s2_write_T_15; // @[package.scala:16:47]
assign _s2_write_T_15 = _GEN_82; // @[package.scala:16:47]
wire _r_c_cat_T_15; // @[package.scala:16:47]
assign _r_c_cat_T_15 = _GEN_82; // @[package.scala:16:47]
wire _r_c_cat_T_38; // @[package.scala:16:47]
assign _r_c_cat_T_38 = _GEN_82; // @[package.scala:16:47]
wire _atomics_T_14; // @[DCache.scala:587:81]
assign _atomics_T_14 = _GEN_82; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_15; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_15 = _GEN_82; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_38; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_38 = _GEN_82; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_15; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_15 = _GEN_82; // @[package.scala:16:47]
wire _GEN_83 = s2_req_cmd == 5'hF; // @[package.scala:16:47]
wire _s2_read_T_18; // @[package.scala:16:47]
assign _s2_read_T_18 = _GEN_83; // @[package.scala:16:47]
wire _s2_write_T_16; // @[package.scala:16:47]
assign _s2_write_T_16 = _GEN_83; // @[package.scala:16:47]
wire _r_c_cat_T_16; // @[package.scala:16:47]
assign _r_c_cat_T_16 = _GEN_83; // @[package.scala:16:47]
wire _r_c_cat_T_39; // @[package.scala:16:47]
assign _r_c_cat_T_39 = _GEN_83; // @[package.scala:16:47]
wire _atomics_T_16; // @[DCache.scala:587:81]
assign _atomics_T_16 = _GEN_83; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_16; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_16 = _GEN_83; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_39; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_39 = _GEN_83; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_16; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_16 = _GEN_83; // @[package.scala:16:47]
wire _s2_read_T_19 = _s2_read_T_14 | _s2_read_T_15; // @[package.scala:16:47, :81:59]
wire _s2_read_T_20 = _s2_read_T_19 | _s2_read_T_16; // @[package.scala:16:47, :81:59]
wire _s2_read_T_21 = _s2_read_T_20 | _s2_read_T_17; // @[package.scala:16:47, :81:59]
wire _s2_read_T_22 = _s2_read_T_21 | _s2_read_T_18; // @[package.scala:16:47, :81:59]
wire _s2_read_T_23 = _s2_read_T_13 | _s2_read_T_22; // @[package.scala:81:59]
assign s2_read = _s2_read_T_6 | _s2_read_T_23; // @[package.scala:81:59]
assign io_cpu_resp_bits_has_data_0 = s2_read; // @[DCache.scala:101:7]
wire _GEN_84 = s2_req_cmd == 5'h1; // @[DCache.scala:339:19]
wire _s2_write_T; // @[Consts.scala:90:32]
assign _s2_write_T = _GEN_84; // @[Consts.scala:90:32]
wire _r_c_cat_T; // @[Consts.scala:90:32]
assign _r_c_cat_T = _GEN_84; // @[Consts.scala:90:32]
wire _r_c_cat_T_23; // @[Consts.scala:90:32]
assign _r_c_cat_T_23 = _GEN_84; // @[Consts.scala:90:32]
wire _metaArb_io_in_3_bits_data_c_cat_T; // @[Consts.scala:90:32]
assign _metaArb_io_in_3_bits_data_c_cat_T = _GEN_84; // @[Consts.scala:90:32]
wire _metaArb_io_in_3_bits_data_c_cat_T_23; // @[Consts.scala:90:32]
assign _metaArb_io_in_3_bits_data_c_cat_T_23 = _GEN_84; // @[Consts.scala:90:32]
wire _io_cpu_store_pending_T; // @[Consts.scala:90:32]
assign _io_cpu_store_pending_T = _GEN_84; // @[Consts.scala:90:32]
wire _GEN_85 = s2_req_cmd == 5'h11; // @[DCache.scala:339:19]
wire _s2_write_T_1; // @[Consts.scala:90:49]
assign _s2_write_T_1 = _GEN_85; // @[Consts.scala:90:49]
wire _r_c_cat_T_1; // @[Consts.scala:90:49]
assign _r_c_cat_T_1 = _GEN_85; // @[Consts.scala:90:49]
wire _r_c_cat_T_24; // @[Consts.scala:90:49]
assign _r_c_cat_T_24 = _GEN_85; // @[Consts.scala:90:49]
wire _tl_out_a_bits_T_4; // @[DCache.scala:610:20]
assign _tl_out_a_bits_T_4 = _GEN_85; // @[DCache.scala:610:20]
wire _uncachedReqs_0_cmd_T; // @[DCache.scala:637:49]
assign _uncachedReqs_0_cmd_T = _GEN_85; // @[DCache.scala:637:49]
wire _metaArb_io_in_3_bits_data_c_cat_T_1; // @[Consts.scala:90:49]
assign _metaArb_io_in_3_bits_data_c_cat_T_1 = _GEN_85; // @[Consts.scala:90:49]
wire _metaArb_io_in_3_bits_data_c_cat_T_24; // @[Consts.scala:90:49]
assign _metaArb_io_in_3_bits_data_c_cat_T_24 = _GEN_85; // @[Consts.scala:90:49]
wire _io_cpu_store_pending_T_1; // @[Consts.scala:90:49]
assign _io_cpu_store_pending_T_1 = _GEN_85; // @[Consts.scala:90:49]
wire _s2_write_T_2 = _s2_write_T | _s2_write_T_1; // @[Consts.scala:90:{32,42,49}]
wire _s2_write_T_4 = _s2_write_T_2 | _s2_write_T_3; // @[Consts.scala:90:{42,59,66}]
wire _s2_write_T_9 = _s2_write_T_5 | _s2_write_T_6; // @[package.scala:16:47, :81:59]
wire _s2_write_T_10 = _s2_write_T_9 | _s2_write_T_7; // @[package.scala:16:47, :81:59]
wire _s2_write_T_11 = _s2_write_T_10 | _s2_write_T_8; // @[package.scala:16:47, :81:59]
wire _s2_write_T_17 = _s2_write_T_12 | _s2_write_T_13; // @[package.scala:16:47, :81:59]
wire _s2_write_T_18 = _s2_write_T_17 | _s2_write_T_14; // @[package.scala:16:47, :81:59]
wire _s2_write_T_19 = _s2_write_T_18 | _s2_write_T_15; // @[package.scala:16:47, :81:59]
wire _s2_write_T_20 = _s2_write_T_19 | _s2_write_T_16; // @[package.scala:16:47, :81:59]
wire _s2_write_T_21 = _s2_write_T_11 | _s2_write_T_20; // @[package.scala:81:59]
wire s2_write = _s2_write_T_4 | _s2_write_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire s2_readwrite = s2_read | s2_write; // @[DCache.scala:354:30]
reg s2_flush_valid_pre_tag_ecc; // @[DCache.scala:355:43]
wire s2_flush_valid = s2_flush_valid_pre_tag_ecc; // @[DCache.scala:355:43, :363:51]
wire s1_meta_clk_en = _s1_meta_clk_en_T; // @[DCache.scala:357:{44,62}]
wire s2_data_en = _s2_data_en_T | io_cpu_replay_next_0; // @[DCache.scala:101:7, :366:{23,38}]
wire s2_data_word_en = _s2_data_word_en_T; // @[DCache.scala:367:{22,63}]
wire _s2_data_s1_word_en_T = ~io_cpu_replay_next_0; // @[DCache.scala:101:7, :377:28]
wire s2_data_s1_word_en = ~_s2_data_s1_word_en_T | s2_data_word_en; // @[DCache.scala:367:22, :377:{27,28}]
wire _s2_data_T = s2_data_s1_word_en; // @[DCache.scala:377:27, :379:39]
wire [1:0] _s2_data_T_1 = _s2_data_T ? s1_data_way : 2'h0; // @[DCache.scala:323:32, :379:{28,39}]
wire _s2_data_T_2 = _s2_data_T_1[0]; // @[Mux.scala:32:36]
wire _s2_data_T_3 = _s2_data_T_1[1]; // @[Mux.scala:32:36]
wire [63:0] _s2_data_T_4 = _s2_data_T_2 ? s2_data_s1_way_words_0_0 : 64'h0; // @[Mux.scala:30:73, :32:36]
wire [63:0] _s2_data_T_5 = _s2_data_T_3 ? s2_data_s1_way_words_1_0 : 64'h0; // @[Mux.scala:30:73, :32:36]
wire [63:0] _s2_data_T_6 = _s2_data_T_4 | _s2_data_T_5; // @[Mux.scala:30:73]
wire [63:0] _s2_data_WIRE = _s2_data_T_6; // @[Mux.scala:30:73]
reg [63:0] s2_data; // @[DCache.scala:379:18]
reg s2_probe_way; // @[DCache.scala:383:31]
assign releaseWay = s2_probe_way; // @[DCache.scala:232:24, :383:31]
reg [1:0] s2_probe_state_state; // @[DCache.scala:384:33]
reg s2_hit_way; // @[DCache.scala:385:29]
reg [1:0] s2_hit_state_state; // @[DCache.scala:386:31]
wire s2_hit_valid = |s2_hit_state_state; // @[Metadata.scala:50:45]
wire _r_c_cat_T_2 = _r_c_cat_T | _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_4 = _r_c_cat_T_2 | _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_9 = _r_c_cat_T_5 | _r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_10 = _r_c_cat_T_9 | _r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_11 = _r_c_cat_T_10 | _r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_17 = _r_c_cat_T_12 | _r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_18 = _r_c_cat_T_17 | _r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_19 = _r_c_cat_T_18 | _r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_20 = _r_c_cat_T_19 | _r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_21 = _r_c_cat_T_11 | _r_c_cat_T_20; // @[package.scala:81:59]
wire _r_c_cat_T_22 = _r_c_cat_T_4 | _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_25 = _r_c_cat_T_23 | _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_27 = _r_c_cat_T_25 | _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_32 = _r_c_cat_T_28 | _r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_33 = _r_c_cat_T_32 | _r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_34 = _r_c_cat_T_33 | _r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_40 = _r_c_cat_T_35 | _r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_41 = _r_c_cat_T_40 | _r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_42 = _r_c_cat_T_41 | _r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_43 = _r_c_cat_T_42 | _r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_44 = _r_c_cat_T_34 | _r_c_cat_T_43; // @[package.scala:81:59]
wire _r_c_cat_T_45 = _r_c_cat_T_27 | _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_86 = s2_req_cmd == 5'h3; // @[DCache.scala:339:19]
wire _r_c_cat_T_46; // @[Consts.scala:91:54]
assign _r_c_cat_T_46 = _GEN_86; // @[Consts.scala:91:54]
wire _metaArb_io_in_3_bits_data_c_cat_T_46; // @[Consts.scala:91:54]
assign _metaArb_io_in_3_bits_data_c_cat_T_46 = _GEN_86; // @[Consts.scala:91:54]
wire _r_c_cat_T_47 = _r_c_cat_T_45 | _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _r_c_cat_T_49 = _r_c_cat_T_47 | _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r_T = {r_c, s2_hit_state_state}; // @[Metadata.scala:29:18, :58:19]
wire _r_T_25 = _r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r_T_27 = {1'h0, _r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _r_T_28 = _r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r_T_30 = _r_T_28 ? 2'h2 : _r_T_27; // @[Misc.scala:35:36, :49:20]
wire _r_T_31 = _r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r_T_33 = _r_T_31 ? 2'h1 : _r_T_30; // @[Misc.scala:35:36, :49:20]
wire _r_T_34 = _r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r_T_36 = _r_T_34 ? 2'h2 : _r_T_33; // @[Misc.scala:35:36, :49:20]
wire _r_T_37 = _r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r_T_39 = _r_T_37 ? 2'h0 : _r_T_36; // @[Misc.scala:35:36, :49:20]
wire _r_T_40 = _r_T == 4'hE; // @[Misc.scala:49:20]
wire _r_T_41 = _r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_42 = _r_T_40 ? 2'h3 : _r_T_39; // @[Misc.scala:35:36, :49:20]
wire _r_T_43 = &_r_T; // @[Misc.scala:49:20]
wire _r_T_44 = _r_T_43 | _r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_45 = _r_T_43 ? 2'h3 : _r_T_42; // @[Misc.scala:35:36, :49:20]
wire _r_T_46 = _r_T == 4'h6; // @[Misc.scala:49:20]
wire _r_T_47 = _r_T_46 | _r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_48 = _r_T_46 ? 2'h2 : _r_T_45; // @[Misc.scala:35:36, :49:20]
wire _r_T_49 = _r_T == 4'h7; // @[Misc.scala:49:20]
wire _r_T_50 = _r_T_49 | _r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_51 = _r_T_49 ? 2'h3 : _r_T_48; // @[Misc.scala:35:36, :49:20]
wire _r_T_52 = _r_T == 4'h1; // @[Misc.scala:49:20]
wire _r_T_53 = _r_T_52 | _r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_54 = _r_T_52 ? 2'h1 : _r_T_51; // @[Misc.scala:35:36, :49:20]
wire _r_T_55 = _r_T == 4'h2; // @[Misc.scala:49:20]
wire _r_T_56 = _r_T_55 | _r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_57 = _r_T_55 ? 2'h2 : _r_T_54; // @[Misc.scala:35:36, :49:20]
wire _r_T_58 = _r_T == 4'h3; // @[Misc.scala:49:20]
wire s2_hit = _r_T_58 | _r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] s2_grow_param = _r_T_58 ? 2'h3 : _r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] s2_new_hit_state_state = s2_grow_param; // @[Misc.scala:35:36]
wire [1:0] metaArb_io_in_2_bits_data_meta_coh_state = s2_new_hit_state_state; // @[Metadata.scala:160:20]
wire [15:0] s2_data_corrected_lo_lo = s2_data[15:0]; // @[package.scala:45:27]
wire [15:0] s2_data_uncorrected_lo_lo = s2_data[15:0]; // @[package.scala:45:27]
wire [15:0] s2_data_corrected_lo_hi = s2_data[31:16]; // @[package.scala:45:27]
wire [15:0] s2_data_uncorrected_lo_hi = s2_data[31:16]; // @[package.scala:45:27]
wire [31:0] s2_data_corrected_lo = {s2_data_corrected_lo_hi, s2_data_corrected_lo_lo}; // @[package.scala:45:27]
wire [15:0] s2_data_corrected_hi_lo = s2_data[47:32]; // @[package.scala:45:27]
wire [15:0] s2_data_uncorrected_hi_lo = s2_data[47:32]; // @[package.scala:45:27]
wire [15:0] s2_data_corrected_hi_hi = s2_data[63:48]; // @[package.scala:45:27]
wire [15:0] s2_data_uncorrected_hi_hi = s2_data[63:48]; // @[package.scala:45:27]
wire [31:0] s2_data_corrected_hi = {s2_data_corrected_hi_hi, s2_data_corrected_hi_lo}; // @[package.scala:45:27]
wire [63:0] s2_data_corrected = {s2_data_corrected_hi, s2_data_corrected_lo}; // @[package.scala:45:27]
wire [63:0] s2_data_word_corrected = s2_data_corrected; // @[package.scala:45:27]
wire [31:0] s2_data_uncorrected_lo = {s2_data_uncorrected_lo_hi, s2_data_uncorrected_lo_lo}; // @[package.scala:45:27]
wire [31:0] s2_data_uncorrected_hi = {s2_data_uncorrected_hi_hi, s2_data_uncorrected_hi_lo}; // @[package.scala:45:27]
wire [63:0] s2_data_uncorrected = {s2_data_uncorrected_hi, s2_data_uncorrected_lo}; // @[package.scala:45:27]
assign s2_data_word = s2_data_uncorrected; // @[package.scala:45:27]
wire s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1 & s2_hit; // @[Misc.scala:35:9]
wire _s2_valid_hit_pre_data_ecc_and_waw_T = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw & s2_readwrite; // @[DCache.scala:354:30, :397:89, :418:89]
wire s2_valid_hit_pre_data_ecc_and_waw = _s2_valid_hit_pre_data_ecc_and_waw_T; // @[DCache.scala:418:{89,105}]
wire s2_valid_hit_pre_data_ecc = s2_valid_hit_pre_data_ecc_and_waw; // @[DCache.scala:418:105, :420:69]
wire s2_valid_flush_line = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw & s2_cmd_flush_line; // @[DCache.scala:341:54, :397:89, :419:75]
wire _s2_victim_tag_T = s2_valid_flush_line; // @[DCache.scala:419:75, :433:47]
wire s2_valid_hit = s2_valid_hit_pre_data_ecc; // @[DCache.scala:420:69, :422:48]
wire _s2_valid_miss_T = s2_valid_masked & s2_readwrite; // @[DCache.scala:337:42, :354:30, :423:39]
wire _s2_valid_miss_T_2 = _s2_valid_miss_T; // @[DCache.scala:423:{39,55}]
wire _s2_valid_miss_T_3 = ~s2_hit; // @[Misc.scala:35:9]
wire s2_valid_miss = _s2_valid_miss_T_2 & _s2_valid_miss_T_3; // @[DCache.scala:423:{55,73,76}]
wire _s2_uncached_T = ~s2_pma_cacheable; // @[DCache.scala:343:19, :424:21]
wire _s2_uncached_T_1 = ~s2_pma_must_alloc; // @[DCache.scala:343:19, :424:61]
wire _s2_uncached_T_2 = s2_req_no_alloc & _s2_uncached_T_1; // @[DCache.scala:339:19, :424:{58,61}]
wire _s2_uncached_T_3 = ~s2_hit_valid; // @[Metadata.scala:50:45]
wire _s2_uncached_T_4 = _s2_uncached_T_2 & _s2_uncached_T_3; // @[DCache.scala:424:{58,80,83}]
wire s2_uncached = _s2_uncached_T | _s2_uncached_T_4; // @[DCache.scala:424:{21,39,80}]
wire _s2_valid_cached_miss_T = ~s2_uncached; // @[DCache.scala:424:39, :425:47]
wire _s2_valid_cached_miss_T_1 = s2_valid_miss & _s2_valid_cached_miss_T; // @[DCache.scala:423:73, :425:{44,47}]
wire _s2_valid_cached_miss_T_3 = ~_s2_valid_cached_miss_T_2; // @[DCache.scala:425:{63,88}]
wire s2_valid_cached_miss = _s2_valid_cached_miss_T_1 & _s2_valid_cached_miss_T_3; // @[DCache.scala:425:{44,60,63}]
wire _tl_out_a_valid_T_6 = s2_valid_cached_miss; // @[DCache.scala:425:60, :605:29]
wire _s2_want_victimize_T = s2_valid_cached_miss | s2_valid_flush_line; // @[DCache.scala:419:75, :425:60, :427:77]
wire _s2_want_victimize_T_1 = _s2_want_victimize_T; // @[DCache.scala:427:{77,100}]
wire _s2_want_victimize_T_2 = _s2_want_victimize_T_1 | s2_flush_valid; // @[DCache.scala:363:51, :427:{100,123}]
wire _s2_cannot_victimize_T = ~s2_flush_valid; // @[DCache.scala:363:51, :428:29]
wire _s2_valid_uncached_pending_T = s2_valid_miss & s2_uncached; // @[DCache.scala:423:73, :424:39, :430:49]
wire _s2_valid_uncached_pending_T_2 = ~_s2_valid_uncached_pending_T_1; // @[DCache.scala:430:{67,92}]
wire s2_valid_uncached_pending = _s2_valid_uncached_pending_T & _s2_valid_uncached_pending_T_2; // @[DCache.scala:430:{49,64,67}]
wire [1:0] s2_victim_or_hit_way = s2_hit_valid ? {1'h0, s2_hit_way} : 2'h1; // @[Metadata.scala:50:45]
wire [20:0] _s2_victim_tag_T_1 = s2_req_addr[31:11]; // @[DCache.scala:339:19, :433:82]
wire [20:0] s2_victim_tag = _s2_victim_tag_T ? _s2_victim_tag_T_1 : 21'h0; // @[DCache.scala:433:{26,47,82}]
wire [1:0] s2_victim_state_state = s2_hit_valid ? s2_hit_state_state : 2'h0; // @[Metadata.scala:50:45]
wire [3:0] _r_T_59 = {2'h0, s2_probe_state_state}; // @[Metadata.scala:120:19]
wire _r_T_72 = _r_T_59 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _r_T_74 = _r_T_72 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _r_T_76 = _r_T_59 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _r_T_78 = _r_T_76 ? 3'h2 : _r_T_74; // @[Misc.scala:38:36, :56:20]
wire _r_T_80 = _r_T_59 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _r_T_82 = _r_T_80 ? 3'h1 : _r_T_78; // @[Misc.scala:38:36, :56:20]
wire _r_T_84 = _r_T_59 == 4'hB; // @[Misc.scala:56:20]
wire _r_T_85 = _r_T_84; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_86 = _r_T_84 ? 3'h1 : _r_T_82; // @[Misc.scala:38:36, :56:20]
wire _r_T_88 = _r_T_59 == 4'h4; // @[Misc.scala:56:20]
wire _r_T_89 = ~_r_T_88 & _r_T_85; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_90 = _r_T_88 ? 3'h5 : _r_T_86; // @[Misc.scala:38:36, :56:20]
wire _r_T_92 = _r_T_59 == 4'h5; // @[Misc.scala:56:20]
wire _r_T_93 = ~_r_T_92 & _r_T_89; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_94 = _r_T_92 ? 3'h4 : _r_T_90; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_95 = {1'h0, _r_T_92}; // @[Misc.scala:38:63, :56:20]
wire _r_T_96 = _r_T_59 == 4'h6; // @[Misc.scala:56:20]
wire _r_T_97 = ~_r_T_96 & _r_T_93; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_98 = _r_T_96 ? 3'h0 : _r_T_94; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_99 = _r_T_96 ? 2'h1 : _r_T_95; // @[Misc.scala:38:63, :56:20]
wire _r_T_100 = _r_T_59 == 4'h7; // @[Misc.scala:56:20]
wire _r_T_101 = _r_T_100 | _r_T_97; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_102 = _r_T_100 ? 3'h0 : _r_T_98; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_103 = _r_T_100 ? 2'h1 : _r_T_99; // @[Misc.scala:38:63, :56:20]
wire _r_T_104 = _r_T_59 == 4'h0; // @[Misc.scala:56:20]
wire _r_T_105 = ~_r_T_104 & _r_T_101; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_106 = _r_T_104 ? 3'h5 : _r_T_102; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_107 = _r_T_104 ? 2'h0 : _r_T_103; // @[Misc.scala:38:63, :56:20]
wire _r_T_108 = _r_T_59 == 4'h1; // @[Misc.scala:56:20]
wire _r_T_109 = ~_r_T_108 & _r_T_105; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_110 = _r_T_108 ? 3'h4 : _r_T_106; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_111 = _r_T_108 ? 2'h1 : _r_T_107; // @[Misc.scala:38:63, :56:20]
wire _r_T_112 = _r_T_59 == 4'h2; // @[Misc.scala:56:20]
wire _r_T_113 = ~_r_T_112 & _r_T_109; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_114 = _r_T_112 ? 3'h3 : _r_T_110; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_115 = _r_T_112 ? 2'h2 : _r_T_111; // @[Misc.scala:38:63, :56:20]
wire _r_T_116 = _r_T_59 == 4'h3; // @[Misc.scala:56:20]
wire s2_prb_ack_data = _r_T_116 | _r_T_113; // @[Misc.scala:38:9, :56:20]
wire [2:0] s2_report_param = _r_T_116 ? 3'h3 : _r_T_114; // @[Misc.scala:38:36, :56:20]
wire [2:0] cleanReleaseMessage_param = s2_report_param; // @[Misc.scala:38:36]
wire [2:0] dirtyReleaseMessage_param = s2_report_param; // @[Misc.scala:38:36]
wire [1:0] r_3 = _r_T_116 ? 2'h2 : _r_T_115; // @[Misc.scala:38:63, :56:20]
wire [1:0] probeNewCoh_state = r_3; // @[Misc.scala:38:63]
wire [1:0] newCoh_state = probeNewCoh_state; // @[Metadata.scala:160:20]
wire [3:0] _r_T_123 = {2'h2, s2_victim_state_state}; // @[Metadata.scala:120:19]
wire _r_T_136 = _r_T_123 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _r_T_138 = _r_T_136 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _r_T_140 = _r_T_123 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _r_T_142 = _r_T_140 ? 3'h2 : _r_T_138; // @[Misc.scala:38:36, :56:20]
wire _r_T_144 = _r_T_123 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _r_T_146 = _r_T_144 ? 3'h1 : _r_T_142; // @[Misc.scala:38:36, :56:20]
wire _r_T_148 = _r_T_123 == 4'hB; // @[Misc.scala:56:20]
wire _r_T_149 = _r_T_148; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_150 = _r_T_148 ? 3'h1 : _r_T_146; // @[Misc.scala:38:36, :56:20]
wire _r_T_152 = _r_T_123 == 4'h4; // @[Misc.scala:56:20]
wire _r_T_153 = ~_r_T_152 & _r_T_149; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_154 = _r_T_152 ? 3'h5 : _r_T_150; // @[Misc.scala:38:36, :56:20]
wire _r_T_156 = _r_T_123 == 4'h5; // @[Misc.scala:56:20]
wire _r_T_157 = ~_r_T_156 & _r_T_153; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_158 = _r_T_156 ? 3'h4 : _r_T_154; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_159 = {1'h0, _r_T_156}; // @[Misc.scala:38:63, :56:20]
wire _r_T_160 = _r_T_123 == 4'h6; // @[Misc.scala:56:20]
wire _r_T_161 = ~_r_T_160 & _r_T_157; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_162 = _r_T_160 ? 3'h0 : _r_T_158; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_163 = _r_T_160 ? 2'h1 : _r_T_159; // @[Misc.scala:38:63, :56:20]
wire _r_T_164 = _r_T_123 == 4'h7; // @[Misc.scala:56:20]
wire _r_T_165 = _r_T_164 | _r_T_161; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_166 = _r_T_164 ? 3'h0 : _r_T_162; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_167 = _r_T_164 ? 2'h1 : _r_T_163; // @[Misc.scala:38:63, :56:20]
wire _r_T_168 = _r_T_123 == 4'h0; // @[Misc.scala:56:20]
wire _r_T_169 = ~_r_T_168 & _r_T_165; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_170 = _r_T_168 ? 3'h5 : _r_T_166; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_171 = _r_T_168 ? 2'h0 : _r_T_167; // @[Misc.scala:38:63, :56:20]
wire _r_T_172 = _r_T_123 == 4'h1; // @[Misc.scala:56:20]
wire _r_T_173 = ~_r_T_172 & _r_T_169; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_174 = _r_T_172 ? 3'h4 : _r_T_170; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_175 = _r_T_172 ? 2'h1 : _r_T_171; // @[Misc.scala:38:63, :56:20]
wire _r_T_176 = _r_T_123 == 4'h2; // @[Misc.scala:56:20]
wire _r_T_177 = ~_r_T_176 & _r_T_173; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_178 = _r_T_176 ? 3'h3 : _r_T_174; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_179 = _r_T_176 ? 2'h2 : _r_T_175; // @[Misc.scala:38:63, :56:20]
wire _r_T_180 = _r_T_123 == 4'h3; // @[Misc.scala:56:20]
wire s2_victim_dirty = _r_T_180 | _r_T_177; // @[Misc.scala:38:9, :56:20]
wire [2:0] s2_shrink_param = _r_T_180 ? 3'h3 : _r_T_178; // @[Misc.scala:38:36, :56:20]
wire [1:0] r_3_1 = _r_T_180 ? 2'h2 : _r_T_179; // @[Misc.scala:38:63, :56:20]
wire [1:0] voluntaryNewCoh_state = r_3_1; // @[Misc.scala:38:63]
wire _s2_update_meta_T = s2_hit_state_state == s2_new_hit_state_state; // @[Metadata.scala:46:46, :160:20]
wire s2_update_meta = ~_s2_update_meta_T; // @[Metadata.scala:46:46, :47:40]
wire s2_dont_nack_uncached = s2_valid_uncached_pending & tl_out_a_ready; // @[DCache.scala:159:22, :430:64, :440:57]
wire _s2_dont_nack_misc_T_7 = ~s2_hit; // @[Misc.scala:35:9]
wire _s2_dont_nack_misc_T_10 = s2_req_cmd == 5'h17; // @[DCache.scala:339:19, :444:17]
wire _s2_dont_nack_misc_T_11 = _s2_dont_nack_misc_T_10; // @[DCache.scala:443:55, :444:17]
wire s2_dont_nack_misc = _s2_dont_nack_misc_T_1 & _s2_dont_nack_misc_T_11; // @[DCache.scala:441:{43,61}, :443:55]
wire _io_cpu_s2_nack_T = ~s2_dont_nack_uncached; // @[DCache.scala:440:57, :445:41]
wire _io_cpu_s2_nack_T_1 = s2_valid_no_xcpt & _io_cpu_s2_nack_T; // @[DCache.scala:332:35, :445:{38,41}]
wire _io_cpu_s2_nack_T_2 = ~s2_dont_nack_misc; // @[DCache.scala:441:61, :445:67]
wire _io_cpu_s2_nack_T_3 = _io_cpu_s2_nack_T_1 & _io_cpu_s2_nack_T_2; // @[DCache.scala:445:{38,64,67}]
wire _io_cpu_s2_nack_T_4 = ~s2_valid_hit; // @[DCache.scala:422:48, :445:89]
assign _io_cpu_s2_nack_T_5 = _io_cpu_s2_nack_T_3 & _io_cpu_s2_nack_T_4; // @[DCache.scala:445:{64,86,89}]
assign io_cpu_s2_nack_0 = _io_cpu_s2_nack_T_5; // @[DCache.scala:101:7, :445:86]
assign _metaArb_io_in_2_valid_T = s2_valid_hit_pre_data_ecc_and_waw & s2_update_meta; // @[Metadata.scala:47:40]
wire _metaArb_io_in_1_valid_T = s2_valid_masked | s2_flush_valid_pre_tag_ecc; // @[DCache.scala:337:42, :355:43, :450:63]
wire _metaArb_io_in_1_valid_T_1 = _metaArb_io_in_1_valid_T; // @[DCache.scala:450:{63,93}]
wire [4:0] _metaArb_io_in_1_bits_idx_T_1 = s2_vaddr[10:6]; // @[DCache.scala:351:21, :453:76]
assign _metaArb_io_in_2_bits_idx_T = s2_vaddr[10:6]; // @[DCache.scala:351:21, :453:76, :465:40]
assign _metaArb_io_in_3_bits_idx_T = s2_vaddr[10:6]; // @[DCache.scala:351:21, :453:76, :744:40]
assign _metaArb_io_in_1_bits_idx_T_2 = _metaArb_io_in_1_bits_idx_T_1; // @[DCache.scala:453:{35,76}]
assign metaArb_io_in_1_bits_idx = _metaArb_io_in_1_bits_idx_T_2; // @[DCache.scala:135:28, :453:35]
wire [10:0] _metaArb_io_in_1_bits_addr_T_1 = {_metaArb_io_in_1_bits_idx_T_2, 6'h0}; // @[DCache.scala:453:35, :454:98]
assign _metaArb_io_in_1_bits_addr_T_2 = {_metaArb_io_in_1_bits_addr_T, _metaArb_io_in_1_bits_addr_T_1}; // @[DCache.scala:454:{36,58,98}]
assign metaArb_io_in_1_bits_addr = _metaArb_io_in_1_bits_addr_T_2; // @[DCache.scala:135:28, :454:36]
assign metaArb_io_in_2_valid = _metaArb_io_in_2_valid_T; // @[DCache.scala:135:28, :462:63]
assign metaArb_io_in_2_bits_way_en = s2_victim_or_hit_way[0]; // @[DCache.scala:135:28, :432:33, :464:32]
assign metaArb_io_in_2_bits_idx = _metaArb_io_in_2_bits_idx_T; // @[DCache.scala:135:28, :465:40]
wire [10:0] _metaArb_io_in_2_bits_addr_T_1 = s2_vaddr[10:0]; // @[DCache.scala:351:21, :466:80]
wire [10:0] _metaArb_io_in_3_bits_addr_T_1 = s2_vaddr[10:0]; // @[DCache.scala:351:21, :466:80, :745:80]
assign _metaArb_io_in_2_bits_addr_T_2 = {_metaArb_io_in_2_bits_addr_T, _metaArb_io_in_2_bits_addr_T_1}; // @[DCache.scala:466:{36,58,80}]
assign metaArb_io_in_2_bits_addr = _metaArb_io_in_2_bits_addr_T_2; // @[DCache.scala:135:28, :466:36]
wire [28:0] _metaArb_io_in_2_bits_data_T = s2_req_addr[39:11]; // @[DCache.scala:339:19, :467:68]
wire [28:0] _metaArb_io_in_3_bits_data_T = s2_req_addr[39:11]; // @[DCache.scala:339:19, :467:68, :746:68]
wire [20:0] metaArb_io_in_2_bits_data_meta_tag; // @[HellaCache.scala:305:20]
assign metaArb_io_in_2_bits_data_meta_tag = _metaArb_io_in_2_bits_data_T[20:0]; // @[HellaCache.scala:305:20, :306:14]
assign _metaArb_io_in_2_bits_data_T_1 = {metaArb_io_in_2_bits_data_meta_coh_state, metaArb_io_in_2_bits_data_meta_tag}; // @[HellaCache.scala:305:20]
assign metaArb_io_in_2_bits_data = _metaArb_io_in_2_bits_data_T_1; // @[DCache.scala:135:28, :467:97]
reg [6:0] lrscCount; // @[DCache.scala:472:26]
wire lrscValid = |(lrscCount[6:2]); // @[DCache.scala:472:26, :473:29]
wire _lrscBackingOff_T = |lrscCount; // @[DCache.scala:472:26, :474:34]
wire _lrscBackingOff_T_1 = ~lrscValid; // @[DCache.scala:473:29, :474:43]
wire lrscBackingOff = _lrscBackingOff_T & _lrscBackingOff_T_1; // @[DCache.scala:474:{34,40,43}]
reg [33:0] lrscAddr; // @[DCache.scala:475:21]
wire [33:0] _lrscAddrMatch_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49]
wire [33:0] _lrscAddr_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :480:29]
wire [33:0] _acquire_address_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :578:38]
wire [33:0] _tl_out_a_bits_T_1 = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :1210:39]
wire [33:0] _error_addr_T_2 = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :1119:27]
wire [33:0] _io_errors_bus_bits_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :1130:58]
wire lrscAddrMatch = lrscAddr == _lrscAddrMatch_T; // @[DCache.scala:475:21, :476:{32,49}]
wire _s2_sc_fail_T = lrscValid & lrscAddrMatch; // @[DCache.scala:473:29, :476:32, :477:41]
wire _s2_sc_fail_T_1 = ~_s2_sc_fail_T; // @[DCache.scala:477:{29,41}]
wire [6:0] _lrscCount_T = s2_hit ? 7'h4F : 7'h0; // @[Misc.scala:35:9]
wire [7:0] _lrscCount_T_1 = {1'h0, lrscCount} - 8'h1; // @[DCache.scala:472:26, :482:51]
wire [6:0] _lrscCount_T_2 = _lrscCount_T_1[6:0]; // @[DCache.scala:482:51]
wire _s2_correct_T = ~any_pstore_valid; // @[DCache.scala:230:30, :487:37]
wire _s2_correct_T_2 = any_pstore_valid | s2_valid; // @[DCache.scala:230:30, :331:25, :487:84]
reg s2_correct_REG; // @[DCache.scala:487:66]
wire _s2_correct_T_3 = ~s2_correct_REG; // @[DCache.scala:487:{58,66}]
wire _GEN_87 = s1_valid_not_nacked & s1_write; // @[DCache.scala:187:38, :492:63]
wire _pstore1_cmd_T; // @[DCache.scala:492:63]
assign _pstore1_cmd_T = _GEN_87; // @[DCache.scala:492:63]
wire _pstore1_addr_T; // @[DCache.scala:493:62]
assign _pstore1_addr_T = _GEN_87; // @[DCache.scala:492:63, :493:62]
wire _pstore1_data_T; // @[DCache.scala:494:73]
assign _pstore1_data_T = _GEN_87; // @[DCache.scala:492:63, :494:73]
wire _pstore1_way_T; // @[DCache.scala:495:63]
assign _pstore1_way_T = _GEN_87; // @[DCache.scala:492:63, :495:63]
wire _pstore1_mask_T; // @[DCache.scala:496:61]
assign _pstore1_mask_T = _GEN_87; // @[DCache.scala:492:63, :496:61]
wire _pstore1_rmw_T_53; // @[DCache.scala:498:84]
assign _pstore1_rmw_T_53 = _GEN_87; // @[DCache.scala:492:63, :498:84]
reg [4:0] pstore1_cmd; // @[DCache.scala:492:30]
reg [39:0] pstore1_addr; // @[DCache.scala:493:31]
wire [39:0] _pstore2_addr_T = pstore1_addr; // @[DCache.scala:493:31, :524:35]
reg [63:0] pstore1_data; // @[DCache.scala:494:31]
assign io_cpu_resp_bits_store_data_0 = pstore1_data; // @[DCache.scala:101:7, :494:31]
wire [63:0] put_data = pstore1_data; // @[Edges.scala:480:17]
wire [63:0] putpartial_data = pstore1_data; // @[Edges.scala:500:17]
wire [63:0] atomics_a_data = pstore1_data; // @[Edges.scala:534:17]
wire [63:0] atomics_a_1_data = pstore1_data; // @[Edges.scala:534:17]
wire [63:0] atomics_a_2_data = pstore1_data; // @[Edges.scala:534:17]
wire [63:0] atomics_a_3_data = pstore1_data; // @[Edges.scala:534:17]
wire [63:0] atomics_a_4_data = pstore1_data; // @[Edges.scala:517:17]
wire [63:0] atomics_a_5_data = pstore1_data; // @[Edges.scala:517:17]
wire [63:0] atomics_a_6_data = pstore1_data; // @[Edges.scala:517:17]
wire [63:0] atomics_a_7_data = pstore1_data; // @[Edges.scala:517:17]
wire [63:0] atomics_a_8_data = pstore1_data; // @[Edges.scala:517:17]
wire [63:0] _amoalu_io_rhs_T = pstore1_data; // @[DCache.scala:494:31, :986:37]
reg pstore1_way; // @[DCache.scala:495:30]
wire _pstore2_way_T = pstore1_way; // @[DCache.scala:495:30, :525:34]
reg [7:0] pstore1_mask; // @[DCache.scala:496:31]
wire [7:0] pstore2_storegen_mask_mergedMask = pstore1_mask; // @[DCache.scala:496:31, :533:37]
wire [7:0] _amoalu_io_mask_T = pstore1_mask; // @[DCache.scala:496:31, :983:38]
wire [7:0] _pstore1_storegen_data_mask_T = pstore1_mask; // @[DCache.scala:496:31, :990:40]
wire [63:0] _pstore1_storegen_data_T_3; // @[DCache.scala:991:52]
wire [63:0] pstore1_storegen_data; // @[DCache.scala:497:42]
wire _pstore1_rmw_T_4 = _pstore1_rmw_T | _pstore1_rmw_T_1; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_5 = _pstore1_rmw_T_4 | _pstore1_rmw_T_2; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_6 = _pstore1_rmw_T_5 | _pstore1_rmw_T_3; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_11 = _pstore1_rmw_T_7 | _pstore1_rmw_T_8; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_12 = _pstore1_rmw_T_11 | _pstore1_rmw_T_9; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_13 = _pstore1_rmw_T_12 | _pstore1_rmw_T_10; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_19 = _pstore1_rmw_T_14 | _pstore1_rmw_T_15; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_20 = _pstore1_rmw_T_19 | _pstore1_rmw_T_16; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_21 = _pstore1_rmw_T_20 | _pstore1_rmw_T_17; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_22 = _pstore1_rmw_T_21 | _pstore1_rmw_T_18; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_23 = _pstore1_rmw_T_13 | _pstore1_rmw_T_22; // @[package.scala:81:59]
wire _pstore1_rmw_T_24 = _pstore1_rmw_T_6 | _pstore1_rmw_T_23; // @[package.scala:81:59]
wire _pstore1_rmw_T_27 = _pstore1_rmw_T_25 | _pstore1_rmw_T_26; // @[Consts.scala:90:{32,42,49}]
wire _pstore1_rmw_T_29 = _pstore1_rmw_T_27 | _pstore1_rmw_T_28; // @[Consts.scala:90:{42,59,66}]
wire _pstore1_rmw_T_34 = _pstore1_rmw_T_30 | _pstore1_rmw_T_31; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_35 = _pstore1_rmw_T_34 | _pstore1_rmw_T_32; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_36 = _pstore1_rmw_T_35 | _pstore1_rmw_T_33; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_42 = _pstore1_rmw_T_37 | _pstore1_rmw_T_38; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_43 = _pstore1_rmw_T_42 | _pstore1_rmw_T_39; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_44 = _pstore1_rmw_T_43 | _pstore1_rmw_T_40; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_45 = _pstore1_rmw_T_44 | _pstore1_rmw_T_41; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_46 = _pstore1_rmw_T_36 | _pstore1_rmw_T_45; // @[package.scala:81:59]
wire _pstore1_rmw_T_47 = _pstore1_rmw_T_29 | _pstore1_rmw_T_46; // @[Consts.scala:87:44, :90:{59,76}]
wire _pstore1_rmw_T_50 = _pstore1_rmw_T_48; // @[DCache.scala:1191:{35,45}]
wire _pstore1_rmw_T_51 = _pstore1_rmw_T_47 & _pstore1_rmw_T_50; // @[DCache.scala:1191:{23,45}]
wire _pstore1_rmw_T_52 = _pstore1_rmw_T_24 | _pstore1_rmw_T_51; // @[DCache.scala:1190:21, :1191:23]
reg pstore1_rmw_r; // @[DCache.scala:498:44]
wire pstore1_rmw = pstore1_rmw_r; // @[DCache.scala:498:{32,44}]
wire _pstore1_merge_likely_T = s2_valid_not_nacked_in_s1 & s2_write; // @[DCache.scala:336:44, :499:56]
wire _GEN_88 = s2_valid_hit & s2_write; // @[DCache.scala:422:48, :490:46]
wire _pstore1_merge_T; // @[DCache.scala:490:46]
assign _pstore1_merge_T = _GEN_88; // @[DCache.scala:490:46]
wire _pstore1_valid_T; // @[DCache.scala:490:46]
assign _pstore1_valid_T = _GEN_88; // @[DCache.scala:490:46]
wire _pstore1_held_T; // @[DCache.scala:490:46]
assign _pstore1_held_T = _GEN_88; // @[DCache.scala:490:46]
wire _pstore1_merge_T_2 = _pstore1_merge_T; // @[DCache.scala:490:{46,58}]
wire _pstore1_merge_T_4 = _pstore1_merge_T_2; // @[DCache.scala:490:58, :491:48]
reg pstore2_valid; // @[DCache.scala:501:30]
wire _pstore_drain_opportunistic_res_T_2 = _pstore_drain_opportunistic_res_T | _pstore_drain_opportunistic_res_T_1; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_res_T_3 = ~_pstore_drain_opportunistic_res_T_2; // @[package.scala:81:59]
wire pstore_drain_opportunistic_res = _pstore_drain_opportunistic_res_T_3; // @[DCache.scala:1185:{15,46}]
wire _pstore_drain_opportunistic_T_4 = _pstore_drain_opportunistic_T | _pstore_drain_opportunistic_T_1; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_5 = _pstore_drain_opportunistic_T_4 | _pstore_drain_opportunistic_T_2; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_6 = _pstore_drain_opportunistic_T_5 | _pstore_drain_opportunistic_T_3; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_11 = _pstore_drain_opportunistic_T_7 | _pstore_drain_opportunistic_T_8; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_12 = _pstore_drain_opportunistic_T_11 | _pstore_drain_opportunistic_T_9; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_13 = _pstore_drain_opportunistic_T_12 | _pstore_drain_opportunistic_T_10; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_19 = _pstore_drain_opportunistic_T_14 | _pstore_drain_opportunistic_T_15; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_20 = _pstore_drain_opportunistic_T_19 | _pstore_drain_opportunistic_T_16; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_21 = _pstore_drain_opportunistic_T_20 | _pstore_drain_opportunistic_T_17; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_22 = _pstore_drain_opportunistic_T_21 | _pstore_drain_opportunistic_T_18; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_23 = _pstore_drain_opportunistic_T_13 | _pstore_drain_opportunistic_T_22; // @[package.scala:81:59]
wire _pstore_drain_opportunistic_T_24 = _pstore_drain_opportunistic_T_6 | _pstore_drain_opportunistic_T_23; // @[package.scala:81:59]
wire _pstore_drain_opportunistic_T_27 = _pstore_drain_opportunistic_T_25 | _pstore_drain_opportunistic_T_26; // @[Consts.scala:90:{32,42,49}]
wire _pstore_drain_opportunistic_T_29 = _pstore_drain_opportunistic_T_27 | _pstore_drain_opportunistic_T_28; // @[Consts.scala:90:{42,59,66}]
wire _pstore_drain_opportunistic_T_34 = _pstore_drain_opportunistic_T_30 | _pstore_drain_opportunistic_T_31; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_35 = _pstore_drain_opportunistic_T_34 | _pstore_drain_opportunistic_T_32; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_36 = _pstore_drain_opportunistic_T_35 | _pstore_drain_opportunistic_T_33; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_42 = _pstore_drain_opportunistic_T_37 | _pstore_drain_opportunistic_T_38; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_43 = _pstore_drain_opportunistic_T_42 | _pstore_drain_opportunistic_T_39; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_44 = _pstore_drain_opportunistic_T_43 | _pstore_drain_opportunistic_T_40; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_45 = _pstore_drain_opportunistic_T_44 | _pstore_drain_opportunistic_T_41; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_46 = _pstore_drain_opportunistic_T_36 | _pstore_drain_opportunistic_T_45; // @[package.scala:81:59]
wire _pstore_drain_opportunistic_T_47 = _pstore_drain_opportunistic_T_29 | _pstore_drain_opportunistic_T_46; // @[Consts.scala:87:44, :90:{59,76}]
wire _pstore_drain_opportunistic_T_50 = _pstore_drain_opportunistic_T_48; // @[DCache.scala:1191:{35,45}]
wire _pstore_drain_opportunistic_T_51 = _pstore_drain_opportunistic_T_47 & _pstore_drain_opportunistic_T_50; // @[DCache.scala:1191:{23,45}]
wire _pstore_drain_opportunistic_T_52 = _pstore_drain_opportunistic_T_24 | _pstore_drain_opportunistic_T_51; // @[DCache.scala:1190:21, :1191:23]
wire _pstore_drain_opportunistic_T_53 = ~_pstore_drain_opportunistic_T_52; // @[DCache.scala:1186:12, :1190:21]
wire _pstore_drain_opportunistic_T_54 = _pstore_drain_opportunistic_T_53 | pstore_drain_opportunistic_res; // @[DCache.scala:1185:46, :1186:{12,28}]
wire _pstore_drain_opportunistic_T_56 = ~_pstore_drain_opportunistic_T_55; // @[DCache.scala:1186:11]
wire _pstore_drain_opportunistic_T_57 = ~_pstore_drain_opportunistic_T_54; // @[DCache.scala:1186:{11,28}]
wire _pstore_drain_opportunistic_T_58 = io_cpu_req_valid_0 & pstore_drain_opportunistic_res; // @[DCache.scala:101:7, :502:55, :1185:46]
wire _pstore_drain_opportunistic_T_59 = ~_pstore_drain_opportunistic_T_58; // @[DCache.scala:502:{36,55}]
wire pstore_drain_opportunistic = _pstore_drain_opportunistic_T_59; // @[DCache.scala:502:{36,92}]
reg pstore_drain_on_miss_REG; // @[DCache.scala:503:56]
wire pstore_drain_on_miss = pstore_drain_on_miss_REG; // @[DCache.scala:503:{46,56}]
reg pstore1_held; // @[DCache.scala:504:29]
wire _GEN_89 = s2_valid & s2_write; // @[DCache.scala:331:25, :505:39]
wire _pstore1_valid_likely_T; // @[DCache.scala:505:39]
assign _pstore1_valid_likely_T = _GEN_89; // @[DCache.scala:505:39]
wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_1; // @[DCache.scala:1082:16]
assign _io_cpu_perf_storeBufferEmptyAfterLoad_T_1 = _GEN_89; // @[DCache.scala:505:39, :1082:16]
wire _io_cpu_perf_storeBufferEmptyAfterStore_T_1; // @[DCache.scala:1086:15]
assign _io_cpu_perf_storeBufferEmptyAfterStore_T_1 = _GEN_89; // @[DCache.scala:505:39, :1086:15]
wire _io_cpu_perf_storeBufferEmptyAfterStore_T_4; // @[DCache.scala:1087:16]
assign _io_cpu_perf_storeBufferEmptyAfterStore_T_4 = _GEN_89; // @[DCache.scala:505:39, :1087:16]
wire _io_cpu_perf_canAcceptStoreThenLoad_T; // @[DCache.scala:1089:16]
assign _io_cpu_perf_canAcceptStoreThenLoad_T = _GEN_89; // @[DCache.scala:505:39, :1089:16]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_55; // @[DCache.scala:1092:100]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_55 = _GEN_89; // @[DCache.scala:505:39, :1092:100]
wire pstore1_valid_likely = _pstore1_valid_likely_T | pstore1_held; // @[DCache.scala:504:29, :505:{39,51}]
wire _pstore1_valid_T_2 = _pstore1_valid_T; // @[DCache.scala:490:{46,58}]
wire _pstore1_valid_T_4 = _pstore1_valid_T_2; // @[DCache.scala:490:58, :491:48]
wire pstore1_valid = _pstore1_valid_T_4 | pstore1_held; // @[DCache.scala:491:48, :504:29, :507:38]
wire _advance_pstore1_T = pstore1_valid; // @[DCache.scala:507:38, :522:40]
assign _any_pstore_valid_T = pstore1_held | pstore2_valid; // @[DCache.scala:501:30, :504:29, :508:36]
assign any_pstore_valid = _any_pstore_valid_T; // @[DCache.scala:230:30, :508:36]
wire _GEN_90 = pstore1_valid_likely & pstore2_valid; // @[DCache.scala:501:30, :505:51, :509:54]
wire _pstore_drain_structural_T; // @[DCache.scala:509:54]
assign _pstore_drain_structural_T = _GEN_90; // @[DCache.scala:509:54]
wire _io_cpu_perf_canAcceptStoreThenLoad_T_6; // @[DCache.scala:1090:20]
assign _io_cpu_perf_canAcceptStoreThenLoad_T_6 = _GEN_90; // @[DCache.scala:509:54, :1090:20]
wire _GEN_91 = s1_valid & s1_write; // @[DCache.scala:182:25, :509:85]
wire _pstore_drain_structural_T_1; // @[DCache.scala:509:85]
assign _pstore_drain_structural_T_1 = _GEN_91; // @[DCache.scala:509:85]
wire _io_cpu_perf_storeBufferEmptyAfterLoad_T; // @[DCache.scala:1081:15]
assign _io_cpu_perf_storeBufferEmptyAfterLoad_T = _GEN_91; // @[DCache.scala:509:85, :1081:15]
wire _io_cpu_perf_storeBufferEmptyAfterStore_T; // @[DCache.scala:1085:15]
assign _io_cpu_perf_storeBufferEmptyAfterStore_T = _GEN_91; // @[DCache.scala:509:85, :1085:15]
wire _io_cpu_perf_canAcceptStoreThenLoad_T_2; // @[DCache.scala:1089:57]
assign _io_cpu_perf_canAcceptStoreThenLoad_T_2 = _GEN_91; // @[DCache.scala:509:85, :1089:57]
wire _io_cpu_perf_canAcceptStoreThenLoad_T_7; // @[DCache.scala:1090:57]
assign _io_cpu_perf_canAcceptStoreThenLoad_T_7 = _GEN_91; // @[DCache.scala:509:85, :1090:57]
wire _io_cpu_perf_canAcceptLoadThenLoad_T; // @[DCache.scala:1092:52]
assign _io_cpu_perf_canAcceptLoadThenLoad_T = _GEN_91; // @[DCache.scala:509:85, :1092:52]
wire _pstore_drain_structural_T_2 = _pstore_drain_structural_T_1 | pstore1_rmw; // @[DCache.scala:498:32, :509:{85,98}]
wire pstore_drain_structural = _pstore_drain_structural_T & _pstore_drain_structural_T_2; // @[DCache.scala:509:{54,71,98}]
wire _pstore_drain_T_1 = pstore_drain_structural; // @[DCache.scala:509:71, :517:17]
wire _dataArb_io_in_0_valid_T_1 = pstore_drain_structural; // @[DCache.scala:509:71, :517:17]
wire _T_48 = s2_valid_hit_pre_data_ecc & s2_write; // @[DCache.scala:420:69, :506:72]
wire _pstore_drain_T_2; // @[DCache.scala:506:72]
assign _pstore_drain_T_2 = _T_48; // @[DCache.scala:506:72]
wire _dataArb_io_in_0_valid_T_2; // @[DCache.scala:506:72]
assign _dataArb_io_in_0_valid_T_2 = _T_48; // @[DCache.scala:506:72]
wire _pstore_drain_T_4 = _pstore_drain_T_2; // @[DCache.scala:506:{72,84}]
wire _pstore_drain_T_5 = _pstore_drain_T_4 | pstore1_held; // @[DCache.scala:504:29, :506:{84,96}]
wire _pstore_drain_T_6 = ~pstore1_rmw; // @[DCache.scala:498:32, :518:44]
wire _pstore_drain_T_7 = _pstore_drain_T_5 & _pstore_drain_T_6; // @[DCache.scala:506:96, :518:{41,44}]
wire _pstore_drain_T_8 = _pstore_drain_T_7 | pstore2_valid; // @[DCache.scala:501:30, :518:{41,58}]
wire _GEN_92 = pstore_drain_opportunistic | pstore_drain_on_miss; // @[DCache.scala:502:92, :503:46, :518:107]
wire _pstore_drain_T_9; // @[DCache.scala:518:107]
assign _pstore_drain_T_9 = _GEN_92; // @[DCache.scala:518:107]
wire _dataArb_io_in_0_valid_T_9; // @[DCache.scala:518:107]
assign _dataArb_io_in_0_valid_T_9 = _GEN_92; // @[DCache.scala:518:107]
wire _pstore_drain_T_10 = _pstore_drain_T_8 & _pstore_drain_T_9; // @[DCache.scala:518:{58,76,107}]
wire _pstore_drain_T_11 = _pstore_drain_T_1 | _pstore_drain_T_10; // @[DCache.scala:517:{17,44}, :518:76]
assign pstore_drain = _pstore_drain_T_11; // @[DCache.scala:516:27, :517:44]
assign dataArb_io_in_0_bits_write = pstore_drain; // @[DCache.scala:152:28, :516:27]
wire _pstore1_held_T_2 = _pstore1_held_T; // @[DCache.scala:490:{46,58}]
wire _pstore1_held_T_4 = _pstore1_held_T_2; // @[DCache.scala:490:58, :491:48]
wire _pstore1_held_T_6 = _pstore1_held_T_4; // @[DCache.scala:491:48, :521:35]
wire _pstore1_held_T_7 = _pstore1_held_T_6 | pstore1_held; // @[DCache.scala:504:29, :521:{35,54}]
wire _pstore1_held_T_8 = _pstore1_held_T_7 & pstore2_valid; // @[DCache.scala:501:30, :521:{54,71}]
wire _pstore1_held_T_9 = ~pstore_drain; // @[DCache.scala:516:27, :521:91]
wire _pstore1_held_T_10 = _pstore1_held_T_8 & _pstore1_held_T_9; // @[DCache.scala:521:{71,88,91}]
wire _advance_pstore1_T_1 = pstore2_valid == pstore_drain; // @[DCache.scala:501:30, :516:27, :522:79]
wire advance_pstore1 = _advance_pstore1_T & _advance_pstore1_T_1; // @[DCache.scala:522:{40,61,79}]
wire _pstore2_storegen_data_T_3 = advance_pstore1; // @[DCache.scala:522:61, :528:78]
wire _pstore2_storegen_data_T_7 = advance_pstore1; // @[DCache.scala:522:61, :528:78]
wire _pstore2_storegen_data_T_11 = advance_pstore1; // @[DCache.scala:522:61, :528:78]
wire _pstore2_storegen_data_T_15 = advance_pstore1; // @[DCache.scala:522:61, :528:78]
wire _pstore2_storegen_data_T_19 = advance_pstore1; // @[DCache.scala:522:61, :528:78]
wire _pstore2_storegen_data_T_23 = advance_pstore1; // @[DCache.scala:522:61, :528:78]
wire _pstore2_storegen_data_T_27 = advance_pstore1; // @[DCache.scala:522:61, :528:78]
wire _pstore2_storegen_data_T_31 = advance_pstore1; // @[DCache.scala:522:61, :528:78]
wire _pstore2_storegen_mask_T = advance_pstore1; // @[DCache.scala:522:61, :532:27]
wire _pstore2_valid_T = ~pstore_drain; // @[DCache.scala:516:27, :521:91, :523:37]
wire _pstore2_valid_T_1 = pstore2_valid & _pstore2_valid_T; // @[DCache.scala:501:30, :523:{34,37}]
wire _pstore2_valid_T_2 = _pstore2_valid_T_1 | advance_pstore1; // @[DCache.scala:522:61, :523:{34,51}]
reg [39:0] pstore2_addr; // @[DCache.scala:524:31]
reg pstore2_way; // @[DCache.scala:525:30]
wire [7:0] _pstore2_storegen_data_T = pstore1_storegen_data[7:0]; // @[DCache.scala:497:42, :528:44]
wire _pstore2_storegen_data_T_1 = pstore1_mask[0]; // @[DCache.scala:496:31, :528:110]
wire _s1_hazard_T_3 = pstore1_mask[0]; // @[package.scala:211:50]
reg [7:0] pstore2_storegen_data_r; // @[DCache.scala:528:22]
wire [7:0] _pstore2_storegen_data_T_4 = pstore1_storegen_data[15:8]; // @[DCache.scala:497:42, :528:44]
wire _pstore2_storegen_data_T_5 = pstore1_mask[1]; // @[DCache.scala:496:31, :528:110]
wire _s1_hazard_T_4 = pstore1_mask[1]; // @[package.scala:211:50]
reg [7:0] pstore2_storegen_data_r_1; // @[DCache.scala:528:22]
wire [7:0] _pstore2_storegen_data_T_8 = pstore1_storegen_data[23:16]; // @[DCache.scala:497:42, :528:44]
wire _pstore2_storegen_data_T_9 = pstore1_mask[2]; // @[DCache.scala:496:31, :528:110]
wire _s1_hazard_T_5 = pstore1_mask[2]; // @[package.scala:211:50]
reg [7:0] pstore2_storegen_data_r_2; // @[DCache.scala:528:22]
wire [7:0] _pstore2_storegen_data_T_12 = pstore1_storegen_data[31:24]; // @[DCache.scala:497:42, :528:44]
wire _pstore2_storegen_data_T_13 = pstore1_mask[3]; // @[DCache.scala:496:31, :528:110]
wire _s1_hazard_T_6 = pstore1_mask[3]; // @[package.scala:211:50]
reg [7:0] pstore2_storegen_data_r_3; // @[DCache.scala:528:22]
wire [7:0] _pstore2_storegen_data_T_16 = pstore1_storegen_data[39:32]; // @[DCache.scala:497:42, :528:44]
wire _pstore2_storegen_data_T_17 = pstore1_mask[4]; // @[DCache.scala:496:31, :528:110]
wire _s1_hazard_T_7 = pstore1_mask[4]; // @[package.scala:211:50]
reg [7:0] pstore2_storegen_data_r_4; // @[DCache.scala:528:22]
wire [7:0] _pstore2_storegen_data_T_20 = pstore1_storegen_data[47:40]; // @[DCache.scala:497:42, :528:44]
wire _pstore2_storegen_data_T_21 = pstore1_mask[5]; // @[DCache.scala:496:31, :528:110]
wire _s1_hazard_T_8 = pstore1_mask[5]; // @[package.scala:211:50]
reg [7:0] pstore2_storegen_data_r_5; // @[DCache.scala:528:22]
wire [7:0] _pstore2_storegen_data_T_24 = pstore1_storegen_data[55:48]; // @[DCache.scala:497:42, :528:44]
wire _pstore2_storegen_data_T_25 = pstore1_mask[6]; // @[DCache.scala:496:31, :528:110]
wire _s1_hazard_T_9 = pstore1_mask[6]; // @[package.scala:211:50]
reg [7:0] pstore2_storegen_data_r_6; // @[DCache.scala:528:22]
wire [7:0] _pstore2_storegen_data_T_28 = pstore1_storegen_data[63:56]; // @[DCache.scala:497:42, :528:44]
wire _pstore2_storegen_data_T_29 = pstore1_mask[7]; // @[DCache.scala:496:31, :528:110]
wire _s1_hazard_T_10 = pstore1_mask[7]; // @[package.scala:211:50]
reg [7:0] pstore2_storegen_data_r_7; // @[DCache.scala:528:22]
wire [15:0] pstore2_storegen_data_lo_lo = {pstore2_storegen_data_r_1, pstore2_storegen_data_r}; // @[package.scala:45:27]
wire [15:0] pstore2_storegen_data_lo_hi = {pstore2_storegen_data_r_3, pstore2_storegen_data_r_2}; // @[package.scala:45:27]
wire [31:0] pstore2_storegen_data_lo = {pstore2_storegen_data_lo_hi, pstore2_storegen_data_lo_lo}; // @[package.scala:45:27]
wire [15:0] pstore2_storegen_data_hi_lo = {pstore2_storegen_data_r_5, pstore2_storegen_data_r_4}; // @[package.scala:45:27]
wire [15:0] pstore2_storegen_data_hi_hi = {pstore2_storegen_data_r_7, pstore2_storegen_data_r_6}; // @[package.scala:45:27]
wire [31:0] pstore2_storegen_data_hi = {pstore2_storegen_data_hi_hi, pstore2_storegen_data_hi_lo}; // @[package.scala:45:27]
wire [63:0] pstore2_storegen_data = {pstore2_storegen_data_hi, pstore2_storegen_data_lo}; // @[package.scala:45:27]
reg [7:0] pstore2_storegen_mask; // @[DCache.scala:531:19]
wire [7:0] _pstore2_storegen_mask_mask_T = ~pstore2_storegen_mask_mergedMask; // @[DCache.scala:533:37, :534:37]
wire [7:0] _pstore2_storegen_mask_mask_T_1 = _pstore2_storegen_mask_mask_T; // @[DCache.scala:534:{19,37}]
wire [7:0] _pstore2_storegen_mask_mask_T_2 = ~_pstore2_storegen_mask_mask_T_1; // @[DCache.scala:534:{15,19}]
wire _dataArb_io_in_0_valid_T_4 = _dataArb_io_in_0_valid_T_2; // @[DCache.scala:506:{72,84}]
wire _dataArb_io_in_0_valid_T_5 = _dataArb_io_in_0_valid_T_4 | pstore1_held; // @[DCache.scala:504:29, :506:{84,96}]
wire _dataArb_io_in_0_valid_T_6 = ~pstore1_rmw; // @[DCache.scala:498:32, :518:44]
wire _dataArb_io_in_0_valid_T_7 = _dataArb_io_in_0_valid_T_5 & _dataArb_io_in_0_valid_T_6; // @[DCache.scala:506:96, :518:{41,44}]
wire _dataArb_io_in_0_valid_T_8 = _dataArb_io_in_0_valid_T_7 | pstore2_valid; // @[DCache.scala:501:30, :518:{41,58}]
wire _dataArb_io_in_0_valid_T_10 = _dataArb_io_in_0_valid_T_8 & _dataArb_io_in_0_valid_T_9; // @[DCache.scala:518:{58,76,107}]
wire _dataArb_io_in_0_valid_T_11 = _dataArb_io_in_0_valid_T_1 | _dataArb_io_in_0_valid_T_10; // @[DCache.scala:517:{17,44}, :518:76]
assign _dataArb_io_in_0_valid_T_12 = _dataArb_io_in_0_valid_T_11; // @[DCache.scala:516:27, :517:44]
assign dataArb_io_in_0_valid = _dataArb_io_in_0_valid_T_12; // @[DCache.scala:152:28, :516:27]
wire [39:0] _GEN_93 = pstore2_valid ? pstore2_addr : pstore1_addr; // @[DCache.scala:493:31, :501:30, :524:31, :549:36]
wire [39:0] _dataArb_io_in_0_bits_addr_T; // @[DCache.scala:549:36]
assign _dataArb_io_in_0_bits_addr_T = _GEN_93; // @[DCache.scala:549:36]
wire [39:0] _dataArb_io_in_0_bits_wordMask_wordMask_T; // @[DCache.scala:554:32]
assign _dataArb_io_in_0_bits_wordMask_wordMask_T = _GEN_93; // @[DCache.scala:549:36, :554:32]
assign dataArb_io_in_0_bits_addr = _dataArb_io_in_0_bits_addr_T[10:0]; // @[DCache.scala:152:28, :549:{30,36}]
assign dataArb_io_in_1_bits_addr = _dataArb_io_in_0_bits_addr_T[10:0]; // @[DCache.scala:152:28, :549:{30,36}]
assign _dataArb_io_in_0_bits_way_en_T = pstore2_valid ? pstore2_way : pstore1_way; // @[DCache.scala:495:30, :501:30, :525:30, :550:38]
assign dataArb_io_in_0_bits_way_en = _dataArb_io_in_0_bits_way_en_T; // @[DCache.scala:152:28, :550:38]
assign dataArb_io_in_1_bits_way_en = _dataArb_io_in_0_bits_way_en_T; // @[DCache.scala:152:28, :550:38]
wire [63:0] _dataArb_io_in_0_bits_wdata_T = pstore2_valid ? pstore2_storegen_data : pstore1_data; // @[package.scala:45:27]
wire [7:0] _dataArb_io_in_0_bits_wdata_T_1 = _dataArb_io_in_0_bits_wdata_T[7:0]; // @[package.scala:211:50]
wire [7:0] _dataArb_io_in_0_bits_wdata_T_2 = _dataArb_io_in_0_bits_wdata_T[15:8]; // @[package.scala:211:50]
wire [7:0] _dataArb_io_in_0_bits_wdata_T_3 = _dataArb_io_in_0_bits_wdata_T[23:16]; // @[package.scala:211:50]
wire [7:0] _dataArb_io_in_0_bits_wdata_T_4 = _dataArb_io_in_0_bits_wdata_T[31:24]; // @[package.scala:211:50]
wire [7:0] _dataArb_io_in_0_bits_wdata_T_5 = _dataArb_io_in_0_bits_wdata_T[39:32]; // @[package.scala:211:50]
wire [7:0] _dataArb_io_in_0_bits_wdata_T_6 = _dataArb_io_in_0_bits_wdata_T[47:40]; // @[package.scala:211:50]
wire [7:0] _dataArb_io_in_0_bits_wdata_T_7 = _dataArb_io_in_0_bits_wdata_T[55:48]; // @[package.scala:211:50]
wire [7:0] _dataArb_io_in_0_bits_wdata_T_8 = _dataArb_io_in_0_bits_wdata_T[63:56]; // @[package.scala:211:50]
wire [15:0] dataArb_io_in_0_bits_wdata_lo_lo = {_dataArb_io_in_0_bits_wdata_T_2, _dataArb_io_in_0_bits_wdata_T_1}; // @[package.scala:45:27, :211:50]
wire [15:0] dataArb_io_in_0_bits_wdata_lo_hi = {_dataArb_io_in_0_bits_wdata_T_4, _dataArb_io_in_0_bits_wdata_T_3}; // @[package.scala:45:27, :211:50]
wire [31:0] dataArb_io_in_0_bits_wdata_lo = {dataArb_io_in_0_bits_wdata_lo_hi, dataArb_io_in_0_bits_wdata_lo_lo}; // @[package.scala:45:27]
wire [15:0] dataArb_io_in_0_bits_wdata_hi_lo = {_dataArb_io_in_0_bits_wdata_T_6, _dataArb_io_in_0_bits_wdata_T_5}; // @[package.scala:45:27, :211:50]
wire [15:0] dataArb_io_in_0_bits_wdata_hi_hi = {_dataArb_io_in_0_bits_wdata_T_8, _dataArb_io_in_0_bits_wdata_T_7}; // @[package.scala:45:27, :211:50]
wire [31:0] dataArb_io_in_0_bits_wdata_hi = {dataArb_io_in_0_bits_wdata_hi_hi, dataArb_io_in_0_bits_wdata_hi_lo}; // @[package.scala:45:27]
assign _dataArb_io_in_0_bits_wdata_T_9 = {dataArb_io_in_0_bits_wdata_hi, dataArb_io_in_0_bits_wdata_lo}; // @[package.scala:45:27]
assign dataArb_io_in_0_bits_wdata = _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27]
assign dataArb_io_in_1_bits_wdata = _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27]
assign dataArb_io_in_2_bits_wdata = _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27]
assign dataArb_io_in_3_bits_wdata = _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T = _dataArb_io_in_0_bits_eccMask_T_17[0]; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_1 = _dataArb_io_in_0_bits_eccMask_T_17[1]; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_2 = _dataArb_io_in_0_bits_eccMask_T_17[2]; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_3 = _dataArb_io_in_0_bits_eccMask_T_17[3]; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_4 = _dataArb_io_in_0_bits_eccMask_T_17[4]; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_5 = _dataArb_io_in_0_bits_eccMask_T_17[5]; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_6 = _dataArb_io_in_0_bits_eccMask_T_17[6]; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_7 = _dataArb_io_in_0_bits_eccMask_T_17[7]; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_8 = _dataArb_io_in_0_bits_wordMask_eccMask_T | _dataArb_io_in_0_bits_wordMask_eccMask_T_1; // @[package.scala:81:59]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_9 = _dataArb_io_in_0_bits_wordMask_eccMask_T_8 | _dataArb_io_in_0_bits_wordMask_eccMask_T_2; // @[package.scala:81:59]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_10 = _dataArb_io_in_0_bits_wordMask_eccMask_T_9 | _dataArb_io_in_0_bits_wordMask_eccMask_T_3; // @[package.scala:81:59]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_11 = _dataArb_io_in_0_bits_wordMask_eccMask_T_10 | _dataArb_io_in_0_bits_wordMask_eccMask_T_4; // @[package.scala:81:59]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_12 = _dataArb_io_in_0_bits_wordMask_eccMask_T_11 | _dataArb_io_in_0_bits_wordMask_eccMask_T_5; // @[package.scala:81:59]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_13 = _dataArb_io_in_0_bits_wordMask_eccMask_T_12 | _dataArb_io_in_0_bits_wordMask_eccMask_T_6; // @[package.scala:81:59]
wire dataArb_io_in_0_bits_wordMask_eccMask = _dataArb_io_in_0_bits_wordMask_eccMask_T_13 | _dataArb_io_in_0_bits_wordMask_eccMask_T_7; // @[package.scala:81:59]
wire [1:0] _dataArb_io_in_0_bits_wordMask_T_3 = {1'h0, dataArb_io_in_0_bits_wordMask_eccMask}; // @[package.scala:81:59]
assign dataArb_io_in_0_bits_wordMask = _dataArb_io_in_0_bits_wordMask_T_3[0]; // @[DCache.scala:152:28, :552:34, :555:55]
assign dataArb_io_in_1_bits_wordMask = _dataArb_io_in_0_bits_wordMask_T_3[0]; // @[DCache.scala:152:28, :552:34, :555:55]
wire [7:0] _dataArb_io_in_0_bits_eccMask_T = pstore2_valid ? pstore2_storegen_mask : pstore1_mask; // @[DCache.scala:496:31, :501:30, :531:19, :557:47]
wire _dataArb_io_in_0_bits_eccMask_T_1 = _dataArb_io_in_0_bits_eccMask_T[0]; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_9 = _dataArb_io_in_0_bits_eccMask_T_1; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_2 = _dataArb_io_in_0_bits_eccMask_T[1]; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_10 = _dataArb_io_in_0_bits_eccMask_T_2; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_3 = _dataArb_io_in_0_bits_eccMask_T[2]; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_11 = _dataArb_io_in_0_bits_eccMask_T_3; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_4 = _dataArb_io_in_0_bits_eccMask_T[3]; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_12 = _dataArb_io_in_0_bits_eccMask_T_4; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_5 = _dataArb_io_in_0_bits_eccMask_T[4]; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_13 = _dataArb_io_in_0_bits_eccMask_T_5; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_6 = _dataArb_io_in_0_bits_eccMask_T[5]; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_14 = _dataArb_io_in_0_bits_eccMask_T_6; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_7 = _dataArb_io_in_0_bits_eccMask_T[6]; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_15 = _dataArb_io_in_0_bits_eccMask_T_7; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_8 = _dataArb_io_in_0_bits_eccMask_T[7]; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_16 = _dataArb_io_in_0_bits_eccMask_T_8; // @[package.scala:211:50]
wire [1:0] dataArb_io_in_0_bits_eccMask_lo_lo = {_dataArb_io_in_0_bits_eccMask_T_10, _dataArb_io_in_0_bits_eccMask_T_9}; // @[package.scala:45:27]
wire [1:0] dataArb_io_in_0_bits_eccMask_lo_hi = {_dataArb_io_in_0_bits_eccMask_T_12, _dataArb_io_in_0_bits_eccMask_T_11}; // @[package.scala:45:27]
wire [3:0] dataArb_io_in_0_bits_eccMask_lo = {dataArb_io_in_0_bits_eccMask_lo_hi, dataArb_io_in_0_bits_eccMask_lo_lo}; // @[package.scala:45:27]
wire [1:0] dataArb_io_in_0_bits_eccMask_hi_lo = {_dataArb_io_in_0_bits_eccMask_T_14, _dataArb_io_in_0_bits_eccMask_T_13}; // @[package.scala:45:27]
wire [1:0] dataArb_io_in_0_bits_eccMask_hi_hi = {_dataArb_io_in_0_bits_eccMask_T_16, _dataArb_io_in_0_bits_eccMask_T_15}; // @[package.scala:45:27]
wire [3:0] dataArb_io_in_0_bits_eccMask_hi = {dataArb_io_in_0_bits_eccMask_hi_hi, dataArb_io_in_0_bits_eccMask_hi_lo}; // @[package.scala:45:27]
assign _dataArb_io_in_0_bits_eccMask_T_17 = {dataArb_io_in_0_bits_eccMask_hi, dataArb_io_in_0_bits_eccMask_lo}; // @[package.scala:45:27]
assign dataArb_io_in_0_bits_eccMask = _dataArb_io_in_0_bits_eccMask_T_17; // @[package.scala:45:27]
assign dataArb_io_in_1_bits_eccMask = _dataArb_io_in_0_bits_eccMask_T_17; // @[package.scala:45:27]
wire [7:0] _s1_hazard_T = pstore1_addr[10:3]; // @[DCache.scala:493:31, :561:9]
wire [7:0] _s1_hazard_T_1 = s1_vaddr[10:3]; // @[DCache.scala:197:21, :561:43]
wire [7:0] _s1_hazard_T_63 = s1_vaddr[10:3]; // @[DCache.scala:197:21, :561:43]
wire _s1_hazard_T_2 = _s1_hazard_T == _s1_hazard_T_1; // @[DCache.scala:561:{9,31,43}]
wire _s1_hazard_T_11 = _s1_hazard_T_3; // @[package.scala:211:50]
wire _s1_hazard_T_12 = _s1_hazard_T_4; // @[package.scala:211:50]
wire _s1_hazard_T_13 = _s1_hazard_T_5; // @[package.scala:211:50]
wire _s1_hazard_T_14 = _s1_hazard_T_6; // @[package.scala:211:50]
wire _s1_hazard_T_15 = _s1_hazard_T_7; // @[package.scala:211:50]
wire _s1_hazard_T_16 = _s1_hazard_T_8; // @[package.scala:211:50]
wire _s1_hazard_T_17 = _s1_hazard_T_9; // @[package.scala:211:50]
wire _s1_hazard_T_18 = _s1_hazard_T_10; // @[package.scala:211:50]
wire [1:0] s1_hazard_lo_lo = {_s1_hazard_T_12, _s1_hazard_T_11}; // @[package.scala:45:27]
wire [1:0] s1_hazard_lo_hi = {_s1_hazard_T_14, _s1_hazard_T_13}; // @[package.scala:45:27]
wire [3:0] s1_hazard_lo = {s1_hazard_lo_hi, s1_hazard_lo_lo}; // @[package.scala:45:27]
wire [1:0] s1_hazard_hi_lo = {_s1_hazard_T_16, _s1_hazard_T_15}; // @[package.scala:45:27]
wire [1:0] s1_hazard_hi_hi = {_s1_hazard_T_18, _s1_hazard_T_17}; // @[package.scala:45:27]
wire [3:0] s1_hazard_hi = {s1_hazard_hi_hi, s1_hazard_hi_lo}; // @[package.scala:45:27]
wire [7:0] _s1_hazard_T_19 = {s1_hazard_hi, s1_hazard_lo}; // @[package.scala:45:27]
wire _s1_hazard_T_20 = _s1_hazard_T_19[0]; // @[package.scala:45:27]
wire _s1_hazard_T_21 = _s1_hazard_T_19[1]; // @[package.scala:45:27]
wire _s1_hazard_T_22 = _s1_hazard_T_19[2]; // @[package.scala:45:27]
wire _s1_hazard_T_23 = _s1_hazard_T_19[3]; // @[package.scala:45:27]
wire _s1_hazard_T_24 = _s1_hazard_T_19[4]; // @[package.scala:45:27]
wire _s1_hazard_T_25 = _s1_hazard_T_19[5]; // @[package.scala:45:27]
wire _s1_hazard_T_26 = _s1_hazard_T_19[6]; // @[package.scala:45:27]
wire _s1_hazard_T_27 = _s1_hazard_T_19[7]; // @[package.scala:45:27]
wire [1:0] s1_hazard_lo_lo_1 = {_s1_hazard_T_21, _s1_hazard_T_20}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_lo_hi_1 = {_s1_hazard_T_23, _s1_hazard_T_22}; // @[DCache.scala:1182:52]
wire [3:0] s1_hazard_lo_1 = {s1_hazard_lo_hi_1, s1_hazard_lo_lo_1}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_hi_lo_1 = {_s1_hazard_T_25, _s1_hazard_T_24}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_hi_hi_1 = {_s1_hazard_T_27, _s1_hazard_T_26}; // @[DCache.scala:1182:52]
wire [3:0] s1_hazard_hi_1 = {s1_hazard_hi_hi_1, s1_hazard_hi_lo_1}; // @[DCache.scala:1182:52]
wire [7:0] _s1_hazard_T_28 = {s1_hazard_hi_1, s1_hazard_lo_1}; // @[DCache.scala:1182:52]
wire _s1_hazard_T_29 = s1_mask_xwr[0]; // @[package.scala:211:50]
wire _s1_hazard_T_91 = s1_mask_xwr[0]; // @[package.scala:211:50]
wire _s1_hazard_T_37 = _s1_hazard_T_29; // @[package.scala:211:50]
wire _s1_hazard_T_30 = s1_mask_xwr[1]; // @[package.scala:211:50]
wire _s1_hazard_T_92 = s1_mask_xwr[1]; // @[package.scala:211:50]
wire _s1_hazard_T_38 = _s1_hazard_T_30; // @[package.scala:211:50]
wire _s1_hazard_T_31 = s1_mask_xwr[2]; // @[package.scala:211:50]
wire _s1_hazard_T_93 = s1_mask_xwr[2]; // @[package.scala:211:50]
wire _s1_hazard_T_39 = _s1_hazard_T_31; // @[package.scala:211:50]
wire _s1_hazard_T_32 = s1_mask_xwr[3]; // @[package.scala:211:50]
wire _s1_hazard_T_94 = s1_mask_xwr[3]; // @[package.scala:211:50]
wire _s1_hazard_T_40 = _s1_hazard_T_32; // @[package.scala:211:50]
wire _s1_hazard_T_33 = s1_mask_xwr[4]; // @[package.scala:211:50]
wire _s1_hazard_T_95 = s1_mask_xwr[4]; // @[package.scala:211:50]
wire _s1_hazard_T_41 = _s1_hazard_T_33; // @[package.scala:211:50]
wire _s1_hazard_T_34 = s1_mask_xwr[5]; // @[package.scala:211:50]
wire _s1_hazard_T_96 = s1_mask_xwr[5]; // @[package.scala:211:50]
wire _s1_hazard_T_42 = _s1_hazard_T_34; // @[package.scala:211:50]
wire _s1_hazard_T_35 = s1_mask_xwr[6]; // @[package.scala:211:50]
wire _s1_hazard_T_97 = s1_mask_xwr[6]; // @[package.scala:211:50]
wire _s1_hazard_T_43 = _s1_hazard_T_35; // @[package.scala:211:50]
wire _s1_hazard_T_36 = s1_mask_xwr[7]; // @[package.scala:211:50]
wire _s1_hazard_T_98 = s1_mask_xwr[7]; // @[package.scala:211:50]
wire _s1_hazard_T_44 = _s1_hazard_T_36; // @[package.scala:211:50]
wire [1:0] s1_hazard_lo_lo_2 = {_s1_hazard_T_38, _s1_hazard_T_37}; // @[package.scala:45:27]
wire [1:0] s1_hazard_lo_hi_2 = {_s1_hazard_T_40, _s1_hazard_T_39}; // @[package.scala:45:27]
wire [3:0] s1_hazard_lo_2 = {s1_hazard_lo_hi_2, s1_hazard_lo_lo_2}; // @[package.scala:45:27]
wire [1:0] s1_hazard_hi_lo_2 = {_s1_hazard_T_42, _s1_hazard_T_41}; // @[package.scala:45:27]
wire [1:0] s1_hazard_hi_hi_2 = {_s1_hazard_T_44, _s1_hazard_T_43}; // @[package.scala:45:27]
wire [3:0] s1_hazard_hi_2 = {s1_hazard_hi_hi_2, s1_hazard_hi_lo_2}; // @[package.scala:45:27]
wire [7:0] _s1_hazard_T_45 = {s1_hazard_hi_2, s1_hazard_lo_2}; // @[package.scala:45:27]
wire _s1_hazard_T_46 = _s1_hazard_T_45[0]; // @[package.scala:45:27]
wire _s1_hazard_T_47 = _s1_hazard_T_45[1]; // @[package.scala:45:27]
wire _s1_hazard_T_48 = _s1_hazard_T_45[2]; // @[package.scala:45:27]
wire _s1_hazard_T_49 = _s1_hazard_T_45[3]; // @[package.scala:45:27]
wire _s1_hazard_T_50 = _s1_hazard_T_45[4]; // @[package.scala:45:27]
wire _s1_hazard_T_51 = _s1_hazard_T_45[5]; // @[package.scala:45:27]
wire _s1_hazard_T_52 = _s1_hazard_T_45[6]; // @[package.scala:45:27]
wire _s1_hazard_T_53 = _s1_hazard_T_45[7]; // @[package.scala:45:27]
wire [1:0] s1_hazard_lo_lo_3 = {_s1_hazard_T_47, _s1_hazard_T_46}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_lo_hi_3 = {_s1_hazard_T_49, _s1_hazard_T_48}; // @[DCache.scala:1182:52]
wire [3:0] s1_hazard_lo_3 = {s1_hazard_lo_hi_3, s1_hazard_lo_lo_3}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_hi_lo_3 = {_s1_hazard_T_51, _s1_hazard_T_50}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_hi_hi_3 = {_s1_hazard_T_53, _s1_hazard_T_52}; // @[DCache.scala:1182:52]
wire [3:0] s1_hazard_hi_3 = {s1_hazard_hi_hi_3, s1_hazard_hi_lo_3}; // @[DCache.scala:1182:52]
wire [7:0] _s1_hazard_T_54 = {s1_hazard_hi_3, s1_hazard_lo_3}; // @[DCache.scala:1182:52]
wire [7:0] _s1_hazard_T_55 = _s1_hazard_T_28 & _s1_hazard_T_54; // @[DCache.scala:562:38, :1182:52]
wire _s1_hazard_T_56 = |_s1_hazard_T_55; // @[DCache.scala:562:{38,66}]
wire [7:0] _s1_hazard_T_57 = pstore1_mask & s1_mask_xwr; // @[DCache.scala:496:31, :562:77]
wire _s1_hazard_T_58 = |_s1_hazard_T_57; // @[DCache.scala:562:{77,92}]
wire _s1_hazard_T_59 = s1_write ? _s1_hazard_T_56 : _s1_hazard_T_58; // @[DCache.scala:562:{8,66,92}]
wire _s1_hazard_T_60 = _s1_hazard_T_2 & _s1_hazard_T_59; // @[DCache.scala:561:{31,65}, :562:8]
wire _s1_hazard_T_61 = pstore1_valid_likely & _s1_hazard_T_60; // @[DCache.scala:505:51, :561:65, :564:27]
wire [7:0] _s1_hazard_T_62 = pstore2_addr[10:3]; // @[DCache.scala:524:31, :561:9]
wire _s1_hazard_T_64 = _s1_hazard_T_62 == _s1_hazard_T_63; // @[DCache.scala:561:{9,31,43}]
wire _s1_hazard_T_65 = pstore2_storegen_mask[0]; // @[package.scala:211:50]
wire _s1_hazard_T_73 = _s1_hazard_T_65; // @[package.scala:211:50]
wire _s1_hazard_T_66 = pstore2_storegen_mask[1]; // @[package.scala:211:50]
wire _s1_hazard_T_74 = _s1_hazard_T_66; // @[package.scala:211:50]
wire _s1_hazard_T_67 = pstore2_storegen_mask[2]; // @[package.scala:211:50]
wire _s1_hazard_T_75 = _s1_hazard_T_67; // @[package.scala:211:50]
wire _s1_hazard_T_68 = pstore2_storegen_mask[3]; // @[package.scala:211:50]
wire _s1_hazard_T_76 = _s1_hazard_T_68; // @[package.scala:211:50]
wire _s1_hazard_T_69 = pstore2_storegen_mask[4]; // @[package.scala:211:50]
wire _s1_hazard_T_77 = _s1_hazard_T_69; // @[package.scala:211:50]
wire _s1_hazard_T_70 = pstore2_storegen_mask[5]; // @[package.scala:211:50]
wire _s1_hazard_T_78 = _s1_hazard_T_70; // @[package.scala:211:50]
wire _s1_hazard_T_71 = pstore2_storegen_mask[6]; // @[package.scala:211:50]
wire _s1_hazard_T_79 = _s1_hazard_T_71; // @[package.scala:211:50]
wire _s1_hazard_T_72 = pstore2_storegen_mask[7]; // @[package.scala:211:50]
wire _s1_hazard_T_80 = _s1_hazard_T_72; // @[package.scala:211:50]
wire [1:0] s1_hazard_lo_lo_4 = {_s1_hazard_T_74, _s1_hazard_T_73}; // @[package.scala:45:27]
wire [1:0] s1_hazard_lo_hi_4 = {_s1_hazard_T_76, _s1_hazard_T_75}; // @[package.scala:45:27]
wire [3:0] s1_hazard_lo_4 = {s1_hazard_lo_hi_4, s1_hazard_lo_lo_4}; // @[package.scala:45:27]
wire [1:0] s1_hazard_hi_lo_4 = {_s1_hazard_T_78, _s1_hazard_T_77}; // @[package.scala:45:27]
wire [1:0] s1_hazard_hi_hi_4 = {_s1_hazard_T_80, _s1_hazard_T_79}; // @[package.scala:45:27]
wire [3:0] s1_hazard_hi_4 = {s1_hazard_hi_hi_4, s1_hazard_hi_lo_4}; // @[package.scala:45:27]
wire [7:0] _s1_hazard_T_81 = {s1_hazard_hi_4, s1_hazard_lo_4}; // @[package.scala:45:27]
wire _s1_hazard_T_82 = _s1_hazard_T_81[0]; // @[package.scala:45:27]
wire _s1_hazard_T_83 = _s1_hazard_T_81[1]; // @[package.scala:45:27]
wire _s1_hazard_T_84 = _s1_hazard_T_81[2]; // @[package.scala:45:27]
wire _s1_hazard_T_85 = _s1_hazard_T_81[3]; // @[package.scala:45:27]
wire _s1_hazard_T_86 = _s1_hazard_T_81[4]; // @[package.scala:45:27]
wire _s1_hazard_T_87 = _s1_hazard_T_81[5]; // @[package.scala:45:27]
wire _s1_hazard_T_88 = _s1_hazard_T_81[6]; // @[package.scala:45:27]
wire _s1_hazard_T_89 = _s1_hazard_T_81[7]; // @[package.scala:45:27]
wire [1:0] s1_hazard_lo_lo_5 = {_s1_hazard_T_83, _s1_hazard_T_82}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_lo_hi_5 = {_s1_hazard_T_85, _s1_hazard_T_84}; // @[DCache.scala:1182:52]
wire [3:0] s1_hazard_lo_5 = {s1_hazard_lo_hi_5, s1_hazard_lo_lo_5}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_hi_lo_5 = {_s1_hazard_T_87, _s1_hazard_T_86}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_hi_hi_5 = {_s1_hazard_T_89, _s1_hazard_T_88}; // @[DCache.scala:1182:52]
wire [3:0] s1_hazard_hi_5 = {s1_hazard_hi_hi_5, s1_hazard_hi_lo_5}; // @[DCache.scala:1182:52]
wire [7:0] _s1_hazard_T_90 = {s1_hazard_hi_5, s1_hazard_lo_5}; // @[DCache.scala:1182:52]
wire _s1_hazard_T_99 = _s1_hazard_T_91; // @[package.scala:211:50]
wire _s1_hazard_T_100 = _s1_hazard_T_92; // @[package.scala:211:50]
wire _s1_hazard_T_101 = _s1_hazard_T_93; // @[package.scala:211:50]
wire _s1_hazard_T_102 = _s1_hazard_T_94; // @[package.scala:211:50]
wire _s1_hazard_T_103 = _s1_hazard_T_95; // @[package.scala:211:50]
wire _s1_hazard_T_104 = _s1_hazard_T_96; // @[package.scala:211:50]
wire _s1_hazard_T_105 = _s1_hazard_T_97; // @[package.scala:211:50]
wire _s1_hazard_T_106 = _s1_hazard_T_98; // @[package.scala:211:50]
wire [1:0] s1_hazard_lo_lo_6 = {_s1_hazard_T_100, _s1_hazard_T_99}; // @[package.scala:45:27]
wire [1:0] s1_hazard_lo_hi_6 = {_s1_hazard_T_102, _s1_hazard_T_101}; // @[package.scala:45:27]
wire [3:0] s1_hazard_lo_6 = {s1_hazard_lo_hi_6, s1_hazard_lo_lo_6}; // @[package.scala:45:27]
wire [1:0] s1_hazard_hi_lo_6 = {_s1_hazard_T_104, _s1_hazard_T_103}; // @[package.scala:45:27]
wire [1:0] s1_hazard_hi_hi_6 = {_s1_hazard_T_106, _s1_hazard_T_105}; // @[package.scala:45:27]
wire [3:0] s1_hazard_hi_6 = {s1_hazard_hi_hi_6, s1_hazard_hi_lo_6}; // @[package.scala:45:27]
wire [7:0] _s1_hazard_T_107 = {s1_hazard_hi_6, s1_hazard_lo_6}; // @[package.scala:45:27]
wire _s1_hazard_T_108 = _s1_hazard_T_107[0]; // @[package.scala:45:27]
wire _s1_hazard_T_109 = _s1_hazard_T_107[1]; // @[package.scala:45:27]
wire _s1_hazard_T_110 = _s1_hazard_T_107[2]; // @[package.scala:45:27]
wire _s1_hazard_T_111 = _s1_hazard_T_107[3]; // @[package.scala:45:27]
wire _s1_hazard_T_112 = _s1_hazard_T_107[4]; // @[package.scala:45:27]
wire _s1_hazard_T_113 = _s1_hazard_T_107[5]; // @[package.scala:45:27]
wire _s1_hazard_T_114 = _s1_hazard_T_107[6]; // @[package.scala:45:27]
wire _s1_hazard_T_115 = _s1_hazard_T_107[7]; // @[package.scala:45:27]
wire [1:0] s1_hazard_lo_lo_7 = {_s1_hazard_T_109, _s1_hazard_T_108}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_lo_hi_7 = {_s1_hazard_T_111, _s1_hazard_T_110}; // @[DCache.scala:1182:52]
wire [3:0] s1_hazard_lo_7 = {s1_hazard_lo_hi_7, s1_hazard_lo_lo_7}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_hi_lo_7 = {_s1_hazard_T_113, _s1_hazard_T_112}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_hi_hi_7 = {_s1_hazard_T_115, _s1_hazard_T_114}; // @[DCache.scala:1182:52]
wire [3:0] s1_hazard_hi_7 = {s1_hazard_hi_hi_7, s1_hazard_hi_lo_7}; // @[DCache.scala:1182:52]
wire [7:0] _s1_hazard_T_116 = {s1_hazard_hi_7, s1_hazard_lo_7}; // @[DCache.scala:1182:52]
wire [7:0] _s1_hazard_T_117 = _s1_hazard_T_90 & _s1_hazard_T_116; // @[DCache.scala:562:38, :1182:52]
wire _s1_hazard_T_118 = |_s1_hazard_T_117; // @[DCache.scala:562:{38,66}]
wire [7:0] _s1_hazard_T_119 = pstore2_storegen_mask & s1_mask_xwr; // @[DCache.scala:531:19, :562:77]
wire _s1_hazard_T_120 = |_s1_hazard_T_119; // @[DCache.scala:562:{77,92}]
wire _s1_hazard_T_121 = s1_write ? _s1_hazard_T_118 : _s1_hazard_T_120; // @[DCache.scala:562:{8,66,92}]
wire _s1_hazard_T_122 = _s1_hazard_T_64 & _s1_hazard_T_121; // @[DCache.scala:561:{31,65}, :562:8]
wire _s1_hazard_T_123 = pstore2_valid & _s1_hazard_T_122; // @[DCache.scala:501:30, :561:65, :565:21]
wire s1_hazard = _s1_hazard_T_61 | _s1_hazard_T_123; // @[DCache.scala:564:{27,69}, :565:21]
wire s1_raw_hazard = s1_read & s1_hazard; // @[DCache.scala:564:69, :566:31]
assign s1_nack = s1_valid & s1_raw_hazard | io_cpu_s2_nack_0 | _metaArb_io_in_2_valid_T | s1_valid & s1_cmd_uses_tlb & _tlb_io_resp_miss; // @[DCache.scala:101:7, :119:19, :182:25, :185:28, :270:55, :276:{39,58,79}, :288:{75,85}, :446:{24,82,92}, :462:63, :566:31, :571:{18,36,46}]
reg io_cpu_s2_nack_cause_raw_REG; // @[DCache.scala:574:38]
assign _io_cpu_s2_nack_cause_raw_T_3 = io_cpu_s2_nack_cause_raw_REG; // @[DCache.scala:574:{38,54}]
assign io_cpu_s2_nack_cause_raw_0 = _io_cpu_s2_nack_cause_raw_T_3; // @[DCache.scala:101:7, :574:54]
wire _a_source_T = ~uncachedInFlight_0; // @[DCache.scala:236:33, :577:34]
wire _a_source_T_1 = _a_source_T; // @[DCache.scala:577:{34,59}]
wire _a_source_T_2 = _a_source_T_1; // @[OneHot.scala:48:45]
wire [39:0] acquire_address = {_acquire_address_T, 6'h0}; // @[DCache.scala:578:{38,49}]
wire [22:0] a_mask = {15'h0, pstore1_mask}; // @[DCache.scala:496:31, :582:29]
wire [39:0] _GEN_94 = {s2_req_addr[39:14], s2_req_addr[13:0] ^ 14'h3000}; // @[DCache.scala:339:19]
wire [39:0] _get_legal_T_4; // @[Parameters.scala:137:31]
assign _get_legal_T_4 = _GEN_94; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_4; // @[Parameters.scala:137:31]
assign _put_legal_T_4 = _GEN_94; // @[Parameters.scala:137:31]
wire [39:0] _putpartial_legal_T_4; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_4 = _GEN_94; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_5 = {1'h0, _get_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_6 = _get_legal_T_5 & 41'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_7 = _get_legal_T_6; // @[Parameters.scala:137:46]
wire _get_legal_T_8 = _get_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _get_legal_T_9 = _get_legal_T_8; // @[Parameters.scala:684:54]
wire _get_legal_T_74 = _get_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _get_legal_T_15 = {1'h0, _get_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_16 = _get_legal_T_15 & 41'h9A112000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_17 = _get_legal_T_16; // @[Parameters.scala:137:46]
wire _get_legal_T_18 = _get_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_95 = {s2_req_addr[39:17], s2_req_addr[16:0] ^ 17'h10000}; // @[DCache.scala:339:19]
wire [39:0] _get_legal_T_19; // @[Parameters.scala:137:31]
assign _get_legal_T_19 = _GEN_95; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_75; // @[Parameters.scala:137:31]
assign _put_legal_T_75 = _GEN_95; // @[Parameters.scala:137:31]
wire [39:0] _putpartial_legal_T_75; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_75 = _GEN_95; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_47; // @[Parameters.scala:137:31]
assign _atomics_legal_T_47 = _GEN_95; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_101; // @[Parameters.scala:137:31]
assign _atomics_legal_T_101 = _GEN_95; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_155; // @[Parameters.scala:137:31]
assign _atomics_legal_T_155 = _GEN_95; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_209; // @[Parameters.scala:137:31]
assign _atomics_legal_T_209 = _GEN_95; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_263; // @[Parameters.scala:137:31]
assign _atomics_legal_T_263 = _GEN_95; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_317; // @[Parameters.scala:137:31]
assign _atomics_legal_T_317 = _GEN_95; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_371; // @[Parameters.scala:137:31]
assign _atomics_legal_T_371 = _GEN_95; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_425; // @[Parameters.scala:137:31]
assign _atomics_legal_T_425 = _GEN_95; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_479; // @[Parameters.scala:137:31]
assign _atomics_legal_T_479 = _GEN_95; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_20 = {1'h0, _get_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_21 = _get_legal_T_20 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_22 = _get_legal_T_21; // @[Parameters.scala:137:46]
wire _get_legal_T_23 = _get_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_96 = {s2_req_addr[39:21], s2_req_addr[20:0] ^ 21'h100000}; // @[DCache.scala:339:19]
wire [39:0] _get_legal_T_24; // @[Parameters.scala:137:31]
assign _get_legal_T_24 = _GEN_96; // @[Parameters.scala:137:31]
wire [39:0] _get_legal_T_29; // @[Parameters.scala:137:31]
assign _get_legal_T_29 = _GEN_96; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_19; // @[Parameters.scala:137:31]
assign _put_legal_T_19 = _GEN_96; // @[Parameters.scala:137:31]
wire [39:0] _putpartial_legal_T_19; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_19 = _GEN_96; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_9; // @[Parameters.scala:137:31]
assign _atomics_legal_T_9 = _GEN_96; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_63; // @[Parameters.scala:137:31]
assign _atomics_legal_T_63 = _GEN_96; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_117; // @[Parameters.scala:137:31]
assign _atomics_legal_T_117 = _GEN_96; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_171; // @[Parameters.scala:137:31]
assign _atomics_legal_T_171 = _GEN_96; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_225; // @[Parameters.scala:137:31]
assign _atomics_legal_T_225 = _GEN_96; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_279; // @[Parameters.scala:137:31]
assign _atomics_legal_T_279 = _GEN_96; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_333; // @[Parameters.scala:137:31]
assign _atomics_legal_T_333 = _GEN_96; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_387; // @[Parameters.scala:137:31]
assign _atomics_legal_T_387 = _GEN_96; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_441; // @[Parameters.scala:137:31]
assign _atomics_legal_T_441 = _GEN_96; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_25 = {1'h0, _get_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_26 = _get_legal_T_25 & 41'h9A103000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_27 = _get_legal_T_26; // @[Parameters.scala:137:46]
wire _get_legal_T_28 = _get_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _get_legal_T_30 = {1'h0, _get_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_31 = _get_legal_T_30 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_32 = _get_legal_T_31; // @[Parameters.scala:137:46]
wire _get_legal_T_33 = _get_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_97 = {s2_req_addr[39:26], s2_req_addr[25:0] ^ 26'h2000000}; // @[DCache.scala:339:19]
wire [39:0] _get_legal_T_34; // @[Parameters.scala:137:31]
assign _get_legal_T_34 = _GEN_97; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_34; // @[Parameters.scala:137:31]
assign _put_legal_T_34 = _GEN_97; // @[Parameters.scala:137:31]
wire [39:0] _putpartial_legal_T_34; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_34 = _GEN_97; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_14; // @[Parameters.scala:137:31]
assign _atomics_legal_T_14 = _GEN_97; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_68; // @[Parameters.scala:137:31]
assign _atomics_legal_T_68 = _GEN_97; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_122; // @[Parameters.scala:137:31]
assign _atomics_legal_T_122 = _GEN_97; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_176; // @[Parameters.scala:137:31]
assign _atomics_legal_T_176 = _GEN_97; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_230; // @[Parameters.scala:137:31]
assign _atomics_legal_T_230 = _GEN_97; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_284; // @[Parameters.scala:137:31]
assign _atomics_legal_T_284 = _GEN_97; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_338; // @[Parameters.scala:137:31]
assign _atomics_legal_T_338 = _GEN_97; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_392; // @[Parameters.scala:137:31]
assign _atomics_legal_T_392 = _GEN_97; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_446; // @[Parameters.scala:137:31]
assign _atomics_legal_T_446 = _GEN_97; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_35 = {1'h0, _get_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_36 = _get_legal_T_35 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_37 = _get_legal_T_36; // @[Parameters.scala:137:46]
wire _get_legal_T_38 = _get_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_98 = {s2_req_addr[39:26], s2_req_addr[25:0] ^ 26'h2010000}; // @[DCache.scala:339:19]
wire [39:0] _get_legal_T_39; // @[Parameters.scala:137:31]
assign _get_legal_T_39 = _GEN_98; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_39; // @[Parameters.scala:137:31]
assign _put_legal_T_39 = _GEN_98; // @[Parameters.scala:137:31]
wire [39:0] _putpartial_legal_T_39; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_39 = _GEN_98; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_19; // @[Parameters.scala:137:31]
assign _atomics_legal_T_19 = _GEN_98; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_73; // @[Parameters.scala:137:31]
assign _atomics_legal_T_73 = _GEN_98; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_127; // @[Parameters.scala:137:31]
assign _atomics_legal_T_127 = _GEN_98; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_181; // @[Parameters.scala:137:31]
assign _atomics_legal_T_181 = _GEN_98; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_235; // @[Parameters.scala:137:31]
assign _atomics_legal_T_235 = _GEN_98; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_289; // @[Parameters.scala:137:31]
assign _atomics_legal_T_289 = _GEN_98; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_343; // @[Parameters.scala:137:31]
assign _atomics_legal_T_343 = _GEN_98; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_397; // @[Parameters.scala:137:31]
assign _atomics_legal_T_397 = _GEN_98; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_451; // @[Parameters.scala:137:31]
assign _atomics_legal_T_451 = _GEN_98; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_40 = {1'h0, _get_legal_T_39}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_41 = _get_legal_T_40 & 41'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_42 = _get_legal_T_41; // @[Parameters.scala:137:46]
wire _get_legal_T_43 = _get_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_99 = {s2_req_addr[39:28], s2_req_addr[27:0] ^ 28'h8000000}; // @[DCache.scala:339:19]
wire [39:0] _get_legal_T_44; // @[Parameters.scala:137:31]
assign _get_legal_T_44 = _GEN_99; // @[Parameters.scala:137:31]
wire [39:0] _get_legal_T_49; // @[Parameters.scala:137:31]
assign _get_legal_T_49 = _GEN_99; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_44; // @[Parameters.scala:137:31]
assign _put_legal_T_44 = _GEN_99; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_49; // @[Parameters.scala:137:31]
assign _put_legal_T_49 = _GEN_99; // @[Parameters.scala:137:31]
wire [39:0] _putpartial_legal_T_44; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_44 = _GEN_99; // @[Parameters.scala:137:31]
wire [39:0] _putpartial_legal_T_49; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_49 = _GEN_99; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_24; // @[Parameters.scala:137:31]
assign _atomics_legal_T_24 = _GEN_99; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_29; // @[Parameters.scala:137:31]
assign _atomics_legal_T_29 = _GEN_99; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_78; // @[Parameters.scala:137:31]
assign _atomics_legal_T_78 = _GEN_99; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_83; // @[Parameters.scala:137:31]
assign _atomics_legal_T_83 = _GEN_99; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_132; // @[Parameters.scala:137:31]
assign _atomics_legal_T_132 = _GEN_99; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_137; // @[Parameters.scala:137:31]
assign _atomics_legal_T_137 = _GEN_99; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_186; // @[Parameters.scala:137:31]
assign _atomics_legal_T_186 = _GEN_99; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_191; // @[Parameters.scala:137:31]
assign _atomics_legal_T_191 = _GEN_99; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_240; // @[Parameters.scala:137:31]
assign _atomics_legal_T_240 = _GEN_99; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_245; // @[Parameters.scala:137:31]
assign _atomics_legal_T_245 = _GEN_99; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_294; // @[Parameters.scala:137:31]
assign _atomics_legal_T_294 = _GEN_99; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_299; // @[Parameters.scala:137:31]
assign _atomics_legal_T_299 = _GEN_99; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_348; // @[Parameters.scala:137:31]
assign _atomics_legal_T_348 = _GEN_99; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_353; // @[Parameters.scala:137:31]
assign _atomics_legal_T_353 = _GEN_99; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_402; // @[Parameters.scala:137:31]
assign _atomics_legal_T_402 = _GEN_99; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_407; // @[Parameters.scala:137:31]
assign _atomics_legal_T_407 = _GEN_99; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_456; // @[Parameters.scala:137:31]
assign _atomics_legal_T_456 = _GEN_99; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_461; // @[Parameters.scala:137:31]
assign _atomics_legal_T_461 = _GEN_99; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_45 = {1'h0, _get_legal_T_44}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_46 = _get_legal_T_45 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_47 = _get_legal_T_46; // @[Parameters.scala:137:46]
wire _get_legal_T_48 = _get_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _get_legal_T_50 = {1'h0, _get_legal_T_49}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_51 = _get_legal_T_50 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_52 = _get_legal_T_51; // @[Parameters.scala:137:46]
wire _get_legal_T_53 = _get_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_100 = {s2_req_addr[39:29], s2_req_addr[28:0] ^ 29'h10000000}; // @[DCache.scala:339:19]
wire [39:0] _get_legal_T_54; // @[Parameters.scala:137:31]
assign _get_legal_T_54 = _GEN_100; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_54; // @[Parameters.scala:137:31]
assign _put_legal_T_54 = _GEN_100; // @[Parameters.scala:137:31]
wire [39:0] _putpartial_legal_T_54; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_54 = _GEN_100; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_55 = {1'h0, _get_legal_T_54}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_56 = _get_legal_T_55 & 41'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_57 = _get_legal_T_56; // @[Parameters.scala:137:46]
wire _get_legal_T_58 = _get_legal_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}]
assign io_cpu_s2_paddr_0 = s2_req_addr[31:0]; // @[DCache.scala:101:7, :339:19]
wire [31:0] get_address = s2_req_addr[31:0]; // @[Edges.scala:460:17]
wire [31:0] put_address = s2_req_addr[31:0]; // @[Edges.scala:480:17]
wire [31:0] putpartial_address = s2_req_addr[31:0]; // @[Edges.scala:500:17]
wire [31:0] atomics_a_address = s2_req_addr[31:0]; // @[Edges.scala:534:17]
wire [31:0] atomics_a_1_address = s2_req_addr[31:0]; // @[Edges.scala:534:17]
wire [31:0] atomics_a_2_address = s2_req_addr[31:0]; // @[Edges.scala:534:17]
wire [31:0] atomics_a_3_address = s2_req_addr[31:0]; // @[Edges.scala:534:17]
wire [31:0] atomics_a_4_address = s2_req_addr[31:0]; // @[Edges.scala:517:17]
wire [31:0] atomics_a_5_address = s2_req_addr[31:0]; // @[Edges.scala:517:17]
wire [31:0] atomics_a_6_address = s2_req_addr[31:0]; // @[Edges.scala:517:17]
wire [31:0] atomics_a_7_address = s2_req_addr[31:0]; // @[Edges.scala:517:17]
wire [31:0] atomics_a_8_address = s2_req_addr[31:0]; // @[Edges.scala:517:17]
wire [39:0] _GEN_101 = {s2_req_addr[39:32], s2_req_addr[31:0] ^ 32'h80000000}; // @[DCache.scala:339:19]
wire [39:0] _get_legal_T_59; // @[Parameters.scala:137:31]
assign _get_legal_T_59 = _GEN_101; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_59; // @[Parameters.scala:137:31]
assign _put_legal_T_59 = _GEN_101; // @[Parameters.scala:137:31]
wire [39:0] _putpartial_legal_T_59; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_59 = _GEN_101; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_34; // @[Parameters.scala:137:31]
assign _atomics_legal_T_34 = _GEN_101; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_88; // @[Parameters.scala:137:31]
assign _atomics_legal_T_88 = _GEN_101; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_142; // @[Parameters.scala:137:31]
assign _atomics_legal_T_142 = _GEN_101; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_196; // @[Parameters.scala:137:31]
assign _atomics_legal_T_196 = _GEN_101; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_250; // @[Parameters.scala:137:31]
assign _atomics_legal_T_250 = _GEN_101; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_304; // @[Parameters.scala:137:31]
assign _atomics_legal_T_304 = _GEN_101; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_358; // @[Parameters.scala:137:31]
assign _atomics_legal_T_358 = _GEN_101; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_412; // @[Parameters.scala:137:31]
assign _atomics_legal_T_412 = _GEN_101; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_466; // @[Parameters.scala:137:31]
assign _atomics_legal_T_466 = _GEN_101; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_60 = {1'h0, _get_legal_T_59}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_61 = _get_legal_T_60 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_62 = _get_legal_T_61; // @[Parameters.scala:137:46]
wire _get_legal_T_63 = _get_legal_T_62 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _get_legal_T_64 = _get_legal_T_18 | _get_legal_T_23; // @[Parameters.scala:685:42]
wire _get_legal_T_65 = _get_legal_T_64 | _get_legal_T_28; // @[Parameters.scala:685:42]
wire _get_legal_T_66 = _get_legal_T_65 | _get_legal_T_33; // @[Parameters.scala:685:42]
wire _get_legal_T_67 = _get_legal_T_66 | _get_legal_T_38; // @[Parameters.scala:685:42]
wire _get_legal_T_68 = _get_legal_T_67 | _get_legal_T_43; // @[Parameters.scala:685:42]
wire _get_legal_T_69 = _get_legal_T_68 | _get_legal_T_48; // @[Parameters.scala:685:42]
wire _get_legal_T_70 = _get_legal_T_69 | _get_legal_T_53; // @[Parameters.scala:685:42]
wire _get_legal_T_71 = _get_legal_T_70 | _get_legal_T_58; // @[Parameters.scala:685:42]
wire _get_legal_T_72 = _get_legal_T_71 | _get_legal_T_63; // @[Parameters.scala:685:42]
wire _get_legal_T_73 = _get_legal_T_72; // @[Parameters.scala:684:54, :685:42]
wire get_legal = _get_legal_T_74 | _get_legal_T_73; // @[Parameters.scala:684:54, :686:26]
wire [7:0] _get_a_mask_T; // @[Misc.scala:222:10]
wire [3:0] get_size; // @[Edges.scala:460:17]
wire [7:0] get_mask; // @[Edges.scala:460:17]
wire [3:0] _GEN_102 = {2'h0, s2_req_size}; // @[Edges.scala:463:15]
assign get_size = _GEN_102; // @[Edges.scala:460:17, :463:15]
wire [3:0] put_size; // @[Edges.scala:480:17]
assign put_size = _GEN_102; // @[Edges.scala:463:15, :480:17]
wire [3:0] putpartial_size; // @[Edges.scala:500:17]
assign putpartial_size = _GEN_102; // @[Edges.scala:463:15, :500:17]
wire [3:0] atomics_a_size; // @[Edges.scala:534:17]
assign atomics_a_size = _GEN_102; // @[Edges.scala:463:15, :534:17]
wire [3:0] atomics_a_1_size; // @[Edges.scala:534:17]
assign atomics_a_1_size = _GEN_102; // @[Edges.scala:463:15, :534:17]
wire [3:0] atomics_a_2_size; // @[Edges.scala:534:17]
assign atomics_a_2_size = _GEN_102; // @[Edges.scala:463:15, :534:17]
wire [3:0] atomics_a_3_size; // @[Edges.scala:534:17]
assign atomics_a_3_size = _GEN_102; // @[Edges.scala:463:15, :534:17]
wire [3:0] atomics_a_4_size; // @[Edges.scala:517:17]
assign atomics_a_4_size = _GEN_102; // @[Edges.scala:463:15, :517:17]
wire [3:0] atomics_a_5_size; // @[Edges.scala:517:17]
assign atomics_a_5_size = _GEN_102; // @[Edges.scala:463:15, :517:17]
wire [3:0] atomics_a_6_size; // @[Edges.scala:517:17]
assign atomics_a_6_size = _GEN_102; // @[Edges.scala:463:15, :517:17]
wire [3:0] atomics_a_7_size; // @[Edges.scala:517:17]
assign atomics_a_7_size = _GEN_102; // @[Edges.scala:463:15, :517:17]
wire [3:0] atomics_a_8_size; // @[Edges.scala:517:17]
assign atomics_a_8_size = _GEN_102; // @[Edges.scala:463:15, :517:17]
wire [2:0] _GEN_103 = {1'h0, s2_req_size}; // @[Misc.scala:202:34]
wire [2:0] _get_a_mask_sizeOH_T; // @[Misc.scala:202:34]
assign _get_a_mask_sizeOH_T = _GEN_103; // @[Misc.scala:202:34]
wire [2:0] _put_a_mask_sizeOH_T; // @[Misc.scala:202:34]
assign _put_a_mask_sizeOH_T = _GEN_103; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T = _GEN_103; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_3; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_3 = _GEN_103; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_6; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_6 = _GEN_103; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_9; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_9 = _GEN_103; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_12; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_12 = _GEN_103; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_15; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_15 = _GEN_103; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_18; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_18 = _GEN_103; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_21; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_21 = _GEN_103; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_24; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_24 = _GEN_103; // @[Misc.scala:202:34]
wire [1:0] get_a_mask_sizeOH_shiftAmount = _get_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << get_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _get_a_mask_sizeOH_T_2 = _get_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] get_a_mask_sizeOH = {_get_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire get_a_mask_sub_sub_sub_0_1 = &s2_req_size; // @[Misc.scala:206:21]
wire get_a_mask_sub_sub_size = get_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire get_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26]
wire put_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_1 = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_2 = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_3 = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_4 = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_5 = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_6 = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_7 = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_8 = s2_req_addr[2]; // @[Misc.scala:210:26]
wire _io_cpu_resp_bits_data_shifted_T = s2_req_addr[2]; // @[Misc.scala:210:26]
wire _io_cpu_resp_bits_data_word_bypass_shifted_T = s2_req_addr[2]; // @[Misc.scala:210:26]
wire get_a_mask_sub_sub_1_2 = get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire get_a_mask_sub_sub_nbit = ~get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire get_a_mask_sub_sub_0_2 = get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_sub_sub_acc_T = get_a_mask_sub_sub_size & get_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_sub_0_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _get_a_mask_sub_sub_acc_T_1 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_sub_1_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire get_a_mask_sub_size = get_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire get_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26]
wire put_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_1 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_2 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_3 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_4 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_5 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_6 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_7 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_8 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire _io_cpu_resp_bits_data_shifted_T_3 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire get_a_mask_sub_nbit = ~get_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire get_a_mask_sub_0_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_sub_acc_T = get_a_mask_sub_size & get_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire get_a_mask_sub_1_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_sub_acc_T_1 = get_a_mask_sub_size & get_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire get_a_mask_sub_2_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_sub_acc_T_2 = get_a_mask_sub_size & get_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire get_a_mask_sub_3_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_sub_acc_T_3 = get_a_mask_sub_size & get_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire get_a_mask_size = get_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire get_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26]
wire put_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_1 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_2 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_3 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_4 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_5 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_6 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_7 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_8 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire _io_cpu_resp_bits_data_shifted_T_6 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire get_a_mask_nbit = ~get_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire get_a_mask_eq = get_a_mask_sub_0_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_acc_T = get_a_mask_size & get_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc = get_a_mask_sub_0_1 | _get_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_1 = get_a_mask_sub_0_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_acc_T_1 = get_a_mask_size & get_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_1 = get_a_mask_sub_0_1 | _get_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_2 = get_a_mask_sub_1_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_acc_T_2 = get_a_mask_size & get_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_2 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_3 = get_a_mask_sub_1_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_acc_T_3 = get_a_mask_size & get_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_3 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_4 = get_a_mask_sub_2_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_acc_T_4 = get_a_mask_size & get_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_4 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_5 = get_a_mask_sub_2_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_acc_T_5 = get_a_mask_size & get_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_5 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_6 = get_a_mask_sub_3_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_acc_T_6 = get_a_mask_size & get_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_6 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_7 = get_a_mask_sub_3_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_acc_T_7 = get_a_mask_size & get_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_7 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] get_a_mask_lo_lo = {get_a_mask_acc_1, get_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] get_a_mask_lo_hi = {get_a_mask_acc_3, get_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] get_a_mask_lo = {get_a_mask_lo_hi, get_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] get_a_mask_hi_lo = {get_a_mask_acc_5, get_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] get_a_mask_hi_hi = {get_a_mask_acc_7, get_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] get_a_mask_hi = {get_a_mask_hi_hi, get_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _get_a_mask_T = {get_a_mask_hi, get_a_mask_lo}; // @[Misc.scala:222:10]
assign get_mask = _get_a_mask_T; // @[Misc.scala:222:10]
wire [40:0] _put_legal_T_5 = {1'h0, _put_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_6 = _put_legal_T_5 & 41'h9A313000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_7 = _put_legal_T_6; // @[Parameters.scala:137:46]
wire _put_legal_T_8 = _put_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _put_legal_T_9 = _put_legal_T_8; // @[Parameters.scala:684:54]
wire _put_legal_T_81 = _put_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _put_legal_T_15 = {1'h0, _put_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_16 = _put_legal_T_15 & 41'h9A312000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_17 = _put_legal_T_16; // @[Parameters.scala:137:46]
wire _put_legal_T_18 = _put_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _put_legal_T_20 = {1'h0, _put_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_21 = _put_legal_T_20 & 41'h9A303000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_22 = _put_legal_T_21; // @[Parameters.scala:137:46]
wire _put_legal_T_23 = _put_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_104 = {s2_req_addr[39:22], s2_req_addr[21:0] ^ 22'h200000}; // @[DCache.scala:339:19]
wire [39:0] _put_legal_T_24; // @[Parameters.scala:137:31]
assign _put_legal_T_24 = _GEN_104; // @[Parameters.scala:137:31]
wire [39:0] _putpartial_legal_T_24; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_24 = _GEN_104; // @[Parameters.scala:137:31]
wire [40:0] _put_legal_T_25 = {1'h0, _put_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_26 = _put_legal_T_25 & 41'h9A313000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_27 = _put_legal_T_26; // @[Parameters.scala:137:46]
wire _put_legal_T_28 = _put_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_105 = {s2_req_addr[39:22], s2_req_addr[21:0] ^ 22'h300000}; // @[DCache.scala:339:19]
wire [39:0] _put_legal_T_29; // @[Parameters.scala:137:31]
assign _put_legal_T_29 = _GEN_105; // @[Parameters.scala:137:31]
wire [39:0] _putpartial_legal_T_29; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_29 = _GEN_105; // @[Parameters.scala:137:31]
wire [40:0] _put_legal_T_30 = {1'h0, _put_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_31 = _put_legal_T_30 & 41'h9A310000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_32 = _put_legal_T_31; // @[Parameters.scala:137:46]
wire _put_legal_T_33 = _put_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _put_legal_T_35 = {1'h0, _put_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_36 = _put_legal_T_35 & 41'h9A310000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_37 = _put_legal_T_36; // @[Parameters.scala:137:46]
wire _put_legal_T_38 = _put_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _put_legal_T_40 = {1'h0, _put_legal_T_39}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_41 = _put_legal_T_40 & 41'h9A313000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_42 = _put_legal_T_41; // @[Parameters.scala:137:46]
wire _put_legal_T_43 = _put_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _put_legal_T_45 = {1'h0, _put_legal_T_44}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_46 = _put_legal_T_45 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_47 = _put_legal_T_46; // @[Parameters.scala:137:46]
wire _put_legal_T_48 = _put_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _put_legal_T_50 = {1'h0, _put_legal_T_49}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_51 = _put_legal_T_50 & 41'h9A310000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_52 = _put_legal_T_51; // @[Parameters.scala:137:46]
wire _put_legal_T_53 = _put_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _put_legal_T_55 = {1'h0, _put_legal_T_54}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_56 = _put_legal_T_55 & 41'h9A313000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_57 = _put_legal_T_56; // @[Parameters.scala:137:46]
wire _put_legal_T_58 = _put_legal_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _put_legal_T_60 = {1'h0, _put_legal_T_59}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_61 = _put_legal_T_60 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_62 = _put_legal_T_61; // @[Parameters.scala:137:46]
wire _put_legal_T_63 = _put_legal_T_62 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _put_legal_T_64 = _put_legal_T_18 | _put_legal_T_23; // @[Parameters.scala:685:42]
wire _put_legal_T_65 = _put_legal_T_64 | _put_legal_T_28; // @[Parameters.scala:685:42]
wire _put_legal_T_66 = _put_legal_T_65 | _put_legal_T_33; // @[Parameters.scala:685:42]
wire _put_legal_T_67 = _put_legal_T_66 | _put_legal_T_38; // @[Parameters.scala:685:42]
wire _put_legal_T_68 = _put_legal_T_67 | _put_legal_T_43; // @[Parameters.scala:685:42]
wire _put_legal_T_69 = _put_legal_T_68 | _put_legal_T_48; // @[Parameters.scala:685:42]
wire _put_legal_T_70 = _put_legal_T_69 | _put_legal_T_53; // @[Parameters.scala:685:42]
wire _put_legal_T_71 = _put_legal_T_70 | _put_legal_T_58; // @[Parameters.scala:685:42]
wire _put_legal_T_72 = _put_legal_T_71 | _put_legal_T_63; // @[Parameters.scala:685:42]
wire _put_legal_T_73 = _put_legal_T_72; // @[Parameters.scala:684:54, :685:42]
wire [40:0] _put_legal_T_76 = {1'h0, _put_legal_T_75}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_77 = _put_legal_T_76 & 41'h9A310000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_78 = _put_legal_T_77; // @[Parameters.scala:137:46]
wire _put_legal_T_79 = _put_legal_T_78 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _put_legal_T_82 = _put_legal_T_81 | _put_legal_T_73; // @[Parameters.scala:684:54, :686:26]
wire put_legal = _put_legal_T_82; // @[Parameters.scala:686:26]
wire [7:0] _put_a_mask_T; // @[Misc.scala:222:10]
wire [7:0] put_mask; // @[Edges.scala:480:17]
wire [1:0] put_a_mask_sizeOH_shiftAmount = _put_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _put_a_mask_sizeOH_T_1 = 4'h1 << put_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _put_a_mask_sizeOH_T_2 = _put_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] put_a_mask_sizeOH = {_put_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire put_a_mask_sub_sub_sub_0_1 = &s2_req_size; // @[Misc.scala:206:21]
wire put_a_mask_sub_sub_size = put_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire put_a_mask_sub_sub_1_2 = put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire put_a_mask_sub_sub_nbit = ~put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire put_a_mask_sub_sub_0_2 = put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_sub_sub_acc_T = put_a_mask_sub_sub_size & put_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_sub_0_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _put_a_mask_sub_sub_acc_T_1 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_sub_1_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire put_a_mask_sub_size = put_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire put_a_mask_sub_nbit = ~put_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire put_a_mask_sub_0_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_sub_acc_T = put_a_mask_sub_size & put_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_0_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire put_a_mask_sub_1_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_sub_acc_T_1 = put_a_mask_sub_size & put_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_1_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire put_a_mask_sub_2_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_sub_acc_T_2 = put_a_mask_sub_size & put_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_2_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire put_a_mask_sub_3_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_sub_acc_T_3 = put_a_mask_sub_size & put_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_3_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire put_a_mask_size = put_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire put_a_mask_nbit = ~put_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire put_a_mask_eq = put_a_mask_sub_0_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_acc_T = put_a_mask_size & put_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc = put_a_mask_sub_0_1 | _put_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_1 = put_a_mask_sub_0_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_acc_T_1 = put_a_mask_size & put_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_1 = put_a_mask_sub_0_1 | _put_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_2 = put_a_mask_sub_1_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_acc_T_2 = put_a_mask_size & put_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_2 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_3 = put_a_mask_sub_1_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_acc_T_3 = put_a_mask_size & put_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_3 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_4 = put_a_mask_sub_2_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_acc_T_4 = put_a_mask_size & put_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_4 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_5 = put_a_mask_sub_2_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_acc_T_5 = put_a_mask_size & put_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_5 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_6 = put_a_mask_sub_3_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_acc_T_6 = put_a_mask_size & put_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_6 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_7 = put_a_mask_sub_3_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_acc_T_7 = put_a_mask_size & put_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_7 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] put_a_mask_lo_lo = {put_a_mask_acc_1, put_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] put_a_mask_lo_hi = {put_a_mask_acc_3, put_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] put_a_mask_lo = {put_a_mask_lo_hi, put_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] put_a_mask_hi_lo = {put_a_mask_acc_5, put_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] put_a_mask_hi_hi = {put_a_mask_acc_7, put_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] put_a_mask_hi = {put_a_mask_hi_hi, put_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _put_a_mask_T = {put_a_mask_hi, put_a_mask_lo}; // @[Misc.scala:222:10]
assign put_mask = _put_a_mask_T; // @[Misc.scala:222:10]
wire [40:0] _putpartial_legal_T_5 = {1'h0, _putpartial_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _putpartial_legal_T_6 = _putpartial_legal_T_5 & 41'h9A313000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _putpartial_legal_T_7 = _putpartial_legal_T_6; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_8 = _putpartial_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _putpartial_legal_T_9 = _putpartial_legal_T_8; // @[Parameters.scala:684:54]
wire _putpartial_legal_T_81 = _putpartial_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _putpartial_legal_T_15 = {1'h0, _putpartial_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _putpartial_legal_T_16 = _putpartial_legal_T_15 & 41'h9A312000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _putpartial_legal_T_17 = _putpartial_legal_T_16; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_18 = _putpartial_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _putpartial_legal_T_20 = {1'h0, _putpartial_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _putpartial_legal_T_21 = _putpartial_legal_T_20 & 41'h9A303000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _putpartial_legal_T_22 = _putpartial_legal_T_21; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_23 = _putpartial_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _putpartial_legal_T_25 = {1'h0, _putpartial_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _putpartial_legal_T_26 = _putpartial_legal_T_25 & 41'h9A313000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _putpartial_legal_T_27 = _putpartial_legal_T_26; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_28 = _putpartial_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _putpartial_legal_T_30 = {1'h0, _putpartial_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _putpartial_legal_T_31 = _putpartial_legal_T_30 & 41'h9A310000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _putpartial_legal_T_32 = _putpartial_legal_T_31; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_33 = _putpartial_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _putpartial_legal_T_35 = {1'h0, _putpartial_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _putpartial_legal_T_36 = _putpartial_legal_T_35 & 41'h9A310000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _putpartial_legal_T_37 = _putpartial_legal_T_36; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_38 = _putpartial_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _putpartial_legal_T_40 = {1'h0, _putpartial_legal_T_39}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _putpartial_legal_T_41 = _putpartial_legal_T_40 & 41'h9A313000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _putpartial_legal_T_42 = _putpartial_legal_T_41; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_43 = _putpartial_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _putpartial_legal_T_45 = {1'h0, _putpartial_legal_T_44}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _putpartial_legal_T_46 = _putpartial_legal_T_45 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _putpartial_legal_T_47 = _putpartial_legal_T_46; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_48 = _putpartial_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _putpartial_legal_T_50 = {1'h0, _putpartial_legal_T_49}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _putpartial_legal_T_51 = _putpartial_legal_T_50 & 41'h9A310000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _putpartial_legal_T_52 = _putpartial_legal_T_51; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_53 = _putpartial_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _putpartial_legal_T_55 = {1'h0, _putpartial_legal_T_54}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _putpartial_legal_T_56 = _putpartial_legal_T_55 & 41'h9A313000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _putpartial_legal_T_57 = _putpartial_legal_T_56; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_58 = _putpartial_legal_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _putpartial_legal_T_60 = {1'h0, _putpartial_legal_T_59}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _putpartial_legal_T_61 = _putpartial_legal_T_60 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _putpartial_legal_T_62 = _putpartial_legal_T_61; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_63 = _putpartial_legal_T_62 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _putpartial_legal_T_64 = _putpartial_legal_T_18 | _putpartial_legal_T_23; // @[Parameters.scala:685:42]
wire _putpartial_legal_T_65 = _putpartial_legal_T_64 | _putpartial_legal_T_28; // @[Parameters.scala:685:42]
wire _putpartial_legal_T_66 = _putpartial_legal_T_65 | _putpartial_legal_T_33; // @[Parameters.scala:685:42]
wire _putpartial_legal_T_67 = _putpartial_legal_T_66 | _putpartial_legal_T_38; // @[Parameters.scala:685:42]
wire _putpartial_legal_T_68 = _putpartial_legal_T_67 | _putpartial_legal_T_43; // @[Parameters.scala:685:42]
wire _putpartial_legal_T_69 = _putpartial_legal_T_68 | _putpartial_legal_T_48; // @[Parameters.scala:685:42]
wire _putpartial_legal_T_70 = _putpartial_legal_T_69 | _putpartial_legal_T_53; // @[Parameters.scala:685:42]
wire _putpartial_legal_T_71 = _putpartial_legal_T_70 | _putpartial_legal_T_58; // @[Parameters.scala:685:42]
wire _putpartial_legal_T_72 = _putpartial_legal_T_71 | _putpartial_legal_T_63; // @[Parameters.scala:685:42]
wire _putpartial_legal_T_73 = _putpartial_legal_T_72; // @[Parameters.scala:684:54, :685:42]
wire [40:0] _putpartial_legal_T_76 = {1'h0, _putpartial_legal_T_75}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _putpartial_legal_T_77 = _putpartial_legal_T_76 & 41'h9A310000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _putpartial_legal_T_78 = _putpartial_legal_T_77; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_79 = _putpartial_legal_T_78 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _putpartial_legal_T_82 = _putpartial_legal_T_81 | _putpartial_legal_T_73; // @[Parameters.scala:684:54, :686:26]
wire putpartial_legal = _putpartial_legal_T_82; // @[Parameters.scala:686:26]
wire [7:0] putpartial_mask; // @[Edges.scala:500:17]
assign putpartial_mask = a_mask[7:0]; // @[Edges.scala:500:17, :508:15]
wire [40:0] _atomics_legal_T_5 = {1'h0, _atomics_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_6 = _atomics_legal_T_5 & 41'h8A010000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_7 = _atomics_legal_T_6; // @[Parameters.scala:137:46]
wire _atomics_legal_T_8 = _atomics_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_10 = {1'h0, _atomics_legal_T_9}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_11 = _atomics_legal_T_10 & 41'h8A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_12 = _atomics_legal_T_11; // @[Parameters.scala:137:46]
wire _atomics_legal_T_13 = _atomics_legal_T_12 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_15 = {1'h0, _atomics_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_16 = _atomics_legal_T_15 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_17 = _atomics_legal_T_16; // @[Parameters.scala:137:46]
wire _atomics_legal_T_18 = _atomics_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_20 = {1'h0, _atomics_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_21 = _atomics_legal_T_20 & 41'h8A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_22 = _atomics_legal_T_21; // @[Parameters.scala:137:46]
wire _atomics_legal_T_23 = _atomics_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_25 = {1'h0, _atomics_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_26 = _atomics_legal_T_25 & 41'h88000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_27 = _atomics_legal_T_26; // @[Parameters.scala:137:46]
wire _atomics_legal_T_28 = _atomics_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_30 = {1'h0, _atomics_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_31 = _atomics_legal_T_30 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_32 = _atomics_legal_T_31; // @[Parameters.scala:137:46]
wire _atomics_legal_T_33 = _atomics_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_35 = {1'h0, _atomics_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_36 = _atomics_legal_T_35 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_37 = _atomics_legal_T_36; // @[Parameters.scala:137:46]
wire _atomics_legal_T_38 = _atomics_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_39 = _atomics_legal_T_8 | _atomics_legal_T_13; // @[Parameters.scala:685:42]
wire _atomics_legal_T_40 = _atomics_legal_T_39 | _atomics_legal_T_18; // @[Parameters.scala:685:42]
wire _atomics_legal_T_41 = _atomics_legal_T_40 | _atomics_legal_T_23; // @[Parameters.scala:685:42]
wire _atomics_legal_T_42 = _atomics_legal_T_41 | _atomics_legal_T_28; // @[Parameters.scala:685:42]
wire _atomics_legal_T_43 = _atomics_legal_T_42 | _atomics_legal_T_33; // @[Parameters.scala:685:42]
wire _atomics_legal_T_44 = _atomics_legal_T_43 | _atomics_legal_T_38; // @[Parameters.scala:685:42]
wire _atomics_legal_T_45 = _atomics_legal_T_44; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_53 = _atomics_legal_T_45; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_48 = {1'h0, _atomics_legal_T_47}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_49 = _atomics_legal_T_48 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_50 = _atomics_legal_T_49; // @[Parameters.scala:137:46]
wire _atomics_legal_T_51 = _atomics_legal_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal = _atomics_legal_T_53; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T; // @[Misc.scala:222:10]
wire [7:0] atomics_a_mask; // @[Edges.scala:534:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount = _atomics_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_1 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_2 = _atomics_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH = {_atomics_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size = atomics_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2 = atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit = ~atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2 = atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size = atomics_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit = ~atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T = atomics_a_mask_sub_size & atomics_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_1 = atomics_a_mask_sub_size & atomics_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_2 = atomics_a_mask_sub_size & atomics_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_3 = atomics_a_mask_sub_size & atomics_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size = atomics_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit = ~atomics_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq = atomics_a_mask_sub_0_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T = atomics_a_mask_size & atomics_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_1 = atomics_a_mask_sub_0_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_1 = atomics_a_mask_size & atomics_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_1 = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_2 = atomics_a_mask_sub_1_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_2 = atomics_a_mask_size & atomics_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_2 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_3 = atomics_a_mask_sub_1_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_3 = atomics_a_mask_size & atomics_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_3 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_4 = atomics_a_mask_sub_2_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_4 = atomics_a_mask_size & atomics_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_4 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_5 = atomics_a_mask_sub_2_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_5 = atomics_a_mask_size & atomics_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_5 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_6 = atomics_a_mask_sub_3_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_6 = atomics_a_mask_size & atomics_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_6 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_7 = atomics_a_mask_sub_3_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_7 = atomics_a_mask_size & atomics_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_7 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo = {atomics_a_mask_acc_1, atomics_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi = {atomics_a_mask_acc_3, atomics_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo = {atomics_a_mask_lo_hi, atomics_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo = {atomics_a_mask_acc_5, atomics_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi = {atomics_a_mask_acc_7, atomics_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi = {atomics_a_mask_hi_hi, atomics_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T = {atomics_a_mask_hi, atomics_a_mask_lo}; // @[Misc.scala:222:10]
assign atomics_a_mask = _atomics_a_mask_T; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_59 = {1'h0, _atomics_legal_T_58}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_60 = _atomics_legal_T_59 & 41'h8A010000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_61 = _atomics_legal_T_60; // @[Parameters.scala:137:46]
wire _atomics_legal_T_62 = _atomics_legal_T_61 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_64 = {1'h0, _atomics_legal_T_63}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_65 = _atomics_legal_T_64 & 41'h8A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_66 = _atomics_legal_T_65; // @[Parameters.scala:137:46]
wire _atomics_legal_T_67 = _atomics_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_69 = {1'h0, _atomics_legal_T_68}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_70 = _atomics_legal_T_69 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_71 = _atomics_legal_T_70; // @[Parameters.scala:137:46]
wire _atomics_legal_T_72 = _atomics_legal_T_71 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_74 = {1'h0, _atomics_legal_T_73}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_75 = _atomics_legal_T_74 & 41'h8A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_76 = _atomics_legal_T_75; // @[Parameters.scala:137:46]
wire _atomics_legal_T_77 = _atomics_legal_T_76 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_79 = {1'h0, _atomics_legal_T_78}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_80 = _atomics_legal_T_79 & 41'h88000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_81 = _atomics_legal_T_80; // @[Parameters.scala:137:46]
wire _atomics_legal_T_82 = _atomics_legal_T_81 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_84 = {1'h0, _atomics_legal_T_83}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_85 = _atomics_legal_T_84 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_86 = _atomics_legal_T_85; // @[Parameters.scala:137:46]
wire _atomics_legal_T_87 = _atomics_legal_T_86 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_89 = {1'h0, _atomics_legal_T_88}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_90 = _atomics_legal_T_89 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_91 = _atomics_legal_T_90; // @[Parameters.scala:137:46]
wire _atomics_legal_T_92 = _atomics_legal_T_91 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_93 = _atomics_legal_T_62 | _atomics_legal_T_67; // @[Parameters.scala:685:42]
wire _atomics_legal_T_94 = _atomics_legal_T_93 | _atomics_legal_T_72; // @[Parameters.scala:685:42]
wire _atomics_legal_T_95 = _atomics_legal_T_94 | _atomics_legal_T_77; // @[Parameters.scala:685:42]
wire _atomics_legal_T_96 = _atomics_legal_T_95 | _atomics_legal_T_82; // @[Parameters.scala:685:42]
wire _atomics_legal_T_97 = _atomics_legal_T_96 | _atomics_legal_T_87; // @[Parameters.scala:685:42]
wire _atomics_legal_T_98 = _atomics_legal_T_97 | _atomics_legal_T_92; // @[Parameters.scala:685:42]
wire _atomics_legal_T_99 = _atomics_legal_T_98; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_107 = _atomics_legal_T_99; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_102 = {1'h0, _atomics_legal_T_101}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_103 = _atomics_legal_T_102 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_104 = _atomics_legal_T_103; // @[Parameters.scala:137:46]
wire _atomics_legal_T_105 = _atomics_legal_T_104 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_1 = _atomics_legal_T_107; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_1; // @[Misc.scala:222:10]
wire [7:0] atomics_a_1_mask; // @[Edges.scala:534:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_1 = _atomics_a_mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_4 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_5 = _atomics_a_mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_1 = {_atomics_a_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_1 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_1 = atomics_a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_1 = atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_1 = atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_1 = atomics_a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_1 = ~atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_4 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_5 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_6 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_7 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_1 = atomics_a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_1 = ~atomics_a_mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_8 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_8 = atomics_a_mask_size_1 & atomics_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_8 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_9 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_9 = atomics_a_mask_size_1 & atomics_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_9 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_10 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_10 = atomics_a_mask_size_1 & atomics_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_10 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_11 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_11 = atomics_a_mask_size_1 & atomics_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_11 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_12 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_12 = atomics_a_mask_size_1 & atomics_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_12 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_13 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_13 = atomics_a_mask_size_1 & atomics_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_13 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_14 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_14 = atomics_a_mask_size_1 & atomics_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_14 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_15 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_15 = atomics_a_mask_size_1 & atomics_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_15 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_1 = {atomics_a_mask_acc_9, atomics_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_1 = {atomics_a_mask_acc_11, atomics_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_1 = {atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_1 = {atomics_a_mask_acc_13, atomics_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_1 = {atomics_a_mask_acc_15, atomics_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_1 = {atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_1 = {atomics_a_mask_hi_1, atomics_a_mask_lo_1}; // @[Misc.scala:222:10]
assign atomics_a_1_mask = _atomics_a_mask_T_1; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_113 = {1'h0, _atomics_legal_T_112}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_114 = _atomics_legal_T_113 & 41'h8A010000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_115 = _atomics_legal_T_114; // @[Parameters.scala:137:46]
wire _atomics_legal_T_116 = _atomics_legal_T_115 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_118 = {1'h0, _atomics_legal_T_117}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_119 = _atomics_legal_T_118 & 41'h8A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_120 = _atomics_legal_T_119; // @[Parameters.scala:137:46]
wire _atomics_legal_T_121 = _atomics_legal_T_120 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_123 = {1'h0, _atomics_legal_T_122}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_124 = _atomics_legal_T_123 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_125 = _atomics_legal_T_124; // @[Parameters.scala:137:46]
wire _atomics_legal_T_126 = _atomics_legal_T_125 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_128 = {1'h0, _atomics_legal_T_127}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_129 = _atomics_legal_T_128 & 41'h8A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_130 = _atomics_legal_T_129; // @[Parameters.scala:137:46]
wire _atomics_legal_T_131 = _atomics_legal_T_130 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_133 = {1'h0, _atomics_legal_T_132}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_134 = _atomics_legal_T_133 & 41'h88000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_135 = _atomics_legal_T_134; // @[Parameters.scala:137:46]
wire _atomics_legal_T_136 = _atomics_legal_T_135 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_138 = {1'h0, _atomics_legal_T_137}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_139 = _atomics_legal_T_138 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_140 = _atomics_legal_T_139; // @[Parameters.scala:137:46]
wire _atomics_legal_T_141 = _atomics_legal_T_140 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_143 = {1'h0, _atomics_legal_T_142}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_144 = _atomics_legal_T_143 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_145 = _atomics_legal_T_144; // @[Parameters.scala:137:46]
wire _atomics_legal_T_146 = _atomics_legal_T_145 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_147 = _atomics_legal_T_116 | _atomics_legal_T_121; // @[Parameters.scala:685:42]
wire _atomics_legal_T_148 = _atomics_legal_T_147 | _atomics_legal_T_126; // @[Parameters.scala:685:42]
wire _atomics_legal_T_149 = _atomics_legal_T_148 | _atomics_legal_T_131; // @[Parameters.scala:685:42]
wire _atomics_legal_T_150 = _atomics_legal_T_149 | _atomics_legal_T_136; // @[Parameters.scala:685:42]
wire _atomics_legal_T_151 = _atomics_legal_T_150 | _atomics_legal_T_141; // @[Parameters.scala:685:42]
wire _atomics_legal_T_152 = _atomics_legal_T_151 | _atomics_legal_T_146; // @[Parameters.scala:685:42]
wire _atomics_legal_T_153 = _atomics_legal_T_152; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_161 = _atomics_legal_T_153; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_156 = {1'h0, _atomics_legal_T_155}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_157 = _atomics_legal_T_156 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_158 = _atomics_legal_T_157; // @[Parameters.scala:137:46]
wire _atomics_legal_T_159 = _atomics_legal_T_158 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_2 = _atomics_legal_T_161; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_2; // @[Misc.scala:222:10]
wire [7:0] atomics_a_2_mask; // @[Edges.scala:534:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_2 = _atomics_a_mask_sizeOH_T_6[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_7 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_2; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_8 = _atomics_a_mask_sizeOH_T_7[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_2 = {_atomics_a_mask_sizeOH_T_8[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_2 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_2 = atomics_a_mask_sizeOH_2[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_2 = atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_2 = atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_4; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_5; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_2 = atomics_a_mask_sizeOH_2[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_2 = ~atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_8 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_9 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_10 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_11 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_2 = atomics_a_mask_sizeOH_2[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_2 = ~atomics_a_mask_bit_2; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_16 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_16 = atomics_a_mask_size_2 & atomics_a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_16 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_16; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_17 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_17 = atomics_a_mask_size_2 & atomics_a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_17 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_17; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_18 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_18 = atomics_a_mask_size_2 & atomics_a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_18 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_18; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_19 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_19 = atomics_a_mask_size_2 & atomics_a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_19 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_19; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_20 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_20 = atomics_a_mask_size_2 & atomics_a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_20 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_20; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_21 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_21 = atomics_a_mask_size_2 & atomics_a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_21 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_21; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_22 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_22 = atomics_a_mask_size_2 & atomics_a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_22 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_22; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_23 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_23 = atomics_a_mask_size_2 & atomics_a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_23 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_23; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_2 = {atomics_a_mask_acc_17, atomics_a_mask_acc_16}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_2 = {atomics_a_mask_acc_19, atomics_a_mask_acc_18}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_2 = {atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_2 = {atomics_a_mask_acc_21, atomics_a_mask_acc_20}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_2 = {atomics_a_mask_acc_23, atomics_a_mask_acc_22}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_2 = {atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_2 = {atomics_a_mask_hi_2, atomics_a_mask_lo_2}; // @[Misc.scala:222:10]
assign atomics_a_2_mask = _atomics_a_mask_T_2; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_167 = {1'h0, _atomics_legal_T_166}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_168 = _atomics_legal_T_167 & 41'h8A010000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_169 = _atomics_legal_T_168; // @[Parameters.scala:137:46]
wire _atomics_legal_T_170 = _atomics_legal_T_169 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_172 = {1'h0, _atomics_legal_T_171}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_173 = _atomics_legal_T_172 & 41'h8A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_174 = _atomics_legal_T_173; // @[Parameters.scala:137:46]
wire _atomics_legal_T_175 = _atomics_legal_T_174 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_177 = {1'h0, _atomics_legal_T_176}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_178 = _atomics_legal_T_177 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_179 = _atomics_legal_T_178; // @[Parameters.scala:137:46]
wire _atomics_legal_T_180 = _atomics_legal_T_179 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_182 = {1'h0, _atomics_legal_T_181}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_183 = _atomics_legal_T_182 & 41'h8A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_184 = _atomics_legal_T_183; // @[Parameters.scala:137:46]
wire _atomics_legal_T_185 = _atomics_legal_T_184 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_187 = {1'h0, _atomics_legal_T_186}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_188 = _atomics_legal_T_187 & 41'h88000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_189 = _atomics_legal_T_188; // @[Parameters.scala:137:46]
wire _atomics_legal_T_190 = _atomics_legal_T_189 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_192 = {1'h0, _atomics_legal_T_191}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_193 = _atomics_legal_T_192 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_194 = _atomics_legal_T_193; // @[Parameters.scala:137:46]
wire _atomics_legal_T_195 = _atomics_legal_T_194 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_197 = {1'h0, _atomics_legal_T_196}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_198 = _atomics_legal_T_197 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_199 = _atomics_legal_T_198; // @[Parameters.scala:137:46]
wire _atomics_legal_T_200 = _atomics_legal_T_199 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_201 = _atomics_legal_T_170 | _atomics_legal_T_175; // @[Parameters.scala:685:42]
wire _atomics_legal_T_202 = _atomics_legal_T_201 | _atomics_legal_T_180; // @[Parameters.scala:685:42]
wire _atomics_legal_T_203 = _atomics_legal_T_202 | _atomics_legal_T_185; // @[Parameters.scala:685:42]
wire _atomics_legal_T_204 = _atomics_legal_T_203 | _atomics_legal_T_190; // @[Parameters.scala:685:42]
wire _atomics_legal_T_205 = _atomics_legal_T_204 | _atomics_legal_T_195; // @[Parameters.scala:685:42]
wire _atomics_legal_T_206 = _atomics_legal_T_205 | _atomics_legal_T_200; // @[Parameters.scala:685:42]
wire _atomics_legal_T_207 = _atomics_legal_T_206; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_215 = _atomics_legal_T_207; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_210 = {1'h0, _atomics_legal_T_209}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_211 = _atomics_legal_T_210 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_212 = _atomics_legal_T_211; // @[Parameters.scala:137:46]
wire _atomics_legal_T_213 = _atomics_legal_T_212 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_3 = _atomics_legal_T_215; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_3; // @[Misc.scala:222:10]
wire [7:0] atomics_a_3_mask; // @[Edges.scala:534:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_3 = _atomics_a_mask_sizeOH_T_9[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_10 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_3; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_11 = _atomics_a_mask_sizeOH_T_10[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_3 = {_atomics_a_mask_sizeOH_T_11[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_3 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_3 = atomics_a_mask_sizeOH_3[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_3 = atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_3 = atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_6; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_7; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_3 = atomics_a_mask_sizeOH_3[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_3 = ~atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_12 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_13 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_14 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_15 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_3 = atomics_a_mask_sizeOH_3[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_3 = ~atomics_a_mask_bit_3; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_24 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_24 = atomics_a_mask_size_3 & atomics_a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_24 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_24; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_25 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_25 = atomics_a_mask_size_3 & atomics_a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_25 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_25; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_26 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_26 = atomics_a_mask_size_3 & atomics_a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_26 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_26; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_27 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_27 = atomics_a_mask_size_3 & atomics_a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_27 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_27; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_28 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_28 = atomics_a_mask_size_3 & atomics_a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_28 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_28; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_29 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_29 = atomics_a_mask_size_3 & atomics_a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_29 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_29; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_30 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_30 = atomics_a_mask_size_3 & atomics_a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_30 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_30; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_31 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_31 = atomics_a_mask_size_3 & atomics_a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_31 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_31; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_3 = {atomics_a_mask_acc_25, atomics_a_mask_acc_24}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_3 = {atomics_a_mask_acc_27, atomics_a_mask_acc_26}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_3 = {atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_3 = {atomics_a_mask_acc_29, atomics_a_mask_acc_28}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_3 = {atomics_a_mask_acc_31, atomics_a_mask_acc_30}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_3 = {atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_3 = {atomics_a_mask_hi_3, atomics_a_mask_lo_3}; // @[Misc.scala:222:10]
assign atomics_a_3_mask = _atomics_a_mask_T_3; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_221 = {1'h0, _atomics_legal_T_220}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_222 = _atomics_legal_T_221 & 41'h8A010000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_223 = _atomics_legal_T_222; // @[Parameters.scala:137:46]
wire _atomics_legal_T_224 = _atomics_legal_T_223 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_226 = {1'h0, _atomics_legal_T_225}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_227 = _atomics_legal_T_226 & 41'h8A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_228 = _atomics_legal_T_227; // @[Parameters.scala:137:46]
wire _atomics_legal_T_229 = _atomics_legal_T_228 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_231 = {1'h0, _atomics_legal_T_230}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_232 = _atomics_legal_T_231 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_233 = _atomics_legal_T_232; // @[Parameters.scala:137:46]
wire _atomics_legal_T_234 = _atomics_legal_T_233 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_236 = {1'h0, _atomics_legal_T_235}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_237 = _atomics_legal_T_236 & 41'h8A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_238 = _atomics_legal_T_237; // @[Parameters.scala:137:46]
wire _atomics_legal_T_239 = _atomics_legal_T_238 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_241 = {1'h0, _atomics_legal_T_240}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_242 = _atomics_legal_T_241 & 41'h88000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_243 = _atomics_legal_T_242; // @[Parameters.scala:137:46]
wire _atomics_legal_T_244 = _atomics_legal_T_243 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_246 = {1'h0, _atomics_legal_T_245}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_247 = _atomics_legal_T_246 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_248 = _atomics_legal_T_247; // @[Parameters.scala:137:46]
wire _atomics_legal_T_249 = _atomics_legal_T_248 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_251 = {1'h0, _atomics_legal_T_250}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_252 = _atomics_legal_T_251 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_253 = _atomics_legal_T_252; // @[Parameters.scala:137:46]
wire _atomics_legal_T_254 = _atomics_legal_T_253 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_255 = _atomics_legal_T_224 | _atomics_legal_T_229; // @[Parameters.scala:685:42]
wire _atomics_legal_T_256 = _atomics_legal_T_255 | _atomics_legal_T_234; // @[Parameters.scala:685:42]
wire _atomics_legal_T_257 = _atomics_legal_T_256 | _atomics_legal_T_239; // @[Parameters.scala:685:42]
wire _atomics_legal_T_258 = _atomics_legal_T_257 | _atomics_legal_T_244; // @[Parameters.scala:685:42]
wire _atomics_legal_T_259 = _atomics_legal_T_258 | _atomics_legal_T_249; // @[Parameters.scala:685:42]
wire _atomics_legal_T_260 = _atomics_legal_T_259 | _atomics_legal_T_254; // @[Parameters.scala:685:42]
wire _atomics_legal_T_261 = _atomics_legal_T_260; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_269 = _atomics_legal_T_261; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_264 = {1'h0, _atomics_legal_T_263}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_265 = _atomics_legal_T_264 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_266 = _atomics_legal_T_265; // @[Parameters.scala:137:46]
wire _atomics_legal_T_267 = _atomics_legal_T_266 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_4 = _atomics_legal_T_269; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_4; // @[Misc.scala:222:10]
wire [7:0] atomics_a_4_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_4 = _atomics_a_mask_sizeOH_T_12[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_13 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_4; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_14 = _atomics_a_mask_sizeOH_T_13[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_4 = {_atomics_a_mask_sizeOH_T_14[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_4 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_4 = atomics_a_mask_sizeOH_4[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_4 = atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_4 = atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_8; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_9; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_4 = atomics_a_mask_sizeOH_4[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_4 = ~atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_16 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_17 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_18 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_19 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_4 = atomics_a_mask_sizeOH_4[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_4 = ~atomics_a_mask_bit_4; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_32 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_32 = atomics_a_mask_size_4 & atomics_a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_32 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_32; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_33 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_33 = atomics_a_mask_size_4 & atomics_a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_33 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_33; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_34 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_34 = atomics_a_mask_size_4 & atomics_a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_34 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_34; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_35 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_35 = atomics_a_mask_size_4 & atomics_a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_35 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_35; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_36 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_36 = atomics_a_mask_size_4 & atomics_a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_36 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_36; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_37 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_37 = atomics_a_mask_size_4 & atomics_a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_37 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_37; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_38 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_38 = atomics_a_mask_size_4 & atomics_a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_38 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_38; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_39 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_39 = atomics_a_mask_size_4 & atomics_a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_39 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_39; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_4 = {atomics_a_mask_acc_33, atomics_a_mask_acc_32}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_4 = {atomics_a_mask_acc_35, atomics_a_mask_acc_34}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_4 = {atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_4 = {atomics_a_mask_acc_37, atomics_a_mask_acc_36}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_4 = {atomics_a_mask_acc_39, atomics_a_mask_acc_38}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_4 = {atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_4 = {atomics_a_mask_hi_4, atomics_a_mask_lo_4}; // @[Misc.scala:222:10]
assign atomics_a_4_mask = _atomics_a_mask_T_4; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_275 = {1'h0, _atomics_legal_T_274}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_276 = _atomics_legal_T_275 & 41'h8A010000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_277 = _atomics_legal_T_276; // @[Parameters.scala:137:46]
wire _atomics_legal_T_278 = _atomics_legal_T_277 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_280 = {1'h0, _atomics_legal_T_279}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_281 = _atomics_legal_T_280 & 41'h8A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_282 = _atomics_legal_T_281; // @[Parameters.scala:137:46]
wire _atomics_legal_T_283 = _atomics_legal_T_282 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_285 = {1'h0, _atomics_legal_T_284}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_286 = _atomics_legal_T_285 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_287 = _atomics_legal_T_286; // @[Parameters.scala:137:46]
wire _atomics_legal_T_288 = _atomics_legal_T_287 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_290 = {1'h0, _atomics_legal_T_289}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_291 = _atomics_legal_T_290 & 41'h8A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_292 = _atomics_legal_T_291; // @[Parameters.scala:137:46]
wire _atomics_legal_T_293 = _atomics_legal_T_292 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_295 = {1'h0, _atomics_legal_T_294}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_296 = _atomics_legal_T_295 & 41'h88000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_297 = _atomics_legal_T_296; // @[Parameters.scala:137:46]
wire _atomics_legal_T_298 = _atomics_legal_T_297 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_300 = {1'h0, _atomics_legal_T_299}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_301 = _atomics_legal_T_300 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_302 = _atomics_legal_T_301; // @[Parameters.scala:137:46]
wire _atomics_legal_T_303 = _atomics_legal_T_302 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_305 = {1'h0, _atomics_legal_T_304}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_306 = _atomics_legal_T_305 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_307 = _atomics_legal_T_306; // @[Parameters.scala:137:46]
wire _atomics_legal_T_308 = _atomics_legal_T_307 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_309 = _atomics_legal_T_278 | _atomics_legal_T_283; // @[Parameters.scala:685:42]
wire _atomics_legal_T_310 = _atomics_legal_T_309 | _atomics_legal_T_288; // @[Parameters.scala:685:42]
wire _atomics_legal_T_311 = _atomics_legal_T_310 | _atomics_legal_T_293; // @[Parameters.scala:685:42]
wire _atomics_legal_T_312 = _atomics_legal_T_311 | _atomics_legal_T_298; // @[Parameters.scala:685:42]
wire _atomics_legal_T_313 = _atomics_legal_T_312 | _atomics_legal_T_303; // @[Parameters.scala:685:42]
wire _atomics_legal_T_314 = _atomics_legal_T_313 | _atomics_legal_T_308; // @[Parameters.scala:685:42]
wire _atomics_legal_T_315 = _atomics_legal_T_314; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_323 = _atomics_legal_T_315; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_318 = {1'h0, _atomics_legal_T_317}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_319 = _atomics_legal_T_318 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_320 = _atomics_legal_T_319; // @[Parameters.scala:137:46]
wire _atomics_legal_T_321 = _atomics_legal_T_320 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_5 = _atomics_legal_T_323; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_5; // @[Misc.scala:222:10]
wire [7:0] atomics_a_5_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_5 = _atomics_a_mask_sizeOH_T_15[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_16 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_5; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_17 = _atomics_a_mask_sizeOH_T_16[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_5 = {_atomics_a_mask_sizeOH_T_17[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_5 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_5 = atomics_a_mask_sizeOH_5[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_5 = atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_5 = atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_10; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_11; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_5 = atomics_a_mask_sizeOH_5[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_5 = ~atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_20 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_21 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_22 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_23 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_5 = atomics_a_mask_sizeOH_5[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_5 = ~atomics_a_mask_bit_5; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_40 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_40 = atomics_a_mask_size_5 & atomics_a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_40 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_40; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_41 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_41 = atomics_a_mask_size_5 & atomics_a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_41 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_41; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_42 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_42 = atomics_a_mask_size_5 & atomics_a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_42 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_42; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_43 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_43 = atomics_a_mask_size_5 & atomics_a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_43 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_43; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_44 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_44 = atomics_a_mask_size_5 & atomics_a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_44 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_44; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_45 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_45 = atomics_a_mask_size_5 & atomics_a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_45 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_45; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_46 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_46 = atomics_a_mask_size_5 & atomics_a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_46 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_46; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_47 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_47 = atomics_a_mask_size_5 & atomics_a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_47 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_47; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_5 = {atomics_a_mask_acc_41, atomics_a_mask_acc_40}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_5 = {atomics_a_mask_acc_43, atomics_a_mask_acc_42}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_5 = {atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_5 = {atomics_a_mask_acc_45, atomics_a_mask_acc_44}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_5 = {atomics_a_mask_acc_47, atomics_a_mask_acc_46}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_5 = {atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_5 = {atomics_a_mask_hi_5, atomics_a_mask_lo_5}; // @[Misc.scala:222:10]
assign atomics_a_5_mask = _atomics_a_mask_T_5; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_329 = {1'h0, _atomics_legal_T_328}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_330 = _atomics_legal_T_329 & 41'h8A010000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_331 = _atomics_legal_T_330; // @[Parameters.scala:137:46]
wire _atomics_legal_T_332 = _atomics_legal_T_331 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_334 = {1'h0, _atomics_legal_T_333}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_335 = _atomics_legal_T_334 & 41'h8A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_336 = _atomics_legal_T_335; // @[Parameters.scala:137:46]
wire _atomics_legal_T_337 = _atomics_legal_T_336 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_339 = {1'h0, _atomics_legal_T_338}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_340 = _atomics_legal_T_339 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_341 = _atomics_legal_T_340; // @[Parameters.scala:137:46]
wire _atomics_legal_T_342 = _atomics_legal_T_341 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_344 = {1'h0, _atomics_legal_T_343}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_345 = _atomics_legal_T_344 & 41'h8A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_346 = _atomics_legal_T_345; // @[Parameters.scala:137:46]
wire _atomics_legal_T_347 = _atomics_legal_T_346 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_349 = {1'h0, _atomics_legal_T_348}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_350 = _atomics_legal_T_349 & 41'h88000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_351 = _atomics_legal_T_350; // @[Parameters.scala:137:46]
wire _atomics_legal_T_352 = _atomics_legal_T_351 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_354 = {1'h0, _atomics_legal_T_353}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_355 = _atomics_legal_T_354 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_356 = _atomics_legal_T_355; // @[Parameters.scala:137:46]
wire _atomics_legal_T_357 = _atomics_legal_T_356 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_359 = {1'h0, _atomics_legal_T_358}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_360 = _atomics_legal_T_359 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_361 = _atomics_legal_T_360; // @[Parameters.scala:137:46]
wire _atomics_legal_T_362 = _atomics_legal_T_361 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_363 = _atomics_legal_T_332 | _atomics_legal_T_337; // @[Parameters.scala:685:42]
wire _atomics_legal_T_364 = _atomics_legal_T_363 | _atomics_legal_T_342; // @[Parameters.scala:685:42]
wire _atomics_legal_T_365 = _atomics_legal_T_364 | _atomics_legal_T_347; // @[Parameters.scala:685:42]
wire _atomics_legal_T_366 = _atomics_legal_T_365 | _atomics_legal_T_352; // @[Parameters.scala:685:42]
wire _atomics_legal_T_367 = _atomics_legal_T_366 | _atomics_legal_T_357; // @[Parameters.scala:685:42]
wire _atomics_legal_T_368 = _atomics_legal_T_367 | _atomics_legal_T_362; // @[Parameters.scala:685:42]
wire _atomics_legal_T_369 = _atomics_legal_T_368; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_377 = _atomics_legal_T_369; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_372 = {1'h0, _atomics_legal_T_371}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_373 = _atomics_legal_T_372 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_374 = _atomics_legal_T_373; // @[Parameters.scala:137:46]
wire _atomics_legal_T_375 = _atomics_legal_T_374 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_6 = _atomics_legal_T_377; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_6; // @[Misc.scala:222:10]
wire [7:0] atomics_a_6_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_6 = _atomics_a_mask_sizeOH_T_18[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_19 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_6; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_20 = _atomics_a_mask_sizeOH_T_19[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_6 = {_atomics_a_mask_sizeOH_T_20[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_6 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_6 = atomics_a_mask_sizeOH_6[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_6 = atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_6 = atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_12; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_13; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_6 = atomics_a_mask_sizeOH_6[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_6 = ~atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_24 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_25 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_26 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_27 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_6 = atomics_a_mask_sizeOH_6[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_6 = ~atomics_a_mask_bit_6; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_48 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_48 = atomics_a_mask_size_6 & atomics_a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_48 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_48; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_49 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_49 = atomics_a_mask_size_6 & atomics_a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_49 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_49; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_50 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_50 = atomics_a_mask_size_6 & atomics_a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_50 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_50; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_51 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_51 = atomics_a_mask_size_6 & atomics_a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_51 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_51; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_52 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_52 = atomics_a_mask_size_6 & atomics_a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_52 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_52; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_53 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_53 = atomics_a_mask_size_6 & atomics_a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_53 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_53; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_54 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_54 = atomics_a_mask_size_6 & atomics_a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_54 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_54; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_55 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_55 = atomics_a_mask_size_6 & atomics_a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_55 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_55; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_6 = {atomics_a_mask_acc_49, atomics_a_mask_acc_48}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_6 = {atomics_a_mask_acc_51, atomics_a_mask_acc_50}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_6 = {atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_6 = {atomics_a_mask_acc_53, atomics_a_mask_acc_52}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_6 = {atomics_a_mask_acc_55, atomics_a_mask_acc_54}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_6 = {atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_6 = {atomics_a_mask_hi_6, atomics_a_mask_lo_6}; // @[Misc.scala:222:10]
assign atomics_a_6_mask = _atomics_a_mask_T_6; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_383 = {1'h0, _atomics_legal_T_382}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_384 = _atomics_legal_T_383 & 41'h8A010000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_385 = _atomics_legal_T_384; // @[Parameters.scala:137:46]
wire _atomics_legal_T_386 = _atomics_legal_T_385 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_388 = {1'h0, _atomics_legal_T_387}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_389 = _atomics_legal_T_388 & 41'h8A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_390 = _atomics_legal_T_389; // @[Parameters.scala:137:46]
wire _atomics_legal_T_391 = _atomics_legal_T_390 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_393 = {1'h0, _atomics_legal_T_392}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_394 = _atomics_legal_T_393 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_395 = _atomics_legal_T_394; // @[Parameters.scala:137:46]
wire _atomics_legal_T_396 = _atomics_legal_T_395 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_398 = {1'h0, _atomics_legal_T_397}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_399 = _atomics_legal_T_398 & 41'h8A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_400 = _atomics_legal_T_399; // @[Parameters.scala:137:46]
wire _atomics_legal_T_401 = _atomics_legal_T_400 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_403 = {1'h0, _atomics_legal_T_402}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_404 = _atomics_legal_T_403 & 41'h88000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_405 = _atomics_legal_T_404; // @[Parameters.scala:137:46]
wire _atomics_legal_T_406 = _atomics_legal_T_405 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_408 = {1'h0, _atomics_legal_T_407}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_409 = _atomics_legal_T_408 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_410 = _atomics_legal_T_409; // @[Parameters.scala:137:46]
wire _atomics_legal_T_411 = _atomics_legal_T_410 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_413 = {1'h0, _atomics_legal_T_412}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_414 = _atomics_legal_T_413 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_415 = _atomics_legal_T_414; // @[Parameters.scala:137:46]
wire _atomics_legal_T_416 = _atomics_legal_T_415 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_417 = _atomics_legal_T_386 | _atomics_legal_T_391; // @[Parameters.scala:685:42]
wire _atomics_legal_T_418 = _atomics_legal_T_417 | _atomics_legal_T_396; // @[Parameters.scala:685:42]
wire _atomics_legal_T_419 = _atomics_legal_T_418 | _atomics_legal_T_401; // @[Parameters.scala:685:42]
wire _atomics_legal_T_420 = _atomics_legal_T_419 | _atomics_legal_T_406; // @[Parameters.scala:685:42]
wire _atomics_legal_T_421 = _atomics_legal_T_420 | _atomics_legal_T_411; // @[Parameters.scala:685:42]
wire _atomics_legal_T_422 = _atomics_legal_T_421 | _atomics_legal_T_416; // @[Parameters.scala:685:42]
wire _atomics_legal_T_423 = _atomics_legal_T_422; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_431 = _atomics_legal_T_423; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_426 = {1'h0, _atomics_legal_T_425}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_427 = _atomics_legal_T_426 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_428 = _atomics_legal_T_427; // @[Parameters.scala:137:46]
wire _atomics_legal_T_429 = _atomics_legal_T_428 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_7 = _atomics_legal_T_431; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_7; // @[Misc.scala:222:10]
wire [7:0] atomics_a_7_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_7 = _atomics_a_mask_sizeOH_T_21[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_22 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_7; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_23 = _atomics_a_mask_sizeOH_T_22[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_7 = {_atomics_a_mask_sizeOH_T_23[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_7 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_7 = atomics_a_mask_sizeOH_7[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_7 = atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_7 = atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_14; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_15; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_7 = atomics_a_mask_sizeOH_7[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_7 = ~atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_28 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_29 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_30 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_31 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_7 = atomics_a_mask_sizeOH_7[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_7 = ~atomics_a_mask_bit_7; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_56 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_56 = atomics_a_mask_size_7 & atomics_a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_56 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_56; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_57 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_57 = atomics_a_mask_size_7 & atomics_a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_57 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_57; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_58 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_58 = atomics_a_mask_size_7 & atomics_a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_58 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_58; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_59 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_59 = atomics_a_mask_size_7 & atomics_a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_59 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_59; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_60 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_60 = atomics_a_mask_size_7 & atomics_a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_60 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_60; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_61 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_61 = atomics_a_mask_size_7 & atomics_a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_61 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_61; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_62 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_62 = atomics_a_mask_size_7 & atomics_a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_62 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_62; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_63 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_63 = atomics_a_mask_size_7 & atomics_a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_63 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_63; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_7 = {atomics_a_mask_acc_57, atomics_a_mask_acc_56}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_7 = {atomics_a_mask_acc_59, atomics_a_mask_acc_58}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_7 = {atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_7 = {atomics_a_mask_acc_61, atomics_a_mask_acc_60}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_7 = {atomics_a_mask_acc_63, atomics_a_mask_acc_62}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_7 = {atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_7 = {atomics_a_mask_hi_7, atomics_a_mask_lo_7}; // @[Misc.scala:222:10]
assign atomics_a_7_mask = _atomics_a_mask_T_7; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_437 = {1'h0, _atomics_legal_T_436}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_438 = _atomics_legal_T_437 & 41'h8A010000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_439 = _atomics_legal_T_438; // @[Parameters.scala:137:46]
wire _atomics_legal_T_440 = _atomics_legal_T_439 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_442 = {1'h0, _atomics_legal_T_441}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_443 = _atomics_legal_T_442 & 41'h8A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_444 = _atomics_legal_T_443; // @[Parameters.scala:137:46]
wire _atomics_legal_T_445 = _atomics_legal_T_444 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_447 = {1'h0, _atomics_legal_T_446}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_448 = _atomics_legal_T_447 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_449 = _atomics_legal_T_448; // @[Parameters.scala:137:46]
wire _atomics_legal_T_450 = _atomics_legal_T_449 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_452 = {1'h0, _atomics_legal_T_451}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_453 = _atomics_legal_T_452 & 41'h8A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_454 = _atomics_legal_T_453; // @[Parameters.scala:137:46]
wire _atomics_legal_T_455 = _atomics_legal_T_454 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_457 = {1'h0, _atomics_legal_T_456}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_458 = _atomics_legal_T_457 & 41'h88000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_459 = _atomics_legal_T_458; // @[Parameters.scala:137:46]
wire _atomics_legal_T_460 = _atomics_legal_T_459 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_462 = {1'h0, _atomics_legal_T_461}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_463 = _atomics_legal_T_462 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_464 = _atomics_legal_T_463; // @[Parameters.scala:137:46]
wire _atomics_legal_T_465 = _atomics_legal_T_464 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_467 = {1'h0, _atomics_legal_T_466}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_468 = _atomics_legal_T_467 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_469 = _atomics_legal_T_468; // @[Parameters.scala:137:46]
wire _atomics_legal_T_470 = _atomics_legal_T_469 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_471 = _atomics_legal_T_440 | _atomics_legal_T_445; // @[Parameters.scala:685:42]
wire _atomics_legal_T_472 = _atomics_legal_T_471 | _atomics_legal_T_450; // @[Parameters.scala:685:42]
wire _atomics_legal_T_473 = _atomics_legal_T_472 | _atomics_legal_T_455; // @[Parameters.scala:685:42]
wire _atomics_legal_T_474 = _atomics_legal_T_473 | _atomics_legal_T_460; // @[Parameters.scala:685:42]
wire _atomics_legal_T_475 = _atomics_legal_T_474 | _atomics_legal_T_465; // @[Parameters.scala:685:42]
wire _atomics_legal_T_476 = _atomics_legal_T_475 | _atomics_legal_T_470; // @[Parameters.scala:685:42]
wire _atomics_legal_T_477 = _atomics_legal_T_476; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_485 = _atomics_legal_T_477; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_480 = {1'h0, _atomics_legal_T_479}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_481 = _atomics_legal_T_480 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_482 = _atomics_legal_T_481; // @[Parameters.scala:137:46]
wire _atomics_legal_T_483 = _atomics_legal_T_482 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_8 = _atomics_legal_T_485; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_8; // @[Misc.scala:222:10]
wire [7:0] atomics_a_8_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_8 = _atomics_a_mask_sizeOH_T_24[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_25 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_8; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_26 = _atomics_a_mask_sizeOH_T_25[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_8 = {_atomics_a_mask_sizeOH_T_26[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_8 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_8 = atomics_a_mask_sizeOH_8[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_8 = atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_8 = atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_16; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_17; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_8 = atomics_a_mask_sizeOH_8[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_8 = ~atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_32 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_32; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_33 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_33; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_34 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_34; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_35 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_35; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_8 = atomics_a_mask_sizeOH_8[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_8 = ~atomics_a_mask_bit_8; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_64 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_64 = atomics_a_mask_size_8 & atomics_a_mask_eq_64; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_64 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_64; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_65 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_65 = atomics_a_mask_size_8 & atomics_a_mask_eq_65; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_65 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_65; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_66 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_66 = atomics_a_mask_size_8 & atomics_a_mask_eq_66; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_66 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_66; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_67 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_67 = atomics_a_mask_size_8 & atomics_a_mask_eq_67; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_67 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_67; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_68 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_68 = atomics_a_mask_size_8 & atomics_a_mask_eq_68; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_68 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_68; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_69 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_69 = atomics_a_mask_size_8 & atomics_a_mask_eq_69; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_69 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_69; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_70 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_70 = atomics_a_mask_size_8 & atomics_a_mask_eq_70; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_70 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_70; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_71 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_71 = atomics_a_mask_size_8 & atomics_a_mask_eq_71; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_71 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_71; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_8 = {atomics_a_mask_acc_65, atomics_a_mask_acc_64}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_8 = {atomics_a_mask_acc_67, atomics_a_mask_acc_66}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_8 = {atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_8 = {atomics_a_mask_acc_69, atomics_a_mask_acc_68}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_8 = {atomics_a_mask_acc_71, atomics_a_mask_acc_70}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_8 = {atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_8 = {atomics_a_mask_hi_8, atomics_a_mask_lo_8}; // @[Misc.scala:222:10]
assign atomics_a_8_mask = _atomics_a_mask_T_8; // @[Misc.scala:222:10]
wire [2:0] _GEN_106 = _atomics_T ? 3'h3 : 3'h0; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_1_opcode; // @[DCache.scala:587:81]
assign _atomics_T_1_opcode = _GEN_106; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_1_param; // @[DCache.scala:587:81]
assign _atomics_T_1_param = _GEN_106; // @[DCache.scala:587:81]
wire [3:0] _atomics_T_1_size = _atomics_T ? atomics_a_size : 4'h0; // @[Edges.scala:534:17]
wire [31:0] _atomics_T_1_address = _atomics_T ? atomics_a_address : 32'h0; // @[Edges.scala:534:17]
wire [7:0] _atomics_T_1_mask = _atomics_T ? atomics_a_mask : 8'h0; // @[Edges.scala:534:17]
wire [63:0] _atomics_T_1_data = _atomics_T ? atomics_a_data : 64'h0; // @[Edges.scala:534:17]
wire [2:0] _atomics_T_3_opcode = _atomics_T_2 ? 3'h3 : _atomics_T_1_opcode; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_3_param = _atomics_T_2 ? 3'h0 : _atomics_T_1_param; // @[DCache.scala:587:81]
wire [3:0] _atomics_T_3_size = _atomics_T_2 ? atomics_a_1_size : _atomics_T_1_size; // @[Edges.scala:534:17]
wire [31:0] _atomics_T_3_address = _atomics_T_2 ? atomics_a_1_address : _atomics_T_1_address; // @[Edges.scala:534:17]
wire [7:0] _atomics_T_3_mask = _atomics_T_2 ? atomics_a_1_mask : _atomics_T_1_mask; // @[Edges.scala:534:17]
wire [63:0] _atomics_T_3_data = _atomics_T_2 ? atomics_a_1_data : _atomics_T_1_data; // @[Edges.scala:534:17]
wire [2:0] _atomics_T_5_opcode = _atomics_T_4 ? 3'h3 : _atomics_T_3_opcode; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_5_param = _atomics_T_4 ? 3'h1 : _atomics_T_3_param; // @[DCache.scala:587:81]
wire [3:0] _atomics_T_5_size = _atomics_T_4 ? atomics_a_2_size : _atomics_T_3_size; // @[Edges.scala:534:17]
wire [31:0] _atomics_T_5_address = _atomics_T_4 ? atomics_a_2_address : _atomics_T_3_address; // @[Edges.scala:534:17]
wire [7:0] _atomics_T_5_mask = _atomics_T_4 ? atomics_a_2_mask : _atomics_T_3_mask; // @[Edges.scala:534:17]
wire [63:0] _atomics_T_5_data = _atomics_T_4 ? atomics_a_2_data : _atomics_T_3_data; // @[Edges.scala:534:17]
wire [2:0] _atomics_T_7_opcode = _atomics_T_6 ? 3'h3 : _atomics_T_5_opcode; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_7_param = _atomics_T_6 ? 3'h2 : _atomics_T_5_param; // @[DCache.scala:587:81]
wire [3:0] _atomics_T_7_size = _atomics_T_6 ? atomics_a_3_size : _atomics_T_5_size; // @[Edges.scala:534:17]
wire [31:0] _atomics_T_7_address = _atomics_T_6 ? atomics_a_3_address : _atomics_T_5_address; // @[Edges.scala:534:17]
wire [7:0] _atomics_T_7_mask = _atomics_T_6 ? atomics_a_3_mask : _atomics_T_5_mask; // @[Edges.scala:534:17]
wire [63:0] _atomics_T_7_data = _atomics_T_6 ? atomics_a_3_data : _atomics_T_5_data; // @[Edges.scala:534:17]
wire [2:0] _atomics_T_9_opcode = _atomics_T_8 ? 3'h2 : _atomics_T_7_opcode; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_9_param = _atomics_T_8 ? 3'h4 : _atomics_T_7_param; // @[DCache.scala:587:81]
wire [3:0] _atomics_T_9_size = _atomics_T_8 ? atomics_a_4_size : _atomics_T_7_size; // @[Edges.scala:517:17]
wire [31:0] _atomics_T_9_address = _atomics_T_8 ? atomics_a_4_address : _atomics_T_7_address; // @[Edges.scala:517:17]
wire [7:0] _atomics_T_9_mask = _atomics_T_8 ? atomics_a_4_mask : _atomics_T_7_mask; // @[Edges.scala:517:17]
wire [63:0] _atomics_T_9_data = _atomics_T_8 ? atomics_a_4_data : _atomics_T_7_data; // @[Edges.scala:517:17]
wire [2:0] _atomics_T_11_opcode = _atomics_T_10 ? 3'h2 : _atomics_T_9_opcode; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_11_param = _atomics_T_10 ? 3'h0 : _atomics_T_9_param; // @[DCache.scala:587:81]
wire [3:0] _atomics_T_11_size = _atomics_T_10 ? atomics_a_5_size : _atomics_T_9_size; // @[Edges.scala:517:17]
wire [31:0] _atomics_T_11_address = _atomics_T_10 ? atomics_a_5_address : _atomics_T_9_address; // @[Edges.scala:517:17]
wire [7:0] _atomics_T_11_mask = _atomics_T_10 ? atomics_a_5_mask : _atomics_T_9_mask; // @[Edges.scala:517:17]
wire [63:0] _atomics_T_11_data = _atomics_T_10 ? atomics_a_5_data : _atomics_T_9_data; // @[Edges.scala:517:17]
wire [2:0] _atomics_T_13_opcode = _atomics_T_12 ? 3'h2 : _atomics_T_11_opcode; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_13_param = _atomics_T_12 ? 3'h1 : _atomics_T_11_param; // @[DCache.scala:587:81]
wire [3:0] _atomics_T_13_size = _atomics_T_12 ? atomics_a_6_size : _atomics_T_11_size; // @[Edges.scala:517:17]
wire [31:0] _atomics_T_13_address = _atomics_T_12 ? atomics_a_6_address : _atomics_T_11_address; // @[Edges.scala:517:17]
wire [7:0] _atomics_T_13_mask = _atomics_T_12 ? atomics_a_6_mask : _atomics_T_11_mask; // @[Edges.scala:517:17]
wire [63:0] _atomics_T_13_data = _atomics_T_12 ? atomics_a_6_data : _atomics_T_11_data; // @[Edges.scala:517:17]
wire [2:0] _atomics_T_15_opcode = _atomics_T_14 ? 3'h2 : _atomics_T_13_opcode; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_15_param = _atomics_T_14 ? 3'h2 : _atomics_T_13_param; // @[DCache.scala:587:81]
wire [3:0] _atomics_T_15_size = _atomics_T_14 ? atomics_a_7_size : _atomics_T_13_size; // @[Edges.scala:517:17]
wire [31:0] _atomics_T_15_address = _atomics_T_14 ? atomics_a_7_address : _atomics_T_13_address; // @[Edges.scala:517:17]
wire [7:0] _atomics_T_15_mask = _atomics_T_14 ? atomics_a_7_mask : _atomics_T_13_mask; // @[Edges.scala:517:17]
wire [63:0] _atomics_T_15_data = _atomics_T_14 ? atomics_a_7_data : _atomics_T_13_data; // @[Edges.scala:517:17]
wire [2:0] atomics_opcode = _atomics_T_16 ? 3'h2 : _atomics_T_15_opcode; // @[DCache.scala:587:81]
wire [2:0] atomics_param = _atomics_T_16 ? 3'h3 : _atomics_T_15_param; // @[DCache.scala:587:81]
wire [3:0] atomics_size = _atomics_T_16 ? atomics_a_8_size : _atomics_T_15_size; // @[Edges.scala:517:17]
wire [31:0] atomics_address = _atomics_T_16 ? atomics_a_8_address : _atomics_T_15_address; // @[Edges.scala:517:17]
wire [7:0] atomics_mask = _atomics_T_16 ? atomics_a_8_mask : _atomics_T_15_mask; // @[Edges.scala:517:17]
wire [63:0] atomics_data = _atomics_T_16 ? atomics_a_8_data : _atomics_T_15_data; // @[Edges.scala:517:17]
wire [14:0] _tl_out_a_valid_T_2 = _tl_out_a_valid_T_1[20:6]; // @[DCache.scala:606:{43,62}]
wire _tl_out_a_valid_T_3 = _tl_out_a_valid_T_2 == 15'h0; // @[DCache.scala:582:29, :606:{62,118}]
wire _tl_out_a_valid_T_10 = ~s2_victim_dirty; // @[Misc.scala:38:9]
wire _tl_out_a_valid_T_11 = _tl_out_a_valid_T_10; // @[DCache.scala:607:{88,91}]
wire _tl_out_a_valid_T_12 = _tl_out_a_valid_T_6 & _tl_out_a_valid_T_11; // @[DCache.scala:605:29, :606:127, :607:88]
wire _tl_out_a_valid_T_13 = s2_valid_uncached_pending | _tl_out_a_valid_T_12; // @[DCache.scala:430:64, :604:32, :606:127]
assign _tl_out_a_valid_T_14 = _tl_out_a_valid_T_13; // @[DCache.scala:603:37, :604:32]
assign tl_out_a_valid = _tl_out_a_valid_T_14; // @[DCache.scala:159:22, :603:37]
wire _tl_out_a_bits_T = ~s2_uncached; // @[DCache.scala:424:39, :425:47, :608:24]
wire [39:0] _tl_out_a_bits_T_2 = {_tl_out_a_bits_T_1, 6'h0}; // @[DCache.scala:1210:{39,60}]
wire [39:0] _tl_out_a_bits_legal_T_1 = _tl_out_a_bits_T_2; // @[DCache.scala:1210:60]
wire [40:0] _tl_out_a_bits_legal_T_2 = {1'h0, _tl_out_a_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _tl_out_a_bits_legal_T_3 = _tl_out_a_bits_legal_T_2 & 41'h8E000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _tl_out_a_bits_legal_T_4 = _tl_out_a_bits_legal_T_3; // @[Parameters.scala:137:46]
wire _tl_out_a_bits_legal_T_5 = _tl_out_a_bits_legal_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _tl_out_a_bits_legal_T_6 = {_tl_out_a_bits_T_2[39:21], _tl_out_a_bits_T_2[20:0] ^ 21'h100000}; // @[DCache.scala:1210:60]
wire [40:0] _tl_out_a_bits_legal_T_7 = {1'h0, _tl_out_a_bits_legal_T_6}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _tl_out_a_bits_legal_T_8 = _tl_out_a_bits_legal_T_7 & 41'h8E101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _tl_out_a_bits_legal_T_9 = _tl_out_a_bits_legal_T_8; // @[Parameters.scala:137:46]
wire _tl_out_a_bits_legal_T_10 = _tl_out_a_bits_legal_T_9 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_107 = {_tl_out_a_bits_T_2[39:26], _tl_out_a_bits_T_2[25:0] ^ 26'h2000000}; // @[DCache.scala:1210:60]
wire [39:0] _tl_out_a_bits_legal_T_11; // @[Parameters.scala:137:31]
assign _tl_out_a_bits_legal_T_11 = _GEN_107; // @[Parameters.scala:137:31]
wire [39:0] _tl_out_a_bits_legal_T_16; // @[Parameters.scala:137:31]
assign _tl_out_a_bits_legal_T_16 = _GEN_107; // @[Parameters.scala:137:31]
wire [40:0] _tl_out_a_bits_legal_T_12 = {1'h0, _tl_out_a_bits_legal_T_11}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _tl_out_a_bits_legal_T_13 = _tl_out_a_bits_legal_T_12 & 41'h8E100000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _tl_out_a_bits_legal_T_14 = _tl_out_a_bits_legal_T_13; // @[Parameters.scala:137:46]
wire _tl_out_a_bits_legal_T_15 = _tl_out_a_bits_legal_T_14 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _tl_out_a_bits_legal_T_17 = {1'h0, _tl_out_a_bits_legal_T_16}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _tl_out_a_bits_legal_T_18 = _tl_out_a_bits_legal_T_17 & 41'h8E101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _tl_out_a_bits_legal_T_19 = _tl_out_a_bits_legal_T_18; // @[Parameters.scala:137:46]
wire _tl_out_a_bits_legal_T_20 = _tl_out_a_bits_legal_T_19 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _tl_out_a_bits_legal_T_21 = {_tl_out_a_bits_T_2[39:28], _tl_out_a_bits_T_2[27:0] ^ 28'hC000000}; // @[DCache.scala:1210:60]
wire [40:0] _tl_out_a_bits_legal_T_22 = {1'h0, _tl_out_a_bits_legal_T_21}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _tl_out_a_bits_legal_T_23 = _tl_out_a_bits_legal_T_22 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _tl_out_a_bits_legal_T_24 = _tl_out_a_bits_legal_T_23; // @[Parameters.scala:137:46]
wire _tl_out_a_bits_legal_T_25 = _tl_out_a_bits_legal_T_24 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _tl_out_a_bits_legal_T_26 = _tl_out_a_bits_legal_T_5 | _tl_out_a_bits_legal_T_10; // @[Parameters.scala:685:42]
wire _tl_out_a_bits_legal_T_27 = _tl_out_a_bits_legal_T_26 | _tl_out_a_bits_legal_T_15; // @[Parameters.scala:685:42]
wire _tl_out_a_bits_legal_T_28 = _tl_out_a_bits_legal_T_27 | _tl_out_a_bits_legal_T_20; // @[Parameters.scala:685:42]
wire _tl_out_a_bits_legal_T_29 = _tl_out_a_bits_legal_T_28 | _tl_out_a_bits_legal_T_25; // @[Parameters.scala:685:42]
wire [39:0] _tl_out_a_bits_legal_T_33 = {_tl_out_a_bits_T_2[39:28], _tl_out_a_bits_T_2[27:0] ^ 28'h8000000}; // @[DCache.scala:1210:60]
wire [40:0] _tl_out_a_bits_legal_T_34 = {1'h0, _tl_out_a_bits_legal_T_33}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _tl_out_a_bits_legal_T_35 = _tl_out_a_bits_legal_T_34 & 41'h8E100000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _tl_out_a_bits_legal_T_36 = _tl_out_a_bits_legal_T_35; // @[Parameters.scala:137:46]
wire _tl_out_a_bits_legal_T_37 = _tl_out_a_bits_legal_T_36 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] tl_out_a_bits_a_address = _tl_out_a_bits_T_2[31:0]; // @[Edges.scala:346:17]
wire [39:0] _tl_out_a_bits_legal_T_38 = {_tl_out_a_bits_T_2[39:32], tl_out_a_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17]
wire [40:0] _tl_out_a_bits_legal_T_39 = {1'h0, _tl_out_a_bits_legal_T_38}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _tl_out_a_bits_legal_T_40 = _tl_out_a_bits_legal_T_39 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _tl_out_a_bits_legal_T_41 = _tl_out_a_bits_legal_T_40; // @[Parameters.scala:137:46]
wire _tl_out_a_bits_legal_T_42 = _tl_out_a_bits_legal_T_41 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _tl_out_a_bits_legal_T_43 = _tl_out_a_bits_legal_T_37 | _tl_out_a_bits_legal_T_42; // @[Parameters.scala:685:42]
wire _tl_out_a_bits_legal_T_44 = _tl_out_a_bits_legal_T_43; // @[Parameters.scala:684:54, :685:42]
wire tl_out_a_bits_legal = _tl_out_a_bits_legal_T_44; // @[Parameters.scala:684:54, :686:26]
wire [2:0] tl_out_a_bits_a_param; // @[Edges.scala:346:17]
assign tl_out_a_bits_a_param = {1'h0, s2_grow_param}; // @[Misc.scala:35:36]
wire tl_out_a_bits_a_mask_sub_sub_bit = _tl_out_a_bits_T_2[2]; // @[Misc.scala:210:26]
wire tl_out_a_bits_a_mask_sub_sub_1_2 = tl_out_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire tl_out_a_bits_a_mask_sub_sub_nbit = ~tl_out_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire tl_out_a_bits_a_mask_sub_sub_0_2 = tl_out_a_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _tl_out_a_bits_a_mask_sub_sub_acc_T = tl_out_a_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38]
wire _tl_out_a_bits_a_mask_sub_sub_acc_T_1 = tl_out_a_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38]
wire tl_out_a_bits_a_mask_sub_bit = _tl_out_a_bits_T_2[1]; // @[Misc.scala:210:26]
wire tl_out_a_bits_a_mask_sub_nbit = ~tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire tl_out_a_bits_a_mask_sub_0_2 = tl_out_a_bits_a_mask_sub_sub_0_2 & tl_out_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire tl_out_a_bits_a_mask_sub_1_2 = tl_out_a_bits_a_mask_sub_sub_0_2 & tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire tl_out_a_bits_a_mask_sub_2_2 = tl_out_a_bits_a_mask_sub_sub_1_2 & tl_out_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire tl_out_a_bits_a_mask_sub_3_2 = tl_out_a_bits_a_mask_sub_sub_1_2 & tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire tl_out_a_bits_a_mask_bit = _tl_out_a_bits_T_2[0]; // @[Misc.scala:210:26]
wire tl_out_a_bits_a_mask_nbit = ~tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire tl_out_a_bits_a_mask_eq = tl_out_a_bits_a_mask_sub_0_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _tl_out_a_bits_a_mask_acc_T = tl_out_a_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38]
wire tl_out_a_bits_a_mask_eq_1 = tl_out_a_bits_a_mask_sub_0_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _tl_out_a_bits_a_mask_acc_T_1 = tl_out_a_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire tl_out_a_bits_a_mask_eq_2 = tl_out_a_bits_a_mask_sub_1_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _tl_out_a_bits_a_mask_acc_T_2 = tl_out_a_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire tl_out_a_bits_a_mask_eq_3 = tl_out_a_bits_a_mask_sub_1_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _tl_out_a_bits_a_mask_acc_T_3 = tl_out_a_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire tl_out_a_bits_a_mask_eq_4 = tl_out_a_bits_a_mask_sub_2_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _tl_out_a_bits_a_mask_acc_T_4 = tl_out_a_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38]
wire tl_out_a_bits_a_mask_eq_5 = tl_out_a_bits_a_mask_sub_2_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _tl_out_a_bits_a_mask_acc_T_5 = tl_out_a_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38]
wire tl_out_a_bits_a_mask_eq_6 = tl_out_a_bits_a_mask_sub_3_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _tl_out_a_bits_a_mask_acc_T_6 = tl_out_a_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38]
wire tl_out_a_bits_a_mask_eq_7 = tl_out_a_bits_a_mask_sub_3_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _tl_out_a_bits_a_mask_acc_T_7 = tl_out_a_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38]
wire _tl_out_a_bits_T_3 = ~s2_write; // @[DCache.scala:609:9]
wire _tl_out_a_bits_T_5 = ~s2_read; // @[DCache.scala:611:9]
wire [2:0] _tl_out_a_bits_T_6_opcode = _tl_out_a_bits_T_5 ? 3'h0 : atomics_opcode; // @[DCache.scala:587:81, :611:{8,9}]
wire [2:0] _tl_out_a_bits_T_6_param = _tl_out_a_bits_T_5 ? 3'h0 : atomics_param; // @[DCache.scala:587:81, :611:{8,9}]
wire [3:0] _tl_out_a_bits_T_6_size = _tl_out_a_bits_T_5 ? put_size : atomics_size; // @[Edges.scala:480:17]
wire [31:0] _tl_out_a_bits_T_6_address = _tl_out_a_bits_T_5 ? put_address : atomics_address; // @[Edges.scala:480:17]
wire [7:0] _tl_out_a_bits_T_6_mask = _tl_out_a_bits_T_5 ? put_mask : atomics_mask; // @[Edges.scala:480:17]
wire [63:0] _tl_out_a_bits_T_6_data = _tl_out_a_bits_T_5 ? put_data : atomics_data; // @[Edges.scala:480:17]
wire [2:0] _tl_out_a_bits_T_7_opcode = _tl_out_a_bits_T_4 ? 3'h1 : _tl_out_a_bits_T_6_opcode; // @[DCache.scala:610:{8,20}, :611:8]
wire [2:0] _tl_out_a_bits_T_7_param = _tl_out_a_bits_T_4 ? 3'h0 : _tl_out_a_bits_T_6_param; // @[DCache.scala:610:{8,20}, :611:8]
wire [3:0] _tl_out_a_bits_T_7_size = _tl_out_a_bits_T_4 ? putpartial_size : _tl_out_a_bits_T_6_size; // @[Edges.scala:500:17]
wire [31:0] _tl_out_a_bits_T_7_address = _tl_out_a_bits_T_4 ? putpartial_address : _tl_out_a_bits_T_6_address; // @[Edges.scala:500:17]
wire [7:0] _tl_out_a_bits_T_7_mask = _tl_out_a_bits_T_4 ? putpartial_mask : _tl_out_a_bits_T_6_mask; // @[Edges.scala:500:17]
wire [63:0] _tl_out_a_bits_T_7_data = _tl_out_a_bits_T_4 ? putpartial_data : _tl_out_a_bits_T_6_data; // @[Edges.scala:500:17]
wire [2:0] _tl_out_a_bits_T_8_opcode = _tl_out_a_bits_T_3 ? 3'h4 : _tl_out_a_bits_T_7_opcode; // @[DCache.scala:609:{8,9}, :610:8]
wire [2:0] _tl_out_a_bits_T_8_param = _tl_out_a_bits_T_3 ? 3'h0 : _tl_out_a_bits_T_7_param; // @[DCache.scala:609:{8,9}, :610:8]
wire [3:0] _tl_out_a_bits_T_8_size = _tl_out_a_bits_T_3 ? get_size : _tl_out_a_bits_T_7_size; // @[Edges.scala:460:17]
wire [31:0] _tl_out_a_bits_T_8_address = _tl_out_a_bits_T_3 ? get_address : _tl_out_a_bits_T_7_address; // @[Edges.scala:460:17]
wire [7:0] _tl_out_a_bits_T_8_mask = _tl_out_a_bits_T_3 ? get_mask : _tl_out_a_bits_T_7_mask; // @[Edges.scala:460:17]
wire [63:0] _tl_out_a_bits_T_8_data = _tl_out_a_bits_T_3 ? 64'h0 : _tl_out_a_bits_T_7_data; // @[DCache.scala:609:{8,9}, :610:8]
assign _tl_out_a_bits_T_9_opcode = _tl_out_a_bits_T ? 3'h6 : _tl_out_a_bits_T_8_opcode; // @[DCache.scala:608:{23,24}, :609:8]
assign _tl_out_a_bits_T_9_param = _tl_out_a_bits_T ? tl_out_a_bits_a_param : _tl_out_a_bits_T_8_param; // @[Edges.scala:346:17]
assign _tl_out_a_bits_T_9_size = _tl_out_a_bits_T ? 4'h6 : _tl_out_a_bits_T_8_size; // @[DCache.scala:608:{23,24}, :609:8]
assign _tl_out_a_bits_T_9_address = _tl_out_a_bits_T ? tl_out_a_bits_a_address : _tl_out_a_bits_T_8_address; // @[Edges.scala:346:17]
assign _tl_out_a_bits_T_9_mask = _tl_out_a_bits_T ? 8'hFF : _tl_out_a_bits_T_8_mask; // @[DCache.scala:608:{23,24}, :609:8]
assign _tl_out_a_bits_T_9_data = _tl_out_a_bits_T ? 64'h0 : _tl_out_a_bits_T_8_data; // @[DCache.scala:608:{23,24}, :609:8]
assign tl_out_a_bits_opcode = _tl_out_a_bits_T_9_opcode; // @[DCache.scala:159:22, :608:23]
assign tl_out_a_bits_param = _tl_out_a_bits_T_9_param; // @[DCache.scala:159:22, :608:23]
assign tl_out_a_bits_size = _tl_out_a_bits_T_9_size; // @[DCache.scala:159:22, :608:23]
assign tl_out_a_bits_address = _tl_out_a_bits_T_9_address; // @[DCache.scala:159:22, :608:23]
assign tl_out_a_bits_mask = _tl_out_a_bits_T_9_mask; // @[DCache.scala:159:22, :608:23]
assign tl_out_a_bits_data = _tl_out_a_bits_T_9_data; // @[DCache.scala:159:22, :608:23]
wire _io_cpu_perf_acquire_T = tl_out_a_ready & tl_out_a_valid; // @[Decoupled.scala:51:35]
wire [4:0] _uncachedReqs_0_cmd_T_1 = {_uncachedReqs_0_cmd_T, 4'h1}; // @[DCache.scala:637:{37,49}]
wire [4:0] _uncachedReqs_0_cmd_T_2 = s2_write ? _uncachedReqs_0_cmd_T_1 : 5'h0; // @[DCache.scala:637:{23,37}]
wire _T_90 = nodeOut_d_ready & nodeOut_d_valid; // @[Decoupled.scala:51:35]
wire _io_cpu_replay_next_T; // @[Decoupled.scala:51:35]
assign _io_cpu_replay_next_T = _T_90; // @[Decoupled.scala:51:35]
wire _io_cpu_perf_blocked_near_end_of_refill_T; // @[Decoupled.scala:51:35]
assign _io_cpu_perf_blocked_near_end_of_refill_T = _T_90; // @[Decoupled.scala:51:35]
wire _io_errors_bus_valid_T; // @[Decoupled.scala:51:35]
assign _io_errors_bus_valid_T = _T_90; // @[Decoupled.scala:51:35]
wire [26:0] _r_beats1_decode_T = 27'hFFF << nodeOut_d_bits_size; // @[package.scala:243:71]
wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire r_beats1_opdata = nodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] r_counter; // @[Edges.scala:229:27]
wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_last = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_done = d_last & _T_90; // @[Decoupled.scala:51:35]
wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _r_counter_T = d_first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] d_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29]
wire [1:0] d_opc = nodeOut_d_bits_opcode[1:0]; // @[DCache.scala:656:26]
wire [1:0] data_plaInput = d_opc; // @[pla.scala:77:22]
wire [1:0] data_invInputs = ~data_plaInput; // @[pla.scala:77:22, :78:21]
wire data_invMatrixOutputs; // @[pla.scala:124:31]
wire data_plaOutput; // @[pla.scala:81:23]
wire grantIsUncachedData = data_plaOutput; // @[pla.scala:81:23]
wire data_andMatrixOutputs_andMatrixInput_0 = data_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire data_andMatrixOutputs_andMatrixInput_1 = data_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire [1:0] _data_andMatrixOutputs_T = {data_andMatrixOutputs_andMatrixInput_0, data_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire data_andMatrixOutputs_0_2 = &_data_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire data_orMatrixOutputs = data_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36]
assign data_invMatrixOutputs = data_orMatrixOutputs; // @[pla.scala:114:36, :124:31]
assign data_plaOutput = data_invMatrixOutputs; // @[pla.scala:81:23, :124:31]
wire _tl_d_data_encoded_T_9 = io_ptw_customCSRs_csrs_0_value_0[9]; // @[CustomCSRs.scala:47:65]
wire _tl_d_data_encoded_T_10 = ~_tl_d_data_encoded_T_9; // @[CustomCSRs.scala:47:65]
wire _tl_d_data_encoded_T_11 = nodeOut_d_bits_corrupt & _tl_d_data_encoded_T_10; // @[DCache.scala:663:{77,80}]
wire [15:0] tl_d_data_encoded_lo_lo_1 = {_tl_d_data_encoded_T_15, _tl_d_data_encoded_T_14}; // @[package.scala:45:27, :211:50]
wire [15:0] tl_d_data_encoded_lo_hi_1 = {_tl_d_data_encoded_T_17, _tl_d_data_encoded_T_16}; // @[package.scala:45:27, :211:50]
wire [31:0] tl_d_data_encoded_lo_1 = {tl_d_data_encoded_lo_hi_1, tl_d_data_encoded_lo_lo_1}; // @[package.scala:45:27]
wire [15:0] tl_d_data_encoded_hi_lo_1 = {_tl_d_data_encoded_T_19, _tl_d_data_encoded_T_18}; // @[package.scala:45:27, :211:50]
wire [15:0] tl_d_data_encoded_hi_hi_1 = {_tl_d_data_encoded_T_21, _tl_d_data_encoded_T_20}; // @[package.scala:45:27, :211:50]
wire [31:0] tl_d_data_encoded_hi_1 = {tl_d_data_encoded_hi_hi_1, tl_d_data_encoded_hi_lo_1}; // @[package.scala:45:27]
assign _tl_d_data_encoded_T_22 = {tl_d_data_encoded_hi_1, tl_d_data_encoded_lo_1}; // @[package.scala:45:27]
assign tl_d_data_encoded = _tl_d_data_encoded_T_22; // @[package.scala:45:27]
wire grantIsCached = _grantIsCached_T | _grantIsCached_T_1; // @[package.scala:16:47, :81:59]
reg grantInProgress; // @[DCache.scala:667:32]
wire block_probe_for_ordering = grantInProgress; // @[DCache.scala:667:32, :768:89]
reg [2:0] blockProbeAfterGrantCount; // @[DCache.scala:668:42]
wire [3:0] _blockProbeAfterGrantCount_T = {1'h0, blockProbeAfterGrantCount} - 4'h1; // @[DCache.scala:668:42, :669:99]
wire [2:0] _blockProbeAfterGrantCount_T_1 = _blockProbeAfterGrantCount_T[2:0]; // @[DCache.scala:669:99]
wire _nodeOut_d_ready_T = ~d_first; // @[Edges.scala:231:25]
wire _nodeOut_d_ready_T_1 = _nodeOut_d_ready_T; // @[DCache.scala:671:{41,50}]
wire _nodeOut_d_ready_T_2 = _nodeOut_d_ready_T_1; // @[DCache.scala:671:{50,69}]
wire _nodeOut_d_ready_T_3 = ~grantIsCached | _nodeOut_d_ready_T_2; // @[package.scala:81:59]
wire _GEN_108 = _T_90 & grantIsCached; // @[Decoupled.scala:51:35]
assign replace = _GEN_108 & d_last; // @[Replacement.scala:37:29, :38:11]
wire _GEN_109 = ~_T_90 | grantIsCached | ~grantIsUncachedData; // @[Decoupled.scala:51:35]
assign s1_data_way = _GEN_109 ? 2'h1 : 2'h2; // @[DCache.scala:323:32, :674:24, :675:26, :684:35]
wire [28:0] _s2_req_addr_dontCareBits_T = s1_paddr[31:3]; // @[DCache.scala:298:21, :701:41]
wire [31:0] s2_req_addr_dontCareBits = {_s2_req_addr_dontCareBits_T, 3'h0}; // @[DCache.scala:701:{41,55}]
wire [2:0] _s2_req_addr_T = uncachedResp_addr[2:0]; // @[DCache.scala:238:30, :702:45]
wire [31:0] _s2_req_addr_T_1 = {s2_req_addr_dontCareBits[31:3], s2_req_addr_dontCareBits[2:0] | _s2_req_addr_T}; // @[DCache.scala:701:55, :702:{26,45}]
wire _dataArb_io_in_1_valid_T = nodeOut_d_valid & grantIsRefill; // @[DCache.scala:666:29, :721:44]
wire _dataArb_io_in_1_valid_T_1 = _dataArb_io_in_1_valid_T; // @[DCache.scala:721:{44,61}]
wire _metaArb_io_in_3_valid_T = grantIsCached & d_done; // @[package.scala:81:59]
wire _metaArb_io_in_3_valid_T_1 = ~nodeOut_d_bits_denied; // @[DCache.scala:741:56]
assign _metaArb_io_in_3_valid_T_2 = _metaArb_io_in_3_valid_T & _metaArb_io_in_3_valid_T_1; // @[DCache.scala:741:{43,53,56}]
assign metaArb_io_in_3_valid = _metaArb_io_in_3_valid_T_2; // @[DCache.scala:135:28, :741:53]
assign metaArb_io_in_3_bits_way_en = refill_way[0]; // @[DCache.scala:135:28, :229:23, :743:32]
assign metaArb_io_in_3_bits_idx = _metaArb_io_in_3_bits_idx_T; // @[DCache.scala:135:28, :744:40]
assign _metaArb_io_in_3_bits_addr_T_2 = {_metaArb_io_in_3_bits_addr_T, _metaArb_io_in_3_bits_addr_T_1}; // @[DCache.scala:745:{36,58,80}]
assign metaArb_io_in_3_bits_addr = _metaArb_io_in_3_bits_addr_T_2; // @[DCache.scala:135:28, :745:36]
wire _metaArb_io_in_3_bits_data_c_cat_T_2 = _metaArb_io_in_3_bits_data_c_cat_T | _metaArb_io_in_3_bits_data_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _metaArb_io_in_3_bits_data_c_cat_T_4 = _metaArb_io_in_3_bits_data_c_cat_T_2 | _metaArb_io_in_3_bits_data_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _metaArb_io_in_3_bits_data_c_cat_T_9 = _metaArb_io_in_3_bits_data_c_cat_T_5 | _metaArb_io_in_3_bits_data_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_10 = _metaArb_io_in_3_bits_data_c_cat_T_9 | _metaArb_io_in_3_bits_data_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_11 = _metaArb_io_in_3_bits_data_c_cat_T_10 | _metaArb_io_in_3_bits_data_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_17 = _metaArb_io_in_3_bits_data_c_cat_T_12 | _metaArb_io_in_3_bits_data_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_18 = _metaArb_io_in_3_bits_data_c_cat_T_17 | _metaArb_io_in_3_bits_data_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_19 = _metaArb_io_in_3_bits_data_c_cat_T_18 | _metaArb_io_in_3_bits_data_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_20 = _metaArb_io_in_3_bits_data_c_cat_T_19 | _metaArb_io_in_3_bits_data_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_21 = _metaArb_io_in_3_bits_data_c_cat_T_11 | _metaArb_io_in_3_bits_data_c_cat_T_20; // @[package.scala:81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_22 = _metaArb_io_in_3_bits_data_c_cat_T_4 | _metaArb_io_in_3_bits_data_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _metaArb_io_in_3_bits_data_c_cat_T_25 = _metaArb_io_in_3_bits_data_c_cat_T_23 | _metaArb_io_in_3_bits_data_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _metaArb_io_in_3_bits_data_c_cat_T_27 = _metaArb_io_in_3_bits_data_c_cat_T_25 | _metaArb_io_in_3_bits_data_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _metaArb_io_in_3_bits_data_c_cat_T_32 = _metaArb_io_in_3_bits_data_c_cat_T_28 | _metaArb_io_in_3_bits_data_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_33 = _metaArb_io_in_3_bits_data_c_cat_T_32 | _metaArb_io_in_3_bits_data_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_34 = _metaArb_io_in_3_bits_data_c_cat_T_33 | _metaArb_io_in_3_bits_data_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_40 = _metaArb_io_in_3_bits_data_c_cat_T_35 | _metaArb_io_in_3_bits_data_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_41 = _metaArb_io_in_3_bits_data_c_cat_T_40 | _metaArb_io_in_3_bits_data_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_42 = _metaArb_io_in_3_bits_data_c_cat_T_41 | _metaArb_io_in_3_bits_data_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_43 = _metaArb_io_in_3_bits_data_c_cat_T_42 | _metaArb_io_in_3_bits_data_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_44 = _metaArb_io_in_3_bits_data_c_cat_T_34 | _metaArb_io_in_3_bits_data_c_cat_T_43; // @[package.scala:81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_45 = _metaArb_io_in_3_bits_data_c_cat_T_27 | _metaArb_io_in_3_bits_data_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _metaArb_io_in_3_bits_data_c_cat_T_47 = _metaArb_io_in_3_bits_data_c_cat_T_45 | _metaArb_io_in_3_bits_data_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _metaArb_io_in_3_bits_data_c_cat_T_49 = _metaArb_io_in_3_bits_data_c_cat_T_47 | _metaArb_io_in_3_bits_data_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] metaArb_io_in_3_bits_data_c = {_metaArb_io_in_3_bits_data_c_cat_T_22, _metaArb_io_in_3_bits_data_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _metaArb_io_in_3_bits_data_T_1 = {metaArb_io_in_3_bits_data_c, nodeOut_d_bits_param}; // @[Metadata.scala:29:18, :84:18]
wire _metaArb_io_in_3_bits_data_T_10 = _metaArb_io_in_3_bits_data_T_1 == 4'h1; // @[Metadata.scala:84:{18,38}]
wire [1:0] _metaArb_io_in_3_bits_data_T_11 = {1'h0, _metaArb_io_in_3_bits_data_T_10}; // @[Metadata.scala:84:38]
wire _metaArb_io_in_3_bits_data_T_12 = _metaArb_io_in_3_bits_data_T_1 == 4'h0; // @[Metadata.scala:84:{18,38}]
wire [1:0] _metaArb_io_in_3_bits_data_T_13 = _metaArb_io_in_3_bits_data_T_12 ? 2'h2 : _metaArb_io_in_3_bits_data_T_11; // @[Metadata.scala:84:38]
wire _metaArb_io_in_3_bits_data_T_14 = _metaArb_io_in_3_bits_data_T_1 == 4'h4; // @[Metadata.scala:84:{18,38}]
wire [1:0] _metaArb_io_in_3_bits_data_T_15 = _metaArb_io_in_3_bits_data_T_14 ? 2'h2 : _metaArb_io_in_3_bits_data_T_13; // @[Metadata.scala:84:38]
wire _metaArb_io_in_3_bits_data_T_16 = _metaArb_io_in_3_bits_data_T_1 == 4'hC; // @[Metadata.scala:84:{18,38}]
wire [1:0] _metaArb_io_in_3_bits_data_T_17 = _metaArb_io_in_3_bits_data_T_16 ? 2'h3 : _metaArb_io_in_3_bits_data_T_15; // @[Metadata.scala:84:38]
wire [1:0] metaArb_io_in_3_bits_data_meta_state = _metaArb_io_in_3_bits_data_T_17; // @[Metadata.scala:84:38, :160:20]
wire [1:0] metaArb_io_in_3_bits_data_meta_1_coh_state = metaArb_io_in_3_bits_data_meta_state; // @[Metadata.scala:160:20]
wire [20:0] metaArb_io_in_3_bits_data_meta_1_tag; // @[HellaCache.scala:305:20]
assign metaArb_io_in_3_bits_data_meta_1_tag = _metaArb_io_in_3_bits_data_T[20:0]; // @[HellaCache.scala:305:20, :306:14]
assign _metaArb_io_in_3_bits_data_T_18 = {metaArb_io_in_3_bits_data_meta_1_coh_state, metaArb_io_in_3_bits_data_meta_1_tag}; // @[HellaCache.scala:305:20]
assign metaArb_io_in_3_bits_data = _metaArb_io_in_3_bits_data_T_18; // @[DCache.scala:135:28, :746:134]
reg blockUncachedGrant; // @[DCache.scala:750:33]
wire _T_100 = grantIsUncachedData & (blockUncachedGrant | s1_valid); // @[Decode.scala:55:116]
assign nodeOut_d_ready = ~(_T_100 | grantIsRefill & ~dataArb_io_in_1_ready) & _nodeOut_d_ready_T_3; // @[DCache.scala:152:28, :666:29, :671:{18,24}, :722:{23,26,51}, :724:20, :752:{31,68}, :753:22]
assign io_cpu_req_ready_0 = _T_100 ? ~(nodeOut_d_valid | _T_10 | ~metaArb_io_in_7_ready | _T_4) & _io_cpu_req_ready_T_4 : ~(_T_10 | ~metaArb_io_in_7_ready | _T_4) & _io_cpu_req_ready_T_4; // @[DCache.scala:101:7, :135:28, :195:9, :233:{20,73}, :258:{33,45,64}, :267:{34,53}, :275:{27,53,79,98}, :752:{31,68}, :755:29, :756:26]
wire _GEN_110 = _T_100 & nodeOut_d_valid; // @[DCache.scala:721:26, :752:{31,68}, :755:29, :757:32]
assign dataArb_io_in_1_valid = _GEN_110 | _dataArb_io_in_1_valid_T_1; // @[DCache.scala:152:28, :721:{26,61}, :752:68, :755:29, :757:32]
assign dataArb_io_in_1_bits_write = ~_GEN_110 & pstore_drain; // @[DCache.scala:152:28, :516:27, :721:26, :734:27, :752:68, :755:29, :757:32, :758:37]
wire _blockUncachedGrant_T = ~dataArb_io_in_1_ready; // @[DCache.scala:152:28, :722:26, :759:31]
wire _block_probe_for_core_progress_T = |blockProbeAfterGrantCount; // @[DCache.scala:668:42, :669:35, :766:65]
wire block_probe_for_core_progress = _block_probe_for_core_progress_T | lrscValid; // @[DCache.scala:473:29, :766:{65,71}]
wire [14:0] _block_probe_for_pending_release_ack_T_1 = _block_probe_for_pending_release_ack_T[20:6]; // @[DCache.scala:767:{88,107}]
wire _block_probe_for_pending_release_ack_T_2 = _block_probe_for_pending_release_ack_T_1 == 15'h0; // @[DCache.scala:582:29, :767:{107,163}]
wire _metaArb_io_in_6_valid_T = ~block_probe_for_core_progress; // @[DCache.scala:766:71, :769:48]
wire _metaArb_io_in_6_valid_T_1 = _metaArb_io_in_6_valid_T | lrscBackingOff; // @[DCache.scala:474:40, :769:{48,79}]
wire [7:0] _metaArb_io_in_6_bits_addr_T = io_cpu_req_bits_addr_0[39:32]; // @[DCache.scala:101:7, :773:58]
assign _metaArb_io_in_6_bits_addr_T_1 = {_metaArb_io_in_6_bits_addr_T, 32'h0}; // @[DCache.scala:773:{36,58}]
assign metaArb_io_in_6_bits_addr = _metaArb_io_in_6_bits_addr_T_1; // @[DCache.scala:135:28, :773:36]
wire _releaseRejected_T_2; // @[DCache.scala:803:44]
wire releaseRejected; // @[DCache.scala:800:29]
wire _s2_release_data_valid_T = ~releaseRejected; // @[DCache.scala:800:29, :802:64]
reg s2_release_data_valid; // @[DCache.scala:802:38]
assign _releaseRejected_T_2 = s2_release_data_valid; // @[DCache.scala:802:38, :803:44]
wire _tl_out_c_valid_T_3 = s2_release_data_valid; // @[DCache.scala:802:38, :810:44]
assign releaseRejected = _releaseRejected_T_2; // @[DCache.scala:800:29, :803:44]
wire [1:0] _releaseDataBeat_T_1 = {1'h0, s2_release_data_valid}; // @[DCache.scala:802:38, :804:98]
wire [2:0] _releaseDataBeat_T_2 = {1'h0, _releaseDataBeat_T_1}; // @[DCache.scala:804:{93,98}]
wire [1:0] _releaseDataBeat_T_3 = _releaseDataBeat_T_2[1:0]; // @[DCache.scala:804:93]
wire [1:0] _releaseDataBeat_T_4 = releaseRejected ? 2'h0 : _releaseDataBeat_T_3; // @[DCache.scala:800:29, :804:{48,93}]
wire [10:0] _releaseDataBeat_T_5 = {9'h0, _releaseDataBeat_T_4}; // @[DCache.scala:804:{43,48}]
wire [9:0] releaseDataBeat = _releaseDataBeat_T_5[9:0]; // @[DCache.scala:804:43]
assign _tl_out_c_valid_T_6 = _tl_out_c_valid_T_3; // @[DCache.scala:810:{44,117}]
assign tl_out_c_valid = _tl_out_c_valid_T_6; // @[Bundles.scala:265:61]
wire [1:0] metaArb_io_in_4_bits_data_meta_coh_state = newCoh_state; // @[HellaCache.scala:305:20]
wire _dataArb_io_in_2_valid_T = releaseDataBeat < 10'h8; // @[DCache.scala:804:43, :900:60]
wire [2:0] _dataArb_io_in_2_bits_addr_T_2 = releaseDataBeat[2:0]; // @[DCache.scala:804:43, :903:90]
wire [5:0] _dataArb_io_in_2_bits_addr_T_3 = {_dataArb_io_in_2_bits_addr_T_2, 3'h0}; // @[DCache.scala:903:{90,117}]
assign _dataArb_io_in_2_bits_addr_T_4 = {5'h0, _dataArb_io_in_2_bits_addr_T_3}; // @[DCache.scala:903:{72,117}]
assign dataArb_io_in_2_bits_addr = _dataArb_io_in_2_bits_addr_T_4; // @[DCache.scala:152:28, :903:72]
assign _metaArb_io_in_4_bits_addr_T_2 = {_metaArb_io_in_4_bits_addr_T, 11'h0}; // @[DCache.scala:912:{36,58}]
assign metaArb_io_in_4_bits_addr = _metaArb_io_in_4_bits_addr_T_2; // @[DCache.scala:135:28, :912:36]
assign _metaArb_io_in_4_bits_data_T_1 = {metaArb_io_in_4_bits_data_meta_coh_state, 21'h0}; // @[HellaCache.scala:305:20]
assign metaArb_io_in_4_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97]
assign metaArb_io_in_5_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97]
assign metaArb_io_in_6_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97]
assign metaArb_io_in_7_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97]
wire _io_cpu_s2_uncached_T = ~s2_hit; // @[Misc.scala:35:9]
assign _io_cpu_s2_uncached_T_1 = s2_uncached & _io_cpu_s2_uncached_T; // @[DCache.scala:424:39, :920:{37,40}]
assign io_cpu_s2_uncached_0 = _io_cpu_s2_uncached_T_1; // @[DCache.scala:101:7, :920:37]
wire _io_cpu_ordered_T = ~s1_req_no_xcpt; // @[DCache.scala:196:25, :929:35]
wire _io_cpu_ordered_T_1 = s1_valid & _io_cpu_ordered_T; // @[DCache.scala:182:25, :929:{32,35}]
wire _io_cpu_ordered_T_2 = ~s2_req_no_xcpt; // @[DCache.scala:339:19, :929:72]
wire _io_cpu_ordered_T_3 = s2_valid & _io_cpu_ordered_T_2; // @[DCache.scala:331:25, :929:{69,72}]
wire _io_cpu_ordered_T_4 = _io_cpu_ordered_T_1 | _io_cpu_ordered_T_3; // @[DCache.scala:929:{32,57,69}]
wire _io_cpu_ordered_T_5 = _io_cpu_ordered_T_4 | cached_grant_wait; // @[DCache.scala:223:34, :929:{57,94}]
wire _io_cpu_ordered_T_7 = _io_cpu_ordered_T_5 | _io_cpu_ordered_T_6; // @[DCache.scala:929:{94,115,142}]
assign _io_cpu_ordered_T_8 = ~_io_cpu_ordered_T_7; // @[DCache.scala:929:{21,115}]
assign io_cpu_ordered_0 = _io_cpu_ordered_T_8; // @[DCache.scala:101:7, :929:21]
wire _io_cpu_store_pending_T_2 = _io_cpu_store_pending_T | _io_cpu_store_pending_T_1; // @[Consts.scala:90:{32,42,49}]
wire _io_cpu_store_pending_T_4 = _io_cpu_store_pending_T_2 | _io_cpu_store_pending_T_3; // @[Consts.scala:90:{42,59,66}]
wire _io_cpu_store_pending_T_9 = _io_cpu_store_pending_T_5 | _io_cpu_store_pending_T_6; // @[package.scala:16:47, :81:59]
wire _io_cpu_store_pending_T_10 = _io_cpu_store_pending_T_9 | _io_cpu_store_pending_T_7; // @[package.scala:16:47, :81:59]
wire _io_cpu_store_pending_T_11 = _io_cpu_store_pending_T_10 | _io_cpu_store_pending_T_8; // @[package.scala:16:47, :81:59]
wire _io_cpu_store_pending_T_17 = _io_cpu_store_pending_T_12 | _io_cpu_store_pending_T_13; // @[package.scala:16:47, :81:59]
wire _io_cpu_store_pending_T_18 = _io_cpu_store_pending_T_17 | _io_cpu_store_pending_T_14; // @[package.scala:16:47, :81:59]
wire _io_cpu_store_pending_T_19 = _io_cpu_store_pending_T_18 | _io_cpu_store_pending_T_15; // @[package.scala:16:47, :81:59]
wire _io_cpu_store_pending_T_20 = _io_cpu_store_pending_T_19 | _io_cpu_store_pending_T_16; // @[package.scala:16:47, :81:59]
wire _io_cpu_store_pending_T_21 = _io_cpu_store_pending_T_11 | _io_cpu_store_pending_T_20; // @[package.scala:81:59]
wire _io_cpu_store_pending_T_22 = _io_cpu_store_pending_T_4 | _io_cpu_store_pending_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _io_cpu_store_pending_T_23 = cached_grant_wait & _io_cpu_store_pending_T_22; // @[DCache.scala:223:34, :930:46]
assign _io_cpu_store_pending_T_25 = _io_cpu_store_pending_T_23 | _io_cpu_store_pending_T_24; // @[DCache.scala:930:{46,70,97}]
assign io_cpu_store_pending_0 = _io_cpu_store_pending_T_25; // @[DCache.scala:101:7, :930:70]
wire _s1_xcpt_valid_T = ~s1_req_no_xcpt; // @[DCache.scala:196:25, :929:35, :932:43]
wire _s1_xcpt_valid_T_1 = _tlb_io_req_valid_T_3 & _s1_xcpt_valid_T; // @[DCache.scala:273:40, :932:{40,43}]
wire _s1_xcpt_valid_T_2 = ~s1_nack; // @[DCache.scala:185:28, :187:41, :932:68]
wire s1_xcpt_valid = _s1_xcpt_valid_T_1 & _s1_xcpt_valid_T_2; // @[DCache.scala:932:{40,65,68}]
reg io_cpu_s2_xcpt_REG; // @[DCache.scala:933:32]
wire _io_cpu_s2_xcpt_T_miss = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_miss; // @[DCache.scala:342:24, :933:{24,32}]
wire [31:0] _io_cpu_s2_xcpt_T_paddr = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_paddr : 32'h0; // @[DCache.scala:342:24, :933:{24,32}]
wire [39:0] _io_cpu_s2_xcpt_T_gpa = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_gpa : 40'h0; // @[DCache.scala:342:24, :933:{24,32}]
assign _io_cpu_s2_xcpt_T_pf_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_ld; // @[DCache.scala:342:24, :933:{24,32}]
assign _io_cpu_s2_xcpt_T_pf_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_st; // @[DCache.scala:342:24, :933:{24,32}]
wire _io_cpu_s2_xcpt_T_pf_inst = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_inst; // @[DCache.scala:342:24, :933:{24,32}]
assign _io_cpu_s2_xcpt_T_ae_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_ld; // @[DCache.scala:342:24, :933:{24,32}]
assign _io_cpu_s2_xcpt_T_ae_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_st; // @[DCache.scala:342:24, :933:{24,32}]
wire _io_cpu_s2_xcpt_T_ae_inst = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_inst; // @[DCache.scala:342:24, :933:{24,32}]
assign _io_cpu_s2_xcpt_T_ma_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_ld; // @[DCache.scala:342:24, :933:{24,32}]
assign _io_cpu_s2_xcpt_T_ma_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_st; // @[DCache.scala:342:24, :933:{24,32}]
wire _io_cpu_s2_xcpt_T_cacheable = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_cacheable; // @[DCache.scala:342:24, :933:{24,32}]
wire _io_cpu_s2_xcpt_T_must_alloc = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_must_alloc; // @[DCache.scala:342:24, :933:{24,32}]
wire _io_cpu_s2_xcpt_T_prefetchable = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_prefetchable; // @[DCache.scala:342:24, :933:{24,32}]
wire [1:0] _io_cpu_s2_xcpt_T_size = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_size : 2'h0; // @[DCache.scala:342:24, :933:{24,32}]
wire [4:0] _io_cpu_s2_xcpt_T_cmd = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_cmd : 5'h0; // @[DCache.scala:342:24, :933:{24,32}]
assign io_cpu_s2_xcpt_pf_ld_0 = _io_cpu_s2_xcpt_T_pf_ld; // @[DCache.scala:101:7, :933:24]
assign io_cpu_s2_xcpt_pf_st_0 = _io_cpu_s2_xcpt_T_pf_st; // @[DCache.scala:101:7, :933:24]
assign io_cpu_s2_xcpt_ae_ld_0 = _io_cpu_s2_xcpt_T_ae_ld; // @[DCache.scala:101:7, :933:24]
assign io_cpu_s2_xcpt_ae_st_0 = _io_cpu_s2_xcpt_T_ae_st; // @[DCache.scala:101:7, :933:24]
assign io_cpu_s2_xcpt_ma_ld_0 = _io_cpu_s2_xcpt_T_ma_ld; // @[DCache.scala:101:7, :933:24]
assign io_cpu_s2_xcpt_ma_st_0 = _io_cpu_s2_xcpt_T_ma_st; // @[DCache.scala:101:7, :933:24]
reg [63:0] s2_uncached_data_word; // @[DCache.scala:947:40]
reg doUncachedResp; // @[DCache.scala:948:31]
assign io_cpu_resp_bits_replay_0 = doUncachedResp; // @[DCache.scala:101:7, :948:31]
wire _io_cpu_resp_valid_T = s2_valid_hit_pre_data_ecc | doUncachedResp; // @[DCache.scala:420:69, :948:31, :949:51]
assign _io_cpu_resp_valid_T_2 = _io_cpu_resp_valid_T; // @[DCache.scala:949:{51,70}]
assign io_cpu_resp_valid_0 = _io_cpu_resp_valid_T_2; // @[DCache.scala:101:7, :949:70]
wire _io_cpu_replay_next_T_1 = _io_cpu_replay_next_T & grantIsUncachedData; // @[Decoupled.scala:51:35]
assign _io_cpu_replay_next_T_3 = _io_cpu_replay_next_T_1; // @[DCache.scala:950:{39,62}]
assign io_cpu_replay_next_0 = _io_cpu_replay_next_T_3; // @[DCache.scala:101:7, :950:62] |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_175 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_175( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InputBuffer :
input clock : Clock
input reset : Reset
output io : { flip enq : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>}}[3]}
inst qs_0 of Queue3_BaseFlit
connect qs_0.clock, clock
connect qs_0.reset, reset
inst qs_1 of Queue3_BaseFlit_1
connect qs_1.clock, clock
connect qs_1.reset, reset
inst qs_2 of Queue3_BaseFlit_2
connect qs_2.clock, clock
connect qs_2.reset, reset
node _sel_T = eq(io.enq[0].bits.virt_channel_id, UInt<1>(0h0))
node sel_0 = and(io.enq[0].valid, _sel_T)
connect qs_0.io.enq.valid, sel_0
connect qs_0.io.enq.bits.head, io.enq[0].bits.head
connect qs_0.io.enq.bits.tail, io.enq[0].bits.tail
connect qs_0.io.enq.bits.payload, io.enq[0].bits.payload
connect io.deq[0].bits, qs_0.io.deq.bits
connect io.deq[0].valid, qs_0.io.deq.valid
connect qs_0.io.deq.ready, io.deq[0].ready
node _sel_T_1 = eq(io.enq[0].bits.virt_channel_id, UInt<1>(0h1))
node sel_0_1 = and(io.enq[0].valid, _sel_T_1)
connect qs_1.io.enq.valid, sel_0_1
connect qs_1.io.enq.bits.head, io.enq[0].bits.head
connect qs_1.io.enq.bits.tail, io.enq[0].bits.tail
connect qs_1.io.enq.bits.payload, io.enq[0].bits.payload
connect io.deq[1].bits, qs_1.io.deq.bits
connect io.deq[1].valid, qs_1.io.deq.valid
connect qs_1.io.deq.ready, io.deq[1].ready
node _sel_T_2 = eq(io.enq[0].bits.virt_channel_id, UInt<2>(0h2))
node sel_0_2 = and(io.enq[0].valid, _sel_T_2)
connect qs_2.io.enq.valid, sel_0_2
connect qs_2.io.enq.bits.head, io.enq[0].bits.head
connect qs_2.io.enq.bits.tail, io.enq[0].bits.tail
connect qs_2.io.enq.bits.payload, io.enq[0].bits.payload
connect io.deq[2].bits, qs_2.io.deq.bits
connect io.deq[2].valid, qs_2.io.deq.valid
connect qs_2.io.deq.ready, io.deq[2].ready | module InputBuffer( // @[InputUnit.scala:49:7]
input clock, // @[InputUnit.scala:49:7]
input reset, // @[InputUnit.scala:49:7]
input io_enq_0_valid, // @[InputUnit.scala:51:14]
input io_enq_0_bits_head, // @[InputUnit.scala:51:14]
input io_enq_0_bits_tail, // @[InputUnit.scala:51:14]
input [144:0] io_enq_0_bits_payload, // @[InputUnit.scala:51:14]
input [1:0] io_enq_0_bits_virt_channel_id, // @[InputUnit.scala:51:14]
input io_deq_0_ready, // @[InputUnit.scala:51:14]
output io_deq_0_valid, // @[InputUnit.scala:51:14]
output io_deq_0_bits_head, // @[InputUnit.scala:51:14]
output io_deq_0_bits_tail, // @[InputUnit.scala:51:14]
output [144:0] io_deq_0_bits_payload, // @[InputUnit.scala:51:14]
input io_deq_1_ready, // @[InputUnit.scala:51:14]
output io_deq_1_valid, // @[InputUnit.scala:51:14]
output io_deq_1_bits_head, // @[InputUnit.scala:51:14]
output io_deq_1_bits_tail, // @[InputUnit.scala:51:14]
output [144:0] io_deq_1_bits_payload, // @[InputUnit.scala:51:14]
input io_deq_2_ready, // @[InputUnit.scala:51:14]
output io_deq_2_valid, // @[InputUnit.scala:51:14]
output io_deq_2_bits_head, // @[InputUnit.scala:51:14]
output io_deq_2_bits_tail, // @[InputUnit.scala:51:14]
output [144:0] io_deq_2_bits_payload // @[InputUnit.scala:51:14]
);
Queue3_BaseFlit qs_0 ( // @[InputUnit.scala:75:57]
.clock (clock),
.reset (reset),
.io_enq_valid (io_enq_0_valid & io_enq_0_bits_virt_channel_id == 2'h0), // @[InputUnit.scala:77:{41,67}]
.io_enq_bits_head (io_enq_0_bits_head),
.io_enq_bits_tail (io_enq_0_bits_tail),
.io_enq_bits_payload (io_enq_0_bits_payload),
.io_deq_ready (io_deq_0_ready),
.io_deq_valid (io_deq_0_valid),
.io_deq_bits_head (io_deq_0_bits_head),
.io_deq_bits_tail (io_deq_0_bits_tail),
.io_deq_bits_payload (io_deq_0_bits_payload)
); // @[InputUnit.scala:75:57]
Queue3_BaseFlit qs_1 ( // @[InputUnit.scala:75:57]
.clock (clock),
.reset (reset),
.io_enq_valid (io_enq_0_valid & io_enq_0_bits_virt_channel_id == 2'h1), // @[InputUnit.scala:77:{41,67}]
.io_enq_bits_head (io_enq_0_bits_head),
.io_enq_bits_tail (io_enq_0_bits_tail),
.io_enq_bits_payload (io_enq_0_bits_payload),
.io_deq_ready (io_deq_1_ready),
.io_deq_valid (io_deq_1_valid),
.io_deq_bits_head (io_deq_1_bits_head),
.io_deq_bits_tail (io_deq_1_bits_tail),
.io_deq_bits_payload (io_deq_1_bits_payload)
); // @[InputUnit.scala:75:57]
Queue3_BaseFlit qs_2 ( // @[InputUnit.scala:75:57]
.clock (clock),
.reset (reset),
.io_enq_valid (io_enq_0_valid & io_enq_0_bits_virt_channel_id == 2'h2), // @[InputUnit.scala:77:{41,67}]
.io_enq_bits_head (io_enq_0_bits_head),
.io_enq_bits_tail (io_enq_0_bits_tail),
.io_enq_bits_payload (io_enq_0_bits_payload),
.io_deq_ready (io_deq_2_ready),
.io_deq_valid (io_deq_2_valid),
.io_deq_bits_head (io_deq_2_bits_head),
.io_deq_bits_tail (io_deq_2_bits_tail),
.io_deq_bits_payload (io_deq_2_bits_payload)
); // @[InputUnit.scala:75:57]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_46 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<4>, q : UInt<4>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_409
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
node _output_T_2 = asAsyncReset(reset)
node _output_T_3 = bits(io.d, 1, 1)
inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_410
connect output_chain_1.clock, clock
connect output_chain_1.reset, _output_T_2
connect output_chain_1.io.d, _output_T_3
wire output_1 : UInt<1>
connect output_1, output_chain_1.io.q
node _output_T_4 = asAsyncReset(reset)
node _output_T_5 = bits(io.d, 2, 2)
inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_411
connect output_chain_2.clock, clock
connect output_chain_2.reset, _output_T_4
connect output_chain_2.io.d, _output_T_5
wire output_2 : UInt<1>
connect output_2, output_chain_2.io.q
node _output_T_6 = asAsyncReset(reset)
node _output_T_7 = bits(io.d, 3, 3)
inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_412
connect output_chain_3.clock, clock
connect output_chain_3.reset, _output_T_6
connect output_chain_3.io.d, _output_T_7
wire output_3 : UInt<1>
connect output_3, output_chain_3.io.q
node io_q_lo = cat(output_1, output_0)
node io_q_hi = cat(output_3, output_2)
node _io_q_T = cat(io_q_hi, io_q_lo)
connect io.q, _io_q_T | module AsyncResetSynchronizerShiftReg_w4_d3_i0_46( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_409 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_410 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_411 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_412 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_71 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node adjustedSig = shl(io.in.sig, 0)
node doShiftSigDown1 = bits(adjustedSig, 26, 26)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _roundMask_T = bits(io.in.sExp, 8, 0)
node _roundMask_T_1 = not(_roundMask_T)
node roundMask_msb = bits(_roundMask_T_1, 8, 8)
node roundMask_lsbs = bits(_roundMask_T_1, 7, 0)
node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7)
node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0)
node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2)
node _roundMask_T_2 = bits(roundMask_shift, 63, 42)
node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0)
node _roundMask_T_4 = shl(UInt<8>(0hff), 8)
node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4)
node _roundMask_T_6 = shr(_roundMask_T_3, 8)
node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5)
node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0)
node _roundMask_T_9 = shl(_roundMask_T_8, 8)
node _roundMask_T_10 = not(_roundMask_T_5)
node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10)
node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11)
node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0)
node _roundMask_T_14 = shl(_roundMask_T_13, 4)
node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14)
node _roundMask_T_16 = shr(_roundMask_T_12, 4)
node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15)
node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0)
node _roundMask_T_19 = shl(_roundMask_T_18, 4)
node _roundMask_T_20 = not(_roundMask_T_15)
node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20)
node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21)
node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0)
node _roundMask_T_24 = shl(_roundMask_T_23, 2)
node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24)
node _roundMask_T_26 = shr(_roundMask_T_22, 2)
node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25)
node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0)
node _roundMask_T_29 = shl(_roundMask_T_28, 2)
node _roundMask_T_30 = not(_roundMask_T_25)
node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30)
node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31)
node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0)
node _roundMask_T_34 = shl(_roundMask_T_33, 1)
node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34)
node _roundMask_T_36 = shr(_roundMask_T_32, 1)
node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35)
node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0)
node _roundMask_T_39 = shl(_roundMask_T_38, 1)
node _roundMask_T_40 = not(_roundMask_T_35)
node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40)
node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41)
node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16)
node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0)
node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0)
node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0)
node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1)
node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47)
node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2)
node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0)
node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1)
node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51)
node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52)
node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4)
node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0)
node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1)
node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56)
node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57)
node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58)
node _roundMask_T_60 = not(_roundMask_T_59)
node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60)
node _roundMask_T_62 = not(_roundMask_T_61)
node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7))
node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3)
node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0)
node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0)
node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0)
node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1)
node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67)
node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2)
node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69)
node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0))
node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71)
node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0))
node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1)
node roundMask = cat(_roundMask_T_74, UInt<2>(0h3))
node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask)
node shiftedRoundMask = shr(_shiftedRoundMask_T, 1)
node _roundPosMask_T = not(shiftedRoundMask)
node roundPosMask = and(_roundPosMask_T, roundMask)
node _roundPosBit_T = and(adjustedSig, roundPosMask)
node roundPosBit = orr(_roundPosBit_T)
node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask)
node anyRoundExtra = orr(_anyRoundExtra_T)
node anyRound = or(roundPosBit, anyRoundExtra)
node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit)
node _roundIncr_T_2 = and(roundMagUp, anyRound)
node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2)
node _roundedSig_T = or(adjustedSig, roundMask)
node _roundedSig_T_1 = shr(_roundedSig_T, 2)
node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1))
node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit)
node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0))
node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4)
node _roundedSig_T_6 = shr(roundMask, 1)
node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0))
node _roundedSig_T_8 = not(_roundedSig_T_7)
node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8)
node _roundedSig_T_10 = not(roundMask)
node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10)
node _roundedSig_T_12 = shr(_roundedSig_T_11, 2)
node _roundedSig_T_13 = and(roundingMode_odd, anyRound)
node _roundedSig_T_14 = shr(roundPosMask, 1)
node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0))
node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15)
node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16)
node _sRoundedExp_T = shr(roundedSig, 24)
node _sRoundedExp_T_1 = cvt(_sRoundedExp_T)
node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1)
node _common_expOut_T = bits(sRoundedExp, 8, 0)
connect common_expOut, _common_expOut_T
node _common_fractOut_T = bits(roundedSig, 23, 1)
node _common_fractOut_T_1 = bits(roundedSig, 22, 0)
node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
node _common_overflow_T = shr(sRoundedExp, 7)
node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3)))
connect common_overflow, _common_overflow_T_1
node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b)))
connect common_totalUnderflow, _common_totalUnderflow_T
node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2)
node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1)
node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1)
node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2)
node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T)
node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0)
node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2)
node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3)
node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit)
node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound)
node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2)
node _roundCarry_T = bits(roundedSig, 25, 25)
node _roundCarry_T_1 = bits(roundedSig, 24, 24)
node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1)
node _common_underflow_T = shr(io.in.sExp, 8)
node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0)))
node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1)
node _common_underflow_T_3 = bits(roundMask, 3, 3)
node _common_underflow_T_4 = bits(roundMask, 2, 2)
node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4)
node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5)
node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1))
node _common_underflow_T_8 = bits(roundMask, 4, 4)
node _common_underflow_T_9 = bits(roundMask, 3, 3)
node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9)
node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0))
node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11)
node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry)
node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit)
node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr)
node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0))
node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16)
node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17)
connect common_underflow, _common_underflow_T_18
node _common_inexact_T = or(common_totalUnderflow, anyRound)
connect common_inexact, _common_inexact_T
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_71( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20]
wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53]
wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38]
wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29]
wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42]
wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25]
wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26]
wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56]
wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22]
wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22]
wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20]
wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20]
wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20]
wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20]
wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20]
wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20]
wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}]
wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}]
wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17]
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56]
wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22]
wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20]
wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20]
wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20]
wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58]
wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24]
wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24]
wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67]
wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49]
wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31]
wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}]
wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46]
wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]
wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]
wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]
wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]
wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_14 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
wire _source_ok_WIRE : UInt<1>[5]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
node _source_ok_T_25 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_26 = or(_source_ok_T_25, _source_ok_WIRE[2])
node _source_ok_T_27 = or(_source_ok_T_26, _source_ok_WIRE[3])
node source_ok = or(_source_ok_T_27, _source_ok_WIRE[4])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = and(_T_11, _T_24)
node _T_65 = and(_T_64, _T_37)
node _T_66 = and(_T_65, _T_50)
node _T_67 = and(_T_66, _T_63)
node _T_68 = asUInt(reset)
node _T_69 = eq(_T_68, UInt<1>(0h0))
when _T_69 :
node _T_70 = eq(_T_67, UInt<1>(0h0))
when _T_70 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_67, UInt<1>(0h1), "") : assert_1
node _T_71 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_71 :
node _T_72 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_73 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_74 = and(_T_72, _T_73)
node _T_75 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_76 = shr(io.in.a.bits.source, 2)
node _T_77 = eq(_T_76, UInt<1>(0h0))
node _T_78 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_79 = and(_T_77, _T_78)
node _T_80 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_81 = and(_T_79, _T_80)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_82 = shr(io.in.a.bits.source, 2)
node _T_83 = eq(_T_82, UInt<1>(0h1))
node _T_84 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_85 = and(_T_83, _T_84)
node _T_86 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_87 = and(_T_85, _T_86)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_88 = shr(io.in.a.bits.source, 2)
node _T_89 = eq(_T_88, UInt<2>(0h2))
node _T_90 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_91 = and(_T_89, _T_90)
node _T_92 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_93 = and(_T_91, _T_92)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_94 = shr(io.in.a.bits.source, 2)
node _T_95 = eq(_T_94, UInt<2>(0h3))
node _T_96 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_97 = and(_T_95, _T_96)
node _T_98 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_99 = and(_T_97, _T_98)
node _T_100 = or(_T_75, _T_81)
node _T_101 = or(_T_100, _T_87)
node _T_102 = or(_T_101, _T_93)
node _T_103 = or(_T_102, _T_99)
node _T_104 = and(_T_74, _T_103)
node _T_105 = or(UInt<1>(0h0), _T_104)
node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_107 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_108 = cvt(_T_107)
node _T_109 = and(_T_108, asSInt(UInt<14>(0h2000)))
node _T_110 = asSInt(_T_109)
node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0)))
node _T_112 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_113 = cvt(_T_112)
node _T_114 = and(_T_113, asSInt(UInt<13>(0h1000)))
node _T_115 = asSInt(_T_114)
node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_118 = cvt(_T_117)
node _T_119 = and(_T_118, asSInt(UInt<17>(0h10000)))
node _T_120 = asSInt(_T_119)
node _T_121 = eq(_T_120, asSInt(UInt<1>(0h0)))
node _T_122 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_123 = cvt(_T_122)
node _T_124 = and(_T_123, asSInt(UInt<18>(0h2f000)))
node _T_125 = asSInt(_T_124)
node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0)))
node _T_127 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_128 = cvt(_T_127)
node _T_129 = and(_T_128, asSInt(UInt<17>(0h10000)))
node _T_130 = asSInt(_T_129)
node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0)))
node _T_132 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_133 = cvt(_T_132)
node _T_134 = and(_T_133, asSInt(UInt<13>(0h1000)))
node _T_135 = asSInt(_T_134)
node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0)))
node _T_137 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_138 = cvt(_T_137)
node _T_139 = and(_T_138, asSInt(UInt<27>(0h4000000)))
node _T_140 = asSInt(_T_139)
node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0)))
node _T_142 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_143 = cvt(_T_142)
node _T_144 = and(_T_143, asSInt(UInt<13>(0h1000)))
node _T_145 = asSInt(_T_144)
node _T_146 = eq(_T_145, asSInt(UInt<1>(0h0)))
node _T_147 = or(_T_111, _T_116)
node _T_148 = or(_T_147, _T_121)
node _T_149 = or(_T_148, _T_126)
node _T_150 = or(_T_149, _T_131)
node _T_151 = or(_T_150, _T_136)
node _T_152 = or(_T_151, _T_141)
node _T_153 = or(_T_152, _T_146)
node _T_154 = and(_T_106, _T_153)
node _T_155 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_156 = or(UInt<1>(0h0), _T_155)
node _T_157 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_158 = cvt(_T_157)
node _T_159 = and(_T_158, asSInt(UInt<17>(0h10000)))
node _T_160 = asSInt(_T_159)
node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0)))
node _T_162 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_163 = cvt(_T_162)
node _T_164 = and(_T_163, asSInt(UInt<29>(0h10000000)))
node _T_165 = asSInt(_T_164)
node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0)))
node _T_167 = or(_T_161, _T_166)
node _T_168 = and(_T_156, _T_167)
node _T_169 = or(UInt<1>(0h0), _T_154)
node _T_170 = or(_T_169, _T_168)
node _T_171 = and(_T_105, _T_170)
node _T_172 = asUInt(reset)
node _T_173 = eq(_T_172, UInt<1>(0h0))
when _T_173 :
node _T_174 = eq(_T_171, UInt<1>(0h0))
when _T_174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_171, UInt<1>(0h1), "") : assert_2
node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_177 = and(_T_175, _T_176)
node _T_178 = or(UInt<1>(0h0), _T_177)
node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_180 = cvt(_T_179)
node _T_181 = and(_T_180, asSInt(UInt<14>(0h2000)))
node _T_182 = asSInt(_T_181)
node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0)))
node _T_184 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_185 = cvt(_T_184)
node _T_186 = and(_T_185, asSInt(UInt<13>(0h1000)))
node _T_187 = asSInt(_T_186)
node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_190 = cvt(_T_189)
node _T_191 = and(_T_190, asSInt(UInt<17>(0h10000)))
node _T_192 = asSInt(_T_191)
node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0)))
node _T_194 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<18>(0h2f000)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_200 = cvt(_T_199)
node _T_201 = and(_T_200, asSInt(UInt<17>(0h10000)))
node _T_202 = asSInt(_T_201)
node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0)))
node _T_204 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_205 = cvt(_T_204)
node _T_206 = and(_T_205, asSInt(UInt<13>(0h1000)))
node _T_207 = asSInt(_T_206)
node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0)))
node _T_209 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_210 = cvt(_T_209)
node _T_211 = and(_T_210, asSInt(UInt<17>(0h10000)))
node _T_212 = asSInt(_T_211)
node _T_213 = eq(_T_212, asSInt(UInt<1>(0h0)))
node _T_214 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_215 = cvt(_T_214)
node _T_216 = and(_T_215, asSInt(UInt<27>(0h4000000)))
node _T_217 = asSInt(_T_216)
node _T_218 = eq(_T_217, asSInt(UInt<1>(0h0)))
node _T_219 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_220 = cvt(_T_219)
node _T_221 = and(_T_220, asSInt(UInt<13>(0h1000)))
node _T_222 = asSInt(_T_221)
node _T_223 = eq(_T_222, asSInt(UInt<1>(0h0)))
node _T_224 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_225 = cvt(_T_224)
node _T_226 = and(_T_225, asSInt(UInt<29>(0h10000000)))
node _T_227 = asSInt(_T_226)
node _T_228 = eq(_T_227, asSInt(UInt<1>(0h0)))
node _T_229 = or(_T_183, _T_188)
node _T_230 = or(_T_229, _T_193)
node _T_231 = or(_T_230, _T_198)
node _T_232 = or(_T_231, _T_203)
node _T_233 = or(_T_232, _T_208)
node _T_234 = or(_T_233, _T_213)
node _T_235 = or(_T_234, _T_218)
node _T_236 = or(_T_235, _T_223)
node _T_237 = or(_T_236, _T_228)
node _T_238 = and(_T_178, _T_237)
node _T_239 = or(UInt<1>(0h0), _T_238)
node _T_240 = and(UInt<1>(0h0), _T_239)
node _T_241 = asUInt(reset)
node _T_242 = eq(_T_241, UInt<1>(0h0))
when _T_242 :
node _T_243 = eq(_T_240, UInt<1>(0h0))
when _T_243 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_240, UInt<1>(0h1), "") : assert_3
node _T_244 = asUInt(reset)
node _T_245 = eq(_T_244, UInt<1>(0h0))
when _T_245 :
node _T_246 = eq(source_ok, UInt<1>(0h0))
when _T_246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_247 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_248 = asUInt(reset)
node _T_249 = eq(_T_248, UInt<1>(0h0))
when _T_249 :
node _T_250 = eq(_T_247, UInt<1>(0h0))
when _T_250 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_247, UInt<1>(0h1), "") : assert_5
node _T_251 = asUInt(reset)
node _T_252 = eq(_T_251, UInt<1>(0h0))
when _T_252 :
node _T_253 = eq(is_aligned, UInt<1>(0h0))
when _T_253 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_254 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_254, UInt<1>(0h1), "") : assert_7
node _T_258 = not(io.in.a.bits.mask)
node _T_259 = eq(_T_258, UInt<1>(0h0))
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_259, UInt<1>(0h1), "") : assert_8
node _T_263 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_264 = asUInt(reset)
node _T_265 = eq(_T_264, UInt<1>(0h0))
when _T_265 :
node _T_266 = eq(_T_263, UInt<1>(0h0))
when _T_266 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_263, UInt<1>(0h1), "") : assert_9
node _T_267 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_267 :
node _T_268 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_269 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_270 = and(_T_268, _T_269)
node _T_271 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_272 = shr(io.in.a.bits.source, 2)
node _T_273 = eq(_T_272, UInt<1>(0h0))
node _T_274 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_275 = and(_T_273, _T_274)
node _T_276 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_277 = and(_T_275, _T_276)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_278 = shr(io.in.a.bits.source, 2)
node _T_279 = eq(_T_278, UInt<1>(0h1))
node _T_280 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_281 = and(_T_279, _T_280)
node _T_282 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_283 = and(_T_281, _T_282)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_284 = shr(io.in.a.bits.source, 2)
node _T_285 = eq(_T_284, UInt<2>(0h2))
node _T_286 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_287 = and(_T_285, _T_286)
node _T_288 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_289 = and(_T_287, _T_288)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_290 = shr(io.in.a.bits.source, 2)
node _T_291 = eq(_T_290, UInt<2>(0h3))
node _T_292 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_293 = and(_T_291, _T_292)
node _T_294 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_295 = and(_T_293, _T_294)
node _T_296 = or(_T_271, _T_277)
node _T_297 = or(_T_296, _T_283)
node _T_298 = or(_T_297, _T_289)
node _T_299 = or(_T_298, _T_295)
node _T_300 = and(_T_270, _T_299)
node _T_301 = or(UInt<1>(0h0), _T_300)
node _T_302 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_303 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_304 = cvt(_T_303)
node _T_305 = and(_T_304, asSInt(UInt<14>(0h2000)))
node _T_306 = asSInt(_T_305)
node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0)))
node _T_308 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_309 = cvt(_T_308)
node _T_310 = and(_T_309, asSInt(UInt<13>(0h1000)))
node _T_311 = asSInt(_T_310)
node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0)))
node _T_313 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_314 = cvt(_T_313)
node _T_315 = and(_T_314, asSInt(UInt<17>(0h10000)))
node _T_316 = asSInt(_T_315)
node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0)))
node _T_318 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_319 = cvt(_T_318)
node _T_320 = and(_T_319, asSInt(UInt<18>(0h2f000)))
node _T_321 = asSInt(_T_320)
node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0)))
node _T_323 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_324 = cvt(_T_323)
node _T_325 = and(_T_324, asSInt(UInt<17>(0h10000)))
node _T_326 = asSInt(_T_325)
node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0)))
node _T_328 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_329 = cvt(_T_328)
node _T_330 = and(_T_329, asSInt(UInt<13>(0h1000)))
node _T_331 = asSInt(_T_330)
node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0)))
node _T_333 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_334 = cvt(_T_333)
node _T_335 = and(_T_334, asSInt(UInt<27>(0h4000000)))
node _T_336 = asSInt(_T_335)
node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0)))
node _T_338 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_339 = cvt(_T_338)
node _T_340 = and(_T_339, asSInt(UInt<13>(0h1000)))
node _T_341 = asSInt(_T_340)
node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0)))
node _T_343 = or(_T_307, _T_312)
node _T_344 = or(_T_343, _T_317)
node _T_345 = or(_T_344, _T_322)
node _T_346 = or(_T_345, _T_327)
node _T_347 = or(_T_346, _T_332)
node _T_348 = or(_T_347, _T_337)
node _T_349 = or(_T_348, _T_342)
node _T_350 = and(_T_302, _T_349)
node _T_351 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_352 = or(UInt<1>(0h0), _T_351)
node _T_353 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_354 = cvt(_T_353)
node _T_355 = and(_T_354, asSInt(UInt<17>(0h10000)))
node _T_356 = asSInt(_T_355)
node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0)))
node _T_358 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_359 = cvt(_T_358)
node _T_360 = and(_T_359, asSInt(UInt<29>(0h10000000)))
node _T_361 = asSInt(_T_360)
node _T_362 = eq(_T_361, asSInt(UInt<1>(0h0)))
node _T_363 = or(_T_357, _T_362)
node _T_364 = and(_T_352, _T_363)
node _T_365 = or(UInt<1>(0h0), _T_350)
node _T_366 = or(_T_365, _T_364)
node _T_367 = and(_T_301, _T_366)
node _T_368 = asUInt(reset)
node _T_369 = eq(_T_368, UInt<1>(0h0))
when _T_369 :
node _T_370 = eq(_T_367, UInt<1>(0h0))
when _T_370 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_367, UInt<1>(0h1), "") : assert_10
node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_373 = and(_T_371, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_376 = cvt(_T_375)
node _T_377 = and(_T_376, asSInt(UInt<14>(0h2000)))
node _T_378 = asSInt(_T_377)
node _T_379 = eq(_T_378, asSInt(UInt<1>(0h0)))
node _T_380 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_381 = cvt(_T_380)
node _T_382 = and(_T_381, asSInt(UInt<13>(0h1000)))
node _T_383 = asSInt(_T_382)
node _T_384 = eq(_T_383, asSInt(UInt<1>(0h0)))
node _T_385 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_386 = cvt(_T_385)
node _T_387 = and(_T_386, asSInt(UInt<17>(0h10000)))
node _T_388 = asSInt(_T_387)
node _T_389 = eq(_T_388, asSInt(UInt<1>(0h0)))
node _T_390 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_391 = cvt(_T_390)
node _T_392 = and(_T_391, asSInt(UInt<18>(0h2f000)))
node _T_393 = asSInt(_T_392)
node _T_394 = eq(_T_393, asSInt(UInt<1>(0h0)))
node _T_395 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_396 = cvt(_T_395)
node _T_397 = and(_T_396, asSInt(UInt<17>(0h10000)))
node _T_398 = asSInt(_T_397)
node _T_399 = eq(_T_398, asSInt(UInt<1>(0h0)))
node _T_400 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_401 = cvt(_T_400)
node _T_402 = and(_T_401, asSInt(UInt<13>(0h1000)))
node _T_403 = asSInt(_T_402)
node _T_404 = eq(_T_403, asSInt(UInt<1>(0h0)))
node _T_405 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_406 = cvt(_T_405)
node _T_407 = and(_T_406, asSInt(UInt<17>(0h10000)))
node _T_408 = asSInt(_T_407)
node _T_409 = eq(_T_408, asSInt(UInt<1>(0h0)))
node _T_410 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_411 = cvt(_T_410)
node _T_412 = and(_T_411, asSInt(UInt<27>(0h4000000)))
node _T_413 = asSInt(_T_412)
node _T_414 = eq(_T_413, asSInt(UInt<1>(0h0)))
node _T_415 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_416 = cvt(_T_415)
node _T_417 = and(_T_416, asSInt(UInt<13>(0h1000)))
node _T_418 = asSInt(_T_417)
node _T_419 = eq(_T_418, asSInt(UInt<1>(0h0)))
node _T_420 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_421 = cvt(_T_420)
node _T_422 = and(_T_421, asSInt(UInt<29>(0h10000000)))
node _T_423 = asSInt(_T_422)
node _T_424 = eq(_T_423, asSInt(UInt<1>(0h0)))
node _T_425 = or(_T_379, _T_384)
node _T_426 = or(_T_425, _T_389)
node _T_427 = or(_T_426, _T_394)
node _T_428 = or(_T_427, _T_399)
node _T_429 = or(_T_428, _T_404)
node _T_430 = or(_T_429, _T_409)
node _T_431 = or(_T_430, _T_414)
node _T_432 = or(_T_431, _T_419)
node _T_433 = or(_T_432, _T_424)
node _T_434 = and(_T_374, _T_433)
node _T_435 = or(UInt<1>(0h0), _T_434)
node _T_436 = and(UInt<1>(0h0), _T_435)
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_436, UInt<1>(0h1), "") : assert_11
node _T_440 = asUInt(reset)
node _T_441 = eq(_T_440, UInt<1>(0h0))
when _T_441 :
node _T_442 = eq(source_ok, UInt<1>(0h0))
when _T_442 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_443 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_444 = asUInt(reset)
node _T_445 = eq(_T_444, UInt<1>(0h0))
when _T_445 :
node _T_446 = eq(_T_443, UInt<1>(0h0))
when _T_446 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_443, UInt<1>(0h1), "") : assert_13
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(is_aligned, UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_450 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_451 = asUInt(reset)
node _T_452 = eq(_T_451, UInt<1>(0h0))
when _T_452 :
node _T_453 = eq(_T_450, UInt<1>(0h0))
when _T_453 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_450, UInt<1>(0h1), "") : assert_15
node _T_454 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_455 = asUInt(reset)
node _T_456 = eq(_T_455, UInt<1>(0h0))
when _T_456 :
node _T_457 = eq(_T_454, UInt<1>(0h0))
when _T_457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_454, UInt<1>(0h1), "") : assert_16
node _T_458 = not(io.in.a.bits.mask)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_459, UInt<1>(0h1), "") : assert_17
node _T_463 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_463, UInt<1>(0h1), "") : assert_18
node _T_467 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_467 :
node _T_468 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_469 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_470 = and(_T_468, _T_469)
node _T_471 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_472 = shr(io.in.a.bits.source, 2)
node _T_473 = eq(_T_472, UInt<1>(0h0))
node _T_474 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_475 = and(_T_473, _T_474)
node _T_476 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_477 = and(_T_475, _T_476)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_478 = shr(io.in.a.bits.source, 2)
node _T_479 = eq(_T_478, UInt<1>(0h1))
node _T_480 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_481 = and(_T_479, _T_480)
node _T_482 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_483 = and(_T_481, _T_482)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_484 = shr(io.in.a.bits.source, 2)
node _T_485 = eq(_T_484, UInt<2>(0h2))
node _T_486 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_487 = and(_T_485, _T_486)
node _T_488 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_489 = and(_T_487, _T_488)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_490 = shr(io.in.a.bits.source, 2)
node _T_491 = eq(_T_490, UInt<2>(0h3))
node _T_492 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_493 = and(_T_491, _T_492)
node _T_494 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_495 = and(_T_493, _T_494)
node _T_496 = or(_T_471, _T_477)
node _T_497 = or(_T_496, _T_483)
node _T_498 = or(_T_497, _T_489)
node _T_499 = or(_T_498, _T_495)
node _T_500 = and(_T_470, _T_499)
node _T_501 = or(UInt<1>(0h0), _T_500)
node _T_502 = asUInt(reset)
node _T_503 = eq(_T_502, UInt<1>(0h0))
when _T_503 :
node _T_504 = eq(_T_501, UInt<1>(0h0))
when _T_504 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_501, UInt<1>(0h1), "") : assert_19
node _T_505 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_506 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_507 = and(_T_505, _T_506)
node _T_508 = or(UInt<1>(0h0), _T_507)
node _T_509 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_510 = cvt(_T_509)
node _T_511 = and(_T_510, asSInt(UInt<13>(0h1000)))
node _T_512 = asSInt(_T_511)
node _T_513 = eq(_T_512, asSInt(UInt<1>(0h0)))
node _T_514 = and(_T_508, _T_513)
node _T_515 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_516 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_517 = and(_T_515, _T_516)
node _T_518 = or(UInt<1>(0h0), _T_517)
node _T_519 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_520 = cvt(_T_519)
node _T_521 = and(_T_520, asSInt(UInt<14>(0h2000)))
node _T_522 = asSInt(_T_521)
node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0)))
node _T_524 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_525 = cvt(_T_524)
node _T_526 = and(_T_525, asSInt(UInt<17>(0h10000)))
node _T_527 = asSInt(_T_526)
node _T_528 = eq(_T_527, asSInt(UInt<1>(0h0)))
node _T_529 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_530 = cvt(_T_529)
node _T_531 = and(_T_530, asSInt(UInt<18>(0h2f000)))
node _T_532 = asSInt(_T_531)
node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0)))
node _T_534 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_535 = cvt(_T_534)
node _T_536 = and(_T_535, asSInt(UInt<17>(0h10000)))
node _T_537 = asSInt(_T_536)
node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0)))
node _T_539 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_540 = cvt(_T_539)
node _T_541 = and(_T_540, asSInt(UInt<13>(0h1000)))
node _T_542 = asSInt(_T_541)
node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0)))
node _T_544 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_545 = cvt(_T_544)
node _T_546 = and(_T_545, asSInt(UInt<17>(0h10000)))
node _T_547 = asSInt(_T_546)
node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0)))
node _T_549 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_550 = cvt(_T_549)
node _T_551 = and(_T_550, asSInt(UInt<27>(0h4000000)))
node _T_552 = asSInt(_T_551)
node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0)))
node _T_554 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_555 = cvt(_T_554)
node _T_556 = and(_T_555, asSInt(UInt<13>(0h1000)))
node _T_557 = asSInt(_T_556)
node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0)))
node _T_559 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_560 = cvt(_T_559)
node _T_561 = and(_T_560, asSInt(UInt<29>(0h10000000)))
node _T_562 = asSInt(_T_561)
node _T_563 = eq(_T_562, asSInt(UInt<1>(0h0)))
node _T_564 = or(_T_523, _T_528)
node _T_565 = or(_T_564, _T_533)
node _T_566 = or(_T_565, _T_538)
node _T_567 = or(_T_566, _T_543)
node _T_568 = or(_T_567, _T_548)
node _T_569 = or(_T_568, _T_553)
node _T_570 = or(_T_569, _T_558)
node _T_571 = or(_T_570, _T_563)
node _T_572 = and(_T_518, _T_571)
node _T_573 = or(UInt<1>(0h0), _T_514)
node _T_574 = or(_T_573, _T_572)
node _T_575 = asUInt(reset)
node _T_576 = eq(_T_575, UInt<1>(0h0))
when _T_576 :
node _T_577 = eq(_T_574, UInt<1>(0h0))
when _T_577 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_574, UInt<1>(0h1), "") : assert_20
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(source_ok, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(is_aligned, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_584 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_584, UInt<1>(0h1), "") : assert_23
node _T_588 = eq(io.in.a.bits.mask, mask)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_588, UInt<1>(0h1), "") : assert_24
node _T_592 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_593 = asUInt(reset)
node _T_594 = eq(_T_593, UInt<1>(0h0))
when _T_594 :
node _T_595 = eq(_T_592, UInt<1>(0h0))
when _T_595 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_592, UInt<1>(0h1), "") : assert_25
node _T_596 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_596 :
node _T_597 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_598 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_599 = and(_T_597, _T_598)
node _T_600 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_601 = shr(io.in.a.bits.source, 2)
node _T_602 = eq(_T_601, UInt<1>(0h0))
node _T_603 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_604 = and(_T_602, _T_603)
node _T_605 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_606 = and(_T_604, _T_605)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_607 = shr(io.in.a.bits.source, 2)
node _T_608 = eq(_T_607, UInt<1>(0h1))
node _T_609 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_610 = and(_T_608, _T_609)
node _T_611 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_612 = and(_T_610, _T_611)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_613 = shr(io.in.a.bits.source, 2)
node _T_614 = eq(_T_613, UInt<2>(0h2))
node _T_615 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_616 = and(_T_614, _T_615)
node _T_617 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_618 = and(_T_616, _T_617)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_619 = shr(io.in.a.bits.source, 2)
node _T_620 = eq(_T_619, UInt<2>(0h3))
node _T_621 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_622 = and(_T_620, _T_621)
node _T_623 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_624 = and(_T_622, _T_623)
node _T_625 = or(_T_600, _T_606)
node _T_626 = or(_T_625, _T_612)
node _T_627 = or(_T_626, _T_618)
node _T_628 = or(_T_627, _T_624)
node _T_629 = and(_T_599, _T_628)
node _T_630 = or(UInt<1>(0h0), _T_629)
node _T_631 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_632 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_633 = and(_T_631, _T_632)
node _T_634 = or(UInt<1>(0h0), _T_633)
node _T_635 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_636 = cvt(_T_635)
node _T_637 = and(_T_636, asSInt(UInt<13>(0h1000)))
node _T_638 = asSInt(_T_637)
node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0)))
node _T_640 = and(_T_634, _T_639)
node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_642 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_643 = and(_T_641, _T_642)
node _T_644 = or(UInt<1>(0h0), _T_643)
node _T_645 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_646 = cvt(_T_645)
node _T_647 = and(_T_646, asSInt(UInt<14>(0h2000)))
node _T_648 = asSInt(_T_647)
node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0)))
node _T_650 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_651 = cvt(_T_650)
node _T_652 = and(_T_651, asSInt(UInt<18>(0h2f000)))
node _T_653 = asSInt(_T_652)
node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0)))
node _T_655 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_656 = cvt(_T_655)
node _T_657 = and(_T_656, asSInt(UInt<17>(0h10000)))
node _T_658 = asSInt(_T_657)
node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0)))
node _T_660 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_661 = cvt(_T_660)
node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000)))
node _T_663 = asSInt(_T_662)
node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0)))
node _T_665 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_666 = cvt(_T_665)
node _T_667 = and(_T_666, asSInt(UInt<17>(0h10000)))
node _T_668 = asSInt(_T_667)
node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0)))
node _T_670 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_671 = cvt(_T_670)
node _T_672 = and(_T_671, asSInt(UInt<27>(0h4000000)))
node _T_673 = asSInt(_T_672)
node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0)))
node _T_675 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_676 = cvt(_T_675)
node _T_677 = and(_T_676, asSInt(UInt<13>(0h1000)))
node _T_678 = asSInt(_T_677)
node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0)))
node _T_680 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_681 = cvt(_T_680)
node _T_682 = and(_T_681, asSInt(UInt<29>(0h10000000)))
node _T_683 = asSInt(_T_682)
node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0)))
node _T_685 = or(_T_649, _T_654)
node _T_686 = or(_T_685, _T_659)
node _T_687 = or(_T_686, _T_664)
node _T_688 = or(_T_687, _T_669)
node _T_689 = or(_T_688, _T_674)
node _T_690 = or(_T_689, _T_679)
node _T_691 = or(_T_690, _T_684)
node _T_692 = and(_T_644, _T_691)
node _T_693 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_694 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_695 = cvt(_T_694)
node _T_696 = and(_T_695, asSInt(UInt<17>(0h10000)))
node _T_697 = asSInt(_T_696)
node _T_698 = eq(_T_697, asSInt(UInt<1>(0h0)))
node _T_699 = and(_T_693, _T_698)
node _T_700 = or(UInt<1>(0h0), _T_640)
node _T_701 = or(_T_700, _T_692)
node _T_702 = or(_T_701, _T_699)
node _T_703 = and(_T_630, _T_702)
node _T_704 = asUInt(reset)
node _T_705 = eq(_T_704, UInt<1>(0h0))
when _T_705 :
node _T_706 = eq(_T_703, UInt<1>(0h0))
when _T_706 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_703, UInt<1>(0h1), "") : assert_26
node _T_707 = asUInt(reset)
node _T_708 = eq(_T_707, UInt<1>(0h0))
when _T_708 :
node _T_709 = eq(source_ok, UInt<1>(0h0))
when _T_709 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_710 = asUInt(reset)
node _T_711 = eq(_T_710, UInt<1>(0h0))
when _T_711 :
node _T_712 = eq(is_aligned, UInt<1>(0h0))
when _T_712 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_713 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_714 = asUInt(reset)
node _T_715 = eq(_T_714, UInt<1>(0h0))
when _T_715 :
node _T_716 = eq(_T_713, UInt<1>(0h0))
when _T_716 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_713, UInt<1>(0h1), "") : assert_29
node _T_717 = eq(io.in.a.bits.mask, mask)
node _T_718 = asUInt(reset)
node _T_719 = eq(_T_718, UInt<1>(0h0))
when _T_719 :
node _T_720 = eq(_T_717, UInt<1>(0h0))
when _T_720 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_717, UInt<1>(0h1), "") : assert_30
node _T_721 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_721 :
node _T_722 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_723 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_724 = and(_T_722, _T_723)
node _T_725 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_726 = shr(io.in.a.bits.source, 2)
node _T_727 = eq(_T_726, UInt<1>(0h0))
node _T_728 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_729 = and(_T_727, _T_728)
node _T_730 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_731 = and(_T_729, _T_730)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_732 = shr(io.in.a.bits.source, 2)
node _T_733 = eq(_T_732, UInt<1>(0h1))
node _T_734 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_735 = and(_T_733, _T_734)
node _T_736 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_737 = and(_T_735, _T_736)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_738 = shr(io.in.a.bits.source, 2)
node _T_739 = eq(_T_738, UInt<2>(0h2))
node _T_740 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_741 = and(_T_739, _T_740)
node _T_742 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_743 = and(_T_741, _T_742)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_744 = shr(io.in.a.bits.source, 2)
node _T_745 = eq(_T_744, UInt<2>(0h3))
node _T_746 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_747 = and(_T_745, _T_746)
node _T_748 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_749 = and(_T_747, _T_748)
node _T_750 = or(_T_725, _T_731)
node _T_751 = or(_T_750, _T_737)
node _T_752 = or(_T_751, _T_743)
node _T_753 = or(_T_752, _T_749)
node _T_754 = and(_T_724, _T_753)
node _T_755 = or(UInt<1>(0h0), _T_754)
node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_757 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_758 = and(_T_756, _T_757)
node _T_759 = or(UInt<1>(0h0), _T_758)
node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_761 = cvt(_T_760)
node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000)))
node _T_763 = asSInt(_T_762)
node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0)))
node _T_765 = and(_T_759, _T_764)
node _T_766 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_767 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_768 = and(_T_766, _T_767)
node _T_769 = or(UInt<1>(0h0), _T_768)
node _T_770 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_771 = cvt(_T_770)
node _T_772 = and(_T_771, asSInt(UInt<14>(0h2000)))
node _T_773 = asSInt(_T_772)
node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0)))
node _T_775 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_776 = cvt(_T_775)
node _T_777 = and(_T_776, asSInt(UInt<18>(0h2f000)))
node _T_778 = asSInt(_T_777)
node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0)))
node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_781 = cvt(_T_780)
node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000)))
node _T_783 = asSInt(_T_782)
node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0)))
node _T_785 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_786 = cvt(_T_785)
node _T_787 = and(_T_786, asSInt(UInt<13>(0h1000)))
node _T_788 = asSInt(_T_787)
node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0)))
node _T_790 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_791 = cvt(_T_790)
node _T_792 = and(_T_791, asSInt(UInt<17>(0h10000)))
node _T_793 = asSInt(_T_792)
node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0)))
node _T_795 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_796 = cvt(_T_795)
node _T_797 = and(_T_796, asSInt(UInt<27>(0h4000000)))
node _T_798 = asSInt(_T_797)
node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0)))
node _T_800 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_801 = cvt(_T_800)
node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000)))
node _T_803 = asSInt(_T_802)
node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0)))
node _T_805 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_806 = cvt(_T_805)
node _T_807 = and(_T_806, asSInt(UInt<29>(0h10000000)))
node _T_808 = asSInt(_T_807)
node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0)))
node _T_810 = or(_T_774, _T_779)
node _T_811 = or(_T_810, _T_784)
node _T_812 = or(_T_811, _T_789)
node _T_813 = or(_T_812, _T_794)
node _T_814 = or(_T_813, _T_799)
node _T_815 = or(_T_814, _T_804)
node _T_816 = or(_T_815, _T_809)
node _T_817 = and(_T_769, _T_816)
node _T_818 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_819 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_820 = cvt(_T_819)
node _T_821 = and(_T_820, asSInt(UInt<17>(0h10000)))
node _T_822 = asSInt(_T_821)
node _T_823 = eq(_T_822, asSInt(UInt<1>(0h0)))
node _T_824 = and(_T_818, _T_823)
node _T_825 = or(UInt<1>(0h0), _T_765)
node _T_826 = or(_T_825, _T_817)
node _T_827 = or(_T_826, _T_824)
node _T_828 = and(_T_755, _T_827)
node _T_829 = asUInt(reset)
node _T_830 = eq(_T_829, UInt<1>(0h0))
when _T_830 :
node _T_831 = eq(_T_828, UInt<1>(0h0))
when _T_831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_828, UInt<1>(0h1), "") : assert_31
node _T_832 = asUInt(reset)
node _T_833 = eq(_T_832, UInt<1>(0h0))
when _T_833 :
node _T_834 = eq(source_ok, UInt<1>(0h0))
when _T_834 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_835 = asUInt(reset)
node _T_836 = eq(_T_835, UInt<1>(0h0))
when _T_836 :
node _T_837 = eq(is_aligned, UInt<1>(0h0))
when _T_837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_838 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_839 = asUInt(reset)
node _T_840 = eq(_T_839, UInt<1>(0h0))
when _T_840 :
node _T_841 = eq(_T_838, UInt<1>(0h0))
when _T_841 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_838, UInt<1>(0h1), "") : assert_34
node _T_842 = not(mask)
node _T_843 = and(io.in.a.bits.mask, _T_842)
node _T_844 = eq(_T_843, UInt<1>(0h0))
node _T_845 = asUInt(reset)
node _T_846 = eq(_T_845, UInt<1>(0h0))
when _T_846 :
node _T_847 = eq(_T_844, UInt<1>(0h0))
when _T_847 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_844, UInt<1>(0h1), "") : assert_35
node _T_848 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_848 :
node _T_849 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_850 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_851 = and(_T_849, _T_850)
node _T_852 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_853 = shr(io.in.a.bits.source, 2)
node _T_854 = eq(_T_853, UInt<1>(0h0))
node _T_855 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_856 = and(_T_854, _T_855)
node _T_857 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_858 = and(_T_856, _T_857)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_859 = shr(io.in.a.bits.source, 2)
node _T_860 = eq(_T_859, UInt<1>(0h1))
node _T_861 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_862 = and(_T_860, _T_861)
node _T_863 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_864 = and(_T_862, _T_863)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_865 = shr(io.in.a.bits.source, 2)
node _T_866 = eq(_T_865, UInt<2>(0h2))
node _T_867 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_868 = and(_T_866, _T_867)
node _T_869 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_870 = and(_T_868, _T_869)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_871 = shr(io.in.a.bits.source, 2)
node _T_872 = eq(_T_871, UInt<2>(0h3))
node _T_873 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_874 = and(_T_872, _T_873)
node _T_875 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_876 = and(_T_874, _T_875)
node _T_877 = or(_T_852, _T_858)
node _T_878 = or(_T_877, _T_864)
node _T_879 = or(_T_878, _T_870)
node _T_880 = or(_T_879, _T_876)
node _T_881 = and(_T_851, _T_880)
node _T_882 = or(UInt<1>(0h0), _T_881)
node _T_883 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_884 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_885 = and(_T_883, _T_884)
node _T_886 = or(UInt<1>(0h0), _T_885)
node _T_887 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_888 = cvt(_T_887)
node _T_889 = and(_T_888, asSInt(UInt<14>(0h2000)))
node _T_890 = asSInt(_T_889)
node _T_891 = eq(_T_890, asSInt(UInt<1>(0h0)))
node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_893 = cvt(_T_892)
node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000)))
node _T_895 = asSInt(_T_894)
node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0)))
node _T_897 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_898 = cvt(_T_897)
node _T_899 = and(_T_898, asSInt(UInt<18>(0h2f000)))
node _T_900 = asSInt(_T_899)
node _T_901 = eq(_T_900, asSInt(UInt<1>(0h0)))
node _T_902 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_903 = cvt(_T_902)
node _T_904 = and(_T_903, asSInt(UInt<17>(0h10000)))
node _T_905 = asSInt(_T_904)
node _T_906 = eq(_T_905, asSInt(UInt<1>(0h0)))
node _T_907 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_908 = cvt(_T_907)
node _T_909 = and(_T_908, asSInt(UInt<13>(0h1000)))
node _T_910 = asSInt(_T_909)
node _T_911 = eq(_T_910, asSInt(UInt<1>(0h0)))
node _T_912 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_913 = cvt(_T_912)
node _T_914 = and(_T_913, asSInt(UInt<17>(0h10000)))
node _T_915 = asSInt(_T_914)
node _T_916 = eq(_T_915, asSInt(UInt<1>(0h0)))
node _T_917 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_918 = cvt(_T_917)
node _T_919 = and(_T_918, asSInt(UInt<27>(0h4000000)))
node _T_920 = asSInt(_T_919)
node _T_921 = eq(_T_920, asSInt(UInt<1>(0h0)))
node _T_922 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_923 = cvt(_T_922)
node _T_924 = and(_T_923, asSInt(UInt<13>(0h1000)))
node _T_925 = asSInt(_T_924)
node _T_926 = eq(_T_925, asSInt(UInt<1>(0h0)))
node _T_927 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_928 = cvt(_T_927)
node _T_929 = and(_T_928, asSInt(UInt<29>(0h10000000)))
node _T_930 = asSInt(_T_929)
node _T_931 = eq(_T_930, asSInt(UInt<1>(0h0)))
node _T_932 = or(_T_891, _T_896)
node _T_933 = or(_T_932, _T_901)
node _T_934 = or(_T_933, _T_906)
node _T_935 = or(_T_934, _T_911)
node _T_936 = or(_T_935, _T_916)
node _T_937 = or(_T_936, _T_921)
node _T_938 = or(_T_937, _T_926)
node _T_939 = or(_T_938, _T_931)
node _T_940 = and(_T_886, _T_939)
node _T_941 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_942 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_943 = cvt(_T_942)
node _T_944 = and(_T_943, asSInt(UInt<17>(0h10000)))
node _T_945 = asSInt(_T_944)
node _T_946 = eq(_T_945, asSInt(UInt<1>(0h0)))
node _T_947 = and(_T_941, _T_946)
node _T_948 = or(UInt<1>(0h0), _T_940)
node _T_949 = or(_T_948, _T_947)
node _T_950 = and(_T_882, _T_949)
node _T_951 = asUInt(reset)
node _T_952 = eq(_T_951, UInt<1>(0h0))
when _T_952 :
node _T_953 = eq(_T_950, UInt<1>(0h0))
when _T_953 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_950, UInt<1>(0h1), "") : assert_36
node _T_954 = asUInt(reset)
node _T_955 = eq(_T_954, UInt<1>(0h0))
when _T_955 :
node _T_956 = eq(source_ok, UInt<1>(0h0))
when _T_956 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_957 = asUInt(reset)
node _T_958 = eq(_T_957, UInt<1>(0h0))
when _T_958 :
node _T_959 = eq(is_aligned, UInt<1>(0h0))
when _T_959 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_960 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_961 = asUInt(reset)
node _T_962 = eq(_T_961, UInt<1>(0h0))
when _T_962 :
node _T_963 = eq(_T_960, UInt<1>(0h0))
when _T_963 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_960, UInt<1>(0h1), "") : assert_39
node _T_964 = eq(io.in.a.bits.mask, mask)
node _T_965 = asUInt(reset)
node _T_966 = eq(_T_965, UInt<1>(0h0))
when _T_966 :
node _T_967 = eq(_T_964, UInt<1>(0h0))
when _T_967 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_964, UInt<1>(0h1), "") : assert_40
node _T_968 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_968 :
node _T_969 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_970 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_971 = and(_T_969, _T_970)
node _T_972 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_973 = shr(io.in.a.bits.source, 2)
node _T_974 = eq(_T_973, UInt<1>(0h0))
node _T_975 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_976 = and(_T_974, _T_975)
node _T_977 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_978 = and(_T_976, _T_977)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_979 = shr(io.in.a.bits.source, 2)
node _T_980 = eq(_T_979, UInt<1>(0h1))
node _T_981 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_982 = and(_T_980, _T_981)
node _T_983 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_984 = and(_T_982, _T_983)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_985 = shr(io.in.a.bits.source, 2)
node _T_986 = eq(_T_985, UInt<2>(0h2))
node _T_987 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_988 = and(_T_986, _T_987)
node _T_989 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_990 = and(_T_988, _T_989)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_991 = shr(io.in.a.bits.source, 2)
node _T_992 = eq(_T_991, UInt<2>(0h3))
node _T_993 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_994 = and(_T_992, _T_993)
node _T_995 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_996 = and(_T_994, _T_995)
node _T_997 = or(_T_972, _T_978)
node _T_998 = or(_T_997, _T_984)
node _T_999 = or(_T_998, _T_990)
node _T_1000 = or(_T_999, _T_996)
node _T_1001 = and(_T_971, _T_1000)
node _T_1002 = or(UInt<1>(0h0), _T_1001)
node _T_1003 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1004 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1005 = and(_T_1003, _T_1004)
node _T_1006 = or(UInt<1>(0h0), _T_1005)
node _T_1007 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1008 = cvt(_T_1007)
node _T_1009 = and(_T_1008, asSInt(UInt<14>(0h2000)))
node _T_1010 = asSInt(_T_1009)
node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0)))
node _T_1012 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1013 = cvt(_T_1012)
node _T_1014 = and(_T_1013, asSInt(UInt<13>(0h1000)))
node _T_1015 = asSInt(_T_1014)
node _T_1016 = eq(_T_1015, asSInt(UInt<1>(0h0)))
node _T_1017 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1018 = cvt(_T_1017)
node _T_1019 = and(_T_1018, asSInt(UInt<18>(0h2f000)))
node _T_1020 = asSInt(_T_1019)
node _T_1021 = eq(_T_1020, asSInt(UInt<1>(0h0)))
node _T_1022 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1023 = cvt(_T_1022)
node _T_1024 = and(_T_1023, asSInt(UInt<17>(0h10000)))
node _T_1025 = asSInt(_T_1024)
node _T_1026 = eq(_T_1025, asSInt(UInt<1>(0h0)))
node _T_1027 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1028 = cvt(_T_1027)
node _T_1029 = and(_T_1028, asSInt(UInt<13>(0h1000)))
node _T_1030 = asSInt(_T_1029)
node _T_1031 = eq(_T_1030, asSInt(UInt<1>(0h0)))
node _T_1032 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1033 = cvt(_T_1032)
node _T_1034 = and(_T_1033, asSInt(UInt<17>(0h10000)))
node _T_1035 = asSInt(_T_1034)
node _T_1036 = eq(_T_1035, asSInt(UInt<1>(0h0)))
node _T_1037 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1038 = cvt(_T_1037)
node _T_1039 = and(_T_1038, asSInt(UInt<27>(0h4000000)))
node _T_1040 = asSInt(_T_1039)
node _T_1041 = eq(_T_1040, asSInt(UInt<1>(0h0)))
node _T_1042 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1043 = cvt(_T_1042)
node _T_1044 = and(_T_1043, asSInt(UInt<13>(0h1000)))
node _T_1045 = asSInt(_T_1044)
node _T_1046 = eq(_T_1045, asSInt(UInt<1>(0h0)))
node _T_1047 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1048 = cvt(_T_1047)
node _T_1049 = and(_T_1048, asSInt(UInt<29>(0h10000000)))
node _T_1050 = asSInt(_T_1049)
node _T_1051 = eq(_T_1050, asSInt(UInt<1>(0h0)))
node _T_1052 = or(_T_1011, _T_1016)
node _T_1053 = or(_T_1052, _T_1021)
node _T_1054 = or(_T_1053, _T_1026)
node _T_1055 = or(_T_1054, _T_1031)
node _T_1056 = or(_T_1055, _T_1036)
node _T_1057 = or(_T_1056, _T_1041)
node _T_1058 = or(_T_1057, _T_1046)
node _T_1059 = or(_T_1058, _T_1051)
node _T_1060 = and(_T_1006, _T_1059)
node _T_1061 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1062 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1063 = cvt(_T_1062)
node _T_1064 = and(_T_1063, asSInt(UInt<17>(0h10000)))
node _T_1065 = asSInt(_T_1064)
node _T_1066 = eq(_T_1065, asSInt(UInt<1>(0h0)))
node _T_1067 = and(_T_1061, _T_1066)
node _T_1068 = or(UInt<1>(0h0), _T_1060)
node _T_1069 = or(_T_1068, _T_1067)
node _T_1070 = and(_T_1002, _T_1069)
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_41
node _T_1074 = asUInt(reset)
node _T_1075 = eq(_T_1074, UInt<1>(0h0))
when _T_1075 :
node _T_1076 = eq(source_ok, UInt<1>(0h0))
when _T_1076 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1077 = asUInt(reset)
node _T_1078 = eq(_T_1077, UInt<1>(0h0))
when _T_1078 :
node _T_1079 = eq(is_aligned, UInt<1>(0h0))
when _T_1079 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1080 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1081 = asUInt(reset)
node _T_1082 = eq(_T_1081, UInt<1>(0h0))
when _T_1082 :
node _T_1083 = eq(_T_1080, UInt<1>(0h0))
when _T_1083 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1080, UInt<1>(0h1), "") : assert_44
node _T_1084 = eq(io.in.a.bits.mask, mask)
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(_T_1084, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1084, UInt<1>(0h1), "") : assert_45
node _T_1088 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1088 :
node _T_1089 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1090 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1091 = and(_T_1089, _T_1090)
node _T_1092 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_1093 = shr(io.in.a.bits.source, 2)
node _T_1094 = eq(_T_1093, UInt<1>(0h0))
node _T_1095 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_1096 = and(_T_1094, _T_1095)
node _T_1097 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_1098 = and(_T_1096, _T_1097)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_1099 = shr(io.in.a.bits.source, 2)
node _T_1100 = eq(_T_1099, UInt<1>(0h1))
node _T_1101 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_1102 = and(_T_1100, _T_1101)
node _T_1103 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_1104 = and(_T_1102, _T_1103)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_1105 = shr(io.in.a.bits.source, 2)
node _T_1106 = eq(_T_1105, UInt<2>(0h2))
node _T_1107 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_1108 = and(_T_1106, _T_1107)
node _T_1109 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_1110 = and(_T_1108, _T_1109)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_1111 = shr(io.in.a.bits.source, 2)
node _T_1112 = eq(_T_1111, UInt<2>(0h3))
node _T_1113 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_1114 = and(_T_1112, _T_1113)
node _T_1115 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_1116 = and(_T_1114, _T_1115)
node _T_1117 = or(_T_1092, _T_1098)
node _T_1118 = or(_T_1117, _T_1104)
node _T_1119 = or(_T_1118, _T_1110)
node _T_1120 = or(_T_1119, _T_1116)
node _T_1121 = and(_T_1091, _T_1120)
node _T_1122 = or(UInt<1>(0h0), _T_1121)
node _T_1123 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1124 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1125 = and(_T_1123, _T_1124)
node _T_1126 = or(UInt<1>(0h0), _T_1125)
node _T_1127 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1128 = cvt(_T_1127)
node _T_1129 = and(_T_1128, asSInt(UInt<13>(0h1000)))
node _T_1130 = asSInt(_T_1129)
node _T_1131 = eq(_T_1130, asSInt(UInt<1>(0h0)))
node _T_1132 = and(_T_1126, _T_1131)
node _T_1133 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1134 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1135 = cvt(_T_1134)
node _T_1136 = and(_T_1135, asSInt(UInt<14>(0h2000)))
node _T_1137 = asSInt(_T_1136)
node _T_1138 = eq(_T_1137, asSInt(UInt<1>(0h0)))
node _T_1139 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1140 = cvt(_T_1139)
node _T_1141 = and(_T_1140, asSInt(UInt<17>(0h10000)))
node _T_1142 = asSInt(_T_1141)
node _T_1143 = eq(_T_1142, asSInt(UInt<1>(0h0)))
node _T_1144 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1145 = cvt(_T_1144)
node _T_1146 = and(_T_1145, asSInt(UInt<18>(0h2f000)))
node _T_1147 = asSInt(_T_1146)
node _T_1148 = eq(_T_1147, asSInt(UInt<1>(0h0)))
node _T_1149 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1150 = cvt(_T_1149)
node _T_1151 = and(_T_1150, asSInt(UInt<17>(0h10000)))
node _T_1152 = asSInt(_T_1151)
node _T_1153 = eq(_T_1152, asSInt(UInt<1>(0h0)))
node _T_1154 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1155 = cvt(_T_1154)
node _T_1156 = and(_T_1155, asSInt(UInt<13>(0h1000)))
node _T_1157 = asSInt(_T_1156)
node _T_1158 = eq(_T_1157, asSInt(UInt<1>(0h0)))
node _T_1159 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1160 = cvt(_T_1159)
node _T_1161 = and(_T_1160, asSInt(UInt<27>(0h4000000)))
node _T_1162 = asSInt(_T_1161)
node _T_1163 = eq(_T_1162, asSInt(UInt<1>(0h0)))
node _T_1164 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1165 = cvt(_T_1164)
node _T_1166 = and(_T_1165, asSInt(UInt<13>(0h1000)))
node _T_1167 = asSInt(_T_1166)
node _T_1168 = eq(_T_1167, asSInt(UInt<1>(0h0)))
node _T_1169 = or(_T_1138, _T_1143)
node _T_1170 = or(_T_1169, _T_1148)
node _T_1171 = or(_T_1170, _T_1153)
node _T_1172 = or(_T_1171, _T_1158)
node _T_1173 = or(_T_1172, _T_1163)
node _T_1174 = or(_T_1173, _T_1168)
node _T_1175 = and(_T_1133, _T_1174)
node _T_1176 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1177 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1178 = and(_T_1176, _T_1177)
node _T_1179 = or(UInt<1>(0h0), _T_1178)
node _T_1180 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1181 = cvt(_T_1180)
node _T_1182 = and(_T_1181, asSInt(UInt<17>(0h10000)))
node _T_1183 = asSInt(_T_1182)
node _T_1184 = eq(_T_1183, asSInt(UInt<1>(0h0)))
node _T_1185 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1186 = cvt(_T_1185)
node _T_1187 = and(_T_1186, asSInt(UInt<29>(0h10000000)))
node _T_1188 = asSInt(_T_1187)
node _T_1189 = eq(_T_1188, asSInt(UInt<1>(0h0)))
node _T_1190 = or(_T_1184, _T_1189)
node _T_1191 = and(_T_1179, _T_1190)
node _T_1192 = or(UInt<1>(0h0), _T_1132)
node _T_1193 = or(_T_1192, _T_1175)
node _T_1194 = or(_T_1193, _T_1191)
node _T_1195 = and(_T_1122, _T_1194)
node _T_1196 = asUInt(reset)
node _T_1197 = eq(_T_1196, UInt<1>(0h0))
when _T_1197 :
node _T_1198 = eq(_T_1195, UInt<1>(0h0))
when _T_1198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1195, UInt<1>(0h1), "") : assert_46
node _T_1199 = asUInt(reset)
node _T_1200 = eq(_T_1199, UInt<1>(0h0))
when _T_1200 :
node _T_1201 = eq(source_ok, UInt<1>(0h0))
when _T_1201 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1202 = asUInt(reset)
node _T_1203 = eq(_T_1202, UInt<1>(0h0))
when _T_1203 :
node _T_1204 = eq(is_aligned, UInt<1>(0h0))
when _T_1204 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1205 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1206 = asUInt(reset)
node _T_1207 = eq(_T_1206, UInt<1>(0h0))
when _T_1207 :
node _T_1208 = eq(_T_1205, UInt<1>(0h0))
when _T_1208 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1205, UInt<1>(0h1), "") : assert_49
node _T_1209 = eq(io.in.a.bits.mask, mask)
node _T_1210 = asUInt(reset)
node _T_1211 = eq(_T_1210, UInt<1>(0h0))
when _T_1211 :
node _T_1212 = eq(_T_1209, UInt<1>(0h0))
when _T_1212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1209, UInt<1>(0h1), "") : assert_50
node _T_1213 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1214 = asUInt(reset)
node _T_1215 = eq(_T_1214, UInt<1>(0h0))
when _T_1215 :
node _T_1216 = eq(_T_1213, UInt<1>(0h0))
when _T_1216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1213, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1217 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1218 = asUInt(reset)
node _T_1219 = eq(_T_1218, UInt<1>(0h0))
when _T_1219 :
node _T_1220 = eq(_T_1217, UInt<1>(0h0))
when _T_1220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1217, UInt<1>(0h1), "") : assert_52
node _source_ok_T_28 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_29 = shr(io.in.d.bits.source, 2)
node _source_ok_T_30 = eq(_source_ok_T_29, UInt<1>(0h0))
node _source_ok_T_31 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_32 = and(_source_ok_T_30, _source_ok_T_31)
node _source_ok_T_33 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_35 = shr(io.in.d.bits.source, 2)
node _source_ok_T_36 = eq(_source_ok_T_35, UInt<1>(0h1))
node _source_ok_T_37 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37)
node _source_ok_T_39 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_41 = shr(io.in.d.bits.source, 2)
node _source_ok_T_42 = eq(_source_ok_T_41, UInt<2>(0h2))
node _source_ok_T_43 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43)
node _source_ok_T_45 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_47 = shr(io.in.d.bits.source, 2)
node _source_ok_T_48 = eq(_source_ok_T_47, UInt<2>(0h3))
node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49)
node _source_ok_T_51 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51)
wire _source_ok_WIRE_1 : UInt<1>[5]
connect _source_ok_WIRE_1[0], _source_ok_T_28
connect _source_ok_WIRE_1[1], _source_ok_T_34
connect _source_ok_WIRE_1[2], _source_ok_T_40
connect _source_ok_WIRE_1[3], _source_ok_T_46
connect _source_ok_WIRE_1[4], _source_ok_T_52
node _source_ok_T_53 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE_1[2])
node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE_1[3])
node source_ok_1 = or(_source_ok_T_55, _source_ok_WIRE_1[4])
node sink_ok = lt(io.in.d.bits.sink, UInt<6>(0h20))
node _T_1221 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1221 :
node _T_1222 = asUInt(reset)
node _T_1223 = eq(_T_1222, UInt<1>(0h0))
when _T_1223 :
node _T_1224 = eq(source_ok_1, UInt<1>(0h0))
when _T_1224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1225 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1226 = asUInt(reset)
node _T_1227 = eq(_T_1226, UInt<1>(0h0))
when _T_1227 :
node _T_1228 = eq(_T_1225, UInt<1>(0h0))
when _T_1228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1225, UInt<1>(0h1), "") : assert_54
node _T_1229 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1230 = asUInt(reset)
node _T_1231 = eq(_T_1230, UInt<1>(0h0))
when _T_1231 :
node _T_1232 = eq(_T_1229, UInt<1>(0h0))
when _T_1232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1229, UInt<1>(0h1), "") : assert_55
node _T_1233 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1234 = asUInt(reset)
node _T_1235 = eq(_T_1234, UInt<1>(0h0))
when _T_1235 :
node _T_1236 = eq(_T_1233, UInt<1>(0h0))
when _T_1236 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1233, UInt<1>(0h1), "") : assert_56
node _T_1237 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1238 = asUInt(reset)
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
when _T_1239 :
node _T_1240 = eq(_T_1237, UInt<1>(0h0))
when _T_1240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1237, UInt<1>(0h1), "") : assert_57
node _T_1241 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1241 :
node _T_1242 = asUInt(reset)
node _T_1243 = eq(_T_1242, UInt<1>(0h0))
when _T_1243 :
node _T_1244 = eq(source_ok_1, UInt<1>(0h0))
when _T_1244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1245 = asUInt(reset)
node _T_1246 = eq(_T_1245, UInt<1>(0h0))
when _T_1246 :
node _T_1247 = eq(sink_ok, UInt<1>(0h0))
when _T_1247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1248 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1249 = asUInt(reset)
node _T_1250 = eq(_T_1249, UInt<1>(0h0))
when _T_1250 :
node _T_1251 = eq(_T_1248, UInt<1>(0h0))
when _T_1251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1248, UInt<1>(0h1), "") : assert_60
node _T_1252 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1253 = asUInt(reset)
node _T_1254 = eq(_T_1253, UInt<1>(0h0))
when _T_1254 :
node _T_1255 = eq(_T_1252, UInt<1>(0h0))
when _T_1255 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1252, UInt<1>(0h1), "") : assert_61
node _T_1256 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1257 = asUInt(reset)
node _T_1258 = eq(_T_1257, UInt<1>(0h0))
when _T_1258 :
node _T_1259 = eq(_T_1256, UInt<1>(0h0))
when _T_1259 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1256, UInt<1>(0h1), "") : assert_62
node _T_1260 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1261 = asUInt(reset)
node _T_1262 = eq(_T_1261, UInt<1>(0h0))
when _T_1262 :
node _T_1263 = eq(_T_1260, UInt<1>(0h0))
when _T_1263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1260, UInt<1>(0h1), "") : assert_63
node _T_1264 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1265 = or(UInt<1>(0h1), _T_1264)
node _T_1266 = asUInt(reset)
node _T_1267 = eq(_T_1266, UInt<1>(0h0))
when _T_1267 :
node _T_1268 = eq(_T_1265, UInt<1>(0h0))
when _T_1268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1265, UInt<1>(0h1), "") : assert_64
node _T_1269 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1269 :
node _T_1270 = asUInt(reset)
node _T_1271 = eq(_T_1270, UInt<1>(0h0))
when _T_1271 :
node _T_1272 = eq(source_ok_1, UInt<1>(0h0))
when _T_1272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1273 = asUInt(reset)
node _T_1274 = eq(_T_1273, UInt<1>(0h0))
when _T_1274 :
node _T_1275 = eq(sink_ok, UInt<1>(0h0))
when _T_1275 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1276 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1277 = asUInt(reset)
node _T_1278 = eq(_T_1277, UInt<1>(0h0))
when _T_1278 :
node _T_1279 = eq(_T_1276, UInt<1>(0h0))
when _T_1279 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1276, UInt<1>(0h1), "") : assert_67
node _T_1280 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1281 = asUInt(reset)
node _T_1282 = eq(_T_1281, UInt<1>(0h0))
when _T_1282 :
node _T_1283 = eq(_T_1280, UInt<1>(0h0))
when _T_1283 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1280, UInt<1>(0h1), "") : assert_68
node _T_1284 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1285 = asUInt(reset)
node _T_1286 = eq(_T_1285, UInt<1>(0h0))
when _T_1286 :
node _T_1287 = eq(_T_1284, UInt<1>(0h0))
when _T_1287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1284, UInt<1>(0h1), "") : assert_69
node _T_1288 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1289 = or(_T_1288, io.in.d.bits.corrupt)
node _T_1290 = asUInt(reset)
node _T_1291 = eq(_T_1290, UInt<1>(0h0))
when _T_1291 :
node _T_1292 = eq(_T_1289, UInt<1>(0h0))
when _T_1292 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1289, UInt<1>(0h1), "") : assert_70
node _T_1293 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1294 = or(UInt<1>(0h1), _T_1293)
node _T_1295 = asUInt(reset)
node _T_1296 = eq(_T_1295, UInt<1>(0h0))
when _T_1296 :
node _T_1297 = eq(_T_1294, UInt<1>(0h0))
when _T_1297 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1294, UInt<1>(0h1), "") : assert_71
node _T_1298 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1298 :
node _T_1299 = asUInt(reset)
node _T_1300 = eq(_T_1299, UInt<1>(0h0))
when _T_1300 :
node _T_1301 = eq(source_ok_1, UInt<1>(0h0))
when _T_1301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1302 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1303 = asUInt(reset)
node _T_1304 = eq(_T_1303, UInt<1>(0h0))
when _T_1304 :
node _T_1305 = eq(_T_1302, UInt<1>(0h0))
when _T_1305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1302, UInt<1>(0h1), "") : assert_73
node _T_1306 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1307 = asUInt(reset)
node _T_1308 = eq(_T_1307, UInt<1>(0h0))
when _T_1308 :
node _T_1309 = eq(_T_1306, UInt<1>(0h0))
when _T_1309 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1306, UInt<1>(0h1), "") : assert_74
node _T_1310 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1311 = or(UInt<1>(0h1), _T_1310)
node _T_1312 = asUInt(reset)
node _T_1313 = eq(_T_1312, UInt<1>(0h0))
when _T_1313 :
node _T_1314 = eq(_T_1311, UInt<1>(0h0))
when _T_1314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1311, UInt<1>(0h1), "") : assert_75
node _T_1315 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1315 :
node _T_1316 = asUInt(reset)
node _T_1317 = eq(_T_1316, UInt<1>(0h0))
when _T_1317 :
node _T_1318 = eq(source_ok_1, UInt<1>(0h0))
when _T_1318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1319 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1320 = asUInt(reset)
node _T_1321 = eq(_T_1320, UInt<1>(0h0))
when _T_1321 :
node _T_1322 = eq(_T_1319, UInt<1>(0h0))
when _T_1322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1319, UInt<1>(0h1), "") : assert_77
node _T_1323 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1324 = or(_T_1323, io.in.d.bits.corrupt)
node _T_1325 = asUInt(reset)
node _T_1326 = eq(_T_1325, UInt<1>(0h0))
when _T_1326 :
node _T_1327 = eq(_T_1324, UInt<1>(0h0))
when _T_1327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1324, UInt<1>(0h1), "") : assert_78
node _T_1328 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1329 = or(UInt<1>(0h1), _T_1328)
node _T_1330 = asUInt(reset)
node _T_1331 = eq(_T_1330, UInt<1>(0h0))
when _T_1331 :
node _T_1332 = eq(_T_1329, UInt<1>(0h0))
when _T_1332 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1329, UInt<1>(0h1), "") : assert_79
node _T_1333 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1333 :
node _T_1334 = asUInt(reset)
node _T_1335 = eq(_T_1334, UInt<1>(0h0))
when _T_1335 :
node _T_1336 = eq(source_ok_1, UInt<1>(0h0))
when _T_1336 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1337 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1338 = asUInt(reset)
node _T_1339 = eq(_T_1338, UInt<1>(0h0))
when _T_1339 :
node _T_1340 = eq(_T_1337, UInt<1>(0h0))
when _T_1340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1337, UInt<1>(0h1), "") : assert_81
node _T_1341 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1342 = asUInt(reset)
node _T_1343 = eq(_T_1342, UInt<1>(0h0))
when _T_1343 :
node _T_1344 = eq(_T_1341, UInt<1>(0h0))
when _T_1344 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1341, UInt<1>(0h1), "") : assert_82
node _T_1345 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1346 = or(UInt<1>(0h1), _T_1345)
node _T_1347 = asUInt(reset)
node _T_1348 = eq(_T_1347, UInt<1>(0h0))
when _T_1348 :
node _T_1349 = eq(_T_1346, UInt<1>(0h0))
when _T_1349 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1346, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1350 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1351 = asUInt(reset)
node _T_1352 = eq(_T_1351, UInt<1>(0h0))
when _T_1352 :
node _T_1353 = eq(_T_1350, UInt<1>(0h0))
when _T_1353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1350, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1354 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1355 = asUInt(reset)
node _T_1356 = eq(_T_1355, UInt<1>(0h0))
when _T_1356 :
node _T_1357 = eq(_T_1354, UInt<1>(0h0))
when _T_1357 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1354, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}
connect _WIRE_4.bits.sink, UInt<5>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1358 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1359 = asUInt(reset)
node _T_1360 = eq(_T_1359, UInt<1>(0h0))
when _T_1360 :
node _T_1361 = eq(_T_1358, UInt<1>(0h0))
when _T_1361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1358, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1362 = eq(a_first, UInt<1>(0h0))
node _T_1363 = and(io.in.a.valid, _T_1362)
when _T_1363 :
node _T_1364 = eq(io.in.a.bits.opcode, opcode)
node _T_1365 = asUInt(reset)
node _T_1366 = eq(_T_1365, UInt<1>(0h0))
when _T_1366 :
node _T_1367 = eq(_T_1364, UInt<1>(0h0))
when _T_1367 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1364, UInt<1>(0h1), "") : assert_87
node _T_1368 = eq(io.in.a.bits.param, param)
node _T_1369 = asUInt(reset)
node _T_1370 = eq(_T_1369, UInt<1>(0h0))
when _T_1370 :
node _T_1371 = eq(_T_1368, UInt<1>(0h0))
when _T_1371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1368, UInt<1>(0h1), "") : assert_88
node _T_1372 = eq(io.in.a.bits.size, size)
node _T_1373 = asUInt(reset)
node _T_1374 = eq(_T_1373, UInt<1>(0h0))
when _T_1374 :
node _T_1375 = eq(_T_1372, UInt<1>(0h0))
when _T_1375 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1372, UInt<1>(0h1), "") : assert_89
node _T_1376 = eq(io.in.a.bits.source, source)
node _T_1377 = asUInt(reset)
node _T_1378 = eq(_T_1377, UInt<1>(0h0))
when _T_1378 :
node _T_1379 = eq(_T_1376, UInt<1>(0h0))
when _T_1379 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1376, UInt<1>(0h1), "") : assert_90
node _T_1380 = eq(io.in.a.bits.address, address)
node _T_1381 = asUInt(reset)
node _T_1382 = eq(_T_1381, UInt<1>(0h0))
when _T_1382 :
node _T_1383 = eq(_T_1380, UInt<1>(0h0))
when _T_1383 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1380, UInt<1>(0h1), "") : assert_91
node _T_1384 = and(io.in.a.ready, io.in.a.valid)
node _T_1385 = and(_T_1384, a_first)
when _T_1385 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1386 = eq(d_first, UInt<1>(0h0))
node _T_1387 = and(io.in.d.valid, _T_1386)
when _T_1387 :
node _T_1388 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1389 = asUInt(reset)
node _T_1390 = eq(_T_1389, UInt<1>(0h0))
when _T_1390 :
node _T_1391 = eq(_T_1388, UInt<1>(0h0))
when _T_1391 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1388, UInt<1>(0h1), "") : assert_92
node _T_1392 = eq(io.in.d.bits.param, param_1)
node _T_1393 = asUInt(reset)
node _T_1394 = eq(_T_1393, UInt<1>(0h0))
when _T_1394 :
node _T_1395 = eq(_T_1392, UInt<1>(0h0))
when _T_1395 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1392, UInt<1>(0h1), "") : assert_93
node _T_1396 = eq(io.in.d.bits.size, size_1)
node _T_1397 = asUInt(reset)
node _T_1398 = eq(_T_1397, UInt<1>(0h0))
when _T_1398 :
node _T_1399 = eq(_T_1396, UInt<1>(0h0))
when _T_1399 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1396, UInt<1>(0h1), "") : assert_94
node _T_1400 = eq(io.in.d.bits.source, source_1)
node _T_1401 = asUInt(reset)
node _T_1402 = eq(_T_1401, UInt<1>(0h0))
when _T_1402 :
node _T_1403 = eq(_T_1400, UInt<1>(0h0))
when _T_1403 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1400, UInt<1>(0h1), "") : assert_95
node _T_1404 = eq(io.in.d.bits.sink, sink)
node _T_1405 = asUInt(reset)
node _T_1406 = eq(_T_1405, UInt<1>(0h0))
when _T_1406 :
node _T_1407 = eq(_T_1404, UInt<1>(0h0))
when _T_1407 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1404, UInt<1>(0h1), "") : assert_96
node _T_1408 = eq(io.in.d.bits.denied, denied)
node _T_1409 = asUInt(reset)
node _T_1410 = eq(_T_1409, UInt<1>(0h0))
when _T_1410 :
node _T_1411 = eq(_T_1408, UInt<1>(0h0))
when _T_1411 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1408, UInt<1>(0h1), "") : assert_97
node _T_1412 = and(io.in.d.ready, io.in.d.valid)
node _T_1413 = and(_T_1412, d_first)
when _T_1413 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<17>, clock, reset, UInt<17>(0h0)
regreset inflight_opcodes : UInt<68>, clock, reset, UInt<68>(0h0)
regreset inflight_sizes : UInt<136>, clock, reset, UInt<136>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<17>
connect a_set, UInt<17>(0h0)
wire a_set_wo_ready : UInt<17>
connect a_set_wo_ready, UInt<17>(0h0)
wire a_opcodes_set : UInt<68>
connect a_opcodes_set, UInt<68>(0h0)
wire a_sizes_set : UInt<136>
connect a_sizes_set, UInt<136>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1414 = and(io.in.a.valid, a_first_1)
node _T_1415 = and(_T_1414, UInt<1>(0h1))
when _T_1415 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1416 = and(io.in.a.ready, io.in.a.valid)
node _T_1417 = and(_T_1416, a_first_1)
node _T_1418 = and(_T_1417, UInt<1>(0h1))
when _T_1418 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1419 = dshr(inflight, io.in.a.bits.source)
node _T_1420 = bits(_T_1419, 0, 0)
node _T_1421 = eq(_T_1420, UInt<1>(0h0))
node _T_1422 = asUInt(reset)
node _T_1423 = eq(_T_1422, UInt<1>(0h0))
when _T_1423 :
node _T_1424 = eq(_T_1421, UInt<1>(0h0))
when _T_1424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1421, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<17>
connect d_clr, UInt<17>(0h0)
wire d_clr_wo_ready : UInt<17>
connect d_clr_wo_ready, UInt<17>(0h0)
wire d_opcodes_clr : UInt<68>
connect d_opcodes_clr, UInt<68>(0h0)
wire d_sizes_clr : UInt<136>
connect d_sizes_clr, UInt<136>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1425 = and(io.in.d.valid, d_first_1)
node _T_1426 = and(_T_1425, UInt<1>(0h1))
node _T_1427 = eq(d_release_ack, UInt<1>(0h0))
node _T_1428 = and(_T_1426, _T_1427)
when _T_1428 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1429 = and(io.in.d.ready, io.in.d.valid)
node _T_1430 = and(_T_1429, d_first_1)
node _T_1431 = and(_T_1430, UInt<1>(0h1))
node _T_1432 = eq(d_release_ack, UInt<1>(0h0))
node _T_1433 = and(_T_1431, _T_1432)
when _T_1433 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1434 = and(io.in.d.valid, d_first_1)
node _T_1435 = and(_T_1434, UInt<1>(0h1))
node _T_1436 = eq(d_release_ack, UInt<1>(0h0))
node _T_1437 = and(_T_1435, _T_1436)
when _T_1437 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1438 = dshr(inflight, io.in.d.bits.source)
node _T_1439 = bits(_T_1438, 0, 0)
node _T_1440 = or(_T_1439, same_cycle_resp)
node _T_1441 = asUInt(reset)
node _T_1442 = eq(_T_1441, UInt<1>(0h0))
when _T_1442 :
node _T_1443 = eq(_T_1440, UInt<1>(0h0))
when _T_1443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1440, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1444 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1445 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1446 = or(_T_1444, _T_1445)
node _T_1447 = asUInt(reset)
node _T_1448 = eq(_T_1447, UInt<1>(0h0))
when _T_1448 :
node _T_1449 = eq(_T_1446, UInt<1>(0h0))
when _T_1449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1446, UInt<1>(0h1), "") : assert_100
node _T_1450 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1451 = asUInt(reset)
node _T_1452 = eq(_T_1451, UInt<1>(0h0))
when _T_1452 :
node _T_1453 = eq(_T_1450, UInt<1>(0h0))
when _T_1453 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1450, UInt<1>(0h1), "") : assert_101
else :
node _T_1454 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1455 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1456 = or(_T_1454, _T_1455)
node _T_1457 = asUInt(reset)
node _T_1458 = eq(_T_1457, UInt<1>(0h0))
when _T_1458 :
node _T_1459 = eq(_T_1456, UInt<1>(0h0))
when _T_1459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1456, UInt<1>(0h1), "") : assert_102
node _T_1460 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1461 = asUInt(reset)
node _T_1462 = eq(_T_1461, UInt<1>(0h0))
when _T_1462 :
node _T_1463 = eq(_T_1460, UInt<1>(0h0))
when _T_1463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1460, UInt<1>(0h1), "") : assert_103
node _T_1464 = and(io.in.d.valid, d_first_1)
node _T_1465 = and(_T_1464, a_first_1)
node _T_1466 = and(_T_1465, io.in.a.valid)
node _T_1467 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1468 = and(_T_1466, _T_1467)
node _T_1469 = eq(d_release_ack, UInt<1>(0h0))
node _T_1470 = and(_T_1468, _T_1469)
when _T_1470 :
node _T_1471 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1472 = or(_T_1471, io.in.a.ready)
node _T_1473 = asUInt(reset)
node _T_1474 = eq(_T_1473, UInt<1>(0h0))
when _T_1474 :
node _T_1475 = eq(_T_1472, UInt<1>(0h0))
when _T_1475 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1472, UInt<1>(0h1), "") : assert_104
node _T_1476 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1477 = orr(a_set_wo_ready)
node _T_1478 = eq(_T_1477, UInt<1>(0h0))
node _T_1479 = or(_T_1476, _T_1478)
node _T_1480 = asUInt(reset)
node _T_1481 = eq(_T_1480, UInt<1>(0h0))
when _T_1481 :
node _T_1482 = eq(_T_1479, UInt<1>(0h0))
when _T_1482 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1479, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_37
node _T_1483 = orr(inflight)
node _T_1484 = eq(_T_1483, UInt<1>(0h0))
node _T_1485 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1486 = or(_T_1484, _T_1485)
node _T_1487 = lt(watchdog, plusarg_reader.out)
node _T_1488 = or(_T_1486, _T_1487)
node _T_1489 = asUInt(reset)
node _T_1490 = eq(_T_1489, UInt<1>(0h0))
when _T_1490 :
node _T_1491 = eq(_T_1488, UInt<1>(0h0))
when _T_1491 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1488, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1492 = and(io.in.a.ready, io.in.a.valid)
node _T_1493 = and(io.in.d.ready, io.in.d.valid)
node _T_1494 = or(_T_1492, _T_1493)
when _T_1494 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<17>, clock, reset, UInt<17>(0h0)
regreset inflight_opcodes_1 : UInt<68>, clock, reset, UInt<68>(0h0)
regreset inflight_sizes_1 : UInt<136>, clock, reset, UInt<136>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<5>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<17>
connect c_set, UInt<17>(0h0)
wire c_set_wo_ready : UInt<17>
connect c_set_wo_ready, UInt<17>(0h0)
wire c_opcodes_set : UInt<68>
connect c_opcodes_set, UInt<68>(0h0)
wire c_sizes_set : UInt<136>
connect c_sizes_set, UInt<136>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1495 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1496 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1497 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1498 = and(_T_1496, _T_1497)
node _T_1499 = and(_T_1495, _T_1498)
when _T_1499 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<5>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1500 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1501 = and(_T_1500, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<5>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1502 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1503 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1504 = and(_T_1502, _T_1503)
node _T_1505 = and(_T_1501, _T_1504)
when _T_1505 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<5>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1506 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1507 = bits(_T_1506, 0, 0)
node _T_1508 = eq(_T_1507, UInt<1>(0h0))
node _T_1509 = asUInt(reset)
node _T_1510 = eq(_T_1509, UInt<1>(0h0))
when _T_1510 :
node _T_1511 = eq(_T_1508, UInt<1>(0h0))
when _T_1511 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1508, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<17>
connect d_clr_1, UInt<17>(0h0)
wire d_clr_wo_ready_1 : UInt<17>
connect d_clr_wo_ready_1, UInt<17>(0h0)
wire d_opcodes_clr_1 : UInt<68>
connect d_opcodes_clr_1, UInt<68>(0h0)
wire d_sizes_clr_1 : UInt<136>
connect d_sizes_clr_1, UInt<136>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1512 = and(io.in.d.valid, d_first_2)
node _T_1513 = and(_T_1512, UInt<1>(0h1))
node _T_1514 = and(_T_1513, d_release_ack_1)
when _T_1514 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1515 = and(io.in.d.ready, io.in.d.valid)
node _T_1516 = and(_T_1515, d_first_2)
node _T_1517 = and(_T_1516, UInt<1>(0h1))
node _T_1518 = and(_T_1517, d_release_ack_1)
when _T_1518 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1519 = and(io.in.d.valid, d_first_2)
node _T_1520 = and(_T_1519, UInt<1>(0h1))
node _T_1521 = and(_T_1520, d_release_ack_1)
when _T_1521 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1522 = dshr(inflight_1, io.in.d.bits.source)
node _T_1523 = bits(_T_1522, 0, 0)
node _T_1524 = or(_T_1523, same_cycle_resp_1)
node _T_1525 = asUInt(reset)
node _T_1526 = eq(_T_1525, UInt<1>(0h0))
when _T_1526 :
node _T_1527 = eq(_T_1524, UInt<1>(0h0))
when _T_1527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1524, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<5>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1528 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1529 = asUInt(reset)
node _T_1530 = eq(_T_1529, UInt<1>(0h0))
when _T_1530 :
node _T_1531 = eq(_T_1528, UInt<1>(0h0))
when _T_1531 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1528, UInt<1>(0h1), "") : assert_109
else :
node _T_1532 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1533 = asUInt(reset)
node _T_1534 = eq(_T_1533, UInt<1>(0h0))
when _T_1534 :
node _T_1535 = eq(_T_1532, UInt<1>(0h0))
when _T_1535 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1532, UInt<1>(0h1), "") : assert_110
node _T_1536 = and(io.in.d.valid, d_first_2)
node _T_1537 = and(_T_1536, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<5>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1538 = and(_T_1537, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<5>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1539 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1540 = and(_T_1538, _T_1539)
node _T_1541 = and(_T_1540, d_release_ack_1)
node _T_1542 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1543 = and(_T_1541, _T_1542)
when _T_1543 :
node _T_1544 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<5>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1545 = or(_T_1544, _WIRE_23.ready)
node _T_1546 = asUInt(reset)
node _T_1547 = eq(_T_1546, UInt<1>(0h0))
when _T_1547 :
node _T_1548 = eq(_T_1545, UInt<1>(0h0))
when _T_1548 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1545, UInt<1>(0h1), "") : assert_111
node _T_1549 = orr(c_set_wo_ready)
when _T_1549 :
node _T_1550 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1551 = asUInt(reset)
node _T_1552 = eq(_T_1551, UInt<1>(0h0))
when _T_1552 :
node _T_1553 = eq(_T_1550, UInt<1>(0h0))
when _T_1553 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1550, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_38
node _T_1554 = orr(inflight_1)
node _T_1555 = eq(_T_1554, UInt<1>(0h0))
node _T_1556 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1557 = or(_T_1555, _T_1556)
node _T_1558 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1559 = or(_T_1557, _T_1558)
node _T_1560 = asUInt(reset)
node _T_1561 = eq(_T_1560, UInt<1>(0h0))
when _T_1561 :
node _T_1562 = eq(_T_1559, UInt<1>(0h0))
when _T_1562 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1559, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<5>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1563 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1564 = and(io.in.d.ready, io.in.d.valid)
node _T_1565 = or(_T_1563, _T_1564)
when _T_1565 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_14( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg [4:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [16:0] inflight; // @[Monitor.scala:614:27]
reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [135:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire [31:0] _GEN_0 = {27'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [31:0] _GEN_3 = {27'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [16:0] inflight_1; // @[Monitor.scala:726:35]
reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_20 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node adjustedSig = shl(io.in.sig, 0)
node doShiftSigDown1 = bits(adjustedSig, 26, 26)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _roundMask_T = bits(io.in.sExp, 8, 0)
node _roundMask_T_1 = not(_roundMask_T)
node roundMask_msb = bits(_roundMask_T_1, 8, 8)
node roundMask_lsbs = bits(_roundMask_T_1, 7, 0)
node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7)
node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0)
node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2)
node _roundMask_T_2 = bits(roundMask_shift, 63, 42)
node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0)
node _roundMask_T_4 = shl(UInt<8>(0hff), 8)
node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4)
node _roundMask_T_6 = shr(_roundMask_T_3, 8)
node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5)
node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0)
node _roundMask_T_9 = shl(_roundMask_T_8, 8)
node _roundMask_T_10 = not(_roundMask_T_5)
node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10)
node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11)
node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0)
node _roundMask_T_14 = shl(_roundMask_T_13, 4)
node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14)
node _roundMask_T_16 = shr(_roundMask_T_12, 4)
node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15)
node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0)
node _roundMask_T_19 = shl(_roundMask_T_18, 4)
node _roundMask_T_20 = not(_roundMask_T_15)
node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20)
node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21)
node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0)
node _roundMask_T_24 = shl(_roundMask_T_23, 2)
node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24)
node _roundMask_T_26 = shr(_roundMask_T_22, 2)
node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25)
node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0)
node _roundMask_T_29 = shl(_roundMask_T_28, 2)
node _roundMask_T_30 = not(_roundMask_T_25)
node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30)
node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31)
node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0)
node _roundMask_T_34 = shl(_roundMask_T_33, 1)
node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34)
node _roundMask_T_36 = shr(_roundMask_T_32, 1)
node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35)
node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0)
node _roundMask_T_39 = shl(_roundMask_T_38, 1)
node _roundMask_T_40 = not(_roundMask_T_35)
node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40)
node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41)
node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16)
node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0)
node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0)
node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0)
node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1)
node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47)
node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2)
node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0)
node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1)
node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51)
node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52)
node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4)
node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0)
node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1)
node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56)
node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57)
node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58)
node _roundMask_T_60 = not(_roundMask_T_59)
node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60)
node _roundMask_T_62 = not(_roundMask_T_61)
node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7))
node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3)
node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0)
node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0)
node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0)
node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1)
node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67)
node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2)
node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69)
node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0))
node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71)
node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0))
node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1)
node roundMask = cat(_roundMask_T_74, UInt<2>(0h3))
node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask)
node shiftedRoundMask = shr(_shiftedRoundMask_T, 1)
node _roundPosMask_T = not(shiftedRoundMask)
node roundPosMask = and(_roundPosMask_T, roundMask)
node _roundPosBit_T = and(adjustedSig, roundPosMask)
node roundPosBit = orr(_roundPosBit_T)
node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask)
node anyRoundExtra = orr(_anyRoundExtra_T)
node anyRound = or(roundPosBit, anyRoundExtra)
node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit)
node _roundIncr_T_2 = and(roundMagUp, anyRound)
node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2)
node _roundedSig_T = or(adjustedSig, roundMask)
node _roundedSig_T_1 = shr(_roundedSig_T, 2)
node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1))
node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit)
node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0))
node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4)
node _roundedSig_T_6 = shr(roundMask, 1)
node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0))
node _roundedSig_T_8 = not(_roundedSig_T_7)
node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8)
node _roundedSig_T_10 = not(roundMask)
node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10)
node _roundedSig_T_12 = shr(_roundedSig_T_11, 2)
node _roundedSig_T_13 = and(roundingMode_odd, anyRound)
node _roundedSig_T_14 = shr(roundPosMask, 1)
node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0))
node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15)
node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16)
node _sRoundedExp_T = shr(roundedSig, 24)
node _sRoundedExp_T_1 = cvt(_sRoundedExp_T)
node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1)
node _common_expOut_T = bits(sRoundedExp, 8, 0)
connect common_expOut, _common_expOut_T
node _common_fractOut_T = bits(roundedSig, 23, 1)
node _common_fractOut_T_1 = bits(roundedSig, 22, 0)
node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
node _common_overflow_T = shr(sRoundedExp, 7)
node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3)))
connect common_overflow, _common_overflow_T_1
node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b)))
connect common_totalUnderflow, _common_totalUnderflow_T
node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2)
node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1)
node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1)
node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2)
node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T)
node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0)
node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2)
node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3)
node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit)
node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound)
node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2)
node _roundCarry_T = bits(roundedSig, 25, 25)
node _roundCarry_T_1 = bits(roundedSig, 24, 24)
node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1)
node _common_underflow_T = shr(io.in.sExp, 8)
node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0)))
node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1)
node _common_underflow_T_3 = bits(roundMask, 3, 3)
node _common_underflow_T_4 = bits(roundMask, 2, 2)
node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4)
node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5)
node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1))
node _common_underflow_T_8 = bits(roundMask, 4, 4)
node _common_underflow_T_9 = bits(roundMask, 3, 3)
node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9)
node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0))
node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11)
node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry)
node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit)
node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr)
node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0))
node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16)
node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17)
connect common_underflow, _common_underflow_T_18
node _common_inexact_T = or(common_totalUnderflow, anyRound)
connect common_inexact, _common_inexact_T
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_20( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_detectTininess, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_detectTininess_0 = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire _common_underflow_T_7 = io_detectTininess_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :222:49]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53]
wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53]
wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53]
wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53]
wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53]
wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53]
wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}]
wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}]
wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25]
wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26]
wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56]
wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22]
wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22]
wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20]
wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20]
wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20]
wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20]
wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20]
wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20]
wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}]
wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}]
wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17]
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56]
wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22]
wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20]
wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20]
wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20]
wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58]
wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24]
wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24]
wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38]
wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38]
assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38]
assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38]
wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32]
assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32]
wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}]
wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29]
wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29]
wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42]
wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [25:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}]
wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24]
wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}]
wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29]
wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_7 & _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:{49,77}, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60]
wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}]
wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42]
wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}]
wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_5 = pegMinNonzeroMagOut ? 9'h194 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18]
wire [8:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}]
wire [8:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14]
wire [8:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 7'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18]
wire [8:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}]
wire [8:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14]
wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [8:0] _expOut_T_14 = pegMinNonzeroMagOut ? 9'h6B : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16]
wire [8:0] _expOut_T_15 = _expOut_T_13 | _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16]
wire [8:0] _expOut_T_16 = pegMaxFiniteMagOut ? 9'h17F : 9'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16]
wire [8:0] _expOut_T_17 = _expOut_T_15 | _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16]
wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [22:0] _fractOut_T_4 = {23{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13]
wire [22:0] fractOut = _fractOut_T_3 | _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_129 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_221
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_129( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_221 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_256 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_256( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module Switch_1 :
input clock : Clock
input reset : Reset
output io : { in : { flip `4` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], flip `3` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], flip `2` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], flip `1` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], flip `0` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1]}, out : { `3` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], `2` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], `1` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], `0` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1]}, sel : { `3` : { flip `4` : UInt<1>[1], flip `3` : UInt<1>[1], flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1], `2` : { flip `4` : UInt<1>[1], flip `3` : UInt<1>[1], flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1], `1` : { flip `4` : UInt<1>[1], flip `3` : UInt<1>[1], flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1], `0` : { flip `4` : UInt<1>[1], flip `3` : UInt<1>[1], flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1]}}
wire in_flat : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[5]
connect in_flat[0], io.in.`0`[0]
connect in_flat[1], io.in.`1`[0]
connect in_flat[2], io.in.`2`[0]
connect in_flat[3], io.in.`3`[0]
connect in_flat[4], io.in.`4`[0]
node sel_flat_lo = cat(io.sel.`0`[0].`1`[0], io.sel.`0`[0].`0`[0])
node sel_flat_hi_hi = cat(io.sel.`0`[0].`4`[0], io.sel.`0`[0].`3`[0])
node sel_flat_hi = cat(sel_flat_hi_hi, io.sel.`0`[0].`2`[0])
node sel_flat = cat(sel_flat_hi, sel_flat_lo)
node _T = bits(sel_flat, 0, 0)
node _T_1 = bits(sel_flat, 1, 1)
node _T_2 = bits(sel_flat, 2, 2)
node _T_3 = bits(sel_flat, 3, 3)
node _T_4 = bits(sel_flat, 4, 4)
node _T_5 = add(_T, _T_1)
node _T_6 = bits(_T_5, 1, 0)
node _T_7 = add(_T_3, _T_4)
node _T_8 = bits(_T_7, 1, 0)
node _T_9 = add(_T_2, _T_8)
node _T_10 = bits(_T_9, 1, 0)
node _T_11 = add(_T_6, _T_10)
node _T_12 = bits(_T_11, 2, 0)
node _T_13 = leq(_T_12, UInt<1>(0h1))
node _T_14 = asUInt(reset)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
node _T_16 = eq(_T_13, UInt<1>(0h0))
when _T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf
assert(clock, _T_13, UInt<1>(0h1), "") : assert
node _io_out_0_0_valid_T = bits(sel_flat, 0, 0)
node _io_out_0_0_valid_T_1 = bits(sel_flat, 1, 1)
node _io_out_0_0_valid_T_2 = bits(sel_flat, 2, 2)
node _io_out_0_0_valid_T_3 = bits(sel_flat, 3, 3)
node _io_out_0_0_valid_T_4 = bits(sel_flat, 4, 4)
node _io_out_0_0_valid_T_5 = mux(_io_out_0_0_valid_T, in_flat[0].valid, UInt<1>(0h0))
node _io_out_0_0_valid_T_6 = mux(_io_out_0_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0))
node _io_out_0_0_valid_T_7 = mux(_io_out_0_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0))
node _io_out_0_0_valid_T_8 = mux(_io_out_0_0_valid_T_3, in_flat[3].valid, UInt<1>(0h0))
node _io_out_0_0_valid_T_9 = mux(_io_out_0_0_valid_T_4, in_flat[4].valid, UInt<1>(0h0))
node _io_out_0_0_valid_T_10 = or(_io_out_0_0_valid_T_5, _io_out_0_0_valid_T_6)
node _io_out_0_0_valid_T_11 = or(_io_out_0_0_valid_T_10, _io_out_0_0_valid_T_7)
node _io_out_0_0_valid_T_12 = or(_io_out_0_0_valid_T_11, _io_out_0_0_valid_T_8)
node _io_out_0_0_valid_T_13 = or(_io_out_0_0_valid_T_12, _io_out_0_0_valid_T_9)
wire _io_out_0_0_valid_WIRE : UInt<1>
connect _io_out_0_0_valid_WIRE, _io_out_0_0_valid_T_13
node _io_out_0_0_valid_T_14 = neq(sel_flat, UInt<1>(0h0))
node _io_out_0_0_valid_T_15 = and(_io_out_0_0_valid_WIRE, _io_out_0_0_valid_T_14)
connect io.out.`0`[0].valid, _io_out_0_0_valid_T_15
node _io_out_0_0_bits_T = bits(sel_flat, 0, 0)
node _io_out_0_0_bits_T_1 = bits(sel_flat, 1, 1)
node _io_out_0_0_bits_T_2 = bits(sel_flat, 2, 2)
node _io_out_0_0_bits_T_3 = bits(sel_flat, 3, 3)
node _io_out_0_0_bits_T_4 = bits(sel_flat, 4, 4)
wire _io_out_0_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}
node _io_out_0_0_bits_T_5 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_6 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_7 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_8 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_9 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_10 = or(_io_out_0_0_bits_T_5, _io_out_0_0_bits_T_6)
node _io_out_0_0_bits_T_11 = or(_io_out_0_0_bits_T_10, _io_out_0_0_bits_T_7)
node _io_out_0_0_bits_T_12 = or(_io_out_0_0_bits_T_11, _io_out_0_0_bits_T_8)
node _io_out_0_0_bits_T_13 = or(_io_out_0_0_bits_T_12, _io_out_0_0_bits_T_9)
wire _io_out_0_0_bits_WIRE_1 : UInt<2>
connect _io_out_0_0_bits_WIRE_1, _io_out_0_0_bits_T_13
connect _io_out_0_0_bits_WIRE.virt_channel_id, _io_out_0_0_bits_WIRE_1
wire _io_out_0_0_bits_WIRE_2 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _io_out_0_0_bits_T_14 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_15 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_16 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_17 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_18 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_19 = or(_io_out_0_0_bits_T_14, _io_out_0_0_bits_T_15)
node _io_out_0_0_bits_T_20 = or(_io_out_0_0_bits_T_19, _io_out_0_0_bits_T_16)
node _io_out_0_0_bits_T_21 = or(_io_out_0_0_bits_T_20, _io_out_0_0_bits_T_17)
node _io_out_0_0_bits_T_22 = or(_io_out_0_0_bits_T_21, _io_out_0_0_bits_T_18)
wire _io_out_0_0_bits_WIRE_3 : UInt<2>
connect _io_out_0_0_bits_WIRE_3, _io_out_0_0_bits_T_22
connect _io_out_0_0_bits_WIRE_2.egress_node_id, _io_out_0_0_bits_WIRE_3
node _io_out_0_0_bits_T_23 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_0_0_bits_T_24 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_0_0_bits_T_25 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_0_0_bits_T_26 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_0_0_bits_T_27 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_0_0_bits_T_28 = or(_io_out_0_0_bits_T_23, _io_out_0_0_bits_T_24)
node _io_out_0_0_bits_T_29 = or(_io_out_0_0_bits_T_28, _io_out_0_0_bits_T_25)
node _io_out_0_0_bits_T_30 = or(_io_out_0_0_bits_T_29, _io_out_0_0_bits_T_26)
node _io_out_0_0_bits_T_31 = or(_io_out_0_0_bits_T_30, _io_out_0_0_bits_T_27)
wire _io_out_0_0_bits_WIRE_4 : UInt<4>
connect _io_out_0_0_bits_WIRE_4, _io_out_0_0_bits_T_31
connect _io_out_0_0_bits_WIRE_2.egress_node, _io_out_0_0_bits_WIRE_4
node _io_out_0_0_bits_T_32 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_33 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_34 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_35 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_36 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_37 = or(_io_out_0_0_bits_T_32, _io_out_0_0_bits_T_33)
node _io_out_0_0_bits_T_38 = or(_io_out_0_0_bits_T_37, _io_out_0_0_bits_T_34)
node _io_out_0_0_bits_T_39 = or(_io_out_0_0_bits_T_38, _io_out_0_0_bits_T_35)
node _io_out_0_0_bits_T_40 = or(_io_out_0_0_bits_T_39, _io_out_0_0_bits_T_36)
wire _io_out_0_0_bits_WIRE_5 : UInt<3>
connect _io_out_0_0_bits_WIRE_5, _io_out_0_0_bits_T_40
connect _io_out_0_0_bits_WIRE_2.ingress_node_id, _io_out_0_0_bits_WIRE_5
node _io_out_0_0_bits_T_41 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_0_0_bits_T_42 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_0_0_bits_T_43 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_0_0_bits_T_44 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_0_0_bits_T_45 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_0_0_bits_T_46 = or(_io_out_0_0_bits_T_41, _io_out_0_0_bits_T_42)
node _io_out_0_0_bits_T_47 = or(_io_out_0_0_bits_T_46, _io_out_0_0_bits_T_43)
node _io_out_0_0_bits_T_48 = or(_io_out_0_0_bits_T_47, _io_out_0_0_bits_T_44)
node _io_out_0_0_bits_T_49 = or(_io_out_0_0_bits_T_48, _io_out_0_0_bits_T_45)
wire _io_out_0_0_bits_WIRE_6 : UInt<4>
connect _io_out_0_0_bits_WIRE_6, _io_out_0_0_bits_T_49
connect _io_out_0_0_bits_WIRE_2.ingress_node, _io_out_0_0_bits_WIRE_6
node _io_out_0_0_bits_T_50 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_51 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_52 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_53 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_54 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_55 = or(_io_out_0_0_bits_T_50, _io_out_0_0_bits_T_51)
node _io_out_0_0_bits_T_56 = or(_io_out_0_0_bits_T_55, _io_out_0_0_bits_T_52)
node _io_out_0_0_bits_T_57 = or(_io_out_0_0_bits_T_56, _io_out_0_0_bits_T_53)
node _io_out_0_0_bits_T_58 = or(_io_out_0_0_bits_T_57, _io_out_0_0_bits_T_54)
wire _io_out_0_0_bits_WIRE_7 : UInt<2>
connect _io_out_0_0_bits_WIRE_7, _io_out_0_0_bits_T_58
connect _io_out_0_0_bits_WIRE_2.vnet_id, _io_out_0_0_bits_WIRE_7
connect _io_out_0_0_bits_WIRE.flow, _io_out_0_0_bits_WIRE_2
node _io_out_0_0_bits_T_59 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0))
node _io_out_0_0_bits_T_60 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0))
node _io_out_0_0_bits_T_61 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0))
node _io_out_0_0_bits_T_62 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.payload, UInt<1>(0h0))
node _io_out_0_0_bits_T_63 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.payload, UInt<1>(0h0))
node _io_out_0_0_bits_T_64 = or(_io_out_0_0_bits_T_59, _io_out_0_0_bits_T_60)
node _io_out_0_0_bits_T_65 = or(_io_out_0_0_bits_T_64, _io_out_0_0_bits_T_61)
node _io_out_0_0_bits_T_66 = or(_io_out_0_0_bits_T_65, _io_out_0_0_bits_T_62)
node _io_out_0_0_bits_T_67 = or(_io_out_0_0_bits_T_66, _io_out_0_0_bits_T_63)
wire _io_out_0_0_bits_WIRE_8 : UInt<145>
connect _io_out_0_0_bits_WIRE_8, _io_out_0_0_bits_T_67
connect _io_out_0_0_bits_WIRE.payload, _io_out_0_0_bits_WIRE_8
node _io_out_0_0_bits_T_68 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0))
node _io_out_0_0_bits_T_69 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0))
node _io_out_0_0_bits_T_70 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0))
node _io_out_0_0_bits_T_71 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.tail, UInt<1>(0h0))
node _io_out_0_0_bits_T_72 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.tail, UInt<1>(0h0))
node _io_out_0_0_bits_T_73 = or(_io_out_0_0_bits_T_68, _io_out_0_0_bits_T_69)
node _io_out_0_0_bits_T_74 = or(_io_out_0_0_bits_T_73, _io_out_0_0_bits_T_70)
node _io_out_0_0_bits_T_75 = or(_io_out_0_0_bits_T_74, _io_out_0_0_bits_T_71)
node _io_out_0_0_bits_T_76 = or(_io_out_0_0_bits_T_75, _io_out_0_0_bits_T_72)
wire _io_out_0_0_bits_WIRE_9 : UInt<1>
connect _io_out_0_0_bits_WIRE_9, _io_out_0_0_bits_T_76
connect _io_out_0_0_bits_WIRE.tail, _io_out_0_0_bits_WIRE_9
node _io_out_0_0_bits_T_77 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0))
node _io_out_0_0_bits_T_78 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0))
node _io_out_0_0_bits_T_79 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0))
node _io_out_0_0_bits_T_80 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.head, UInt<1>(0h0))
node _io_out_0_0_bits_T_81 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.head, UInt<1>(0h0))
node _io_out_0_0_bits_T_82 = or(_io_out_0_0_bits_T_77, _io_out_0_0_bits_T_78)
node _io_out_0_0_bits_T_83 = or(_io_out_0_0_bits_T_82, _io_out_0_0_bits_T_79)
node _io_out_0_0_bits_T_84 = or(_io_out_0_0_bits_T_83, _io_out_0_0_bits_T_80)
node _io_out_0_0_bits_T_85 = or(_io_out_0_0_bits_T_84, _io_out_0_0_bits_T_81)
wire _io_out_0_0_bits_WIRE_10 : UInt<1>
connect _io_out_0_0_bits_WIRE_10, _io_out_0_0_bits_T_85
connect _io_out_0_0_bits_WIRE.head, _io_out_0_0_bits_WIRE_10
connect io.out.`0`[0].bits, _io_out_0_0_bits_WIRE
node _io_out_0_0_bits_virt_channel_id_T = bits(sel_flat, 0, 0)
node _io_out_0_0_bits_virt_channel_id_T_1 = bits(sel_flat, 1, 1)
node _io_out_0_0_bits_virt_channel_id_T_2 = bits(sel_flat, 2, 2)
node _io_out_0_0_bits_virt_channel_id_T_3 = bits(sel_flat, 3, 3)
node _io_out_0_0_bits_virt_channel_id_T_4 = bits(sel_flat, 4, 4)
node _io_out_0_0_bits_virt_channel_id_T_5 = mux(_io_out_0_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_0_0_bits_virt_channel_id_T_6 = mux(_io_out_0_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_0_0_bits_virt_channel_id_T_7 = mux(_io_out_0_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_0_0_bits_virt_channel_id_T_8 = mux(_io_out_0_0_bits_virt_channel_id_T_3, in_flat[3].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_0_0_bits_virt_channel_id_T_9 = mux(_io_out_0_0_bits_virt_channel_id_T_4, in_flat[4].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_0_0_bits_virt_channel_id_T_10 = or(_io_out_0_0_bits_virt_channel_id_T_5, _io_out_0_0_bits_virt_channel_id_T_6)
node _io_out_0_0_bits_virt_channel_id_T_11 = or(_io_out_0_0_bits_virt_channel_id_T_10, _io_out_0_0_bits_virt_channel_id_T_7)
node _io_out_0_0_bits_virt_channel_id_T_12 = or(_io_out_0_0_bits_virt_channel_id_T_11, _io_out_0_0_bits_virt_channel_id_T_8)
node _io_out_0_0_bits_virt_channel_id_T_13 = or(_io_out_0_0_bits_virt_channel_id_T_12, _io_out_0_0_bits_virt_channel_id_T_9)
wire _io_out_0_0_bits_virt_channel_id_WIRE : UInt<2>
connect _io_out_0_0_bits_virt_channel_id_WIRE, _io_out_0_0_bits_virt_channel_id_T_13
connect io.out.`0`[0].bits.virt_channel_id, _io_out_0_0_bits_virt_channel_id_WIRE
node sel_flat_lo_1 = cat(io.sel.`1`[0].`1`[0], io.sel.`1`[0].`0`[0])
node sel_flat_hi_hi_1 = cat(io.sel.`1`[0].`4`[0], io.sel.`1`[0].`3`[0])
node sel_flat_hi_1 = cat(sel_flat_hi_hi_1, io.sel.`1`[0].`2`[0])
node sel_flat_1 = cat(sel_flat_hi_1, sel_flat_lo_1)
node _T_17 = bits(sel_flat_1, 0, 0)
node _T_18 = bits(sel_flat_1, 1, 1)
node _T_19 = bits(sel_flat_1, 2, 2)
node _T_20 = bits(sel_flat_1, 3, 3)
node _T_21 = bits(sel_flat_1, 4, 4)
node _T_22 = add(_T_17, _T_18)
node _T_23 = bits(_T_22, 1, 0)
node _T_24 = add(_T_20, _T_21)
node _T_25 = bits(_T_24, 1, 0)
node _T_26 = add(_T_19, _T_25)
node _T_27 = bits(_T_26, 1, 0)
node _T_28 = add(_T_23, _T_27)
node _T_29 = bits(_T_28, 2, 0)
node _T_30 = leq(_T_29, UInt<1>(0h1))
node _T_31 = asUInt(reset)
node _T_32 = eq(_T_31, UInt<1>(0h0))
when _T_32 :
node _T_33 = eq(_T_30, UInt<1>(0h0))
when _T_33 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf_1
assert(clock, _T_30, UInt<1>(0h1), "") : assert_1
node _io_out_1_0_valid_T = bits(sel_flat_1, 0, 0)
node _io_out_1_0_valid_T_1 = bits(sel_flat_1, 1, 1)
node _io_out_1_0_valid_T_2 = bits(sel_flat_1, 2, 2)
node _io_out_1_0_valid_T_3 = bits(sel_flat_1, 3, 3)
node _io_out_1_0_valid_T_4 = bits(sel_flat_1, 4, 4)
node _io_out_1_0_valid_T_5 = mux(_io_out_1_0_valid_T, in_flat[0].valid, UInt<1>(0h0))
node _io_out_1_0_valid_T_6 = mux(_io_out_1_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0))
node _io_out_1_0_valid_T_7 = mux(_io_out_1_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0))
node _io_out_1_0_valid_T_8 = mux(_io_out_1_0_valid_T_3, in_flat[3].valid, UInt<1>(0h0))
node _io_out_1_0_valid_T_9 = mux(_io_out_1_0_valid_T_4, in_flat[4].valid, UInt<1>(0h0))
node _io_out_1_0_valid_T_10 = or(_io_out_1_0_valid_T_5, _io_out_1_0_valid_T_6)
node _io_out_1_0_valid_T_11 = or(_io_out_1_0_valid_T_10, _io_out_1_0_valid_T_7)
node _io_out_1_0_valid_T_12 = or(_io_out_1_0_valid_T_11, _io_out_1_0_valid_T_8)
node _io_out_1_0_valid_T_13 = or(_io_out_1_0_valid_T_12, _io_out_1_0_valid_T_9)
wire _io_out_1_0_valid_WIRE : UInt<1>
connect _io_out_1_0_valid_WIRE, _io_out_1_0_valid_T_13
node _io_out_1_0_valid_T_14 = neq(sel_flat_1, UInt<1>(0h0))
node _io_out_1_0_valid_T_15 = and(_io_out_1_0_valid_WIRE, _io_out_1_0_valid_T_14)
connect io.out.`1`[0].valid, _io_out_1_0_valid_T_15
node _io_out_1_0_bits_T = bits(sel_flat_1, 0, 0)
node _io_out_1_0_bits_T_1 = bits(sel_flat_1, 1, 1)
node _io_out_1_0_bits_T_2 = bits(sel_flat_1, 2, 2)
node _io_out_1_0_bits_T_3 = bits(sel_flat_1, 3, 3)
node _io_out_1_0_bits_T_4 = bits(sel_flat_1, 4, 4)
wire _io_out_1_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}
node _io_out_1_0_bits_T_5 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_6 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_7 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_8 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_9 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_10 = or(_io_out_1_0_bits_T_5, _io_out_1_0_bits_T_6)
node _io_out_1_0_bits_T_11 = or(_io_out_1_0_bits_T_10, _io_out_1_0_bits_T_7)
node _io_out_1_0_bits_T_12 = or(_io_out_1_0_bits_T_11, _io_out_1_0_bits_T_8)
node _io_out_1_0_bits_T_13 = or(_io_out_1_0_bits_T_12, _io_out_1_0_bits_T_9)
wire _io_out_1_0_bits_WIRE_1 : UInt<2>
connect _io_out_1_0_bits_WIRE_1, _io_out_1_0_bits_T_13
connect _io_out_1_0_bits_WIRE.virt_channel_id, _io_out_1_0_bits_WIRE_1
wire _io_out_1_0_bits_WIRE_2 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _io_out_1_0_bits_T_14 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_15 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_16 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_17 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_18 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_19 = or(_io_out_1_0_bits_T_14, _io_out_1_0_bits_T_15)
node _io_out_1_0_bits_T_20 = or(_io_out_1_0_bits_T_19, _io_out_1_0_bits_T_16)
node _io_out_1_0_bits_T_21 = or(_io_out_1_0_bits_T_20, _io_out_1_0_bits_T_17)
node _io_out_1_0_bits_T_22 = or(_io_out_1_0_bits_T_21, _io_out_1_0_bits_T_18)
wire _io_out_1_0_bits_WIRE_3 : UInt<2>
connect _io_out_1_0_bits_WIRE_3, _io_out_1_0_bits_T_22
connect _io_out_1_0_bits_WIRE_2.egress_node_id, _io_out_1_0_bits_WIRE_3
node _io_out_1_0_bits_T_23 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_1_0_bits_T_24 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_1_0_bits_T_25 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_1_0_bits_T_26 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_1_0_bits_T_27 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_1_0_bits_T_28 = or(_io_out_1_0_bits_T_23, _io_out_1_0_bits_T_24)
node _io_out_1_0_bits_T_29 = or(_io_out_1_0_bits_T_28, _io_out_1_0_bits_T_25)
node _io_out_1_0_bits_T_30 = or(_io_out_1_0_bits_T_29, _io_out_1_0_bits_T_26)
node _io_out_1_0_bits_T_31 = or(_io_out_1_0_bits_T_30, _io_out_1_0_bits_T_27)
wire _io_out_1_0_bits_WIRE_4 : UInt<4>
connect _io_out_1_0_bits_WIRE_4, _io_out_1_0_bits_T_31
connect _io_out_1_0_bits_WIRE_2.egress_node, _io_out_1_0_bits_WIRE_4
node _io_out_1_0_bits_T_32 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_33 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_34 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_35 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_36 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_37 = or(_io_out_1_0_bits_T_32, _io_out_1_0_bits_T_33)
node _io_out_1_0_bits_T_38 = or(_io_out_1_0_bits_T_37, _io_out_1_0_bits_T_34)
node _io_out_1_0_bits_T_39 = or(_io_out_1_0_bits_T_38, _io_out_1_0_bits_T_35)
node _io_out_1_0_bits_T_40 = or(_io_out_1_0_bits_T_39, _io_out_1_0_bits_T_36)
wire _io_out_1_0_bits_WIRE_5 : UInt<3>
connect _io_out_1_0_bits_WIRE_5, _io_out_1_0_bits_T_40
connect _io_out_1_0_bits_WIRE_2.ingress_node_id, _io_out_1_0_bits_WIRE_5
node _io_out_1_0_bits_T_41 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_1_0_bits_T_42 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_1_0_bits_T_43 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_1_0_bits_T_44 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_1_0_bits_T_45 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_1_0_bits_T_46 = or(_io_out_1_0_bits_T_41, _io_out_1_0_bits_T_42)
node _io_out_1_0_bits_T_47 = or(_io_out_1_0_bits_T_46, _io_out_1_0_bits_T_43)
node _io_out_1_0_bits_T_48 = or(_io_out_1_0_bits_T_47, _io_out_1_0_bits_T_44)
node _io_out_1_0_bits_T_49 = or(_io_out_1_0_bits_T_48, _io_out_1_0_bits_T_45)
wire _io_out_1_0_bits_WIRE_6 : UInt<4>
connect _io_out_1_0_bits_WIRE_6, _io_out_1_0_bits_T_49
connect _io_out_1_0_bits_WIRE_2.ingress_node, _io_out_1_0_bits_WIRE_6
node _io_out_1_0_bits_T_50 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_51 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_52 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_53 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_54 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_55 = or(_io_out_1_0_bits_T_50, _io_out_1_0_bits_T_51)
node _io_out_1_0_bits_T_56 = or(_io_out_1_0_bits_T_55, _io_out_1_0_bits_T_52)
node _io_out_1_0_bits_T_57 = or(_io_out_1_0_bits_T_56, _io_out_1_0_bits_T_53)
node _io_out_1_0_bits_T_58 = or(_io_out_1_0_bits_T_57, _io_out_1_0_bits_T_54)
wire _io_out_1_0_bits_WIRE_7 : UInt<2>
connect _io_out_1_0_bits_WIRE_7, _io_out_1_0_bits_T_58
connect _io_out_1_0_bits_WIRE_2.vnet_id, _io_out_1_0_bits_WIRE_7
connect _io_out_1_0_bits_WIRE.flow, _io_out_1_0_bits_WIRE_2
node _io_out_1_0_bits_T_59 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0))
node _io_out_1_0_bits_T_60 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0))
node _io_out_1_0_bits_T_61 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0))
node _io_out_1_0_bits_T_62 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.payload, UInt<1>(0h0))
node _io_out_1_0_bits_T_63 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.payload, UInt<1>(0h0))
node _io_out_1_0_bits_T_64 = or(_io_out_1_0_bits_T_59, _io_out_1_0_bits_T_60)
node _io_out_1_0_bits_T_65 = or(_io_out_1_0_bits_T_64, _io_out_1_0_bits_T_61)
node _io_out_1_0_bits_T_66 = or(_io_out_1_0_bits_T_65, _io_out_1_0_bits_T_62)
node _io_out_1_0_bits_T_67 = or(_io_out_1_0_bits_T_66, _io_out_1_0_bits_T_63)
wire _io_out_1_0_bits_WIRE_8 : UInt<145>
connect _io_out_1_0_bits_WIRE_8, _io_out_1_0_bits_T_67
connect _io_out_1_0_bits_WIRE.payload, _io_out_1_0_bits_WIRE_8
node _io_out_1_0_bits_T_68 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0))
node _io_out_1_0_bits_T_69 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0))
node _io_out_1_0_bits_T_70 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0))
node _io_out_1_0_bits_T_71 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.tail, UInt<1>(0h0))
node _io_out_1_0_bits_T_72 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.tail, UInt<1>(0h0))
node _io_out_1_0_bits_T_73 = or(_io_out_1_0_bits_T_68, _io_out_1_0_bits_T_69)
node _io_out_1_0_bits_T_74 = or(_io_out_1_0_bits_T_73, _io_out_1_0_bits_T_70)
node _io_out_1_0_bits_T_75 = or(_io_out_1_0_bits_T_74, _io_out_1_0_bits_T_71)
node _io_out_1_0_bits_T_76 = or(_io_out_1_0_bits_T_75, _io_out_1_0_bits_T_72)
wire _io_out_1_0_bits_WIRE_9 : UInt<1>
connect _io_out_1_0_bits_WIRE_9, _io_out_1_0_bits_T_76
connect _io_out_1_0_bits_WIRE.tail, _io_out_1_0_bits_WIRE_9
node _io_out_1_0_bits_T_77 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0))
node _io_out_1_0_bits_T_78 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0))
node _io_out_1_0_bits_T_79 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0))
node _io_out_1_0_bits_T_80 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.head, UInt<1>(0h0))
node _io_out_1_0_bits_T_81 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.head, UInt<1>(0h0))
node _io_out_1_0_bits_T_82 = or(_io_out_1_0_bits_T_77, _io_out_1_0_bits_T_78)
node _io_out_1_0_bits_T_83 = or(_io_out_1_0_bits_T_82, _io_out_1_0_bits_T_79)
node _io_out_1_0_bits_T_84 = or(_io_out_1_0_bits_T_83, _io_out_1_0_bits_T_80)
node _io_out_1_0_bits_T_85 = or(_io_out_1_0_bits_T_84, _io_out_1_0_bits_T_81)
wire _io_out_1_0_bits_WIRE_10 : UInt<1>
connect _io_out_1_0_bits_WIRE_10, _io_out_1_0_bits_T_85
connect _io_out_1_0_bits_WIRE.head, _io_out_1_0_bits_WIRE_10
connect io.out.`1`[0].bits, _io_out_1_0_bits_WIRE
node _io_out_1_0_bits_virt_channel_id_T = bits(sel_flat_1, 0, 0)
node _io_out_1_0_bits_virt_channel_id_T_1 = bits(sel_flat_1, 1, 1)
node _io_out_1_0_bits_virt_channel_id_T_2 = bits(sel_flat_1, 2, 2)
node _io_out_1_0_bits_virt_channel_id_T_3 = bits(sel_flat_1, 3, 3)
node _io_out_1_0_bits_virt_channel_id_T_4 = bits(sel_flat_1, 4, 4)
node _io_out_1_0_bits_virt_channel_id_T_5 = mux(_io_out_1_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_1_0_bits_virt_channel_id_T_6 = mux(_io_out_1_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_1_0_bits_virt_channel_id_T_7 = mux(_io_out_1_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_1_0_bits_virt_channel_id_T_8 = mux(_io_out_1_0_bits_virt_channel_id_T_3, in_flat[3].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_1_0_bits_virt_channel_id_T_9 = mux(_io_out_1_0_bits_virt_channel_id_T_4, in_flat[4].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_1_0_bits_virt_channel_id_T_10 = or(_io_out_1_0_bits_virt_channel_id_T_5, _io_out_1_0_bits_virt_channel_id_T_6)
node _io_out_1_0_bits_virt_channel_id_T_11 = or(_io_out_1_0_bits_virt_channel_id_T_10, _io_out_1_0_bits_virt_channel_id_T_7)
node _io_out_1_0_bits_virt_channel_id_T_12 = or(_io_out_1_0_bits_virt_channel_id_T_11, _io_out_1_0_bits_virt_channel_id_T_8)
node _io_out_1_0_bits_virt_channel_id_T_13 = or(_io_out_1_0_bits_virt_channel_id_T_12, _io_out_1_0_bits_virt_channel_id_T_9)
wire _io_out_1_0_bits_virt_channel_id_WIRE : UInt<2>
connect _io_out_1_0_bits_virt_channel_id_WIRE, _io_out_1_0_bits_virt_channel_id_T_13
connect io.out.`1`[0].bits.virt_channel_id, _io_out_1_0_bits_virt_channel_id_WIRE
node sel_flat_lo_2 = cat(io.sel.`2`[0].`1`[0], io.sel.`2`[0].`0`[0])
node sel_flat_hi_hi_2 = cat(io.sel.`2`[0].`4`[0], io.sel.`2`[0].`3`[0])
node sel_flat_hi_2 = cat(sel_flat_hi_hi_2, io.sel.`2`[0].`2`[0])
node sel_flat_2 = cat(sel_flat_hi_2, sel_flat_lo_2)
node _T_34 = bits(sel_flat_2, 0, 0)
node _T_35 = bits(sel_flat_2, 1, 1)
node _T_36 = bits(sel_flat_2, 2, 2)
node _T_37 = bits(sel_flat_2, 3, 3)
node _T_38 = bits(sel_flat_2, 4, 4)
node _T_39 = add(_T_34, _T_35)
node _T_40 = bits(_T_39, 1, 0)
node _T_41 = add(_T_37, _T_38)
node _T_42 = bits(_T_41, 1, 0)
node _T_43 = add(_T_36, _T_42)
node _T_44 = bits(_T_43, 1, 0)
node _T_45 = add(_T_40, _T_44)
node _T_46 = bits(_T_45, 2, 0)
node _T_47 = leq(_T_46, UInt<1>(0h1))
node _T_48 = asUInt(reset)
node _T_49 = eq(_T_48, UInt<1>(0h0))
when _T_49 :
node _T_50 = eq(_T_47, UInt<1>(0h0))
when _T_50 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf_2
assert(clock, _T_47, UInt<1>(0h1), "") : assert_2
node _io_out_2_0_valid_T = bits(sel_flat_2, 0, 0)
node _io_out_2_0_valid_T_1 = bits(sel_flat_2, 1, 1)
node _io_out_2_0_valid_T_2 = bits(sel_flat_2, 2, 2)
node _io_out_2_0_valid_T_3 = bits(sel_flat_2, 3, 3)
node _io_out_2_0_valid_T_4 = bits(sel_flat_2, 4, 4)
node _io_out_2_0_valid_T_5 = mux(_io_out_2_0_valid_T, in_flat[0].valid, UInt<1>(0h0))
node _io_out_2_0_valid_T_6 = mux(_io_out_2_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0))
node _io_out_2_0_valid_T_7 = mux(_io_out_2_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0))
node _io_out_2_0_valid_T_8 = mux(_io_out_2_0_valid_T_3, in_flat[3].valid, UInt<1>(0h0))
node _io_out_2_0_valid_T_9 = mux(_io_out_2_0_valid_T_4, in_flat[4].valid, UInt<1>(0h0))
node _io_out_2_0_valid_T_10 = or(_io_out_2_0_valid_T_5, _io_out_2_0_valid_T_6)
node _io_out_2_0_valid_T_11 = or(_io_out_2_0_valid_T_10, _io_out_2_0_valid_T_7)
node _io_out_2_0_valid_T_12 = or(_io_out_2_0_valid_T_11, _io_out_2_0_valid_T_8)
node _io_out_2_0_valid_T_13 = or(_io_out_2_0_valid_T_12, _io_out_2_0_valid_T_9)
wire _io_out_2_0_valid_WIRE : UInt<1>
connect _io_out_2_0_valid_WIRE, _io_out_2_0_valid_T_13
node _io_out_2_0_valid_T_14 = neq(sel_flat_2, UInt<1>(0h0))
node _io_out_2_0_valid_T_15 = and(_io_out_2_0_valid_WIRE, _io_out_2_0_valid_T_14)
connect io.out.`2`[0].valid, _io_out_2_0_valid_T_15
node _io_out_2_0_bits_T = bits(sel_flat_2, 0, 0)
node _io_out_2_0_bits_T_1 = bits(sel_flat_2, 1, 1)
node _io_out_2_0_bits_T_2 = bits(sel_flat_2, 2, 2)
node _io_out_2_0_bits_T_3 = bits(sel_flat_2, 3, 3)
node _io_out_2_0_bits_T_4 = bits(sel_flat_2, 4, 4)
wire _io_out_2_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}
node _io_out_2_0_bits_T_5 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_6 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_7 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_8 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_9 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_10 = or(_io_out_2_0_bits_T_5, _io_out_2_0_bits_T_6)
node _io_out_2_0_bits_T_11 = or(_io_out_2_0_bits_T_10, _io_out_2_0_bits_T_7)
node _io_out_2_0_bits_T_12 = or(_io_out_2_0_bits_T_11, _io_out_2_0_bits_T_8)
node _io_out_2_0_bits_T_13 = or(_io_out_2_0_bits_T_12, _io_out_2_0_bits_T_9)
wire _io_out_2_0_bits_WIRE_1 : UInt<2>
connect _io_out_2_0_bits_WIRE_1, _io_out_2_0_bits_T_13
connect _io_out_2_0_bits_WIRE.virt_channel_id, _io_out_2_0_bits_WIRE_1
wire _io_out_2_0_bits_WIRE_2 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _io_out_2_0_bits_T_14 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_15 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_16 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_17 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_18 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_19 = or(_io_out_2_0_bits_T_14, _io_out_2_0_bits_T_15)
node _io_out_2_0_bits_T_20 = or(_io_out_2_0_bits_T_19, _io_out_2_0_bits_T_16)
node _io_out_2_0_bits_T_21 = or(_io_out_2_0_bits_T_20, _io_out_2_0_bits_T_17)
node _io_out_2_0_bits_T_22 = or(_io_out_2_0_bits_T_21, _io_out_2_0_bits_T_18)
wire _io_out_2_0_bits_WIRE_3 : UInt<2>
connect _io_out_2_0_bits_WIRE_3, _io_out_2_0_bits_T_22
connect _io_out_2_0_bits_WIRE_2.egress_node_id, _io_out_2_0_bits_WIRE_3
node _io_out_2_0_bits_T_23 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_2_0_bits_T_24 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_2_0_bits_T_25 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_2_0_bits_T_26 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_2_0_bits_T_27 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_2_0_bits_T_28 = or(_io_out_2_0_bits_T_23, _io_out_2_0_bits_T_24)
node _io_out_2_0_bits_T_29 = or(_io_out_2_0_bits_T_28, _io_out_2_0_bits_T_25)
node _io_out_2_0_bits_T_30 = or(_io_out_2_0_bits_T_29, _io_out_2_0_bits_T_26)
node _io_out_2_0_bits_T_31 = or(_io_out_2_0_bits_T_30, _io_out_2_0_bits_T_27)
wire _io_out_2_0_bits_WIRE_4 : UInt<4>
connect _io_out_2_0_bits_WIRE_4, _io_out_2_0_bits_T_31
connect _io_out_2_0_bits_WIRE_2.egress_node, _io_out_2_0_bits_WIRE_4
node _io_out_2_0_bits_T_32 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_33 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_34 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_35 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_36 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_37 = or(_io_out_2_0_bits_T_32, _io_out_2_0_bits_T_33)
node _io_out_2_0_bits_T_38 = or(_io_out_2_0_bits_T_37, _io_out_2_0_bits_T_34)
node _io_out_2_0_bits_T_39 = or(_io_out_2_0_bits_T_38, _io_out_2_0_bits_T_35)
node _io_out_2_0_bits_T_40 = or(_io_out_2_0_bits_T_39, _io_out_2_0_bits_T_36)
wire _io_out_2_0_bits_WIRE_5 : UInt<3>
connect _io_out_2_0_bits_WIRE_5, _io_out_2_0_bits_T_40
connect _io_out_2_0_bits_WIRE_2.ingress_node_id, _io_out_2_0_bits_WIRE_5
node _io_out_2_0_bits_T_41 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_2_0_bits_T_42 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_2_0_bits_T_43 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_2_0_bits_T_44 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_2_0_bits_T_45 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_2_0_bits_T_46 = or(_io_out_2_0_bits_T_41, _io_out_2_0_bits_T_42)
node _io_out_2_0_bits_T_47 = or(_io_out_2_0_bits_T_46, _io_out_2_0_bits_T_43)
node _io_out_2_0_bits_T_48 = or(_io_out_2_0_bits_T_47, _io_out_2_0_bits_T_44)
node _io_out_2_0_bits_T_49 = or(_io_out_2_0_bits_T_48, _io_out_2_0_bits_T_45)
wire _io_out_2_0_bits_WIRE_6 : UInt<4>
connect _io_out_2_0_bits_WIRE_6, _io_out_2_0_bits_T_49
connect _io_out_2_0_bits_WIRE_2.ingress_node, _io_out_2_0_bits_WIRE_6
node _io_out_2_0_bits_T_50 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_51 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_52 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_53 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_54 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_55 = or(_io_out_2_0_bits_T_50, _io_out_2_0_bits_T_51)
node _io_out_2_0_bits_T_56 = or(_io_out_2_0_bits_T_55, _io_out_2_0_bits_T_52)
node _io_out_2_0_bits_T_57 = or(_io_out_2_0_bits_T_56, _io_out_2_0_bits_T_53)
node _io_out_2_0_bits_T_58 = or(_io_out_2_0_bits_T_57, _io_out_2_0_bits_T_54)
wire _io_out_2_0_bits_WIRE_7 : UInt<2>
connect _io_out_2_0_bits_WIRE_7, _io_out_2_0_bits_T_58
connect _io_out_2_0_bits_WIRE_2.vnet_id, _io_out_2_0_bits_WIRE_7
connect _io_out_2_0_bits_WIRE.flow, _io_out_2_0_bits_WIRE_2
node _io_out_2_0_bits_T_59 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0))
node _io_out_2_0_bits_T_60 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0))
node _io_out_2_0_bits_T_61 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0))
node _io_out_2_0_bits_T_62 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.payload, UInt<1>(0h0))
node _io_out_2_0_bits_T_63 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.payload, UInt<1>(0h0))
node _io_out_2_0_bits_T_64 = or(_io_out_2_0_bits_T_59, _io_out_2_0_bits_T_60)
node _io_out_2_0_bits_T_65 = or(_io_out_2_0_bits_T_64, _io_out_2_0_bits_T_61)
node _io_out_2_0_bits_T_66 = or(_io_out_2_0_bits_T_65, _io_out_2_0_bits_T_62)
node _io_out_2_0_bits_T_67 = or(_io_out_2_0_bits_T_66, _io_out_2_0_bits_T_63)
wire _io_out_2_0_bits_WIRE_8 : UInt<145>
connect _io_out_2_0_bits_WIRE_8, _io_out_2_0_bits_T_67
connect _io_out_2_0_bits_WIRE.payload, _io_out_2_0_bits_WIRE_8
node _io_out_2_0_bits_T_68 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0))
node _io_out_2_0_bits_T_69 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0))
node _io_out_2_0_bits_T_70 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0))
node _io_out_2_0_bits_T_71 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.tail, UInt<1>(0h0))
node _io_out_2_0_bits_T_72 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.tail, UInt<1>(0h0))
node _io_out_2_0_bits_T_73 = or(_io_out_2_0_bits_T_68, _io_out_2_0_bits_T_69)
node _io_out_2_0_bits_T_74 = or(_io_out_2_0_bits_T_73, _io_out_2_0_bits_T_70)
node _io_out_2_0_bits_T_75 = or(_io_out_2_0_bits_T_74, _io_out_2_0_bits_T_71)
node _io_out_2_0_bits_T_76 = or(_io_out_2_0_bits_T_75, _io_out_2_0_bits_T_72)
wire _io_out_2_0_bits_WIRE_9 : UInt<1>
connect _io_out_2_0_bits_WIRE_9, _io_out_2_0_bits_T_76
connect _io_out_2_0_bits_WIRE.tail, _io_out_2_0_bits_WIRE_9
node _io_out_2_0_bits_T_77 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0))
node _io_out_2_0_bits_T_78 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0))
node _io_out_2_0_bits_T_79 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0))
node _io_out_2_0_bits_T_80 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.head, UInt<1>(0h0))
node _io_out_2_0_bits_T_81 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.head, UInt<1>(0h0))
node _io_out_2_0_bits_T_82 = or(_io_out_2_0_bits_T_77, _io_out_2_0_bits_T_78)
node _io_out_2_0_bits_T_83 = or(_io_out_2_0_bits_T_82, _io_out_2_0_bits_T_79)
node _io_out_2_0_bits_T_84 = or(_io_out_2_0_bits_T_83, _io_out_2_0_bits_T_80)
node _io_out_2_0_bits_T_85 = or(_io_out_2_0_bits_T_84, _io_out_2_0_bits_T_81)
wire _io_out_2_0_bits_WIRE_10 : UInt<1>
connect _io_out_2_0_bits_WIRE_10, _io_out_2_0_bits_T_85
connect _io_out_2_0_bits_WIRE.head, _io_out_2_0_bits_WIRE_10
connect io.out.`2`[0].bits, _io_out_2_0_bits_WIRE
node _io_out_2_0_bits_virt_channel_id_T = bits(sel_flat_2, 0, 0)
node _io_out_2_0_bits_virt_channel_id_T_1 = bits(sel_flat_2, 1, 1)
node _io_out_2_0_bits_virt_channel_id_T_2 = bits(sel_flat_2, 2, 2)
node _io_out_2_0_bits_virt_channel_id_T_3 = bits(sel_flat_2, 3, 3)
node _io_out_2_0_bits_virt_channel_id_T_4 = bits(sel_flat_2, 4, 4)
node _io_out_2_0_bits_virt_channel_id_T_5 = mux(_io_out_2_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_2_0_bits_virt_channel_id_T_6 = mux(_io_out_2_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_2_0_bits_virt_channel_id_T_7 = mux(_io_out_2_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_2_0_bits_virt_channel_id_T_8 = mux(_io_out_2_0_bits_virt_channel_id_T_3, in_flat[3].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_2_0_bits_virt_channel_id_T_9 = mux(_io_out_2_0_bits_virt_channel_id_T_4, in_flat[4].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_2_0_bits_virt_channel_id_T_10 = or(_io_out_2_0_bits_virt_channel_id_T_5, _io_out_2_0_bits_virt_channel_id_T_6)
node _io_out_2_0_bits_virt_channel_id_T_11 = or(_io_out_2_0_bits_virt_channel_id_T_10, _io_out_2_0_bits_virt_channel_id_T_7)
node _io_out_2_0_bits_virt_channel_id_T_12 = or(_io_out_2_0_bits_virt_channel_id_T_11, _io_out_2_0_bits_virt_channel_id_T_8)
node _io_out_2_0_bits_virt_channel_id_T_13 = or(_io_out_2_0_bits_virt_channel_id_T_12, _io_out_2_0_bits_virt_channel_id_T_9)
wire _io_out_2_0_bits_virt_channel_id_WIRE : UInt<2>
connect _io_out_2_0_bits_virt_channel_id_WIRE, _io_out_2_0_bits_virt_channel_id_T_13
connect io.out.`2`[0].bits.virt_channel_id, _io_out_2_0_bits_virt_channel_id_WIRE
node sel_flat_lo_3 = cat(io.sel.`3`[0].`1`[0], io.sel.`3`[0].`0`[0])
node sel_flat_hi_hi_3 = cat(io.sel.`3`[0].`4`[0], io.sel.`3`[0].`3`[0])
node sel_flat_hi_3 = cat(sel_flat_hi_hi_3, io.sel.`3`[0].`2`[0])
node sel_flat_3 = cat(sel_flat_hi_3, sel_flat_lo_3)
node _T_51 = bits(sel_flat_3, 0, 0)
node _T_52 = bits(sel_flat_3, 1, 1)
node _T_53 = bits(sel_flat_3, 2, 2)
node _T_54 = bits(sel_flat_3, 3, 3)
node _T_55 = bits(sel_flat_3, 4, 4)
node _T_56 = add(_T_51, _T_52)
node _T_57 = bits(_T_56, 1, 0)
node _T_58 = add(_T_54, _T_55)
node _T_59 = bits(_T_58, 1, 0)
node _T_60 = add(_T_53, _T_59)
node _T_61 = bits(_T_60, 1, 0)
node _T_62 = add(_T_57, _T_61)
node _T_63 = bits(_T_62, 2, 0)
node _T_64 = leq(_T_63, UInt<1>(0h1))
node _T_65 = asUInt(reset)
node _T_66 = eq(_T_65, UInt<1>(0h0))
when _T_66 :
node _T_67 = eq(_T_64, UInt<1>(0h0))
when _T_67 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf_3
assert(clock, _T_64, UInt<1>(0h1), "") : assert_3
node _io_out_3_0_valid_T = bits(sel_flat_3, 0, 0)
node _io_out_3_0_valid_T_1 = bits(sel_flat_3, 1, 1)
node _io_out_3_0_valid_T_2 = bits(sel_flat_3, 2, 2)
node _io_out_3_0_valid_T_3 = bits(sel_flat_3, 3, 3)
node _io_out_3_0_valid_T_4 = bits(sel_flat_3, 4, 4)
node _io_out_3_0_valid_T_5 = mux(_io_out_3_0_valid_T, in_flat[0].valid, UInt<1>(0h0))
node _io_out_3_0_valid_T_6 = mux(_io_out_3_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0))
node _io_out_3_0_valid_T_7 = mux(_io_out_3_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0))
node _io_out_3_0_valid_T_8 = mux(_io_out_3_0_valid_T_3, in_flat[3].valid, UInt<1>(0h0))
node _io_out_3_0_valid_T_9 = mux(_io_out_3_0_valid_T_4, in_flat[4].valid, UInt<1>(0h0))
node _io_out_3_0_valid_T_10 = or(_io_out_3_0_valid_T_5, _io_out_3_0_valid_T_6)
node _io_out_3_0_valid_T_11 = or(_io_out_3_0_valid_T_10, _io_out_3_0_valid_T_7)
node _io_out_3_0_valid_T_12 = or(_io_out_3_0_valid_T_11, _io_out_3_0_valid_T_8)
node _io_out_3_0_valid_T_13 = or(_io_out_3_0_valid_T_12, _io_out_3_0_valid_T_9)
wire _io_out_3_0_valid_WIRE : UInt<1>
connect _io_out_3_0_valid_WIRE, _io_out_3_0_valid_T_13
node _io_out_3_0_valid_T_14 = neq(sel_flat_3, UInt<1>(0h0))
node _io_out_3_0_valid_T_15 = and(_io_out_3_0_valid_WIRE, _io_out_3_0_valid_T_14)
connect io.out.`3`[0].valid, _io_out_3_0_valid_T_15
node _io_out_3_0_bits_T = bits(sel_flat_3, 0, 0)
node _io_out_3_0_bits_T_1 = bits(sel_flat_3, 1, 1)
node _io_out_3_0_bits_T_2 = bits(sel_flat_3, 2, 2)
node _io_out_3_0_bits_T_3 = bits(sel_flat_3, 3, 3)
node _io_out_3_0_bits_T_4 = bits(sel_flat_3, 4, 4)
wire _io_out_3_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}
node _io_out_3_0_bits_T_5 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_6 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_7 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_8 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_9 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_10 = or(_io_out_3_0_bits_T_5, _io_out_3_0_bits_T_6)
node _io_out_3_0_bits_T_11 = or(_io_out_3_0_bits_T_10, _io_out_3_0_bits_T_7)
node _io_out_3_0_bits_T_12 = or(_io_out_3_0_bits_T_11, _io_out_3_0_bits_T_8)
node _io_out_3_0_bits_T_13 = or(_io_out_3_0_bits_T_12, _io_out_3_0_bits_T_9)
wire _io_out_3_0_bits_WIRE_1 : UInt<2>
connect _io_out_3_0_bits_WIRE_1, _io_out_3_0_bits_T_13
connect _io_out_3_0_bits_WIRE.virt_channel_id, _io_out_3_0_bits_WIRE_1
wire _io_out_3_0_bits_WIRE_2 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _io_out_3_0_bits_T_14 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_15 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_16 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_17 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_18 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_19 = or(_io_out_3_0_bits_T_14, _io_out_3_0_bits_T_15)
node _io_out_3_0_bits_T_20 = or(_io_out_3_0_bits_T_19, _io_out_3_0_bits_T_16)
node _io_out_3_0_bits_T_21 = or(_io_out_3_0_bits_T_20, _io_out_3_0_bits_T_17)
node _io_out_3_0_bits_T_22 = or(_io_out_3_0_bits_T_21, _io_out_3_0_bits_T_18)
wire _io_out_3_0_bits_WIRE_3 : UInt<2>
connect _io_out_3_0_bits_WIRE_3, _io_out_3_0_bits_T_22
connect _io_out_3_0_bits_WIRE_2.egress_node_id, _io_out_3_0_bits_WIRE_3
node _io_out_3_0_bits_T_23 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_3_0_bits_T_24 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_3_0_bits_T_25 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_3_0_bits_T_26 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_3_0_bits_T_27 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_3_0_bits_T_28 = or(_io_out_3_0_bits_T_23, _io_out_3_0_bits_T_24)
node _io_out_3_0_bits_T_29 = or(_io_out_3_0_bits_T_28, _io_out_3_0_bits_T_25)
node _io_out_3_0_bits_T_30 = or(_io_out_3_0_bits_T_29, _io_out_3_0_bits_T_26)
node _io_out_3_0_bits_T_31 = or(_io_out_3_0_bits_T_30, _io_out_3_0_bits_T_27)
wire _io_out_3_0_bits_WIRE_4 : UInt<4>
connect _io_out_3_0_bits_WIRE_4, _io_out_3_0_bits_T_31
connect _io_out_3_0_bits_WIRE_2.egress_node, _io_out_3_0_bits_WIRE_4
node _io_out_3_0_bits_T_32 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_33 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_34 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_35 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_36 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_37 = or(_io_out_3_0_bits_T_32, _io_out_3_0_bits_T_33)
node _io_out_3_0_bits_T_38 = or(_io_out_3_0_bits_T_37, _io_out_3_0_bits_T_34)
node _io_out_3_0_bits_T_39 = or(_io_out_3_0_bits_T_38, _io_out_3_0_bits_T_35)
node _io_out_3_0_bits_T_40 = or(_io_out_3_0_bits_T_39, _io_out_3_0_bits_T_36)
wire _io_out_3_0_bits_WIRE_5 : UInt<3>
connect _io_out_3_0_bits_WIRE_5, _io_out_3_0_bits_T_40
connect _io_out_3_0_bits_WIRE_2.ingress_node_id, _io_out_3_0_bits_WIRE_5
node _io_out_3_0_bits_T_41 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_3_0_bits_T_42 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_3_0_bits_T_43 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_3_0_bits_T_44 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_3_0_bits_T_45 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_3_0_bits_T_46 = or(_io_out_3_0_bits_T_41, _io_out_3_0_bits_T_42)
node _io_out_3_0_bits_T_47 = or(_io_out_3_0_bits_T_46, _io_out_3_0_bits_T_43)
node _io_out_3_0_bits_T_48 = or(_io_out_3_0_bits_T_47, _io_out_3_0_bits_T_44)
node _io_out_3_0_bits_T_49 = or(_io_out_3_0_bits_T_48, _io_out_3_0_bits_T_45)
wire _io_out_3_0_bits_WIRE_6 : UInt<4>
connect _io_out_3_0_bits_WIRE_6, _io_out_3_0_bits_T_49
connect _io_out_3_0_bits_WIRE_2.ingress_node, _io_out_3_0_bits_WIRE_6
node _io_out_3_0_bits_T_50 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_51 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_52 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_53 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_54 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_55 = or(_io_out_3_0_bits_T_50, _io_out_3_0_bits_T_51)
node _io_out_3_0_bits_T_56 = or(_io_out_3_0_bits_T_55, _io_out_3_0_bits_T_52)
node _io_out_3_0_bits_T_57 = or(_io_out_3_0_bits_T_56, _io_out_3_0_bits_T_53)
node _io_out_3_0_bits_T_58 = or(_io_out_3_0_bits_T_57, _io_out_3_0_bits_T_54)
wire _io_out_3_0_bits_WIRE_7 : UInt<2>
connect _io_out_3_0_bits_WIRE_7, _io_out_3_0_bits_T_58
connect _io_out_3_0_bits_WIRE_2.vnet_id, _io_out_3_0_bits_WIRE_7
connect _io_out_3_0_bits_WIRE.flow, _io_out_3_0_bits_WIRE_2
node _io_out_3_0_bits_T_59 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0))
node _io_out_3_0_bits_T_60 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0))
node _io_out_3_0_bits_T_61 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0))
node _io_out_3_0_bits_T_62 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.payload, UInt<1>(0h0))
node _io_out_3_0_bits_T_63 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.payload, UInt<1>(0h0))
node _io_out_3_0_bits_T_64 = or(_io_out_3_0_bits_T_59, _io_out_3_0_bits_T_60)
node _io_out_3_0_bits_T_65 = or(_io_out_3_0_bits_T_64, _io_out_3_0_bits_T_61)
node _io_out_3_0_bits_T_66 = or(_io_out_3_0_bits_T_65, _io_out_3_0_bits_T_62)
node _io_out_3_0_bits_T_67 = or(_io_out_3_0_bits_T_66, _io_out_3_0_bits_T_63)
wire _io_out_3_0_bits_WIRE_8 : UInt<145>
connect _io_out_3_0_bits_WIRE_8, _io_out_3_0_bits_T_67
connect _io_out_3_0_bits_WIRE.payload, _io_out_3_0_bits_WIRE_8
node _io_out_3_0_bits_T_68 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0))
node _io_out_3_0_bits_T_69 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0))
node _io_out_3_0_bits_T_70 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0))
node _io_out_3_0_bits_T_71 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.tail, UInt<1>(0h0))
node _io_out_3_0_bits_T_72 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.tail, UInt<1>(0h0))
node _io_out_3_0_bits_T_73 = or(_io_out_3_0_bits_T_68, _io_out_3_0_bits_T_69)
node _io_out_3_0_bits_T_74 = or(_io_out_3_0_bits_T_73, _io_out_3_0_bits_T_70)
node _io_out_3_0_bits_T_75 = or(_io_out_3_0_bits_T_74, _io_out_3_0_bits_T_71)
node _io_out_3_0_bits_T_76 = or(_io_out_3_0_bits_T_75, _io_out_3_0_bits_T_72)
wire _io_out_3_0_bits_WIRE_9 : UInt<1>
connect _io_out_3_0_bits_WIRE_9, _io_out_3_0_bits_T_76
connect _io_out_3_0_bits_WIRE.tail, _io_out_3_0_bits_WIRE_9
node _io_out_3_0_bits_T_77 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0))
node _io_out_3_0_bits_T_78 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0))
node _io_out_3_0_bits_T_79 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0))
node _io_out_3_0_bits_T_80 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.head, UInt<1>(0h0))
node _io_out_3_0_bits_T_81 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.head, UInt<1>(0h0))
node _io_out_3_0_bits_T_82 = or(_io_out_3_0_bits_T_77, _io_out_3_0_bits_T_78)
node _io_out_3_0_bits_T_83 = or(_io_out_3_0_bits_T_82, _io_out_3_0_bits_T_79)
node _io_out_3_0_bits_T_84 = or(_io_out_3_0_bits_T_83, _io_out_3_0_bits_T_80)
node _io_out_3_0_bits_T_85 = or(_io_out_3_0_bits_T_84, _io_out_3_0_bits_T_81)
wire _io_out_3_0_bits_WIRE_10 : UInt<1>
connect _io_out_3_0_bits_WIRE_10, _io_out_3_0_bits_T_85
connect _io_out_3_0_bits_WIRE.head, _io_out_3_0_bits_WIRE_10
connect io.out.`3`[0].bits, _io_out_3_0_bits_WIRE
node _io_out_3_0_bits_virt_channel_id_T = bits(sel_flat_3, 0, 0)
node _io_out_3_0_bits_virt_channel_id_T_1 = bits(sel_flat_3, 1, 1)
node _io_out_3_0_bits_virt_channel_id_T_2 = bits(sel_flat_3, 2, 2)
node _io_out_3_0_bits_virt_channel_id_T_3 = bits(sel_flat_3, 3, 3)
node _io_out_3_0_bits_virt_channel_id_T_4 = bits(sel_flat_3, 4, 4)
node _io_out_3_0_bits_virt_channel_id_T_5 = mux(_io_out_3_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_3_0_bits_virt_channel_id_T_6 = mux(_io_out_3_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_3_0_bits_virt_channel_id_T_7 = mux(_io_out_3_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_3_0_bits_virt_channel_id_T_8 = mux(_io_out_3_0_bits_virt_channel_id_T_3, in_flat[3].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_3_0_bits_virt_channel_id_T_9 = mux(_io_out_3_0_bits_virt_channel_id_T_4, in_flat[4].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_3_0_bits_virt_channel_id_T_10 = or(_io_out_3_0_bits_virt_channel_id_T_5, _io_out_3_0_bits_virt_channel_id_T_6)
node _io_out_3_0_bits_virt_channel_id_T_11 = or(_io_out_3_0_bits_virt_channel_id_T_10, _io_out_3_0_bits_virt_channel_id_T_7)
node _io_out_3_0_bits_virt_channel_id_T_12 = or(_io_out_3_0_bits_virt_channel_id_T_11, _io_out_3_0_bits_virt_channel_id_T_8)
node _io_out_3_0_bits_virt_channel_id_T_13 = or(_io_out_3_0_bits_virt_channel_id_T_12, _io_out_3_0_bits_virt_channel_id_T_9)
wire _io_out_3_0_bits_virt_channel_id_WIRE : UInt<2>
connect _io_out_3_0_bits_virt_channel_id_WIRE, _io_out_3_0_bits_virt_channel_id_T_13
connect io.out.`3`[0].bits.virt_channel_id, _io_out_3_0_bits_virt_channel_id_WIRE | module Switch_1( // @[Switch.scala:16:7]
input clock, // @[Switch.scala:16:7]
input reset, // @[Switch.scala:16:7]
input io_in_4_0_valid, // @[Switch.scala:27:14]
input io_in_4_0_bits_flit_head, // @[Switch.scala:27:14]
input io_in_4_0_bits_flit_tail, // @[Switch.scala:27:14]
input [144:0] io_in_4_0_bits_flit_payload, // @[Switch.scala:27:14]
input [1:0] io_in_4_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14]
input [3:0] io_in_4_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14]
input [2:0] io_in_4_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14]
input [3:0] io_in_4_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14]
input [1:0] io_in_4_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14]
input [1:0] io_in_4_0_bits_out_virt_channel, // @[Switch.scala:27:14]
input io_in_3_0_valid, // @[Switch.scala:27:14]
input io_in_3_0_bits_flit_head, // @[Switch.scala:27:14]
input io_in_3_0_bits_flit_tail, // @[Switch.scala:27:14]
input [144:0] io_in_3_0_bits_flit_payload, // @[Switch.scala:27:14]
input [1:0] io_in_3_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14]
input [3:0] io_in_3_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14]
input [2:0] io_in_3_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14]
input [3:0] io_in_3_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14]
input [1:0] io_in_3_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14]
input [1:0] io_in_3_0_bits_out_virt_channel, // @[Switch.scala:27:14]
input io_in_2_0_valid, // @[Switch.scala:27:14]
input io_in_2_0_bits_flit_head, // @[Switch.scala:27:14]
input io_in_2_0_bits_flit_tail, // @[Switch.scala:27:14]
input [144:0] io_in_2_0_bits_flit_payload, // @[Switch.scala:27:14]
input [1:0] io_in_2_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14]
input [3:0] io_in_2_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14]
input [2:0] io_in_2_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14]
input [3:0] io_in_2_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14]
input [1:0] io_in_2_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14]
input [1:0] io_in_2_0_bits_out_virt_channel, // @[Switch.scala:27:14]
input io_in_1_0_valid, // @[Switch.scala:27:14]
input io_in_1_0_bits_flit_head, // @[Switch.scala:27:14]
input io_in_1_0_bits_flit_tail, // @[Switch.scala:27:14]
input [144:0] io_in_1_0_bits_flit_payload, // @[Switch.scala:27:14]
input [1:0] io_in_1_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14]
input [3:0] io_in_1_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14]
input [2:0] io_in_1_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14]
input [3:0] io_in_1_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14]
input [1:0] io_in_1_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14]
input [1:0] io_in_1_0_bits_out_virt_channel, // @[Switch.scala:27:14]
input io_in_0_0_valid, // @[Switch.scala:27:14]
input io_in_0_0_bits_flit_head, // @[Switch.scala:27:14]
input io_in_0_0_bits_flit_tail, // @[Switch.scala:27:14]
input [144:0] io_in_0_0_bits_flit_payload, // @[Switch.scala:27:14]
input [1:0] io_in_0_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14]
input [3:0] io_in_0_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14]
input [2:0] io_in_0_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14]
input [3:0] io_in_0_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14]
input [1:0] io_in_0_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14]
input [1:0] io_in_0_0_bits_out_virt_channel, // @[Switch.scala:27:14]
output io_out_3_0_valid, // @[Switch.scala:27:14]
output io_out_3_0_bits_head, // @[Switch.scala:27:14]
output io_out_3_0_bits_tail, // @[Switch.scala:27:14]
output [144:0] io_out_3_0_bits_payload, // @[Switch.scala:27:14]
output [3:0] io_out_3_0_bits_flow_ingress_node, // @[Switch.scala:27:14]
output [2:0] io_out_3_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14]
output io_out_2_0_valid, // @[Switch.scala:27:14]
output io_out_2_0_bits_head, // @[Switch.scala:27:14]
output io_out_2_0_bits_tail, // @[Switch.scala:27:14]
output [144:0] io_out_2_0_bits_payload, // @[Switch.scala:27:14]
output [1:0] io_out_2_0_bits_flow_vnet_id, // @[Switch.scala:27:14]
output [3:0] io_out_2_0_bits_flow_ingress_node, // @[Switch.scala:27:14]
output [2:0] io_out_2_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14]
output [3:0] io_out_2_0_bits_flow_egress_node, // @[Switch.scala:27:14]
output [1:0] io_out_2_0_bits_flow_egress_node_id, // @[Switch.scala:27:14]
output [1:0] io_out_2_0_bits_virt_channel_id, // @[Switch.scala:27:14]
output io_out_1_0_valid, // @[Switch.scala:27:14]
output io_out_1_0_bits_head, // @[Switch.scala:27:14]
output io_out_1_0_bits_tail, // @[Switch.scala:27:14]
output [144:0] io_out_1_0_bits_payload, // @[Switch.scala:27:14]
output [1:0] io_out_1_0_bits_flow_vnet_id, // @[Switch.scala:27:14]
output [3:0] io_out_1_0_bits_flow_ingress_node, // @[Switch.scala:27:14]
output [2:0] io_out_1_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14]
output [3:0] io_out_1_0_bits_flow_egress_node, // @[Switch.scala:27:14]
output [1:0] io_out_1_0_bits_flow_egress_node_id, // @[Switch.scala:27:14]
output [1:0] io_out_1_0_bits_virt_channel_id, // @[Switch.scala:27:14]
output io_out_0_0_valid, // @[Switch.scala:27:14]
output io_out_0_0_bits_head, // @[Switch.scala:27:14]
output io_out_0_0_bits_tail, // @[Switch.scala:27:14]
output [144:0] io_out_0_0_bits_payload, // @[Switch.scala:27:14]
output [1:0] io_out_0_0_bits_flow_vnet_id, // @[Switch.scala:27:14]
output [3:0] io_out_0_0_bits_flow_ingress_node, // @[Switch.scala:27:14]
output [2:0] io_out_0_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14]
output [3:0] io_out_0_0_bits_flow_egress_node, // @[Switch.scala:27:14]
output [1:0] io_out_0_0_bits_flow_egress_node_id, // @[Switch.scala:27:14]
output [1:0] io_out_0_0_bits_virt_channel_id, // @[Switch.scala:27:14]
input io_sel_3_0_4_0, // @[Switch.scala:27:14]
input io_sel_3_0_3_0, // @[Switch.scala:27:14]
input io_sel_3_0_2_0, // @[Switch.scala:27:14]
input io_sel_3_0_1_0, // @[Switch.scala:27:14]
input io_sel_3_0_0_0, // @[Switch.scala:27:14]
input io_sel_2_0_4_0, // @[Switch.scala:27:14]
input io_sel_2_0_3_0, // @[Switch.scala:27:14]
input io_sel_2_0_2_0, // @[Switch.scala:27:14]
input io_sel_2_0_1_0, // @[Switch.scala:27:14]
input io_sel_2_0_0_0, // @[Switch.scala:27:14]
input io_sel_1_0_4_0, // @[Switch.scala:27:14]
input io_sel_1_0_3_0, // @[Switch.scala:27:14]
input io_sel_1_0_2_0, // @[Switch.scala:27:14]
input io_sel_1_0_1_0, // @[Switch.scala:27:14]
input io_sel_1_0_0_0, // @[Switch.scala:27:14]
input io_sel_0_0_4_0, // @[Switch.scala:27:14]
input io_sel_0_0_3_0, // @[Switch.scala:27:14]
input io_sel_0_0_2_0, // @[Switch.scala:27:14]
input io_sel_0_0_1_0, // @[Switch.scala:27:14]
input io_sel_0_0_0_0 // @[Switch.scala:27:14]
); |
Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i1_e8_s24_6 :
output io : { flip signedIn : UInt<1>, flip in : UInt<1>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node _intAsRawFloat_sign_T = bits(io.in, 0, 0)
node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T)
node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in)
node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1)
node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in)
node _intAsRawFloat_extAbsIn_T = cat(UInt<2>(0h0), intAsRawFloat_absIn)
node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 1, 0)
node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0)
node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1)
node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<1>(0h0), UInt<1>(0h1))
node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist)
node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 1, 1)
wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>}
connect intAsRawFloat.isNaN, UInt<1>(0h0)
connect intAsRawFloat.isInf, UInt<1>(0h0)
node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 0, 0)
node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0))
connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1
connect intAsRawFloat.sign, intAsRawFloat_sign
node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 0, 0)
node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T)
node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1)
node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2)
connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3
connect intAsRawFloat.sig, intAsRawFloat_sig
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_6
connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0)
connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig
connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp
connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign
connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module INToRecFN_i1_e8_s24_6(); // @[INToRecFN.scala:43:7]
wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31]
wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44]
wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22]
wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33]
wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72]
wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72]
wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20]
wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20]
wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15]
wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15]
wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15]
wire io_in = 1'h1; // @[Mux.scala:50:70]
wire io_detectTininess = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70]
wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70]
wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70]
wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70]
wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7]
wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29]
wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52]
wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23]
wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36]
RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_6 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Router_28 :
input clock : Clock
input reset : Reset
output auto : { debug_out : { va_stall : UInt[2], sa_stall : UInt[2]}, source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}}
wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}
invalidate destNodesIn.vc_free
invalidate destNodesIn.credit_return
invalidate destNodesIn.flit[0].bits.virt_channel_id
invalidate destNodesIn.flit[0].bits.flow.egress_node_id
invalidate destNodesIn.flit[0].bits.flow.egress_node
invalidate destNodesIn.flit[0].bits.flow.ingress_node_id
invalidate destNodesIn.flit[0].bits.flow.ingress_node
invalidate destNodesIn.flit[0].bits.flow.vnet_id
invalidate destNodesIn.flit[0].bits.payload
invalidate destNodesIn.flit[0].bits.tail
invalidate destNodesIn.flit[0].bits.head
invalidate destNodesIn.flit[0].valid
inst monitor of NoCMonitor_70
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.vc_free, destNodesIn.vc_free
connect monitor.io.in.credit_return, destNodesIn.credit_return
connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id
connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id
connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node
connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id
connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node
connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id
connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload
connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail
connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head
connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid
wire destNodesIn_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}
invalidate destNodesIn_1.vc_free
invalidate destNodesIn_1.credit_return
invalidate destNodesIn_1.flit[0].bits.virt_channel_id
invalidate destNodesIn_1.flit[0].bits.flow.egress_node_id
invalidate destNodesIn_1.flit[0].bits.flow.egress_node
invalidate destNodesIn_1.flit[0].bits.flow.ingress_node_id
invalidate destNodesIn_1.flit[0].bits.flow.ingress_node
invalidate destNodesIn_1.flit[0].bits.flow.vnet_id
invalidate destNodesIn_1.flit[0].bits.payload
invalidate destNodesIn_1.flit[0].bits.tail
invalidate destNodesIn_1.flit[0].bits.head
invalidate destNodesIn_1.flit[0].valid
inst monitor_1 of NoCMonitor_71
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.vc_free, destNodesIn_1.vc_free
connect monitor_1.io.in.credit_return, destNodesIn_1.credit_return
connect monitor_1.io.in.flit[0].bits.virt_channel_id, destNodesIn_1.flit[0].bits.virt_channel_id
connect monitor_1.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_1.flit[0].bits.flow.egress_node_id
connect monitor_1.io.in.flit[0].bits.flow.egress_node, destNodesIn_1.flit[0].bits.flow.egress_node
connect monitor_1.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_1.flit[0].bits.flow.ingress_node_id
connect monitor_1.io.in.flit[0].bits.flow.ingress_node, destNodesIn_1.flit[0].bits.flow.ingress_node
connect monitor_1.io.in.flit[0].bits.flow.vnet_id, destNodesIn_1.flit[0].bits.flow.vnet_id
connect monitor_1.io.in.flit[0].bits.payload, destNodesIn_1.flit[0].bits.payload
connect monitor_1.io.in.flit[0].bits.tail, destNodesIn_1.flit[0].bits.tail
connect monitor_1.io.in.flit[0].bits.head, destNodesIn_1.flit[0].bits.head
connect monitor_1.io.in.flit[0].valid, destNodesIn_1.flit[0].valid
wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}
invalidate sourceNodesOut.vc_free
invalidate sourceNodesOut.credit_return
invalidate sourceNodesOut.flit[0].bits.virt_channel_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node
invalidate sourceNodesOut.flit[0].bits.flow.vnet_id
invalidate sourceNodesOut.flit[0].bits.payload
invalidate sourceNodesOut.flit[0].bits.tail
invalidate sourceNodesOut.flit[0].bits.head
invalidate sourceNodesOut.flit[0].valid
wire sourceNodesOut_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}
invalidate sourceNodesOut_1.vc_free
invalidate sourceNodesOut_1.credit_return
invalidate sourceNodesOut_1.flit[0].bits.virt_channel_id
invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node_id
invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node
invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node_id
invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node
invalidate sourceNodesOut_1.flit[0].bits.flow.vnet_id
invalidate sourceNodesOut_1.flit[0].bits.payload
invalidate sourceNodesOut_1.flit[0].bits.tail
invalidate sourceNodesOut_1.flit[0].bits.head
invalidate sourceNodesOut_1.flit[0].valid
wire debugNodeOut : { va_stall : UInt[2], sa_stall : UInt[2]}
invalidate debugNodeOut.sa_stall[0]
invalidate debugNodeOut.sa_stall[1]
invalidate debugNodeOut.va_stall[0]
invalidate debugNodeOut.va_stall[1]
connect destNodesIn, auto.dest_nodes_in_0
connect destNodesIn_1, auto.dest_nodes_in_1
connect auto.source_nodes_out_0, sourceNodesOut
connect auto.source_nodes_out_1, sourceNodesOut_1
connect auto.debug_out, debugNodeOut
inst input_unit_0_from_27 of InputUnit_70
connect input_unit_0_from_27.clock, clock
connect input_unit_0_from_27.reset, reset
inst input_unit_1_from_30 of InputUnit_71
connect input_unit_1_from_30.clock, clock
connect input_unit_1_from_30.reset, reset
inst output_unit_0_to_27 of OutputUnit_70
connect output_unit_0_to_27.clock, clock
connect output_unit_0_to_27.reset, reset
inst output_unit_1_to_30 of OutputUnit_71
connect output_unit_1_to_30.clock, clock
connect output_unit_1_to_30.reset, reset
inst switch of Switch_28
connect switch.clock, clock
connect switch.reset, reset
inst switch_allocator of SwitchAllocator_28
connect switch_allocator.clock, clock
connect switch_allocator.reset, reset
inst vc_allocator of RotatingSingleVCAllocator_28
connect vc_allocator.clock, clock
connect vc_allocator.reset, reset
inst route_computer of RouteComputer_28
connect route_computer.clock, clock
connect route_computer.reset, reset
node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid)
node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid)
node _fires_count_T_2 = add(_fires_count_T, _fires_count_T_1)
node _fires_count_T_3 = bits(_fires_count_T_2, 1, 0)
wire fires_count : UInt
connect fires_count, _fires_count_T_3
connect input_unit_0_from_27.io.in, destNodesIn
connect input_unit_1_from_30.io.in, destNodesIn_1
connect output_unit_0_to_27.io.out.vc_free, sourceNodesOut.vc_free
connect output_unit_0_to_27.io.out.credit_return, sourceNodesOut.credit_return
connect sourceNodesOut.flit, output_unit_0_to_27.io.out.flit
connect output_unit_1_to_30.io.out.vc_free, sourceNodesOut_1.vc_free
connect output_unit_1_to_30.io.out.credit_return, sourceNodesOut_1.credit_return
connect sourceNodesOut_1.flit, output_unit_1_to_30.io.out.flit
connect route_computer.io.req.`0`, input_unit_0_from_27.io.router_req
connect route_computer.io.req.`1`, input_unit_1_from_30.io.router_req
connect input_unit_0_from_27.io.router_resp, route_computer.io.resp.`0`
connect input_unit_1_from_30.io.router_resp, route_computer.io.resp.`1`
connect vc_allocator.io.req.`0`, input_unit_0_from_27.io.vcalloc_req
connect vc_allocator.io.req.`1`, input_unit_1_from_30.io.vcalloc_req
connect input_unit_0_from_27.io.vcalloc_resp, vc_allocator.io.resp.`0`
connect input_unit_1_from_30.io.vcalloc_resp, vc_allocator.io.resp.`1`
connect output_unit_0_to_27.io.allocs, vc_allocator.io.out_allocs.`0`
connect output_unit_1_to_30.io.allocs, vc_allocator.io.out_allocs.`1`
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_27.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_27.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_27.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_27.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_27.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_27.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_27.io.channel_status[1].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_27.io.channel_status[1].flow.egress_node
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_27.io.channel_status[1].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_27.io.channel_status[1].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_27.io.channel_status[1].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_27.io.channel_status[1].occupied
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_27.io.channel_status[2].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_27.io.channel_status[2].flow.egress_node
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_27.io.channel_status[2].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_27.io.channel_status[2].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_27.io.channel_status[2].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_27.io.channel_status[2].occupied
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_27.io.channel_status[3].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_27.io.channel_status[3].flow.egress_node
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_27.io.channel_status[3].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_27.io.channel_status[3].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_27.io.channel_status[3].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_27.io.channel_status[3].occupied
connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_27.io.channel_status[4].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_27.io.channel_status[4].flow.egress_node
connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_27.io.channel_status[4].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_27.io.channel_status[4].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_27.io.channel_status[4].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_27.io.channel_status[4].occupied
connect vc_allocator.io.channel_status.`0`[5].flow.egress_node_id, output_unit_0_to_27.io.channel_status[5].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[5].flow.egress_node, output_unit_0_to_27.io.channel_status[5].flow.egress_node
connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node_id, output_unit_0_to_27.io.channel_status[5].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node, output_unit_0_to_27.io.channel_status[5].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[5].flow.vnet_id, output_unit_0_to_27.io.channel_status[5].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[5].occupied, output_unit_0_to_27.io.channel_status[5].occupied
connect vc_allocator.io.channel_status.`0`[6].flow.egress_node_id, output_unit_0_to_27.io.channel_status[6].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[6].flow.egress_node, output_unit_0_to_27.io.channel_status[6].flow.egress_node
connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node_id, output_unit_0_to_27.io.channel_status[6].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node, output_unit_0_to_27.io.channel_status[6].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[6].flow.vnet_id, output_unit_0_to_27.io.channel_status[6].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[6].occupied, output_unit_0_to_27.io.channel_status[6].occupied
connect vc_allocator.io.channel_status.`0`[7].flow.egress_node_id, output_unit_0_to_27.io.channel_status[7].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[7].flow.egress_node, output_unit_0_to_27.io.channel_status[7].flow.egress_node
connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node_id, output_unit_0_to_27.io.channel_status[7].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node, output_unit_0_to_27.io.channel_status[7].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[7].flow.vnet_id, output_unit_0_to_27.io.channel_status[7].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[7].occupied, output_unit_0_to_27.io.channel_status[7].occupied
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, output_unit_1_to_30.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, output_unit_1_to_30.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, output_unit_1_to_30.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, output_unit_1_to_30.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, output_unit_1_to_30.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[0].occupied, output_unit_1_to_30.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`1`[1].flow.egress_node_id, output_unit_1_to_30.io.channel_status[1].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[1].flow.egress_node, output_unit_1_to_30.io.channel_status[1].flow.egress_node
connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node_id, output_unit_1_to_30.io.channel_status[1].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node, output_unit_1_to_30.io.channel_status[1].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[1].flow.vnet_id, output_unit_1_to_30.io.channel_status[1].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[1].occupied, output_unit_1_to_30.io.channel_status[1].occupied
connect vc_allocator.io.channel_status.`1`[2].flow.egress_node_id, output_unit_1_to_30.io.channel_status[2].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[2].flow.egress_node, output_unit_1_to_30.io.channel_status[2].flow.egress_node
connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node_id, output_unit_1_to_30.io.channel_status[2].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node, output_unit_1_to_30.io.channel_status[2].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[2].flow.vnet_id, output_unit_1_to_30.io.channel_status[2].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[2].occupied, output_unit_1_to_30.io.channel_status[2].occupied
connect vc_allocator.io.channel_status.`1`[3].flow.egress_node_id, output_unit_1_to_30.io.channel_status[3].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[3].flow.egress_node, output_unit_1_to_30.io.channel_status[3].flow.egress_node
connect vc_allocator.io.channel_status.`1`[3].flow.ingress_node_id, output_unit_1_to_30.io.channel_status[3].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[3].flow.ingress_node, output_unit_1_to_30.io.channel_status[3].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[3].flow.vnet_id, output_unit_1_to_30.io.channel_status[3].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[3].occupied, output_unit_1_to_30.io.channel_status[3].occupied
connect vc_allocator.io.channel_status.`1`[4].flow.egress_node_id, output_unit_1_to_30.io.channel_status[4].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[4].flow.egress_node, output_unit_1_to_30.io.channel_status[4].flow.egress_node
connect vc_allocator.io.channel_status.`1`[4].flow.ingress_node_id, output_unit_1_to_30.io.channel_status[4].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[4].flow.ingress_node, output_unit_1_to_30.io.channel_status[4].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[4].flow.vnet_id, output_unit_1_to_30.io.channel_status[4].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[4].occupied, output_unit_1_to_30.io.channel_status[4].occupied
connect vc_allocator.io.channel_status.`1`[5].flow.egress_node_id, output_unit_1_to_30.io.channel_status[5].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[5].flow.egress_node, output_unit_1_to_30.io.channel_status[5].flow.egress_node
connect vc_allocator.io.channel_status.`1`[5].flow.ingress_node_id, output_unit_1_to_30.io.channel_status[5].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[5].flow.ingress_node, output_unit_1_to_30.io.channel_status[5].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[5].flow.vnet_id, output_unit_1_to_30.io.channel_status[5].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[5].occupied, output_unit_1_to_30.io.channel_status[5].occupied
connect vc_allocator.io.channel_status.`1`[6].flow.egress_node_id, output_unit_1_to_30.io.channel_status[6].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[6].flow.egress_node, output_unit_1_to_30.io.channel_status[6].flow.egress_node
connect vc_allocator.io.channel_status.`1`[6].flow.ingress_node_id, output_unit_1_to_30.io.channel_status[6].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[6].flow.ingress_node, output_unit_1_to_30.io.channel_status[6].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[6].flow.vnet_id, output_unit_1_to_30.io.channel_status[6].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[6].occupied, output_unit_1_to_30.io.channel_status[6].occupied
connect vc_allocator.io.channel_status.`1`[7].flow.egress_node_id, output_unit_1_to_30.io.channel_status[7].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[7].flow.egress_node, output_unit_1_to_30.io.channel_status[7].flow.egress_node
connect vc_allocator.io.channel_status.`1`[7].flow.ingress_node_id, output_unit_1_to_30.io.channel_status[7].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[7].flow.ingress_node, output_unit_1_to_30.io.channel_status[7].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[7].flow.vnet_id, output_unit_1_to_30.io.channel_status[7].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[7].occupied, output_unit_1_to_30.io.channel_status[7].occupied
connect input_unit_0_from_27.io.out_credit_available.`0`[0], output_unit_0_to_27.io.credit_available[0]
connect input_unit_0_from_27.io.out_credit_available.`0`[1], output_unit_0_to_27.io.credit_available[1]
connect input_unit_0_from_27.io.out_credit_available.`0`[2], output_unit_0_to_27.io.credit_available[2]
connect input_unit_0_from_27.io.out_credit_available.`0`[3], output_unit_0_to_27.io.credit_available[3]
connect input_unit_0_from_27.io.out_credit_available.`0`[4], output_unit_0_to_27.io.credit_available[4]
connect input_unit_0_from_27.io.out_credit_available.`0`[5], output_unit_0_to_27.io.credit_available[5]
connect input_unit_0_from_27.io.out_credit_available.`0`[6], output_unit_0_to_27.io.credit_available[6]
connect input_unit_0_from_27.io.out_credit_available.`0`[7], output_unit_0_to_27.io.credit_available[7]
connect input_unit_0_from_27.io.out_credit_available.`1`[0], output_unit_1_to_30.io.credit_available[0]
connect input_unit_0_from_27.io.out_credit_available.`1`[1], output_unit_1_to_30.io.credit_available[1]
connect input_unit_0_from_27.io.out_credit_available.`1`[2], output_unit_1_to_30.io.credit_available[2]
connect input_unit_0_from_27.io.out_credit_available.`1`[3], output_unit_1_to_30.io.credit_available[3]
connect input_unit_0_from_27.io.out_credit_available.`1`[4], output_unit_1_to_30.io.credit_available[4]
connect input_unit_0_from_27.io.out_credit_available.`1`[5], output_unit_1_to_30.io.credit_available[5]
connect input_unit_0_from_27.io.out_credit_available.`1`[6], output_unit_1_to_30.io.credit_available[6]
connect input_unit_0_from_27.io.out_credit_available.`1`[7], output_unit_1_to_30.io.credit_available[7]
connect input_unit_1_from_30.io.out_credit_available.`0`[0], output_unit_0_to_27.io.credit_available[0]
connect input_unit_1_from_30.io.out_credit_available.`0`[1], output_unit_0_to_27.io.credit_available[1]
connect input_unit_1_from_30.io.out_credit_available.`0`[2], output_unit_0_to_27.io.credit_available[2]
connect input_unit_1_from_30.io.out_credit_available.`0`[3], output_unit_0_to_27.io.credit_available[3]
connect input_unit_1_from_30.io.out_credit_available.`0`[4], output_unit_0_to_27.io.credit_available[4]
connect input_unit_1_from_30.io.out_credit_available.`0`[5], output_unit_0_to_27.io.credit_available[5]
connect input_unit_1_from_30.io.out_credit_available.`0`[6], output_unit_0_to_27.io.credit_available[6]
connect input_unit_1_from_30.io.out_credit_available.`0`[7], output_unit_0_to_27.io.credit_available[7]
connect input_unit_1_from_30.io.out_credit_available.`1`[0], output_unit_1_to_30.io.credit_available[0]
connect input_unit_1_from_30.io.out_credit_available.`1`[1], output_unit_1_to_30.io.credit_available[1]
connect input_unit_1_from_30.io.out_credit_available.`1`[2], output_unit_1_to_30.io.credit_available[2]
connect input_unit_1_from_30.io.out_credit_available.`1`[3], output_unit_1_to_30.io.credit_available[3]
connect input_unit_1_from_30.io.out_credit_available.`1`[4], output_unit_1_to_30.io.credit_available[4]
connect input_unit_1_from_30.io.out_credit_available.`1`[5], output_unit_1_to_30.io.credit_available[5]
connect input_unit_1_from_30.io.out_credit_available.`1`[6], output_unit_1_to_30.io.credit_available[6]
connect input_unit_1_from_30.io.out_credit_available.`1`[7], output_unit_1_to_30.io.credit_available[7]
connect switch_allocator.io.req.`0`[0], input_unit_0_from_27.io.salloc_req[0]
connect switch_allocator.io.req.`1`[0], input_unit_1_from_30.io.salloc_req[0]
connect output_unit_0_to_27.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail
connect output_unit_0_to_27.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc
connect output_unit_0_to_27.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail
connect output_unit_0_to_27.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc
connect output_unit_0_to_27.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail
connect output_unit_0_to_27.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc
connect output_unit_0_to_27.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail
connect output_unit_0_to_27.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc
connect output_unit_0_to_27.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail
connect output_unit_0_to_27.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc
connect output_unit_0_to_27.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`0`[5].tail
connect output_unit_0_to_27.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`0`[5].alloc
connect output_unit_0_to_27.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`0`[6].tail
connect output_unit_0_to_27.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`0`[6].alloc
connect output_unit_0_to_27.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`0`[7].tail
connect output_unit_0_to_27.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`0`[7].alloc
connect output_unit_1_to_30.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail
connect output_unit_1_to_30.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc
connect output_unit_1_to_30.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`1`[1].tail
connect output_unit_1_to_30.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`1`[1].alloc
connect output_unit_1_to_30.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`1`[2].tail
connect output_unit_1_to_30.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`1`[2].alloc
connect output_unit_1_to_30.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`1`[3].tail
connect output_unit_1_to_30.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`1`[3].alloc
connect output_unit_1_to_30.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`1`[4].tail
connect output_unit_1_to_30.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`1`[4].alloc
connect output_unit_1_to_30.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`1`[5].tail
connect output_unit_1_to_30.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`1`[5].alloc
connect output_unit_1_to_30.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`1`[6].tail
connect output_unit_1_to_30.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`1`[6].alloc
connect output_unit_1_to_30.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`1`[7].tail
connect output_unit_1_to_30.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`1`[7].alloc
connect switch.io.in.`0`[0], input_unit_0_from_27.io.out[0]
connect switch.io.in.`1`[0], input_unit_1_from_30.io.out[0]
connect output_unit_0_to_27.io.in, switch.io.out.`0`
connect output_unit_1_to_30.io.in, switch.io.out.`1`
reg REG : { `1` : { `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock
connect REG, switch_allocator.io.switch_sel
connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0]
connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0]
connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0]
connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0]
connect input_unit_0_from_27.io.block, UInt<1>(0h0)
connect input_unit_1_from_30.io.block, UInt<1>(0h0)
connect debugNodeOut.va_stall[0], input_unit_0_from_27.io.debug.va_stall
connect debugNodeOut.va_stall[1], input_unit_1_from_30.io.debug.va_stall
connect debugNodeOut.sa_stall[0], input_unit_0_from_27.io.debug.sa_stall
connect debugNodeOut.sa_stall[1], input_unit_1_from_30.io.debug.sa_stall
regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1))
node _debug_tsc_T_1 = tail(_debug_tsc_T, 1)
connect debug_tsc, _debug_tsc_T_1
regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_sample_T = add(debug_sample, UInt<1>(0h1))
node _debug_sample_T_1 = tail(_debug_sample_T, 1)
connect debug_sample, _debug_sample_T_1
inst plusarg_reader of plusarg_reader_46
node _T = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_1 = tail(_T, 1)
node _T_2 = eq(debug_sample, _T_1)
when _T_2 :
connect debug_sample, UInt<1>(0h0)
regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid)
node _util_ctr_T_1 = tail(_util_ctr_T, 1)
connect util_ctr, _util_ctr_T_1
node _fired_T = or(fired, destNodesIn.flit[0].valid)
connect fired, _fired_T
node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_5 = tail(_T_4, 1)
node _T_6 = eq(debug_sample, _T_5)
node _T_7 = and(_T_3, _T_6)
node _T_8 = and(_T_7, fired)
when _T_8 :
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
printf(clock, UInt<1>(0h1), "nocsample %d 27 31 %d\n", debug_tsc, util_ctr) : printf
connect fired, destNodesIn.flit[0].valid
regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_2 = add(util_ctr_1, destNodesIn_1.flit[0].valid)
node _util_ctr_T_3 = tail(_util_ctr_T_2, 1)
connect util_ctr_1, _util_ctr_T_3
node _fired_T_1 = or(fired_1, destNodesIn_1.flit[0].valid)
connect fired_1, _fired_T_1
node _T_11 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_12 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_13 = tail(_T_12, 1)
node _T_14 = eq(debug_sample, _T_13)
node _T_15 = and(_T_11, _T_14)
node _T_16 = and(_T_15, fired_1)
when _T_16 :
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
printf(clock, UInt<1>(0h1), "nocsample %d 30 31 %d\n", debug_tsc, util_ctr_1) : printf_1
connect fired_1, destNodesIn_1.flit[0].valid | module Router_28( // @[Router.scala:89:25]
input clock, // @[Router.scala:89:25]
input reset, // @[Router.scala:89:25]
output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25]
);
wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _route_computer_io_resp_1_vc_sel_0_4; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_5; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_6; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_7; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_3; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_4; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_5; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_6; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_7; // @[Router.scala:136:32]
wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_6; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_7; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_6; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_7; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_1_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_2_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_3_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_4_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_5_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_6_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_7_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_6_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_7_alloc; // @[Router.scala:133:30]
wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_2_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_3_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_4_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_5_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_6_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_7_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_6_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_7_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34]
wire _switch_io_out_1_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _switch_io_out_0_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _output_unit_1_to_30_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_1_to_30_io_credit_available_2; // @[Router.scala:122:13]
wire _output_unit_1_to_30_io_credit_available_3; // @[Router.scala:122:13]
wire _output_unit_1_to_30_io_credit_available_4; // @[Router.scala:122:13]
wire _output_unit_1_to_30_io_credit_available_5; // @[Router.scala:122:13]
wire _output_unit_1_to_30_io_credit_available_6; // @[Router.scala:122:13]
wire _output_unit_1_to_30_io_credit_available_7; // @[Router.scala:122:13]
wire _output_unit_1_to_30_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_30_io_channel_status_2_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_30_io_channel_status_3_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_30_io_channel_status_4_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_30_io_channel_status_5_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_30_io_channel_status_6_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_30_io_channel_status_7_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_27_io_credit_available_4; // @[Router.scala:122:13]
wire _output_unit_0_to_27_io_credit_available_5; // @[Router.scala:122:13]
wire _output_unit_0_to_27_io_credit_available_6; // @[Router.scala:122:13]
wire _output_unit_0_to_27_io_credit_available_7; // @[Router.scala:122:13]
wire _output_unit_0_to_27_io_channel_status_4_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_27_io_channel_status_5_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_27_io_channel_status_6_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_27_io_channel_status_7_occupied; // @[Router.scala:122:13]
wire [2:0] _input_unit_1_from_30_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_30_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_1_from_30_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_30_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_1_from_30_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_30_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_1_from_30_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_30_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_1_from_30_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13]
wire _input_unit_1_from_30_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:112:13]
wire _input_unit_1_from_30_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:112:13]
wire _input_unit_1_from_30_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_30_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_1_from_30_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13]
wire _input_unit_1_from_30_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13]
wire _input_unit_1_from_30_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13]
wire _input_unit_1_from_30_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13]
wire _input_unit_1_from_30_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13]
wire _input_unit_1_from_30_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13]
wire _input_unit_1_from_30_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_1_from_30_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13]
wire _input_unit_1_from_30_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13]
wire _input_unit_1_from_30_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13]
wire _input_unit_1_from_30_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_1_from_30_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_30_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_1_from_30_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_1_from_30_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_30_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_1_from_30_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_30_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_1_from_30_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_30_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_30_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_27_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_27_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_27_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_27_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_27_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_27_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_0_from_27_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_27_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_0_from_27_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13]
wire _input_unit_0_from_27_io_vcalloc_req_bits_vc_sel_1_3; // @[Router.scala:112:13]
wire _input_unit_0_from_27_io_vcalloc_req_bits_vc_sel_1_4; // @[Router.scala:112:13]
wire _input_unit_0_from_27_io_vcalloc_req_bits_vc_sel_1_5; // @[Router.scala:112:13]
wire _input_unit_0_from_27_io_vcalloc_req_bits_vc_sel_1_6; // @[Router.scala:112:13]
wire _input_unit_0_from_27_io_vcalloc_req_bits_vc_sel_1_7; // @[Router.scala:112:13]
wire _input_unit_0_from_27_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_27_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_0_from_27_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13]
wire _input_unit_0_from_27_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13]
wire _input_unit_0_from_27_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13]
wire _input_unit_0_from_27_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13]
wire _input_unit_0_from_27_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13]
wire _input_unit_0_from_27_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13]
wire _input_unit_0_from_27_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_0_from_27_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13]
wire _input_unit_0_from_27_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13]
wire _input_unit_0_from_27_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13]
wire _input_unit_0_from_27_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_0_from_27_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_27_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_0_from_27_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_0_from_27_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_27_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_27_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_27_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_27_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_27_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_27_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_27_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_30_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35]
reg REG_1_0_1_0; // @[Router.scala:178:14]
reg REG_1_0_0_0; // @[Router.scala:178:14]
reg REG_0_0_1_0; // @[Router.scala:178:14]
reg REG_0_0_0_0; // @[Router.scala:178:14]
reg [63:0] debug_tsc; // @[Router.scala:195:28]
reg [63:0] debug_sample; // @[Router.scala:197:31]
wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11]
reg [63:0] util_ctr; // @[Router.scala:203:29]
reg fired; // @[Router.scala:204:26]
wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11]
wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_1; // @[Router.scala:203:29]
reg fired_1; // @[Router.scala:204:26]
wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] |
Generate the Verilog code corresponding to this FIRRTL code module TLSplitACDxBENoC_acd_router_6ClockSinkDomain :
output auto : { routers_debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, routers_egress_nodes_out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip routers_ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip routers_ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, routers_source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}, flip routers_dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}, flip clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst routers of Router_6
connect routers.clock, childClock
connect routers.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
connect clockNodeIn, auto.clock_in
connect routers.auto.dest_nodes_in, auto.routers_dest_nodes_in
connect routers.auto.source_nodes_out.vc_free, auto.routers_source_nodes_out.vc_free
connect routers.auto.source_nodes_out.credit_return, auto.routers_source_nodes_out.credit_return
connect auto.routers_source_nodes_out.flit, routers.auto.source_nodes_out.flit
connect routers.auto.ingress_nodes_in_0, auto.routers_ingress_nodes_in_0
connect routers.auto.ingress_nodes_in_1, auto.routers_ingress_nodes_in_1
connect auto.routers_egress_nodes_out.flit.bits, routers.auto.egress_nodes_out.flit.bits
connect auto.routers_egress_nodes_out.flit.valid, routers.auto.egress_nodes_out.flit.valid
connect routers.auto.egress_nodes_out.flit.ready, auto.routers_egress_nodes_out.flit.ready
connect auto.routers_debug_out, routers.auto.debug_out
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset | module TLSplitACDxBENoC_acd_router_6ClockSinkDomain( // @[ClockDomain.scala:14:9]
output [2:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_routers_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_routers_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
Router_6 routers ( // @[NoC.scala:67:22]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0),
.auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1),
.auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2),
.auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0),
.auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1),
.auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2),
.auto_egress_nodes_out_flit_ready (auto_routers_egress_nodes_out_flit_ready),
.auto_egress_nodes_out_flit_valid (auto_routers_egress_nodes_out_flit_valid),
.auto_egress_nodes_out_flit_bits_head (auto_routers_egress_nodes_out_flit_bits_head),
.auto_egress_nodes_out_flit_bits_tail (auto_routers_egress_nodes_out_flit_bits_tail),
.auto_egress_nodes_out_flit_bits_payload (auto_routers_egress_nodes_out_flit_bits_payload),
.auto_ingress_nodes_in_1_flit_ready (auto_routers_ingress_nodes_in_1_flit_ready),
.auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid),
.auto_ingress_nodes_in_1_flit_bits_head (auto_routers_ingress_nodes_in_1_flit_bits_head),
.auto_ingress_nodes_in_1_flit_bits_tail (auto_routers_ingress_nodes_in_1_flit_bits_tail),
.auto_ingress_nodes_in_1_flit_bits_payload (auto_routers_ingress_nodes_in_1_flit_bits_payload),
.auto_ingress_nodes_in_1_flit_bits_egress_id (auto_routers_ingress_nodes_in_1_flit_bits_egress_id),
.auto_ingress_nodes_in_0_flit_ready (auto_routers_ingress_nodes_in_0_flit_ready),
.auto_ingress_nodes_in_0_flit_valid (auto_routers_ingress_nodes_in_0_flit_valid),
.auto_ingress_nodes_in_0_flit_bits_head (auto_routers_ingress_nodes_in_0_flit_bits_head),
.auto_ingress_nodes_in_0_flit_bits_tail (auto_routers_ingress_nodes_in_0_flit_bits_tail),
.auto_ingress_nodes_in_0_flit_bits_payload (auto_routers_ingress_nodes_in_0_flit_bits_payload),
.auto_ingress_nodes_in_0_flit_bits_egress_id (auto_routers_ingress_nodes_in_0_flit_bits_egress_id),
.auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid),
.auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head),
.auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail),
.auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload),
.auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return),
.auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free),
.auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid),
.auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head),
.auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail),
.auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload),
.auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return),
.auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free)
); // @[NoC.scala:67:22]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLDebugModuleOuterAsync :
output auto : { asource_out : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}, int_out : { sync : UInt<1>[1]}}
output io : { flip dmi_clock : Clock, flip dmi_reset : Reset, flip dmi : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<7>, data : UInt<32>, op : UInt<2>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<32>, resp : UInt<2>}}}, ctrl : { flip debugUnavail : UInt<1>[1], ndreset : UInt<1>, dmactive : UInt<1>, flip dmactiveAck : UInt<1>}, innerCtrl : { mem : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[1], hrmask : UInt<1>[1]}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip hgDebugInt : UInt<1>[1]}
input rf_reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst dmiXbar of TLXbar_dmixbar_i1_o2_a9d32s1k1z2u
connect dmiXbar.clock, childClock
connect dmiXbar.reset, childReset
inst dmi2tl of DMIToTL
connect dmi2tl.clock, childClock
connect dmi2tl.reset, childReset
inst dmOuter of TLDebugModuleOuter
connect dmOuter.clock, childClock
connect dmOuter.reset, childReset
inst intsource of IntSyncCrossingSource_n1x1_Registered
inst dmiBypass of TLBusBypass
connect dmiBypass.clock, childClock
connect dmiBypass.reset, childReset
inst asource of TLAsyncCrossingSource_a9d32s1k1z2u
connect asource.clock, childClock
connect asource.reset, childReset
wire intnodeOut : { sync : UInt<1>[1]}
invalidate intnodeOut.sync[0]
wire intnodeIn : { sync : UInt<1>[1]}
invalidate intnodeIn.sync[0]
connect intnodeOut, intnodeIn
connect dmiBypass.auto.node_in_in, dmiXbar.auto.anon_out_0
connect dmOuter.auto.dmi_in, dmiXbar.auto.anon_out_1
connect dmiXbar.auto.anon_in, dmi2tl.auto.out
connect intsource.auto.in[0], dmOuter.auto.int_out[0]
connect intnodeIn, intsource.auto.out
connect asource.auto.in, dmiBypass.auto.node_out_out
connect auto.int_out, intnodeOut
connect asource.auto.out.e.safe.sink_reset_n, auto.asource_out.e.safe.sink_reset_n
connect auto.asource_out.e.safe.source_reset_n, asource.auto.out.e.safe.source_reset_n
connect auto.asource_out.e.safe.widx_valid, asource.auto.out.e.safe.widx_valid
connect asource.auto.out.e.safe.ridx_valid, auto.asource_out.e.safe.ridx_valid
connect auto.asource_out.e.widx, asource.auto.out.e.widx
connect asource.auto.out.e.ridx, auto.asource_out.e.ridx
connect auto.asource_out.e.mem, asource.auto.out.e.mem
connect asource.auto.out.d, auto.asource_out.d
connect asource.auto.out.c.safe.sink_reset_n, auto.asource_out.c.safe.sink_reset_n
connect auto.asource_out.c.safe.source_reset_n, asource.auto.out.c.safe.source_reset_n
connect auto.asource_out.c.safe.widx_valid, asource.auto.out.c.safe.widx_valid
connect asource.auto.out.c.safe.ridx_valid, auto.asource_out.c.safe.ridx_valid
connect auto.asource_out.c.widx, asource.auto.out.c.widx
connect asource.auto.out.c.ridx, auto.asource_out.c.ridx
connect auto.asource_out.c.mem, asource.auto.out.c.mem
connect asource.auto.out.b, auto.asource_out.b
connect asource.auto.out.a.safe.sink_reset_n, auto.asource_out.a.safe.sink_reset_n
connect auto.asource_out.a.safe.source_reset_n, asource.auto.out.a.safe.source_reset_n
connect auto.asource_out.a.safe.widx_valid, asource.auto.out.a.safe.widx_valid
connect asource.auto.out.a.safe.ridx_valid, auto.asource_out.a.safe.ridx_valid
connect auto.asource_out.a.widx, asource.auto.out.a.widx
connect asource.auto.out.a.ridx, auto.asource_out.a.ridx
connect auto.asource_out.a.mem, asource.auto.out.a.mem
connect childClock, io.dmi_clock
connect childReset, io.dmi_reset
connect dmi2tl.io.dmi, io.dmi
inst dmactiveAck_dmactiveAckSync of AsyncResetSynchronizerShiftReg_w1_d3_i0_98
connect dmactiveAck_dmactiveAckSync.clock, childClock
connect dmactiveAck_dmactiveAckSync.reset, childReset
connect dmactiveAck_dmactiveAckSync.io.d, io.ctrl.dmactiveAck
wire dmactiveAck : UInt<1>
connect dmactiveAck, dmactiveAck_dmactiveAckSync.io.q
node _dmiBypass_io_bypass_T = not(io.ctrl.dmactive)
node _dmiBypass_io_bypass_T_1 = not(dmactiveAck)
node _dmiBypass_io_bypass_T_2 = or(_dmiBypass_io_bypass_T, _dmiBypass_io_bypass_T_1)
connect dmiBypass.io.bypass, _dmiBypass_io_bypass_T_2
connect dmOuter.io.ctrl.dmactiveAck, io.ctrl.dmactiveAck
connect io.ctrl.dmactive, dmOuter.io.ctrl.dmactive
connect io.ctrl.ndreset, dmOuter.io.ctrl.ndreset
connect dmOuter.io.ctrl.debugUnavail[0], io.ctrl.debugUnavail[0]
connect dmOuter.io.ctrl.dmactiveAck, dmactiveAck
inst io_innerCtrl_source of AsyncQueueSource_DebugInternalBundle
connect io_innerCtrl_source.clock, childClock
connect io_innerCtrl_source.reset, childReset
connect io_innerCtrl_source.io.enq, dmOuter.io.innerCtrl
connect io_innerCtrl_source.io.async.safe.sink_reset_n, io.innerCtrl.safe.sink_reset_n
connect io.innerCtrl.safe.source_reset_n, io_innerCtrl_source.io.async.safe.source_reset_n
connect io.innerCtrl.safe.widx_valid, io_innerCtrl_source.io.async.safe.widx_valid
connect io_innerCtrl_source.io.async.safe.ridx_valid, io.innerCtrl.safe.ridx_valid
connect io.innerCtrl.widx, io_innerCtrl_source.io.async.widx
connect io_innerCtrl_source.io.async.ridx, io.innerCtrl.ridx
connect io.innerCtrl.mem, io_innerCtrl_source.io.async.mem
connect dmOuter.io.hgDebugInt[0], io.hgDebugInt[0] | module TLDebugModuleOuterAsync( // @[Debug.scala:709:9]
output [2:0] auto_asource_out_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25]
output [8:0] auto_asource_out_a_mem_0_address, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_asource_out_a_mem_0_data, // @[LazyModuleImp.scala:107:25]
input auto_asource_out_a_ridx, // @[LazyModuleImp.scala:107:25]
output auto_asource_out_a_widx, // @[LazyModuleImp.scala:107:25]
input auto_asource_out_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25]
output auto_asource_out_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25]
output auto_asource_out_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25]
input auto_asource_out_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_asource_out_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_asource_out_d_mem_0_size, // @[LazyModuleImp.scala:107:25]
input auto_asource_out_d_mem_0_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_asource_out_d_mem_0_data, // @[LazyModuleImp.scala:107:25]
output auto_asource_out_d_ridx, // @[LazyModuleImp.scala:107:25]
input auto_asource_out_d_widx, // @[LazyModuleImp.scala:107:25]
output auto_asource_out_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25]
input auto_asource_out_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25]
input auto_asource_out_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25]
output auto_asource_out_d_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25]
output auto_int_out_sync_0, // @[LazyModuleImp.scala:107:25]
input io_dmi_clock, // @[Debug.scala:713:16]
input io_dmi_reset, // @[Debug.scala:713:16]
output io_dmi_req_ready, // @[Debug.scala:713:16]
input io_dmi_req_valid, // @[Debug.scala:713:16]
input [6:0] io_dmi_req_bits_addr, // @[Debug.scala:713:16]
input [31:0] io_dmi_req_bits_data, // @[Debug.scala:713:16]
input [1:0] io_dmi_req_bits_op, // @[Debug.scala:713:16]
input io_dmi_resp_ready, // @[Debug.scala:713:16]
output io_dmi_resp_valid, // @[Debug.scala:713:16]
output [31:0] io_dmi_resp_bits_data, // @[Debug.scala:713:16]
output [1:0] io_dmi_resp_bits_resp, // @[Debug.scala:713:16]
output io_ctrl_ndreset, // @[Debug.scala:713:16]
output io_ctrl_dmactive, // @[Debug.scala:713:16]
input io_ctrl_dmactiveAck, // @[Debug.scala:713:16]
output io_innerCtrl_mem_0_resumereq, // @[Debug.scala:713:16]
output [9:0] io_innerCtrl_mem_0_hartsel, // @[Debug.scala:713:16]
output io_innerCtrl_mem_0_ackhavereset, // @[Debug.scala:713:16]
output io_innerCtrl_mem_0_hrmask_0, // @[Debug.scala:713:16]
input io_innerCtrl_ridx, // @[Debug.scala:713:16]
output io_innerCtrl_widx, // @[Debug.scala:713:16]
input io_innerCtrl_safe_ridx_valid, // @[Debug.scala:713:16]
output io_innerCtrl_safe_widx_valid, // @[Debug.scala:713:16]
output io_innerCtrl_safe_source_reset_n, // @[Debug.scala:713:16]
input io_innerCtrl_safe_sink_reset_n, // @[Debug.scala:713:16]
input io_hgDebugInt_0, // @[Debug.scala:713:16]
input rf_reset // @[Debug.scala:732:22]
);
wire _io_innerCtrl_source_io_enq_ready; // @[AsyncQueue.scala:220:24]
wire _asource_auto_in_a_ready; // @[AsyncCrossing.scala:94:29]
wire _asource_auto_in_d_valid; // @[AsyncCrossing.scala:94:29]
wire [2:0] _asource_auto_in_d_bits_opcode; // @[AsyncCrossing.scala:94:29]
wire [1:0] _asource_auto_in_d_bits_param; // @[AsyncCrossing.scala:94:29]
wire [1:0] _asource_auto_in_d_bits_size; // @[AsyncCrossing.scala:94:29]
wire _asource_auto_in_d_bits_source; // @[AsyncCrossing.scala:94:29]
wire _asource_auto_in_d_bits_sink; // @[AsyncCrossing.scala:94:29]
wire _asource_auto_in_d_bits_denied; // @[AsyncCrossing.scala:94:29]
wire [31:0] _asource_auto_in_d_bits_data; // @[AsyncCrossing.scala:94:29]
wire _asource_auto_in_d_bits_corrupt; // @[AsyncCrossing.scala:94:29]
wire _dmiBypass_auto_node_out_out_a_valid; // @[Debug.scala:704:29]
wire [2:0] _dmiBypass_auto_node_out_out_a_bits_opcode; // @[Debug.scala:704:29]
wire [8:0] _dmiBypass_auto_node_out_out_a_bits_address; // @[Debug.scala:704:29]
wire [31:0] _dmiBypass_auto_node_out_out_a_bits_data; // @[Debug.scala:704:29]
wire _dmiBypass_auto_node_out_out_d_ready; // @[Debug.scala:704:29]
wire _dmiBypass_auto_node_in_in_a_ready; // @[Debug.scala:704:29]
wire _dmiBypass_auto_node_in_in_d_valid; // @[Debug.scala:704:29]
wire [2:0] _dmiBypass_auto_node_in_in_d_bits_opcode; // @[Debug.scala:704:29]
wire [1:0] _dmiBypass_auto_node_in_in_d_bits_param; // @[Debug.scala:704:29]
wire [1:0] _dmiBypass_auto_node_in_in_d_bits_size; // @[Debug.scala:704:29]
wire _dmiBypass_auto_node_in_in_d_bits_source; // @[Debug.scala:704:29]
wire _dmiBypass_auto_node_in_in_d_bits_sink; // @[Debug.scala:704:29]
wire _dmiBypass_auto_node_in_in_d_bits_denied; // @[Debug.scala:704:29]
wire [31:0] _dmiBypass_auto_node_in_in_d_bits_data; // @[Debug.scala:704:29]
wire _dmiBypass_auto_node_in_in_d_bits_corrupt; // @[Debug.scala:704:29]
wire _dmOuter_auto_dmi_in_a_ready; // @[Debug.scala:700:27]
wire _dmOuter_auto_dmi_in_d_valid; // @[Debug.scala:700:27]
wire [2:0] _dmOuter_auto_dmi_in_d_bits_opcode; // @[Debug.scala:700:27]
wire [31:0] _dmOuter_auto_dmi_in_d_bits_data; // @[Debug.scala:700:27]
wire _dmOuter_auto_int_out_0; // @[Debug.scala:700:27]
wire _dmOuter_io_innerCtrl_valid; // @[Debug.scala:700:27]
wire _dmOuter_io_innerCtrl_bits_resumereq; // @[Debug.scala:700:27]
wire [9:0] _dmOuter_io_innerCtrl_bits_hartsel; // @[Debug.scala:700:27]
wire _dmOuter_io_innerCtrl_bits_ackhavereset; // @[Debug.scala:700:27]
wire _dmOuter_io_innerCtrl_bits_hrmask_0; // @[Debug.scala:700:27]
wire _dmi2tl_auto_out_a_valid; // @[Debug.scala:678:28]
wire [2:0] _dmi2tl_auto_out_a_bits_opcode; // @[Debug.scala:678:28]
wire [8:0] _dmi2tl_auto_out_a_bits_address; // @[Debug.scala:678:28]
wire [31:0] _dmi2tl_auto_out_a_bits_data; // @[Debug.scala:678:28]
wire _dmi2tl_auto_out_d_ready; // @[Debug.scala:678:28]
wire _dmiXbar_auto_anon_in_a_ready; // @[Debug.scala:675:28]
wire _dmiXbar_auto_anon_in_d_valid; // @[Debug.scala:675:28]
wire [2:0] _dmiXbar_auto_anon_in_d_bits_opcode; // @[Debug.scala:675:28]
wire [1:0] _dmiXbar_auto_anon_in_d_bits_param; // @[Debug.scala:675:28]
wire [1:0] _dmiXbar_auto_anon_in_d_bits_size; // @[Debug.scala:675:28]
wire _dmiXbar_auto_anon_in_d_bits_sink; // @[Debug.scala:675:28]
wire _dmiXbar_auto_anon_in_d_bits_denied; // @[Debug.scala:675:28]
wire [31:0] _dmiXbar_auto_anon_in_d_bits_data; // @[Debug.scala:675:28]
wire _dmiXbar_auto_anon_in_d_bits_corrupt; // @[Debug.scala:675:28]
wire _dmiXbar_auto_anon_out_1_a_valid; // @[Debug.scala:675:28]
wire [2:0] _dmiXbar_auto_anon_out_1_a_bits_opcode; // @[Debug.scala:675:28]
wire [6:0] _dmiXbar_auto_anon_out_1_a_bits_address; // @[Debug.scala:675:28]
wire [31:0] _dmiXbar_auto_anon_out_1_a_bits_data; // @[Debug.scala:675:28]
wire _dmiXbar_auto_anon_out_1_d_ready; // @[Debug.scala:675:28]
wire _dmiXbar_auto_anon_out_0_a_valid; // @[Debug.scala:675:28]
wire [2:0] _dmiXbar_auto_anon_out_0_a_bits_opcode; // @[Debug.scala:675:28]
wire [8:0] _dmiXbar_auto_anon_out_0_a_bits_address; // @[Debug.scala:675:28]
wire [31:0] _dmiXbar_auto_anon_out_0_a_bits_data; // @[Debug.scala:675:28]
wire _dmiXbar_auto_anon_out_0_d_ready; // @[Debug.scala:675:28]
wire auto_asource_out_a_ridx_0 = auto_asource_out_a_ridx; // @[Debug.scala:709:9]
wire auto_asource_out_a_safe_ridx_valid_0 = auto_asource_out_a_safe_ridx_valid; // @[Debug.scala:709:9]
wire auto_asource_out_a_safe_sink_reset_n_0 = auto_asource_out_a_safe_sink_reset_n; // @[Debug.scala:709:9]
wire [2:0] auto_asource_out_d_mem_0_opcode_0 = auto_asource_out_d_mem_0_opcode; // @[Debug.scala:709:9]
wire [1:0] auto_asource_out_d_mem_0_size_0 = auto_asource_out_d_mem_0_size; // @[Debug.scala:709:9]
wire auto_asource_out_d_mem_0_source_0 = auto_asource_out_d_mem_0_source; // @[Debug.scala:709:9]
wire [31:0] auto_asource_out_d_mem_0_data_0 = auto_asource_out_d_mem_0_data; // @[Debug.scala:709:9]
wire auto_asource_out_d_widx_0 = auto_asource_out_d_widx; // @[Debug.scala:709:9]
wire auto_asource_out_d_safe_widx_valid_0 = auto_asource_out_d_safe_widx_valid; // @[Debug.scala:709:9]
wire auto_asource_out_d_safe_source_reset_n_0 = auto_asource_out_d_safe_source_reset_n; // @[Debug.scala:709:9]
wire io_dmi_clock_0 = io_dmi_clock; // @[Debug.scala:709:9]
wire io_dmi_reset_0 = io_dmi_reset; // @[Debug.scala:709:9]
wire io_dmi_req_valid_0 = io_dmi_req_valid; // @[Debug.scala:709:9]
wire [6:0] io_dmi_req_bits_addr_0 = io_dmi_req_bits_addr; // @[Debug.scala:709:9]
wire [31:0] io_dmi_req_bits_data_0 = io_dmi_req_bits_data; // @[Debug.scala:709:9]
wire [1:0] io_dmi_req_bits_op_0 = io_dmi_req_bits_op; // @[Debug.scala:709:9]
wire io_dmi_resp_ready_0 = io_dmi_resp_ready; // @[Debug.scala:709:9]
wire io_ctrl_dmactiveAck_0 = io_ctrl_dmactiveAck; // @[Debug.scala:709:9]
wire io_innerCtrl_ridx_0 = io_innerCtrl_ridx; // @[Debug.scala:709:9]
wire io_innerCtrl_safe_ridx_valid_0 = io_innerCtrl_safe_ridx_valid; // @[Debug.scala:709:9]
wire io_innerCtrl_safe_sink_reset_n_0 = io_innerCtrl_safe_sink_reset_n; // @[Debug.scala:709:9]
wire io_hgDebugInt_0_0 = io_hgDebugInt_0; // @[Debug.scala:709:9]
wire auto_asource_out_a_mem_0_source = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_a_mem_0_corrupt = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_b_mem_0_source = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_b_mem_0_corrupt = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_b_ridx = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_b_widx = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_b_safe_ridx_valid = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_b_safe_widx_valid = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_b_safe_source_reset_n = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_b_safe_sink_reset_n = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_c_mem_0_source = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_c_mem_0_corrupt = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_c_ridx = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_c_widx = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_c_safe_ridx_valid = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_c_safe_widx_valid = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_c_safe_source_reset_n = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_c_safe_sink_reset_n = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_d_mem_0_sink = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_d_mem_0_denied = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_d_mem_0_corrupt = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_e_mem_0_sink = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_e_ridx = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_e_widx = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_e_safe_ridx_valid = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_e_safe_widx_valid = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_e_safe_source_reset_n = 1'h0; // @[Debug.scala:709:9]
wire auto_asource_out_e_safe_sink_reset_n = 1'h0; // @[Debug.scala:709:9]
wire io_ctrl_debugUnavail_0 = 1'h0; // @[Debug.scala:709:9]
wire io_innerCtrl_mem_0_hasel = 1'h0; // @[Debug.scala:709:9]
wire io_innerCtrl_mem_0_hamask_0 = 1'h0; // @[Debug.scala:709:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire [31:0] auto_asource_out_b_mem_0_data = 32'h0; // @[AsyncCrossing.scala:94:29]
wire [31:0] auto_asource_out_c_mem_0_data = 32'h0; // @[AsyncCrossing.scala:94:29]
wire [3:0] auto_asource_out_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:94:29]
wire [8:0] auto_asource_out_b_mem_0_address = 9'h0; // @[AsyncCrossing.scala:94:29]
wire [8:0] auto_asource_out_c_mem_0_address = 9'h0; // @[AsyncCrossing.scala:94:29]
wire [1:0] auto_asource_out_b_mem_0_param = 2'h0; // @[Debug.scala:709:9]
wire [1:0] auto_asource_out_b_mem_0_size = 2'h0; // @[Debug.scala:709:9]
wire [1:0] auto_asource_out_c_mem_0_size = 2'h0; // @[Debug.scala:709:9]
wire [1:0] auto_asource_out_d_mem_0_param = 2'h0; // @[Debug.scala:709:9]
wire [3:0] auto_asource_out_a_mem_0_mask = 4'hF; // @[AsyncCrossing.scala:94:29]
wire [1:0] auto_asource_out_a_mem_0_size = 2'h2; // @[AsyncCrossing.scala:94:29]
wire [2:0] auto_asource_out_a_mem_0_param = 3'h0; // @[Debug.scala:709:9]
wire [2:0] auto_asource_out_b_mem_0_opcode = 3'h0; // @[Debug.scala:709:9]
wire [2:0] auto_asource_out_c_mem_0_opcode = 3'h0; // @[Debug.scala:709:9]
wire [2:0] auto_asource_out_c_mem_0_param = 3'h0; // @[Debug.scala:709:9]
wire intnodeOut_sync_0; // @[MixedNode.scala:542:17]
wire childClock = io_dmi_clock_0; // @[Debug.scala:709:9]
wire childReset = io_dmi_reset_0; // @[Debug.scala:709:9]
wire [2:0] auto_asource_out_a_mem_0_opcode_0; // @[Debug.scala:709:9]
wire [8:0] auto_asource_out_a_mem_0_address_0; // @[Debug.scala:709:9]
wire [31:0] auto_asource_out_a_mem_0_data_0; // @[Debug.scala:709:9]
wire auto_asource_out_a_safe_widx_valid_0; // @[Debug.scala:709:9]
wire auto_asource_out_a_safe_source_reset_n_0; // @[Debug.scala:709:9]
wire auto_asource_out_a_widx_0; // @[Debug.scala:709:9]
wire auto_asource_out_d_safe_ridx_valid_0; // @[Debug.scala:709:9]
wire auto_asource_out_d_safe_sink_reset_n_0; // @[Debug.scala:709:9]
wire auto_asource_out_d_ridx_0; // @[Debug.scala:709:9]
wire auto_int_out_sync_0_0; // @[Debug.scala:709:9]
wire io_dmi_req_ready_0; // @[Debug.scala:709:9]
wire [31:0] io_dmi_resp_bits_data_0; // @[Debug.scala:709:9]
wire [1:0] io_dmi_resp_bits_resp_0; // @[Debug.scala:709:9]
wire io_dmi_resp_valid_0; // @[Debug.scala:709:9]
wire io_ctrl_ndreset_0; // @[Debug.scala:709:9]
wire io_ctrl_dmactive_0; // @[Debug.scala:709:9]
wire io_innerCtrl_mem_0_hrmask_0_0; // @[Debug.scala:709:9]
wire io_innerCtrl_mem_0_resumereq_0; // @[Debug.scala:709:9]
wire [9:0] io_innerCtrl_mem_0_hartsel_0; // @[Debug.scala:709:9]
wire io_innerCtrl_mem_0_ackhavereset_0; // @[Debug.scala:709:9]
wire io_innerCtrl_safe_widx_valid_0; // @[Debug.scala:709:9]
wire io_innerCtrl_safe_source_reset_n_0; // @[Debug.scala:709:9]
wire io_innerCtrl_widx_0; // @[Debug.scala:709:9]
wire intnodeIn_sync_0; // @[MixedNode.scala:551:17]
assign auto_int_out_sync_0_0 = intnodeOut_sync_0; // @[Debug.scala:709:9]
assign intnodeOut_sync_0 = intnodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
wire dmactiveAck; // @[ShiftReg.scala:48:24]
wire _dmiBypass_io_bypass_T = ~io_ctrl_dmactive_0; // @[Debug.scala:709:9, :742:37]
wire _dmiBypass_io_bypass_T_1 = ~dmactiveAck; // @[ShiftReg.scala:48:24]
wire _dmiBypass_io_bypass_T_2 = _dmiBypass_io_bypass_T | _dmiBypass_io_bypass_T_1; // @[Debug.scala:742:{37,55,57}]
TLXbar_dmixbar_i1_o2_a9d32s1k1z2u dmiXbar ( // @[Debug.scala:675:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_anon_in_a_ready (_dmiXbar_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_dmi2tl_auto_out_a_valid), // @[Debug.scala:678:28]
.auto_anon_in_a_bits_opcode (_dmi2tl_auto_out_a_bits_opcode), // @[Debug.scala:678:28]
.auto_anon_in_a_bits_address (_dmi2tl_auto_out_a_bits_address), // @[Debug.scala:678:28]
.auto_anon_in_a_bits_data (_dmi2tl_auto_out_a_bits_data), // @[Debug.scala:678:28]
.auto_anon_in_d_ready (_dmi2tl_auto_out_d_ready), // @[Debug.scala:678:28]
.auto_anon_in_d_valid (_dmiXbar_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_dmiXbar_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_param (_dmiXbar_auto_anon_in_d_bits_param),
.auto_anon_in_d_bits_size (_dmiXbar_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_sink (_dmiXbar_auto_anon_in_d_bits_sink),
.auto_anon_in_d_bits_denied (_dmiXbar_auto_anon_in_d_bits_denied),
.auto_anon_in_d_bits_data (_dmiXbar_auto_anon_in_d_bits_data),
.auto_anon_in_d_bits_corrupt (_dmiXbar_auto_anon_in_d_bits_corrupt),
.auto_anon_out_1_a_ready (_dmOuter_auto_dmi_in_a_ready), // @[Debug.scala:700:27]
.auto_anon_out_1_a_valid (_dmiXbar_auto_anon_out_1_a_valid),
.auto_anon_out_1_a_bits_opcode (_dmiXbar_auto_anon_out_1_a_bits_opcode),
.auto_anon_out_1_a_bits_address (_dmiXbar_auto_anon_out_1_a_bits_address),
.auto_anon_out_1_a_bits_data (_dmiXbar_auto_anon_out_1_a_bits_data),
.auto_anon_out_1_d_ready (_dmiXbar_auto_anon_out_1_d_ready),
.auto_anon_out_1_d_valid (_dmOuter_auto_dmi_in_d_valid), // @[Debug.scala:700:27]
.auto_anon_out_1_d_bits_opcode (_dmOuter_auto_dmi_in_d_bits_opcode), // @[Debug.scala:700:27]
.auto_anon_out_1_d_bits_data (_dmOuter_auto_dmi_in_d_bits_data), // @[Debug.scala:700:27]
.auto_anon_out_0_a_ready (_dmiBypass_auto_node_in_in_a_ready), // @[Debug.scala:704:29]
.auto_anon_out_0_a_valid (_dmiXbar_auto_anon_out_0_a_valid),
.auto_anon_out_0_a_bits_opcode (_dmiXbar_auto_anon_out_0_a_bits_opcode),
.auto_anon_out_0_a_bits_address (_dmiXbar_auto_anon_out_0_a_bits_address),
.auto_anon_out_0_a_bits_data (_dmiXbar_auto_anon_out_0_a_bits_data),
.auto_anon_out_0_d_ready (_dmiXbar_auto_anon_out_0_d_ready),
.auto_anon_out_0_d_valid (_dmiBypass_auto_node_in_in_d_valid), // @[Debug.scala:704:29]
.auto_anon_out_0_d_bits_opcode (_dmiBypass_auto_node_in_in_d_bits_opcode), // @[Debug.scala:704:29]
.auto_anon_out_0_d_bits_param (_dmiBypass_auto_node_in_in_d_bits_param), // @[Debug.scala:704:29]
.auto_anon_out_0_d_bits_size (_dmiBypass_auto_node_in_in_d_bits_size), // @[Debug.scala:704:29]
.auto_anon_out_0_d_bits_source (_dmiBypass_auto_node_in_in_d_bits_source), // @[Debug.scala:704:29]
.auto_anon_out_0_d_bits_sink (_dmiBypass_auto_node_in_in_d_bits_sink), // @[Debug.scala:704:29]
.auto_anon_out_0_d_bits_denied (_dmiBypass_auto_node_in_in_d_bits_denied), // @[Debug.scala:704:29]
.auto_anon_out_0_d_bits_data (_dmiBypass_auto_node_in_in_d_bits_data), // @[Debug.scala:704:29]
.auto_anon_out_0_d_bits_corrupt (_dmiBypass_auto_node_in_in_d_bits_corrupt) // @[Debug.scala:704:29]
); // @[Debug.scala:675:28]
DMIToTL dmi2tl ( // @[Debug.scala:678:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_out_a_ready (_dmiXbar_auto_anon_in_a_ready), // @[Debug.scala:675:28]
.auto_out_a_valid (_dmi2tl_auto_out_a_valid),
.auto_out_a_bits_opcode (_dmi2tl_auto_out_a_bits_opcode),
.auto_out_a_bits_address (_dmi2tl_auto_out_a_bits_address),
.auto_out_a_bits_data (_dmi2tl_auto_out_a_bits_data),
.auto_out_d_ready (_dmi2tl_auto_out_d_ready),
.auto_out_d_valid (_dmiXbar_auto_anon_in_d_valid), // @[Debug.scala:675:28]
.auto_out_d_bits_opcode (_dmiXbar_auto_anon_in_d_bits_opcode), // @[Debug.scala:675:28]
.auto_out_d_bits_param (_dmiXbar_auto_anon_in_d_bits_param), // @[Debug.scala:675:28]
.auto_out_d_bits_size (_dmiXbar_auto_anon_in_d_bits_size), // @[Debug.scala:675:28]
.auto_out_d_bits_sink (_dmiXbar_auto_anon_in_d_bits_sink), // @[Debug.scala:675:28]
.auto_out_d_bits_denied (_dmiXbar_auto_anon_in_d_bits_denied), // @[Debug.scala:675:28]
.auto_out_d_bits_data (_dmiXbar_auto_anon_in_d_bits_data), // @[Debug.scala:675:28]
.auto_out_d_bits_corrupt (_dmiXbar_auto_anon_in_d_bits_corrupt), // @[Debug.scala:675:28]
.io_dmi_req_ready (io_dmi_req_ready_0),
.io_dmi_req_valid (io_dmi_req_valid_0), // @[Debug.scala:709:9]
.io_dmi_req_bits_addr (io_dmi_req_bits_addr_0), // @[Debug.scala:709:9]
.io_dmi_req_bits_data (io_dmi_req_bits_data_0), // @[Debug.scala:709:9]
.io_dmi_req_bits_op (io_dmi_req_bits_op_0), // @[Debug.scala:709:9]
.io_dmi_resp_ready (io_dmi_resp_ready_0), // @[Debug.scala:709:9]
.io_dmi_resp_valid (io_dmi_resp_valid_0),
.io_dmi_resp_bits_data (io_dmi_resp_bits_data_0),
.io_dmi_resp_bits_resp (io_dmi_resp_bits_resp_0)
); // @[Debug.scala:678:28]
TLDebugModuleOuter dmOuter ( // @[Debug.scala:700:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_dmi_in_a_ready (_dmOuter_auto_dmi_in_a_ready),
.auto_dmi_in_a_valid (_dmiXbar_auto_anon_out_1_a_valid), // @[Debug.scala:675:28]
.auto_dmi_in_a_bits_opcode (_dmiXbar_auto_anon_out_1_a_bits_opcode), // @[Debug.scala:675:28]
.auto_dmi_in_a_bits_address (_dmiXbar_auto_anon_out_1_a_bits_address), // @[Debug.scala:675:28]
.auto_dmi_in_a_bits_data (_dmiXbar_auto_anon_out_1_a_bits_data), // @[Debug.scala:675:28]
.auto_dmi_in_d_ready (_dmiXbar_auto_anon_out_1_d_ready), // @[Debug.scala:675:28]
.auto_dmi_in_d_valid (_dmOuter_auto_dmi_in_d_valid),
.auto_dmi_in_d_bits_opcode (_dmOuter_auto_dmi_in_d_bits_opcode),
.auto_dmi_in_d_bits_data (_dmOuter_auto_dmi_in_d_bits_data),
.auto_int_out_0 (_dmOuter_auto_int_out_0),
.io_ctrl_ndreset (io_ctrl_ndreset_0),
.io_ctrl_dmactive (io_ctrl_dmactive_0),
.io_ctrl_dmactiveAck (dmactiveAck), // @[ShiftReg.scala:48:24]
.io_innerCtrl_ready (_io_innerCtrl_source_io_enq_ready), // @[AsyncQueue.scala:220:24]
.io_innerCtrl_valid (_dmOuter_io_innerCtrl_valid),
.io_innerCtrl_bits_resumereq (_dmOuter_io_innerCtrl_bits_resumereq),
.io_innerCtrl_bits_hartsel (_dmOuter_io_innerCtrl_bits_hartsel),
.io_innerCtrl_bits_ackhavereset (_dmOuter_io_innerCtrl_bits_ackhavereset),
.io_innerCtrl_bits_hrmask_0 (_dmOuter_io_innerCtrl_bits_hrmask_0),
.io_hgDebugInt_0 (io_hgDebugInt_0_0) // @[Debug.scala:709:9]
); // @[Debug.scala:700:27]
IntSyncCrossingSource_n1x1_Registered intsource ( // @[Crossing.scala:29:31]
.auto_in_0 (_dmOuter_auto_int_out_0), // @[Debug.scala:700:27]
.auto_out_sync_0 (intnodeIn_sync_0)
); // @[Crossing.scala:29:31]
TLBusBypass dmiBypass ( // @[Debug.scala:704:29]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_node_out_out_a_ready (_asource_auto_in_a_ready), // @[AsyncCrossing.scala:94:29]
.auto_node_out_out_a_valid (_dmiBypass_auto_node_out_out_a_valid),
.auto_node_out_out_a_bits_opcode (_dmiBypass_auto_node_out_out_a_bits_opcode),
.auto_node_out_out_a_bits_address (_dmiBypass_auto_node_out_out_a_bits_address),
.auto_node_out_out_a_bits_data (_dmiBypass_auto_node_out_out_a_bits_data),
.auto_node_out_out_d_ready (_dmiBypass_auto_node_out_out_d_ready),
.auto_node_out_out_d_valid (_asource_auto_in_d_valid), // @[AsyncCrossing.scala:94:29]
.auto_node_out_out_d_bits_opcode (_asource_auto_in_d_bits_opcode), // @[AsyncCrossing.scala:94:29]
.auto_node_out_out_d_bits_param (_asource_auto_in_d_bits_param), // @[AsyncCrossing.scala:94:29]
.auto_node_out_out_d_bits_size (_asource_auto_in_d_bits_size), // @[AsyncCrossing.scala:94:29]
.auto_node_out_out_d_bits_source (_asource_auto_in_d_bits_source), // @[AsyncCrossing.scala:94:29]
.auto_node_out_out_d_bits_sink (_asource_auto_in_d_bits_sink), // @[AsyncCrossing.scala:94:29]
.auto_node_out_out_d_bits_denied (_asource_auto_in_d_bits_denied), // @[AsyncCrossing.scala:94:29]
.auto_node_out_out_d_bits_data (_asource_auto_in_d_bits_data), // @[AsyncCrossing.scala:94:29]
.auto_node_out_out_d_bits_corrupt (_asource_auto_in_d_bits_corrupt), // @[AsyncCrossing.scala:94:29]
.auto_node_in_in_a_ready (_dmiBypass_auto_node_in_in_a_ready),
.auto_node_in_in_a_valid (_dmiXbar_auto_anon_out_0_a_valid), // @[Debug.scala:675:28]
.auto_node_in_in_a_bits_opcode (_dmiXbar_auto_anon_out_0_a_bits_opcode), // @[Debug.scala:675:28]
.auto_node_in_in_a_bits_address (_dmiXbar_auto_anon_out_0_a_bits_address), // @[Debug.scala:675:28]
.auto_node_in_in_a_bits_data (_dmiXbar_auto_anon_out_0_a_bits_data), // @[Debug.scala:675:28]
.auto_node_in_in_d_ready (_dmiXbar_auto_anon_out_0_d_ready), // @[Debug.scala:675:28]
.auto_node_in_in_d_valid (_dmiBypass_auto_node_in_in_d_valid),
.auto_node_in_in_d_bits_opcode (_dmiBypass_auto_node_in_in_d_bits_opcode),
.auto_node_in_in_d_bits_param (_dmiBypass_auto_node_in_in_d_bits_param),
.auto_node_in_in_d_bits_size (_dmiBypass_auto_node_in_in_d_bits_size),
.auto_node_in_in_d_bits_source (_dmiBypass_auto_node_in_in_d_bits_source),
.auto_node_in_in_d_bits_sink (_dmiBypass_auto_node_in_in_d_bits_sink),
.auto_node_in_in_d_bits_denied (_dmiBypass_auto_node_in_in_d_bits_denied),
.auto_node_in_in_d_bits_data (_dmiBypass_auto_node_in_in_d_bits_data),
.auto_node_in_in_d_bits_corrupt (_dmiBypass_auto_node_in_in_d_bits_corrupt),
.io_bypass (_dmiBypass_io_bypass_T_2) // @[Debug.scala:742:55]
); // @[Debug.scala:704:29]
TLAsyncCrossingSource_a9d32s1k1z2u asource ( // @[AsyncCrossing.scala:94:29]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (_asource_auto_in_a_ready),
.auto_in_a_valid (_dmiBypass_auto_node_out_out_a_valid), // @[Debug.scala:704:29]
.auto_in_a_bits_opcode (_dmiBypass_auto_node_out_out_a_bits_opcode), // @[Debug.scala:704:29]
.auto_in_a_bits_address (_dmiBypass_auto_node_out_out_a_bits_address), // @[Debug.scala:704:29]
.auto_in_a_bits_data (_dmiBypass_auto_node_out_out_a_bits_data), // @[Debug.scala:704:29]
.auto_in_d_ready (_dmiBypass_auto_node_out_out_d_ready), // @[Debug.scala:704:29]
.auto_in_d_valid (_asource_auto_in_d_valid),
.auto_in_d_bits_opcode (_asource_auto_in_d_bits_opcode),
.auto_in_d_bits_param (_asource_auto_in_d_bits_param),
.auto_in_d_bits_size (_asource_auto_in_d_bits_size),
.auto_in_d_bits_source (_asource_auto_in_d_bits_source),
.auto_in_d_bits_sink (_asource_auto_in_d_bits_sink),
.auto_in_d_bits_denied (_asource_auto_in_d_bits_denied),
.auto_in_d_bits_data (_asource_auto_in_d_bits_data),
.auto_in_d_bits_corrupt (_asource_auto_in_d_bits_corrupt),
.auto_out_a_mem_0_opcode (auto_asource_out_a_mem_0_opcode_0),
.auto_out_a_mem_0_address (auto_asource_out_a_mem_0_address_0),
.auto_out_a_mem_0_data (auto_asource_out_a_mem_0_data_0),
.auto_out_a_ridx (auto_asource_out_a_ridx_0), // @[Debug.scala:709:9]
.auto_out_a_widx (auto_asource_out_a_widx_0),
.auto_out_a_safe_ridx_valid (auto_asource_out_a_safe_ridx_valid_0), // @[Debug.scala:709:9]
.auto_out_a_safe_widx_valid (auto_asource_out_a_safe_widx_valid_0),
.auto_out_a_safe_source_reset_n (auto_asource_out_a_safe_source_reset_n_0),
.auto_out_a_safe_sink_reset_n (auto_asource_out_a_safe_sink_reset_n_0), // @[Debug.scala:709:9]
.auto_out_d_mem_0_opcode (auto_asource_out_d_mem_0_opcode_0), // @[Debug.scala:709:9]
.auto_out_d_mem_0_size (auto_asource_out_d_mem_0_size_0), // @[Debug.scala:709:9]
.auto_out_d_mem_0_source (auto_asource_out_d_mem_0_source_0), // @[Debug.scala:709:9]
.auto_out_d_mem_0_data (auto_asource_out_d_mem_0_data_0), // @[Debug.scala:709:9]
.auto_out_d_ridx (auto_asource_out_d_ridx_0),
.auto_out_d_widx (auto_asource_out_d_widx_0), // @[Debug.scala:709:9]
.auto_out_d_safe_ridx_valid (auto_asource_out_d_safe_ridx_valid_0),
.auto_out_d_safe_widx_valid (auto_asource_out_d_safe_widx_valid_0), // @[Debug.scala:709:9]
.auto_out_d_safe_source_reset_n (auto_asource_out_d_safe_source_reset_n_0), // @[Debug.scala:709:9]
.auto_out_d_safe_sink_reset_n (auto_asource_out_d_safe_sink_reset_n_0)
); // @[AsyncCrossing.scala:94:29]
AsyncResetSynchronizerShiftReg_w1_d3_i0_98 dmactiveAck_dmactiveAckSync ( // @[ShiftReg.scala:45:23]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.io_d (io_ctrl_dmactiveAck_0), // @[Debug.scala:709:9]
.io_q (dmactiveAck)
); // @[ShiftReg.scala:45:23]
AsyncQueueSource_DebugInternalBundle io_innerCtrl_source ( // @[AsyncQueue.scala:220:24]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.io_enq_ready (_io_innerCtrl_source_io_enq_ready),
.io_enq_valid (_dmOuter_io_innerCtrl_valid), // @[Debug.scala:700:27]
.io_enq_bits_resumereq (_dmOuter_io_innerCtrl_bits_resumereq), // @[Debug.scala:700:27]
.io_enq_bits_hartsel (_dmOuter_io_innerCtrl_bits_hartsel), // @[Debug.scala:700:27]
.io_enq_bits_ackhavereset (_dmOuter_io_innerCtrl_bits_ackhavereset), // @[Debug.scala:700:27]
.io_enq_bits_hrmask_0 (_dmOuter_io_innerCtrl_bits_hrmask_0), // @[Debug.scala:700:27]
.io_async_mem_0_resumereq (io_innerCtrl_mem_0_resumereq_0),
.io_async_mem_0_hartsel (io_innerCtrl_mem_0_hartsel_0),
.io_async_mem_0_ackhavereset (io_innerCtrl_mem_0_ackhavereset_0),
.io_async_mem_0_hrmask_0 (io_innerCtrl_mem_0_hrmask_0_0),
.io_async_ridx (io_innerCtrl_ridx_0), // @[Debug.scala:709:9]
.io_async_widx (io_innerCtrl_widx_0),
.io_async_safe_ridx_valid (io_innerCtrl_safe_ridx_valid_0), // @[Debug.scala:709:9]
.io_async_safe_widx_valid (io_innerCtrl_safe_widx_valid_0),
.io_async_safe_source_reset_n (io_innerCtrl_safe_source_reset_n_0),
.io_async_safe_sink_reset_n (io_innerCtrl_safe_sink_reset_n_0) // @[Debug.scala:709:9]
); // @[AsyncQueue.scala:220:24]
assign auto_asource_out_a_mem_0_opcode = auto_asource_out_a_mem_0_opcode_0; // @[Debug.scala:709:9]
assign auto_asource_out_a_mem_0_address = auto_asource_out_a_mem_0_address_0; // @[Debug.scala:709:9]
assign auto_asource_out_a_mem_0_data = auto_asource_out_a_mem_0_data_0; // @[Debug.scala:709:9]
assign auto_asource_out_a_widx = auto_asource_out_a_widx_0; // @[Debug.scala:709:9]
assign auto_asource_out_a_safe_widx_valid = auto_asource_out_a_safe_widx_valid_0; // @[Debug.scala:709:9]
assign auto_asource_out_a_safe_source_reset_n = auto_asource_out_a_safe_source_reset_n_0; // @[Debug.scala:709:9]
assign auto_asource_out_d_ridx = auto_asource_out_d_ridx_0; // @[Debug.scala:709:9]
assign auto_asource_out_d_safe_ridx_valid = auto_asource_out_d_safe_ridx_valid_0; // @[Debug.scala:709:9]
assign auto_asource_out_d_safe_sink_reset_n = auto_asource_out_d_safe_sink_reset_n_0; // @[Debug.scala:709:9]
assign auto_int_out_sync_0 = auto_int_out_sync_0_0; // @[Debug.scala:709:9]
assign io_dmi_req_ready = io_dmi_req_ready_0; // @[Debug.scala:709:9]
assign io_dmi_resp_valid = io_dmi_resp_valid_0; // @[Debug.scala:709:9]
assign io_dmi_resp_bits_data = io_dmi_resp_bits_data_0; // @[Debug.scala:709:9]
assign io_dmi_resp_bits_resp = io_dmi_resp_bits_resp_0; // @[Debug.scala:709:9]
assign io_ctrl_ndreset = io_ctrl_ndreset_0; // @[Debug.scala:709:9]
assign io_ctrl_dmactive = io_ctrl_dmactive_0; // @[Debug.scala:709:9]
assign io_innerCtrl_mem_0_resumereq = io_innerCtrl_mem_0_resumereq_0; // @[Debug.scala:709:9]
assign io_innerCtrl_mem_0_hartsel = io_innerCtrl_mem_0_hartsel_0; // @[Debug.scala:709:9]
assign io_innerCtrl_mem_0_ackhavereset = io_innerCtrl_mem_0_ackhavereset_0; // @[Debug.scala:709:9]
assign io_innerCtrl_mem_0_hrmask_0 = io_innerCtrl_mem_0_hrmask_0_0; // @[Debug.scala:709:9]
assign io_innerCtrl_widx = io_innerCtrl_widx_0; // @[Debug.scala:709:9]
assign io_innerCtrl_safe_widx_valid = io_innerCtrl_safe_widx_valid_0; // @[Debug.scala:709:9]
assign io_innerCtrl_safe_source_reset_n = io_innerCtrl_safe_source_reset_n_0; // @[Debug.scala:709:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_97 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_185
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_97( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_185 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_100 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_100( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_86 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_86( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_18 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_38
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_18( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_38 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_38 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0)
node _source_ok_T = shr(io.in.a.bits.source, 11)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits = bits(_uncommonBits_T, 10, 0)
node _T_4 = shr(io.in.a.bits.source, 11)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<11>(0h40f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0)
node _T_24 = shr(io.in.a.bits.source, 11)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0)
node _T_86 = shr(io.in.a.bits.source, 11)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0)
node _T_152 = shr(io.in.a.bits.source, 11)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0)
node _T_199 = shr(io.in.a.bits.source, 11)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_208 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_209 = cvt(_T_208)
node _T_210 = and(_T_209, asSInt(UInt<17>(0h10000)))
node _T_211 = asSInt(_T_210)
node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0)))
node _T_213 = and(_T_207, _T_212)
node _T_214 = or(UInt<1>(0h0), _T_213)
node _T_215 = and(_T_206, _T_214)
node _T_216 = asUInt(reset)
node _T_217 = eq(_T_216, UInt<1>(0h0))
when _T_217 :
node _T_218 = eq(_T_215, UInt<1>(0h0))
when _T_218 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_215, UInt<1>(0h1), "") : assert_26
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(is_aligned, UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_225 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_225, UInt<1>(0h1), "") : assert_29
node _T_229 = eq(io.in.a.bits.mask, mask)
node _T_230 = asUInt(reset)
node _T_231 = eq(_T_230, UInt<1>(0h0))
when _T_231 :
node _T_232 = eq(_T_229, UInt<1>(0h0))
when _T_232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_229, UInt<1>(0h1), "") : assert_30
node _T_233 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_233 :
node _T_234 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_235 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_236 = and(_T_234, _T_235)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0)
node _T_237 = shr(io.in.a.bits.source, 11)
node _T_238 = eq(_T_237, UInt<1>(0h0))
node _T_239 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_240 = and(_T_238, _T_239)
node _T_241 = leq(uncommonBits_5, UInt<11>(0h40f))
node _T_242 = and(_T_240, _T_241)
node _T_243 = and(_T_236, _T_242)
node _T_244 = or(UInt<1>(0h0), _T_243)
node _T_245 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_246 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<17>(0h10000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = and(_T_245, _T_250)
node _T_252 = or(UInt<1>(0h0), _T_251)
node _T_253 = and(_T_244, _T_252)
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_253, UInt<1>(0h1), "") : assert_31
node _T_257 = asUInt(reset)
node _T_258 = eq(_T_257, UInt<1>(0h0))
when _T_258 :
node _T_259 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_259 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(is_aligned, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_263 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_264 = asUInt(reset)
node _T_265 = eq(_T_264, UInt<1>(0h0))
when _T_265 :
node _T_266 = eq(_T_263, UInt<1>(0h0))
when _T_266 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_263, UInt<1>(0h1), "") : assert_34
node _T_267 = not(mask)
node _T_268 = and(io.in.a.bits.mask, _T_267)
node _T_269 = eq(_T_268, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_269, UInt<1>(0h1), "") : assert_35
node _T_273 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_273 :
node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_276 = and(_T_274, _T_275)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0)
node _T_277 = shr(io.in.a.bits.source, 11)
node _T_278 = eq(_T_277, UInt<1>(0h0))
node _T_279 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_280 = and(_T_278, _T_279)
node _T_281 = leq(uncommonBits_6, UInt<11>(0h40f))
node _T_282 = and(_T_280, _T_281)
node _T_283 = and(_T_276, _T_282)
node _T_284 = or(UInt<1>(0h0), _T_283)
node _T_285 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_286 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_287 = cvt(_T_286)
node _T_288 = and(_T_287, asSInt(UInt<17>(0h10000)))
node _T_289 = asSInt(_T_288)
node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0)))
node _T_291 = and(_T_285, _T_290)
node _T_292 = or(UInt<1>(0h0), _T_291)
node _T_293 = and(_T_284, _T_292)
node _T_294 = asUInt(reset)
node _T_295 = eq(_T_294, UInt<1>(0h0))
when _T_295 :
node _T_296 = eq(_T_293, UInt<1>(0h0))
when _T_296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_293, UInt<1>(0h1), "") : assert_36
node _T_297 = asUInt(reset)
node _T_298 = eq(_T_297, UInt<1>(0h0))
when _T_298 :
node _T_299 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_299 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(is_aligned, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_303 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_304 = asUInt(reset)
node _T_305 = eq(_T_304, UInt<1>(0h0))
when _T_305 :
node _T_306 = eq(_T_303, UInt<1>(0h0))
when _T_306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_303, UInt<1>(0h1), "") : assert_39
node _T_307 = eq(io.in.a.bits.mask, mask)
node _T_308 = asUInt(reset)
node _T_309 = eq(_T_308, UInt<1>(0h0))
when _T_309 :
node _T_310 = eq(_T_307, UInt<1>(0h0))
when _T_310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_307, UInt<1>(0h1), "") : assert_40
node _T_311 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_311 :
node _T_312 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_313 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_314 = and(_T_312, _T_313)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0)
node _T_315 = shr(io.in.a.bits.source, 11)
node _T_316 = eq(_T_315, UInt<1>(0h0))
node _T_317 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_318 = and(_T_316, _T_317)
node _T_319 = leq(uncommonBits_7, UInt<11>(0h40f))
node _T_320 = and(_T_318, _T_319)
node _T_321 = and(_T_314, _T_320)
node _T_322 = or(UInt<1>(0h0), _T_321)
node _T_323 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_324 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_325 = cvt(_T_324)
node _T_326 = and(_T_325, asSInt(UInt<17>(0h10000)))
node _T_327 = asSInt(_T_326)
node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0)))
node _T_329 = and(_T_323, _T_328)
node _T_330 = or(UInt<1>(0h0), _T_329)
node _T_331 = and(_T_322, _T_330)
node _T_332 = asUInt(reset)
node _T_333 = eq(_T_332, UInt<1>(0h0))
when _T_333 :
node _T_334 = eq(_T_331, UInt<1>(0h0))
when _T_334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_331, UInt<1>(0h1), "") : assert_41
node _T_335 = asUInt(reset)
node _T_336 = eq(_T_335, UInt<1>(0h0))
when _T_336 :
node _T_337 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_337 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(is_aligned, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_341 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_342 = asUInt(reset)
node _T_343 = eq(_T_342, UInt<1>(0h0))
when _T_343 :
node _T_344 = eq(_T_341, UInt<1>(0h0))
when _T_344 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_341, UInt<1>(0h1), "") : assert_44
node _T_345 = eq(io.in.a.bits.mask, mask)
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_345, UInt<1>(0h1), "") : assert_45
node _T_349 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_349 :
node _T_350 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_351 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_352 = and(_T_350, _T_351)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0)
node _T_353 = shr(io.in.a.bits.source, 11)
node _T_354 = eq(_T_353, UInt<1>(0h0))
node _T_355 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_356 = and(_T_354, _T_355)
node _T_357 = leq(uncommonBits_8, UInt<11>(0h40f))
node _T_358 = and(_T_356, _T_357)
node _T_359 = and(_T_352, _T_358)
node _T_360 = or(UInt<1>(0h0), _T_359)
node _T_361 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_362 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_363 = cvt(_T_362)
node _T_364 = and(_T_363, asSInt(UInt<17>(0h10000)))
node _T_365 = asSInt(_T_364)
node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0)))
node _T_367 = and(_T_361, _T_366)
node _T_368 = or(UInt<1>(0h0), _T_367)
node _T_369 = and(_T_360, _T_368)
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(_T_369, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_369, UInt<1>(0h1), "") : assert_46
node _T_373 = asUInt(reset)
node _T_374 = eq(_T_373, UInt<1>(0h0))
when _T_374 :
node _T_375 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_375 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(is_aligned, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_379 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_380 = asUInt(reset)
node _T_381 = eq(_T_380, UInt<1>(0h0))
when _T_381 :
node _T_382 = eq(_T_379, UInt<1>(0h0))
when _T_382 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_379, UInt<1>(0h1), "") : assert_49
node _T_383 = eq(io.in.a.bits.mask, mask)
node _T_384 = asUInt(reset)
node _T_385 = eq(_T_384, UInt<1>(0h0))
when _T_385 :
node _T_386 = eq(_T_383, UInt<1>(0h0))
when _T_386 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_383, UInt<1>(0h1), "") : assert_50
node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_387, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_391 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_392 = asUInt(reset)
node _T_393 = eq(_T_392, UInt<1>(0h0))
when _T_393 :
node _T_394 = eq(_T_391, UInt<1>(0h0))
when _T_394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_391, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 11)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_395 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_395 :
node _T_396 = asUInt(reset)
node _T_397 = eq(_T_396, UInt<1>(0h0))
when _T_397 :
node _T_398 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_398 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_399 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_400 = asUInt(reset)
node _T_401 = eq(_T_400, UInt<1>(0h0))
when _T_401 :
node _T_402 = eq(_T_399, UInt<1>(0h0))
when _T_402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_399, UInt<1>(0h1), "") : assert_54
node _T_403 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_404 = asUInt(reset)
node _T_405 = eq(_T_404, UInt<1>(0h0))
when _T_405 :
node _T_406 = eq(_T_403, UInt<1>(0h0))
when _T_406 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_403, UInt<1>(0h1), "") : assert_55
node _T_407 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_408 = asUInt(reset)
node _T_409 = eq(_T_408, UInt<1>(0h0))
when _T_409 :
node _T_410 = eq(_T_407, UInt<1>(0h0))
when _T_410 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_407, UInt<1>(0h1), "") : assert_56
node _T_411 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_411, UInt<1>(0h1), "") : assert_57
node _T_415 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_415 :
node _T_416 = asUInt(reset)
node _T_417 = eq(_T_416, UInt<1>(0h0))
when _T_417 :
node _T_418 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_418 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(sink_ok, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_422 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_423 = asUInt(reset)
node _T_424 = eq(_T_423, UInt<1>(0h0))
when _T_424 :
node _T_425 = eq(_T_422, UInt<1>(0h0))
when _T_425 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_422, UInt<1>(0h1), "") : assert_60
node _T_426 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(_T_426, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_426, UInt<1>(0h1), "") : assert_61
node _T_430 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_431 = asUInt(reset)
node _T_432 = eq(_T_431, UInt<1>(0h0))
when _T_432 :
node _T_433 = eq(_T_430, UInt<1>(0h0))
when _T_433 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_430, UInt<1>(0h1), "") : assert_62
node _T_434 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_435 = asUInt(reset)
node _T_436 = eq(_T_435, UInt<1>(0h0))
when _T_436 :
node _T_437 = eq(_T_434, UInt<1>(0h0))
when _T_437 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_434, UInt<1>(0h1), "") : assert_63
node _T_438 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_439 = or(UInt<1>(0h0), _T_438)
node _T_440 = asUInt(reset)
node _T_441 = eq(_T_440, UInt<1>(0h0))
when _T_441 :
node _T_442 = eq(_T_439, UInt<1>(0h0))
when _T_442 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_439, UInt<1>(0h1), "") : assert_64
node _T_443 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_443 :
node _T_444 = asUInt(reset)
node _T_445 = eq(_T_444, UInt<1>(0h0))
when _T_445 :
node _T_446 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_446 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(sink_ok, UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_450 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_451 = asUInt(reset)
node _T_452 = eq(_T_451, UInt<1>(0h0))
when _T_452 :
node _T_453 = eq(_T_450, UInt<1>(0h0))
when _T_453 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_450, UInt<1>(0h1), "") : assert_67
node _T_454 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_455 = asUInt(reset)
node _T_456 = eq(_T_455, UInt<1>(0h0))
when _T_456 :
node _T_457 = eq(_T_454, UInt<1>(0h0))
when _T_457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_454, UInt<1>(0h1), "") : assert_68
node _T_458 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_459 = asUInt(reset)
node _T_460 = eq(_T_459, UInt<1>(0h0))
when _T_460 :
node _T_461 = eq(_T_458, UInt<1>(0h0))
when _T_461 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_458, UInt<1>(0h1), "") : assert_69
node _T_462 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_463 = or(_T_462, io.in.d.bits.corrupt)
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_463, UInt<1>(0h1), "") : assert_70
node _T_467 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_468 = or(UInt<1>(0h0), _T_467)
node _T_469 = asUInt(reset)
node _T_470 = eq(_T_469, UInt<1>(0h0))
when _T_470 :
node _T_471 = eq(_T_468, UInt<1>(0h0))
when _T_471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_468, UInt<1>(0h1), "") : assert_71
node _T_472 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_472 :
node _T_473 = asUInt(reset)
node _T_474 = eq(_T_473, UInt<1>(0h0))
when _T_474 :
node _T_475 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_476 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_477 = asUInt(reset)
node _T_478 = eq(_T_477, UInt<1>(0h0))
when _T_478 :
node _T_479 = eq(_T_476, UInt<1>(0h0))
when _T_479 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_476, UInt<1>(0h1), "") : assert_73
node _T_480 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_481 = asUInt(reset)
node _T_482 = eq(_T_481, UInt<1>(0h0))
when _T_482 :
node _T_483 = eq(_T_480, UInt<1>(0h0))
when _T_483 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_480, UInt<1>(0h1), "") : assert_74
node _T_484 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_485 = or(UInt<1>(0h0), _T_484)
node _T_486 = asUInt(reset)
node _T_487 = eq(_T_486, UInt<1>(0h0))
when _T_487 :
node _T_488 = eq(_T_485, UInt<1>(0h0))
when _T_488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_485, UInt<1>(0h1), "") : assert_75
node _T_489 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_489 :
node _T_490 = asUInt(reset)
node _T_491 = eq(_T_490, UInt<1>(0h0))
when _T_491 :
node _T_492 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_492 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_493 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_494 = asUInt(reset)
node _T_495 = eq(_T_494, UInt<1>(0h0))
when _T_495 :
node _T_496 = eq(_T_493, UInt<1>(0h0))
when _T_496 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_493, UInt<1>(0h1), "") : assert_77
node _T_497 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_498 = or(_T_497, io.in.d.bits.corrupt)
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_498, UInt<1>(0h1), "") : assert_78
node _T_502 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_503 = or(UInt<1>(0h0), _T_502)
node _T_504 = asUInt(reset)
node _T_505 = eq(_T_504, UInt<1>(0h0))
when _T_505 :
node _T_506 = eq(_T_503, UInt<1>(0h0))
when _T_506 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_503, UInt<1>(0h1), "") : assert_79
node _T_507 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_507 :
node _T_508 = asUInt(reset)
node _T_509 = eq(_T_508, UInt<1>(0h0))
when _T_509 :
node _T_510 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_510 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_511 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_512 = asUInt(reset)
node _T_513 = eq(_T_512, UInt<1>(0h0))
when _T_513 :
node _T_514 = eq(_T_511, UInt<1>(0h0))
when _T_514 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_511, UInt<1>(0h1), "") : assert_81
node _T_515 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_516 = asUInt(reset)
node _T_517 = eq(_T_516, UInt<1>(0h0))
when _T_517 :
node _T_518 = eq(_T_515, UInt<1>(0h0))
when _T_518 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_515, UInt<1>(0h1), "") : assert_82
node _T_519 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_520 = or(UInt<1>(0h0), _T_519)
node _T_521 = asUInt(reset)
node _T_522 = eq(_T_521, UInt<1>(0h0))
when _T_522 :
node _T_523 = eq(_T_520, UInt<1>(0h0))
when _T_523 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_520, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<17>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_524 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_525 = asUInt(reset)
node _T_526 = eq(_T_525, UInt<1>(0h0))
when _T_526 :
node _T_527 = eq(_T_524, UInt<1>(0h0))
when _T_527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_524, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<17>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_528 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_529 = asUInt(reset)
node _T_530 = eq(_T_529, UInt<1>(0h0))
when _T_530 :
node _T_531 = eq(_T_528, UInt<1>(0h0))
when _T_531 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_528, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_532 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_533 = asUInt(reset)
node _T_534 = eq(_T_533, UInt<1>(0h0))
when _T_534 :
node _T_535 = eq(_T_532, UInt<1>(0h0))
when _T_535 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_532, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(UInt<1>(0h0), a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_536 = eq(a_first, UInt<1>(0h0))
node _T_537 = and(io.in.a.valid, _T_536)
when _T_537 :
node _T_538 = eq(io.in.a.bits.opcode, opcode)
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_538, UInt<1>(0h1), "") : assert_87
node _T_542 = eq(io.in.a.bits.param, param)
node _T_543 = asUInt(reset)
node _T_544 = eq(_T_543, UInt<1>(0h0))
when _T_544 :
node _T_545 = eq(_T_542, UInt<1>(0h0))
when _T_545 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_542, UInt<1>(0h1), "") : assert_88
node _T_546 = eq(io.in.a.bits.size, size)
node _T_547 = asUInt(reset)
node _T_548 = eq(_T_547, UInt<1>(0h0))
when _T_548 :
node _T_549 = eq(_T_546, UInt<1>(0h0))
when _T_549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_546, UInt<1>(0h1), "") : assert_89
node _T_550 = eq(io.in.a.bits.source, source)
node _T_551 = asUInt(reset)
node _T_552 = eq(_T_551, UInt<1>(0h0))
when _T_552 :
node _T_553 = eq(_T_550, UInt<1>(0h0))
when _T_553 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_550, UInt<1>(0h1), "") : assert_90
node _T_554 = eq(io.in.a.bits.address, address)
node _T_555 = asUInt(reset)
node _T_556 = eq(_T_555, UInt<1>(0h0))
when _T_556 :
node _T_557 = eq(_T_554, UInt<1>(0h0))
when _T_557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_554, UInt<1>(0h1), "") : assert_91
node _T_558 = and(io.in.a.ready, io.in.a.valid)
node _T_559 = and(_T_558, a_first)
when _T_559 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(UInt<1>(0h1), d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_560 = eq(d_first, UInt<1>(0h0))
node _T_561 = and(io.in.d.valid, _T_560)
when _T_561 :
node _T_562 = eq(io.in.d.bits.opcode, opcode_1)
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(_T_562, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_562, UInt<1>(0h1), "") : assert_92
node _T_566 = eq(io.in.d.bits.param, param_1)
node _T_567 = asUInt(reset)
node _T_568 = eq(_T_567, UInt<1>(0h0))
when _T_568 :
node _T_569 = eq(_T_566, UInt<1>(0h0))
when _T_569 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_566, UInt<1>(0h1), "") : assert_93
node _T_570 = eq(io.in.d.bits.size, size_1)
node _T_571 = asUInt(reset)
node _T_572 = eq(_T_571, UInt<1>(0h0))
when _T_572 :
node _T_573 = eq(_T_570, UInt<1>(0h0))
when _T_573 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_570, UInt<1>(0h1), "") : assert_94
node _T_574 = eq(io.in.d.bits.source, source_1)
node _T_575 = asUInt(reset)
node _T_576 = eq(_T_575, UInt<1>(0h0))
when _T_576 :
node _T_577 = eq(_T_574, UInt<1>(0h0))
when _T_577 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_574, UInt<1>(0h1), "") : assert_95
node _T_578 = eq(io.in.d.bits.sink, sink)
node _T_579 = asUInt(reset)
node _T_580 = eq(_T_579, UInt<1>(0h0))
when _T_580 :
node _T_581 = eq(_T_578, UInt<1>(0h0))
when _T_581 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_578, UInt<1>(0h1), "") : assert_96
node _T_582 = eq(io.in.d.bits.denied, denied)
node _T_583 = asUInt(reset)
node _T_584 = eq(_T_583, UInt<1>(0h0))
when _T_584 :
node _T_585 = eq(_T_582, UInt<1>(0h0))
when _T_585 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_582, UInt<1>(0h1), "") : assert_97
node _T_586 = and(io.in.d.ready, io.in.d.valid)
node _T_587 = and(_T_586, d_first)
when _T_587 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(UInt<1>(0h0), a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(UInt<1>(0h1), d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1040>
connect a_set, UInt<1040>(0h0)
wire a_set_wo_ready : UInt<1040>
connect a_set_wo_ready, UInt<1040>(0h0)
wire a_opcodes_set : UInt<4160>
connect a_opcodes_set, UInt<4160>(0h0)
wire a_sizes_set : UInt<4160>
connect a_sizes_set, UInt<4160>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_588 = and(io.in.a.valid, a_first_1)
node _T_589 = and(_T_588, UInt<1>(0h1))
when _T_589 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_590 = and(io.in.a.ready, io.in.a.valid)
node _T_591 = and(_T_590, a_first_1)
node _T_592 = and(_T_591, UInt<1>(0h1))
when _T_592 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_593 = dshr(inflight, io.in.a.bits.source)
node _T_594 = bits(_T_593, 0, 0)
node _T_595 = eq(_T_594, UInt<1>(0h0))
node _T_596 = asUInt(reset)
node _T_597 = eq(_T_596, UInt<1>(0h0))
when _T_597 :
node _T_598 = eq(_T_595, UInt<1>(0h0))
when _T_598 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_595, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1040>
connect d_clr, UInt<1040>(0h0)
wire d_clr_wo_ready : UInt<1040>
connect d_clr_wo_ready, UInt<1040>(0h0)
wire d_opcodes_clr : UInt<4160>
connect d_opcodes_clr, UInt<4160>(0h0)
wire d_sizes_clr : UInt<4160>
connect d_sizes_clr, UInt<4160>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_599 = and(io.in.d.valid, d_first_1)
node _T_600 = and(_T_599, UInt<1>(0h1))
node _T_601 = eq(d_release_ack, UInt<1>(0h0))
node _T_602 = and(_T_600, _T_601)
when _T_602 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_603 = and(io.in.d.ready, io.in.d.valid)
node _T_604 = and(_T_603, d_first_1)
node _T_605 = and(_T_604, UInt<1>(0h1))
node _T_606 = eq(d_release_ack, UInt<1>(0h0))
node _T_607 = and(_T_605, _T_606)
when _T_607 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_608 = and(io.in.d.valid, d_first_1)
node _T_609 = and(_T_608, UInt<1>(0h1))
node _T_610 = eq(d_release_ack, UInt<1>(0h0))
node _T_611 = and(_T_609, _T_610)
when _T_611 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_612 = dshr(inflight, io.in.d.bits.source)
node _T_613 = bits(_T_612, 0, 0)
node _T_614 = or(_T_613, same_cycle_resp)
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(_T_614, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_614, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_618 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_619 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_620 = or(_T_618, _T_619)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_620, UInt<1>(0h1), "") : assert_100
node _T_624 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_625 = asUInt(reset)
node _T_626 = eq(_T_625, UInt<1>(0h0))
when _T_626 :
node _T_627 = eq(_T_624, UInt<1>(0h0))
when _T_627 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_624, UInt<1>(0h1), "") : assert_101
else :
node _T_628 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_629 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_630 = or(_T_628, _T_629)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_630, UInt<1>(0h1), "") : assert_102
node _T_634 = eq(io.in.d.bits.size, a_size_lookup)
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_T_634, UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_634, UInt<1>(0h1), "") : assert_103
node _T_638 = and(io.in.d.valid, d_first_1)
node _T_639 = and(_T_638, a_first_1)
node _T_640 = and(_T_639, io.in.a.valid)
node _T_641 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_642 = and(_T_640, _T_641)
node _T_643 = eq(d_release_ack, UInt<1>(0h0))
node _T_644 = and(_T_642, _T_643)
when _T_644 :
node _T_645 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_646 = or(_T_645, io.in.a.ready)
node _T_647 = asUInt(reset)
node _T_648 = eq(_T_647, UInt<1>(0h0))
when _T_648 :
node _T_649 = eq(_T_646, UInt<1>(0h0))
when _T_649 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_646, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_77
node _T_650 = orr(inflight)
node _T_651 = eq(_T_650, UInt<1>(0h0))
node _T_652 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_653 = or(_T_651, _T_652)
node _T_654 = lt(watchdog, plusarg_reader.out)
node _T_655 = or(_T_653, _T_654)
node _T_656 = asUInt(reset)
node _T_657 = eq(_T_656, UInt<1>(0h0))
when _T_657 :
node _T_658 = eq(_T_655, UInt<1>(0h0))
when _T_658 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_655, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_659 = and(io.in.a.ready, io.in.a.valid)
node _T_660 = and(io.in.d.ready, io.in.d.valid)
node _T_661 = or(_T_659, _T_660)
when _T_661 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<17>(0h0)
connect _c_first_WIRE.bits.source, UInt<11>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<17>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(UInt<1>(0h1), d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1040>
connect c_set, UInt<1040>(0h0)
wire c_set_wo_ready : UInt<1040>
connect c_set_wo_ready, UInt<1040>(0h0)
wire c_opcodes_set : UInt<4160>
connect c_opcodes_set, UInt<4160>(0h0)
wire c_sizes_set : UInt<4160>
connect c_sizes_set, UInt<4160>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<17>(0h0)
connect _WIRE_6.bits.source, UInt<11>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_662 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<17>(0h0)
connect _WIRE_8.bits.source, UInt<11>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_663 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_664 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_665 = and(_T_663, _T_664)
node _T_666 = and(_T_662, _T_665)
when _T_666 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<17>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<17>(0h0)
connect _WIRE_10.bits.source, UInt<11>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_667 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_668 = and(_T_667, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<17>(0h0)
connect _WIRE_12.bits.source, UInt<11>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_669 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_670 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_671 = and(_T_669, _T_670)
node _T_672 = and(_T_668, _T_671)
when _T_672 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<17>(0h0)
connect _c_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<17>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<17>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<17>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<17>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<17>(0h0)
connect _WIRE_14.bits.source, UInt<11>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_673 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_674 = bits(_T_673, 0, 0)
node _T_675 = eq(_T_674, UInt<1>(0h0))
node _T_676 = asUInt(reset)
node _T_677 = eq(_T_676, UInt<1>(0h0))
when _T_677 :
node _T_678 = eq(_T_675, UInt<1>(0h0))
when _T_678 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_675, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<17>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<17>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1040>
connect d_clr_1, UInt<1040>(0h0)
wire d_clr_wo_ready_1 : UInt<1040>
connect d_clr_wo_ready_1, UInt<1040>(0h0)
wire d_opcodes_clr_1 : UInt<4160>
connect d_opcodes_clr_1, UInt<4160>(0h0)
wire d_sizes_clr_1 : UInt<4160>
connect d_sizes_clr_1, UInt<4160>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_679 = and(io.in.d.valid, d_first_2)
node _T_680 = and(_T_679, UInt<1>(0h1))
node _T_681 = and(_T_680, d_release_ack_1)
when _T_681 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_682 = and(io.in.d.ready, io.in.d.valid)
node _T_683 = and(_T_682, d_first_2)
node _T_684 = and(_T_683, UInt<1>(0h1))
node _T_685 = and(_T_684, d_release_ack_1)
when _T_685 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_686 = and(io.in.d.valid, d_first_2)
node _T_687 = and(_T_686, UInt<1>(0h1))
node _T_688 = and(_T_687, d_release_ack_1)
when _T_688 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<17>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<17>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<17>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_689 = dshr(inflight_1, io.in.d.bits.source)
node _T_690 = bits(_T_689, 0, 0)
node _T_691 = or(_T_690, same_cycle_resp_1)
node _T_692 = asUInt(reset)
node _T_693 = eq(_T_692, UInt<1>(0h0))
when _T_693 :
node _T_694 = eq(_T_691, UInt<1>(0h0))
when _T_694 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_691, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<17>(0h0)
connect _WIRE_16.bits.source, UInt<11>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_695 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_696 = asUInt(reset)
node _T_697 = eq(_T_696, UInt<1>(0h0))
when _T_697 :
node _T_698 = eq(_T_695, UInt<1>(0h0))
when _T_698 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_695, UInt<1>(0h1), "") : assert_108
else :
node _T_699 = eq(io.in.d.bits.size, c_size_lookup)
node _T_700 = asUInt(reset)
node _T_701 = eq(_T_700, UInt<1>(0h0))
when _T_701 :
node _T_702 = eq(_T_699, UInt<1>(0h0))
when _T_702 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_699, UInt<1>(0h1), "") : assert_109
node _T_703 = and(io.in.d.valid, d_first_2)
node _T_704 = and(_T_703, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<17>(0h0)
connect _WIRE_18.bits.source, UInt<11>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_705 = and(_T_704, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<17>(0h0)
connect _WIRE_20.bits.source, UInt<11>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_706 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_707 = and(_T_705, _T_706)
node _T_708 = and(_T_707, d_release_ack_1)
node _T_709 = eq(c_probe_ack, UInt<1>(0h0))
node _T_710 = and(_T_708, _T_709)
when _T_710 :
node _T_711 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<17>(0h0)
connect _WIRE_22.bits.source, UInt<11>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_712 = or(_T_711, _WIRE_23.ready)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_78
node _T_716 = orr(inflight_1)
node _T_717 = eq(_T_716, UInt<1>(0h0))
node _T_718 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_719 = or(_T_717, _T_718)
node _T_720 = lt(watchdog_1, plusarg_reader_1.out)
node _T_721 = or(_T_719, _T_720)
node _T_722 = asUInt(reset)
node _T_723 = eq(_T_722, UInt<1>(0h0))
when _T_723 :
node _T_724 = eq(_T_721, UInt<1>(0h0))
when _T_724 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_721, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<17>(0h0)
connect _WIRE_24.bits.source, UInt<11>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_725 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_726 = and(io.in.d.ready, io.in.d.valid)
node _T_727 = or(_T_725, _T_726)
when _T_727 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_38( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_release_ack = 1'h0; // @[Monitor.scala:673:46]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire d_first_beats1_opdata = 1'h1; // @[Edges.scala:106:36]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire d_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:106:36]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire d_first_beats1_opdata_2 = 1'h1; // @[Edges.scala:106:36]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [2:0] io_in_d_bits_opcode = 3'h1; // @[Monitor.scala:36:7]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [4159:0] _inflight_opcodes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62]
wire [4159:0] _inflight_sizes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58]
wire [1039:0] _inflight_T_4 = 1040'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_first_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_first_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_first_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_first_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34]
wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34]
wire [4159:0] d_opcodes_clr_1 = 4160'h0; // @[Monitor.scala:776:34]
wire [4159:0] d_sizes_clr_1 = 4160'h0; // @[Monitor.scala:777:34]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34]
wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34]
wire [1039:0] d_clr_1 = 1040'h0; // @[Monitor.scala:774:34]
wire [1039:0] d_clr_wo_ready_1 = 1040'h0; // @[Monitor.scala:775:34]
wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52]
wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79]
wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77]
wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35]
wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [16:0] _is_aligned_T = {14'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_659 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_659; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_659; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [16:0] address; // @[Monitor.scala:391:22]
wire _T_727 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_727; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_727; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_727; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [1039:0] a_set; // @[Monitor.scala:626:34]
wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_592 = _T_659 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_592 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_592 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_592 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_592 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_592 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [1039:0] d_clr; // @[Monitor.scala:664:34]
wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _T_638 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [2047:0] _GEN_4 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_638 ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_605 = _T_727 & d_first_1; // @[Decoupled.scala:51:35]
assign d_clr = _T_605 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_605 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}]
wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_605 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113]
wire [1039:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}]
wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}]
wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue_9 :
input clock : Clock
input reset : Reset
output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, flip brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt<21>}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<4>}
inst main of BranchKillableQueue_8
connect main.clock, clock
connect main.reset, reset
reg out_reg : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, clock
regreset out_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock
connect main.io.enq, io.enq
connect main.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect main.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect main.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect main.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect main.io.brupdate.b2.taken, io.brupdate.b2.taken
connect main.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect main.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect main.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect main.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect main.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect main.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect main.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect main.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect main.io.brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect main.io.brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect main.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect main.io.brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect main.io.brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect main.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect main.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect main.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect main.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect main.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect main.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect main.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect main.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect main.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect main.io.brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect main.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect main.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect main.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect main.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect main.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect main.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect main.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect main.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect main.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect main.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect main.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect main.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect main.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect main.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect main.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect main.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect main.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect main.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect main.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect main.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect main.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect main.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect main.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect main.io.brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect main.io.brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect main.io.brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect main.io.brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect main.io.brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect main.io.brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect main.io.brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect main.io.brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect main.io.brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect main.io.brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect main.io.brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect main.io.brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect main.io.brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect main.io.brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect main.io.brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect main.io.brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect main.io.brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect main.io.brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect main.io.brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect main.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect main.io.brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect main.io.brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect main.io.brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect main.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect main.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect main.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect main.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect main.io.brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect main.io.brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect main.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect main.io.brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect main.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect main.io.brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect main.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect main.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect main.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect main.io.brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect main.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect main.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect main.io.brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect main.io.brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect main.io.brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect main.io.brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect main.io.brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect main.io.brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect main.io.brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect main.io.brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect main.io.brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect main.io.brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect main.io.brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect main.io.brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect main.io.brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect main.io.brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect main.io.brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect main.io.brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect main.io.brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect main.io.brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect main.io.brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect main.io.brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect main.io.brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect main.io.brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect main.io.brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect main.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect main.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect main.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect main.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect main.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect main.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect main.io.flush, io.flush
node _io_empty_T = eq(out_valid, UInt<1>(0h0))
node _io_empty_T_1 = and(main.io.empty, _io_empty_T)
connect io.empty, _io_empty_T_1
node _io_count_T = add(main.io.count, out_valid)
node _io_count_T_1 = tail(_io_count_T, 1)
connect io.count, _io_count_T_1
connect io.deq.valid, out_valid
connect io.deq.bits, out_reg
connect io.deq.bits.uop, out_uop
wire out_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect out_uop_out, out_uop
node _out_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _out_uop_out_br_mask_T_1 = and(out_uop.br_mask, _out_uop_out_br_mask_T)
connect out_uop_out.br_mask, _out_uop_out_br_mask_T_1
connect out_uop, out_uop_out
node _out_valid_T = and(io.brupdate.b1.mispredict_mask, out_uop.br_mask)
node _out_valid_T_1 = neq(_out_valid_T, UInt<1>(0h0))
node _out_valid_T_2 = or(_out_valid_T_1, UInt<1>(0h0))
node _out_valid_T_3 = eq(_out_valid_T_2, UInt<1>(0h0))
node _out_valid_T_4 = and(out_valid, _out_valid_T_3)
node _out_valid_T_5 = and(io.flush, out_uop.uses_ldq)
node _out_valid_T_6 = eq(_out_valid_T_5, UInt<1>(0h0))
node _out_valid_T_7 = and(_out_valid_T_4, _out_valid_T_6)
connect out_valid, _out_valid_T_7
connect main.io.deq.ready, UInt<1>(0h0)
node _T = and(io.deq.ready, io.deq.valid)
node _T_1 = eq(out_valid, UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
when _T_2 :
node _out_valid_T_8 = and(io.brupdate.b1.mispredict_mask, main.io.deq.bits.uop.br_mask)
node _out_valid_T_9 = neq(_out_valid_T_8, UInt<1>(0h0))
node _out_valid_T_10 = or(_out_valid_T_9, UInt<1>(0h0))
node _out_valid_T_11 = eq(_out_valid_T_10, UInt<1>(0h0))
node _out_valid_T_12 = and(main.io.deq.valid, _out_valid_T_11)
node _out_valid_T_13 = and(io.flush, main.io.deq.bits.uop.uses_ldq)
node _out_valid_T_14 = eq(_out_valid_T_13, UInt<1>(0h0))
node _out_valid_T_15 = and(_out_valid_T_12, _out_valid_T_14)
connect out_valid, _out_valid_T_15
connect out_reg, main.io.deq.bits
wire out_uop_out_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect out_uop_out_1, main.io.deq.bits.uop
node _out_uop_out_br_mask_T_2 = not(io.brupdate.b1.resolve_mask)
node _out_uop_out_br_mask_T_3 = and(main.io.deq.bits.uop.br_mask, _out_uop_out_br_mask_T_2)
connect out_uop_out_1.br_mask, _out_uop_out_br_mask_T_3
connect out_uop, out_uop_out_1
connect main.io.deq.ready, UInt<1>(0h1) | module BranchKillableQueue_9( // @[util.scala:458:7]
input clock, // @[util.scala:458:7]
input reset, // @[util.scala:458:7]
output io_enq_ready, // @[util.scala:463:14]
input io_enq_valid, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14]
input io_enq_bits_uop_is_rvc, // @[util.scala:463:14]
input [33:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfb, // @[util.scala:463:14]
input io_enq_bits_uop_is_fence, // @[util.scala:463:14]
input io_enq_bits_uop_is_fencei, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfence, // @[util.scala:463:14]
input io_enq_bits_uop_is_amo, // @[util.scala:463:14]
input io_enq_bits_uop_is_eret, // @[util.scala:463:14]
input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
input io_enq_bits_uop_is_rocc, // @[util.scala:463:14]
input io_enq_bits_uop_is_mov, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14]
input io_enq_bits_uop_edge_inst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14]
input io_enq_bits_uop_taken, // @[util.scala:463:14]
input io_enq_bits_uop_imm_rename, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14]
input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_pdst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_prs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_prs2, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_prs3, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_ppred, // @[util.scala:463:14]
input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14]
input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14]
input io_enq_bits_uop_exception, // @[util.scala:463:14]
input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14]
input io_enq_bits_uop_mem_signed, // @[util.scala:463:14]
input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14]
input io_enq_bits_uop_uses_stq, // @[util.scala:463:14]
input io_enq_bits_uop_is_unique, // @[util.scala:463:14]
input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14]
input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
input io_enq_bits_uop_frs3_en, // @[util.scala:463:14]
input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14]
input io_enq_bits_uop_fp_val, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14]
input [33:0] io_enq_bits_addr, // @[util.scala:463:14]
input [63:0] io_enq_bits_data, // @[util.scala:463:14]
input io_enq_bits_is_hella, // @[util.scala:463:14]
input io_enq_bits_tag_match, // @[util.scala:463:14]
input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:463:14]
input [21:0] io_enq_bits_old_meta_tag, // @[util.scala:463:14]
input [1:0] io_enq_bits_way_en, // @[util.scala:463:14]
input [4:0] io_enq_bits_sdq_id, // @[util.scala:463:14]
input io_deq_ready, // @[util.scala:463:14]
output io_deq_valid, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14]
output io_deq_bits_uop_is_rvc, // @[util.scala:463:14]
output [33:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfb, // @[util.scala:463:14]
output io_deq_bits_uop_is_fence, // @[util.scala:463:14]
output io_deq_bits_uop_is_fencei, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfence, // @[util.scala:463:14]
output io_deq_bits_uop_is_amo, // @[util.scala:463:14]
output io_deq_bits_uop_is_eret, // @[util.scala:463:14]
output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
output io_deq_bits_uop_is_rocc, // @[util.scala:463:14]
output io_deq_bits_uop_is_mov, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14]
output io_deq_bits_uop_edge_inst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14]
output io_deq_bits_uop_taken, // @[util.scala:463:14]
output io_deq_bits_uop_imm_rename, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14]
output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_pdst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_prs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_prs2, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_prs3, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_ppred, // @[util.scala:463:14]
output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14]
output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14]
output io_deq_bits_uop_exception, // @[util.scala:463:14]
output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14]
output io_deq_bits_uop_mem_signed, // @[util.scala:463:14]
output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14]
output io_deq_bits_uop_uses_stq, // @[util.scala:463:14]
output io_deq_bits_uop_is_unique, // @[util.scala:463:14]
output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14]
output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
output io_deq_bits_uop_frs3_en, // @[util.scala:463:14]
output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14]
output io_deq_bits_uop_fp_val, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14]
output [33:0] io_deq_bits_addr, // @[util.scala:463:14]
output [63:0] io_deq_bits_data, // @[util.scala:463:14]
output io_deq_bits_is_hella, // @[util.scala:463:14]
output io_deq_bits_tag_match, // @[util.scala:463:14]
output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:463:14]
output [21:0] io_deq_bits_old_meta_tag, // @[util.scala:463:14]
output [1:0] io_deq_bits_way_en, // @[util.scala:463:14]
output [4:0] io_deq_bits_sdq_id, // @[util.scala:463:14]
output io_empty // @[util.scala:463:14]
);
wire _out_valid_T_12; // @[util.scala:496:38]
wire [31:0] _main_io_deq_bits_uop_inst; // @[util.scala:476:22]
wire [31:0] _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22]
wire [33:0] _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_br_type; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_taken; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_pimm; // @[util.scala:476:22]
wire [19:0] _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_pdst; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_prs1; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_prs2; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_prs3; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_ppred; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_exception; // @[util.scala:476:22]
wire [63:0] _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_ldst; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22]
wire [33:0] _main_io_deq_bits_addr; // @[util.scala:476:22]
wire [63:0] _main_io_deq_bits_data; // @[util.scala:476:22]
wire _main_io_deq_bits_is_hella; // @[util.scala:476:22]
wire _main_io_deq_bits_tag_match; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22]
wire [21:0] _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_way_en; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_sdq_id; // @[util.scala:476:22]
wire _main_io_empty; // @[util.scala:476:22]
wire [3:0] _main_io_count; // @[util.scala:476:22]
wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7]
wire [33:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7]
wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7]
wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7]
wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7]
wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7]
wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7]
wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7]
wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7]
wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7]
wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7]
wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7]
wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7]
wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7]
wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7]
wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7]
wire [33:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:458:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7]
wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:458:7]
wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:458:7]
wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:458:7]
wire [21:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:458:7]
wire [1:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:458:7]
wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:458:7]
wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7]
wire _out_valid_T_3 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}]
wire _out_valid_T_6 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}]
wire _out_valid_T_11 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}]
wire _out_valid_T_14 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}]
wire [3:0] _out_uop_out_br_mask_T = 4'hF; // @[util.scala:93:27]
wire [3:0] _out_uop_out_br_mask_T_2 = 4'hF; // @[util.scala:93:27]
wire [20:0] io_brupdate_b2_target_offset = 21'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [4:0] io_brupdate_b2_uop_pimm = 5'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [4:0] io_brupdate_b2_uop_rob_idx = 5'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [4:0] io_brupdate_b2_uop_fcn_op = 5'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_uop_imm_sel = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_uop_op2_sel = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_uop_csr_cmd = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_uop_fp_rm = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_uop_debug_fsrc = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_uop_debug_tsrc = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_pdst = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_prs1 = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_prs2 = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_prs3 = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_stale_pdst = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_op1_sel = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_fp_typ = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[util.scala:458:7, :463:14, :476:22]
wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_0 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_1 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_2 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_3 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_0 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_1 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_2 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_3 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_4 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_5 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_6 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_7 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_8 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_9 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p1_speculative_child = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p2_speculative_child = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_dis_col_sel = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fence = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfence = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_amo = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_eret = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_rocc = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_mov = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_taken = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_imm_rename = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wen = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_toint = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fma = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_div = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_vec = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_exception = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_unique = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fcn_dw = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_val = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_mispredict = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_taken = 1'h0; // @[util.scala:458:7]
wire io_flush = 1'h0; // @[util.scala:458:7]
wire _out_valid_T_1 = 1'h0; // @[util.scala:126:59]
wire _out_valid_T_2 = 1'h0; // @[util.scala:61:61]
wire _out_valid_T_5 = 1'h0; // @[util.scala:492:94]
wire _out_valid_T_9 = 1'h0; // @[util.scala:126:59]
wire _out_valid_T_10 = 1'h0; // @[util.scala:61:61]
wire _out_valid_T_13 = 1'h0; // @[util.scala:496:117]
wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b2_uop_br_type = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] _out_valid_T = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] _out_valid_T_8 = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire _io_empty_T_1; // @[util.scala:484:31]
wire [3:0] _io_count_T_1; // @[util.scala:485:31]
wire io_enq_ready_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
wire [33:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
wire io_deq_bits_uop_taken_0; // @[util.scala:458:7]
wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_exception_0; // @[util.scala:458:7]
wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7]
wire [21:0] io_deq_bits_old_meta_tag_0; // @[util.scala:458:7]
wire [33:0] io_deq_bits_addr_0; // @[util.scala:458:7]
wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7]
wire io_deq_bits_is_hella_0; // @[util.scala:458:7]
wire io_deq_bits_tag_match_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_way_en_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:458:7]
wire io_deq_valid_0; // @[util.scala:458:7]
wire io_empty_0; // @[util.scala:458:7]
wire [3:0] io_count; // @[util.scala:458:7]
reg [31:0] out_reg_uop_inst; // @[util.scala:477:22]
reg [31:0] out_reg_uop_debug_inst; // @[util.scala:477:22]
reg out_reg_uop_is_rvc; // @[util.scala:477:22]
reg [33:0] out_reg_uop_debug_pc; // @[util.scala:477:22]
reg out_reg_uop_iq_type_0; // @[util.scala:477:22]
reg out_reg_uop_iq_type_1; // @[util.scala:477:22]
reg out_reg_uop_iq_type_2; // @[util.scala:477:22]
reg out_reg_uop_iq_type_3; // @[util.scala:477:22]
reg out_reg_uop_fu_code_0; // @[util.scala:477:22]
reg out_reg_uop_fu_code_1; // @[util.scala:477:22]
reg out_reg_uop_fu_code_2; // @[util.scala:477:22]
reg out_reg_uop_fu_code_3; // @[util.scala:477:22]
reg out_reg_uop_fu_code_4; // @[util.scala:477:22]
reg out_reg_uop_fu_code_5; // @[util.scala:477:22]
reg out_reg_uop_fu_code_6; // @[util.scala:477:22]
reg out_reg_uop_fu_code_7; // @[util.scala:477:22]
reg out_reg_uop_fu_code_8; // @[util.scala:477:22]
reg out_reg_uop_fu_code_9; // @[util.scala:477:22]
reg out_reg_uop_iw_issued; // @[util.scala:477:22]
reg out_reg_uop_iw_issued_partial_agen; // @[util.scala:477:22]
reg out_reg_uop_iw_issued_partial_dgen; // @[util.scala:477:22]
reg out_reg_uop_iw_p1_speculative_child; // @[util.scala:477:22]
reg out_reg_uop_iw_p2_speculative_child; // @[util.scala:477:22]
reg out_reg_uop_iw_p1_bypass_hint; // @[util.scala:477:22]
reg out_reg_uop_iw_p2_bypass_hint; // @[util.scala:477:22]
reg out_reg_uop_iw_p3_bypass_hint; // @[util.scala:477:22]
reg out_reg_uop_dis_col_sel; // @[util.scala:477:22]
reg [3:0] out_reg_uop_br_mask; // @[util.scala:477:22]
reg [1:0] out_reg_uop_br_tag; // @[util.scala:477:22]
reg [3:0] out_reg_uop_br_type; // @[util.scala:477:22]
reg out_reg_uop_is_sfb; // @[util.scala:477:22]
reg out_reg_uop_is_fence; // @[util.scala:477:22]
reg out_reg_uop_is_fencei; // @[util.scala:477:22]
reg out_reg_uop_is_sfence; // @[util.scala:477:22]
reg out_reg_uop_is_amo; // @[util.scala:477:22]
reg out_reg_uop_is_eret; // @[util.scala:477:22]
reg out_reg_uop_is_sys_pc2epc; // @[util.scala:477:22]
reg out_reg_uop_is_rocc; // @[util.scala:477:22]
reg out_reg_uop_is_mov; // @[util.scala:477:22]
reg [3:0] out_reg_uop_ftq_idx; // @[util.scala:477:22]
reg out_reg_uop_edge_inst; // @[util.scala:477:22]
reg [5:0] out_reg_uop_pc_lob; // @[util.scala:477:22]
reg out_reg_uop_taken; // @[util.scala:477:22]
reg out_reg_uop_imm_rename; // @[util.scala:477:22]
reg [2:0] out_reg_uop_imm_sel; // @[util.scala:477:22]
reg [4:0] out_reg_uop_pimm; // @[util.scala:477:22]
reg [19:0] out_reg_uop_imm_packed; // @[util.scala:477:22]
reg [1:0] out_reg_uop_op1_sel; // @[util.scala:477:22]
reg [2:0] out_reg_uop_op2_sel; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ldst; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_wen; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ren1; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ren2; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ren3; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_swap12; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_swap23; // @[util.scala:477:22]
reg [1:0] out_reg_uop_fp_ctrl_typeTagIn; // @[util.scala:477:22]
reg [1:0] out_reg_uop_fp_ctrl_typeTagOut; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_fromint; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_toint; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_fastpipe; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_fma; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_div; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_sqrt; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_wflags; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_vec; // @[util.scala:477:22]
reg [4:0] out_reg_uop_rob_idx; // @[util.scala:477:22]
reg [3:0] out_reg_uop_ldq_idx; // @[util.scala:477:22]
reg [3:0] out_reg_uop_stq_idx; // @[util.scala:477:22]
reg [1:0] out_reg_uop_rxq_idx; // @[util.scala:477:22]
reg [5:0] out_reg_uop_pdst; // @[util.scala:477:22]
reg [5:0] out_reg_uop_prs1; // @[util.scala:477:22]
reg [5:0] out_reg_uop_prs2; // @[util.scala:477:22]
reg [5:0] out_reg_uop_prs3; // @[util.scala:477:22]
reg [3:0] out_reg_uop_ppred; // @[util.scala:477:22]
reg out_reg_uop_prs1_busy; // @[util.scala:477:22]
reg out_reg_uop_prs2_busy; // @[util.scala:477:22]
reg out_reg_uop_prs3_busy; // @[util.scala:477:22]
reg out_reg_uop_ppred_busy; // @[util.scala:477:22]
reg [5:0] out_reg_uop_stale_pdst; // @[util.scala:477:22]
reg out_reg_uop_exception; // @[util.scala:477:22]
reg [63:0] out_reg_uop_exc_cause; // @[util.scala:477:22]
reg [4:0] out_reg_uop_mem_cmd; // @[util.scala:477:22]
reg [1:0] out_reg_uop_mem_size; // @[util.scala:477:22]
reg out_reg_uop_mem_signed; // @[util.scala:477:22]
reg out_reg_uop_uses_ldq; // @[util.scala:477:22]
reg out_reg_uop_uses_stq; // @[util.scala:477:22]
reg out_reg_uop_is_unique; // @[util.scala:477:22]
reg out_reg_uop_flush_on_commit; // @[util.scala:477:22]
reg [2:0] out_reg_uop_csr_cmd; // @[util.scala:477:22]
reg out_reg_uop_ldst_is_rs1; // @[util.scala:477:22]
reg [5:0] out_reg_uop_ldst; // @[util.scala:477:22]
reg [5:0] out_reg_uop_lrs1; // @[util.scala:477:22]
reg [5:0] out_reg_uop_lrs2; // @[util.scala:477:22]
reg [5:0] out_reg_uop_lrs3; // @[util.scala:477:22]
reg [1:0] out_reg_uop_dst_rtype; // @[util.scala:477:22]
reg [1:0] out_reg_uop_lrs1_rtype; // @[util.scala:477:22]
reg [1:0] out_reg_uop_lrs2_rtype; // @[util.scala:477:22]
reg out_reg_uop_frs3_en; // @[util.scala:477:22]
reg out_reg_uop_fcn_dw; // @[util.scala:477:22]
reg [4:0] out_reg_uop_fcn_op; // @[util.scala:477:22]
reg out_reg_uop_fp_val; // @[util.scala:477:22]
reg [2:0] out_reg_uop_fp_rm; // @[util.scala:477:22]
reg [1:0] out_reg_uop_fp_typ; // @[util.scala:477:22]
reg out_reg_uop_xcpt_pf_if; // @[util.scala:477:22]
reg out_reg_uop_xcpt_ae_if; // @[util.scala:477:22]
reg out_reg_uop_xcpt_ma_if; // @[util.scala:477:22]
reg out_reg_uop_bp_debug_if; // @[util.scala:477:22]
reg out_reg_uop_bp_xcpt_if; // @[util.scala:477:22]
reg [2:0] out_reg_uop_debug_fsrc; // @[util.scala:477:22]
reg [2:0] out_reg_uop_debug_tsrc; // @[util.scala:477:22]
reg [33:0] out_reg_addr; // @[util.scala:477:22]
assign io_deq_bits_addr_0 = out_reg_addr; // @[util.scala:458:7, :477:22]
reg [63:0] out_reg_data; // @[util.scala:477:22]
assign io_deq_bits_data_0 = out_reg_data; // @[util.scala:458:7, :477:22]
reg out_reg_is_hella; // @[util.scala:477:22]
assign io_deq_bits_is_hella_0 = out_reg_is_hella; // @[util.scala:458:7, :477:22]
reg out_reg_tag_match; // @[util.scala:477:22]
assign io_deq_bits_tag_match_0 = out_reg_tag_match; // @[util.scala:458:7, :477:22]
reg [1:0] out_reg_old_meta_coh_state; // @[util.scala:477:22]
assign io_deq_bits_old_meta_coh_state_0 = out_reg_old_meta_coh_state; // @[util.scala:458:7, :477:22]
reg [21:0] out_reg_old_meta_tag; // @[util.scala:477:22]
assign io_deq_bits_old_meta_tag_0 = out_reg_old_meta_tag; // @[util.scala:458:7, :477:22]
reg [1:0] out_reg_way_en; // @[util.scala:477:22]
assign io_deq_bits_way_en_0 = out_reg_way_en; // @[util.scala:458:7, :477:22]
reg [4:0] out_reg_sdq_id; // @[util.scala:477:22]
assign io_deq_bits_sdq_id_0 = out_reg_sdq_id; // @[util.scala:458:7, :477:22]
reg out_valid; // @[util.scala:478:28]
assign io_deq_valid_0 = out_valid; // @[util.scala:458:7, :478:28]
wire _out_valid_T_4 = out_valid; // @[util.scala:478:28, :492:28]
reg [31:0] out_uop_inst; // @[util.scala:479:22]
assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :479:22]
wire [31:0] out_uop_out_inst = out_uop_inst; // @[util.scala:104:23, :479:22]
reg [31:0] out_uop_debug_inst; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :479:22]
wire [31:0] out_uop_out_debug_inst = out_uop_debug_inst; // @[util.scala:104:23, :479:22]
reg out_uop_is_rvc; // @[util.scala:479:22]
assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_rvc = out_uop_is_rvc; // @[util.scala:104:23, :479:22]
reg [33:0] out_uop_debug_pc; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :479:22]
wire [33:0] out_uop_out_debug_pc = out_uop_debug_pc; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_0; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_0 = out_uop_iq_type_0; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_1; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_1 = out_uop_iq_type_1; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_2; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_2 = out_uop_iq_type_2; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_3; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_3 = out_uop_iq_type_3; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_0; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_0 = out_uop_fu_code_0; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_1; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_1 = out_uop_fu_code_1; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_2; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_2 = out_uop_fu_code_2; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_3; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_3 = out_uop_fu_code_3; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_4; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_4 = out_uop_fu_code_4; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_5; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_5 = out_uop_fu_code_5; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_6; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_6 = out_uop_fu_code_6; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_7; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_7 = out_uop_fu_code_7; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_8; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_8 = out_uop_fu_code_8; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_9; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_9 = out_uop_fu_code_9; // @[util.scala:104:23, :479:22]
reg out_uop_iw_issued; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_issued = out_uop_iw_issued; // @[util.scala:104:23, :479:22]
reg out_uop_iw_issued_partial_agen; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_issued_partial_agen = out_uop_iw_issued_partial_agen; // @[util.scala:104:23, :479:22]
reg out_uop_iw_issued_partial_dgen; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_issued_partial_dgen = out_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p1_speculative_child; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p1_speculative_child = out_uop_iw_p1_speculative_child; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p2_speculative_child; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p2_speculative_child = out_uop_iw_p2_speculative_child; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p1_bypass_hint; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p1_bypass_hint = out_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p2_bypass_hint; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p2_bypass_hint = out_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p3_bypass_hint; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p3_bypass_hint = out_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22]
reg out_uop_dis_col_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :479:22]
wire out_uop_out_dis_col_sel = out_uop_dis_col_sel; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_br_mask; // @[util.scala:479:22]
assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :479:22]
wire [3:0] _out_uop_out_br_mask_T_1 = out_uop_br_mask; // @[util.scala:93:25, :479:22]
reg [1:0] out_uop_br_tag; // @[util.scala:479:22]
assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_br_tag = out_uop_br_tag; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_br_type; // @[util.scala:479:22]
assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_br_type = out_uop_br_type; // @[util.scala:104:23, :479:22]
reg out_uop_is_sfb; // @[util.scala:479:22]
assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_sfb = out_uop_is_sfb; // @[util.scala:104:23, :479:22]
reg out_uop_is_fence; // @[util.scala:479:22]
assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_fence = out_uop_is_fence; // @[util.scala:104:23, :479:22]
reg out_uop_is_fencei; // @[util.scala:479:22]
assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_fencei = out_uop_is_fencei; // @[util.scala:104:23, :479:22]
reg out_uop_is_sfence; // @[util.scala:479:22]
assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_sfence = out_uop_is_sfence; // @[util.scala:104:23, :479:22]
reg out_uop_is_amo; // @[util.scala:479:22]
assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_amo = out_uop_is_amo; // @[util.scala:104:23, :479:22]
reg out_uop_is_eret; // @[util.scala:479:22]
assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_eret = out_uop_is_eret; // @[util.scala:104:23, :479:22]
reg out_uop_is_sys_pc2epc; // @[util.scala:479:22]
assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_sys_pc2epc = out_uop_is_sys_pc2epc; // @[util.scala:104:23, :479:22]
reg out_uop_is_rocc; // @[util.scala:479:22]
assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_rocc = out_uop_is_rocc; // @[util.scala:104:23, :479:22]
reg out_uop_is_mov; // @[util.scala:479:22]
assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_mov = out_uop_is_mov; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_ftq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_ftq_idx = out_uop_ftq_idx; // @[util.scala:104:23, :479:22]
reg out_uop_edge_inst; // @[util.scala:479:22]
assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :479:22]
wire out_uop_out_edge_inst = out_uop_edge_inst; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_pc_lob; // @[util.scala:479:22]
assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_pc_lob = out_uop_pc_lob; // @[util.scala:104:23, :479:22]
reg out_uop_taken; // @[util.scala:479:22]
assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :479:22]
wire out_uop_out_taken = out_uop_taken; // @[util.scala:104:23, :479:22]
reg out_uop_imm_rename; // @[util.scala:479:22]
assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :479:22]
wire out_uop_out_imm_rename = out_uop_imm_rename; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_imm_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_imm_sel = out_uop_imm_sel; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_pimm; // @[util.scala:479:22]
assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_pimm = out_uop_pimm; // @[util.scala:104:23, :479:22]
reg [19:0] out_uop_imm_packed; // @[util.scala:479:22]
assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :479:22]
wire [19:0] out_uop_out_imm_packed = out_uop_imm_packed; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_op1_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_op1_sel = out_uop_op1_sel; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_op2_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_op2_sel = out_uop_op2_sel; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ldst; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ldst = out_uop_fp_ctrl_ldst; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_wen; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_wen = out_uop_fp_ctrl_wen; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ren1; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ren1 = out_uop_fp_ctrl_ren1; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ren2; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ren2 = out_uop_fp_ctrl_ren2; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ren3; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ren3 = out_uop_fp_ctrl_ren3; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_swap12; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_swap12 = out_uop_fp_ctrl_swap12; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_swap23; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_swap23 = out_uop_fp_ctrl_swap23; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_fp_ctrl_typeTagIn = out_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_fp_ctrl_typeTagOut = out_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_fromint; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_fromint = out_uop_fp_ctrl_fromint; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_toint; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_toint = out_uop_fp_ctrl_toint; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_fastpipe; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_fastpipe = out_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_fma; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_fma = out_uop_fp_ctrl_fma; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_div; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_div = out_uop_fp_ctrl_div; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_sqrt; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_sqrt = out_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_wflags; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_wflags = out_uop_fp_ctrl_wflags; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_vec; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_vec = out_uop_fp_ctrl_vec; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_rob_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_rob_idx = out_uop_rob_idx; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_ldq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_ldq_idx = out_uop_ldq_idx; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_stq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_stq_idx = out_uop_stq_idx; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_rxq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_rxq_idx = out_uop_rxq_idx; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_pdst; // @[util.scala:479:22]
assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_pdst = out_uop_pdst; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_prs1; // @[util.scala:479:22]
assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_prs1 = out_uop_prs1; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_prs2; // @[util.scala:479:22]
assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_prs2 = out_uop_prs2; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_prs3; // @[util.scala:479:22]
assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_prs3 = out_uop_prs3; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_ppred; // @[util.scala:479:22]
assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_ppred = out_uop_ppred; // @[util.scala:104:23, :479:22]
reg out_uop_prs1_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_prs1_busy = out_uop_prs1_busy; // @[util.scala:104:23, :479:22]
reg out_uop_prs2_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_prs2_busy = out_uop_prs2_busy; // @[util.scala:104:23, :479:22]
reg out_uop_prs3_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_prs3_busy = out_uop_prs3_busy; // @[util.scala:104:23, :479:22]
reg out_uop_ppred_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_ppred_busy = out_uop_ppred_busy; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_stale_pdst; // @[util.scala:479:22]
assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_stale_pdst = out_uop_stale_pdst; // @[util.scala:104:23, :479:22]
reg out_uop_exception; // @[util.scala:479:22]
assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :479:22]
wire out_uop_out_exception = out_uop_exception; // @[util.scala:104:23, :479:22]
reg [63:0] out_uop_exc_cause; // @[util.scala:479:22]
assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :479:22]
wire [63:0] out_uop_out_exc_cause = out_uop_exc_cause; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_mem_cmd; // @[util.scala:479:22]
assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_mem_cmd = out_uop_mem_cmd; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_mem_size; // @[util.scala:479:22]
assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_mem_size = out_uop_mem_size; // @[util.scala:104:23, :479:22]
reg out_uop_mem_signed; // @[util.scala:479:22]
assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :479:22]
wire out_uop_out_mem_signed = out_uop_mem_signed; // @[util.scala:104:23, :479:22]
reg out_uop_uses_ldq; // @[util.scala:479:22]
assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :479:22]
wire out_uop_out_uses_ldq = out_uop_uses_ldq; // @[util.scala:104:23, :479:22]
reg out_uop_uses_stq; // @[util.scala:479:22]
assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :479:22]
wire out_uop_out_uses_stq = out_uop_uses_stq; // @[util.scala:104:23, :479:22]
reg out_uop_is_unique; // @[util.scala:479:22]
assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_unique = out_uop_is_unique; // @[util.scala:104:23, :479:22]
reg out_uop_flush_on_commit; // @[util.scala:479:22]
assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :479:22]
wire out_uop_out_flush_on_commit = out_uop_flush_on_commit; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_csr_cmd; // @[util.scala:479:22]
assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_csr_cmd = out_uop_csr_cmd; // @[util.scala:104:23, :479:22]
reg out_uop_ldst_is_rs1; // @[util.scala:479:22]
assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :479:22]
wire out_uop_out_ldst_is_rs1 = out_uop_ldst_is_rs1; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_ldst; // @[util.scala:479:22]
assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_ldst = out_uop_ldst; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_lrs1; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_lrs1 = out_uop_lrs1; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_lrs2; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_lrs2 = out_uop_lrs2; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_lrs3; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_lrs3 = out_uop_lrs3; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_dst_rtype; // @[util.scala:479:22]
assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_dst_rtype = out_uop_dst_rtype; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_lrs1_rtype; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_lrs1_rtype = out_uop_lrs1_rtype; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_lrs2_rtype; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_lrs2_rtype = out_uop_lrs2_rtype; // @[util.scala:104:23, :479:22]
reg out_uop_frs3_en; // @[util.scala:479:22]
assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :479:22]
wire out_uop_out_frs3_en = out_uop_frs3_en; // @[util.scala:104:23, :479:22]
reg out_uop_fcn_dw; // @[util.scala:479:22]
assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :479:22]
wire out_uop_out_fcn_dw = out_uop_fcn_dw; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_fcn_op; // @[util.scala:479:22]
assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_fcn_op = out_uop_fcn_op; // @[util.scala:104:23, :479:22]
reg out_uop_fp_val; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_val = out_uop_fp_val; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_fp_rm; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_fp_rm = out_uop_fp_rm; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_fp_typ; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_fp_typ = out_uop_fp_typ; // @[util.scala:104:23, :479:22]
reg out_uop_xcpt_pf_if; // @[util.scala:479:22]
assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_xcpt_pf_if = out_uop_xcpt_pf_if; // @[util.scala:104:23, :479:22]
reg out_uop_xcpt_ae_if; // @[util.scala:479:22]
assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_xcpt_ae_if = out_uop_xcpt_ae_if; // @[util.scala:104:23, :479:22]
reg out_uop_xcpt_ma_if; // @[util.scala:479:22]
assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_xcpt_ma_if = out_uop_xcpt_ma_if; // @[util.scala:104:23, :479:22]
reg out_uop_bp_debug_if; // @[util.scala:479:22]
assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_bp_debug_if = out_uop_bp_debug_if; // @[util.scala:104:23, :479:22]
reg out_uop_bp_xcpt_if; // @[util.scala:479:22]
assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_bp_xcpt_if = out_uop_bp_xcpt_if; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_debug_fsrc; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_debug_fsrc = out_uop_debug_fsrc; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_debug_tsrc; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_debug_tsrc = out_uop_debug_tsrc; // @[util.scala:104:23, :479:22]
wire _io_empty_T = ~out_valid; // @[util.scala:478:28, :484:34]
assign _io_empty_T_1 = _main_io_empty & _io_empty_T; // @[util.scala:476:22, :484:{31,34}]
assign io_empty_0 = _io_empty_T_1; // @[util.scala:458:7, :484:31]
wire [4:0] _io_count_T = {1'h0, _main_io_count} + {4'h0, out_valid}; // @[util.scala:126:51, :458:7, :463:14, :476:22, :478:28, :485:31]
assign _io_count_T_1 = _io_count_T[3:0]; // @[util.scala:485:31]
assign io_count = _io_count_T_1; // @[util.scala:458:7, :485:31]
wire [3:0] out_uop_out_br_mask; // @[util.scala:104:23]
assign out_uop_out_br_mask = _out_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
wire _out_valid_T_7 = _out_valid_T_4; // @[util.scala:492:{28,80}]
wire main_io_deq_ready = io_deq_ready_0 & io_deq_valid_0 | ~out_valid; // @[Decoupled.scala:51:35]
wire _out_valid_T_15 = _out_valid_T_12; // @[util.scala:496:{38,103}]
wire [3:0] _out_uop_out_br_mask_T_3; // @[util.scala:93:25]
wire out_uop_out_1_iq_type_0; // @[util.scala:104:23]
wire out_uop_out_1_iq_type_1; // @[util.scala:104:23]
wire out_uop_out_1_iq_type_2; // @[util.scala:104:23]
wire out_uop_out_1_iq_type_3; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_0; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_1; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_2; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_3; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_4; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_5; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_6; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_7; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_8; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_9; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ldst; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_wen; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ren1; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ren2; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ren3; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_swap12; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_swap23; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_fp_ctrl_typeTagIn; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_fp_ctrl_typeTagOut; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_fromint; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_toint; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_fastpipe; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_fma; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_div; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_sqrt; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_wflags; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_vec; // @[util.scala:104:23]
wire [31:0] out_uop_out_1_inst; // @[util.scala:104:23]
wire [31:0] out_uop_out_1_debug_inst; // @[util.scala:104:23]
wire out_uop_out_1_is_rvc; // @[util.scala:104:23]
wire [33:0] out_uop_out_1_debug_pc; // @[util.scala:104:23]
wire out_uop_out_1_iw_issued; // @[util.scala:104:23]
wire out_uop_out_1_iw_issued_partial_agen; // @[util.scala:104:23]
wire out_uop_out_1_iw_issued_partial_dgen; // @[util.scala:104:23]
wire out_uop_out_1_iw_p1_speculative_child; // @[util.scala:104:23]
wire out_uop_out_1_iw_p2_speculative_child; // @[util.scala:104:23]
wire out_uop_out_1_iw_p1_bypass_hint; // @[util.scala:104:23]
wire out_uop_out_1_iw_p2_bypass_hint; // @[util.scala:104:23]
wire out_uop_out_1_iw_p3_bypass_hint; // @[util.scala:104:23]
wire out_uop_out_1_dis_col_sel; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_br_mask; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_br_tag; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_br_type; // @[util.scala:104:23]
wire out_uop_out_1_is_sfb; // @[util.scala:104:23]
wire out_uop_out_1_is_fence; // @[util.scala:104:23]
wire out_uop_out_1_is_fencei; // @[util.scala:104:23]
wire out_uop_out_1_is_sfence; // @[util.scala:104:23]
wire out_uop_out_1_is_amo; // @[util.scala:104:23]
wire out_uop_out_1_is_eret; // @[util.scala:104:23]
wire out_uop_out_1_is_sys_pc2epc; // @[util.scala:104:23]
wire out_uop_out_1_is_rocc; // @[util.scala:104:23]
wire out_uop_out_1_is_mov; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_ftq_idx; // @[util.scala:104:23]
wire out_uop_out_1_edge_inst; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_pc_lob; // @[util.scala:104:23]
wire out_uop_out_1_taken; // @[util.scala:104:23]
wire out_uop_out_1_imm_rename; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_imm_sel; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_pimm; // @[util.scala:104:23]
wire [19:0] out_uop_out_1_imm_packed; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_op1_sel; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_op2_sel; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_rob_idx; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_ldq_idx; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_stq_idx; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_rxq_idx; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_pdst; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_prs1; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_prs2; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_prs3; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_ppred; // @[util.scala:104:23]
wire out_uop_out_1_prs1_busy; // @[util.scala:104:23]
wire out_uop_out_1_prs2_busy; // @[util.scala:104:23]
wire out_uop_out_1_prs3_busy; // @[util.scala:104:23]
wire out_uop_out_1_ppred_busy; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_stale_pdst; // @[util.scala:104:23]
wire out_uop_out_1_exception; // @[util.scala:104:23]
wire [63:0] out_uop_out_1_exc_cause; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_mem_cmd; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_mem_size; // @[util.scala:104:23]
wire out_uop_out_1_mem_signed; // @[util.scala:104:23]
wire out_uop_out_1_uses_ldq; // @[util.scala:104:23]
wire out_uop_out_1_uses_stq; // @[util.scala:104:23]
wire out_uop_out_1_is_unique; // @[util.scala:104:23]
wire out_uop_out_1_flush_on_commit; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_csr_cmd; // @[util.scala:104:23]
wire out_uop_out_1_ldst_is_rs1; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_ldst; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_lrs1; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_lrs2; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_lrs3; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_dst_rtype; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_lrs1_rtype; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_lrs2_rtype; // @[util.scala:104:23]
wire out_uop_out_1_frs3_en; // @[util.scala:104:23]
wire out_uop_out_1_fcn_dw; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_fcn_op; // @[util.scala:104:23]
wire out_uop_out_1_fp_val; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_fp_rm; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_fp_typ; // @[util.scala:104:23]
wire out_uop_out_1_xcpt_pf_if; // @[util.scala:104:23]
wire out_uop_out_1_xcpt_ae_if; // @[util.scala:104:23]
wire out_uop_out_1_xcpt_ma_if; // @[util.scala:104:23]
wire out_uop_out_1_bp_debug_if; // @[util.scala:104:23]
wire out_uop_out_1_bp_xcpt_if; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_debug_fsrc; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_debug_tsrc; // @[util.scala:104:23]
assign out_uop_out_1_br_mask = _out_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23]
always @(posedge clock) begin // @[util.scala:458:7]
if (main_io_deq_ready) begin // @[util.scala:495:23]
out_reg_uop_inst <= _main_io_deq_bits_uop_inst; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_inst <= _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22, :477:22]
out_reg_uop_is_rvc <= _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_pc <= _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_0 <= _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_1 <= _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_2 <= _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_3 <= _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_0 <= _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_1 <= _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_2 <= _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_3 <= _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_4 <= _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_5 <= _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_6 <= _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_7 <= _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_8 <= _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_9 <= _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_issued <= _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_issued_partial_agen <= _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_issued_partial_dgen <= _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p1_speculative_child <= _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p2_speculative_child <= _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p1_bypass_hint <= _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p2_bypass_hint <= _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p3_bypass_hint <= _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22, :477:22]
out_reg_uop_dis_col_sel <= _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_br_mask <= _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22, :477:22]
out_reg_uop_br_tag <= _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22, :477:22]
out_reg_uop_br_type <= _main_io_deq_bits_uop_br_type; // @[util.scala:476:22, :477:22]
out_reg_uop_is_sfb <= _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22, :477:22]
out_reg_uop_is_fence <= _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22, :477:22]
out_reg_uop_is_fencei <= _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22, :477:22]
out_reg_uop_is_sfence <= _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22, :477:22]
out_reg_uop_is_amo <= _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22, :477:22]
out_reg_uop_is_eret <= _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22, :477:22]
out_reg_uop_is_sys_pc2epc <= _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22, :477:22]
out_reg_uop_is_rocc <= _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22, :477:22]
out_reg_uop_is_mov <= _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22, :477:22]
out_reg_uop_ftq_idx <= _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_edge_inst <= _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22, :477:22]
out_reg_uop_pc_lob <= _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22, :477:22]
out_reg_uop_taken <= _main_io_deq_bits_uop_taken; // @[util.scala:476:22, :477:22]
out_reg_uop_imm_rename <= _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22, :477:22]
out_reg_uop_imm_sel <= _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_pimm <= _main_io_deq_bits_uop_pimm; // @[util.scala:476:22, :477:22]
out_reg_uop_imm_packed <= _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22, :477:22]
out_reg_uop_op1_sel <= _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_op2_sel <= _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ldst <= _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_wen <= _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ren1 <= _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ren2 <= _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ren3 <= _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_swap12 <= _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_swap23 <= _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_typeTagIn <= _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_typeTagOut <= _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_fromint <= _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_toint <= _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_fastpipe <= _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_fma <= _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_div <= _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_sqrt <= _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_wflags <= _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_vec <= _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22, :477:22]
out_reg_uop_rob_idx <= _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_ldq_idx <= _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_stq_idx <= _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_rxq_idx <= _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_pdst <= _main_io_deq_bits_uop_pdst; // @[util.scala:476:22, :477:22]
out_reg_uop_prs1 <= _main_io_deq_bits_uop_prs1; // @[util.scala:476:22, :477:22]
out_reg_uop_prs2 <= _main_io_deq_bits_uop_prs2; // @[util.scala:476:22, :477:22]
out_reg_uop_prs3 <= _main_io_deq_bits_uop_prs3; // @[util.scala:476:22, :477:22]
out_reg_uop_ppred <= _main_io_deq_bits_uop_ppred; // @[util.scala:476:22, :477:22]
out_reg_uop_prs1_busy <= _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_prs2_busy <= _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_prs3_busy <= _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_ppred_busy <= _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_stale_pdst <= _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22, :477:22]
out_reg_uop_exception <= _main_io_deq_bits_uop_exception; // @[util.scala:476:22, :477:22]
out_reg_uop_exc_cause <= _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22, :477:22]
out_reg_uop_mem_cmd <= _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22, :477:22]
out_reg_uop_mem_size <= _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22, :477:22]
out_reg_uop_mem_signed <= _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22, :477:22]
out_reg_uop_uses_ldq <= _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22, :477:22]
out_reg_uop_uses_stq <= _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22, :477:22]
out_reg_uop_is_unique <= _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22, :477:22]
out_reg_uop_flush_on_commit <= _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22, :477:22]
out_reg_uop_csr_cmd <= _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22, :477:22]
out_reg_uop_ldst_is_rs1 <= _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22, :477:22]
out_reg_uop_ldst <= _main_io_deq_bits_uop_ldst; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs1 <= _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs2 <= _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs3 <= _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22, :477:22]
out_reg_uop_dst_rtype <= _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs1_rtype <= _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs2_rtype <= _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22, :477:22]
out_reg_uop_frs3_en <= _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22, :477:22]
out_reg_uop_fcn_dw <= _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22, :477:22]
out_reg_uop_fcn_op <= _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_val <= _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_rm <= _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_typ <= _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22, :477:22]
out_reg_uop_xcpt_pf_if <= _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22, :477:22]
out_reg_uop_xcpt_ae_if <= _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22, :477:22]
out_reg_uop_xcpt_ma_if <= _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22, :477:22]
out_reg_uop_bp_debug_if <= _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22, :477:22]
out_reg_uop_bp_xcpt_if <= _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_fsrc <= _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_tsrc <= _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22, :477:22]
out_reg_addr <= _main_io_deq_bits_addr; // @[util.scala:476:22, :477:22]
out_reg_data <= _main_io_deq_bits_data; // @[util.scala:476:22, :477:22]
out_reg_is_hella <= _main_io_deq_bits_is_hella; // @[util.scala:476:22, :477:22]
out_reg_tag_match <= _main_io_deq_bits_tag_match; // @[util.scala:476:22, :477:22]
out_reg_old_meta_coh_state <= _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22, :477:22]
out_reg_old_meta_tag <= _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22, :477:22]
out_reg_way_en <= _main_io_deq_bits_way_en; // @[util.scala:476:22, :477:22]
out_reg_sdq_id <= _main_io_deq_bits_sdq_id; // @[util.scala:476:22, :477:22]
end
out_uop_inst <= main_io_deq_ready ? out_uop_out_1_inst : out_uop_out_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_inst <= main_io_deq_ready ? out_uop_out_1_debug_inst : out_uop_out_debug_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_rvc <= main_io_deq_ready ? out_uop_out_1_is_rvc : out_uop_out_is_rvc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_pc <= main_io_deq_ready ? out_uop_out_1_debug_pc : out_uop_out_debug_pc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_0 <= main_io_deq_ready ? out_uop_out_1_iq_type_0 : out_uop_out_iq_type_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_1 <= main_io_deq_ready ? out_uop_out_1_iq_type_1 : out_uop_out_iq_type_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_2 <= main_io_deq_ready ? out_uop_out_1_iq_type_2 : out_uop_out_iq_type_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_3 <= main_io_deq_ready ? out_uop_out_1_iq_type_3 : out_uop_out_iq_type_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_0 <= main_io_deq_ready ? out_uop_out_1_fu_code_0 : out_uop_out_fu_code_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_1 <= main_io_deq_ready ? out_uop_out_1_fu_code_1 : out_uop_out_fu_code_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_2 <= main_io_deq_ready ? out_uop_out_1_fu_code_2 : out_uop_out_fu_code_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_3 <= main_io_deq_ready ? out_uop_out_1_fu_code_3 : out_uop_out_fu_code_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_4 <= main_io_deq_ready ? out_uop_out_1_fu_code_4 : out_uop_out_fu_code_4; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_5 <= main_io_deq_ready ? out_uop_out_1_fu_code_5 : out_uop_out_fu_code_5; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_6 <= main_io_deq_ready ? out_uop_out_1_fu_code_6 : out_uop_out_fu_code_6; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_7 <= main_io_deq_ready ? out_uop_out_1_fu_code_7 : out_uop_out_fu_code_7; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_8 <= main_io_deq_ready ? out_uop_out_1_fu_code_8 : out_uop_out_fu_code_8; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_9 <= main_io_deq_ready ? out_uop_out_1_fu_code_9 : out_uop_out_fu_code_9; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_issued <= main_io_deq_ready ? out_uop_out_1_iw_issued : out_uop_out_iw_issued; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_issued_partial_agen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_agen : out_uop_out_iw_issued_partial_agen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_issued_partial_dgen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_dgen : out_uop_out_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p1_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p1_speculative_child : out_uop_out_iw_p1_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p2_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p2_speculative_child : out_uop_out_iw_p2_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p1_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p1_bypass_hint : out_uop_out_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p2_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p2_bypass_hint : out_uop_out_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p3_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p3_bypass_hint : out_uop_out_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_dis_col_sel <= main_io_deq_ready ? out_uop_out_1_dis_col_sel : out_uop_out_dis_col_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_br_mask <= main_io_deq_ready ? out_uop_out_1_br_mask : out_uop_out_br_mask; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_br_tag <= main_io_deq_ready ? out_uop_out_1_br_tag : out_uop_out_br_tag; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_br_type <= main_io_deq_ready ? out_uop_out_1_br_type : out_uop_out_br_type; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_sfb <= main_io_deq_ready ? out_uop_out_1_is_sfb : out_uop_out_is_sfb; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_fence <= main_io_deq_ready ? out_uop_out_1_is_fence : out_uop_out_is_fence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_fencei <= main_io_deq_ready ? out_uop_out_1_is_fencei : out_uop_out_is_fencei; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_sfence <= main_io_deq_ready ? out_uop_out_1_is_sfence : out_uop_out_is_sfence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_amo <= main_io_deq_ready ? out_uop_out_1_is_amo : out_uop_out_is_amo; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_eret <= main_io_deq_ready ? out_uop_out_1_is_eret : out_uop_out_is_eret; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_sys_pc2epc <= main_io_deq_ready ? out_uop_out_1_is_sys_pc2epc : out_uop_out_is_sys_pc2epc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_rocc <= main_io_deq_ready ? out_uop_out_1_is_rocc : out_uop_out_is_rocc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_mov <= main_io_deq_ready ? out_uop_out_1_is_mov : out_uop_out_is_mov; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ftq_idx <= main_io_deq_ready ? out_uop_out_1_ftq_idx : out_uop_out_ftq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_edge_inst <= main_io_deq_ready ? out_uop_out_1_edge_inst : out_uop_out_edge_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_pc_lob <= main_io_deq_ready ? out_uop_out_1_pc_lob : out_uop_out_pc_lob; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_taken <= main_io_deq_ready ? out_uop_out_1_taken : out_uop_out_taken; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_imm_rename <= main_io_deq_ready ? out_uop_out_1_imm_rename : out_uop_out_imm_rename; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_imm_sel <= main_io_deq_ready ? out_uop_out_1_imm_sel : out_uop_out_imm_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_pimm <= main_io_deq_ready ? out_uop_out_1_pimm : out_uop_out_pimm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_imm_packed <= main_io_deq_ready ? out_uop_out_1_imm_packed : out_uop_out_imm_packed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_op1_sel <= main_io_deq_ready ? out_uop_out_1_op1_sel : out_uop_out_op1_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_op2_sel <= main_io_deq_ready ? out_uop_out_1_op2_sel : out_uop_out_op2_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ldst <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ldst : out_uop_out_fp_ctrl_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_wen <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wen : out_uop_out_fp_ctrl_wen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ren1 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren1 : out_uop_out_fp_ctrl_ren1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ren2 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren2 : out_uop_out_fp_ctrl_ren2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ren3 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren3 : out_uop_out_fp_ctrl_ren3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_swap12 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap12 : out_uop_out_fp_ctrl_swap12; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_swap23 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap23 : out_uop_out_fp_ctrl_swap23; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_typeTagIn <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagIn : out_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_typeTagOut <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagOut : out_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_fromint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fromint : out_uop_out_fp_ctrl_fromint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_toint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_toint : out_uop_out_fp_ctrl_toint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_fastpipe <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fastpipe : out_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_fma <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fma : out_uop_out_fp_ctrl_fma; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_div <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_div : out_uop_out_fp_ctrl_div; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_sqrt <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_sqrt : out_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_wflags <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wflags : out_uop_out_fp_ctrl_wflags; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_vec <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_vec : out_uop_out_fp_ctrl_vec; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_rob_idx <= main_io_deq_ready ? out_uop_out_1_rob_idx : out_uop_out_rob_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ldq_idx <= main_io_deq_ready ? out_uop_out_1_ldq_idx : out_uop_out_ldq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_stq_idx <= main_io_deq_ready ? out_uop_out_1_stq_idx : out_uop_out_stq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_rxq_idx <= main_io_deq_ready ? out_uop_out_1_rxq_idx : out_uop_out_rxq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_pdst <= main_io_deq_ready ? out_uop_out_1_pdst : out_uop_out_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs1 <= main_io_deq_ready ? out_uop_out_1_prs1 : out_uop_out_prs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs2 <= main_io_deq_ready ? out_uop_out_1_prs2 : out_uop_out_prs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs3 <= main_io_deq_ready ? out_uop_out_1_prs3 : out_uop_out_prs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ppred <= main_io_deq_ready ? out_uop_out_1_ppred : out_uop_out_ppred; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs1_busy <= main_io_deq_ready ? out_uop_out_1_prs1_busy : out_uop_out_prs1_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs2_busy <= main_io_deq_ready ? out_uop_out_1_prs2_busy : out_uop_out_prs2_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs3_busy <= main_io_deq_ready ? out_uop_out_1_prs3_busy : out_uop_out_prs3_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ppred_busy <= main_io_deq_ready ? out_uop_out_1_ppred_busy : out_uop_out_ppred_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_stale_pdst <= main_io_deq_ready ? out_uop_out_1_stale_pdst : out_uop_out_stale_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_exception <= main_io_deq_ready ? out_uop_out_1_exception : out_uop_out_exception; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_exc_cause <= main_io_deq_ready ? out_uop_out_1_exc_cause : out_uop_out_exc_cause; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_mem_cmd <= main_io_deq_ready ? out_uop_out_1_mem_cmd : out_uop_out_mem_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_mem_size <= main_io_deq_ready ? out_uop_out_1_mem_size : out_uop_out_mem_size; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_mem_signed <= main_io_deq_ready ? out_uop_out_1_mem_signed : out_uop_out_mem_signed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_uses_ldq <= main_io_deq_ready ? out_uop_out_1_uses_ldq : out_uop_out_uses_ldq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_uses_stq <= main_io_deq_ready ? out_uop_out_1_uses_stq : out_uop_out_uses_stq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_unique <= main_io_deq_ready ? out_uop_out_1_is_unique : out_uop_out_is_unique; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_flush_on_commit <= main_io_deq_ready ? out_uop_out_1_flush_on_commit : out_uop_out_flush_on_commit; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_csr_cmd <= main_io_deq_ready ? out_uop_out_1_csr_cmd : out_uop_out_csr_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ldst_is_rs1 <= main_io_deq_ready ? out_uop_out_1_ldst_is_rs1 : out_uop_out_ldst_is_rs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ldst <= main_io_deq_ready ? out_uop_out_1_ldst : out_uop_out_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs1 <= main_io_deq_ready ? out_uop_out_1_lrs1 : out_uop_out_lrs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs2 <= main_io_deq_ready ? out_uop_out_1_lrs2 : out_uop_out_lrs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs3 <= main_io_deq_ready ? out_uop_out_1_lrs3 : out_uop_out_lrs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_dst_rtype <= main_io_deq_ready ? out_uop_out_1_dst_rtype : out_uop_out_dst_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs1_rtype <= main_io_deq_ready ? out_uop_out_1_lrs1_rtype : out_uop_out_lrs1_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs2_rtype <= main_io_deq_ready ? out_uop_out_1_lrs2_rtype : out_uop_out_lrs2_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_frs3_en <= main_io_deq_ready ? out_uop_out_1_frs3_en : out_uop_out_frs3_en; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fcn_dw <= main_io_deq_ready ? out_uop_out_1_fcn_dw : out_uop_out_fcn_dw; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fcn_op <= main_io_deq_ready ? out_uop_out_1_fcn_op : out_uop_out_fcn_op; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_val <= main_io_deq_ready ? out_uop_out_1_fp_val : out_uop_out_fp_val; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_rm <= main_io_deq_ready ? out_uop_out_1_fp_rm : out_uop_out_fp_rm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_typ <= main_io_deq_ready ? out_uop_out_1_fp_typ : out_uop_out_fp_typ; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_xcpt_pf_if <= main_io_deq_ready ? out_uop_out_1_xcpt_pf_if : out_uop_out_xcpt_pf_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_xcpt_ae_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ae_if : out_uop_out_xcpt_ae_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_xcpt_ma_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ma_if : out_uop_out_xcpt_ma_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_bp_debug_if <= main_io_deq_ready ? out_uop_out_1_bp_debug_if : out_uop_out_bp_debug_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_bp_xcpt_if <= main_io_deq_ready ? out_uop_out_1_bp_xcpt_if : out_uop_out_bp_xcpt_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_fsrc <= main_io_deq_ready ? out_uop_out_1_debug_fsrc : out_uop_out_debug_fsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_tsrc <= main_io_deq_ready ? out_uop_out_1_debug_tsrc : out_uop_out_debug_tsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
if (reset) // @[util.scala:458:7]
out_valid <= 1'h0; // @[util.scala:478:28]
else // @[util.scala:458:7]
out_valid <= main_io_deq_ready ? _out_valid_T_15 : _out_valid_T_7; // @[util.scala:478:28, :492:{15,80}, :495:{23,38}, :496:{17,103}]
always @(posedge)
BranchKillableQueue_8 main ( // @[util.scala:476:22]
.clock (clock),
.reset (reset),
.io_enq_ready (io_enq_ready_0),
.io_enq_valid (io_enq_valid_0), // @[util.scala:458:7]
.io_enq_bits_uop_inst (io_enq_bits_uop_inst_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_inst (io_enq_bits_uop_debug_inst_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_rvc (io_enq_bits_uop_is_rvc_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_pc (io_enq_bits_uop_debug_pc_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_0 (io_enq_bits_uop_iq_type_0_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_1 (io_enq_bits_uop_iq_type_1_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_2 (io_enq_bits_uop_iq_type_2_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_3 (io_enq_bits_uop_iq_type_3_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_0 (io_enq_bits_uop_fu_code_0_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_1 (io_enq_bits_uop_fu_code_1_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_2 (io_enq_bits_uop_fu_code_2_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_3 (io_enq_bits_uop_fu_code_3_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_4 (io_enq_bits_uop_fu_code_4_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_5 (io_enq_bits_uop_fu_code_5_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_6 (io_enq_bits_uop_fu_code_6_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_7 (io_enq_bits_uop_fu_code_7_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_8 (io_enq_bits_uop_fu_code_8_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_9 (io_enq_bits_uop_fu_code_9_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_issued (io_enq_bits_uop_iw_issued_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_issued_partial_agen (io_enq_bits_uop_iw_issued_partial_agen_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_issued_partial_dgen (io_enq_bits_uop_iw_issued_partial_dgen_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p1_speculative_child (io_enq_bits_uop_iw_p1_speculative_child_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p2_speculative_child (io_enq_bits_uop_iw_p2_speculative_child_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p1_bypass_hint (io_enq_bits_uop_iw_p1_bypass_hint_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p2_bypass_hint (io_enq_bits_uop_iw_p2_bypass_hint_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p3_bypass_hint (io_enq_bits_uop_iw_p3_bypass_hint_0), // @[util.scala:458:7]
.io_enq_bits_uop_dis_col_sel (io_enq_bits_uop_dis_col_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_br_mask (io_enq_bits_uop_br_mask_0), // @[util.scala:458:7]
.io_enq_bits_uop_br_tag (io_enq_bits_uop_br_tag_0), // @[util.scala:458:7]
.io_enq_bits_uop_br_type (io_enq_bits_uop_br_type_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_sfb (io_enq_bits_uop_is_sfb_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_fence (io_enq_bits_uop_is_fence_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_fencei (io_enq_bits_uop_is_fencei_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_sfence (io_enq_bits_uop_is_sfence_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_amo (io_enq_bits_uop_is_amo_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_eret (io_enq_bits_uop_is_eret_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_sys_pc2epc (io_enq_bits_uop_is_sys_pc2epc_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_rocc (io_enq_bits_uop_is_rocc_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_mov (io_enq_bits_uop_is_mov_0), // @[util.scala:458:7]
.io_enq_bits_uop_ftq_idx (io_enq_bits_uop_ftq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_edge_inst (io_enq_bits_uop_edge_inst_0), // @[util.scala:458:7]
.io_enq_bits_uop_pc_lob (io_enq_bits_uop_pc_lob_0), // @[util.scala:458:7]
.io_enq_bits_uop_taken (io_enq_bits_uop_taken_0), // @[util.scala:458:7]
.io_enq_bits_uop_imm_rename (io_enq_bits_uop_imm_rename_0), // @[util.scala:458:7]
.io_enq_bits_uop_imm_sel (io_enq_bits_uop_imm_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_pimm (io_enq_bits_uop_pimm_0), // @[util.scala:458:7]
.io_enq_bits_uop_imm_packed (io_enq_bits_uop_imm_packed_0), // @[util.scala:458:7]
.io_enq_bits_uop_op1_sel (io_enq_bits_uop_op1_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_op2_sel (io_enq_bits_uop_op2_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ldst (io_enq_bits_uop_fp_ctrl_ldst_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_wen (io_enq_bits_uop_fp_ctrl_wen_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ren1 (io_enq_bits_uop_fp_ctrl_ren1_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ren2 (io_enq_bits_uop_fp_ctrl_ren2_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ren3 (io_enq_bits_uop_fp_ctrl_ren3_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_swap12 (io_enq_bits_uop_fp_ctrl_swap12_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_swap23 (io_enq_bits_uop_fp_ctrl_swap23_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_typeTagIn (io_enq_bits_uop_fp_ctrl_typeTagIn_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_typeTagOut (io_enq_bits_uop_fp_ctrl_typeTagOut_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_fromint (io_enq_bits_uop_fp_ctrl_fromint_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_toint (io_enq_bits_uop_fp_ctrl_toint_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_fastpipe (io_enq_bits_uop_fp_ctrl_fastpipe_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_fma (io_enq_bits_uop_fp_ctrl_fma_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_div (io_enq_bits_uop_fp_ctrl_div_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_sqrt (io_enq_bits_uop_fp_ctrl_sqrt_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_wflags (io_enq_bits_uop_fp_ctrl_wflags_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_vec (io_enq_bits_uop_fp_ctrl_vec_0), // @[util.scala:458:7]
.io_enq_bits_uop_rob_idx (io_enq_bits_uop_rob_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_ldq_idx (io_enq_bits_uop_ldq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_stq_idx (io_enq_bits_uop_stq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_rxq_idx (io_enq_bits_uop_rxq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_pdst (io_enq_bits_uop_pdst_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs1 (io_enq_bits_uop_prs1_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs2 (io_enq_bits_uop_prs2_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs3 (io_enq_bits_uop_prs3_0), // @[util.scala:458:7]
.io_enq_bits_uop_ppred (io_enq_bits_uop_ppred_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs1_busy (io_enq_bits_uop_prs1_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs2_busy (io_enq_bits_uop_prs2_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs3_busy (io_enq_bits_uop_prs3_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_ppred_busy (io_enq_bits_uop_ppred_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_stale_pdst (io_enq_bits_uop_stale_pdst_0), // @[util.scala:458:7]
.io_enq_bits_uop_exception (io_enq_bits_uop_exception_0), // @[util.scala:458:7]
.io_enq_bits_uop_exc_cause (io_enq_bits_uop_exc_cause_0), // @[util.scala:458:7]
.io_enq_bits_uop_mem_cmd (io_enq_bits_uop_mem_cmd_0), // @[util.scala:458:7]
.io_enq_bits_uop_mem_size (io_enq_bits_uop_mem_size_0), // @[util.scala:458:7]
.io_enq_bits_uop_mem_signed (io_enq_bits_uop_mem_signed_0), // @[util.scala:458:7]
.io_enq_bits_uop_uses_ldq (io_enq_bits_uop_uses_ldq_0), // @[util.scala:458:7]
.io_enq_bits_uop_uses_stq (io_enq_bits_uop_uses_stq_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_unique (io_enq_bits_uop_is_unique_0), // @[util.scala:458:7]
.io_enq_bits_uop_flush_on_commit (io_enq_bits_uop_flush_on_commit_0), // @[util.scala:458:7]
.io_enq_bits_uop_csr_cmd (io_enq_bits_uop_csr_cmd_0), // @[util.scala:458:7]
.io_enq_bits_uop_ldst_is_rs1 (io_enq_bits_uop_ldst_is_rs1_0), // @[util.scala:458:7]
.io_enq_bits_uop_ldst (io_enq_bits_uop_ldst_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs1 (io_enq_bits_uop_lrs1_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs2 (io_enq_bits_uop_lrs2_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs3 (io_enq_bits_uop_lrs3_0), // @[util.scala:458:7]
.io_enq_bits_uop_dst_rtype (io_enq_bits_uop_dst_rtype_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs1_rtype (io_enq_bits_uop_lrs1_rtype_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs2_rtype (io_enq_bits_uop_lrs2_rtype_0), // @[util.scala:458:7]
.io_enq_bits_uop_frs3_en (io_enq_bits_uop_frs3_en_0), // @[util.scala:458:7]
.io_enq_bits_uop_fcn_dw (io_enq_bits_uop_fcn_dw_0), // @[util.scala:458:7]
.io_enq_bits_uop_fcn_op (io_enq_bits_uop_fcn_op_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_val (io_enq_bits_uop_fp_val_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_rm (io_enq_bits_uop_fp_rm_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_typ (io_enq_bits_uop_fp_typ_0), // @[util.scala:458:7]
.io_enq_bits_uop_xcpt_pf_if (io_enq_bits_uop_xcpt_pf_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_xcpt_ae_if (io_enq_bits_uop_xcpt_ae_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_xcpt_ma_if (io_enq_bits_uop_xcpt_ma_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_bp_debug_if (io_enq_bits_uop_bp_debug_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_bp_xcpt_if (io_enq_bits_uop_bp_xcpt_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_fsrc (io_enq_bits_uop_debug_fsrc_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_tsrc (io_enq_bits_uop_debug_tsrc_0), // @[util.scala:458:7]
.io_enq_bits_addr (io_enq_bits_addr_0), // @[util.scala:458:7]
.io_enq_bits_data (io_enq_bits_data_0), // @[util.scala:458:7]
.io_enq_bits_is_hella (io_enq_bits_is_hella_0), // @[util.scala:458:7]
.io_enq_bits_tag_match (io_enq_bits_tag_match_0), // @[util.scala:458:7]
.io_enq_bits_old_meta_coh_state (io_enq_bits_old_meta_coh_state_0), // @[util.scala:458:7]
.io_enq_bits_old_meta_tag (io_enq_bits_old_meta_tag_0), // @[util.scala:458:7]
.io_enq_bits_way_en (io_enq_bits_way_en_0), // @[util.scala:458:7]
.io_enq_bits_sdq_id (io_enq_bits_sdq_id_0), // @[util.scala:458:7]
.io_deq_ready (main_io_deq_ready), // @[util.scala:495:23]
.io_deq_valid (_out_valid_T_12),
.io_deq_bits_uop_inst (_main_io_deq_bits_uop_inst),
.io_deq_bits_uop_debug_inst (_main_io_deq_bits_uop_debug_inst),
.io_deq_bits_uop_is_rvc (_main_io_deq_bits_uop_is_rvc),
.io_deq_bits_uop_debug_pc (_main_io_deq_bits_uop_debug_pc),
.io_deq_bits_uop_iq_type_0 (_main_io_deq_bits_uop_iq_type_0),
.io_deq_bits_uop_iq_type_1 (_main_io_deq_bits_uop_iq_type_1),
.io_deq_bits_uop_iq_type_2 (_main_io_deq_bits_uop_iq_type_2),
.io_deq_bits_uop_iq_type_3 (_main_io_deq_bits_uop_iq_type_3),
.io_deq_bits_uop_fu_code_0 (_main_io_deq_bits_uop_fu_code_0),
.io_deq_bits_uop_fu_code_1 (_main_io_deq_bits_uop_fu_code_1),
.io_deq_bits_uop_fu_code_2 (_main_io_deq_bits_uop_fu_code_2),
.io_deq_bits_uop_fu_code_3 (_main_io_deq_bits_uop_fu_code_3),
.io_deq_bits_uop_fu_code_4 (_main_io_deq_bits_uop_fu_code_4),
.io_deq_bits_uop_fu_code_5 (_main_io_deq_bits_uop_fu_code_5),
.io_deq_bits_uop_fu_code_6 (_main_io_deq_bits_uop_fu_code_6),
.io_deq_bits_uop_fu_code_7 (_main_io_deq_bits_uop_fu_code_7),
.io_deq_bits_uop_fu_code_8 (_main_io_deq_bits_uop_fu_code_8),
.io_deq_bits_uop_fu_code_9 (_main_io_deq_bits_uop_fu_code_9),
.io_deq_bits_uop_iw_issued (_main_io_deq_bits_uop_iw_issued),
.io_deq_bits_uop_iw_issued_partial_agen (_main_io_deq_bits_uop_iw_issued_partial_agen),
.io_deq_bits_uop_iw_issued_partial_dgen (_main_io_deq_bits_uop_iw_issued_partial_dgen),
.io_deq_bits_uop_iw_p1_speculative_child (_main_io_deq_bits_uop_iw_p1_speculative_child),
.io_deq_bits_uop_iw_p2_speculative_child (_main_io_deq_bits_uop_iw_p2_speculative_child),
.io_deq_bits_uop_iw_p1_bypass_hint (_main_io_deq_bits_uop_iw_p1_bypass_hint),
.io_deq_bits_uop_iw_p2_bypass_hint (_main_io_deq_bits_uop_iw_p2_bypass_hint),
.io_deq_bits_uop_iw_p3_bypass_hint (_main_io_deq_bits_uop_iw_p3_bypass_hint),
.io_deq_bits_uop_dis_col_sel (_main_io_deq_bits_uop_dis_col_sel),
.io_deq_bits_uop_br_mask (_main_io_deq_bits_uop_br_mask),
.io_deq_bits_uop_br_tag (_main_io_deq_bits_uop_br_tag),
.io_deq_bits_uop_br_type (_main_io_deq_bits_uop_br_type),
.io_deq_bits_uop_is_sfb (_main_io_deq_bits_uop_is_sfb),
.io_deq_bits_uop_is_fence (_main_io_deq_bits_uop_is_fence),
.io_deq_bits_uop_is_fencei (_main_io_deq_bits_uop_is_fencei),
.io_deq_bits_uop_is_sfence (_main_io_deq_bits_uop_is_sfence),
.io_deq_bits_uop_is_amo (_main_io_deq_bits_uop_is_amo),
.io_deq_bits_uop_is_eret (_main_io_deq_bits_uop_is_eret),
.io_deq_bits_uop_is_sys_pc2epc (_main_io_deq_bits_uop_is_sys_pc2epc),
.io_deq_bits_uop_is_rocc (_main_io_deq_bits_uop_is_rocc),
.io_deq_bits_uop_is_mov (_main_io_deq_bits_uop_is_mov),
.io_deq_bits_uop_ftq_idx (_main_io_deq_bits_uop_ftq_idx),
.io_deq_bits_uop_edge_inst (_main_io_deq_bits_uop_edge_inst),
.io_deq_bits_uop_pc_lob (_main_io_deq_bits_uop_pc_lob),
.io_deq_bits_uop_taken (_main_io_deq_bits_uop_taken),
.io_deq_bits_uop_imm_rename (_main_io_deq_bits_uop_imm_rename),
.io_deq_bits_uop_imm_sel (_main_io_deq_bits_uop_imm_sel),
.io_deq_bits_uop_pimm (_main_io_deq_bits_uop_pimm),
.io_deq_bits_uop_imm_packed (_main_io_deq_bits_uop_imm_packed),
.io_deq_bits_uop_op1_sel (_main_io_deq_bits_uop_op1_sel),
.io_deq_bits_uop_op2_sel (_main_io_deq_bits_uop_op2_sel),
.io_deq_bits_uop_fp_ctrl_ldst (_main_io_deq_bits_uop_fp_ctrl_ldst),
.io_deq_bits_uop_fp_ctrl_wen (_main_io_deq_bits_uop_fp_ctrl_wen),
.io_deq_bits_uop_fp_ctrl_ren1 (_main_io_deq_bits_uop_fp_ctrl_ren1),
.io_deq_bits_uop_fp_ctrl_ren2 (_main_io_deq_bits_uop_fp_ctrl_ren2),
.io_deq_bits_uop_fp_ctrl_ren3 (_main_io_deq_bits_uop_fp_ctrl_ren3),
.io_deq_bits_uop_fp_ctrl_swap12 (_main_io_deq_bits_uop_fp_ctrl_swap12),
.io_deq_bits_uop_fp_ctrl_swap23 (_main_io_deq_bits_uop_fp_ctrl_swap23),
.io_deq_bits_uop_fp_ctrl_typeTagIn (_main_io_deq_bits_uop_fp_ctrl_typeTagIn),
.io_deq_bits_uop_fp_ctrl_typeTagOut (_main_io_deq_bits_uop_fp_ctrl_typeTagOut),
.io_deq_bits_uop_fp_ctrl_fromint (_main_io_deq_bits_uop_fp_ctrl_fromint),
.io_deq_bits_uop_fp_ctrl_toint (_main_io_deq_bits_uop_fp_ctrl_toint),
.io_deq_bits_uop_fp_ctrl_fastpipe (_main_io_deq_bits_uop_fp_ctrl_fastpipe),
.io_deq_bits_uop_fp_ctrl_fma (_main_io_deq_bits_uop_fp_ctrl_fma),
.io_deq_bits_uop_fp_ctrl_div (_main_io_deq_bits_uop_fp_ctrl_div),
.io_deq_bits_uop_fp_ctrl_sqrt (_main_io_deq_bits_uop_fp_ctrl_sqrt),
.io_deq_bits_uop_fp_ctrl_wflags (_main_io_deq_bits_uop_fp_ctrl_wflags),
.io_deq_bits_uop_fp_ctrl_vec (_main_io_deq_bits_uop_fp_ctrl_vec),
.io_deq_bits_uop_rob_idx (_main_io_deq_bits_uop_rob_idx),
.io_deq_bits_uop_ldq_idx (_main_io_deq_bits_uop_ldq_idx),
.io_deq_bits_uop_stq_idx (_main_io_deq_bits_uop_stq_idx),
.io_deq_bits_uop_rxq_idx (_main_io_deq_bits_uop_rxq_idx),
.io_deq_bits_uop_pdst (_main_io_deq_bits_uop_pdst),
.io_deq_bits_uop_prs1 (_main_io_deq_bits_uop_prs1),
.io_deq_bits_uop_prs2 (_main_io_deq_bits_uop_prs2),
.io_deq_bits_uop_prs3 (_main_io_deq_bits_uop_prs3),
.io_deq_bits_uop_ppred (_main_io_deq_bits_uop_ppred),
.io_deq_bits_uop_prs1_busy (_main_io_deq_bits_uop_prs1_busy),
.io_deq_bits_uop_prs2_busy (_main_io_deq_bits_uop_prs2_busy),
.io_deq_bits_uop_prs3_busy (_main_io_deq_bits_uop_prs3_busy),
.io_deq_bits_uop_ppred_busy (_main_io_deq_bits_uop_ppred_busy),
.io_deq_bits_uop_stale_pdst (_main_io_deq_bits_uop_stale_pdst),
.io_deq_bits_uop_exception (_main_io_deq_bits_uop_exception),
.io_deq_bits_uop_exc_cause (_main_io_deq_bits_uop_exc_cause),
.io_deq_bits_uop_mem_cmd (_main_io_deq_bits_uop_mem_cmd),
.io_deq_bits_uop_mem_size (_main_io_deq_bits_uop_mem_size),
.io_deq_bits_uop_mem_signed (_main_io_deq_bits_uop_mem_signed),
.io_deq_bits_uop_uses_ldq (_main_io_deq_bits_uop_uses_ldq),
.io_deq_bits_uop_uses_stq (_main_io_deq_bits_uop_uses_stq),
.io_deq_bits_uop_is_unique (_main_io_deq_bits_uop_is_unique),
.io_deq_bits_uop_flush_on_commit (_main_io_deq_bits_uop_flush_on_commit),
.io_deq_bits_uop_csr_cmd (_main_io_deq_bits_uop_csr_cmd),
.io_deq_bits_uop_ldst_is_rs1 (_main_io_deq_bits_uop_ldst_is_rs1),
.io_deq_bits_uop_ldst (_main_io_deq_bits_uop_ldst),
.io_deq_bits_uop_lrs1 (_main_io_deq_bits_uop_lrs1),
.io_deq_bits_uop_lrs2 (_main_io_deq_bits_uop_lrs2),
.io_deq_bits_uop_lrs3 (_main_io_deq_bits_uop_lrs3),
.io_deq_bits_uop_dst_rtype (_main_io_deq_bits_uop_dst_rtype),
.io_deq_bits_uop_lrs1_rtype (_main_io_deq_bits_uop_lrs1_rtype),
.io_deq_bits_uop_lrs2_rtype (_main_io_deq_bits_uop_lrs2_rtype),
.io_deq_bits_uop_frs3_en (_main_io_deq_bits_uop_frs3_en),
.io_deq_bits_uop_fcn_dw (_main_io_deq_bits_uop_fcn_dw),
.io_deq_bits_uop_fcn_op (_main_io_deq_bits_uop_fcn_op),
.io_deq_bits_uop_fp_val (_main_io_deq_bits_uop_fp_val),
.io_deq_bits_uop_fp_rm (_main_io_deq_bits_uop_fp_rm),
.io_deq_bits_uop_fp_typ (_main_io_deq_bits_uop_fp_typ),
.io_deq_bits_uop_xcpt_pf_if (_main_io_deq_bits_uop_xcpt_pf_if),
.io_deq_bits_uop_xcpt_ae_if (_main_io_deq_bits_uop_xcpt_ae_if),
.io_deq_bits_uop_xcpt_ma_if (_main_io_deq_bits_uop_xcpt_ma_if),
.io_deq_bits_uop_bp_debug_if (_main_io_deq_bits_uop_bp_debug_if),
.io_deq_bits_uop_bp_xcpt_if (_main_io_deq_bits_uop_bp_xcpt_if),
.io_deq_bits_uop_debug_fsrc (_main_io_deq_bits_uop_debug_fsrc),
.io_deq_bits_uop_debug_tsrc (_main_io_deq_bits_uop_debug_tsrc),
.io_deq_bits_addr (_main_io_deq_bits_addr),
.io_deq_bits_data (_main_io_deq_bits_data),
.io_deq_bits_is_hella (_main_io_deq_bits_is_hella),
.io_deq_bits_tag_match (_main_io_deq_bits_tag_match),
.io_deq_bits_old_meta_coh_state (_main_io_deq_bits_old_meta_coh_state),
.io_deq_bits_old_meta_tag (_main_io_deq_bits_old_meta_tag),
.io_deq_bits_way_en (_main_io_deq_bits_way_en),
.io_deq_bits_sdq_id (_main_io_deq_bits_sdq_id),
.io_empty (_main_io_empty),
.io_count (_main_io_count)
); // @[util.scala:476:22]
assign out_uop_out_1_inst = _main_io_deq_bits_uop_inst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_inst = _main_io_deq_bits_uop_debug_inst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_rvc = _main_io_deq_bits_uop_is_rvc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_pc = _main_io_deq_bits_uop_debug_pc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_0 = _main_io_deq_bits_uop_iq_type_0; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_1 = _main_io_deq_bits_uop_iq_type_1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_2 = _main_io_deq_bits_uop_iq_type_2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_3 = _main_io_deq_bits_uop_iq_type_3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_0 = _main_io_deq_bits_uop_fu_code_0; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_1 = _main_io_deq_bits_uop_fu_code_1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_2 = _main_io_deq_bits_uop_fu_code_2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_3 = _main_io_deq_bits_uop_fu_code_3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_4 = _main_io_deq_bits_uop_fu_code_4; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_5 = _main_io_deq_bits_uop_fu_code_5; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_6 = _main_io_deq_bits_uop_fu_code_6; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_7 = _main_io_deq_bits_uop_fu_code_7; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_8 = _main_io_deq_bits_uop_fu_code_8; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_9 = _main_io_deq_bits_uop_fu_code_9; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_issued = _main_io_deq_bits_uop_iw_issued; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_issued_partial_agen = _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_issued_partial_dgen = _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p1_speculative_child = _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p2_speculative_child = _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p1_bypass_hint = _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p2_bypass_hint = _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p3_bypass_hint = _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_dis_col_sel = _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_br_tag = _main_io_deq_bits_uop_br_tag; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_br_type = _main_io_deq_bits_uop_br_type; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_sfb = _main_io_deq_bits_uop_is_sfb; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_fence = _main_io_deq_bits_uop_is_fence; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_fencei = _main_io_deq_bits_uop_is_fencei; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_sfence = _main_io_deq_bits_uop_is_sfence; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_amo = _main_io_deq_bits_uop_is_amo; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_eret = _main_io_deq_bits_uop_is_eret; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_sys_pc2epc = _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_rocc = _main_io_deq_bits_uop_is_rocc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_mov = _main_io_deq_bits_uop_is_mov; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ftq_idx = _main_io_deq_bits_uop_ftq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_edge_inst = _main_io_deq_bits_uop_edge_inst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_pc_lob = _main_io_deq_bits_uop_pc_lob; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_taken = _main_io_deq_bits_uop_taken; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_imm_rename = _main_io_deq_bits_uop_imm_rename; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_imm_sel = _main_io_deq_bits_uop_imm_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_pimm = _main_io_deq_bits_uop_pimm; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_imm_packed = _main_io_deq_bits_uop_imm_packed; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_op1_sel = _main_io_deq_bits_uop_op1_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_op2_sel = _main_io_deq_bits_uop_op2_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ldst = _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_wen = _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ren1 = _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ren2 = _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ren3 = _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_swap12 = _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_swap23 = _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_typeTagIn = _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_typeTagOut = _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_fromint = _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_toint = _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_fastpipe = _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_fma = _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_div = _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_sqrt = _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_wflags = _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_vec = _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_rob_idx = _main_io_deq_bits_uop_rob_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ldq_idx = _main_io_deq_bits_uop_ldq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_stq_idx = _main_io_deq_bits_uop_stq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_rxq_idx = _main_io_deq_bits_uop_rxq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_pdst = _main_io_deq_bits_uop_pdst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs1 = _main_io_deq_bits_uop_prs1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs2 = _main_io_deq_bits_uop_prs2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs3 = _main_io_deq_bits_uop_prs3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ppred = _main_io_deq_bits_uop_ppred; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs1_busy = _main_io_deq_bits_uop_prs1_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs2_busy = _main_io_deq_bits_uop_prs2_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs3_busy = _main_io_deq_bits_uop_prs3_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ppred_busy = _main_io_deq_bits_uop_ppred_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_stale_pdst = _main_io_deq_bits_uop_stale_pdst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_exception = _main_io_deq_bits_uop_exception; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_exc_cause = _main_io_deq_bits_uop_exc_cause; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_mem_cmd = _main_io_deq_bits_uop_mem_cmd; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_mem_size = _main_io_deq_bits_uop_mem_size; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_mem_signed = _main_io_deq_bits_uop_mem_signed; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_uses_ldq = _main_io_deq_bits_uop_uses_ldq; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_uses_stq = _main_io_deq_bits_uop_uses_stq; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_unique = _main_io_deq_bits_uop_is_unique; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_flush_on_commit = _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_csr_cmd = _main_io_deq_bits_uop_csr_cmd; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ldst_is_rs1 = _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ldst = _main_io_deq_bits_uop_ldst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs1 = _main_io_deq_bits_uop_lrs1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs2 = _main_io_deq_bits_uop_lrs2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs3 = _main_io_deq_bits_uop_lrs3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_dst_rtype = _main_io_deq_bits_uop_dst_rtype; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs1_rtype = _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs2_rtype = _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_frs3_en = _main_io_deq_bits_uop_frs3_en; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fcn_dw = _main_io_deq_bits_uop_fcn_dw; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fcn_op = _main_io_deq_bits_uop_fcn_op; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_val = _main_io_deq_bits_uop_fp_val; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_rm = _main_io_deq_bits_uop_fp_rm; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_typ = _main_io_deq_bits_uop_fp_typ; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_xcpt_pf_if = _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_xcpt_ae_if = _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_xcpt_ma_if = _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_bp_debug_if = _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_bp_xcpt_if = _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_fsrc = _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_tsrc = _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:104:23, :476:22]
assign _out_uop_out_br_mask_T_3 = _main_io_deq_bits_uop_br_mask; // @[util.scala:93:25, :476:22]
assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7]
assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7]
assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:458:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7]
assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:458:7]
assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:458:7]
assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7]
assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:458:7]
assign io_deq_bits_way_en = io_deq_bits_way_en_0; // @[util.scala:458:7]
assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:458:7]
assign io_empty = io_empty_0; // @[util.scala:458:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_53 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_64
connect io_out_sink_valid_1.clock, clock
connect io_out_sink_valid_1.reset, reset
connect io_out_sink_valid_1.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid_1.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_53( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_64 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_242 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_242( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s3k3z4c_1 :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeIn.e.bits.sink
invalidate nodeIn.e.valid
invalidate nodeIn.e.ready
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.c.bits.corrupt
invalidate nodeIn.c.bits.data
invalidate nodeIn.c.bits.address
invalidate nodeIn.c.bits.source
invalidate nodeIn.c.bits.size
invalidate nodeIn.c.bits.param
invalidate nodeIn.c.bits.opcode
invalidate nodeIn.c.valid
invalidate nodeIn.c.ready
invalidate nodeIn.b.bits.corrupt
invalidate nodeIn.b.bits.data
invalidate nodeIn.b.bits.mask
invalidate nodeIn.b.bits.address
invalidate nodeIn.b.bits.source
invalidate nodeIn.b.bits.size
invalidate nodeIn.b.bits.param
invalidate nodeIn.b.bits.opcode
invalidate nodeIn.b.valid
invalidate nodeIn.b.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_41
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink
connect monitor.io.in.e.valid, nodeIn.e.valid
connect monitor.io.in.e.ready, nodeIn.e.ready
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt
connect monitor.io.in.c.bits.data, nodeIn.c.bits.data
connect monitor.io.in.c.bits.address, nodeIn.c.bits.address
connect monitor.io.in.c.bits.source, nodeIn.c.bits.source
connect monitor.io.in.c.bits.size, nodeIn.c.bits.size
connect monitor.io.in.c.bits.param, nodeIn.c.bits.param
connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode
connect monitor.io.in.c.valid, nodeIn.c.valid
connect monitor.io.in.c.ready, nodeIn.c.ready
connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt
connect monitor.io.in.b.bits.data, nodeIn.b.bits.data
connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask
connect monitor.io.in.b.bits.address, nodeIn.b.bits.address
connect monitor.io.in.b.bits.source, nodeIn.b.bits.source
connect monitor.io.in.b.bits.size, nodeIn.b.bits.size
connect monitor.io.in.b.bits.param, nodeIn.b.bits.param
connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode
connect monitor.io.in.b.valid, nodeIn.b.valid
connect monitor.io.in.b.ready, nodeIn.b.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeOut.e.bits.sink
invalidate nodeOut.e.valid
invalidate nodeOut.e.ready
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.c.bits.corrupt
invalidate nodeOut.c.bits.data
invalidate nodeOut.c.bits.address
invalidate nodeOut.c.bits.source
invalidate nodeOut.c.bits.size
invalidate nodeOut.c.bits.param
invalidate nodeOut.c.bits.opcode
invalidate nodeOut.c.valid
invalidate nodeOut.c.ready
invalidate nodeOut.b.bits.corrupt
invalidate nodeOut.b.bits.data
invalidate nodeOut.b.bits.mask
invalidate nodeOut.b.bits.address
invalidate nodeOut.b.bits.source
invalidate nodeOut.b.bits.size
invalidate nodeOut.b.bits.param
invalidate nodeOut.b.bits.opcode
invalidate nodeOut.b.valid
invalidate nodeOut.b.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a32d64s3k3z4c
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a32d64s3k3z4c
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
inst nodeIn_b_q of Queue2_TLBundleB_a32d64s3k3z4c
connect nodeIn_b_q.clock, clock
connect nodeIn_b_q.reset, reset
connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid
connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt
connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data
connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask
connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address
connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source
connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size
connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param
connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode
connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready
connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits
connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid
connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready
inst nodeOut_c_q of Queue2_TLBundleC_a32d64s3k3z4c
connect nodeOut_c_q.clock, clock
connect nodeOut_c_q.reset, reset
connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid
connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt
connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data
connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address
connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source
connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size
connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param
connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode
connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready
connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits
connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid
connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready
inst nodeOut_e_q of Queue2_TLBundleE_a32d64s3k3z4c
connect nodeOut_e_q.clock, clock
connect nodeOut_e_q.reset, reset
connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid
connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink
connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready
connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits
connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid
connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready | module TLBuffer_a32d64s3k3z4c_1( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9]
wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9]
wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9]
wire [2:0] auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9]
wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_out_e_ready_0 = auto_out_e_ready; // @[Buffer.scala:40:9]
wire [63:0] auto_out_b_bits_data = 64'h0; // @[Decoupled.scala:362:21]
wire [63:0] nodeOut_b_bits_data = 64'h0; // @[Decoupled.scala:362:21]
wire [7:0] auto_out_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21]
wire [7:0] nodeOut_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21]
wire [3:0] auto_out_b_bits_size = 4'h6; // @[Decoupled.scala:362:21]
wire [3:0] nodeOut_b_bits_size = 4'h6; // @[Decoupled.scala:362:21]
wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21]
wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21]
wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire auto_in_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire auto_out_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_e_ready; // @[MixedNode.scala:551:17]
wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9]
wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeOut_e_ready = auto_out_e_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_b_valid_0; // @[Buffer.scala:40:9]
wire auto_in_c_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire auto_in_e_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_b_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_c_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9]
assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9]
TLMonitor_41 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17]
.io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17]
.io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17]
.io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17]
.io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17]
.io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17]
.io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17]
.io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17]
.io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d64s3k3z4c nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d64s3k3z4c nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleB_a32d64s3k3z4c nodeIn_b_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_b_ready),
.io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_b_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_b_valid),
.io_deq_bits_opcode (nodeIn_b_bits_opcode),
.io_deq_bits_param (nodeIn_b_bits_param),
.io_deq_bits_size (nodeIn_b_bits_size),
.io_deq_bits_source (nodeIn_b_bits_source),
.io_deq_bits_address (nodeIn_b_bits_address),
.io_deq_bits_mask (nodeIn_b_bits_mask),
.io_deq_bits_data (nodeIn_b_bits_data),
.io_deq_bits_corrupt (nodeIn_b_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleC_a32d64s3k3z4c nodeOut_c_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_c_ready),
.io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_c_valid),
.io_deq_bits_opcode (nodeOut_c_bits_opcode),
.io_deq_bits_param (nodeOut_c_bits_param),
.io_deq_bits_size (nodeOut_c_bits_size),
.io_deq_bits_source (nodeOut_c_bits_source),
.io_deq_bits_address (nodeOut_c_bits_address),
.io_deq_bits_data (nodeOut_c_bits_data),
.io_deq_bits_corrupt (nodeOut_c_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleE_a32d64s3k3z4c nodeOut_e_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_e_ready),
.io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_e_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_e_valid),
.io_deq_bits_sink (nodeOut_e_bits_sink)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9]
assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_202 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_202( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_11 :
input clock : Clock
input reset : Reset
output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}
regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1)
reg flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, clock
inst q of Queue2_EgressFlit_11
connect q.clock, clock
connect q.reset, reset
connect q.io.enq.valid, io.in[0].valid
connect q.io.enq.bits.head, io.in[0].bits.head
connect q.io.enq.bits.tail, io.in[0].bits.tail
node _q_io_enq_bits_ingress_id_T = eq(UInt<4>(0hd), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1)
node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4)
node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<2>(0h3), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7)
node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<2>(0h2), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10)
node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<4>(0hc), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13)
node _q_io_enq_bits_ingress_id_T_15 = eq(UInt<4>(0h8), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_16 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_17 = and(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16)
node _q_io_enq_bits_ingress_id_T_18 = eq(UInt<4>(0hf), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_19 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_20 = and(_q_io_enq_bits_ingress_id_T_18, _q_io_enq_bits_ingress_id_T_19)
node _q_io_enq_bits_ingress_id_T_21 = eq(UInt<3>(0h7), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_22 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_23 = and(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_22)
node _q_io_enq_bits_ingress_id_T_24 = eq(UInt<2>(0h3), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_25 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_26 = and(_q_io_enq_bits_ingress_id_T_24, _q_io_enq_bits_ingress_id_T_25)
node _q_io_enq_bits_ingress_id_T_27 = eq(UInt<4>(0he), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_28 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_29 = and(_q_io_enq_bits_ingress_id_T_27, _q_io_enq_bits_ingress_id_T_28)
node _q_io_enq_bits_ingress_id_T_30 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_31 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_32 = and(_q_io_enq_bits_ingress_id_T_30, _q_io_enq_bits_ingress_id_T_31)
node _q_io_enq_bits_ingress_id_T_33 = eq(UInt<4>(0hb), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_34 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_35 = and(_q_io_enq_bits_ingress_id_T_33, _q_io_enq_bits_ingress_id_T_34)
node _q_io_enq_bits_ingress_id_T_36 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<5>(0h15), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_37 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<5>(0hb), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_38 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<5>(0h3), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_39 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<5>(0h7), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_40 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<5>(0h13), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_41 = mux(_q_io_enq_bits_ingress_id_T_17, UInt<5>(0hf), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_42 = mux(_q_io_enq_bits_ingress_id_T_20, UInt<5>(0h19), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_43 = mux(_q_io_enq_bits_ingress_id_T_23, UInt<5>(0hd), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_44 = mux(_q_io_enq_bits_ingress_id_T_26, UInt<5>(0h9), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_45 = mux(_q_io_enq_bits_ingress_id_T_29, UInt<5>(0h17), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_46 = mux(_q_io_enq_bits_ingress_id_T_32, UInt<5>(0h5), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_47 = mux(_q_io_enq_bits_ingress_id_T_35, UInt<5>(0h11), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_48 = or(_q_io_enq_bits_ingress_id_T_36, _q_io_enq_bits_ingress_id_T_37)
node _q_io_enq_bits_ingress_id_T_49 = or(_q_io_enq_bits_ingress_id_T_48, _q_io_enq_bits_ingress_id_T_38)
node _q_io_enq_bits_ingress_id_T_50 = or(_q_io_enq_bits_ingress_id_T_49, _q_io_enq_bits_ingress_id_T_39)
node _q_io_enq_bits_ingress_id_T_51 = or(_q_io_enq_bits_ingress_id_T_50, _q_io_enq_bits_ingress_id_T_40)
node _q_io_enq_bits_ingress_id_T_52 = or(_q_io_enq_bits_ingress_id_T_51, _q_io_enq_bits_ingress_id_T_41)
node _q_io_enq_bits_ingress_id_T_53 = or(_q_io_enq_bits_ingress_id_T_52, _q_io_enq_bits_ingress_id_T_42)
node _q_io_enq_bits_ingress_id_T_54 = or(_q_io_enq_bits_ingress_id_T_53, _q_io_enq_bits_ingress_id_T_43)
node _q_io_enq_bits_ingress_id_T_55 = or(_q_io_enq_bits_ingress_id_T_54, _q_io_enq_bits_ingress_id_T_44)
node _q_io_enq_bits_ingress_id_T_56 = or(_q_io_enq_bits_ingress_id_T_55, _q_io_enq_bits_ingress_id_T_45)
node _q_io_enq_bits_ingress_id_T_57 = or(_q_io_enq_bits_ingress_id_T_56, _q_io_enq_bits_ingress_id_T_46)
node _q_io_enq_bits_ingress_id_T_58 = or(_q_io_enq_bits_ingress_id_T_57, _q_io_enq_bits_ingress_id_T_47)
wire _q_io_enq_bits_ingress_id_WIRE : UInt<5>
connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_58
connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE
connect q.io.enq.bits.payload, io.in[0].bits.payload
connect io.out.bits, q.io.deq.bits
connect io.out.valid, q.io.deq.valid
connect q.io.deq.ready, io.out.ready
node _T = eq(q.io.enq.ready, UInt<1>(0h0))
node _T_1 = and(q.io.enq.valid, _T)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0))
connect io.credit_available[0], _io_credit_available_0_T
node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0))
connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T
connect io.channel_status[0].flow, flow
node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail)
when _T_6 :
connect channel_empty, UInt<1>(0h1)
when io.allocs[0].alloc :
connect channel_empty, UInt<1>(0h0)
connect flow, io.allocs[0].flow | module EgressUnit_11( // @[EgressUnit.scala:12:7]
input clock, // @[EgressUnit.scala:12:7]
input reset, // @[EgressUnit.scala:12:7]
input io_in_0_valid, // @[EgressUnit.scala:18:14]
input io_in_0_bits_head, // @[EgressUnit.scala:18:14]
input io_in_0_bits_tail, // @[EgressUnit.scala:18:14]
input [144:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14]
input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14]
input [2:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14]
output io_credit_available_0, // @[EgressUnit.scala:18:14]
output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14]
input io_allocs_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14]
input io_out_ready, // @[EgressUnit.scala:18:14]
output io_out_valid, // @[EgressUnit.scala:18:14]
output io_out_bits_head, // @[EgressUnit.scala:18:14]
output io_out_bits_tail, // @[EgressUnit.scala:18:14]
output [144:0] io_out_bits_payload // @[EgressUnit.scala:18:14]
);
wire _q_io_enq_ready; // @[EgressUnit.scala:22:17]
wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17]
reg channel_empty; // @[EgressUnit.scala:20:30]
wire _q_io_enq_bits_ingress_id_T_34 = io_in_0_bits_flow_ingress_node_id == 3'h1; // @[EgressUnit.scala:32:27] |
Generate the Verilog code corresponding to this FIRRTL code module ComposedBranchPredictorBank_2 :
input clock : Clock
input reset : Reset
output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, flip f0_mask : UInt<4>, flip f1_ghist : UInt<64>, flip f1_lhist : UInt<1>, flip resp_in : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}[1], resp : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}, f3_meta : UInt<120>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}}
connect io.resp, io.resp_in[0]
connect io.f3_meta, UInt<1>(0h0)
node s0_idx = shr(io.f0_pc, 4)
reg s1_idx : UInt, clock
connect s1_idx, s0_idx
reg s2_idx : UInt, clock
connect s2_idx, s1_idx
reg s3_idx : UInt, clock
connect s3_idx, s2_idx
reg s1_valid : UInt<1>, clock
connect s1_valid, io.f0_valid
reg s2_valid : UInt<1>, clock
connect s2_valid, s1_valid
reg s3_valid : UInt<1>, clock
connect s3_valid, s2_valid
reg s1_mask : UInt, clock
connect s1_mask, io.f0_mask
reg s2_mask : UInt, clock
connect s2_mask, s1_mask
reg s3_mask : UInt, clock
connect s3_mask, s2_mask
reg s1_pc : UInt, clock
connect s1_pc, io.f0_pc
node s0_update_idx = shr(io.update.bits.pc, 4)
reg s1_update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}, clock
connect s1_update.bits.meta, io.update.bits.meta
connect s1_update.bits.target, io.update.bits.target
connect s1_update.bits.lhist, io.update.bits.lhist
connect s1_update.bits.ghist, io.update.bits.ghist
connect s1_update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect s1_update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect s1_update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect s1_update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect s1_update.bits.cfi_taken, io.update.bits.cfi_taken
connect s1_update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect s1_update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect s1_update.bits.br_mask, io.update.bits.br_mask
connect s1_update.bits.pc, io.update.bits.pc
connect s1_update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect s1_update.bits.is_repair_update, io.update.bits.is_repair_update
connect s1_update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect s1_update.valid, io.update.valid
reg s1_update_idx : UInt, clock
connect s1_update_idx, s0_update_idx
reg s1_update_valid : UInt<1>, clock
connect s1_update_valid, io.update.valid
inst loop of LoopBranchPredictorBank_2
connect loop.clock, clock
connect loop.reset, reset
inst tage of TageBranchPredictorBank_2
connect tage.clock, clock
connect tage.reset, reset
inst btb of BTBBranchPredictorBank_2
connect btb.clock, clock
connect btb.reset, reset
inst bim of BIMBranchPredictorBank_2
connect bim.clock, clock
connect bim.reset, reset
inst ubtb of FAMicroBTBBranchPredictorBank_2
connect ubtb.clock, clock
connect ubtb.reset, reset
invalidate loop.io.update.bits.meta
invalidate loop.io.update.bits.target
invalidate loop.io.update.bits.lhist
invalidate loop.io.update.bits.ghist
invalidate loop.io.update.bits.cfi_is_jalr
invalidate loop.io.update.bits.cfi_is_jal
invalidate loop.io.update.bits.cfi_is_br
invalidate loop.io.update.bits.cfi_mispredicted
invalidate loop.io.update.bits.cfi_taken
invalidate loop.io.update.bits.cfi_idx.bits
invalidate loop.io.update.bits.cfi_idx.valid
invalidate loop.io.update.bits.br_mask
invalidate loop.io.update.bits.pc
invalidate loop.io.update.bits.btb_mispredicts
invalidate loop.io.update.bits.is_repair_update
invalidate loop.io.update.bits.is_mispredict_update
invalidate loop.io.update.valid
invalidate loop.io.f3_fire
invalidate loop.io.f3_meta
invalidate loop.io.resp.f3[0].predicted_pc.bits
invalidate loop.io.resp.f3[0].predicted_pc.valid
invalidate loop.io.resp.f3[0].is_jal
invalidate loop.io.resp.f3[0].is_br
invalidate loop.io.resp.f3[0].taken
invalidate loop.io.resp.f3[1].predicted_pc.bits
invalidate loop.io.resp.f3[1].predicted_pc.valid
invalidate loop.io.resp.f3[1].is_jal
invalidate loop.io.resp.f3[1].is_br
invalidate loop.io.resp.f3[1].taken
invalidate loop.io.resp.f3[2].predicted_pc.bits
invalidate loop.io.resp.f3[2].predicted_pc.valid
invalidate loop.io.resp.f3[2].is_jal
invalidate loop.io.resp.f3[2].is_br
invalidate loop.io.resp.f3[2].taken
invalidate loop.io.resp.f3[3].predicted_pc.bits
invalidate loop.io.resp.f3[3].predicted_pc.valid
invalidate loop.io.resp.f3[3].is_jal
invalidate loop.io.resp.f3[3].is_br
invalidate loop.io.resp.f3[3].taken
invalidate loop.io.resp.f2[0].predicted_pc.bits
invalidate loop.io.resp.f2[0].predicted_pc.valid
invalidate loop.io.resp.f2[0].is_jal
invalidate loop.io.resp.f2[0].is_br
invalidate loop.io.resp.f2[0].taken
invalidate loop.io.resp.f2[1].predicted_pc.bits
invalidate loop.io.resp.f2[1].predicted_pc.valid
invalidate loop.io.resp.f2[1].is_jal
invalidate loop.io.resp.f2[1].is_br
invalidate loop.io.resp.f2[1].taken
invalidate loop.io.resp.f2[2].predicted_pc.bits
invalidate loop.io.resp.f2[2].predicted_pc.valid
invalidate loop.io.resp.f2[2].is_jal
invalidate loop.io.resp.f2[2].is_br
invalidate loop.io.resp.f2[2].taken
invalidate loop.io.resp.f2[3].predicted_pc.bits
invalidate loop.io.resp.f2[3].predicted_pc.valid
invalidate loop.io.resp.f2[3].is_jal
invalidate loop.io.resp.f2[3].is_br
invalidate loop.io.resp.f2[3].taken
invalidate loop.io.resp.f1[0].predicted_pc.bits
invalidate loop.io.resp.f1[0].predicted_pc.valid
invalidate loop.io.resp.f1[0].is_jal
invalidate loop.io.resp.f1[0].is_br
invalidate loop.io.resp.f1[0].taken
invalidate loop.io.resp.f1[1].predicted_pc.bits
invalidate loop.io.resp.f1[1].predicted_pc.valid
invalidate loop.io.resp.f1[1].is_jal
invalidate loop.io.resp.f1[1].is_br
invalidate loop.io.resp.f1[1].taken
invalidate loop.io.resp.f1[2].predicted_pc.bits
invalidate loop.io.resp.f1[2].predicted_pc.valid
invalidate loop.io.resp.f1[2].is_jal
invalidate loop.io.resp.f1[2].is_br
invalidate loop.io.resp.f1[2].taken
invalidate loop.io.resp.f1[3].predicted_pc.bits
invalidate loop.io.resp.f1[3].predicted_pc.valid
invalidate loop.io.resp.f1[3].is_jal
invalidate loop.io.resp.f1[3].is_br
invalidate loop.io.resp.f1[3].taken
invalidate loop.io.resp_in[0].f3[0].predicted_pc.bits
invalidate loop.io.resp_in[0].f3[0].predicted_pc.valid
invalidate loop.io.resp_in[0].f3[0].is_jal
invalidate loop.io.resp_in[0].f3[0].is_br
invalidate loop.io.resp_in[0].f3[0].taken
invalidate loop.io.resp_in[0].f3[1].predicted_pc.bits
invalidate loop.io.resp_in[0].f3[1].predicted_pc.valid
invalidate loop.io.resp_in[0].f3[1].is_jal
invalidate loop.io.resp_in[0].f3[1].is_br
invalidate loop.io.resp_in[0].f3[1].taken
invalidate loop.io.resp_in[0].f3[2].predicted_pc.bits
invalidate loop.io.resp_in[0].f3[2].predicted_pc.valid
invalidate loop.io.resp_in[0].f3[2].is_jal
invalidate loop.io.resp_in[0].f3[2].is_br
invalidate loop.io.resp_in[0].f3[2].taken
invalidate loop.io.resp_in[0].f3[3].predicted_pc.bits
invalidate loop.io.resp_in[0].f3[3].predicted_pc.valid
invalidate loop.io.resp_in[0].f3[3].is_jal
invalidate loop.io.resp_in[0].f3[3].is_br
invalidate loop.io.resp_in[0].f3[3].taken
invalidate loop.io.resp_in[0].f2[0].predicted_pc.bits
invalidate loop.io.resp_in[0].f2[0].predicted_pc.valid
invalidate loop.io.resp_in[0].f2[0].is_jal
invalidate loop.io.resp_in[0].f2[0].is_br
invalidate loop.io.resp_in[0].f2[0].taken
invalidate loop.io.resp_in[0].f2[1].predicted_pc.bits
invalidate loop.io.resp_in[0].f2[1].predicted_pc.valid
invalidate loop.io.resp_in[0].f2[1].is_jal
invalidate loop.io.resp_in[0].f2[1].is_br
invalidate loop.io.resp_in[0].f2[1].taken
invalidate loop.io.resp_in[0].f2[2].predicted_pc.bits
invalidate loop.io.resp_in[0].f2[2].predicted_pc.valid
invalidate loop.io.resp_in[0].f2[2].is_jal
invalidate loop.io.resp_in[0].f2[2].is_br
invalidate loop.io.resp_in[0].f2[2].taken
invalidate loop.io.resp_in[0].f2[3].predicted_pc.bits
invalidate loop.io.resp_in[0].f2[3].predicted_pc.valid
invalidate loop.io.resp_in[0].f2[3].is_jal
invalidate loop.io.resp_in[0].f2[3].is_br
invalidate loop.io.resp_in[0].f2[3].taken
invalidate loop.io.resp_in[0].f1[0].predicted_pc.bits
invalidate loop.io.resp_in[0].f1[0].predicted_pc.valid
invalidate loop.io.resp_in[0].f1[0].is_jal
invalidate loop.io.resp_in[0].f1[0].is_br
invalidate loop.io.resp_in[0].f1[0].taken
invalidate loop.io.resp_in[0].f1[1].predicted_pc.bits
invalidate loop.io.resp_in[0].f1[1].predicted_pc.valid
invalidate loop.io.resp_in[0].f1[1].is_jal
invalidate loop.io.resp_in[0].f1[1].is_br
invalidate loop.io.resp_in[0].f1[1].taken
invalidate loop.io.resp_in[0].f1[2].predicted_pc.bits
invalidate loop.io.resp_in[0].f1[2].predicted_pc.valid
invalidate loop.io.resp_in[0].f1[2].is_jal
invalidate loop.io.resp_in[0].f1[2].is_br
invalidate loop.io.resp_in[0].f1[2].taken
invalidate loop.io.resp_in[0].f1[3].predicted_pc.bits
invalidate loop.io.resp_in[0].f1[3].predicted_pc.valid
invalidate loop.io.resp_in[0].f1[3].is_jal
invalidate loop.io.resp_in[0].f1[3].is_br
invalidate loop.io.resp_in[0].f1[3].taken
invalidate loop.io.f1_lhist
invalidate loop.io.f1_ghist
invalidate loop.io.f0_mask
invalidate loop.io.f0_pc
invalidate loop.io.f0_valid
invalidate tage.io.update.bits.meta
invalidate tage.io.update.bits.target
invalidate tage.io.update.bits.lhist
invalidate tage.io.update.bits.ghist
invalidate tage.io.update.bits.cfi_is_jalr
invalidate tage.io.update.bits.cfi_is_jal
invalidate tage.io.update.bits.cfi_is_br
invalidate tage.io.update.bits.cfi_mispredicted
invalidate tage.io.update.bits.cfi_taken
invalidate tage.io.update.bits.cfi_idx.bits
invalidate tage.io.update.bits.cfi_idx.valid
invalidate tage.io.update.bits.br_mask
invalidate tage.io.update.bits.pc
invalidate tage.io.update.bits.btb_mispredicts
invalidate tage.io.update.bits.is_repair_update
invalidate tage.io.update.bits.is_mispredict_update
invalidate tage.io.update.valid
invalidate tage.io.f3_fire
invalidate tage.io.f3_meta
invalidate tage.io.resp.f3[0].predicted_pc.bits
invalidate tage.io.resp.f3[0].predicted_pc.valid
invalidate tage.io.resp.f3[0].is_jal
invalidate tage.io.resp.f3[0].is_br
invalidate tage.io.resp.f3[0].taken
invalidate tage.io.resp.f3[1].predicted_pc.bits
invalidate tage.io.resp.f3[1].predicted_pc.valid
invalidate tage.io.resp.f3[1].is_jal
invalidate tage.io.resp.f3[1].is_br
invalidate tage.io.resp.f3[1].taken
invalidate tage.io.resp.f3[2].predicted_pc.bits
invalidate tage.io.resp.f3[2].predicted_pc.valid
invalidate tage.io.resp.f3[2].is_jal
invalidate tage.io.resp.f3[2].is_br
invalidate tage.io.resp.f3[2].taken
invalidate tage.io.resp.f3[3].predicted_pc.bits
invalidate tage.io.resp.f3[3].predicted_pc.valid
invalidate tage.io.resp.f3[3].is_jal
invalidate tage.io.resp.f3[3].is_br
invalidate tage.io.resp.f3[3].taken
invalidate tage.io.resp.f2[0].predicted_pc.bits
invalidate tage.io.resp.f2[0].predicted_pc.valid
invalidate tage.io.resp.f2[0].is_jal
invalidate tage.io.resp.f2[0].is_br
invalidate tage.io.resp.f2[0].taken
invalidate tage.io.resp.f2[1].predicted_pc.bits
invalidate tage.io.resp.f2[1].predicted_pc.valid
invalidate tage.io.resp.f2[1].is_jal
invalidate tage.io.resp.f2[1].is_br
invalidate tage.io.resp.f2[1].taken
invalidate tage.io.resp.f2[2].predicted_pc.bits
invalidate tage.io.resp.f2[2].predicted_pc.valid
invalidate tage.io.resp.f2[2].is_jal
invalidate tage.io.resp.f2[2].is_br
invalidate tage.io.resp.f2[2].taken
invalidate tage.io.resp.f2[3].predicted_pc.bits
invalidate tage.io.resp.f2[3].predicted_pc.valid
invalidate tage.io.resp.f2[3].is_jal
invalidate tage.io.resp.f2[3].is_br
invalidate tage.io.resp.f2[3].taken
invalidate tage.io.resp.f1[0].predicted_pc.bits
invalidate tage.io.resp.f1[0].predicted_pc.valid
invalidate tage.io.resp.f1[0].is_jal
invalidate tage.io.resp.f1[0].is_br
invalidate tage.io.resp.f1[0].taken
invalidate tage.io.resp.f1[1].predicted_pc.bits
invalidate tage.io.resp.f1[1].predicted_pc.valid
invalidate tage.io.resp.f1[1].is_jal
invalidate tage.io.resp.f1[1].is_br
invalidate tage.io.resp.f1[1].taken
invalidate tage.io.resp.f1[2].predicted_pc.bits
invalidate tage.io.resp.f1[2].predicted_pc.valid
invalidate tage.io.resp.f1[2].is_jal
invalidate tage.io.resp.f1[2].is_br
invalidate tage.io.resp.f1[2].taken
invalidate tage.io.resp.f1[3].predicted_pc.bits
invalidate tage.io.resp.f1[3].predicted_pc.valid
invalidate tage.io.resp.f1[3].is_jal
invalidate tage.io.resp.f1[3].is_br
invalidate tage.io.resp.f1[3].taken
invalidate tage.io.resp_in[0].f3[0].predicted_pc.bits
invalidate tage.io.resp_in[0].f3[0].predicted_pc.valid
invalidate tage.io.resp_in[0].f3[0].is_jal
invalidate tage.io.resp_in[0].f3[0].is_br
invalidate tage.io.resp_in[0].f3[0].taken
invalidate tage.io.resp_in[0].f3[1].predicted_pc.bits
invalidate tage.io.resp_in[0].f3[1].predicted_pc.valid
invalidate tage.io.resp_in[0].f3[1].is_jal
invalidate tage.io.resp_in[0].f3[1].is_br
invalidate tage.io.resp_in[0].f3[1].taken
invalidate tage.io.resp_in[0].f3[2].predicted_pc.bits
invalidate tage.io.resp_in[0].f3[2].predicted_pc.valid
invalidate tage.io.resp_in[0].f3[2].is_jal
invalidate tage.io.resp_in[0].f3[2].is_br
invalidate tage.io.resp_in[0].f3[2].taken
invalidate tage.io.resp_in[0].f3[3].predicted_pc.bits
invalidate tage.io.resp_in[0].f3[3].predicted_pc.valid
invalidate tage.io.resp_in[0].f3[3].is_jal
invalidate tage.io.resp_in[0].f3[3].is_br
invalidate tage.io.resp_in[0].f3[3].taken
invalidate tage.io.resp_in[0].f2[0].predicted_pc.bits
invalidate tage.io.resp_in[0].f2[0].predicted_pc.valid
invalidate tage.io.resp_in[0].f2[0].is_jal
invalidate tage.io.resp_in[0].f2[0].is_br
invalidate tage.io.resp_in[0].f2[0].taken
invalidate tage.io.resp_in[0].f2[1].predicted_pc.bits
invalidate tage.io.resp_in[0].f2[1].predicted_pc.valid
invalidate tage.io.resp_in[0].f2[1].is_jal
invalidate tage.io.resp_in[0].f2[1].is_br
invalidate tage.io.resp_in[0].f2[1].taken
invalidate tage.io.resp_in[0].f2[2].predicted_pc.bits
invalidate tage.io.resp_in[0].f2[2].predicted_pc.valid
invalidate tage.io.resp_in[0].f2[2].is_jal
invalidate tage.io.resp_in[0].f2[2].is_br
invalidate tage.io.resp_in[0].f2[2].taken
invalidate tage.io.resp_in[0].f2[3].predicted_pc.bits
invalidate tage.io.resp_in[0].f2[3].predicted_pc.valid
invalidate tage.io.resp_in[0].f2[3].is_jal
invalidate tage.io.resp_in[0].f2[3].is_br
invalidate tage.io.resp_in[0].f2[3].taken
invalidate tage.io.resp_in[0].f1[0].predicted_pc.bits
invalidate tage.io.resp_in[0].f1[0].predicted_pc.valid
invalidate tage.io.resp_in[0].f1[0].is_jal
invalidate tage.io.resp_in[0].f1[0].is_br
invalidate tage.io.resp_in[0].f1[0].taken
invalidate tage.io.resp_in[0].f1[1].predicted_pc.bits
invalidate tage.io.resp_in[0].f1[1].predicted_pc.valid
invalidate tage.io.resp_in[0].f1[1].is_jal
invalidate tage.io.resp_in[0].f1[1].is_br
invalidate tage.io.resp_in[0].f1[1].taken
invalidate tage.io.resp_in[0].f1[2].predicted_pc.bits
invalidate tage.io.resp_in[0].f1[2].predicted_pc.valid
invalidate tage.io.resp_in[0].f1[2].is_jal
invalidate tage.io.resp_in[0].f1[2].is_br
invalidate tage.io.resp_in[0].f1[2].taken
invalidate tage.io.resp_in[0].f1[3].predicted_pc.bits
invalidate tage.io.resp_in[0].f1[3].predicted_pc.valid
invalidate tage.io.resp_in[0].f1[3].is_jal
invalidate tage.io.resp_in[0].f1[3].is_br
invalidate tage.io.resp_in[0].f1[3].taken
invalidate tage.io.f1_lhist
invalidate tage.io.f1_ghist
invalidate tage.io.f0_mask
invalidate tage.io.f0_pc
invalidate tage.io.f0_valid
invalidate btb.io.update.bits.meta
invalidate btb.io.update.bits.target
invalidate btb.io.update.bits.lhist
invalidate btb.io.update.bits.ghist
invalidate btb.io.update.bits.cfi_is_jalr
invalidate btb.io.update.bits.cfi_is_jal
invalidate btb.io.update.bits.cfi_is_br
invalidate btb.io.update.bits.cfi_mispredicted
invalidate btb.io.update.bits.cfi_taken
invalidate btb.io.update.bits.cfi_idx.bits
invalidate btb.io.update.bits.cfi_idx.valid
invalidate btb.io.update.bits.br_mask
invalidate btb.io.update.bits.pc
invalidate btb.io.update.bits.btb_mispredicts
invalidate btb.io.update.bits.is_repair_update
invalidate btb.io.update.bits.is_mispredict_update
invalidate btb.io.update.valid
invalidate btb.io.f3_fire
invalidate btb.io.f3_meta
invalidate btb.io.resp.f3[0].predicted_pc.bits
invalidate btb.io.resp.f3[0].predicted_pc.valid
invalidate btb.io.resp.f3[0].is_jal
invalidate btb.io.resp.f3[0].is_br
invalidate btb.io.resp.f3[0].taken
invalidate btb.io.resp.f3[1].predicted_pc.bits
invalidate btb.io.resp.f3[1].predicted_pc.valid
invalidate btb.io.resp.f3[1].is_jal
invalidate btb.io.resp.f3[1].is_br
invalidate btb.io.resp.f3[1].taken
invalidate btb.io.resp.f3[2].predicted_pc.bits
invalidate btb.io.resp.f3[2].predicted_pc.valid
invalidate btb.io.resp.f3[2].is_jal
invalidate btb.io.resp.f3[2].is_br
invalidate btb.io.resp.f3[2].taken
invalidate btb.io.resp.f3[3].predicted_pc.bits
invalidate btb.io.resp.f3[3].predicted_pc.valid
invalidate btb.io.resp.f3[3].is_jal
invalidate btb.io.resp.f3[3].is_br
invalidate btb.io.resp.f3[3].taken
invalidate btb.io.resp.f2[0].predicted_pc.bits
invalidate btb.io.resp.f2[0].predicted_pc.valid
invalidate btb.io.resp.f2[0].is_jal
invalidate btb.io.resp.f2[0].is_br
invalidate btb.io.resp.f2[0].taken
invalidate btb.io.resp.f2[1].predicted_pc.bits
invalidate btb.io.resp.f2[1].predicted_pc.valid
invalidate btb.io.resp.f2[1].is_jal
invalidate btb.io.resp.f2[1].is_br
invalidate btb.io.resp.f2[1].taken
invalidate btb.io.resp.f2[2].predicted_pc.bits
invalidate btb.io.resp.f2[2].predicted_pc.valid
invalidate btb.io.resp.f2[2].is_jal
invalidate btb.io.resp.f2[2].is_br
invalidate btb.io.resp.f2[2].taken
invalidate btb.io.resp.f2[3].predicted_pc.bits
invalidate btb.io.resp.f2[3].predicted_pc.valid
invalidate btb.io.resp.f2[3].is_jal
invalidate btb.io.resp.f2[3].is_br
invalidate btb.io.resp.f2[3].taken
invalidate btb.io.resp.f1[0].predicted_pc.bits
invalidate btb.io.resp.f1[0].predicted_pc.valid
invalidate btb.io.resp.f1[0].is_jal
invalidate btb.io.resp.f1[0].is_br
invalidate btb.io.resp.f1[0].taken
invalidate btb.io.resp.f1[1].predicted_pc.bits
invalidate btb.io.resp.f1[1].predicted_pc.valid
invalidate btb.io.resp.f1[1].is_jal
invalidate btb.io.resp.f1[1].is_br
invalidate btb.io.resp.f1[1].taken
invalidate btb.io.resp.f1[2].predicted_pc.bits
invalidate btb.io.resp.f1[2].predicted_pc.valid
invalidate btb.io.resp.f1[2].is_jal
invalidate btb.io.resp.f1[2].is_br
invalidate btb.io.resp.f1[2].taken
invalidate btb.io.resp.f1[3].predicted_pc.bits
invalidate btb.io.resp.f1[3].predicted_pc.valid
invalidate btb.io.resp.f1[3].is_jal
invalidate btb.io.resp.f1[3].is_br
invalidate btb.io.resp.f1[3].taken
invalidate btb.io.resp_in[0].f3[0].predicted_pc.bits
invalidate btb.io.resp_in[0].f3[0].predicted_pc.valid
invalidate btb.io.resp_in[0].f3[0].is_jal
invalidate btb.io.resp_in[0].f3[0].is_br
invalidate btb.io.resp_in[0].f3[0].taken
invalidate btb.io.resp_in[0].f3[1].predicted_pc.bits
invalidate btb.io.resp_in[0].f3[1].predicted_pc.valid
invalidate btb.io.resp_in[0].f3[1].is_jal
invalidate btb.io.resp_in[0].f3[1].is_br
invalidate btb.io.resp_in[0].f3[1].taken
invalidate btb.io.resp_in[0].f3[2].predicted_pc.bits
invalidate btb.io.resp_in[0].f3[2].predicted_pc.valid
invalidate btb.io.resp_in[0].f3[2].is_jal
invalidate btb.io.resp_in[0].f3[2].is_br
invalidate btb.io.resp_in[0].f3[2].taken
invalidate btb.io.resp_in[0].f3[3].predicted_pc.bits
invalidate btb.io.resp_in[0].f3[3].predicted_pc.valid
invalidate btb.io.resp_in[0].f3[3].is_jal
invalidate btb.io.resp_in[0].f3[3].is_br
invalidate btb.io.resp_in[0].f3[3].taken
invalidate btb.io.resp_in[0].f2[0].predicted_pc.bits
invalidate btb.io.resp_in[0].f2[0].predicted_pc.valid
invalidate btb.io.resp_in[0].f2[0].is_jal
invalidate btb.io.resp_in[0].f2[0].is_br
invalidate btb.io.resp_in[0].f2[0].taken
invalidate btb.io.resp_in[0].f2[1].predicted_pc.bits
invalidate btb.io.resp_in[0].f2[1].predicted_pc.valid
invalidate btb.io.resp_in[0].f2[1].is_jal
invalidate btb.io.resp_in[0].f2[1].is_br
invalidate btb.io.resp_in[0].f2[1].taken
invalidate btb.io.resp_in[0].f2[2].predicted_pc.bits
invalidate btb.io.resp_in[0].f2[2].predicted_pc.valid
invalidate btb.io.resp_in[0].f2[2].is_jal
invalidate btb.io.resp_in[0].f2[2].is_br
invalidate btb.io.resp_in[0].f2[2].taken
invalidate btb.io.resp_in[0].f2[3].predicted_pc.bits
invalidate btb.io.resp_in[0].f2[3].predicted_pc.valid
invalidate btb.io.resp_in[0].f2[3].is_jal
invalidate btb.io.resp_in[0].f2[3].is_br
invalidate btb.io.resp_in[0].f2[3].taken
invalidate btb.io.resp_in[0].f1[0].predicted_pc.bits
invalidate btb.io.resp_in[0].f1[0].predicted_pc.valid
invalidate btb.io.resp_in[0].f1[0].is_jal
invalidate btb.io.resp_in[0].f1[0].is_br
invalidate btb.io.resp_in[0].f1[0].taken
invalidate btb.io.resp_in[0].f1[1].predicted_pc.bits
invalidate btb.io.resp_in[0].f1[1].predicted_pc.valid
invalidate btb.io.resp_in[0].f1[1].is_jal
invalidate btb.io.resp_in[0].f1[1].is_br
invalidate btb.io.resp_in[0].f1[1].taken
invalidate btb.io.resp_in[0].f1[2].predicted_pc.bits
invalidate btb.io.resp_in[0].f1[2].predicted_pc.valid
invalidate btb.io.resp_in[0].f1[2].is_jal
invalidate btb.io.resp_in[0].f1[2].is_br
invalidate btb.io.resp_in[0].f1[2].taken
invalidate btb.io.resp_in[0].f1[3].predicted_pc.bits
invalidate btb.io.resp_in[0].f1[3].predicted_pc.valid
invalidate btb.io.resp_in[0].f1[3].is_jal
invalidate btb.io.resp_in[0].f1[3].is_br
invalidate btb.io.resp_in[0].f1[3].taken
invalidate btb.io.f1_lhist
invalidate btb.io.f1_ghist
invalidate btb.io.f0_mask
invalidate btb.io.f0_pc
invalidate btb.io.f0_valid
invalidate ubtb.io.update.bits.meta
invalidate ubtb.io.update.bits.target
invalidate ubtb.io.update.bits.lhist
invalidate ubtb.io.update.bits.ghist
invalidate ubtb.io.update.bits.cfi_is_jalr
invalidate ubtb.io.update.bits.cfi_is_jal
invalidate ubtb.io.update.bits.cfi_is_br
invalidate ubtb.io.update.bits.cfi_mispredicted
invalidate ubtb.io.update.bits.cfi_taken
invalidate ubtb.io.update.bits.cfi_idx.bits
invalidate ubtb.io.update.bits.cfi_idx.valid
invalidate ubtb.io.update.bits.br_mask
invalidate ubtb.io.update.bits.pc
invalidate ubtb.io.update.bits.btb_mispredicts
invalidate ubtb.io.update.bits.is_repair_update
invalidate ubtb.io.update.bits.is_mispredict_update
invalidate ubtb.io.update.valid
invalidate ubtb.io.f3_fire
invalidate ubtb.io.f3_meta
invalidate ubtb.io.resp.f3[0].predicted_pc.bits
invalidate ubtb.io.resp.f3[0].predicted_pc.valid
invalidate ubtb.io.resp.f3[0].is_jal
invalidate ubtb.io.resp.f3[0].is_br
invalidate ubtb.io.resp.f3[0].taken
invalidate ubtb.io.resp.f3[1].predicted_pc.bits
invalidate ubtb.io.resp.f3[1].predicted_pc.valid
invalidate ubtb.io.resp.f3[1].is_jal
invalidate ubtb.io.resp.f3[1].is_br
invalidate ubtb.io.resp.f3[1].taken
invalidate ubtb.io.resp.f3[2].predicted_pc.bits
invalidate ubtb.io.resp.f3[2].predicted_pc.valid
invalidate ubtb.io.resp.f3[2].is_jal
invalidate ubtb.io.resp.f3[2].is_br
invalidate ubtb.io.resp.f3[2].taken
invalidate ubtb.io.resp.f3[3].predicted_pc.bits
invalidate ubtb.io.resp.f3[3].predicted_pc.valid
invalidate ubtb.io.resp.f3[3].is_jal
invalidate ubtb.io.resp.f3[3].is_br
invalidate ubtb.io.resp.f3[3].taken
invalidate ubtb.io.resp.f2[0].predicted_pc.bits
invalidate ubtb.io.resp.f2[0].predicted_pc.valid
invalidate ubtb.io.resp.f2[0].is_jal
invalidate ubtb.io.resp.f2[0].is_br
invalidate ubtb.io.resp.f2[0].taken
invalidate ubtb.io.resp.f2[1].predicted_pc.bits
invalidate ubtb.io.resp.f2[1].predicted_pc.valid
invalidate ubtb.io.resp.f2[1].is_jal
invalidate ubtb.io.resp.f2[1].is_br
invalidate ubtb.io.resp.f2[1].taken
invalidate ubtb.io.resp.f2[2].predicted_pc.bits
invalidate ubtb.io.resp.f2[2].predicted_pc.valid
invalidate ubtb.io.resp.f2[2].is_jal
invalidate ubtb.io.resp.f2[2].is_br
invalidate ubtb.io.resp.f2[2].taken
invalidate ubtb.io.resp.f2[3].predicted_pc.bits
invalidate ubtb.io.resp.f2[3].predicted_pc.valid
invalidate ubtb.io.resp.f2[3].is_jal
invalidate ubtb.io.resp.f2[3].is_br
invalidate ubtb.io.resp.f2[3].taken
invalidate ubtb.io.resp.f1[0].predicted_pc.bits
invalidate ubtb.io.resp.f1[0].predicted_pc.valid
invalidate ubtb.io.resp.f1[0].is_jal
invalidate ubtb.io.resp.f1[0].is_br
invalidate ubtb.io.resp.f1[0].taken
invalidate ubtb.io.resp.f1[1].predicted_pc.bits
invalidate ubtb.io.resp.f1[1].predicted_pc.valid
invalidate ubtb.io.resp.f1[1].is_jal
invalidate ubtb.io.resp.f1[1].is_br
invalidate ubtb.io.resp.f1[1].taken
invalidate ubtb.io.resp.f1[2].predicted_pc.bits
invalidate ubtb.io.resp.f1[2].predicted_pc.valid
invalidate ubtb.io.resp.f1[2].is_jal
invalidate ubtb.io.resp.f1[2].is_br
invalidate ubtb.io.resp.f1[2].taken
invalidate ubtb.io.resp.f1[3].predicted_pc.bits
invalidate ubtb.io.resp.f1[3].predicted_pc.valid
invalidate ubtb.io.resp.f1[3].is_jal
invalidate ubtb.io.resp.f1[3].is_br
invalidate ubtb.io.resp.f1[3].taken
invalidate ubtb.io.resp_in[0].f3[0].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f3[0].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f3[0].is_jal
invalidate ubtb.io.resp_in[0].f3[0].is_br
invalidate ubtb.io.resp_in[0].f3[0].taken
invalidate ubtb.io.resp_in[0].f3[1].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f3[1].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f3[1].is_jal
invalidate ubtb.io.resp_in[0].f3[1].is_br
invalidate ubtb.io.resp_in[0].f3[1].taken
invalidate ubtb.io.resp_in[0].f3[2].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f3[2].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f3[2].is_jal
invalidate ubtb.io.resp_in[0].f3[2].is_br
invalidate ubtb.io.resp_in[0].f3[2].taken
invalidate ubtb.io.resp_in[0].f3[3].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f3[3].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f3[3].is_jal
invalidate ubtb.io.resp_in[0].f3[3].is_br
invalidate ubtb.io.resp_in[0].f3[3].taken
invalidate ubtb.io.resp_in[0].f2[0].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f2[0].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f2[0].is_jal
invalidate ubtb.io.resp_in[0].f2[0].is_br
invalidate ubtb.io.resp_in[0].f2[0].taken
invalidate ubtb.io.resp_in[0].f2[1].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f2[1].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f2[1].is_jal
invalidate ubtb.io.resp_in[0].f2[1].is_br
invalidate ubtb.io.resp_in[0].f2[1].taken
invalidate ubtb.io.resp_in[0].f2[2].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f2[2].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f2[2].is_jal
invalidate ubtb.io.resp_in[0].f2[2].is_br
invalidate ubtb.io.resp_in[0].f2[2].taken
invalidate ubtb.io.resp_in[0].f2[3].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f2[3].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f2[3].is_jal
invalidate ubtb.io.resp_in[0].f2[3].is_br
invalidate ubtb.io.resp_in[0].f2[3].taken
invalidate ubtb.io.resp_in[0].f1[0].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f1[0].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f1[0].is_jal
invalidate ubtb.io.resp_in[0].f1[0].is_br
invalidate ubtb.io.resp_in[0].f1[0].taken
invalidate ubtb.io.resp_in[0].f1[1].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f1[1].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f1[1].is_jal
invalidate ubtb.io.resp_in[0].f1[1].is_br
invalidate ubtb.io.resp_in[0].f1[1].taken
invalidate ubtb.io.resp_in[0].f1[2].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f1[2].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f1[2].is_jal
invalidate ubtb.io.resp_in[0].f1[2].is_br
invalidate ubtb.io.resp_in[0].f1[2].taken
invalidate ubtb.io.resp_in[0].f1[3].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f1[3].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f1[3].is_jal
invalidate ubtb.io.resp_in[0].f1[3].is_br
invalidate ubtb.io.resp_in[0].f1[3].taken
invalidate ubtb.io.f1_lhist
invalidate ubtb.io.f1_ghist
invalidate ubtb.io.f0_mask
invalidate ubtb.io.f0_pc
invalidate ubtb.io.f0_valid
invalidate bim.io.update.bits.meta
invalidate bim.io.update.bits.target
invalidate bim.io.update.bits.lhist
invalidate bim.io.update.bits.ghist
invalidate bim.io.update.bits.cfi_is_jalr
invalidate bim.io.update.bits.cfi_is_jal
invalidate bim.io.update.bits.cfi_is_br
invalidate bim.io.update.bits.cfi_mispredicted
invalidate bim.io.update.bits.cfi_taken
invalidate bim.io.update.bits.cfi_idx.bits
invalidate bim.io.update.bits.cfi_idx.valid
invalidate bim.io.update.bits.br_mask
invalidate bim.io.update.bits.pc
invalidate bim.io.update.bits.btb_mispredicts
invalidate bim.io.update.bits.is_repair_update
invalidate bim.io.update.bits.is_mispredict_update
invalidate bim.io.update.valid
invalidate bim.io.f3_fire
invalidate bim.io.f3_meta
invalidate bim.io.resp.f3[0].predicted_pc.bits
invalidate bim.io.resp.f3[0].predicted_pc.valid
invalidate bim.io.resp.f3[0].is_jal
invalidate bim.io.resp.f3[0].is_br
invalidate bim.io.resp.f3[0].taken
invalidate bim.io.resp.f3[1].predicted_pc.bits
invalidate bim.io.resp.f3[1].predicted_pc.valid
invalidate bim.io.resp.f3[1].is_jal
invalidate bim.io.resp.f3[1].is_br
invalidate bim.io.resp.f3[1].taken
invalidate bim.io.resp.f3[2].predicted_pc.bits
invalidate bim.io.resp.f3[2].predicted_pc.valid
invalidate bim.io.resp.f3[2].is_jal
invalidate bim.io.resp.f3[2].is_br
invalidate bim.io.resp.f3[2].taken
invalidate bim.io.resp.f3[3].predicted_pc.bits
invalidate bim.io.resp.f3[3].predicted_pc.valid
invalidate bim.io.resp.f3[3].is_jal
invalidate bim.io.resp.f3[3].is_br
invalidate bim.io.resp.f3[3].taken
invalidate bim.io.resp.f2[0].predicted_pc.bits
invalidate bim.io.resp.f2[0].predicted_pc.valid
invalidate bim.io.resp.f2[0].is_jal
invalidate bim.io.resp.f2[0].is_br
invalidate bim.io.resp.f2[0].taken
invalidate bim.io.resp.f2[1].predicted_pc.bits
invalidate bim.io.resp.f2[1].predicted_pc.valid
invalidate bim.io.resp.f2[1].is_jal
invalidate bim.io.resp.f2[1].is_br
invalidate bim.io.resp.f2[1].taken
invalidate bim.io.resp.f2[2].predicted_pc.bits
invalidate bim.io.resp.f2[2].predicted_pc.valid
invalidate bim.io.resp.f2[2].is_jal
invalidate bim.io.resp.f2[2].is_br
invalidate bim.io.resp.f2[2].taken
invalidate bim.io.resp.f2[3].predicted_pc.bits
invalidate bim.io.resp.f2[3].predicted_pc.valid
invalidate bim.io.resp.f2[3].is_jal
invalidate bim.io.resp.f2[3].is_br
invalidate bim.io.resp.f2[3].taken
invalidate bim.io.resp.f1[0].predicted_pc.bits
invalidate bim.io.resp.f1[0].predicted_pc.valid
invalidate bim.io.resp.f1[0].is_jal
invalidate bim.io.resp.f1[0].is_br
invalidate bim.io.resp.f1[0].taken
invalidate bim.io.resp.f1[1].predicted_pc.bits
invalidate bim.io.resp.f1[1].predicted_pc.valid
invalidate bim.io.resp.f1[1].is_jal
invalidate bim.io.resp.f1[1].is_br
invalidate bim.io.resp.f1[1].taken
invalidate bim.io.resp.f1[2].predicted_pc.bits
invalidate bim.io.resp.f1[2].predicted_pc.valid
invalidate bim.io.resp.f1[2].is_jal
invalidate bim.io.resp.f1[2].is_br
invalidate bim.io.resp.f1[2].taken
invalidate bim.io.resp.f1[3].predicted_pc.bits
invalidate bim.io.resp.f1[3].predicted_pc.valid
invalidate bim.io.resp.f1[3].is_jal
invalidate bim.io.resp.f1[3].is_br
invalidate bim.io.resp.f1[3].taken
invalidate bim.io.resp_in[0].f3[0].predicted_pc.bits
invalidate bim.io.resp_in[0].f3[0].predicted_pc.valid
invalidate bim.io.resp_in[0].f3[0].is_jal
invalidate bim.io.resp_in[0].f3[0].is_br
invalidate bim.io.resp_in[0].f3[0].taken
invalidate bim.io.resp_in[0].f3[1].predicted_pc.bits
invalidate bim.io.resp_in[0].f3[1].predicted_pc.valid
invalidate bim.io.resp_in[0].f3[1].is_jal
invalidate bim.io.resp_in[0].f3[1].is_br
invalidate bim.io.resp_in[0].f3[1].taken
invalidate bim.io.resp_in[0].f3[2].predicted_pc.bits
invalidate bim.io.resp_in[0].f3[2].predicted_pc.valid
invalidate bim.io.resp_in[0].f3[2].is_jal
invalidate bim.io.resp_in[0].f3[2].is_br
invalidate bim.io.resp_in[0].f3[2].taken
invalidate bim.io.resp_in[0].f3[3].predicted_pc.bits
invalidate bim.io.resp_in[0].f3[3].predicted_pc.valid
invalidate bim.io.resp_in[0].f3[3].is_jal
invalidate bim.io.resp_in[0].f3[3].is_br
invalidate bim.io.resp_in[0].f3[3].taken
invalidate bim.io.resp_in[0].f2[0].predicted_pc.bits
invalidate bim.io.resp_in[0].f2[0].predicted_pc.valid
invalidate bim.io.resp_in[0].f2[0].is_jal
invalidate bim.io.resp_in[0].f2[0].is_br
invalidate bim.io.resp_in[0].f2[0].taken
invalidate bim.io.resp_in[0].f2[1].predicted_pc.bits
invalidate bim.io.resp_in[0].f2[1].predicted_pc.valid
invalidate bim.io.resp_in[0].f2[1].is_jal
invalidate bim.io.resp_in[0].f2[1].is_br
invalidate bim.io.resp_in[0].f2[1].taken
invalidate bim.io.resp_in[0].f2[2].predicted_pc.bits
invalidate bim.io.resp_in[0].f2[2].predicted_pc.valid
invalidate bim.io.resp_in[0].f2[2].is_jal
invalidate bim.io.resp_in[0].f2[2].is_br
invalidate bim.io.resp_in[0].f2[2].taken
invalidate bim.io.resp_in[0].f2[3].predicted_pc.bits
invalidate bim.io.resp_in[0].f2[3].predicted_pc.valid
invalidate bim.io.resp_in[0].f2[3].is_jal
invalidate bim.io.resp_in[0].f2[3].is_br
invalidate bim.io.resp_in[0].f2[3].taken
invalidate bim.io.resp_in[0].f1[0].predicted_pc.bits
invalidate bim.io.resp_in[0].f1[0].predicted_pc.valid
invalidate bim.io.resp_in[0].f1[0].is_jal
invalidate bim.io.resp_in[0].f1[0].is_br
invalidate bim.io.resp_in[0].f1[0].taken
invalidate bim.io.resp_in[0].f1[1].predicted_pc.bits
invalidate bim.io.resp_in[0].f1[1].predicted_pc.valid
invalidate bim.io.resp_in[0].f1[1].is_jal
invalidate bim.io.resp_in[0].f1[1].is_br
invalidate bim.io.resp_in[0].f1[1].taken
invalidate bim.io.resp_in[0].f1[2].predicted_pc.bits
invalidate bim.io.resp_in[0].f1[2].predicted_pc.valid
invalidate bim.io.resp_in[0].f1[2].is_jal
invalidate bim.io.resp_in[0].f1[2].is_br
invalidate bim.io.resp_in[0].f1[2].taken
invalidate bim.io.resp_in[0].f1[3].predicted_pc.bits
invalidate bim.io.resp_in[0].f1[3].predicted_pc.valid
invalidate bim.io.resp_in[0].f1[3].is_jal
invalidate bim.io.resp_in[0].f1[3].is_br
invalidate bim.io.resp_in[0].f1[3].taken
invalidate bim.io.f1_lhist
invalidate bim.io.f1_ghist
invalidate bim.io.f0_mask
invalidate bim.io.f0_pc
invalidate bim.io.f0_valid
connect ubtb.io.resp_in[0].f3[0].predicted_pc.bits, io.resp_in[0].f3[0].predicted_pc.bits
connect ubtb.io.resp_in[0].f3[0].predicted_pc.valid, io.resp_in[0].f3[0].predicted_pc.valid
connect ubtb.io.resp_in[0].f3[0].is_jal, io.resp_in[0].f3[0].is_jal
connect ubtb.io.resp_in[0].f3[0].is_br, io.resp_in[0].f3[0].is_br
connect ubtb.io.resp_in[0].f3[0].taken, io.resp_in[0].f3[0].taken
connect ubtb.io.resp_in[0].f3[1].predicted_pc.bits, io.resp_in[0].f3[1].predicted_pc.bits
connect ubtb.io.resp_in[0].f3[1].predicted_pc.valid, io.resp_in[0].f3[1].predicted_pc.valid
connect ubtb.io.resp_in[0].f3[1].is_jal, io.resp_in[0].f3[1].is_jal
connect ubtb.io.resp_in[0].f3[1].is_br, io.resp_in[0].f3[1].is_br
connect ubtb.io.resp_in[0].f3[1].taken, io.resp_in[0].f3[1].taken
connect ubtb.io.resp_in[0].f3[2].predicted_pc.bits, io.resp_in[0].f3[2].predicted_pc.bits
connect ubtb.io.resp_in[0].f3[2].predicted_pc.valid, io.resp_in[0].f3[2].predicted_pc.valid
connect ubtb.io.resp_in[0].f3[2].is_jal, io.resp_in[0].f3[2].is_jal
connect ubtb.io.resp_in[0].f3[2].is_br, io.resp_in[0].f3[2].is_br
connect ubtb.io.resp_in[0].f3[2].taken, io.resp_in[0].f3[2].taken
connect ubtb.io.resp_in[0].f3[3].predicted_pc.bits, io.resp_in[0].f3[3].predicted_pc.bits
connect ubtb.io.resp_in[0].f3[3].predicted_pc.valid, io.resp_in[0].f3[3].predicted_pc.valid
connect ubtb.io.resp_in[0].f3[3].is_jal, io.resp_in[0].f3[3].is_jal
connect ubtb.io.resp_in[0].f3[3].is_br, io.resp_in[0].f3[3].is_br
connect ubtb.io.resp_in[0].f3[3].taken, io.resp_in[0].f3[3].taken
connect ubtb.io.resp_in[0].f2[0].predicted_pc.bits, io.resp_in[0].f2[0].predicted_pc.bits
connect ubtb.io.resp_in[0].f2[0].predicted_pc.valid, io.resp_in[0].f2[0].predicted_pc.valid
connect ubtb.io.resp_in[0].f2[0].is_jal, io.resp_in[0].f2[0].is_jal
connect ubtb.io.resp_in[0].f2[0].is_br, io.resp_in[0].f2[0].is_br
connect ubtb.io.resp_in[0].f2[0].taken, io.resp_in[0].f2[0].taken
connect ubtb.io.resp_in[0].f2[1].predicted_pc.bits, io.resp_in[0].f2[1].predicted_pc.bits
connect ubtb.io.resp_in[0].f2[1].predicted_pc.valid, io.resp_in[0].f2[1].predicted_pc.valid
connect ubtb.io.resp_in[0].f2[1].is_jal, io.resp_in[0].f2[1].is_jal
connect ubtb.io.resp_in[0].f2[1].is_br, io.resp_in[0].f2[1].is_br
connect ubtb.io.resp_in[0].f2[1].taken, io.resp_in[0].f2[1].taken
connect ubtb.io.resp_in[0].f2[2].predicted_pc.bits, io.resp_in[0].f2[2].predicted_pc.bits
connect ubtb.io.resp_in[0].f2[2].predicted_pc.valid, io.resp_in[0].f2[2].predicted_pc.valid
connect ubtb.io.resp_in[0].f2[2].is_jal, io.resp_in[0].f2[2].is_jal
connect ubtb.io.resp_in[0].f2[2].is_br, io.resp_in[0].f2[2].is_br
connect ubtb.io.resp_in[0].f2[2].taken, io.resp_in[0].f2[2].taken
connect ubtb.io.resp_in[0].f2[3].predicted_pc.bits, io.resp_in[0].f2[3].predicted_pc.bits
connect ubtb.io.resp_in[0].f2[3].predicted_pc.valid, io.resp_in[0].f2[3].predicted_pc.valid
connect ubtb.io.resp_in[0].f2[3].is_jal, io.resp_in[0].f2[3].is_jal
connect ubtb.io.resp_in[0].f2[3].is_br, io.resp_in[0].f2[3].is_br
connect ubtb.io.resp_in[0].f2[3].taken, io.resp_in[0].f2[3].taken
connect ubtb.io.resp_in[0].f1[0].predicted_pc.bits, io.resp_in[0].f1[0].predicted_pc.bits
connect ubtb.io.resp_in[0].f1[0].predicted_pc.valid, io.resp_in[0].f1[0].predicted_pc.valid
connect ubtb.io.resp_in[0].f1[0].is_jal, io.resp_in[0].f1[0].is_jal
connect ubtb.io.resp_in[0].f1[0].is_br, io.resp_in[0].f1[0].is_br
connect ubtb.io.resp_in[0].f1[0].taken, io.resp_in[0].f1[0].taken
connect ubtb.io.resp_in[0].f1[1].predicted_pc.bits, io.resp_in[0].f1[1].predicted_pc.bits
connect ubtb.io.resp_in[0].f1[1].predicted_pc.valid, io.resp_in[0].f1[1].predicted_pc.valid
connect ubtb.io.resp_in[0].f1[1].is_jal, io.resp_in[0].f1[1].is_jal
connect ubtb.io.resp_in[0].f1[1].is_br, io.resp_in[0].f1[1].is_br
connect ubtb.io.resp_in[0].f1[1].taken, io.resp_in[0].f1[1].taken
connect ubtb.io.resp_in[0].f1[2].predicted_pc.bits, io.resp_in[0].f1[2].predicted_pc.bits
connect ubtb.io.resp_in[0].f1[2].predicted_pc.valid, io.resp_in[0].f1[2].predicted_pc.valid
connect ubtb.io.resp_in[0].f1[2].is_jal, io.resp_in[0].f1[2].is_jal
connect ubtb.io.resp_in[0].f1[2].is_br, io.resp_in[0].f1[2].is_br
connect ubtb.io.resp_in[0].f1[2].taken, io.resp_in[0].f1[2].taken
connect ubtb.io.resp_in[0].f1[3].predicted_pc.bits, io.resp_in[0].f1[3].predicted_pc.bits
connect ubtb.io.resp_in[0].f1[3].predicted_pc.valid, io.resp_in[0].f1[3].predicted_pc.valid
connect ubtb.io.resp_in[0].f1[3].is_jal, io.resp_in[0].f1[3].is_jal
connect ubtb.io.resp_in[0].f1[3].is_br, io.resp_in[0].f1[3].is_br
connect ubtb.io.resp_in[0].f1[3].taken, io.resp_in[0].f1[3].taken
connect bim.io.resp_in[0].f3[0].predicted_pc.bits, ubtb.io.resp.f3[0].predicted_pc.bits
connect bim.io.resp_in[0].f3[0].predicted_pc.valid, ubtb.io.resp.f3[0].predicted_pc.valid
connect bim.io.resp_in[0].f3[0].is_jal, ubtb.io.resp.f3[0].is_jal
connect bim.io.resp_in[0].f3[0].is_br, ubtb.io.resp.f3[0].is_br
connect bim.io.resp_in[0].f3[0].taken, ubtb.io.resp.f3[0].taken
connect bim.io.resp_in[0].f3[1].predicted_pc.bits, ubtb.io.resp.f3[1].predicted_pc.bits
connect bim.io.resp_in[0].f3[1].predicted_pc.valid, ubtb.io.resp.f3[1].predicted_pc.valid
connect bim.io.resp_in[0].f3[1].is_jal, ubtb.io.resp.f3[1].is_jal
connect bim.io.resp_in[0].f3[1].is_br, ubtb.io.resp.f3[1].is_br
connect bim.io.resp_in[0].f3[1].taken, ubtb.io.resp.f3[1].taken
connect bim.io.resp_in[0].f3[2].predicted_pc.bits, ubtb.io.resp.f3[2].predicted_pc.bits
connect bim.io.resp_in[0].f3[2].predicted_pc.valid, ubtb.io.resp.f3[2].predicted_pc.valid
connect bim.io.resp_in[0].f3[2].is_jal, ubtb.io.resp.f3[2].is_jal
connect bim.io.resp_in[0].f3[2].is_br, ubtb.io.resp.f3[2].is_br
connect bim.io.resp_in[0].f3[2].taken, ubtb.io.resp.f3[2].taken
connect bim.io.resp_in[0].f3[3].predicted_pc.bits, ubtb.io.resp.f3[3].predicted_pc.bits
connect bim.io.resp_in[0].f3[3].predicted_pc.valid, ubtb.io.resp.f3[3].predicted_pc.valid
connect bim.io.resp_in[0].f3[3].is_jal, ubtb.io.resp.f3[3].is_jal
connect bim.io.resp_in[0].f3[3].is_br, ubtb.io.resp.f3[3].is_br
connect bim.io.resp_in[0].f3[3].taken, ubtb.io.resp.f3[3].taken
connect bim.io.resp_in[0].f2[0].predicted_pc.bits, ubtb.io.resp.f2[0].predicted_pc.bits
connect bim.io.resp_in[0].f2[0].predicted_pc.valid, ubtb.io.resp.f2[0].predicted_pc.valid
connect bim.io.resp_in[0].f2[0].is_jal, ubtb.io.resp.f2[0].is_jal
connect bim.io.resp_in[0].f2[0].is_br, ubtb.io.resp.f2[0].is_br
connect bim.io.resp_in[0].f2[0].taken, ubtb.io.resp.f2[0].taken
connect bim.io.resp_in[0].f2[1].predicted_pc.bits, ubtb.io.resp.f2[1].predicted_pc.bits
connect bim.io.resp_in[0].f2[1].predicted_pc.valid, ubtb.io.resp.f2[1].predicted_pc.valid
connect bim.io.resp_in[0].f2[1].is_jal, ubtb.io.resp.f2[1].is_jal
connect bim.io.resp_in[0].f2[1].is_br, ubtb.io.resp.f2[1].is_br
connect bim.io.resp_in[0].f2[1].taken, ubtb.io.resp.f2[1].taken
connect bim.io.resp_in[0].f2[2].predicted_pc.bits, ubtb.io.resp.f2[2].predicted_pc.bits
connect bim.io.resp_in[0].f2[2].predicted_pc.valid, ubtb.io.resp.f2[2].predicted_pc.valid
connect bim.io.resp_in[0].f2[2].is_jal, ubtb.io.resp.f2[2].is_jal
connect bim.io.resp_in[0].f2[2].is_br, ubtb.io.resp.f2[2].is_br
connect bim.io.resp_in[0].f2[2].taken, ubtb.io.resp.f2[2].taken
connect bim.io.resp_in[0].f2[3].predicted_pc.bits, ubtb.io.resp.f2[3].predicted_pc.bits
connect bim.io.resp_in[0].f2[3].predicted_pc.valid, ubtb.io.resp.f2[3].predicted_pc.valid
connect bim.io.resp_in[0].f2[3].is_jal, ubtb.io.resp.f2[3].is_jal
connect bim.io.resp_in[0].f2[3].is_br, ubtb.io.resp.f2[3].is_br
connect bim.io.resp_in[0].f2[3].taken, ubtb.io.resp.f2[3].taken
connect bim.io.resp_in[0].f1[0].predicted_pc.bits, ubtb.io.resp.f1[0].predicted_pc.bits
connect bim.io.resp_in[0].f1[0].predicted_pc.valid, ubtb.io.resp.f1[0].predicted_pc.valid
connect bim.io.resp_in[0].f1[0].is_jal, ubtb.io.resp.f1[0].is_jal
connect bim.io.resp_in[0].f1[0].is_br, ubtb.io.resp.f1[0].is_br
connect bim.io.resp_in[0].f1[0].taken, ubtb.io.resp.f1[0].taken
connect bim.io.resp_in[0].f1[1].predicted_pc.bits, ubtb.io.resp.f1[1].predicted_pc.bits
connect bim.io.resp_in[0].f1[1].predicted_pc.valid, ubtb.io.resp.f1[1].predicted_pc.valid
connect bim.io.resp_in[0].f1[1].is_jal, ubtb.io.resp.f1[1].is_jal
connect bim.io.resp_in[0].f1[1].is_br, ubtb.io.resp.f1[1].is_br
connect bim.io.resp_in[0].f1[1].taken, ubtb.io.resp.f1[1].taken
connect bim.io.resp_in[0].f1[2].predicted_pc.bits, ubtb.io.resp.f1[2].predicted_pc.bits
connect bim.io.resp_in[0].f1[2].predicted_pc.valid, ubtb.io.resp.f1[2].predicted_pc.valid
connect bim.io.resp_in[0].f1[2].is_jal, ubtb.io.resp.f1[2].is_jal
connect bim.io.resp_in[0].f1[2].is_br, ubtb.io.resp.f1[2].is_br
connect bim.io.resp_in[0].f1[2].taken, ubtb.io.resp.f1[2].taken
connect bim.io.resp_in[0].f1[3].predicted_pc.bits, ubtb.io.resp.f1[3].predicted_pc.bits
connect bim.io.resp_in[0].f1[3].predicted_pc.valid, ubtb.io.resp.f1[3].predicted_pc.valid
connect bim.io.resp_in[0].f1[3].is_jal, ubtb.io.resp.f1[3].is_jal
connect bim.io.resp_in[0].f1[3].is_br, ubtb.io.resp.f1[3].is_br
connect bim.io.resp_in[0].f1[3].taken, ubtb.io.resp.f1[3].taken
connect btb.io.resp_in[0].f3[0].predicted_pc.bits, bim.io.resp.f3[0].predicted_pc.bits
connect btb.io.resp_in[0].f3[0].predicted_pc.valid, bim.io.resp.f3[0].predicted_pc.valid
connect btb.io.resp_in[0].f3[0].is_jal, bim.io.resp.f3[0].is_jal
connect btb.io.resp_in[0].f3[0].is_br, bim.io.resp.f3[0].is_br
connect btb.io.resp_in[0].f3[0].taken, bim.io.resp.f3[0].taken
connect btb.io.resp_in[0].f3[1].predicted_pc.bits, bim.io.resp.f3[1].predicted_pc.bits
connect btb.io.resp_in[0].f3[1].predicted_pc.valid, bim.io.resp.f3[1].predicted_pc.valid
connect btb.io.resp_in[0].f3[1].is_jal, bim.io.resp.f3[1].is_jal
connect btb.io.resp_in[0].f3[1].is_br, bim.io.resp.f3[1].is_br
connect btb.io.resp_in[0].f3[1].taken, bim.io.resp.f3[1].taken
connect btb.io.resp_in[0].f3[2].predicted_pc.bits, bim.io.resp.f3[2].predicted_pc.bits
connect btb.io.resp_in[0].f3[2].predicted_pc.valid, bim.io.resp.f3[2].predicted_pc.valid
connect btb.io.resp_in[0].f3[2].is_jal, bim.io.resp.f3[2].is_jal
connect btb.io.resp_in[0].f3[2].is_br, bim.io.resp.f3[2].is_br
connect btb.io.resp_in[0].f3[2].taken, bim.io.resp.f3[2].taken
connect btb.io.resp_in[0].f3[3].predicted_pc.bits, bim.io.resp.f3[3].predicted_pc.bits
connect btb.io.resp_in[0].f3[3].predicted_pc.valid, bim.io.resp.f3[3].predicted_pc.valid
connect btb.io.resp_in[0].f3[3].is_jal, bim.io.resp.f3[3].is_jal
connect btb.io.resp_in[0].f3[3].is_br, bim.io.resp.f3[3].is_br
connect btb.io.resp_in[0].f3[3].taken, bim.io.resp.f3[3].taken
connect btb.io.resp_in[0].f2[0].predicted_pc.bits, bim.io.resp.f2[0].predicted_pc.bits
connect btb.io.resp_in[0].f2[0].predicted_pc.valid, bim.io.resp.f2[0].predicted_pc.valid
connect btb.io.resp_in[0].f2[0].is_jal, bim.io.resp.f2[0].is_jal
connect btb.io.resp_in[0].f2[0].is_br, bim.io.resp.f2[0].is_br
connect btb.io.resp_in[0].f2[0].taken, bim.io.resp.f2[0].taken
connect btb.io.resp_in[0].f2[1].predicted_pc.bits, bim.io.resp.f2[1].predicted_pc.bits
connect btb.io.resp_in[0].f2[1].predicted_pc.valid, bim.io.resp.f2[1].predicted_pc.valid
connect btb.io.resp_in[0].f2[1].is_jal, bim.io.resp.f2[1].is_jal
connect btb.io.resp_in[0].f2[1].is_br, bim.io.resp.f2[1].is_br
connect btb.io.resp_in[0].f2[1].taken, bim.io.resp.f2[1].taken
connect btb.io.resp_in[0].f2[2].predicted_pc.bits, bim.io.resp.f2[2].predicted_pc.bits
connect btb.io.resp_in[0].f2[2].predicted_pc.valid, bim.io.resp.f2[2].predicted_pc.valid
connect btb.io.resp_in[0].f2[2].is_jal, bim.io.resp.f2[2].is_jal
connect btb.io.resp_in[0].f2[2].is_br, bim.io.resp.f2[2].is_br
connect btb.io.resp_in[0].f2[2].taken, bim.io.resp.f2[2].taken
connect btb.io.resp_in[0].f2[3].predicted_pc.bits, bim.io.resp.f2[3].predicted_pc.bits
connect btb.io.resp_in[0].f2[3].predicted_pc.valid, bim.io.resp.f2[3].predicted_pc.valid
connect btb.io.resp_in[0].f2[3].is_jal, bim.io.resp.f2[3].is_jal
connect btb.io.resp_in[0].f2[3].is_br, bim.io.resp.f2[3].is_br
connect btb.io.resp_in[0].f2[3].taken, bim.io.resp.f2[3].taken
connect btb.io.resp_in[0].f1[0].predicted_pc.bits, bim.io.resp.f1[0].predicted_pc.bits
connect btb.io.resp_in[0].f1[0].predicted_pc.valid, bim.io.resp.f1[0].predicted_pc.valid
connect btb.io.resp_in[0].f1[0].is_jal, bim.io.resp.f1[0].is_jal
connect btb.io.resp_in[0].f1[0].is_br, bim.io.resp.f1[0].is_br
connect btb.io.resp_in[0].f1[0].taken, bim.io.resp.f1[0].taken
connect btb.io.resp_in[0].f1[1].predicted_pc.bits, bim.io.resp.f1[1].predicted_pc.bits
connect btb.io.resp_in[0].f1[1].predicted_pc.valid, bim.io.resp.f1[1].predicted_pc.valid
connect btb.io.resp_in[0].f1[1].is_jal, bim.io.resp.f1[1].is_jal
connect btb.io.resp_in[0].f1[1].is_br, bim.io.resp.f1[1].is_br
connect btb.io.resp_in[0].f1[1].taken, bim.io.resp.f1[1].taken
connect btb.io.resp_in[0].f1[2].predicted_pc.bits, bim.io.resp.f1[2].predicted_pc.bits
connect btb.io.resp_in[0].f1[2].predicted_pc.valid, bim.io.resp.f1[2].predicted_pc.valid
connect btb.io.resp_in[0].f1[2].is_jal, bim.io.resp.f1[2].is_jal
connect btb.io.resp_in[0].f1[2].is_br, bim.io.resp.f1[2].is_br
connect btb.io.resp_in[0].f1[2].taken, bim.io.resp.f1[2].taken
connect btb.io.resp_in[0].f1[3].predicted_pc.bits, bim.io.resp.f1[3].predicted_pc.bits
connect btb.io.resp_in[0].f1[3].predicted_pc.valid, bim.io.resp.f1[3].predicted_pc.valid
connect btb.io.resp_in[0].f1[3].is_jal, bim.io.resp.f1[3].is_jal
connect btb.io.resp_in[0].f1[3].is_br, bim.io.resp.f1[3].is_br
connect btb.io.resp_in[0].f1[3].taken, bim.io.resp.f1[3].taken
connect tage.io.resp_in[0].f3[0].predicted_pc.bits, btb.io.resp.f3[0].predicted_pc.bits
connect tage.io.resp_in[0].f3[0].predicted_pc.valid, btb.io.resp.f3[0].predicted_pc.valid
connect tage.io.resp_in[0].f3[0].is_jal, btb.io.resp.f3[0].is_jal
connect tage.io.resp_in[0].f3[0].is_br, btb.io.resp.f3[0].is_br
connect tage.io.resp_in[0].f3[0].taken, btb.io.resp.f3[0].taken
connect tage.io.resp_in[0].f3[1].predicted_pc.bits, btb.io.resp.f3[1].predicted_pc.bits
connect tage.io.resp_in[0].f3[1].predicted_pc.valid, btb.io.resp.f3[1].predicted_pc.valid
connect tage.io.resp_in[0].f3[1].is_jal, btb.io.resp.f3[1].is_jal
connect tage.io.resp_in[0].f3[1].is_br, btb.io.resp.f3[1].is_br
connect tage.io.resp_in[0].f3[1].taken, btb.io.resp.f3[1].taken
connect tage.io.resp_in[0].f3[2].predicted_pc.bits, btb.io.resp.f3[2].predicted_pc.bits
connect tage.io.resp_in[0].f3[2].predicted_pc.valid, btb.io.resp.f3[2].predicted_pc.valid
connect tage.io.resp_in[0].f3[2].is_jal, btb.io.resp.f3[2].is_jal
connect tage.io.resp_in[0].f3[2].is_br, btb.io.resp.f3[2].is_br
connect tage.io.resp_in[0].f3[2].taken, btb.io.resp.f3[2].taken
connect tage.io.resp_in[0].f3[3].predicted_pc.bits, btb.io.resp.f3[3].predicted_pc.bits
connect tage.io.resp_in[0].f3[3].predicted_pc.valid, btb.io.resp.f3[3].predicted_pc.valid
connect tage.io.resp_in[0].f3[3].is_jal, btb.io.resp.f3[3].is_jal
connect tage.io.resp_in[0].f3[3].is_br, btb.io.resp.f3[3].is_br
connect tage.io.resp_in[0].f3[3].taken, btb.io.resp.f3[3].taken
connect tage.io.resp_in[0].f2[0].predicted_pc.bits, btb.io.resp.f2[0].predicted_pc.bits
connect tage.io.resp_in[0].f2[0].predicted_pc.valid, btb.io.resp.f2[0].predicted_pc.valid
connect tage.io.resp_in[0].f2[0].is_jal, btb.io.resp.f2[0].is_jal
connect tage.io.resp_in[0].f2[0].is_br, btb.io.resp.f2[0].is_br
connect tage.io.resp_in[0].f2[0].taken, btb.io.resp.f2[0].taken
connect tage.io.resp_in[0].f2[1].predicted_pc.bits, btb.io.resp.f2[1].predicted_pc.bits
connect tage.io.resp_in[0].f2[1].predicted_pc.valid, btb.io.resp.f2[1].predicted_pc.valid
connect tage.io.resp_in[0].f2[1].is_jal, btb.io.resp.f2[1].is_jal
connect tage.io.resp_in[0].f2[1].is_br, btb.io.resp.f2[1].is_br
connect tage.io.resp_in[0].f2[1].taken, btb.io.resp.f2[1].taken
connect tage.io.resp_in[0].f2[2].predicted_pc.bits, btb.io.resp.f2[2].predicted_pc.bits
connect tage.io.resp_in[0].f2[2].predicted_pc.valid, btb.io.resp.f2[2].predicted_pc.valid
connect tage.io.resp_in[0].f2[2].is_jal, btb.io.resp.f2[2].is_jal
connect tage.io.resp_in[0].f2[2].is_br, btb.io.resp.f2[2].is_br
connect tage.io.resp_in[0].f2[2].taken, btb.io.resp.f2[2].taken
connect tage.io.resp_in[0].f2[3].predicted_pc.bits, btb.io.resp.f2[3].predicted_pc.bits
connect tage.io.resp_in[0].f2[3].predicted_pc.valid, btb.io.resp.f2[3].predicted_pc.valid
connect tage.io.resp_in[0].f2[3].is_jal, btb.io.resp.f2[3].is_jal
connect tage.io.resp_in[0].f2[3].is_br, btb.io.resp.f2[3].is_br
connect tage.io.resp_in[0].f2[3].taken, btb.io.resp.f2[3].taken
connect tage.io.resp_in[0].f1[0].predicted_pc.bits, btb.io.resp.f1[0].predicted_pc.bits
connect tage.io.resp_in[0].f1[0].predicted_pc.valid, btb.io.resp.f1[0].predicted_pc.valid
connect tage.io.resp_in[0].f1[0].is_jal, btb.io.resp.f1[0].is_jal
connect tage.io.resp_in[0].f1[0].is_br, btb.io.resp.f1[0].is_br
connect tage.io.resp_in[0].f1[0].taken, btb.io.resp.f1[0].taken
connect tage.io.resp_in[0].f1[1].predicted_pc.bits, btb.io.resp.f1[1].predicted_pc.bits
connect tage.io.resp_in[0].f1[1].predicted_pc.valid, btb.io.resp.f1[1].predicted_pc.valid
connect tage.io.resp_in[0].f1[1].is_jal, btb.io.resp.f1[1].is_jal
connect tage.io.resp_in[0].f1[1].is_br, btb.io.resp.f1[1].is_br
connect tage.io.resp_in[0].f1[1].taken, btb.io.resp.f1[1].taken
connect tage.io.resp_in[0].f1[2].predicted_pc.bits, btb.io.resp.f1[2].predicted_pc.bits
connect tage.io.resp_in[0].f1[2].predicted_pc.valid, btb.io.resp.f1[2].predicted_pc.valid
connect tage.io.resp_in[0].f1[2].is_jal, btb.io.resp.f1[2].is_jal
connect tage.io.resp_in[0].f1[2].is_br, btb.io.resp.f1[2].is_br
connect tage.io.resp_in[0].f1[2].taken, btb.io.resp.f1[2].taken
connect tage.io.resp_in[0].f1[3].predicted_pc.bits, btb.io.resp.f1[3].predicted_pc.bits
connect tage.io.resp_in[0].f1[3].predicted_pc.valid, btb.io.resp.f1[3].predicted_pc.valid
connect tage.io.resp_in[0].f1[3].is_jal, btb.io.resp.f1[3].is_jal
connect tage.io.resp_in[0].f1[3].is_br, btb.io.resp.f1[3].is_br
connect tage.io.resp_in[0].f1[3].taken, btb.io.resp.f1[3].taken
connect loop.io.resp_in[0].f3[0].predicted_pc.bits, tage.io.resp.f3[0].predicted_pc.bits
connect loop.io.resp_in[0].f3[0].predicted_pc.valid, tage.io.resp.f3[0].predicted_pc.valid
connect loop.io.resp_in[0].f3[0].is_jal, tage.io.resp.f3[0].is_jal
connect loop.io.resp_in[0].f3[0].is_br, tage.io.resp.f3[0].is_br
connect loop.io.resp_in[0].f3[0].taken, tage.io.resp.f3[0].taken
connect loop.io.resp_in[0].f3[1].predicted_pc.bits, tage.io.resp.f3[1].predicted_pc.bits
connect loop.io.resp_in[0].f3[1].predicted_pc.valid, tage.io.resp.f3[1].predicted_pc.valid
connect loop.io.resp_in[0].f3[1].is_jal, tage.io.resp.f3[1].is_jal
connect loop.io.resp_in[0].f3[1].is_br, tage.io.resp.f3[1].is_br
connect loop.io.resp_in[0].f3[1].taken, tage.io.resp.f3[1].taken
connect loop.io.resp_in[0].f3[2].predicted_pc.bits, tage.io.resp.f3[2].predicted_pc.bits
connect loop.io.resp_in[0].f3[2].predicted_pc.valid, tage.io.resp.f3[2].predicted_pc.valid
connect loop.io.resp_in[0].f3[2].is_jal, tage.io.resp.f3[2].is_jal
connect loop.io.resp_in[0].f3[2].is_br, tage.io.resp.f3[2].is_br
connect loop.io.resp_in[0].f3[2].taken, tage.io.resp.f3[2].taken
connect loop.io.resp_in[0].f3[3].predicted_pc.bits, tage.io.resp.f3[3].predicted_pc.bits
connect loop.io.resp_in[0].f3[3].predicted_pc.valid, tage.io.resp.f3[3].predicted_pc.valid
connect loop.io.resp_in[0].f3[3].is_jal, tage.io.resp.f3[3].is_jal
connect loop.io.resp_in[0].f3[3].is_br, tage.io.resp.f3[3].is_br
connect loop.io.resp_in[0].f3[3].taken, tage.io.resp.f3[3].taken
connect loop.io.resp_in[0].f2[0].predicted_pc.bits, tage.io.resp.f2[0].predicted_pc.bits
connect loop.io.resp_in[0].f2[0].predicted_pc.valid, tage.io.resp.f2[0].predicted_pc.valid
connect loop.io.resp_in[0].f2[0].is_jal, tage.io.resp.f2[0].is_jal
connect loop.io.resp_in[0].f2[0].is_br, tage.io.resp.f2[0].is_br
connect loop.io.resp_in[0].f2[0].taken, tage.io.resp.f2[0].taken
connect loop.io.resp_in[0].f2[1].predicted_pc.bits, tage.io.resp.f2[1].predicted_pc.bits
connect loop.io.resp_in[0].f2[1].predicted_pc.valid, tage.io.resp.f2[1].predicted_pc.valid
connect loop.io.resp_in[0].f2[1].is_jal, tage.io.resp.f2[1].is_jal
connect loop.io.resp_in[0].f2[1].is_br, tage.io.resp.f2[1].is_br
connect loop.io.resp_in[0].f2[1].taken, tage.io.resp.f2[1].taken
connect loop.io.resp_in[0].f2[2].predicted_pc.bits, tage.io.resp.f2[2].predicted_pc.bits
connect loop.io.resp_in[0].f2[2].predicted_pc.valid, tage.io.resp.f2[2].predicted_pc.valid
connect loop.io.resp_in[0].f2[2].is_jal, tage.io.resp.f2[2].is_jal
connect loop.io.resp_in[0].f2[2].is_br, tage.io.resp.f2[2].is_br
connect loop.io.resp_in[0].f2[2].taken, tage.io.resp.f2[2].taken
connect loop.io.resp_in[0].f2[3].predicted_pc.bits, tage.io.resp.f2[3].predicted_pc.bits
connect loop.io.resp_in[0].f2[3].predicted_pc.valid, tage.io.resp.f2[3].predicted_pc.valid
connect loop.io.resp_in[0].f2[3].is_jal, tage.io.resp.f2[3].is_jal
connect loop.io.resp_in[0].f2[3].is_br, tage.io.resp.f2[3].is_br
connect loop.io.resp_in[0].f2[3].taken, tage.io.resp.f2[3].taken
connect loop.io.resp_in[0].f1[0].predicted_pc.bits, tage.io.resp.f1[0].predicted_pc.bits
connect loop.io.resp_in[0].f1[0].predicted_pc.valid, tage.io.resp.f1[0].predicted_pc.valid
connect loop.io.resp_in[0].f1[0].is_jal, tage.io.resp.f1[0].is_jal
connect loop.io.resp_in[0].f1[0].is_br, tage.io.resp.f1[0].is_br
connect loop.io.resp_in[0].f1[0].taken, tage.io.resp.f1[0].taken
connect loop.io.resp_in[0].f1[1].predicted_pc.bits, tage.io.resp.f1[1].predicted_pc.bits
connect loop.io.resp_in[0].f1[1].predicted_pc.valid, tage.io.resp.f1[1].predicted_pc.valid
connect loop.io.resp_in[0].f1[1].is_jal, tage.io.resp.f1[1].is_jal
connect loop.io.resp_in[0].f1[1].is_br, tage.io.resp.f1[1].is_br
connect loop.io.resp_in[0].f1[1].taken, tage.io.resp.f1[1].taken
connect loop.io.resp_in[0].f1[2].predicted_pc.bits, tage.io.resp.f1[2].predicted_pc.bits
connect loop.io.resp_in[0].f1[2].predicted_pc.valid, tage.io.resp.f1[2].predicted_pc.valid
connect loop.io.resp_in[0].f1[2].is_jal, tage.io.resp.f1[2].is_jal
connect loop.io.resp_in[0].f1[2].is_br, tage.io.resp.f1[2].is_br
connect loop.io.resp_in[0].f1[2].taken, tage.io.resp.f1[2].taken
connect loop.io.resp_in[0].f1[3].predicted_pc.bits, tage.io.resp.f1[3].predicted_pc.bits
connect loop.io.resp_in[0].f1[3].predicted_pc.valid, tage.io.resp.f1[3].predicted_pc.valid
connect loop.io.resp_in[0].f1[3].is_jal, tage.io.resp.f1[3].is_jal
connect loop.io.resp_in[0].f1[3].is_br, tage.io.resp.f1[3].is_br
connect loop.io.resp_in[0].f1[3].taken, tage.io.resp.f1[3].taken
connect io.resp, loop.io.resp
connect loop.io.f0_valid, io.f0_valid
connect loop.io.f0_pc, io.f0_pc
connect loop.io.f0_mask, io.f0_mask
connect loop.io.f1_ghist, io.f1_ghist
connect loop.io.f1_lhist, io.f1_lhist
connect loop.io.f3_fire, io.f3_fire
node _T = shl(UInt<1>(0h0), 40)
node _T_1 = bits(loop.io.f3_meta, 39, 0)
node _T_2 = or(_T, _T_1)
connect tage.io.f0_valid, io.f0_valid
connect tage.io.f0_pc, io.f0_pc
connect tage.io.f0_mask, io.f0_mask
connect tage.io.f1_ghist, io.f1_ghist
connect tage.io.f1_lhist, io.f1_lhist
connect tage.io.f3_fire, io.f3_fire
node _T_3 = shl(_T_2, 56)
node _T_4 = bits(tage.io.f3_meta, 55, 0)
node _T_5 = or(_T_3, _T_4)
connect btb.io.f0_valid, io.f0_valid
connect btb.io.f0_pc, io.f0_pc
connect btb.io.f0_mask, io.f0_mask
connect btb.io.f1_ghist, io.f1_ghist
connect btb.io.f1_lhist, io.f1_lhist
connect btb.io.f3_fire, io.f3_fire
node _T_6 = shl(_T_5, 1)
node _T_7 = bits(btb.io.f3_meta, 0, 0)
node _T_8 = or(_T_6, _T_7)
connect ubtb.io.f0_valid, io.f0_valid
connect ubtb.io.f0_pc, io.f0_pc
connect ubtb.io.f0_mask, io.f0_mask
connect ubtb.io.f1_ghist, io.f1_ghist
connect ubtb.io.f1_lhist, io.f1_lhist
connect ubtb.io.f3_fire, io.f3_fire
node _T_9 = shl(_T_8, 8)
node _T_10 = bits(ubtb.io.f3_meta, 7, 0)
node _T_11 = or(_T_9, _T_10)
connect bim.io.f0_valid, io.f0_valid
connect bim.io.f0_pc, io.f0_pc
connect bim.io.f0_mask, io.f0_mask
connect bim.io.f1_ghist, io.f1_ghist
connect bim.io.f1_lhist, io.f1_lhist
connect bim.io.f3_fire, io.f3_fire
node _T_12 = shl(_T_11, 8)
node _T_13 = bits(bim.io.f3_meta, 7, 0)
node _T_14 = or(_T_12, _T_13)
connect io.f3_meta, _T_14
connect bim.io.update.bits.meta, io.update.bits.meta
connect bim.io.update.bits.target, io.update.bits.target
connect bim.io.update.bits.lhist, io.update.bits.lhist
connect bim.io.update.bits.ghist, io.update.bits.ghist
connect bim.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect bim.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect bim.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect bim.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect bim.io.update.bits.cfi_taken, io.update.bits.cfi_taken
connect bim.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect bim.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect bim.io.update.bits.br_mask, io.update.bits.br_mask
connect bim.io.update.bits.pc, io.update.bits.pc
connect bim.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect bim.io.update.bits.is_repair_update, io.update.bits.is_repair_update
connect bim.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect bim.io.update.valid, io.update.valid
connect bim.io.update.bits.meta, io.update.bits.meta
node _T_15 = shr(io.update.bits.meta, 8)
connect ubtb.io.update.bits.meta, io.update.bits.meta
connect ubtb.io.update.bits.target, io.update.bits.target
connect ubtb.io.update.bits.lhist, io.update.bits.lhist
connect ubtb.io.update.bits.ghist, io.update.bits.ghist
connect ubtb.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect ubtb.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect ubtb.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect ubtb.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect ubtb.io.update.bits.cfi_taken, io.update.bits.cfi_taken
connect ubtb.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect ubtb.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect ubtb.io.update.bits.br_mask, io.update.bits.br_mask
connect ubtb.io.update.bits.pc, io.update.bits.pc
connect ubtb.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect ubtb.io.update.bits.is_repair_update, io.update.bits.is_repair_update
connect ubtb.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect ubtb.io.update.valid, io.update.valid
connect ubtb.io.update.bits.meta, _T_15
node _T_16 = shr(_T_15, 8)
connect btb.io.update.bits.meta, io.update.bits.meta
connect btb.io.update.bits.target, io.update.bits.target
connect btb.io.update.bits.lhist, io.update.bits.lhist
connect btb.io.update.bits.ghist, io.update.bits.ghist
connect btb.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect btb.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect btb.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect btb.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect btb.io.update.bits.cfi_taken, io.update.bits.cfi_taken
connect btb.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect btb.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect btb.io.update.bits.br_mask, io.update.bits.br_mask
connect btb.io.update.bits.pc, io.update.bits.pc
connect btb.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect btb.io.update.bits.is_repair_update, io.update.bits.is_repair_update
connect btb.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect btb.io.update.valid, io.update.valid
connect btb.io.update.bits.meta, _T_16
node _T_17 = shr(_T_16, 1)
connect tage.io.update.bits.meta, io.update.bits.meta
connect tage.io.update.bits.target, io.update.bits.target
connect tage.io.update.bits.lhist, io.update.bits.lhist
connect tage.io.update.bits.ghist, io.update.bits.ghist
connect tage.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect tage.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect tage.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect tage.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect tage.io.update.bits.cfi_taken, io.update.bits.cfi_taken
connect tage.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect tage.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect tage.io.update.bits.br_mask, io.update.bits.br_mask
connect tage.io.update.bits.pc, io.update.bits.pc
connect tage.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect tage.io.update.bits.is_repair_update, io.update.bits.is_repair_update
connect tage.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect tage.io.update.valid, io.update.valid
connect tage.io.update.bits.meta, _T_17
node _T_18 = shr(_T_17, 56)
connect loop.io.update.bits.meta, io.update.bits.meta
connect loop.io.update.bits.target, io.update.bits.target
connect loop.io.update.bits.lhist, io.update.bits.lhist
connect loop.io.update.bits.ghist, io.update.bits.ghist
connect loop.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect loop.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect loop.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect loop.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect loop.io.update.bits.cfi_taken, io.update.bits.cfi_taken
connect loop.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect loop.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect loop.io.update.bits.br_mask, io.update.bits.br_mask
connect loop.io.update.bits.pc, io.update.bits.pc
connect loop.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect loop.io.update.bits.is_repair_update, io.update.bits.is_repair_update
connect loop.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect loop.io.update.valid, io.update.valid
connect loop.io.update.bits.meta, _T_18
node _T_19 = shr(_T_18, 40) | module ComposedBranchPredictorBank_2( // @[composer.scala:14:7]
input clock, // @[composer.scala:14:7]
input reset, // @[composer.scala:14:7]
input io_f0_valid, // @[predictor.scala:140:14]
input [39:0] io_f0_pc, // @[predictor.scala:140:14]
input [3:0] io_f0_mask, // @[predictor.scala:140:14]
input [63:0] io_f1_ghist, // @[predictor.scala:140:14]
output io_resp_f1_0_taken, // @[predictor.scala:140:14]
output io_resp_f1_0_is_br, // @[predictor.scala:140:14]
output io_resp_f1_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_1_taken, // @[predictor.scala:140:14]
output io_resp_f1_1_is_br, // @[predictor.scala:140:14]
output io_resp_f1_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_2_taken, // @[predictor.scala:140:14]
output io_resp_f1_2_is_br, // @[predictor.scala:140:14]
output io_resp_f1_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_3_taken, // @[predictor.scala:140:14]
output io_resp_f1_3_is_br, // @[predictor.scala:140:14]
output io_resp_f1_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_0_taken, // @[predictor.scala:140:14]
output io_resp_f2_0_is_br, // @[predictor.scala:140:14]
output io_resp_f2_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_1_taken, // @[predictor.scala:140:14]
output io_resp_f2_1_is_br, // @[predictor.scala:140:14]
output io_resp_f2_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_2_taken, // @[predictor.scala:140:14]
output io_resp_f2_2_is_br, // @[predictor.scala:140:14]
output io_resp_f2_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_3_taken, // @[predictor.scala:140:14]
output io_resp_f2_3_is_br, // @[predictor.scala:140:14]
output io_resp_f2_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_0_taken, // @[predictor.scala:140:14]
output io_resp_f3_0_is_br, // @[predictor.scala:140:14]
output io_resp_f3_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_1_taken, // @[predictor.scala:140:14]
output io_resp_f3_1_is_br, // @[predictor.scala:140:14]
output io_resp_f3_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_2_taken, // @[predictor.scala:140:14]
output io_resp_f3_2_is_br, // @[predictor.scala:140:14]
output io_resp_f3_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_3_taken, // @[predictor.scala:140:14]
output io_resp_f3_3_is_br, // @[predictor.scala:140:14]
output io_resp_f3_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14]
output [119:0] io_f3_meta, // @[predictor.scala:140:14]
input io_f3_fire, // @[predictor.scala:140:14]
input io_update_valid, // @[predictor.scala:140:14]
input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14]
input io_update_bits_is_repair_update, // @[predictor.scala:140:14]
input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14]
input [39:0] io_update_bits_pc, // @[predictor.scala:140:14]
input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14]
input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14]
input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14]
input io_update_bits_cfi_taken, // @[predictor.scala:140:14]
input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_br, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14]
input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14]
input io_update_bits_lhist, // @[predictor.scala:140:14]
input [39:0] io_update_bits_target, // @[predictor.scala:140:14]
input [119:0] io_update_bits_meta // @[predictor.scala:140:14]
);
wire _ubtb_io_resp_f1_0_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_0_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_0_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_1_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_1_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_1_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_2_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_2_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_2_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_3_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_3_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_3_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_0_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_0_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_0_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_1_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_1_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_1_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_2_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_2_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_2_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_3_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_3_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_3_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_0_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_0_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_0_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_1_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_1_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_1_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_2_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_2_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_2_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_3_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_3_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_3_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire [119:0] _ubtb_io_f3_meta; // @[config-mixins.scala:449:26]
wire _bim_io_resp_f1_0_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_0_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_0_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_1_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_1_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_1_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_2_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_2_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_2_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_3_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_3_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_3_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_0_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_0_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_0_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_1_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_1_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_1_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_2_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_2_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_2_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_3_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_3_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_3_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_0_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_0_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_0_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_1_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_1_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_1_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_2_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_2_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_2_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_3_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_3_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_3_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire [119:0] _bim_io_f3_meta; // @[config-mixins.scala:448:25]
wire _btb_io_resp_f1_0_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_0_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_0_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_1_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_1_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_1_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_2_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_2_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_2_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_3_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_3_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_3_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_0_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_0_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_0_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_1_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_1_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_1_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_2_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_2_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_2_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_3_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_3_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_3_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_0_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_0_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_0_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_1_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_1_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_1_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_2_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_2_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_2_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_3_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_3_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_3_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire [119:0] _btb_io_f3_meta; // @[config-mixins.scala:447:25]
wire _tage_io_resp_f1_0_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_0_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_0_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_1_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_1_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_1_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_2_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_2_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_2_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_3_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_3_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_3_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_0_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_0_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_0_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_1_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_1_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_1_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_2_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_2_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_2_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_3_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_3_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_3_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_0_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_0_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_0_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_1_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_1_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_1_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_2_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_2_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_2_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_3_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_3_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_3_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire [119:0] _tage_io_f3_meta; // @[config-mixins.scala:446:26]
wire [119:0] _loop_io_f3_meta; // @[config-mixins.scala:445:26]
wire io_f0_valid_0 = io_f0_valid; // @[composer.scala:14:7]
wire [39:0] io_f0_pc_0 = io_f0_pc; // @[composer.scala:14:7]
wire [3:0] io_f0_mask_0 = io_f0_mask; // @[composer.scala:14:7]
wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[composer.scala:14:7]
wire io_f3_fire_0 = io_f3_fire; // @[composer.scala:14:7]
wire io_update_valid_0 = io_update_valid; // @[composer.scala:14:7]
wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[composer.scala:14:7]
wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[composer.scala:14:7]
wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[composer.scala:14:7]
wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[composer.scala:14:7]
wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[composer.scala:14:7]
wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[composer.scala:14:7]
wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[composer.scala:14:7]
wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[composer.scala:14:7]
wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[composer.scala:14:7]
wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[composer.scala:14:7]
wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[composer.scala:14:7]
wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[composer.scala:14:7]
wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[composer.scala:14:7]
wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[composer.scala:14:7]
wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[composer.scala:14:7]
wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[composer.scala:14:7]
wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire io_f1_lhist = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_0_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_0_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_0_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_0_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_1_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_1_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_1_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_1_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_2_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_2_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_2_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_2_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_3_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_3_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_3_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_3_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_0_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_0_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_0_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_0_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_1_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_1_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_1_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_1_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_2_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_2_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_2_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_2_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_3_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_3_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_3_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_3_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_0_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_0_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_0_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_0_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_1_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_1_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_1_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_1_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_2_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_2_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_2_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_2_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_3_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_3_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_3_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_3_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_f1_0_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f1_0_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f1_0_taken_0; // @[composer.scala:14:7]
wire io_resp_f1_0_is_br_0; // @[composer.scala:14:7]
wire io_resp_f1_0_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f1_1_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f1_1_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f1_1_taken_0; // @[composer.scala:14:7]
wire io_resp_f1_1_is_br_0; // @[composer.scala:14:7]
wire io_resp_f1_1_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f1_2_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f1_2_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f1_2_taken_0; // @[composer.scala:14:7]
wire io_resp_f1_2_is_br_0; // @[composer.scala:14:7]
wire io_resp_f1_2_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f1_3_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f1_3_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f1_3_taken_0; // @[composer.scala:14:7]
wire io_resp_f1_3_is_br_0; // @[composer.scala:14:7]
wire io_resp_f1_3_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f2_0_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f2_0_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f2_0_taken_0; // @[composer.scala:14:7]
wire io_resp_f2_0_is_br_0; // @[composer.scala:14:7]
wire io_resp_f2_0_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f2_1_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f2_1_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f2_1_taken_0; // @[composer.scala:14:7]
wire io_resp_f2_1_is_br_0; // @[composer.scala:14:7]
wire io_resp_f2_1_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f2_2_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f2_2_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f2_2_taken_0; // @[composer.scala:14:7]
wire io_resp_f2_2_is_br_0; // @[composer.scala:14:7]
wire io_resp_f2_2_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f2_3_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f2_3_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f2_3_taken_0; // @[composer.scala:14:7]
wire io_resp_f2_3_is_br_0; // @[composer.scala:14:7]
wire io_resp_f2_3_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f3_0_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f3_0_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f3_0_taken_0; // @[composer.scala:14:7]
wire io_resp_f3_0_is_br_0; // @[composer.scala:14:7]
wire io_resp_f3_0_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f3_1_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f3_1_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f3_1_taken_0; // @[composer.scala:14:7]
wire io_resp_f3_1_is_br_0; // @[composer.scala:14:7]
wire io_resp_f3_1_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f3_2_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f3_2_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f3_2_taken_0; // @[composer.scala:14:7]
wire io_resp_f3_2_is_br_0; // @[composer.scala:14:7]
wire io_resp_f3_2_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f3_3_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f3_3_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f3_3_taken_0; // @[composer.scala:14:7]
wire io_resp_f3_3_is_br_0; // @[composer.scala:14:7]
wire io_resp_f3_3_is_jal_0; // @[composer.scala:14:7]
wire [119:0] io_f3_meta_0; // @[composer.scala:14:7]
wire [35:0] s0_idx = io_f0_pc_0[39:4]; // @[frontend.scala:162:35]
reg [35:0] s1_idx; // @[predictor.scala:163:29]
reg [35:0] s2_idx; // @[predictor.scala:164:29]
reg [35:0] s3_idx; // @[predictor.scala:165:29]
reg s1_valid; // @[predictor.scala:168:25]
reg s2_valid; // @[predictor.scala:169:25]
reg s3_valid; // @[predictor.scala:170:25]
reg [3:0] s1_mask; // @[predictor.scala:173:24]
reg [3:0] s2_mask; // @[predictor.scala:174:24]
reg [3:0] s3_mask; // @[predictor.scala:175:24]
reg [39:0] s1_pc; // @[predictor.scala:178:22]
wire [35:0] s0_update_idx = io_update_bits_pc_0[39:4]; // @[frontend.scala:162:35]
reg s1_update_valid; // @[predictor.scala:184:30]
reg s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30]
reg s1_update_bits_is_repair_update; // @[predictor.scala:184:30]
reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30]
reg [39:0] s1_update_bits_pc; // @[predictor.scala:184:30]
reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30]
reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_taken; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_br; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:184:30]
reg [63:0] s1_update_bits_ghist; // @[predictor.scala:184:30]
reg s1_update_bits_lhist; // @[predictor.scala:184:30]
reg [39:0] s1_update_bits_target; // @[predictor.scala:184:30]
reg [119:0] s1_update_bits_meta; // @[predictor.scala:184:30]
reg [35:0] s1_update_idx; // @[predictor.scala:185:30]
reg s1_update_valid_0; // @[predictor.scala:186:32]
assign io_f3_meta_0 = {7'h0, _loop_io_f3_meta[39:0], _tage_io_f3_meta[55:0], _btb_io_f3_meta[0], _ubtb_io_f3_meta[7:0], _bim_io_f3_meta[7:0]}; // @[composer.scala:14:7, :31:49, :36:14]
always @(posedge clock) begin // @[composer.scala:14:7]
s1_idx <= s0_idx; // @[frontend.scala:162:35]
s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29]
s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29]
s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25]
s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25]
s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25]
s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24]
s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24]
s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24]
s1_pc <= io_f0_pc_0; // @[predictor.scala:178:22]
s1_update_valid <= io_update_valid_0; // @[predictor.scala:184:30]
s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:184:30]
s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:184:30]
s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:184:30]
s1_update_bits_pc <= io_update_bits_pc_0; // @[predictor.scala:184:30]
s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:184:30]
s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:184:30]
s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:184:30]
s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:184:30]
s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:184:30]
s1_update_idx <= s0_update_idx; // @[frontend.scala:162:35]
s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:186:32]
always @(posedge)
LoopBranchPredictorBank_2 loop ( // @[config-mixins.scala:445:26]
.clock (clock),
.reset (reset),
.io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7]
.io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7]
.io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7]
.io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7]
.io_resp_in_0_f1_0_taken (_tage_io_resp_f1_0_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_0_is_br (_tage_io_resp_f1_0_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_0_is_jal (_tage_io_resp_f1_0_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_0_predicted_pc_valid (_tage_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_0_predicted_pc_bits (_tage_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_1_taken (_tage_io_resp_f1_1_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_1_is_br (_tage_io_resp_f1_1_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_1_is_jal (_tage_io_resp_f1_1_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_1_predicted_pc_valid (_tage_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_1_predicted_pc_bits (_tage_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_2_taken (_tage_io_resp_f1_2_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_2_is_br (_tage_io_resp_f1_2_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_2_is_jal (_tage_io_resp_f1_2_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_2_predicted_pc_valid (_tage_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_2_predicted_pc_bits (_tage_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_3_taken (_tage_io_resp_f1_3_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_3_is_br (_tage_io_resp_f1_3_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_3_is_jal (_tage_io_resp_f1_3_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_3_predicted_pc_valid (_tage_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_3_predicted_pc_bits (_tage_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_0_taken (_tage_io_resp_f2_0_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_0_is_br (_tage_io_resp_f2_0_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_0_is_jal (_tage_io_resp_f2_0_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_0_predicted_pc_valid (_tage_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_0_predicted_pc_bits (_tage_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_1_taken (_tage_io_resp_f2_1_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_1_is_br (_tage_io_resp_f2_1_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_1_is_jal (_tage_io_resp_f2_1_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_1_predicted_pc_valid (_tage_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_1_predicted_pc_bits (_tage_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_2_taken (_tage_io_resp_f2_2_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_2_is_br (_tage_io_resp_f2_2_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_2_is_jal (_tage_io_resp_f2_2_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_2_predicted_pc_valid (_tage_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_2_predicted_pc_bits (_tage_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_3_taken (_tage_io_resp_f2_3_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_3_is_br (_tage_io_resp_f2_3_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_3_is_jal (_tage_io_resp_f2_3_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_3_predicted_pc_valid (_tage_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_3_predicted_pc_bits (_tage_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_0_taken (_tage_io_resp_f3_0_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_0_is_br (_tage_io_resp_f3_0_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_0_is_jal (_tage_io_resp_f3_0_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_0_predicted_pc_valid (_tage_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_0_predicted_pc_bits (_tage_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_1_taken (_tage_io_resp_f3_1_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_1_is_br (_tage_io_resp_f3_1_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_1_is_jal (_tage_io_resp_f3_1_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_1_predicted_pc_valid (_tage_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_1_predicted_pc_bits (_tage_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_2_taken (_tage_io_resp_f3_2_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_2_is_br (_tage_io_resp_f3_2_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_2_is_jal (_tage_io_resp_f3_2_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_2_predicted_pc_valid (_tage_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_2_predicted_pc_bits (_tage_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_3_taken (_tage_io_resp_f3_3_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_3_is_br (_tage_io_resp_f3_3_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_3_is_jal (_tage_io_resp_f3_3_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_3_predicted_pc_valid (_tage_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_3_predicted_pc_bits (_tage_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_f1_0_taken (io_resp_f1_0_taken_0),
.io_resp_f1_0_is_br (io_resp_f1_0_is_br_0),
.io_resp_f1_0_is_jal (io_resp_f1_0_is_jal_0),
.io_resp_f1_0_predicted_pc_valid (io_resp_f1_0_predicted_pc_valid_0),
.io_resp_f1_0_predicted_pc_bits (io_resp_f1_0_predicted_pc_bits_0),
.io_resp_f1_1_taken (io_resp_f1_1_taken_0),
.io_resp_f1_1_is_br (io_resp_f1_1_is_br_0),
.io_resp_f1_1_is_jal (io_resp_f1_1_is_jal_0),
.io_resp_f1_1_predicted_pc_valid (io_resp_f1_1_predicted_pc_valid_0),
.io_resp_f1_1_predicted_pc_bits (io_resp_f1_1_predicted_pc_bits_0),
.io_resp_f1_2_taken (io_resp_f1_2_taken_0),
.io_resp_f1_2_is_br (io_resp_f1_2_is_br_0),
.io_resp_f1_2_is_jal (io_resp_f1_2_is_jal_0),
.io_resp_f1_2_predicted_pc_valid (io_resp_f1_2_predicted_pc_valid_0),
.io_resp_f1_2_predicted_pc_bits (io_resp_f1_2_predicted_pc_bits_0),
.io_resp_f1_3_taken (io_resp_f1_3_taken_0),
.io_resp_f1_3_is_br (io_resp_f1_3_is_br_0),
.io_resp_f1_3_is_jal (io_resp_f1_3_is_jal_0),
.io_resp_f1_3_predicted_pc_valid (io_resp_f1_3_predicted_pc_valid_0),
.io_resp_f1_3_predicted_pc_bits (io_resp_f1_3_predicted_pc_bits_0),
.io_resp_f2_0_taken (io_resp_f2_0_taken_0),
.io_resp_f2_0_is_br (io_resp_f2_0_is_br_0),
.io_resp_f2_0_is_jal (io_resp_f2_0_is_jal_0),
.io_resp_f2_0_predicted_pc_valid (io_resp_f2_0_predicted_pc_valid_0),
.io_resp_f2_0_predicted_pc_bits (io_resp_f2_0_predicted_pc_bits_0),
.io_resp_f2_1_taken (io_resp_f2_1_taken_0),
.io_resp_f2_1_is_br (io_resp_f2_1_is_br_0),
.io_resp_f2_1_is_jal (io_resp_f2_1_is_jal_0),
.io_resp_f2_1_predicted_pc_valid (io_resp_f2_1_predicted_pc_valid_0),
.io_resp_f2_1_predicted_pc_bits (io_resp_f2_1_predicted_pc_bits_0),
.io_resp_f2_2_taken (io_resp_f2_2_taken_0),
.io_resp_f2_2_is_br (io_resp_f2_2_is_br_0),
.io_resp_f2_2_is_jal (io_resp_f2_2_is_jal_0),
.io_resp_f2_2_predicted_pc_valid (io_resp_f2_2_predicted_pc_valid_0),
.io_resp_f2_2_predicted_pc_bits (io_resp_f2_2_predicted_pc_bits_0),
.io_resp_f2_3_taken (io_resp_f2_3_taken_0),
.io_resp_f2_3_is_br (io_resp_f2_3_is_br_0),
.io_resp_f2_3_is_jal (io_resp_f2_3_is_jal_0),
.io_resp_f2_3_predicted_pc_valid (io_resp_f2_3_predicted_pc_valid_0),
.io_resp_f2_3_predicted_pc_bits (io_resp_f2_3_predicted_pc_bits_0),
.io_resp_f3_0_taken (io_resp_f3_0_taken_0),
.io_resp_f3_0_is_br (io_resp_f3_0_is_br_0),
.io_resp_f3_0_is_jal (io_resp_f3_0_is_jal_0),
.io_resp_f3_0_predicted_pc_valid (io_resp_f3_0_predicted_pc_valid_0),
.io_resp_f3_0_predicted_pc_bits (io_resp_f3_0_predicted_pc_bits_0),
.io_resp_f3_1_taken (io_resp_f3_1_taken_0),
.io_resp_f3_1_is_br (io_resp_f3_1_is_br_0),
.io_resp_f3_1_is_jal (io_resp_f3_1_is_jal_0),
.io_resp_f3_1_predicted_pc_valid (io_resp_f3_1_predicted_pc_valid_0),
.io_resp_f3_1_predicted_pc_bits (io_resp_f3_1_predicted_pc_bits_0),
.io_resp_f3_2_taken (io_resp_f3_2_taken_0),
.io_resp_f3_2_is_br (io_resp_f3_2_is_br_0),
.io_resp_f3_2_is_jal (io_resp_f3_2_is_jal_0),
.io_resp_f3_2_predicted_pc_valid (io_resp_f3_2_predicted_pc_valid_0),
.io_resp_f3_2_predicted_pc_bits (io_resp_f3_2_predicted_pc_bits_0),
.io_resp_f3_3_taken (io_resp_f3_3_taken_0),
.io_resp_f3_3_is_br (io_resp_f3_3_is_br_0),
.io_resp_f3_3_is_jal (io_resp_f3_3_is_jal_0),
.io_resp_f3_3_predicted_pc_valid (io_resp_f3_3_predicted_pc_valid_0),
.io_resp_f3_3_predicted_pc_bits (io_resp_f3_3_predicted_pc_bits_0),
.io_f3_meta (_loop_io_f3_meta),
.io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7]
.io_update_valid (io_update_valid_0), // @[composer.scala:14:7]
.io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7]
.io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7]
.io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7]
.io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7]
.io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7]
.io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7]
.io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7]
.io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7]
.io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7]
.io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7]
.io_update_bits_meta ({73'h0, io_update_bits_meta_0[119:73]}) // @[composer.scala:14:7, :42:27, :43:31]
); // @[config-mixins.scala:445:26]
TageBranchPredictorBank_2 tage ( // @[config-mixins.scala:446:26]
.clock (clock),
.reset (reset),
.io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7]
.io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7]
.io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7]
.io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7]
.io_resp_in_0_f1_0_taken (_btb_io_resp_f1_0_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_0_is_br (_btb_io_resp_f1_0_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_0_is_jal (_btb_io_resp_f1_0_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_0_predicted_pc_valid (_btb_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_0_predicted_pc_bits (_btb_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_1_taken (_btb_io_resp_f1_1_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_1_is_br (_btb_io_resp_f1_1_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_1_is_jal (_btb_io_resp_f1_1_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_1_predicted_pc_valid (_btb_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_1_predicted_pc_bits (_btb_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_2_taken (_btb_io_resp_f1_2_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_2_is_br (_btb_io_resp_f1_2_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_2_is_jal (_btb_io_resp_f1_2_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_2_predicted_pc_valid (_btb_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_2_predicted_pc_bits (_btb_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_3_taken (_btb_io_resp_f1_3_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_3_is_br (_btb_io_resp_f1_3_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_3_is_jal (_btb_io_resp_f1_3_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_3_predicted_pc_valid (_btb_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_3_predicted_pc_bits (_btb_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_0_taken (_btb_io_resp_f2_0_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_0_is_br (_btb_io_resp_f2_0_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_0_is_jal (_btb_io_resp_f2_0_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_0_predicted_pc_valid (_btb_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_0_predicted_pc_bits (_btb_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_1_taken (_btb_io_resp_f2_1_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_1_is_br (_btb_io_resp_f2_1_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_1_is_jal (_btb_io_resp_f2_1_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_1_predicted_pc_valid (_btb_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_1_predicted_pc_bits (_btb_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_2_taken (_btb_io_resp_f2_2_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_2_is_br (_btb_io_resp_f2_2_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_2_is_jal (_btb_io_resp_f2_2_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_2_predicted_pc_valid (_btb_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_2_predicted_pc_bits (_btb_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_3_taken (_btb_io_resp_f2_3_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_3_is_br (_btb_io_resp_f2_3_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_3_is_jal (_btb_io_resp_f2_3_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_3_predicted_pc_valid (_btb_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_3_predicted_pc_bits (_btb_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_0_taken (_btb_io_resp_f3_0_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_0_is_br (_btb_io_resp_f3_0_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_0_is_jal (_btb_io_resp_f3_0_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_0_predicted_pc_valid (_btb_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_0_predicted_pc_bits (_btb_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_1_taken (_btb_io_resp_f3_1_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_1_is_br (_btb_io_resp_f3_1_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_1_is_jal (_btb_io_resp_f3_1_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_1_predicted_pc_valid (_btb_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_1_predicted_pc_bits (_btb_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_2_taken (_btb_io_resp_f3_2_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_2_is_br (_btb_io_resp_f3_2_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_2_is_jal (_btb_io_resp_f3_2_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_2_predicted_pc_valid (_btb_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_2_predicted_pc_bits (_btb_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_3_taken (_btb_io_resp_f3_3_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_3_is_br (_btb_io_resp_f3_3_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_3_is_jal (_btb_io_resp_f3_3_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_3_predicted_pc_valid (_btb_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_3_predicted_pc_bits (_btb_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_f1_0_taken (_tage_io_resp_f1_0_taken),
.io_resp_f1_0_is_br (_tage_io_resp_f1_0_is_br),
.io_resp_f1_0_is_jal (_tage_io_resp_f1_0_is_jal),
.io_resp_f1_0_predicted_pc_valid (_tage_io_resp_f1_0_predicted_pc_valid),
.io_resp_f1_0_predicted_pc_bits (_tage_io_resp_f1_0_predicted_pc_bits),
.io_resp_f1_1_taken (_tage_io_resp_f1_1_taken),
.io_resp_f1_1_is_br (_tage_io_resp_f1_1_is_br),
.io_resp_f1_1_is_jal (_tage_io_resp_f1_1_is_jal),
.io_resp_f1_1_predicted_pc_valid (_tage_io_resp_f1_1_predicted_pc_valid),
.io_resp_f1_1_predicted_pc_bits (_tage_io_resp_f1_1_predicted_pc_bits),
.io_resp_f1_2_taken (_tage_io_resp_f1_2_taken),
.io_resp_f1_2_is_br (_tage_io_resp_f1_2_is_br),
.io_resp_f1_2_is_jal (_tage_io_resp_f1_2_is_jal),
.io_resp_f1_2_predicted_pc_valid (_tage_io_resp_f1_2_predicted_pc_valid),
.io_resp_f1_2_predicted_pc_bits (_tage_io_resp_f1_2_predicted_pc_bits),
.io_resp_f1_3_taken (_tage_io_resp_f1_3_taken),
.io_resp_f1_3_is_br (_tage_io_resp_f1_3_is_br),
.io_resp_f1_3_is_jal (_tage_io_resp_f1_3_is_jal),
.io_resp_f1_3_predicted_pc_valid (_tage_io_resp_f1_3_predicted_pc_valid),
.io_resp_f1_3_predicted_pc_bits (_tage_io_resp_f1_3_predicted_pc_bits),
.io_resp_f2_0_taken (_tage_io_resp_f2_0_taken),
.io_resp_f2_0_is_br (_tage_io_resp_f2_0_is_br),
.io_resp_f2_0_is_jal (_tage_io_resp_f2_0_is_jal),
.io_resp_f2_0_predicted_pc_valid (_tage_io_resp_f2_0_predicted_pc_valid),
.io_resp_f2_0_predicted_pc_bits (_tage_io_resp_f2_0_predicted_pc_bits),
.io_resp_f2_1_taken (_tage_io_resp_f2_1_taken),
.io_resp_f2_1_is_br (_tage_io_resp_f2_1_is_br),
.io_resp_f2_1_is_jal (_tage_io_resp_f2_1_is_jal),
.io_resp_f2_1_predicted_pc_valid (_tage_io_resp_f2_1_predicted_pc_valid),
.io_resp_f2_1_predicted_pc_bits (_tage_io_resp_f2_1_predicted_pc_bits),
.io_resp_f2_2_taken (_tage_io_resp_f2_2_taken),
.io_resp_f2_2_is_br (_tage_io_resp_f2_2_is_br),
.io_resp_f2_2_is_jal (_tage_io_resp_f2_2_is_jal),
.io_resp_f2_2_predicted_pc_valid (_tage_io_resp_f2_2_predicted_pc_valid),
.io_resp_f2_2_predicted_pc_bits (_tage_io_resp_f2_2_predicted_pc_bits),
.io_resp_f2_3_taken (_tage_io_resp_f2_3_taken),
.io_resp_f2_3_is_br (_tage_io_resp_f2_3_is_br),
.io_resp_f2_3_is_jal (_tage_io_resp_f2_3_is_jal),
.io_resp_f2_3_predicted_pc_valid (_tage_io_resp_f2_3_predicted_pc_valid),
.io_resp_f2_3_predicted_pc_bits (_tage_io_resp_f2_3_predicted_pc_bits),
.io_resp_f3_0_taken (_tage_io_resp_f3_0_taken),
.io_resp_f3_0_is_br (_tage_io_resp_f3_0_is_br),
.io_resp_f3_0_is_jal (_tage_io_resp_f3_0_is_jal),
.io_resp_f3_0_predicted_pc_valid (_tage_io_resp_f3_0_predicted_pc_valid),
.io_resp_f3_0_predicted_pc_bits (_tage_io_resp_f3_0_predicted_pc_bits),
.io_resp_f3_1_taken (_tage_io_resp_f3_1_taken),
.io_resp_f3_1_is_br (_tage_io_resp_f3_1_is_br),
.io_resp_f3_1_is_jal (_tage_io_resp_f3_1_is_jal),
.io_resp_f3_1_predicted_pc_valid (_tage_io_resp_f3_1_predicted_pc_valid),
.io_resp_f3_1_predicted_pc_bits (_tage_io_resp_f3_1_predicted_pc_bits),
.io_resp_f3_2_taken (_tage_io_resp_f3_2_taken),
.io_resp_f3_2_is_br (_tage_io_resp_f3_2_is_br),
.io_resp_f3_2_is_jal (_tage_io_resp_f3_2_is_jal),
.io_resp_f3_2_predicted_pc_valid (_tage_io_resp_f3_2_predicted_pc_valid),
.io_resp_f3_2_predicted_pc_bits (_tage_io_resp_f3_2_predicted_pc_bits),
.io_resp_f3_3_taken (_tage_io_resp_f3_3_taken),
.io_resp_f3_3_is_br (_tage_io_resp_f3_3_is_br),
.io_resp_f3_3_is_jal (_tage_io_resp_f3_3_is_jal),
.io_resp_f3_3_predicted_pc_valid (_tage_io_resp_f3_3_predicted_pc_valid),
.io_resp_f3_3_predicted_pc_bits (_tage_io_resp_f3_3_predicted_pc_bits),
.io_f3_meta (_tage_io_f3_meta),
.io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7]
.io_update_valid (io_update_valid_0), // @[composer.scala:14:7]
.io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7]
.io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7]
.io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7]
.io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7]
.io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7]
.io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7]
.io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7]
.io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7]
.io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7]
.io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7]
.io_update_bits_meta ({17'h0, io_update_bits_meta_0[119:17]}) // @[composer.scala:14:7, :42:27, :43:31]
); // @[config-mixins.scala:446:26]
BTBBranchPredictorBank_2 btb ( // @[config-mixins.scala:447:25]
.clock (clock),
.reset (reset),
.io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7]
.io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7]
.io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7]
.io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7]
.io_resp_in_0_f1_0_taken (_bim_io_resp_f1_0_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_0_is_br (_bim_io_resp_f1_0_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_0_is_jal (_bim_io_resp_f1_0_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_0_predicted_pc_valid (_bim_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_0_predicted_pc_bits (_bim_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_1_taken (_bim_io_resp_f1_1_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_1_is_br (_bim_io_resp_f1_1_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_1_is_jal (_bim_io_resp_f1_1_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_1_predicted_pc_valid (_bim_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_1_predicted_pc_bits (_bim_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_2_taken (_bim_io_resp_f1_2_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_2_is_br (_bim_io_resp_f1_2_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_2_is_jal (_bim_io_resp_f1_2_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_2_predicted_pc_valid (_bim_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_2_predicted_pc_bits (_bim_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_3_taken (_bim_io_resp_f1_3_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_3_is_br (_bim_io_resp_f1_3_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_3_is_jal (_bim_io_resp_f1_3_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_3_predicted_pc_valid (_bim_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_3_predicted_pc_bits (_bim_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_0_taken (_bim_io_resp_f2_0_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_0_is_br (_bim_io_resp_f2_0_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_0_is_jal (_bim_io_resp_f2_0_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_0_predicted_pc_valid (_bim_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_0_predicted_pc_bits (_bim_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_1_taken (_bim_io_resp_f2_1_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_1_is_br (_bim_io_resp_f2_1_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_1_is_jal (_bim_io_resp_f2_1_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_1_predicted_pc_valid (_bim_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_1_predicted_pc_bits (_bim_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_2_taken (_bim_io_resp_f2_2_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_2_is_br (_bim_io_resp_f2_2_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_2_is_jal (_bim_io_resp_f2_2_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_2_predicted_pc_valid (_bim_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_2_predicted_pc_bits (_bim_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_3_taken (_bim_io_resp_f2_3_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_3_is_br (_bim_io_resp_f2_3_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_3_is_jal (_bim_io_resp_f2_3_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_3_predicted_pc_valid (_bim_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_3_predicted_pc_bits (_bim_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_0_taken (_bim_io_resp_f3_0_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_0_is_br (_bim_io_resp_f3_0_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_0_is_jal (_bim_io_resp_f3_0_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_0_predicted_pc_valid (_bim_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_0_predicted_pc_bits (_bim_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_1_taken (_bim_io_resp_f3_1_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_1_is_br (_bim_io_resp_f3_1_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_1_is_jal (_bim_io_resp_f3_1_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_1_predicted_pc_valid (_bim_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_1_predicted_pc_bits (_bim_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_2_taken (_bim_io_resp_f3_2_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_2_is_br (_bim_io_resp_f3_2_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_2_is_jal (_bim_io_resp_f3_2_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_2_predicted_pc_valid (_bim_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_2_predicted_pc_bits (_bim_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_3_taken (_bim_io_resp_f3_3_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_3_is_br (_bim_io_resp_f3_3_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_3_is_jal (_bim_io_resp_f3_3_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_3_predicted_pc_valid (_bim_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_3_predicted_pc_bits (_bim_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_f1_0_taken (_btb_io_resp_f1_0_taken),
.io_resp_f1_0_is_br (_btb_io_resp_f1_0_is_br),
.io_resp_f1_0_is_jal (_btb_io_resp_f1_0_is_jal),
.io_resp_f1_0_predicted_pc_valid (_btb_io_resp_f1_0_predicted_pc_valid),
.io_resp_f1_0_predicted_pc_bits (_btb_io_resp_f1_0_predicted_pc_bits),
.io_resp_f1_1_taken (_btb_io_resp_f1_1_taken),
.io_resp_f1_1_is_br (_btb_io_resp_f1_1_is_br),
.io_resp_f1_1_is_jal (_btb_io_resp_f1_1_is_jal),
.io_resp_f1_1_predicted_pc_valid (_btb_io_resp_f1_1_predicted_pc_valid),
.io_resp_f1_1_predicted_pc_bits (_btb_io_resp_f1_1_predicted_pc_bits),
.io_resp_f1_2_taken (_btb_io_resp_f1_2_taken),
.io_resp_f1_2_is_br (_btb_io_resp_f1_2_is_br),
.io_resp_f1_2_is_jal (_btb_io_resp_f1_2_is_jal),
.io_resp_f1_2_predicted_pc_valid (_btb_io_resp_f1_2_predicted_pc_valid),
.io_resp_f1_2_predicted_pc_bits (_btb_io_resp_f1_2_predicted_pc_bits),
.io_resp_f1_3_taken (_btb_io_resp_f1_3_taken),
.io_resp_f1_3_is_br (_btb_io_resp_f1_3_is_br),
.io_resp_f1_3_is_jal (_btb_io_resp_f1_3_is_jal),
.io_resp_f1_3_predicted_pc_valid (_btb_io_resp_f1_3_predicted_pc_valid),
.io_resp_f1_3_predicted_pc_bits (_btb_io_resp_f1_3_predicted_pc_bits),
.io_resp_f2_0_taken (_btb_io_resp_f2_0_taken),
.io_resp_f2_0_is_br (_btb_io_resp_f2_0_is_br),
.io_resp_f2_0_is_jal (_btb_io_resp_f2_0_is_jal),
.io_resp_f2_0_predicted_pc_valid (_btb_io_resp_f2_0_predicted_pc_valid),
.io_resp_f2_0_predicted_pc_bits (_btb_io_resp_f2_0_predicted_pc_bits),
.io_resp_f2_1_taken (_btb_io_resp_f2_1_taken),
.io_resp_f2_1_is_br (_btb_io_resp_f2_1_is_br),
.io_resp_f2_1_is_jal (_btb_io_resp_f2_1_is_jal),
.io_resp_f2_1_predicted_pc_valid (_btb_io_resp_f2_1_predicted_pc_valid),
.io_resp_f2_1_predicted_pc_bits (_btb_io_resp_f2_1_predicted_pc_bits),
.io_resp_f2_2_taken (_btb_io_resp_f2_2_taken),
.io_resp_f2_2_is_br (_btb_io_resp_f2_2_is_br),
.io_resp_f2_2_is_jal (_btb_io_resp_f2_2_is_jal),
.io_resp_f2_2_predicted_pc_valid (_btb_io_resp_f2_2_predicted_pc_valid),
.io_resp_f2_2_predicted_pc_bits (_btb_io_resp_f2_2_predicted_pc_bits),
.io_resp_f2_3_taken (_btb_io_resp_f2_3_taken),
.io_resp_f2_3_is_br (_btb_io_resp_f2_3_is_br),
.io_resp_f2_3_is_jal (_btb_io_resp_f2_3_is_jal),
.io_resp_f2_3_predicted_pc_valid (_btb_io_resp_f2_3_predicted_pc_valid),
.io_resp_f2_3_predicted_pc_bits (_btb_io_resp_f2_3_predicted_pc_bits),
.io_resp_f3_0_taken (_btb_io_resp_f3_0_taken),
.io_resp_f3_0_is_br (_btb_io_resp_f3_0_is_br),
.io_resp_f3_0_is_jal (_btb_io_resp_f3_0_is_jal),
.io_resp_f3_0_predicted_pc_valid (_btb_io_resp_f3_0_predicted_pc_valid),
.io_resp_f3_0_predicted_pc_bits (_btb_io_resp_f3_0_predicted_pc_bits),
.io_resp_f3_1_taken (_btb_io_resp_f3_1_taken),
.io_resp_f3_1_is_br (_btb_io_resp_f3_1_is_br),
.io_resp_f3_1_is_jal (_btb_io_resp_f3_1_is_jal),
.io_resp_f3_1_predicted_pc_valid (_btb_io_resp_f3_1_predicted_pc_valid),
.io_resp_f3_1_predicted_pc_bits (_btb_io_resp_f3_1_predicted_pc_bits),
.io_resp_f3_2_taken (_btb_io_resp_f3_2_taken),
.io_resp_f3_2_is_br (_btb_io_resp_f3_2_is_br),
.io_resp_f3_2_is_jal (_btb_io_resp_f3_2_is_jal),
.io_resp_f3_2_predicted_pc_valid (_btb_io_resp_f3_2_predicted_pc_valid),
.io_resp_f3_2_predicted_pc_bits (_btb_io_resp_f3_2_predicted_pc_bits),
.io_resp_f3_3_taken (_btb_io_resp_f3_3_taken),
.io_resp_f3_3_is_br (_btb_io_resp_f3_3_is_br),
.io_resp_f3_3_is_jal (_btb_io_resp_f3_3_is_jal),
.io_resp_f3_3_predicted_pc_valid (_btb_io_resp_f3_3_predicted_pc_valid),
.io_resp_f3_3_predicted_pc_bits (_btb_io_resp_f3_3_predicted_pc_bits),
.io_f3_meta (_btb_io_f3_meta),
.io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7]
.io_update_valid (io_update_valid_0), // @[composer.scala:14:7]
.io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7]
.io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7]
.io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7]
.io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7]
.io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7]
.io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7]
.io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7]
.io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7]
.io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7]
.io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7]
.io_update_bits_meta ({16'h0, io_update_bits_meta_0[119:16]}) // @[composer.scala:14:7, :42:27, :43:31]
); // @[config-mixins.scala:447:25]
BIMBranchPredictorBank_2 bim ( // @[config-mixins.scala:448:25]
.clock (clock),
.reset (reset),
.io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7]
.io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7]
.io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7]
.io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7]
.io_resp_in_0_f1_0_taken (_ubtb_io_resp_f1_0_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_0_is_br (_ubtb_io_resp_f1_0_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_0_is_jal (_ubtb_io_resp_f1_0_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_0_predicted_pc_valid (_ubtb_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_0_predicted_pc_bits (_ubtb_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_1_taken (_ubtb_io_resp_f1_1_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_1_is_br (_ubtb_io_resp_f1_1_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_1_is_jal (_ubtb_io_resp_f1_1_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_1_predicted_pc_valid (_ubtb_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_1_predicted_pc_bits (_ubtb_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_2_taken (_ubtb_io_resp_f1_2_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_2_is_br (_ubtb_io_resp_f1_2_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_2_is_jal (_ubtb_io_resp_f1_2_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_2_predicted_pc_valid (_ubtb_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_2_predicted_pc_bits (_ubtb_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_3_taken (_ubtb_io_resp_f1_3_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_3_is_br (_ubtb_io_resp_f1_3_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_3_is_jal (_ubtb_io_resp_f1_3_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_3_predicted_pc_valid (_ubtb_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_3_predicted_pc_bits (_ubtb_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_0_taken (_ubtb_io_resp_f2_0_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_0_is_br (_ubtb_io_resp_f2_0_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_0_is_jal (_ubtb_io_resp_f2_0_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_0_predicted_pc_valid (_ubtb_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_0_predicted_pc_bits (_ubtb_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_1_taken (_ubtb_io_resp_f2_1_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_1_is_br (_ubtb_io_resp_f2_1_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_1_is_jal (_ubtb_io_resp_f2_1_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_1_predicted_pc_valid (_ubtb_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_1_predicted_pc_bits (_ubtb_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_2_taken (_ubtb_io_resp_f2_2_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_2_is_br (_ubtb_io_resp_f2_2_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_2_is_jal (_ubtb_io_resp_f2_2_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_2_predicted_pc_valid (_ubtb_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_2_predicted_pc_bits (_ubtb_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_3_taken (_ubtb_io_resp_f2_3_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_3_is_br (_ubtb_io_resp_f2_3_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_3_is_jal (_ubtb_io_resp_f2_3_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_3_predicted_pc_valid (_ubtb_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_3_predicted_pc_bits (_ubtb_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_0_taken (_ubtb_io_resp_f3_0_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_0_is_br (_ubtb_io_resp_f3_0_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_0_is_jal (_ubtb_io_resp_f3_0_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_0_predicted_pc_valid (_ubtb_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_0_predicted_pc_bits (_ubtb_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_1_taken (_ubtb_io_resp_f3_1_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_1_is_br (_ubtb_io_resp_f3_1_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_1_is_jal (_ubtb_io_resp_f3_1_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_1_predicted_pc_valid (_ubtb_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_1_predicted_pc_bits (_ubtb_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_2_taken (_ubtb_io_resp_f3_2_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_2_is_br (_ubtb_io_resp_f3_2_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_2_is_jal (_ubtb_io_resp_f3_2_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_2_predicted_pc_valid (_ubtb_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_2_predicted_pc_bits (_ubtb_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_3_taken (_ubtb_io_resp_f3_3_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_3_is_br (_ubtb_io_resp_f3_3_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_3_is_jal (_ubtb_io_resp_f3_3_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_3_predicted_pc_valid (_ubtb_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_3_predicted_pc_bits (_ubtb_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_f1_0_taken (_bim_io_resp_f1_0_taken),
.io_resp_f1_0_is_br (_bim_io_resp_f1_0_is_br),
.io_resp_f1_0_is_jal (_bim_io_resp_f1_0_is_jal),
.io_resp_f1_0_predicted_pc_valid (_bim_io_resp_f1_0_predicted_pc_valid),
.io_resp_f1_0_predicted_pc_bits (_bim_io_resp_f1_0_predicted_pc_bits),
.io_resp_f1_1_taken (_bim_io_resp_f1_1_taken),
.io_resp_f1_1_is_br (_bim_io_resp_f1_1_is_br),
.io_resp_f1_1_is_jal (_bim_io_resp_f1_1_is_jal),
.io_resp_f1_1_predicted_pc_valid (_bim_io_resp_f1_1_predicted_pc_valid),
.io_resp_f1_1_predicted_pc_bits (_bim_io_resp_f1_1_predicted_pc_bits),
.io_resp_f1_2_taken (_bim_io_resp_f1_2_taken),
.io_resp_f1_2_is_br (_bim_io_resp_f1_2_is_br),
.io_resp_f1_2_is_jal (_bim_io_resp_f1_2_is_jal),
.io_resp_f1_2_predicted_pc_valid (_bim_io_resp_f1_2_predicted_pc_valid),
.io_resp_f1_2_predicted_pc_bits (_bim_io_resp_f1_2_predicted_pc_bits),
.io_resp_f1_3_taken (_bim_io_resp_f1_3_taken),
.io_resp_f1_3_is_br (_bim_io_resp_f1_3_is_br),
.io_resp_f1_3_is_jal (_bim_io_resp_f1_3_is_jal),
.io_resp_f1_3_predicted_pc_valid (_bim_io_resp_f1_3_predicted_pc_valid),
.io_resp_f1_3_predicted_pc_bits (_bim_io_resp_f1_3_predicted_pc_bits),
.io_resp_f2_0_taken (_bim_io_resp_f2_0_taken),
.io_resp_f2_0_is_br (_bim_io_resp_f2_0_is_br),
.io_resp_f2_0_is_jal (_bim_io_resp_f2_0_is_jal),
.io_resp_f2_0_predicted_pc_valid (_bim_io_resp_f2_0_predicted_pc_valid),
.io_resp_f2_0_predicted_pc_bits (_bim_io_resp_f2_0_predicted_pc_bits),
.io_resp_f2_1_taken (_bim_io_resp_f2_1_taken),
.io_resp_f2_1_is_br (_bim_io_resp_f2_1_is_br),
.io_resp_f2_1_is_jal (_bim_io_resp_f2_1_is_jal),
.io_resp_f2_1_predicted_pc_valid (_bim_io_resp_f2_1_predicted_pc_valid),
.io_resp_f2_1_predicted_pc_bits (_bim_io_resp_f2_1_predicted_pc_bits),
.io_resp_f2_2_taken (_bim_io_resp_f2_2_taken),
.io_resp_f2_2_is_br (_bim_io_resp_f2_2_is_br),
.io_resp_f2_2_is_jal (_bim_io_resp_f2_2_is_jal),
.io_resp_f2_2_predicted_pc_valid (_bim_io_resp_f2_2_predicted_pc_valid),
.io_resp_f2_2_predicted_pc_bits (_bim_io_resp_f2_2_predicted_pc_bits),
.io_resp_f2_3_taken (_bim_io_resp_f2_3_taken),
.io_resp_f2_3_is_br (_bim_io_resp_f2_3_is_br),
.io_resp_f2_3_is_jal (_bim_io_resp_f2_3_is_jal),
.io_resp_f2_3_predicted_pc_valid (_bim_io_resp_f2_3_predicted_pc_valid),
.io_resp_f2_3_predicted_pc_bits (_bim_io_resp_f2_3_predicted_pc_bits),
.io_resp_f3_0_taken (_bim_io_resp_f3_0_taken),
.io_resp_f3_0_is_br (_bim_io_resp_f3_0_is_br),
.io_resp_f3_0_is_jal (_bim_io_resp_f3_0_is_jal),
.io_resp_f3_0_predicted_pc_valid (_bim_io_resp_f3_0_predicted_pc_valid),
.io_resp_f3_0_predicted_pc_bits (_bim_io_resp_f3_0_predicted_pc_bits),
.io_resp_f3_1_taken (_bim_io_resp_f3_1_taken),
.io_resp_f3_1_is_br (_bim_io_resp_f3_1_is_br),
.io_resp_f3_1_is_jal (_bim_io_resp_f3_1_is_jal),
.io_resp_f3_1_predicted_pc_valid (_bim_io_resp_f3_1_predicted_pc_valid),
.io_resp_f3_1_predicted_pc_bits (_bim_io_resp_f3_1_predicted_pc_bits),
.io_resp_f3_2_taken (_bim_io_resp_f3_2_taken),
.io_resp_f3_2_is_br (_bim_io_resp_f3_2_is_br),
.io_resp_f3_2_is_jal (_bim_io_resp_f3_2_is_jal),
.io_resp_f3_2_predicted_pc_valid (_bim_io_resp_f3_2_predicted_pc_valid),
.io_resp_f3_2_predicted_pc_bits (_bim_io_resp_f3_2_predicted_pc_bits),
.io_resp_f3_3_taken (_bim_io_resp_f3_3_taken),
.io_resp_f3_3_is_br (_bim_io_resp_f3_3_is_br),
.io_resp_f3_3_is_jal (_bim_io_resp_f3_3_is_jal),
.io_resp_f3_3_predicted_pc_valid (_bim_io_resp_f3_3_predicted_pc_valid),
.io_resp_f3_3_predicted_pc_bits (_bim_io_resp_f3_3_predicted_pc_bits),
.io_f3_meta (_bim_io_f3_meta),
.io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7]
.io_update_valid (io_update_valid_0), // @[composer.scala:14:7]
.io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7]
.io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7]
.io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7]
.io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7]
.io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7]
.io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7]
.io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7]
.io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7]
.io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7]
.io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7]
.io_update_bits_meta (io_update_bits_meta_0) // @[composer.scala:14:7]
); // @[config-mixins.scala:448:25]
FAMicroBTBBranchPredictorBank_2 ubtb ( // @[config-mixins.scala:449:26]
.clock (clock),
.reset (reset),
.io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7]
.io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7]
.io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7]
.io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7]
.io_resp_f1_0_taken (_ubtb_io_resp_f1_0_taken),
.io_resp_f1_0_is_br (_ubtb_io_resp_f1_0_is_br),
.io_resp_f1_0_is_jal (_ubtb_io_resp_f1_0_is_jal),
.io_resp_f1_0_predicted_pc_valid (_ubtb_io_resp_f1_0_predicted_pc_valid),
.io_resp_f1_0_predicted_pc_bits (_ubtb_io_resp_f1_0_predicted_pc_bits),
.io_resp_f1_1_taken (_ubtb_io_resp_f1_1_taken),
.io_resp_f1_1_is_br (_ubtb_io_resp_f1_1_is_br),
.io_resp_f1_1_is_jal (_ubtb_io_resp_f1_1_is_jal),
.io_resp_f1_1_predicted_pc_valid (_ubtb_io_resp_f1_1_predicted_pc_valid),
.io_resp_f1_1_predicted_pc_bits (_ubtb_io_resp_f1_1_predicted_pc_bits),
.io_resp_f1_2_taken (_ubtb_io_resp_f1_2_taken),
.io_resp_f1_2_is_br (_ubtb_io_resp_f1_2_is_br),
.io_resp_f1_2_is_jal (_ubtb_io_resp_f1_2_is_jal),
.io_resp_f1_2_predicted_pc_valid (_ubtb_io_resp_f1_2_predicted_pc_valid),
.io_resp_f1_2_predicted_pc_bits (_ubtb_io_resp_f1_2_predicted_pc_bits),
.io_resp_f1_3_taken (_ubtb_io_resp_f1_3_taken),
.io_resp_f1_3_is_br (_ubtb_io_resp_f1_3_is_br),
.io_resp_f1_3_is_jal (_ubtb_io_resp_f1_3_is_jal),
.io_resp_f1_3_predicted_pc_valid (_ubtb_io_resp_f1_3_predicted_pc_valid),
.io_resp_f1_3_predicted_pc_bits (_ubtb_io_resp_f1_3_predicted_pc_bits),
.io_resp_f2_0_taken (_ubtb_io_resp_f2_0_taken),
.io_resp_f2_0_is_br (_ubtb_io_resp_f2_0_is_br),
.io_resp_f2_0_is_jal (_ubtb_io_resp_f2_0_is_jal),
.io_resp_f2_0_predicted_pc_valid (_ubtb_io_resp_f2_0_predicted_pc_valid),
.io_resp_f2_0_predicted_pc_bits (_ubtb_io_resp_f2_0_predicted_pc_bits),
.io_resp_f2_1_taken (_ubtb_io_resp_f2_1_taken),
.io_resp_f2_1_is_br (_ubtb_io_resp_f2_1_is_br),
.io_resp_f2_1_is_jal (_ubtb_io_resp_f2_1_is_jal),
.io_resp_f2_1_predicted_pc_valid (_ubtb_io_resp_f2_1_predicted_pc_valid),
.io_resp_f2_1_predicted_pc_bits (_ubtb_io_resp_f2_1_predicted_pc_bits),
.io_resp_f2_2_taken (_ubtb_io_resp_f2_2_taken),
.io_resp_f2_2_is_br (_ubtb_io_resp_f2_2_is_br),
.io_resp_f2_2_is_jal (_ubtb_io_resp_f2_2_is_jal),
.io_resp_f2_2_predicted_pc_valid (_ubtb_io_resp_f2_2_predicted_pc_valid),
.io_resp_f2_2_predicted_pc_bits (_ubtb_io_resp_f2_2_predicted_pc_bits),
.io_resp_f2_3_taken (_ubtb_io_resp_f2_3_taken),
.io_resp_f2_3_is_br (_ubtb_io_resp_f2_3_is_br),
.io_resp_f2_3_is_jal (_ubtb_io_resp_f2_3_is_jal),
.io_resp_f2_3_predicted_pc_valid (_ubtb_io_resp_f2_3_predicted_pc_valid),
.io_resp_f2_3_predicted_pc_bits (_ubtb_io_resp_f2_3_predicted_pc_bits),
.io_resp_f3_0_taken (_ubtb_io_resp_f3_0_taken),
.io_resp_f3_0_is_br (_ubtb_io_resp_f3_0_is_br),
.io_resp_f3_0_is_jal (_ubtb_io_resp_f3_0_is_jal),
.io_resp_f3_0_predicted_pc_valid (_ubtb_io_resp_f3_0_predicted_pc_valid),
.io_resp_f3_0_predicted_pc_bits (_ubtb_io_resp_f3_0_predicted_pc_bits),
.io_resp_f3_1_taken (_ubtb_io_resp_f3_1_taken),
.io_resp_f3_1_is_br (_ubtb_io_resp_f3_1_is_br),
.io_resp_f3_1_is_jal (_ubtb_io_resp_f3_1_is_jal),
.io_resp_f3_1_predicted_pc_valid (_ubtb_io_resp_f3_1_predicted_pc_valid),
.io_resp_f3_1_predicted_pc_bits (_ubtb_io_resp_f3_1_predicted_pc_bits),
.io_resp_f3_2_taken (_ubtb_io_resp_f3_2_taken),
.io_resp_f3_2_is_br (_ubtb_io_resp_f3_2_is_br),
.io_resp_f3_2_is_jal (_ubtb_io_resp_f3_2_is_jal),
.io_resp_f3_2_predicted_pc_valid (_ubtb_io_resp_f3_2_predicted_pc_valid),
.io_resp_f3_2_predicted_pc_bits (_ubtb_io_resp_f3_2_predicted_pc_bits),
.io_resp_f3_3_taken (_ubtb_io_resp_f3_3_taken),
.io_resp_f3_3_is_br (_ubtb_io_resp_f3_3_is_br),
.io_resp_f3_3_is_jal (_ubtb_io_resp_f3_3_is_jal),
.io_resp_f3_3_predicted_pc_valid (_ubtb_io_resp_f3_3_predicted_pc_valid),
.io_resp_f3_3_predicted_pc_bits (_ubtb_io_resp_f3_3_predicted_pc_bits),
.io_f3_meta (_ubtb_io_f3_meta),
.io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7]
.io_update_valid (io_update_valid_0), // @[composer.scala:14:7]
.io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7]
.io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7]
.io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7]
.io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7]
.io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7]
.io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7]
.io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7]
.io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7]
.io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7]
.io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7]
.io_update_bits_meta ({8'h0, io_update_bits_meta_0[119:8]}) // @[composer.scala:14:7, :31:22, :42:27, :43:31]
); // @[config-mixins.scala:449:26]
assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[composer.scala:14:7]
assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[composer.scala:14:7]
assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[composer.scala:14:7]
assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[composer.scala:14:7]
assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[composer.scala:14:7]
assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[composer.scala:14:7]
assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[composer.scala:14:7]
assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[composer.scala:14:7]
assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[composer.scala:14:7]
assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[composer.scala:14:7]
assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[composer.scala:14:7]
assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[composer.scala:14:7]
assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[composer.scala:14:7]
assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[composer.scala:14:7]
assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[composer.scala:14:7]
assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[composer.scala:14:7]
assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[composer.scala:14:7]
assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[composer.scala:14:7]
assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[composer.scala:14:7]
assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[composer.scala:14:7]
assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[composer.scala:14:7]
assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[composer.scala:14:7]
assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[composer.scala:14:7]
assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[composer.scala:14:7]
assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_f3_meta = io_f3_meta_0; // @[composer.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PhitToFlit_p32_f32_7 :
input clock : Clock
input reset : Reset
output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}}
reg data : UInt<32>[0], clock
regreset beat : UInt<0>, clock, reset, UInt<0>(0h0)
node _io_in_ready_T = neq(beat, UInt<1>(0h0))
node _io_in_ready_T_1 = or(io.out.ready, _io_in_ready_T)
connect io.in.ready, _io_in_ready_T_1
node _io_out_valid_T = eq(beat, UInt<1>(0h0))
node _io_out_valid_T_1 = and(io.in.valid, _io_out_valid_T)
connect io.out.valid, _io_out_valid_T_1
connect io.out.bits.flit, io.in.bits.phit
node _T = and(io.in.ready, io.in.valid)
when _T :
node _beat_T = eq(beat, UInt<1>(0h0))
node _beat_T_1 = add(beat, UInt<1>(0h1))
node _beat_T_2 = tail(_beat_T_1, 1)
node _beat_T_3 = mux(_beat_T, UInt<1>(0h0), _beat_T_2)
connect beat, _beat_T_3 | module PhitToFlit_p32_f32_7( // @[Serdes.scala:103:7]
input clock, // @[Serdes.scala:103:7]
input reset, // @[Serdes.scala:103:7]
output io_in_ready, // @[Serdes.scala:105:14]
input io_in_valid, // @[Serdes.scala:105:14]
input [31:0] io_in_bits_phit, // @[Serdes.scala:105:14]
input io_out_ready, // @[Serdes.scala:105:14]
output io_out_valid, // @[Serdes.scala:105:14]
output [31:0] io_out_bits_flit // @[Serdes.scala:105:14]
);
wire io_in_valid_0 = io_in_valid; // @[Serdes.scala:103:7]
wire [31:0] io_in_bits_phit_0 = io_in_bits_phit; // @[Serdes.scala:103:7]
wire io_out_ready_0 = io_out_ready; // @[Serdes.scala:103:7]
wire [1:0] _beat_T_1 = 2'h1; // @[Serdes.scala:120:53]
wire _io_out_valid_T = 1'h1; // @[Serdes.scala:116:39]
wire _beat_T = 1'h1; // @[Serdes.scala:120:22]
wire _beat_T_2 = 1'h1; // @[Serdes.scala:120:53]
wire _io_in_ready_T = 1'h0; // @[Serdes.scala:115:39]
wire _io_in_ready_T_1; // @[Serdes.scala:115:31]
wire _beat_T_3 = 1'h0; // @[Serdes.scala:120:16]
wire _io_out_valid_T_1 = io_in_valid_0; // @[Serdes.scala:103:7, :116:31]
wire [31:0] io_out_bits_flit_0 = io_in_bits_phit_0; // @[Serdes.scala:103:7]
assign _io_in_ready_T_1 = io_out_ready_0; // @[Serdes.scala:103:7, :115:31]
wire io_in_ready_0; // @[Serdes.scala:103:7]
wire io_out_valid_0; // @[Serdes.scala:103:7]
assign io_in_ready_0 = _io_in_ready_T_1; // @[Serdes.scala:103:7, :115:31]
assign io_out_valid_0 = _io_out_valid_T_1; // @[Serdes.scala:103:7, :116:31]
assign io_in_ready = io_in_ready_0; // @[Serdes.scala:103:7]
assign io_out_valid = io_out_valid_0; // @[Serdes.scala:103:7]
assign io_out_bits_flit = io_out_bits_flit_0; // @[Serdes.scala:103:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module DirectFFT :
input clock : Clock
input reset : Reset
output io : { flip in : { valid : UInt<1>, bits : { real : SInt<16>, imag : SInt<16>}[8], sync : UInt<1>}, out : { valid : UInt<1>, bits : { real : SInt<16>, imag : SInt<16>}[8], sync : UInt<1>}}
reg valid_delay : UInt<1>, clock
connect valid_delay, io.in.valid
node _sync_T = not(valid_delay)
node _sync_T_1 = and(_sync_T, io.in.valid)
wire sync_c_1 : UInt
connect sync_c_1, UInt<1>(0h0)
wire sync_c_2 : UInt<1>
connect sync_c_2, UInt<1>(0h0)
when UInt<1>(0h1) :
connect sync_c_2, UInt<1>(0h1)
wire sync : UInt
connect sync, sync_c_1
node _io_out_sync_T = eq(sync, UInt<1>(0h0))
node _io_out_sync_T_1 = and(io.in.valid, _io_out_sync_T)
connect io.out.sync, _io_out_sync_T_1
connect io.out.valid, io.in.valid
wire twiddle_rom_real : SInt<19>
wire twiddle_rom_imag : SInt<19>
wire _twiddle_rom_real_new : SInt<19>
wire _twiddle_rom_real_new_WIRE : SInt<19>
connect _twiddle_rom_real_new_WIRE, asSInt(UInt<19>(0h20000))
connect _twiddle_rom_real_new, _twiddle_rom_real_new_WIRE
connect twiddle_rom_real, _twiddle_rom_real_new
wire _twiddle_rom_imag_new : SInt<1>
wire _twiddle_rom_imag_new_WIRE : SInt<1>
connect _twiddle_rom_imag_new_WIRE, asSInt(UInt<1>(0h0))
connect _twiddle_rom_imag_new, _twiddle_rom_imag_new_WIRE
connect twiddle_rom_imag, _twiddle_rom_imag_new
wire twiddle_rom_twiddle : { real : SInt<19>, imag : SInt<19>}
wire _twiddle_rom_twiddle_real_new : SInt<19>
wire _twiddle_rom_twiddle_real_new_WIRE : SInt<19>
node _twiddle_rom_twiddle_real_new_T = asUInt(twiddle_rom_real)
node _twiddle_rom_twiddle_real_new_T_1 = asSInt(_twiddle_rom_twiddle_real_new_T)
connect _twiddle_rom_twiddle_real_new_WIRE, _twiddle_rom_twiddle_real_new_T_1
connect _twiddle_rom_twiddle_real_new, _twiddle_rom_twiddle_real_new_WIRE
connect twiddle_rom_twiddle.real, _twiddle_rom_twiddle_real_new
wire _twiddle_rom_twiddle_imag_new : SInt<19>
wire _twiddle_rom_twiddle_imag_new_WIRE : SInt<19>
node _twiddle_rom_twiddle_imag_new_T = asUInt(twiddle_rom_imag)
node _twiddle_rom_twiddle_imag_new_T_1 = asSInt(_twiddle_rom_twiddle_imag_new_T)
connect _twiddle_rom_twiddle_imag_new_WIRE, _twiddle_rom_twiddle_imag_new_T_1
connect _twiddle_rom_twiddle_imag_new, _twiddle_rom_twiddle_imag_new_WIRE
connect twiddle_rom_twiddle.imag, _twiddle_rom_twiddle_imag_new
wire twiddle_rom_real_1 : SInt<19>
wire twiddle_rom_imag_1 : SInt<19>
wire _twiddle_rom_real_new_1 : SInt<18>
wire _twiddle_rom_real_new_WIRE_1 : SInt<18>
connect _twiddle_rom_real_new_WIRE_1, asSInt(UInt<18>(0h16a0a))
connect _twiddle_rom_real_new_1, _twiddle_rom_real_new_WIRE_1
connect twiddle_rom_real_1, _twiddle_rom_real_new_1
wire _twiddle_rom_imag_new_1 : SInt<18>
wire _twiddle_rom_imag_new_WIRE_1 : SInt<18>
connect _twiddle_rom_imag_new_WIRE_1, asSInt(UInt<18>(0h295f6))
connect _twiddle_rom_imag_new_1, _twiddle_rom_imag_new_WIRE_1
connect twiddle_rom_imag_1, _twiddle_rom_imag_new_1
wire twiddle_rom_twiddle_1 : { real : SInt<19>, imag : SInt<19>}
wire _twiddle_rom_twiddle_real_new_1 : SInt<19>
wire _twiddle_rom_twiddle_real_new_WIRE_1 : SInt<19>
node _twiddle_rom_twiddle_real_new_T_2 = asUInt(twiddle_rom_real_1)
node _twiddle_rom_twiddle_real_new_T_3 = asSInt(_twiddle_rom_twiddle_real_new_T_2)
connect _twiddle_rom_twiddle_real_new_WIRE_1, _twiddle_rom_twiddle_real_new_T_3
connect _twiddle_rom_twiddle_real_new_1, _twiddle_rom_twiddle_real_new_WIRE_1
connect twiddle_rom_twiddle_1.real, _twiddle_rom_twiddle_real_new_1
wire _twiddle_rom_twiddle_imag_new_1 : SInt<19>
wire _twiddle_rom_twiddle_imag_new_WIRE_1 : SInt<19>
node _twiddle_rom_twiddle_imag_new_T_2 = asUInt(twiddle_rom_imag_1)
node _twiddle_rom_twiddle_imag_new_T_3 = asSInt(_twiddle_rom_twiddle_imag_new_T_2)
connect _twiddle_rom_twiddle_imag_new_WIRE_1, _twiddle_rom_twiddle_imag_new_T_3
connect _twiddle_rom_twiddle_imag_new_1, _twiddle_rom_twiddle_imag_new_WIRE_1
connect twiddle_rom_twiddle_1.imag, _twiddle_rom_twiddle_imag_new_1
wire twiddle_rom : { real : SInt<19>, imag : SInt<19>}[2]
connect twiddle_rom[0], twiddle_rom_twiddle
connect twiddle_rom[1], twiddle_rom_twiddle_1
wire indices_rom : UInt<2>[7]
connect indices_rom[0], UInt<1>(0h0)
connect indices_rom[1], UInt<1>(0h0)
connect indices_rom[2], UInt<1>(0h0)
connect indices_rom[3], UInt<2>(0h2)
connect indices_rom[4], UInt<2>(0h2)
connect indices_rom[5], UInt<1>(0h1)
connect indices_rom[6], UInt<2>(0h3)
node start = mul(sync, UInt<3>(0h7))
wire twiddle : { real : SInt<19>, imag : SInt<19>}[7]
node _twiddle_0_true_branch_qual2_T = add(start, UInt<1>(0h0))
node _twiddle_0_true_branch_qual2_T_1 = tail(_twiddle_0_true_branch_qual2_T, 1)
node _twiddle_0_true_branch_qual2_T_2 = or(_twiddle_0_true_branch_qual2_T_1, UInt<3>(0h0))
node _twiddle_0_true_branch_qual2_T_3 = bits(_twiddle_0_true_branch_qual2_T_2, 2, 0)
node _twiddle_0_true_branch_qual2_T_4 = bits(indices_rom[_twiddle_0_true_branch_qual2_T_3], 0, 0)
node _twiddle_0_true_branch_T = sub(asSInt(UInt<1>(0h0)), twiddle_rom[_twiddle_0_true_branch_qual2_T_4].real)
node _twiddle_0_true_branch_T_1 = tail(_twiddle_0_true_branch_T, 1)
node _twiddle_0_true_branch_T_2 = asSInt(_twiddle_0_true_branch_T_1)
wire _twiddle_0_true_branch_new : SInt<19>
wire _twiddle_0_true_branch_new_WIRE : SInt<19>
node _twiddle_0_true_branch_new_T = asUInt(_twiddle_0_true_branch_T_2)
node _twiddle_0_true_branch_new_T_1 = asSInt(_twiddle_0_true_branch_new_T)
connect _twiddle_0_true_branch_new_WIRE, _twiddle_0_true_branch_new_T_1
connect _twiddle_0_true_branch_new, _twiddle_0_true_branch_new_WIRE
wire twiddle_0_true_branch_result : { real : SInt<19>, imag : SInt<19>}
wire _twiddle_0_true_branch_result_real_new : SInt<19>
wire _twiddle_0_true_branch_result_real_new_WIRE : SInt<19>
node _twiddle_0_true_branch_result_real_new_T = asUInt(twiddle_rom[_twiddle_0_true_branch_qual2_T_4].imag)
node _twiddle_0_true_branch_result_real_new_T_1 = asSInt(_twiddle_0_true_branch_result_real_new_T)
connect _twiddle_0_true_branch_result_real_new_WIRE, _twiddle_0_true_branch_result_real_new_T_1
connect _twiddle_0_true_branch_result_real_new, _twiddle_0_true_branch_result_real_new_WIRE
connect twiddle_0_true_branch_result.real, _twiddle_0_true_branch_result_real_new
wire _twiddle_0_true_branch_result_imag_new : SInt<19>
wire _twiddle_0_true_branch_result_imag_new_WIRE : SInt<19>
node _twiddle_0_true_branch_result_imag_new_T = asUInt(_twiddle_0_true_branch_new)
node _twiddle_0_true_branch_result_imag_new_T_1 = asSInt(_twiddle_0_true_branch_result_imag_new_T)
connect _twiddle_0_true_branch_result_imag_new_WIRE, _twiddle_0_true_branch_result_imag_new_T_1
connect _twiddle_0_true_branch_result_imag_new, _twiddle_0_true_branch_result_imag_new_WIRE
connect twiddle_0_true_branch_result.imag, _twiddle_0_true_branch_result_imag_new
wire twiddle_0_true_branch : { real : SInt<19>, imag : SInt<19>}
node _twiddle_0_true_branch_T_3 = asUInt(twiddle_0_true_branch_result.imag)
node _twiddle_0_true_branch_T_4 = asUInt(twiddle_0_true_branch_result.real)
node _twiddle_0_true_branch_T_5 = cat(_twiddle_0_true_branch_T_4, _twiddle_0_true_branch_T_3)
wire _twiddle_0_true_branch_WIRE : UInt<38>
connect _twiddle_0_true_branch_WIRE, _twiddle_0_true_branch_T_5
node _twiddle_0_true_branch_T_6 = bits(_twiddle_0_true_branch_WIRE, 18, 0)
node _twiddle_0_true_branch_T_7 = asSInt(_twiddle_0_true_branch_T_6)
connect twiddle_0_true_branch.imag, _twiddle_0_true_branch_T_7
node _twiddle_0_true_branch_T_8 = bits(_twiddle_0_true_branch_WIRE, 37, 19)
node _twiddle_0_true_branch_T_9 = asSInt(_twiddle_0_true_branch_T_8)
connect twiddle_0_true_branch.real, _twiddle_0_true_branch_T_9
node _twiddle_0_false_branch_T = add(start, UInt<1>(0h0))
node _twiddle_0_false_branch_T_1 = tail(_twiddle_0_false_branch_T, 1)
node _twiddle_0_false_branch_T_2 = or(_twiddle_0_false_branch_T_1, UInt<3>(0h0))
node _twiddle_0_false_branch_T_3 = bits(_twiddle_0_false_branch_T_2, 2, 0)
node _twiddle_0_false_branch_T_4 = bits(indices_rom[_twiddle_0_false_branch_T_3], 0, 0)
wire twiddle_0_false_branch : { real : SInt<19>, imag : SInt<19>}
node _twiddle_0_false_branch_T_5 = asUInt(twiddle_rom[_twiddle_0_false_branch_T_4].imag)
node _twiddle_0_false_branch_T_6 = asUInt(twiddle_rom[_twiddle_0_false_branch_T_4].real)
node _twiddle_0_false_branch_T_7 = cat(_twiddle_0_false_branch_T_6, _twiddle_0_false_branch_T_5)
wire _twiddle_0_false_branch_WIRE : UInt<38>
connect _twiddle_0_false_branch_WIRE, _twiddle_0_false_branch_T_7
node _twiddle_0_false_branch_T_8 = bits(_twiddle_0_false_branch_WIRE, 18, 0)
node _twiddle_0_false_branch_T_9 = asSInt(_twiddle_0_false_branch_T_8)
connect twiddle_0_false_branch.imag, _twiddle_0_false_branch_T_9
node _twiddle_0_false_branch_T_10 = bits(_twiddle_0_false_branch_WIRE, 37, 19)
node _twiddle_0_false_branch_T_11 = asSInt(_twiddle_0_false_branch_T_10)
connect twiddle_0_false_branch.real, _twiddle_0_false_branch_T_11
node _twiddle_0_index_T = add(start, UInt<1>(0h0))
node _twiddle_0_index_T_1 = tail(_twiddle_0_index_T, 1)
node _twiddle_0_index_T_2 = or(_twiddle_0_index_T_1, UInt<3>(0h0))
node _twiddle_0_index_T_3 = bits(_twiddle_0_index_T_2, 2, 0)
node _twiddle_0_T = bits(indices_rom[_twiddle_0_index_T_3], 1, 1)
node _twiddle_0_T_1 = mux(_twiddle_0_T, twiddle_0_true_branch, twiddle_0_false_branch)
wire _twiddle_0_twiddle_0_imag_new : SInt<19>
wire _twiddle_0_twiddle_0_imag_new_WIRE : SInt<19>
node _twiddle_0_twiddle_0_imag_new_T = asUInt(_twiddle_0_T_1.imag)
node _twiddle_0_twiddle_0_imag_new_T_1 = asSInt(_twiddle_0_twiddle_0_imag_new_T)
connect _twiddle_0_twiddle_0_imag_new_WIRE, _twiddle_0_twiddle_0_imag_new_T_1
connect _twiddle_0_twiddle_0_imag_new, _twiddle_0_twiddle_0_imag_new_WIRE
connect twiddle[0].imag, _twiddle_0_twiddle_0_imag_new
wire _twiddle_0_twiddle_0_real_new : SInt<19>
wire _twiddle_0_twiddle_0_real_new_WIRE : SInt<19>
node _twiddle_0_twiddle_0_real_new_T = asUInt(_twiddle_0_T_1.real)
node _twiddle_0_twiddle_0_real_new_T_1 = asSInt(_twiddle_0_twiddle_0_real_new_T)
connect _twiddle_0_twiddle_0_real_new_WIRE, _twiddle_0_twiddle_0_real_new_T_1
connect _twiddle_0_twiddle_0_real_new, _twiddle_0_twiddle_0_real_new_WIRE
connect twiddle[0].real, _twiddle_0_twiddle_0_real_new
node _twiddle_1_true_branch_qual2_T = add(start, UInt<1>(0h1))
node _twiddle_1_true_branch_qual2_T_1 = tail(_twiddle_1_true_branch_qual2_T, 1)
node _twiddle_1_true_branch_qual2_T_2 = or(_twiddle_1_true_branch_qual2_T_1, UInt<3>(0h0))
node _twiddle_1_true_branch_qual2_T_3 = bits(_twiddle_1_true_branch_qual2_T_2, 2, 0)
node _twiddle_1_true_branch_qual2_T_4 = bits(indices_rom[_twiddle_1_true_branch_qual2_T_3], 0, 0)
node _twiddle_1_true_branch_T = sub(asSInt(UInt<1>(0h0)), twiddle_rom[_twiddle_1_true_branch_qual2_T_4].real)
node _twiddle_1_true_branch_T_1 = tail(_twiddle_1_true_branch_T, 1)
node _twiddle_1_true_branch_T_2 = asSInt(_twiddle_1_true_branch_T_1)
wire _twiddle_1_true_branch_new : SInt<19>
wire _twiddle_1_true_branch_new_WIRE : SInt<19>
node _twiddle_1_true_branch_new_T = asUInt(_twiddle_1_true_branch_T_2)
node _twiddle_1_true_branch_new_T_1 = asSInt(_twiddle_1_true_branch_new_T)
connect _twiddle_1_true_branch_new_WIRE, _twiddle_1_true_branch_new_T_1
connect _twiddle_1_true_branch_new, _twiddle_1_true_branch_new_WIRE
wire twiddle_1_true_branch_result : { real : SInt<19>, imag : SInt<19>}
wire _twiddle_1_true_branch_result_real_new : SInt<19>
wire _twiddle_1_true_branch_result_real_new_WIRE : SInt<19>
node _twiddle_1_true_branch_result_real_new_T = asUInt(twiddle_rom[_twiddle_1_true_branch_qual2_T_4].imag)
node _twiddle_1_true_branch_result_real_new_T_1 = asSInt(_twiddle_1_true_branch_result_real_new_T)
connect _twiddle_1_true_branch_result_real_new_WIRE, _twiddle_1_true_branch_result_real_new_T_1
connect _twiddle_1_true_branch_result_real_new, _twiddle_1_true_branch_result_real_new_WIRE
connect twiddle_1_true_branch_result.real, _twiddle_1_true_branch_result_real_new
wire _twiddle_1_true_branch_result_imag_new : SInt<19>
wire _twiddle_1_true_branch_result_imag_new_WIRE : SInt<19>
node _twiddle_1_true_branch_result_imag_new_T = asUInt(_twiddle_1_true_branch_new)
node _twiddle_1_true_branch_result_imag_new_T_1 = asSInt(_twiddle_1_true_branch_result_imag_new_T)
connect _twiddle_1_true_branch_result_imag_new_WIRE, _twiddle_1_true_branch_result_imag_new_T_1
connect _twiddle_1_true_branch_result_imag_new, _twiddle_1_true_branch_result_imag_new_WIRE
connect twiddle_1_true_branch_result.imag, _twiddle_1_true_branch_result_imag_new
wire twiddle_1_true_branch : { real : SInt<19>, imag : SInt<19>}
node _twiddle_1_true_branch_T_3 = asUInt(twiddle_1_true_branch_result.imag)
node _twiddle_1_true_branch_T_4 = asUInt(twiddle_1_true_branch_result.real)
node _twiddle_1_true_branch_T_5 = cat(_twiddle_1_true_branch_T_4, _twiddle_1_true_branch_T_3)
wire _twiddle_1_true_branch_WIRE : UInt<38>
connect _twiddle_1_true_branch_WIRE, _twiddle_1_true_branch_T_5
node _twiddle_1_true_branch_T_6 = bits(_twiddle_1_true_branch_WIRE, 18, 0)
node _twiddle_1_true_branch_T_7 = asSInt(_twiddle_1_true_branch_T_6)
connect twiddle_1_true_branch.imag, _twiddle_1_true_branch_T_7
node _twiddle_1_true_branch_T_8 = bits(_twiddle_1_true_branch_WIRE, 37, 19)
node _twiddle_1_true_branch_T_9 = asSInt(_twiddle_1_true_branch_T_8)
connect twiddle_1_true_branch.real, _twiddle_1_true_branch_T_9
node _twiddle_1_false_branch_T = add(start, UInt<1>(0h1))
node _twiddle_1_false_branch_T_1 = tail(_twiddle_1_false_branch_T, 1)
node _twiddle_1_false_branch_T_2 = or(_twiddle_1_false_branch_T_1, UInt<3>(0h0))
node _twiddle_1_false_branch_T_3 = bits(_twiddle_1_false_branch_T_2, 2, 0)
node _twiddle_1_false_branch_T_4 = bits(indices_rom[_twiddle_1_false_branch_T_3], 0, 0)
wire twiddle_1_false_branch : { real : SInt<19>, imag : SInt<19>}
node _twiddle_1_false_branch_T_5 = asUInt(twiddle_rom[_twiddle_1_false_branch_T_4].imag)
node _twiddle_1_false_branch_T_6 = asUInt(twiddle_rom[_twiddle_1_false_branch_T_4].real)
node _twiddle_1_false_branch_T_7 = cat(_twiddle_1_false_branch_T_6, _twiddle_1_false_branch_T_5)
wire _twiddle_1_false_branch_WIRE : UInt<38>
connect _twiddle_1_false_branch_WIRE, _twiddle_1_false_branch_T_7
node _twiddle_1_false_branch_T_8 = bits(_twiddle_1_false_branch_WIRE, 18, 0)
node _twiddle_1_false_branch_T_9 = asSInt(_twiddle_1_false_branch_T_8)
connect twiddle_1_false_branch.imag, _twiddle_1_false_branch_T_9
node _twiddle_1_false_branch_T_10 = bits(_twiddle_1_false_branch_WIRE, 37, 19)
node _twiddle_1_false_branch_T_11 = asSInt(_twiddle_1_false_branch_T_10)
connect twiddle_1_false_branch.real, _twiddle_1_false_branch_T_11
node _twiddle_1_index_T = add(start, UInt<1>(0h1))
node _twiddle_1_index_T_1 = tail(_twiddle_1_index_T, 1)
node _twiddle_1_index_T_2 = or(_twiddle_1_index_T_1, UInt<3>(0h0))
node _twiddle_1_index_T_3 = bits(_twiddle_1_index_T_2, 2, 0)
node _twiddle_1_T = bits(indices_rom[_twiddle_1_index_T_3], 1, 1)
node _twiddle_1_T_1 = mux(_twiddle_1_T, twiddle_1_true_branch, twiddle_1_false_branch)
wire _twiddle_1_twiddle_1_imag_new : SInt<19>
wire _twiddle_1_twiddle_1_imag_new_WIRE : SInt<19>
node _twiddle_1_twiddle_1_imag_new_T = asUInt(_twiddle_1_T_1.imag)
node _twiddle_1_twiddle_1_imag_new_T_1 = asSInt(_twiddle_1_twiddle_1_imag_new_T)
connect _twiddle_1_twiddle_1_imag_new_WIRE, _twiddle_1_twiddle_1_imag_new_T_1
connect _twiddle_1_twiddle_1_imag_new, _twiddle_1_twiddle_1_imag_new_WIRE
connect twiddle[1].imag, _twiddle_1_twiddle_1_imag_new
wire _twiddle_1_twiddle_1_real_new : SInt<19>
wire _twiddle_1_twiddle_1_real_new_WIRE : SInt<19>
node _twiddle_1_twiddle_1_real_new_T = asUInt(_twiddle_1_T_1.real)
node _twiddle_1_twiddle_1_real_new_T_1 = asSInt(_twiddle_1_twiddle_1_real_new_T)
connect _twiddle_1_twiddle_1_real_new_WIRE, _twiddle_1_twiddle_1_real_new_T_1
connect _twiddle_1_twiddle_1_real_new, _twiddle_1_twiddle_1_real_new_WIRE
connect twiddle[1].real, _twiddle_1_twiddle_1_real_new
node _twiddle_2_true_branch_qual2_T = add(start, UInt<2>(0h2))
node _twiddle_2_true_branch_qual2_T_1 = tail(_twiddle_2_true_branch_qual2_T, 1)
node _twiddle_2_true_branch_qual2_T_2 = or(_twiddle_2_true_branch_qual2_T_1, UInt<3>(0h0))
node _twiddle_2_true_branch_qual2_T_3 = bits(_twiddle_2_true_branch_qual2_T_2, 2, 0)
node _twiddle_2_true_branch_qual2_T_4 = bits(indices_rom[_twiddle_2_true_branch_qual2_T_3], 0, 0)
node _twiddle_2_true_branch_T = sub(asSInt(UInt<1>(0h0)), twiddle_rom[_twiddle_2_true_branch_qual2_T_4].real)
node _twiddle_2_true_branch_T_1 = tail(_twiddle_2_true_branch_T, 1)
node _twiddle_2_true_branch_T_2 = asSInt(_twiddle_2_true_branch_T_1)
wire _twiddle_2_true_branch_new : SInt<19>
wire _twiddle_2_true_branch_new_WIRE : SInt<19>
node _twiddle_2_true_branch_new_T = asUInt(_twiddle_2_true_branch_T_2)
node _twiddle_2_true_branch_new_T_1 = asSInt(_twiddle_2_true_branch_new_T)
connect _twiddle_2_true_branch_new_WIRE, _twiddle_2_true_branch_new_T_1
connect _twiddle_2_true_branch_new, _twiddle_2_true_branch_new_WIRE
wire twiddle_2_true_branch_result : { real : SInt<19>, imag : SInt<19>}
wire _twiddle_2_true_branch_result_real_new : SInt<19>
wire _twiddle_2_true_branch_result_real_new_WIRE : SInt<19>
node _twiddle_2_true_branch_result_real_new_T = asUInt(twiddle_rom[_twiddle_2_true_branch_qual2_T_4].imag)
node _twiddle_2_true_branch_result_real_new_T_1 = asSInt(_twiddle_2_true_branch_result_real_new_T)
connect _twiddle_2_true_branch_result_real_new_WIRE, _twiddle_2_true_branch_result_real_new_T_1
connect _twiddle_2_true_branch_result_real_new, _twiddle_2_true_branch_result_real_new_WIRE
connect twiddle_2_true_branch_result.real, _twiddle_2_true_branch_result_real_new
wire _twiddle_2_true_branch_result_imag_new : SInt<19>
wire _twiddle_2_true_branch_result_imag_new_WIRE : SInt<19>
node _twiddle_2_true_branch_result_imag_new_T = asUInt(_twiddle_2_true_branch_new)
node _twiddle_2_true_branch_result_imag_new_T_1 = asSInt(_twiddle_2_true_branch_result_imag_new_T)
connect _twiddle_2_true_branch_result_imag_new_WIRE, _twiddle_2_true_branch_result_imag_new_T_1
connect _twiddle_2_true_branch_result_imag_new, _twiddle_2_true_branch_result_imag_new_WIRE
connect twiddle_2_true_branch_result.imag, _twiddle_2_true_branch_result_imag_new
wire twiddle_2_true_branch : { real : SInt<19>, imag : SInt<19>}
node _twiddle_2_true_branch_T_3 = asUInt(twiddle_2_true_branch_result.imag)
node _twiddle_2_true_branch_T_4 = asUInt(twiddle_2_true_branch_result.real)
node _twiddle_2_true_branch_T_5 = cat(_twiddle_2_true_branch_T_4, _twiddle_2_true_branch_T_3)
wire _twiddle_2_true_branch_WIRE : UInt<38>
connect _twiddle_2_true_branch_WIRE, _twiddle_2_true_branch_T_5
node _twiddle_2_true_branch_T_6 = bits(_twiddle_2_true_branch_WIRE, 18, 0)
node _twiddle_2_true_branch_T_7 = asSInt(_twiddle_2_true_branch_T_6)
connect twiddle_2_true_branch.imag, _twiddle_2_true_branch_T_7
node _twiddle_2_true_branch_T_8 = bits(_twiddle_2_true_branch_WIRE, 37, 19)
node _twiddle_2_true_branch_T_9 = asSInt(_twiddle_2_true_branch_T_8)
connect twiddle_2_true_branch.real, _twiddle_2_true_branch_T_9
node _twiddle_2_false_branch_T = add(start, UInt<2>(0h2))
node _twiddle_2_false_branch_T_1 = tail(_twiddle_2_false_branch_T, 1)
node _twiddle_2_false_branch_T_2 = or(_twiddle_2_false_branch_T_1, UInt<3>(0h0))
node _twiddle_2_false_branch_T_3 = bits(_twiddle_2_false_branch_T_2, 2, 0)
node _twiddle_2_false_branch_T_4 = bits(indices_rom[_twiddle_2_false_branch_T_3], 0, 0)
wire twiddle_2_false_branch : { real : SInt<19>, imag : SInt<19>}
node _twiddle_2_false_branch_T_5 = asUInt(twiddle_rom[_twiddle_2_false_branch_T_4].imag)
node _twiddle_2_false_branch_T_6 = asUInt(twiddle_rom[_twiddle_2_false_branch_T_4].real)
node _twiddle_2_false_branch_T_7 = cat(_twiddle_2_false_branch_T_6, _twiddle_2_false_branch_T_5)
wire _twiddle_2_false_branch_WIRE : UInt<38>
connect _twiddle_2_false_branch_WIRE, _twiddle_2_false_branch_T_7
node _twiddle_2_false_branch_T_8 = bits(_twiddle_2_false_branch_WIRE, 18, 0)
node _twiddle_2_false_branch_T_9 = asSInt(_twiddle_2_false_branch_T_8)
connect twiddle_2_false_branch.imag, _twiddle_2_false_branch_T_9
node _twiddle_2_false_branch_T_10 = bits(_twiddle_2_false_branch_WIRE, 37, 19)
node _twiddle_2_false_branch_T_11 = asSInt(_twiddle_2_false_branch_T_10)
connect twiddle_2_false_branch.real, _twiddle_2_false_branch_T_11
node _twiddle_2_index_T = add(start, UInt<2>(0h2))
node _twiddle_2_index_T_1 = tail(_twiddle_2_index_T, 1)
node _twiddle_2_index_T_2 = or(_twiddle_2_index_T_1, UInt<3>(0h0))
node _twiddle_2_index_T_3 = bits(_twiddle_2_index_T_2, 2, 0)
node _twiddle_2_T = bits(indices_rom[_twiddle_2_index_T_3], 1, 1)
node _twiddle_2_T_1 = mux(_twiddle_2_T, twiddle_2_true_branch, twiddle_2_false_branch)
wire _twiddle_2_twiddle_2_imag_new : SInt<19>
wire _twiddle_2_twiddle_2_imag_new_WIRE : SInt<19>
node _twiddle_2_twiddle_2_imag_new_T = asUInt(_twiddle_2_T_1.imag)
node _twiddle_2_twiddle_2_imag_new_T_1 = asSInt(_twiddle_2_twiddle_2_imag_new_T)
connect _twiddle_2_twiddle_2_imag_new_WIRE, _twiddle_2_twiddle_2_imag_new_T_1
connect _twiddle_2_twiddle_2_imag_new, _twiddle_2_twiddle_2_imag_new_WIRE
connect twiddle[2].imag, _twiddle_2_twiddle_2_imag_new
wire _twiddle_2_twiddle_2_real_new : SInt<19>
wire _twiddle_2_twiddle_2_real_new_WIRE : SInt<19>
node _twiddle_2_twiddle_2_real_new_T = asUInt(_twiddle_2_T_1.real)
node _twiddle_2_twiddle_2_real_new_T_1 = asSInt(_twiddle_2_twiddle_2_real_new_T)
connect _twiddle_2_twiddle_2_real_new_WIRE, _twiddle_2_twiddle_2_real_new_T_1
connect _twiddle_2_twiddle_2_real_new, _twiddle_2_twiddle_2_real_new_WIRE
connect twiddle[2].real, _twiddle_2_twiddle_2_real_new
node _twiddle_3_true_branch_qual2_T = add(start, UInt<2>(0h3))
node _twiddle_3_true_branch_qual2_T_1 = tail(_twiddle_3_true_branch_qual2_T, 1)
node _twiddle_3_true_branch_qual2_T_2 = or(_twiddle_3_true_branch_qual2_T_1, UInt<3>(0h0))
node _twiddle_3_true_branch_qual2_T_3 = bits(_twiddle_3_true_branch_qual2_T_2, 2, 0)
node _twiddle_3_true_branch_qual2_T_4 = bits(indices_rom[_twiddle_3_true_branch_qual2_T_3], 0, 0)
node _twiddle_3_true_branch_T = sub(asSInt(UInt<1>(0h0)), twiddle_rom[_twiddle_3_true_branch_qual2_T_4].real)
node _twiddle_3_true_branch_T_1 = tail(_twiddle_3_true_branch_T, 1)
node _twiddle_3_true_branch_T_2 = asSInt(_twiddle_3_true_branch_T_1)
wire _twiddle_3_true_branch_new : SInt<19>
wire _twiddle_3_true_branch_new_WIRE : SInt<19>
node _twiddle_3_true_branch_new_T = asUInt(_twiddle_3_true_branch_T_2)
node _twiddle_3_true_branch_new_T_1 = asSInt(_twiddle_3_true_branch_new_T)
connect _twiddle_3_true_branch_new_WIRE, _twiddle_3_true_branch_new_T_1
connect _twiddle_3_true_branch_new, _twiddle_3_true_branch_new_WIRE
wire twiddle_3_true_branch_result : { real : SInt<19>, imag : SInt<19>}
wire _twiddle_3_true_branch_result_real_new : SInt<19>
wire _twiddle_3_true_branch_result_real_new_WIRE : SInt<19>
node _twiddle_3_true_branch_result_real_new_T = asUInt(twiddle_rom[_twiddle_3_true_branch_qual2_T_4].imag)
node _twiddle_3_true_branch_result_real_new_T_1 = asSInt(_twiddle_3_true_branch_result_real_new_T)
connect _twiddle_3_true_branch_result_real_new_WIRE, _twiddle_3_true_branch_result_real_new_T_1
connect _twiddle_3_true_branch_result_real_new, _twiddle_3_true_branch_result_real_new_WIRE
connect twiddle_3_true_branch_result.real, _twiddle_3_true_branch_result_real_new
wire _twiddle_3_true_branch_result_imag_new : SInt<19>
wire _twiddle_3_true_branch_result_imag_new_WIRE : SInt<19>
node _twiddle_3_true_branch_result_imag_new_T = asUInt(_twiddle_3_true_branch_new)
node _twiddle_3_true_branch_result_imag_new_T_1 = asSInt(_twiddle_3_true_branch_result_imag_new_T)
connect _twiddle_3_true_branch_result_imag_new_WIRE, _twiddle_3_true_branch_result_imag_new_T_1
connect _twiddle_3_true_branch_result_imag_new, _twiddle_3_true_branch_result_imag_new_WIRE
connect twiddle_3_true_branch_result.imag, _twiddle_3_true_branch_result_imag_new
wire twiddle_3_true_branch : { real : SInt<19>, imag : SInt<19>}
node _twiddle_3_true_branch_T_3 = asUInt(twiddle_3_true_branch_result.imag)
node _twiddle_3_true_branch_T_4 = asUInt(twiddle_3_true_branch_result.real)
node _twiddle_3_true_branch_T_5 = cat(_twiddle_3_true_branch_T_4, _twiddle_3_true_branch_T_3)
wire _twiddle_3_true_branch_WIRE : UInt<38>
connect _twiddle_3_true_branch_WIRE, _twiddle_3_true_branch_T_5
node _twiddle_3_true_branch_T_6 = bits(_twiddle_3_true_branch_WIRE, 18, 0)
node _twiddle_3_true_branch_T_7 = asSInt(_twiddle_3_true_branch_T_6)
connect twiddle_3_true_branch.imag, _twiddle_3_true_branch_T_7
node _twiddle_3_true_branch_T_8 = bits(_twiddle_3_true_branch_WIRE, 37, 19)
node _twiddle_3_true_branch_T_9 = asSInt(_twiddle_3_true_branch_T_8)
connect twiddle_3_true_branch.real, _twiddle_3_true_branch_T_9
node _twiddle_3_false_branch_T = add(start, UInt<2>(0h3))
node _twiddle_3_false_branch_T_1 = tail(_twiddle_3_false_branch_T, 1)
node _twiddle_3_false_branch_T_2 = or(_twiddle_3_false_branch_T_1, UInt<3>(0h0))
node _twiddle_3_false_branch_T_3 = bits(_twiddle_3_false_branch_T_2, 2, 0)
node _twiddle_3_false_branch_T_4 = bits(indices_rom[_twiddle_3_false_branch_T_3], 0, 0)
wire twiddle_3_false_branch : { real : SInt<19>, imag : SInt<19>}
node _twiddle_3_false_branch_T_5 = asUInt(twiddle_rom[_twiddle_3_false_branch_T_4].imag)
node _twiddle_3_false_branch_T_6 = asUInt(twiddle_rom[_twiddle_3_false_branch_T_4].real)
node _twiddle_3_false_branch_T_7 = cat(_twiddle_3_false_branch_T_6, _twiddle_3_false_branch_T_5)
wire _twiddle_3_false_branch_WIRE : UInt<38>
connect _twiddle_3_false_branch_WIRE, _twiddle_3_false_branch_T_7
node _twiddle_3_false_branch_T_8 = bits(_twiddle_3_false_branch_WIRE, 18, 0)
node _twiddle_3_false_branch_T_9 = asSInt(_twiddle_3_false_branch_T_8)
connect twiddle_3_false_branch.imag, _twiddle_3_false_branch_T_9
node _twiddle_3_false_branch_T_10 = bits(_twiddle_3_false_branch_WIRE, 37, 19)
node _twiddle_3_false_branch_T_11 = asSInt(_twiddle_3_false_branch_T_10)
connect twiddle_3_false_branch.real, _twiddle_3_false_branch_T_11
node _twiddle_3_index_T = add(start, UInt<2>(0h3))
node _twiddle_3_index_T_1 = tail(_twiddle_3_index_T, 1)
node _twiddle_3_index_T_2 = or(_twiddle_3_index_T_1, UInt<3>(0h0))
node _twiddle_3_index_T_3 = bits(_twiddle_3_index_T_2, 2, 0)
node _twiddle_3_T = bits(indices_rom[_twiddle_3_index_T_3], 1, 1)
node _twiddle_3_T_1 = mux(_twiddle_3_T, twiddle_3_true_branch, twiddle_3_false_branch)
wire _twiddle_3_twiddle_3_imag_new : SInt<19>
wire _twiddle_3_twiddle_3_imag_new_WIRE : SInt<19>
node _twiddle_3_twiddle_3_imag_new_T = asUInt(_twiddle_3_T_1.imag)
node _twiddle_3_twiddle_3_imag_new_T_1 = asSInt(_twiddle_3_twiddle_3_imag_new_T)
connect _twiddle_3_twiddle_3_imag_new_WIRE, _twiddle_3_twiddle_3_imag_new_T_1
connect _twiddle_3_twiddle_3_imag_new, _twiddle_3_twiddle_3_imag_new_WIRE
connect twiddle[3].imag, _twiddle_3_twiddle_3_imag_new
wire _twiddle_3_twiddle_3_real_new : SInt<19>
wire _twiddle_3_twiddle_3_real_new_WIRE : SInt<19>
node _twiddle_3_twiddle_3_real_new_T = asUInt(_twiddle_3_T_1.real)
node _twiddle_3_twiddle_3_real_new_T_1 = asSInt(_twiddle_3_twiddle_3_real_new_T)
connect _twiddle_3_twiddle_3_real_new_WIRE, _twiddle_3_twiddle_3_real_new_T_1
connect _twiddle_3_twiddle_3_real_new, _twiddle_3_twiddle_3_real_new_WIRE
connect twiddle[3].real, _twiddle_3_twiddle_3_real_new
node _twiddle_4_true_branch_qual2_T = add(start, UInt<3>(0h4))
node _twiddle_4_true_branch_qual2_T_1 = tail(_twiddle_4_true_branch_qual2_T, 1)
node _twiddle_4_true_branch_qual2_T_2 = or(_twiddle_4_true_branch_qual2_T_1, UInt<3>(0h0))
node _twiddle_4_true_branch_qual2_T_3 = bits(_twiddle_4_true_branch_qual2_T_2, 2, 0)
node _twiddle_4_true_branch_qual2_T_4 = bits(indices_rom[_twiddle_4_true_branch_qual2_T_3], 0, 0)
node _twiddle_4_true_branch_T = sub(asSInt(UInt<1>(0h0)), twiddle_rom[_twiddle_4_true_branch_qual2_T_4].real)
node _twiddle_4_true_branch_T_1 = tail(_twiddle_4_true_branch_T, 1)
node _twiddle_4_true_branch_T_2 = asSInt(_twiddle_4_true_branch_T_1)
wire _twiddle_4_true_branch_new : SInt<19>
wire _twiddle_4_true_branch_new_WIRE : SInt<19>
node _twiddle_4_true_branch_new_T = asUInt(_twiddle_4_true_branch_T_2)
node _twiddle_4_true_branch_new_T_1 = asSInt(_twiddle_4_true_branch_new_T)
connect _twiddle_4_true_branch_new_WIRE, _twiddle_4_true_branch_new_T_1
connect _twiddle_4_true_branch_new, _twiddle_4_true_branch_new_WIRE
wire twiddle_4_true_branch_result : { real : SInt<19>, imag : SInt<19>}
wire _twiddle_4_true_branch_result_real_new : SInt<19>
wire _twiddle_4_true_branch_result_real_new_WIRE : SInt<19>
node _twiddle_4_true_branch_result_real_new_T = asUInt(twiddle_rom[_twiddle_4_true_branch_qual2_T_4].imag)
node _twiddle_4_true_branch_result_real_new_T_1 = asSInt(_twiddle_4_true_branch_result_real_new_T)
connect _twiddle_4_true_branch_result_real_new_WIRE, _twiddle_4_true_branch_result_real_new_T_1
connect _twiddle_4_true_branch_result_real_new, _twiddle_4_true_branch_result_real_new_WIRE
connect twiddle_4_true_branch_result.real, _twiddle_4_true_branch_result_real_new
wire _twiddle_4_true_branch_result_imag_new : SInt<19>
wire _twiddle_4_true_branch_result_imag_new_WIRE : SInt<19>
node _twiddle_4_true_branch_result_imag_new_T = asUInt(_twiddle_4_true_branch_new)
node _twiddle_4_true_branch_result_imag_new_T_1 = asSInt(_twiddle_4_true_branch_result_imag_new_T)
connect _twiddle_4_true_branch_result_imag_new_WIRE, _twiddle_4_true_branch_result_imag_new_T_1
connect _twiddle_4_true_branch_result_imag_new, _twiddle_4_true_branch_result_imag_new_WIRE
connect twiddle_4_true_branch_result.imag, _twiddle_4_true_branch_result_imag_new
wire twiddle_4_true_branch : { real : SInt<19>, imag : SInt<19>}
node _twiddle_4_true_branch_T_3 = asUInt(twiddle_4_true_branch_result.imag)
node _twiddle_4_true_branch_T_4 = asUInt(twiddle_4_true_branch_result.real)
node _twiddle_4_true_branch_T_5 = cat(_twiddle_4_true_branch_T_4, _twiddle_4_true_branch_T_3)
wire _twiddle_4_true_branch_WIRE : UInt<38>
connect _twiddle_4_true_branch_WIRE, _twiddle_4_true_branch_T_5
node _twiddle_4_true_branch_T_6 = bits(_twiddle_4_true_branch_WIRE, 18, 0)
node _twiddle_4_true_branch_T_7 = asSInt(_twiddle_4_true_branch_T_6)
connect twiddle_4_true_branch.imag, _twiddle_4_true_branch_T_7
node _twiddle_4_true_branch_T_8 = bits(_twiddle_4_true_branch_WIRE, 37, 19)
node _twiddle_4_true_branch_T_9 = asSInt(_twiddle_4_true_branch_T_8)
connect twiddle_4_true_branch.real, _twiddle_4_true_branch_T_9
node _twiddle_4_false_branch_T = add(start, UInt<3>(0h4))
node _twiddle_4_false_branch_T_1 = tail(_twiddle_4_false_branch_T, 1)
node _twiddle_4_false_branch_T_2 = or(_twiddle_4_false_branch_T_1, UInt<3>(0h0))
node _twiddle_4_false_branch_T_3 = bits(_twiddle_4_false_branch_T_2, 2, 0)
node _twiddle_4_false_branch_T_4 = bits(indices_rom[_twiddle_4_false_branch_T_3], 0, 0)
wire twiddle_4_false_branch : { real : SInt<19>, imag : SInt<19>}
node _twiddle_4_false_branch_T_5 = asUInt(twiddle_rom[_twiddle_4_false_branch_T_4].imag)
node _twiddle_4_false_branch_T_6 = asUInt(twiddle_rom[_twiddle_4_false_branch_T_4].real)
node _twiddle_4_false_branch_T_7 = cat(_twiddle_4_false_branch_T_6, _twiddle_4_false_branch_T_5)
wire _twiddle_4_false_branch_WIRE : UInt<38>
connect _twiddle_4_false_branch_WIRE, _twiddle_4_false_branch_T_7
node _twiddle_4_false_branch_T_8 = bits(_twiddle_4_false_branch_WIRE, 18, 0)
node _twiddle_4_false_branch_T_9 = asSInt(_twiddle_4_false_branch_T_8)
connect twiddle_4_false_branch.imag, _twiddle_4_false_branch_T_9
node _twiddle_4_false_branch_T_10 = bits(_twiddle_4_false_branch_WIRE, 37, 19)
node _twiddle_4_false_branch_T_11 = asSInt(_twiddle_4_false_branch_T_10)
connect twiddle_4_false_branch.real, _twiddle_4_false_branch_T_11
node _twiddle_4_index_T = add(start, UInt<3>(0h4))
node _twiddle_4_index_T_1 = tail(_twiddle_4_index_T, 1)
node _twiddle_4_index_T_2 = or(_twiddle_4_index_T_1, UInt<3>(0h0))
node _twiddle_4_index_T_3 = bits(_twiddle_4_index_T_2, 2, 0)
node _twiddle_4_T = bits(indices_rom[_twiddle_4_index_T_3], 1, 1)
node _twiddle_4_T_1 = mux(_twiddle_4_T, twiddle_4_true_branch, twiddle_4_false_branch)
wire _twiddle_4_twiddle_4_imag_new : SInt<19>
wire _twiddle_4_twiddle_4_imag_new_WIRE : SInt<19>
node _twiddle_4_twiddle_4_imag_new_T = asUInt(_twiddle_4_T_1.imag)
node _twiddle_4_twiddle_4_imag_new_T_1 = asSInt(_twiddle_4_twiddle_4_imag_new_T)
connect _twiddle_4_twiddle_4_imag_new_WIRE, _twiddle_4_twiddle_4_imag_new_T_1
connect _twiddle_4_twiddle_4_imag_new, _twiddle_4_twiddle_4_imag_new_WIRE
connect twiddle[4].imag, _twiddle_4_twiddle_4_imag_new
wire _twiddle_4_twiddle_4_real_new : SInt<19>
wire _twiddle_4_twiddle_4_real_new_WIRE : SInt<19>
node _twiddle_4_twiddle_4_real_new_T = asUInt(_twiddle_4_T_1.real)
node _twiddle_4_twiddle_4_real_new_T_1 = asSInt(_twiddle_4_twiddle_4_real_new_T)
connect _twiddle_4_twiddle_4_real_new_WIRE, _twiddle_4_twiddle_4_real_new_T_1
connect _twiddle_4_twiddle_4_real_new, _twiddle_4_twiddle_4_real_new_WIRE
connect twiddle[4].real, _twiddle_4_twiddle_4_real_new
node _twiddle_5_true_branch_qual2_T = add(start, UInt<3>(0h5))
node _twiddle_5_true_branch_qual2_T_1 = tail(_twiddle_5_true_branch_qual2_T, 1)
node _twiddle_5_true_branch_qual2_T_2 = or(_twiddle_5_true_branch_qual2_T_1, UInt<3>(0h0))
node _twiddle_5_true_branch_qual2_T_3 = bits(_twiddle_5_true_branch_qual2_T_2, 2, 0)
node _twiddle_5_true_branch_qual2_T_4 = bits(indices_rom[_twiddle_5_true_branch_qual2_T_3], 0, 0)
node _twiddle_5_true_branch_T = sub(asSInt(UInt<1>(0h0)), twiddle_rom[_twiddle_5_true_branch_qual2_T_4].real)
node _twiddle_5_true_branch_T_1 = tail(_twiddle_5_true_branch_T, 1)
node _twiddle_5_true_branch_T_2 = asSInt(_twiddle_5_true_branch_T_1)
wire _twiddle_5_true_branch_new : SInt<19>
wire _twiddle_5_true_branch_new_WIRE : SInt<19>
node _twiddle_5_true_branch_new_T = asUInt(_twiddle_5_true_branch_T_2)
node _twiddle_5_true_branch_new_T_1 = asSInt(_twiddle_5_true_branch_new_T)
connect _twiddle_5_true_branch_new_WIRE, _twiddle_5_true_branch_new_T_1
connect _twiddle_5_true_branch_new, _twiddle_5_true_branch_new_WIRE
wire twiddle_5_true_branch_result : { real : SInt<19>, imag : SInt<19>}
wire _twiddle_5_true_branch_result_real_new : SInt<19>
wire _twiddle_5_true_branch_result_real_new_WIRE : SInt<19>
node _twiddle_5_true_branch_result_real_new_T = asUInt(twiddle_rom[_twiddle_5_true_branch_qual2_T_4].imag)
node _twiddle_5_true_branch_result_real_new_T_1 = asSInt(_twiddle_5_true_branch_result_real_new_T)
connect _twiddle_5_true_branch_result_real_new_WIRE, _twiddle_5_true_branch_result_real_new_T_1
connect _twiddle_5_true_branch_result_real_new, _twiddle_5_true_branch_result_real_new_WIRE
connect twiddle_5_true_branch_result.real, _twiddle_5_true_branch_result_real_new
wire _twiddle_5_true_branch_result_imag_new : SInt<19>
wire _twiddle_5_true_branch_result_imag_new_WIRE : SInt<19>
node _twiddle_5_true_branch_result_imag_new_T = asUInt(_twiddle_5_true_branch_new)
node _twiddle_5_true_branch_result_imag_new_T_1 = asSInt(_twiddle_5_true_branch_result_imag_new_T)
connect _twiddle_5_true_branch_result_imag_new_WIRE, _twiddle_5_true_branch_result_imag_new_T_1
connect _twiddle_5_true_branch_result_imag_new, _twiddle_5_true_branch_result_imag_new_WIRE
connect twiddle_5_true_branch_result.imag, _twiddle_5_true_branch_result_imag_new
wire twiddle_5_true_branch : { real : SInt<19>, imag : SInt<19>}
node _twiddle_5_true_branch_T_3 = asUInt(twiddle_5_true_branch_result.imag)
node _twiddle_5_true_branch_T_4 = asUInt(twiddle_5_true_branch_result.real)
node _twiddle_5_true_branch_T_5 = cat(_twiddle_5_true_branch_T_4, _twiddle_5_true_branch_T_3)
wire _twiddle_5_true_branch_WIRE : UInt<38>
connect _twiddle_5_true_branch_WIRE, _twiddle_5_true_branch_T_5
node _twiddle_5_true_branch_T_6 = bits(_twiddle_5_true_branch_WIRE, 18, 0)
node _twiddle_5_true_branch_T_7 = asSInt(_twiddle_5_true_branch_T_6)
connect twiddle_5_true_branch.imag, _twiddle_5_true_branch_T_7
node _twiddle_5_true_branch_T_8 = bits(_twiddle_5_true_branch_WIRE, 37, 19)
node _twiddle_5_true_branch_T_9 = asSInt(_twiddle_5_true_branch_T_8)
connect twiddle_5_true_branch.real, _twiddle_5_true_branch_T_9
node _twiddle_5_false_branch_T = add(start, UInt<3>(0h5))
node _twiddle_5_false_branch_T_1 = tail(_twiddle_5_false_branch_T, 1)
node _twiddle_5_false_branch_T_2 = or(_twiddle_5_false_branch_T_1, UInt<3>(0h0))
node _twiddle_5_false_branch_T_3 = bits(_twiddle_5_false_branch_T_2, 2, 0)
node _twiddle_5_false_branch_T_4 = bits(indices_rom[_twiddle_5_false_branch_T_3], 0, 0)
wire twiddle_5_false_branch : { real : SInt<19>, imag : SInt<19>}
node _twiddle_5_false_branch_T_5 = asUInt(twiddle_rom[_twiddle_5_false_branch_T_4].imag)
node _twiddle_5_false_branch_T_6 = asUInt(twiddle_rom[_twiddle_5_false_branch_T_4].real)
node _twiddle_5_false_branch_T_7 = cat(_twiddle_5_false_branch_T_6, _twiddle_5_false_branch_T_5)
wire _twiddle_5_false_branch_WIRE : UInt<38>
connect _twiddle_5_false_branch_WIRE, _twiddle_5_false_branch_T_7
node _twiddle_5_false_branch_T_8 = bits(_twiddle_5_false_branch_WIRE, 18, 0)
node _twiddle_5_false_branch_T_9 = asSInt(_twiddle_5_false_branch_T_8)
connect twiddle_5_false_branch.imag, _twiddle_5_false_branch_T_9
node _twiddle_5_false_branch_T_10 = bits(_twiddle_5_false_branch_WIRE, 37, 19)
node _twiddle_5_false_branch_T_11 = asSInt(_twiddle_5_false_branch_T_10)
connect twiddle_5_false_branch.real, _twiddle_5_false_branch_T_11
node _twiddle_5_index_T = add(start, UInt<3>(0h5))
node _twiddle_5_index_T_1 = tail(_twiddle_5_index_T, 1)
node _twiddle_5_index_T_2 = or(_twiddle_5_index_T_1, UInt<3>(0h0))
node _twiddle_5_index_T_3 = bits(_twiddle_5_index_T_2, 2, 0)
node _twiddle_5_T = bits(indices_rom[_twiddle_5_index_T_3], 1, 1)
node _twiddle_5_T_1 = mux(_twiddle_5_T, twiddle_5_true_branch, twiddle_5_false_branch)
wire _twiddle_5_twiddle_5_imag_new : SInt<19>
wire _twiddle_5_twiddle_5_imag_new_WIRE : SInt<19>
node _twiddle_5_twiddle_5_imag_new_T = asUInt(_twiddle_5_T_1.imag)
node _twiddle_5_twiddle_5_imag_new_T_1 = asSInt(_twiddle_5_twiddle_5_imag_new_T)
connect _twiddle_5_twiddle_5_imag_new_WIRE, _twiddle_5_twiddle_5_imag_new_T_1
connect _twiddle_5_twiddle_5_imag_new, _twiddle_5_twiddle_5_imag_new_WIRE
connect twiddle[5].imag, _twiddle_5_twiddle_5_imag_new
wire _twiddle_5_twiddle_5_real_new : SInt<19>
wire _twiddle_5_twiddle_5_real_new_WIRE : SInt<19>
node _twiddle_5_twiddle_5_real_new_T = asUInt(_twiddle_5_T_1.real)
node _twiddle_5_twiddle_5_real_new_T_1 = asSInt(_twiddle_5_twiddle_5_real_new_T)
connect _twiddle_5_twiddle_5_real_new_WIRE, _twiddle_5_twiddle_5_real_new_T_1
connect _twiddle_5_twiddle_5_real_new, _twiddle_5_twiddle_5_real_new_WIRE
connect twiddle[5].real, _twiddle_5_twiddle_5_real_new
node _twiddle_6_true_branch_qual2_T = add(start, UInt<3>(0h6))
node _twiddle_6_true_branch_qual2_T_1 = tail(_twiddle_6_true_branch_qual2_T, 1)
node _twiddle_6_true_branch_qual2_T_2 = or(_twiddle_6_true_branch_qual2_T_1, UInt<3>(0h0))
node _twiddle_6_true_branch_qual2_T_3 = bits(_twiddle_6_true_branch_qual2_T_2, 2, 0)
node _twiddle_6_true_branch_qual2_T_4 = bits(indices_rom[_twiddle_6_true_branch_qual2_T_3], 0, 0)
node _twiddle_6_true_branch_T = sub(asSInt(UInt<1>(0h0)), twiddle_rom[_twiddle_6_true_branch_qual2_T_4].real)
node _twiddle_6_true_branch_T_1 = tail(_twiddle_6_true_branch_T, 1)
node _twiddle_6_true_branch_T_2 = asSInt(_twiddle_6_true_branch_T_1)
wire _twiddle_6_true_branch_new : SInt<19>
wire _twiddle_6_true_branch_new_WIRE : SInt<19>
node _twiddle_6_true_branch_new_T = asUInt(_twiddle_6_true_branch_T_2)
node _twiddle_6_true_branch_new_T_1 = asSInt(_twiddle_6_true_branch_new_T)
connect _twiddle_6_true_branch_new_WIRE, _twiddle_6_true_branch_new_T_1
connect _twiddle_6_true_branch_new, _twiddle_6_true_branch_new_WIRE
wire twiddle_6_true_branch_result : { real : SInt<19>, imag : SInt<19>}
wire _twiddle_6_true_branch_result_real_new : SInt<19>
wire _twiddle_6_true_branch_result_real_new_WIRE : SInt<19>
node _twiddle_6_true_branch_result_real_new_T = asUInt(twiddle_rom[_twiddle_6_true_branch_qual2_T_4].imag)
node _twiddle_6_true_branch_result_real_new_T_1 = asSInt(_twiddle_6_true_branch_result_real_new_T)
connect _twiddle_6_true_branch_result_real_new_WIRE, _twiddle_6_true_branch_result_real_new_T_1
connect _twiddle_6_true_branch_result_real_new, _twiddle_6_true_branch_result_real_new_WIRE
connect twiddle_6_true_branch_result.real, _twiddle_6_true_branch_result_real_new
wire _twiddle_6_true_branch_result_imag_new : SInt<19>
wire _twiddle_6_true_branch_result_imag_new_WIRE : SInt<19>
node _twiddle_6_true_branch_result_imag_new_T = asUInt(_twiddle_6_true_branch_new)
node _twiddle_6_true_branch_result_imag_new_T_1 = asSInt(_twiddle_6_true_branch_result_imag_new_T)
connect _twiddle_6_true_branch_result_imag_new_WIRE, _twiddle_6_true_branch_result_imag_new_T_1
connect _twiddle_6_true_branch_result_imag_new, _twiddle_6_true_branch_result_imag_new_WIRE
connect twiddle_6_true_branch_result.imag, _twiddle_6_true_branch_result_imag_new
wire twiddle_6_true_branch : { real : SInt<19>, imag : SInt<19>}
node _twiddle_6_true_branch_T_3 = asUInt(twiddle_6_true_branch_result.imag)
node _twiddle_6_true_branch_T_4 = asUInt(twiddle_6_true_branch_result.real)
node _twiddle_6_true_branch_T_5 = cat(_twiddle_6_true_branch_T_4, _twiddle_6_true_branch_T_3)
wire _twiddle_6_true_branch_WIRE : UInt<38>
connect _twiddle_6_true_branch_WIRE, _twiddle_6_true_branch_T_5
node _twiddle_6_true_branch_T_6 = bits(_twiddle_6_true_branch_WIRE, 18, 0)
node _twiddle_6_true_branch_T_7 = asSInt(_twiddle_6_true_branch_T_6)
connect twiddle_6_true_branch.imag, _twiddle_6_true_branch_T_7
node _twiddle_6_true_branch_T_8 = bits(_twiddle_6_true_branch_WIRE, 37, 19)
node _twiddle_6_true_branch_T_9 = asSInt(_twiddle_6_true_branch_T_8)
connect twiddle_6_true_branch.real, _twiddle_6_true_branch_T_9
node _twiddle_6_false_branch_T = add(start, UInt<3>(0h6))
node _twiddle_6_false_branch_T_1 = tail(_twiddle_6_false_branch_T, 1)
node _twiddle_6_false_branch_T_2 = or(_twiddle_6_false_branch_T_1, UInt<3>(0h0))
node _twiddle_6_false_branch_T_3 = bits(_twiddle_6_false_branch_T_2, 2, 0)
node _twiddle_6_false_branch_T_4 = bits(indices_rom[_twiddle_6_false_branch_T_3], 0, 0)
wire twiddle_6_false_branch : { real : SInt<19>, imag : SInt<19>}
node _twiddle_6_false_branch_T_5 = asUInt(twiddle_rom[_twiddle_6_false_branch_T_4].imag)
node _twiddle_6_false_branch_T_6 = asUInt(twiddle_rom[_twiddle_6_false_branch_T_4].real)
node _twiddle_6_false_branch_T_7 = cat(_twiddle_6_false_branch_T_6, _twiddle_6_false_branch_T_5)
wire _twiddle_6_false_branch_WIRE : UInt<38>
connect _twiddle_6_false_branch_WIRE, _twiddle_6_false_branch_T_7
node _twiddle_6_false_branch_T_8 = bits(_twiddle_6_false_branch_WIRE, 18, 0)
node _twiddle_6_false_branch_T_9 = asSInt(_twiddle_6_false_branch_T_8)
connect twiddle_6_false_branch.imag, _twiddle_6_false_branch_T_9
node _twiddle_6_false_branch_T_10 = bits(_twiddle_6_false_branch_WIRE, 37, 19)
node _twiddle_6_false_branch_T_11 = asSInt(_twiddle_6_false_branch_T_10)
connect twiddle_6_false_branch.real, _twiddle_6_false_branch_T_11
node _twiddle_6_index_T = add(start, UInt<3>(0h6))
node _twiddle_6_index_T_1 = tail(_twiddle_6_index_T, 1)
node _twiddle_6_index_T_2 = or(_twiddle_6_index_T_1, UInt<3>(0h0))
node _twiddle_6_index_T_3 = bits(_twiddle_6_index_T_2, 2, 0)
node _twiddle_6_T = bits(indices_rom[_twiddle_6_index_T_3], 1, 1)
node _twiddle_6_T_1 = mux(_twiddle_6_T, twiddle_6_true_branch, twiddle_6_false_branch)
wire _twiddle_6_twiddle_6_imag_new : SInt<19>
wire _twiddle_6_twiddle_6_imag_new_WIRE : SInt<19>
node _twiddle_6_twiddle_6_imag_new_T = asUInt(_twiddle_6_T_1.imag)
node _twiddle_6_twiddle_6_imag_new_T_1 = asSInt(_twiddle_6_twiddle_6_imag_new_T)
connect _twiddle_6_twiddle_6_imag_new_WIRE, _twiddle_6_twiddle_6_imag_new_T_1
connect _twiddle_6_twiddle_6_imag_new, _twiddle_6_twiddle_6_imag_new_WIRE
connect twiddle[6].imag, _twiddle_6_twiddle_6_imag_new
wire _twiddle_6_twiddle_6_real_new : SInt<19>
wire _twiddle_6_twiddle_6_real_new_WIRE : SInt<19>
node _twiddle_6_twiddle_6_real_new_T = asUInt(_twiddle_6_T_1.real)
node _twiddle_6_twiddle_6_real_new_T_1 = asSInt(_twiddle_6_twiddle_6_real_new_T)
connect _twiddle_6_twiddle_6_real_new_WIRE, _twiddle_6_twiddle_6_real_new_T_1
connect _twiddle_6_twiddle_6_real_new, _twiddle_6_twiddle_6_real_new_WIRE
connect twiddle[6].real, _twiddle_6_twiddle_6_real_new
wire stage_outputs_0_0 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_0_1 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_0_2 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_0_3 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_0_4 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_0_5 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_0_6 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_0_7 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_1_0 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_1_1 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_1_2 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_1_3 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_1_4 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_1_5 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_1_6 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_1_7 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_2_0 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_2_1 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_2_2 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_2_3 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_2_4 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_2_5 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_2_6 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_2_7 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_3_0 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_3_1 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_3_2 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_3_3 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_3_4 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_3_5 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_3_6 : { real : SInt<16>, imag : SInt<16>}
wire stage_outputs_3_7 : { real : SInt<16>, imag : SInt<16>}
wire _stage_outputs_0_0_stage_outputs_0_0_imag_new : SInt<16>
wire _stage_outputs_0_0_stage_outputs_0_0_imag_new_WIRE : SInt<16>
node _stage_outputs_0_0_stage_outputs_0_0_imag_new_T = asUInt(io.in.bits[0].imag)
node _stage_outputs_0_0_stage_outputs_0_0_imag_new_T_1 = asSInt(_stage_outputs_0_0_stage_outputs_0_0_imag_new_T)
connect _stage_outputs_0_0_stage_outputs_0_0_imag_new_WIRE, _stage_outputs_0_0_stage_outputs_0_0_imag_new_T_1
connect _stage_outputs_0_0_stage_outputs_0_0_imag_new, _stage_outputs_0_0_stage_outputs_0_0_imag_new_WIRE
connect stage_outputs_0_0.imag, _stage_outputs_0_0_stage_outputs_0_0_imag_new
wire _stage_outputs_0_0_stage_outputs_0_0_real_new : SInt<16>
wire _stage_outputs_0_0_stage_outputs_0_0_real_new_WIRE : SInt<16>
node _stage_outputs_0_0_stage_outputs_0_0_real_new_T = asUInt(io.in.bits[0].real)
node _stage_outputs_0_0_stage_outputs_0_0_real_new_T_1 = asSInt(_stage_outputs_0_0_stage_outputs_0_0_real_new_T)
connect _stage_outputs_0_0_stage_outputs_0_0_real_new_WIRE, _stage_outputs_0_0_stage_outputs_0_0_real_new_T_1
connect _stage_outputs_0_0_stage_outputs_0_0_real_new, _stage_outputs_0_0_stage_outputs_0_0_real_new_WIRE
connect stage_outputs_0_0.real, _stage_outputs_0_0_stage_outputs_0_0_real_new
wire _stage_outputs_0_1_stage_outputs_0_1_imag_new : SInt<16>
wire _stage_outputs_0_1_stage_outputs_0_1_imag_new_WIRE : SInt<16>
node _stage_outputs_0_1_stage_outputs_0_1_imag_new_T = asUInt(io.in.bits[1].imag)
node _stage_outputs_0_1_stage_outputs_0_1_imag_new_T_1 = asSInt(_stage_outputs_0_1_stage_outputs_0_1_imag_new_T)
connect _stage_outputs_0_1_stage_outputs_0_1_imag_new_WIRE, _stage_outputs_0_1_stage_outputs_0_1_imag_new_T_1
connect _stage_outputs_0_1_stage_outputs_0_1_imag_new, _stage_outputs_0_1_stage_outputs_0_1_imag_new_WIRE
connect stage_outputs_0_1.imag, _stage_outputs_0_1_stage_outputs_0_1_imag_new
wire _stage_outputs_0_1_stage_outputs_0_1_real_new : SInt<16>
wire _stage_outputs_0_1_stage_outputs_0_1_real_new_WIRE : SInt<16>
node _stage_outputs_0_1_stage_outputs_0_1_real_new_T = asUInt(io.in.bits[1].real)
node _stage_outputs_0_1_stage_outputs_0_1_real_new_T_1 = asSInt(_stage_outputs_0_1_stage_outputs_0_1_real_new_T)
connect _stage_outputs_0_1_stage_outputs_0_1_real_new_WIRE, _stage_outputs_0_1_stage_outputs_0_1_real_new_T_1
connect _stage_outputs_0_1_stage_outputs_0_1_real_new, _stage_outputs_0_1_stage_outputs_0_1_real_new_WIRE
connect stage_outputs_0_1.real, _stage_outputs_0_1_stage_outputs_0_1_real_new
wire _stage_outputs_0_2_stage_outputs_0_2_imag_new : SInt<16>
wire _stage_outputs_0_2_stage_outputs_0_2_imag_new_WIRE : SInt<16>
node _stage_outputs_0_2_stage_outputs_0_2_imag_new_T = asUInt(io.in.bits[2].imag)
node _stage_outputs_0_2_stage_outputs_0_2_imag_new_T_1 = asSInt(_stage_outputs_0_2_stage_outputs_0_2_imag_new_T)
connect _stage_outputs_0_2_stage_outputs_0_2_imag_new_WIRE, _stage_outputs_0_2_stage_outputs_0_2_imag_new_T_1
connect _stage_outputs_0_2_stage_outputs_0_2_imag_new, _stage_outputs_0_2_stage_outputs_0_2_imag_new_WIRE
connect stage_outputs_0_2.imag, _stage_outputs_0_2_stage_outputs_0_2_imag_new
wire _stage_outputs_0_2_stage_outputs_0_2_real_new : SInt<16>
wire _stage_outputs_0_2_stage_outputs_0_2_real_new_WIRE : SInt<16>
node _stage_outputs_0_2_stage_outputs_0_2_real_new_T = asUInt(io.in.bits[2].real)
node _stage_outputs_0_2_stage_outputs_0_2_real_new_T_1 = asSInt(_stage_outputs_0_2_stage_outputs_0_2_real_new_T)
connect _stage_outputs_0_2_stage_outputs_0_2_real_new_WIRE, _stage_outputs_0_2_stage_outputs_0_2_real_new_T_1
connect _stage_outputs_0_2_stage_outputs_0_2_real_new, _stage_outputs_0_2_stage_outputs_0_2_real_new_WIRE
connect stage_outputs_0_2.real, _stage_outputs_0_2_stage_outputs_0_2_real_new
wire _stage_outputs_0_3_stage_outputs_0_3_imag_new : SInt<16>
wire _stage_outputs_0_3_stage_outputs_0_3_imag_new_WIRE : SInt<16>
node _stage_outputs_0_3_stage_outputs_0_3_imag_new_T = asUInt(io.in.bits[3].imag)
node _stage_outputs_0_3_stage_outputs_0_3_imag_new_T_1 = asSInt(_stage_outputs_0_3_stage_outputs_0_3_imag_new_T)
connect _stage_outputs_0_3_stage_outputs_0_3_imag_new_WIRE, _stage_outputs_0_3_stage_outputs_0_3_imag_new_T_1
connect _stage_outputs_0_3_stage_outputs_0_3_imag_new, _stage_outputs_0_3_stage_outputs_0_3_imag_new_WIRE
connect stage_outputs_0_3.imag, _stage_outputs_0_3_stage_outputs_0_3_imag_new
wire _stage_outputs_0_3_stage_outputs_0_3_real_new : SInt<16>
wire _stage_outputs_0_3_stage_outputs_0_3_real_new_WIRE : SInt<16>
node _stage_outputs_0_3_stage_outputs_0_3_real_new_T = asUInt(io.in.bits[3].real)
node _stage_outputs_0_3_stage_outputs_0_3_real_new_T_1 = asSInt(_stage_outputs_0_3_stage_outputs_0_3_real_new_T)
connect _stage_outputs_0_3_stage_outputs_0_3_real_new_WIRE, _stage_outputs_0_3_stage_outputs_0_3_real_new_T_1
connect _stage_outputs_0_3_stage_outputs_0_3_real_new, _stage_outputs_0_3_stage_outputs_0_3_real_new_WIRE
connect stage_outputs_0_3.real, _stage_outputs_0_3_stage_outputs_0_3_real_new
wire _stage_outputs_0_4_stage_outputs_0_4_imag_new : SInt<16>
wire _stage_outputs_0_4_stage_outputs_0_4_imag_new_WIRE : SInt<16>
node _stage_outputs_0_4_stage_outputs_0_4_imag_new_T = asUInt(io.in.bits[4].imag)
node _stage_outputs_0_4_stage_outputs_0_4_imag_new_T_1 = asSInt(_stage_outputs_0_4_stage_outputs_0_4_imag_new_T)
connect _stage_outputs_0_4_stage_outputs_0_4_imag_new_WIRE, _stage_outputs_0_4_stage_outputs_0_4_imag_new_T_1
connect _stage_outputs_0_4_stage_outputs_0_4_imag_new, _stage_outputs_0_4_stage_outputs_0_4_imag_new_WIRE
connect stage_outputs_0_4.imag, _stage_outputs_0_4_stage_outputs_0_4_imag_new
wire _stage_outputs_0_4_stage_outputs_0_4_real_new : SInt<16>
wire _stage_outputs_0_4_stage_outputs_0_4_real_new_WIRE : SInt<16>
node _stage_outputs_0_4_stage_outputs_0_4_real_new_T = asUInt(io.in.bits[4].real)
node _stage_outputs_0_4_stage_outputs_0_4_real_new_T_1 = asSInt(_stage_outputs_0_4_stage_outputs_0_4_real_new_T)
connect _stage_outputs_0_4_stage_outputs_0_4_real_new_WIRE, _stage_outputs_0_4_stage_outputs_0_4_real_new_T_1
connect _stage_outputs_0_4_stage_outputs_0_4_real_new, _stage_outputs_0_4_stage_outputs_0_4_real_new_WIRE
connect stage_outputs_0_4.real, _stage_outputs_0_4_stage_outputs_0_4_real_new
wire _stage_outputs_0_5_stage_outputs_0_5_imag_new : SInt<16>
wire _stage_outputs_0_5_stage_outputs_0_5_imag_new_WIRE : SInt<16>
node _stage_outputs_0_5_stage_outputs_0_5_imag_new_T = asUInt(io.in.bits[5].imag)
node _stage_outputs_0_5_stage_outputs_0_5_imag_new_T_1 = asSInt(_stage_outputs_0_5_stage_outputs_0_5_imag_new_T)
connect _stage_outputs_0_5_stage_outputs_0_5_imag_new_WIRE, _stage_outputs_0_5_stage_outputs_0_5_imag_new_T_1
connect _stage_outputs_0_5_stage_outputs_0_5_imag_new, _stage_outputs_0_5_stage_outputs_0_5_imag_new_WIRE
connect stage_outputs_0_5.imag, _stage_outputs_0_5_stage_outputs_0_5_imag_new
wire _stage_outputs_0_5_stage_outputs_0_5_real_new : SInt<16>
wire _stage_outputs_0_5_stage_outputs_0_5_real_new_WIRE : SInt<16>
node _stage_outputs_0_5_stage_outputs_0_5_real_new_T = asUInt(io.in.bits[5].real)
node _stage_outputs_0_5_stage_outputs_0_5_real_new_T_1 = asSInt(_stage_outputs_0_5_stage_outputs_0_5_real_new_T)
connect _stage_outputs_0_5_stage_outputs_0_5_real_new_WIRE, _stage_outputs_0_5_stage_outputs_0_5_real_new_T_1
connect _stage_outputs_0_5_stage_outputs_0_5_real_new, _stage_outputs_0_5_stage_outputs_0_5_real_new_WIRE
connect stage_outputs_0_5.real, _stage_outputs_0_5_stage_outputs_0_5_real_new
wire _stage_outputs_0_6_stage_outputs_0_6_imag_new : SInt<16>
wire _stage_outputs_0_6_stage_outputs_0_6_imag_new_WIRE : SInt<16>
node _stage_outputs_0_6_stage_outputs_0_6_imag_new_T = asUInt(io.in.bits[6].imag)
node _stage_outputs_0_6_stage_outputs_0_6_imag_new_T_1 = asSInt(_stage_outputs_0_6_stage_outputs_0_6_imag_new_T)
connect _stage_outputs_0_6_stage_outputs_0_6_imag_new_WIRE, _stage_outputs_0_6_stage_outputs_0_6_imag_new_T_1
connect _stage_outputs_0_6_stage_outputs_0_6_imag_new, _stage_outputs_0_6_stage_outputs_0_6_imag_new_WIRE
connect stage_outputs_0_6.imag, _stage_outputs_0_6_stage_outputs_0_6_imag_new
wire _stage_outputs_0_6_stage_outputs_0_6_real_new : SInt<16>
wire _stage_outputs_0_6_stage_outputs_0_6_real_new_WIRE : SInt<16>
node _stage_outputs_0_6_stage_outputs_0_6_real_new_T = asUInt(io.in.bits[6].real)
node _stage_outputs_0_6_stage_outputs_0_6_real_new_T_1 = asSInt(_stage_outputs_0_6_stage_outputs_0_6_real_new_T)
connect _stage_outputs_0_6_stage_outputs_0_6_real_new_WIRE, _stage_outputs_0_6_stage_outputs_0_6_real_new_T_1
connect _stage_outputs_0_6_stage_outputs_0_6_real_new, _stage_outputs_0_6_stage_outputs_0_6_real_new_WIRE
connect stage_outputs_0_6.real, _stage_outputs_0_6_stage_outputs_0_6_real_new
wire _stage_outputs_0_7_stage_outputs_0_7_imag_new : SInt<16>
wire _stage_outputs_0_7_stage_outputs_0_7_imag_new_WIRE : SInt<16>
node _stage_outputs_0_7_stage_outputs_0_7_imag_new_T = asUInt(io.in.bits[7].imag)
node _stage_outputs_0_7_stage_outputs_0_7_imag_new_T_1 = asSInt(_stage_outputs_0_7_stage_outputs_0_7_imag_new_T)
connect _stage_outputs_0_7_stage_outputs_0_7_imag_new_WIRE, _stage_outputs_0_7_stage_outputs_0_7_imag_new_T_1
connect _stage_outputs_0_7_stage_outputs_0_7_imag_new, _stage_outputs_0_7_stage_outputs_0_7_imag_new_WIRE
connect stage_outputs_0_7.imag, _stage_outputs_0_7_stage_outputs_0_7_imag_new
wire _stage_outputs_0_7_stage_outputs_0_7_real_new : SInt<16>
wire _stage_outputs_0_7_stage_outputs_0_7_real_new_WIRE : SInt<16>
node _stage_outputs_0_7_stage_outputs_0_7_real_new_T = asUInt(io.in.bits[7].real)
node _stage_outputs_0_7_stage_outputs_0_7_real_new_T_1 = asSInt(_stage_outputs_0_7_stage_outputs_0_7_real_new_T)
connect _stage_outputs_0_7_stage_outputs_0_7_real_new_WIRE, _stage_outputs_0_7_stage_outputs_0_7_real_new_T_1
connect _stage_outputs_0_7_stage_outputs_0_7_real_new, _stage_outputs_0_7_stage_outputs_0_7_real_new_WIRE
connect stage_outputs_0_7.real, _stage_outputs_0_7_stage_outputs_0_7_real_new
wire butterfly_outputs_product_c_p_d_out_0 : SInt<19>
wire _butterfly_outputs_product_c_p_d_out_new_WIRE : SInt<19>
node _butterfly_outputs_product_c_p_d_out_new_T = asUInt(twiddle[0].real)
node _butterfly_outputs_product_c_p_d_out_new_T_1 = asSInt(_butterfly_outputs_product_c_p_d_out_new_T)
connect _butterfly_outputs_product_c_p_d_out_new_WIRE, _butterfly_outputs_product_c_p_d_out_new_T_1
connect butterfly_outputs_product_c_p_d_out_0, _butterfly_outputs_product_c_p_d_out_new_WIRE
wire butterfly_outputs_product_c_p_d_out_1 : SInt<19>
wire _butterfly_outputs_product_c_p_d_out_new_WIRE_1 : SInt<19>
node _butterfly_outputs_product_c_p_d_out_new_T_2 = asUInt(twiddle[0].imag)
node _butterfly_outputs_product_c_p_d_out_new_T_3 = asSInt(_butterfly_outputs_product_c_p_d_out_new_T_2)
connect _butterfly_outputs_product_c_p_d_out_new_WIRE_1, _butterfly_outputs_product_c_p_d_out_new_T_3
connect butterfly_outputs_product_c_p_d_out_1, _butterfly_outputs_product_c_p_d_out_new_WIRE_1
wire _butterfly_outputs_product_c_p_d_this : SInt<19>
wire _butterfly_outputs_product_c_p_d_new : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T = asUInt(butterfly_outputs_product_c_p_d_out_0)
node _butterfly_outputs_product_c_p_d_new_T_1 = asSInt(_butterfly_outputs_product_c_p_d_new_T)
connect _butterfly_outputs_product_c_p_d_new_WIRE, _butterfly_outputs_product_c_p_d_new_T_1
connect _butterfly_outputs_product_c_p_d_new, _butterfly_outputs_product_c_p_d_new_WIRE
connect _butterfly_outputs_product_c_p_d_this, _butterfly_outputs_product_c_p_d_new
wire _butterfly_outputs_product_c_p_d_that : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_1 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_1 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_2 = asUInt(butterfly_outputs_product_c_p_d_out_1)
node _butterfly_outputs_product_c_p_d_new_T_3 = asSInt(_butterfly_outputs_product_c_p_d_new_T_2)
connect _butterfly_outputs_product_c_p_d_new_WIRE_1, _butterfly_outputs_product_c_p_d_new_T_3
connect _butterfly_outputs_product_c_p_d_new_1, _butterfly_outputs_product_c_p_d_new_WIRE_1
connect _butterfly_outputs_product_c_p_d_that, _butterfly_outputs_product_c_p_d_new_1
node _butterfly_outputs_product_c_p_d_T = add(_butterfly_outputs_product_c_p_d_this, _butterfly_outputs_product_c_p_d_that)
node _butterfly_outputs_product_c_p_d_T_1 = tail(_butterfly_outputs_product_c_p_d_T, 1)
node _butterfly_outputs_product_c_p_d_T_2 = asSInt(_butterfly_outputs_product_c_p_d_T_1)
wire butterfly_outputs_product_c_p_d : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_2 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_4 = asUInt(_butterfly_outputs_product_c_p_d_T_2)
node _butterfly_outputs_product_c_p_d_new_T_5 = asSInt(_butterfly_outputs_product_c_p_d_new_T_4)
connect _butterfly_outputs_product_c_p_d_new_WIRE_2, _butterfly_outputs_product_c_p_d_new_T_5
connect butterfly_outputs_product_c_p_d, _butterfly_outputs_product_c_p_d_new_WIRE_2
wire butterfly_outputs_product_a_p_b_out_0 : SInt<16>
wire _butterfly_outputs_product_a_p_b_out_new_WIRE : SInt<16>
node _butterfly_outputs_product_a_p_b_out_new_T = asUInt(stage_outputs_0_4.real)
node _butterfly_outputs_product_a_p_b_out_new_T_1 = asSInt(_butterfly_outputs_product_a_p_b_out_new_T)
connect _butterfly_outputs_product_a_p_b_out_new_WIRE, _butterfly_outputs_product_a_p_b_out_new_T_1
connect butterfly_outputs_product_a_p_b_out_0, _butterfly_outputs_product_a_p_b_out_new_WIRE
wire butterfly_outputs_product_a_p_b_out_1 : SInt<16>
wire _butterfly_outputs_product_a_p_b_out_new_WIRE_1 : SInt<16>
node _butterfly_outputs_product_a_p_b_out_new_T_2 = asUInt(stage_outputs_0_4.imag)
node _butterfly_outputs_product_a_p_b_out_new_T_3 = asSInt(_butterfly_outputs_product_a_p_b_out_new_T_2)
connect _butterfly_outputs_product_a_p_b_out_new_WIRE_1, _butterfly_outputs_product_a_p_b_out_new_T_3
connect butterfly_outputs_product_a_p_b_out_1, _butterfly_outputs_product_a_p_b_out_new_WIRE_1
wire _butterfly_outputs_product_a_p_b_this : SInt<16>
wire _butterfly_outputs_product_a_p_b_new : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T = asUInt(butterfly_outputs_product_a_p_b_out_0)
node _butterfly_outputs_product_a_p_b_new_T_1 = asSInt(_butterfly_outputs_product_a_p_b_new_T)
connect _butterfly_outputs_product_a_p_b_new_WIRE, _butterfly_outputs_product_a_p_b_new_T_1
connect _butterfly_outputs_product_a_p_b_new, _butterfly_outputs_product_a_p_b_new_WIRE
connect _butterfly_outputs_product_a_p_b_this, _butterfly_outputs_product_a_p_b_new
wire _butterfly_outputs_product_a_p_b_that : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_1 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_1 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_2 = asUInt(butterfly_outputs_product_a_p_b_out_1)
node _butterfly_outputs_product_a_p_b_new_T_3 = asSInt(_butterfly_outputs_product_a_p_b_new_T_2)
connect _butterfly_outputs_product_a_p_b_new_WIRE_1, _butterfly_outputs_product_a_p_b_new_T_3
connect _butterfly_outputs_product_a_p_b_new_1, _butterfly_outputs_product_a_p_b_new_WIRE_1
connect _butterfly_outputs_product_a_p_b_that, _butterfly_outputs_product_a_p_b_new_1
node _butterfly_outputs_product_a_p_b_T = add(_butterfly_outputs_product_a_p_b_this, _butterfly_outputs_product_a_p_b_that)
node _butterfly_outputs_product_a_p_b_T_1 = tail(_butterfly_outputs_product_a_p_b_T, 1)
node _butterfly_outputs_product_a_p_b_T_2 = asSInt(_butterfly_outputs_product_a_p_b_T_1)
wire butterfly_outputs_product_a_p_b : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_2 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_4 = asUInt(_butterfly_outputs_product_a_p_b_T_2)
node _butterfly_outputs_product_a_p_b_new_T_5 = asSInt(_butterfly_outputs_product_a_p_b_new_T_4)
connect _butterfly_outputs_product_a_p_b_new_WIRE_2, _butterfly_outputs_product_a_p_b_new_T_5
connect butterfly_outputs_product_a_p_b, _butterfly_outputs_product_a_p_b_new_WIRE_2
wire butterfly_outputs_product_b_m_a_out_0 : SInt<16>
wire _butterfly_outputs_product_b_m_a_out_new_WIRE : SInt<16>
node _butterfly_outputs_product_b_m_a_out_new_T = asUInt(stage_outputs_0_4.imag)
node _butterfly_outputs_product_b_m_a_out_new_T_1 = asSInt(_butterfly_outputs_product_b_m_a_out_new_T)
connect _butterfly_outputs_product_b_m_a_out_new_WIRE, _butterfly_outputs_product_b_m_a_out_new_T_1
connect butterfly_outputs_product_b_m_a_out_0, _butterfly_outputs_product_b_m_a_out_new_WIRE
wire butterfly_outputs_product_b_m_a_out_1 : SInt<16>
wire _butterfly_outputs_product_b_m_a_out_new_WIRE_1 : SInt<16>
node _butterfly_outputs_product_b_m_a_out_new_T_2 = asUInt(stage_outputs_0_4.real)
node _butterfly_outputs_product_b_m_a_out_new_T_3 = asSInt(_butterfly_outputs_product_b_m_a_out_new_T_2)
connect _butterfly_outputs_product_b_m_a_out_new_WIRE_1, _butterfly_outputs_product_b_m_a_out_new_T_3
connect butterfly_outputs_product_b_m_a_out_1, _butterfly_outputs_product_b_m_a_out_new_WIRE_1
wire _butterfly_outputs_product_b_m_a_this : SInt<16>
wire _butterfly_outputs_product_b_m_a_new : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T = asUInt(butterfly_outputs_product_b_m_a_out_0)
node _butterfly_outputs_product_b_m_a_new_T_1 = asSInt(_butterfly_outputs_product_b_m_a_new_T)
connect _butterfly_outputs_product_b_m_a_new_WIRE, _butterfly_outputs_product_b_m_a_new_T_1
connect _butterfly_outputs_product_b_m_a_new, _butterfly_outputs_product_b_m_a_new_WIRE
connect _butterfly_outputs_product_b_m_a_this, _butterfly_outputs_product_b_m_a_new
wire _butterfly_outputs_product_b_m_a_that : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_1 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_1 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_2 = asUInt(butterfly_outputs_product_b_m_a_out_1)
node _butterfly_outputs_product_b_m_a_new_T_3 = asSInt(_butterfly_outputs_product_b_m_a_new_T_2)
connect _butterfly_outputs_product_b_m_a_new_WIRE_1, _butterfly_outputs_product_b_m_a_new_T_3
connect _butterfly_outputs_product_b_m_a_new_1, _butterfly_outputs_product_b_m_a_new_WIRE_1
connect _butterfly_outputs_product_b_m_a_that, _butterfly_outputs_product_b_m_a_new_1
node _butterfly_outputs_product_b_m_a_T = sub(_butterfly_outputs_product_b_m_a_this, _butterfly_outputs_product_b_m_a_that)
node _butterfly_outputs_product_b_m_a_T_1 = tail(_butterfly_outputs_product_b_m_a_T, 1)
node _butterfly_outputs_product_b_m_a_T_2 = asSInt(_butterfly_outputs_product_b_m_a_T_1)
wire butterfly_outputs_product_b_m_a : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_2 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_4 = asUInt(_butterfly_outputs_product_b_m_a_T_2)
node _butterfly_outputs_product_b_m_a_new_T_5 = asSInt(_butterfly_outputs_product_b_m_a_new_T_4)
connect _butterfly_outputs_product_b_m_a_new_WIRE_2, _butterfly_outputs_product_b_m_a_new_T_5
connect butterfly_outputs_product_b_m_a, _butterfly_outputs_product_b_m_a_new_WIRE_2
node _butterfly_outputs_product_ac_p_ad_T = mul(stage_outputs_0_4.real, butterfly_outputs_product_c_p_d)
wire butterfly_outputs_product_ac_p_ad : SInt<35>
wire _butterfly_outputs_product_ac_p_ad_new_WIRE : SInt<35>
node _butterfly_outputs_product_ac_p_ad_new_T = asUInt(_butterfly_outputs_product_ac_p_ad_T)
node _butterfly_outputs_product_ac_p_ad_new_T_1 = asSInt(_butterfly_outputs_product_ac_p_ad_new_T)
connect _butterfly_outputs_product_ac_p_ad_new_WIRE, _butterfly_outputs_product_ac_p_ad_new_T_1
connect butterfly_outputs_product_ac_p_ad, _butterfly_outputs_product_ac_p_ad_new_WIRE
node _butterfly_outputs_product_ad_p_bd_T = mul(butterfly_outputs_product_a_p_b, twiddle[0].imag)
wire butterfly_outputs_product_ad_p_bd : SInt<35>
wire _butterfly_outputs_product_ad_p_bd_new_WIRE : SInt<35>
node _butterfly_outputs_product_ad_p_bd_new_T = asUInt(_butterfly_outputs_product_ad_p_bd_T)
node _butterfly_outputs_product_ad_p_bd_new_T_1 = asSInt(_butterfly_outputs_product_ad_p_bd_new_T)
connect _butterfly_outputs_product_ad_p_bd_new_WIRE, _butterfly_outputs_product_ad_p_bd_new_T_1
connect butterfly_outputs_product_ad_p_bd, _butterfly_outputs_product_ad_p_bd_new_WIRE
node _butterfly_outputs_product_bc_m_ac_T = mul(butterfly_outputs_product_b_m_a, twiddle[0].real)
wire butterfly_outputs_product_bc_m_ac : SInt<35>
wire _butterfly_outputs_product_bc_m_ac_new_WIRE : SInt<35>
node _butterfly_outputs_product_bc_m_ac_new_T = asUInt(_butterfly_outputs_product_bc_m_ac_T)
node _butterfly_outputs_product_bc_m_ac_new_T_1 = asSInt(_butterfly_outputs_product_bc_m_ac_new_T)
connect _butterfly_outputs_product_bc_m_ac_new_WIRE, _butterfly_outputs_product_bc_m_ac_new_T_1
connect butterfly_outputs_product_bc_m_ac, _butterfly_outputs_product_bc_m_ac_new_WIRE
wire butterfly_outputs_product_out_0 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE : SInt<35>
node _butterfly_outputs_product_out_new_T = asUInt(butterfly_outputs_product_ac_p_ad)
node _butterfly_outputs_product_out_new_T_1 = asSInt(_butterfly_outputs_product_out_new_T)
connect _butterfly_outputs_product_out_new_WIRE, _butterfly_outputs_product_out_new_T_1
connect butterfly_outputs_product_out_0, _butterfly_outputs_product_out_new_WIRE
wire butterfly_outputs_product_out_1 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_1 : SInt<35>
node _butterfly_outputs_product_out_new_T_2 = asUInt(butterfly_outputs_product_ad_p_bd)
node _butterfly_outputs_product_out_new_T_3 = asSInt(_butterfly_outputs_product_out_new_T_2)
connect _butterfly_outputs_product_out_new_WIRE_1, _butterfly_outputs_product_out_new_T_3
connect butterfly_outputs_product_out_1, _butterfly_outputs_product_out_new_WIRE_1
wire _butterfly_outputs_product_this : SInt<35>
wire _butterfly_outputs_product_new : SInt<35>
wire _butterfly_outputs_product_new_WIRE : SInt<35>
node _butterfly_outputs_product_new_T = asUInt(butterfly_outputs_product_out_0)
node _butterfly_outputs_product_new_T_1 = asSInt(_butterfly_outputs_product_new_T)
connect _butterfly_outputs_product_new_WIRE, _butterfly_outputs_product_new_T_1
connect _butterfly_outputs_product_new, _butterfly_outputs_product_new_WIRE
connect _butterfly_outputs_product_this, _butterfly_outputs_product_new
wire _butterfly_outputs_product_that : SInt<35>
wire _butterfly_outputs_product_new_1 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_1 : SInt<35>
node _butterfly_outputs_product_new_T_2 = asUInt(butterfly_outputs_product_out_1)
node _butterfly_outputs_product_new_T_3 = asSInt(_butterfly_outputs_product_new_T_2)
connect _butterfly_outputs_product_new_WIRE_1, _butterfly_outputs_product_new_T_3
connect _butterfly_outputs_product_new_1, _butterfly_outputs_product_new_WIRE_1
connect _butterfly_outputs_product_that, _butterfly_outputs_product_new_1
node _butterfly_outputs_product_T = sub(_butterfly_outputs_product_this, _butterfly_outputs_product_that)
node _butterfly_outputs_product_T_1 = tail(_butterfly_outputs_product_T, 1)
node _butterfly_outputs_product_T_2 = asSInt(_butterfly_outputs_product_T_1)
wire _butterfly_outputs_product_new_2 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_2 : SInt<35>
node _butterfly_outputs_product_new_T_4 = asUInt(_butterfly_outputs_product_T_2)
node _butterfly_outputs_product_new_T_5 = asSInt(_butterfly_outputs_product_new_T_4)
connect _butterfly_outputs_product_new_WIRE_2, _butterfly_outputs_product_new_T_5
connect _butterfly_outputs_product_new_2, _butterfly_outputs_product_new_WIRE_2
wire butterfly_outputs_product_out_0_1 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_2 : SInt<35>
node _butterfly_outputs_product_out_new_T_4 = asUInt(butterfly_outputs_product_ac_p_ad)
node _butterfly_outputs_product_out_new_T_5 = asSInt(_butterfly_outputs_product_out_new_T_4)
connect _butterfly_outputs_product_out_new_WIRE_2, _butterfly_outputs_product_out_new_T_5
connect butterfly_outputs_product_out_0_1, _butterfly_outputs_product_out_new_WIRE_2
wire butterfly_outputs_product_out_1_1 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_3 : SInt<35>
node _butterfly_outputs_product_out_new_T_6 = asUInt(butterfly_outputs_product_bc_m_ac)
node _butterfly_outputs_product_out_new_T_7 = asSInt(_butterfly_outputs_product_out_new_T_6)
connect _butterfly_outputs_product_out_new_WIRE_3, _butterfly_outputs_product_out_new_T_7
connect butterfly_outputs_product_out_1_1, _butterfly_outputs_product_out_new_WIRE_3
wire _butterfly_outputs_product_this_1 : SInt<35>
wire _butterfly_outputs_product_new_3 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_3 : SInt<35>
node _butterfly_outputs_product_new_T_6 = asUInt(butterfly_outputs_product_out_0_1)
node _butterfly_outputs_product_new_T_7 = asSInt(_butterfly_outputs_product_new_T_6)
connect _butterfly_outputs_product_new_WIRE_3, _butterfly_outputs_product_new_T_7
connect _butterfly_outputs_product_new_3, _butterfly_outputs_product_new_WIRE_3
connect _butterfly_outputs_product_this_1, _butterfly_outputs_product_new_3
wire _butterfly_outputs_product_that_1 : SInt<35>
wire _butterfly_outputs_product_new_4 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_4 : SInt<35>
node _butterfly_outputs_product_new_T_8 = asUInt(butterfly_outputs_product_out_1_1)
node _butterfly_outputs_product_new_T_9 = asSInt(_butterfly_outputs_product_new_T_8)
connect _butterfly_outputs_product_new_WIRE_4, _butterfly_outputs_product_new_T_9
connect _butterfly_outputs_product_new_4, _butterfly_outputs_product_new_WIRE_4
connect _butterfly_outputs_product_that_1, _butterfly_outputs_product_new_4
node _butterfly_outputs_product_T_3 = add(_butterfly_outputs_product_this_1, _butterfly_outputs_product_that_1)
node _butterfly_outputs_product_T_4 = tail(_butterfly_outputs_product_T_3, 1)
node _butterfly_outputs_product_T_5 = asSInt(_butterfly_outputs_product_T_4)
wire _butterfly_outputs_product_new_5 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_5 : SInt<35>
node _butterfly_outputs_product_new_T_10 = asUInt(_butterfly_outputs_product_T_5)
node _butterfly_outputs_product_new_T_11 = asSInt(_butterfly_outputs_product_new_T_10)
connect _butterfly_outputs_product_new_WIRE_5, _butterfly_outputs_product_new_T_11
connect _butterfly_outputs_product_new_5, _butterfly_outputs_product_new_WIRE_5
wire butterfly_outputs_product : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_product_result_real_new : SInt<35>
wire _butterfly_outputs_product_result_real_new_WIRE : SInt<35>
node _butterfly_outputs_product_result_real_new_T = asUInt(_butterfly_outputs_product_new_2)
node _butterfly_outputs_product_result_real_new_T_1 = asSInt(_butterfly_outputs_product_result_real_new_T)
connect _butterfly_outputs_product_result_real_new_WIRE, _butterfly_outputs_product_result_real_new_T_1
connect _butterfly_outputs_product_result_real_new, _butterfly_outputs_product_result_real_new_WIRE
connect butterfly_outputs_product.real, _butterfly_outputs_product_result_real_new
wire _butterfly_outputs_product_result_imag_new : SInt<35>
wire _butterfly_outputs_product_result_imag_new_WIRE : SInt<35>
node _butterfly_outputs_product_result_imag_new_T = asUInt(_butterfly_outputs_product_new_5)
node _butterfly_outputs_product_result_imag_new_T_1 = asSInt(_butterfly_outputs_product_result_imag_new_T)
connect _butterfly_outputs_product_result_imag_new_WIRE, _butterfly_outputs_product_result_imag_new_T_1
connect _butterfly_outputs_product_result_imag_new, _butterfly_outputs_product_result_imag_new_WIRE
connect butterfly_outputs_product.imag, _butterfly_outputs_product_result_imag_new
node _butterfly_outputs_out_T = shl(stage_outputs_0_0.real, 17)
wire butterfly_outputs_out_0 : SInt<35>
wire _butterfly_outputs_out_new_WIRE : SInt<35>
node _butterfly_outputs_out_new_T = asUInt(_butterfly_outputs_out_T)
node _butterfly_outputs_out_new_T_1 = asSInt(_butterfly_outputs_out_new_T)
connect _butterfly_outputs_out_new_WIRE, _butterfly_outputs_out_new_T_1
connect butterfly_outputs_out_0, _butterfly_outputs_out_new_WIRE
wire butterfly_outputs_out_1 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_1 : SInt<35>
node _butterfly_outputs_out_new_T_2 = asUInt(butterfly_outputs_product.real)
node _butterfly_outputs_out_new_T_3 = asSInt(_butterfly_outputs_out_new_T_2)
connect _butterfly_outputs_out_new_WIRE_1, _butterfly_outputs_out_new_T_3
connect butterfly_outputs_out_1, _butterfly_outputs_out_new_WIRE_1
wire _butterfly_outputs_this : SInt<35>
wire _butterfly_outputs_new : SInt<35>
wire _butterfly_outputs_new_WIRE : SInt<35>
node _butterfly_outputs_new_T = asUInt(butterfly_outputs_out_0)
node _butterfly_outputs_new_T_1 = asSInt(_butterfly_outputs_new_T)
connect _butterfly_outputs_new_WIRE, _butterfly_outputs_new_T_1
connect _butterfly_outputs_new, _butterfly_outputs_new_WIRE
connect _butterfly_outputs_this, _butterfly_outputs_new
wire _butterfly_outputs_that : SInt<35>
wire _butterfly_outputs_new_1 : SInt<35>
wire _butterfly_outputs_new_WIRE_1 : SInt<35>
node _butterfly_outputs_new_T_2 = asUInt(butterfly_outputs_out_1)
node _butterfly_outputs_new_T_3 = asSInt(_butterfly_outputs_new_T_2)
connect _butterfly_outputs_new_WIRE_1, _butterfly_outputs_new_T_3
connect _butterfly_outputs_new_1, _butterfly_outputs_new_WIRE_1
connect _butterfly_outputs_that, _butterfly_outputs_new_1
node _butterfly_outputs_T = add(_butterfly_outputs_this, _butterfly_outputs_that)
node _butterfly_outputs_T_1 = tail(_butterfly_outputs_T, 1)
node _butterfly_outputs_T_2 = asSInt(_butterfly_outputs_T_1)
wire _butterfly_outputs_new_2 : SInt<35>
wire _butterfly_outputs_new_WIRE_2 : SInt<35>
node _butterfly_outputs_new_T_4 = asUInt(_butterfly_outputs_T_2)
node _butterfly_outputs_new_T_5 = asSInt(_butterfly_outputs_new_T_4)
connect _butterfly_outputs_new_WIRE_2, _butterfly_outputs_new_T_5
connect _butterfly_outputs_new_2, _butterfly_outputs_new_WIRE_2
node _butterfly_outputs_out_T_1 = shl(stage_outputs_0_0.imag, 17)
wire butterfly_outputs_out_0_1 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_2 : SInt<35>
node _butterfly_outputs_out_new_T_4 = asUInt(_butterfly_outputs_out_T_1)
node _butterfly_outputs_out_new_T_5 = asSInt(_butterfly_outputs_out_new_T_4)
connect _butterfly_outputs_out_new_WIRE_2, _butterfly_outputs_out_new_T_5
connect butterfly_outputs_out_0_1, _butterfly_outputs_out_new_WIRE_2
wire butterfly_outputs_out_1_1 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_3 : SInt<35>
node _butterfly_outputs_out_new_T_6 = asUInt(butterfly_outputs_product.imag)
node _butterfly_outputs_out_new_T_7 = asSInt(_butterfly_outputs_out_new_T_6)
connect _butterfly_outputs_out_new_WIRE_3, _butterfly_outputs_out_new_T_7
connect butterfly_outputs_out_1_1, _butterfly_outputs_out_new_WIRE_3
wire _butterfly_outputs_this_1 : SInt<35>
wire _butterfly_outputs_new_3 : SInt<35>
wire _butterfly_outputs_new_WIRE_3 : SInt<35>
node _butterfly_outputs_new_T_6 = asUInt(butterfly_outputs_out_0_1)
node _butterfly_outputs_new_T_7 = asSInt(_butterfly_outputs_new_T_6)
connect _butterfly_outputs_new_WIRE_3, _butterfly_outputs_new_T_7
connect _butterfly_outputs_new_3, _butterfly_outputs_new_WIRE_3
connect _butterfly_outputs_this_1, _butterfly_outputs_new_3
wire _butterfly_outputs_that_1 : SInt<35>
wire _butterfly_outputs_new_4 : SInt<35>
wire _butterfly_outputs_new_WIRE_4 : SInt<35>
node _butterfly_outputs_new_T_8 = asUInt(butterfly_outputs_out_1_1)
node _butterfly_outputs_new_T_9 = asSInt(_butterfly_outputs_new_T_8)
connect _butterfly_outputs_new_WIRE_4, _butterfly_outputs_new_T_9
connect _butterfly_outputs_new_4, _butterfly_outputs_new_WIRE_4
connect _butterfly_outputs_that_1, _butterfly_outputs_new_4
node _butterfly_outputs_T_3 = add(_butterfly_outputs_this_1, _butterfly_outputs_that_1)
node _butterfly_outputs_T_4 = tail(_butterfly_outputs_T_3, 1)
node _butterfly_outputs_T_5 = asSInt(_butterfly_outputs_T_4)
wire _butterfly_outputs_new_5 : SInt<35>
wire _butterfly_outputs_new_WIRE_5 : SInt<35>
node _butterfly_outputs_new_T_10 = asUInt(_butterfly_outputs_T_5)
node _butterfly_outputs_new_T_11 = asSInt(_butterfly_outputs_new_T_10)
connect _butterfly_outputs_new_WIRE_5, _butterfly_outputs_new_T_11
connect _butterfly_outputs_new_5, _butterfly_outputs_new_WIRE_5
wire butterfly_outputs_0 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_result_real_new : SInt<35>
wire _butterfly_outputs_result_real_new_WIRE : SInt<35>
node _butterfly_outputs_result_real_new_T = asUInt(_butterfly_outputs_new_2)
node _butterfly_outputs_result_real_new_T_1 = asSInt(_butterfly_outputs_result_real_new_T)
connect _butterfly_outputs_result_real_new_WIRE, _butterfly_outputs_result_real_new_T_1
connect _butterfly_outputs_result_real_new, _butterfly_outputs_result_real_new_WIRE
connect butterfly_outputs_0.real, _butterfly_outputs_result_real_new
wire _butterfly_outputs_result_imag_new : SInt<35>
wire _butterfly_outputs_result_imag_new_WIRE : SInt<35>
node _butterfly_outputs_result_imag_new_T = asUInt(_butterfly_outputs_new_5)
node _butterfly_outputs_result_imag_new_T_1 = asSInt(_butterfly_outputs_result_imag_new_T)
connect _butterfly_outputs_result_imag_new_WIRE, _butterfly_outputs_result_imag_new_T_1
connect _butterfly_outputs_result_imag_new, _butterfly_outputs_result_imag_new_WIRE
connect butterfly_outputs_0.imag, _butterfly_outputs_result_imag_new
node _butterfly_outputs_out_T_2 = shl(stage_outputs_0_0.real, 17)
wire butterfly_outputs_out_0_2 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_4 : SInt<35>
node _butterfly_outputs_out_new_T_8 = asUInt(_butterfly_outputs_out_T_2)
node _butterfly_outputs_out_new_T_9 = asSInt(_butterfly_outputs_out_new_T_8)
connect _butterfly_outputs_out_new_WIRE_4, _butterfly_outputs_out_new_T_9
connect butterfly_outputs_out_0_2, _butterfly_outputs_out_new_WIRE_4
wire butterfly_outputs_out_1_2 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_5 : SInt<35>
node _butterfly_outputs_out_new_T_10 = asUInt(butterfly_outputs_product.real)
node _butterfly_outputs_out_new_T_11 = asSInt(_butterfly_outputs_out_new_T_10)
connect _butterfly_outputs_out_new_WIRE_5, _butterfly_outputs_out_new_T_11
connect butterfly_outputs_out_1_2, _butterfly_outputs_out_new_WIRE_5
wire _butterfly_outputs_this_2 : SInt<35>
wire _butterfly_outputs_new_6 : SInt<35>
wire _butterfly_outputs_new_WIRE_6 : SInt<35>
node _butterfly_outputs_new_T_12 = asUInt(butterfly_outputs_out_0_2)
node _butterfly_outputs_new_T_13 = asSInt(_butterfly_outputs_new_T_12)
connect _butterfly_outputs_new_WIRE_6, _butterfly_outputs_new_T_13
connect _butterfly_outputs_new_6, _butterfly_outputs_new_WIRE_6
connect _butterfly_outputs_this_2, _butterfly_outputs_new_6
wire _butterfly_outputs_that_2 : SInt<35>
wire _butterfly_outputs_new_7 : SInt<35>
wire _butterfly_outputs_new_WIRE_7 : SInt<35>
node _butterfly_outputs_new_T_14 = asUInt(butterfly_outputs_out_1_2)
node _butterfly_outputs_new_T_15 = asSInt(_butterfly_outputs_new_T_14)
connect _butterfly_outputs_new_WIRE_7, _butterfly_outputs_new_T_15
connect _butterfly_outputs_new_7, _butterfly_outputs_new_WIRE_7
connect _butterfly_outputs_that_2, _butterfly_outputs_new_7
node _butterfly_outputs_T_6 = sub(_butterfly_outputs_this_2, _butterfly_outputs_that_2)
node _butterfly_outputs_T_7 = tail(_butterfly_outputs_T_6, 1)
node _butterfly_outputs_T_8 = asSInt(_butterfly_outputs_T_7)
wire _butterfly_outputs_new_8 : SInt<35>
wire _butterfly_outputs_new_WIRE_8 : SInt<35>
node _butterfly_outputs_new_T_16 = asUInt(_butterfly_outputs_T_8)
node _butterfly_outputs_new_T_17 = asSInt(_butterfly_outputs_new_T_16)
connect _butterfly_outputs_new_WIRE_8, _butterfly_outputs_new_T_17
connect _butterfly_outputs_new_8, _butterfly_outputs_new_WIRE_8
node _butterfly_outputs_out_T_3 = shl(stage_outputs_0_0.imag, 17)
wire butterfly_outputs_out_0_3 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_6 : SInt<35>
node _butterfly_outputs_out_new_T_12 = asUInt(_butterfly_outputs_out_T_3)
node _butterfly_outputs_out_new_T_13 = asSInt(_butterfly_outputs_out_new_T_12)
connect _butterfly_outputs_out_new_WIRE_6, _butterfly_outputs_out_new_T_13
connect butterfly_outputs_out_0_3, _butterfly_outputs_out_new_WIRE_6
wire butterfly_outputs_out_1_3 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_7 : SInt<35>
node _butterfly_outputs_out_new_T_14 = asUInt(butterfly_outputs_product.imag)
node _butterfly_outputs_out_new_T_15 = asSInt(_butterfly_outputs_out_new_T_14)
connect _butterfly_outputs_out_new_WIRE_7, _butterfly_outputs_out_new_T_15
connect butterfly_outputs_out_1_3, _butterfly_outputs_out_new_WIRE_7
wire _butterfly_outputs_this_3 : SInt<35>
wire _butterfly_outputs_new_9 : SInt<35>
wire _butterfly_outputs_new_WIRE_9 : SInt<35>
node _butterfly_outputs_new_T_18 = asUInt(butterfly_outputs_out_0_3)
node _butterfly_outputs_new_T_19 = asSInt(_butterfly_outputs_new_T_18)
connect _butterfly_outputs_new_WIRE_9, _butterfly_outputs_new_T_19
connect _butterfly_outputs_new_9, _butterfly_outputs_new_WIRE_9
connect _butterfly_outputs_this_3, _butterfly_outputs_new_9
wire _butterfly_outputs_that_3 : SInt<35>
wire _butterfly_outputs_new_10 : SInt<35>
wire _butterfly_outputs_new_WIRE_10 : SInt<35>
node _butterfly_outputs_new_T_20 = asUInt(butterfly_outputs_out_1_3)
node _butterfly_outputs_new_T_21 = asSInt(_butterfly_outputs_new_T_20)
connect _butterfly_outputs_new_WIRE_10, _butterfly_outputs_new_T_21
connect _butterfly_outputs_new_10, _butterfly_outputs_new_WIRE_10
connect _butterfly_outputs_that_3, _butterfly_outputs_new_10
node _butterfly_outputs_T_9 = sub(_butterfly_outputs_this_3, _butterfly_outputs_that_3)
node _butterfly_outputs_T_10 = tail(_butterfly_outputs_T_9, 1)
node _butterfly_outputs_T_11 = asSInt(_butterfly_outputs_T_10)
wire _butterfly_outputs_new_11 : SInt<35>
wire _butterfly_outputs_new_WIRE_11 : SInt<35>
node _butterfly_outputs_new_T_22 = asUInt(_butterfly_outputs_T_11)
node _butterfly_outputs_new_T_23 = asSInt(_butterfly_outputs_new_T_22)
connect _butterfly_outputs_new_WIRE_11, _butterfly_outputs_new_T_23
connect _butterfly_outputs_new_11, _butterfly_outputs_new_WIRE_11
wire butterfly_outputs_1 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_result_real_new_1 : SInt<35>
wire _butterfly_outputs_result_real_new_WIRE_1 : SInt<35>
node _butterfly_outputs_result_real_new_T_2 = asUInt(_butterfly_outputs_new_8)
node _butterfly_outputs_result_real_new_T_3 = asSInt(_butterfly_outputs_result_real_new_T_2)
connect _butterfly_outputs_result_real_new_WIRE_1, _butterfly_outputs_result_real_new_T_3
connect _butterfly_outputs_result_real_new_1, _butterfly_outputs_result_real_new_WIRE_1
connect butterfly_outputs_1.real, _butterfly_outputs_result_real_new_1
wire _butterfly_outputs_result_imag_new_1 : SInt<35>
wire _butterfly_outputs_result_imag_new_WIRE_1 : SInt<35>
node _butterfly_outputs_result_imag_new_T_2 = asUInt(_butterfly_outputs_new_11)
node _butterfly_outputs_result_imag_new_T_3 = asSInt(_butterfly_outputs_result_imag_new_T_2)
connect _butterfly_outputs_result_imag_new_WIRE_1, _butterfly_outputs_result_imag_new_T_3
connect _butterfly_outputs_result_imag_new_1, _butterfly_outputs_result_imag_new_WIRE_1
connect butterfly_outputs_1.imag, _butterfly_outputs_result_imag_new_1
node _stage_outputs_1_0_stage_outputs_1_0_imag_T = shr(butterfly_outputs_0.imag, 17)
wire _stage_outputs_1_0_stage_outputs_1_0_imag_new : SInt<18>
wire _stage_outputs_1_0_stage_outputs_1_0_imag_new_WIRE : SInt<18>
node _stage_outputs_1_0_stage_outputs_1_0_imag_new_T = asUInt(_stage_outputs_1_0_stage_outputs_1_0_imag_T)
node _stage_outputs_1_0_stage_outputs_1_0_imag_new_T_1 = asSInt(_stage_outputs_1_0_stage_outputs_1_0_imag_new_T)
connect _stage_outputs_1_0_stage_outputs_1_0_imag_new_WIRE, _stage_outputs_1_0_stage_outputs_1_0_imag_new_T_1
connect _stage_outputs_1_0_stage_outputs_1_0_imag_new, _stage_outputs_1_0_stage_outputs_1_0_imag_new_WIRE
connect stage_outputs_1_0.imag, _stage_outputs_1_0_stage_outputs_1_0_imag_new
node _stage_outputs_1_0_stage_outputs_1_0_real_T = shr(butterfly_outputs_0.real, 17)
wire _stage_outputs_1_0_stage_outputs_1_0_real_new : SInt<18>
wire _stage_outputs_1_0_stage_outputs_1_0_real_new_WIRE : SInt<18>
node _stage_outputs_1_0_stage_outputs_1_0_real_new_T = asUInt(_stage_outputs_1_0_stage_outputs_1_0_real_T)
node _stage_outputs_1_0_stage_outputs_1_0_real_new_T_1 = asSInt(_stage_outputs_1_0_stage_outputs_1_0_real_new_T)
connect _stage_outputs_1_0_stage_outputs_1_0_real_new_WIRE, _stage_outputs_1_0_stage_outputs_1_0_real_new_T_1
connect _stage_outputs_1_0_stage_outputs_1_0_real_new, _stage_outputs_1_0_stage_outputs_1_0_real_new_WIRE
connect stage_outputs_1_0.real, _stage_outputs_1_0_stage_outputs_1_0_real_new
node _stage_outputs_1_4_stage_outputs_1_4_imag_T = shr(butterfly_outputs_1.imag, 17)
wire _stage_outputs_1_4_stage_outputs_1_4_imag_new : SInt<18>
wire _stage_outputs_1_4_stage_outputs_1_4_imag_new_WIRE : SInt<18>
node _stage_outputs_1_4_stage_outputs_1_4_imag_new_T = asUInt(_stage_outputs_1_4_stage_outputs_1_4_imag_T)
node _stage_outputs_1_4_stage_outputs_1_4_imag_new_T_1 = asSInt(_stage_outputs_1_4_stage_outputs_1_4_imag_new_T)
connect _stage_outputs_1_4_stage_outputs_1_4_imag_new_WIRE, _stage_outputs_1_4_stage_outputs_1_4_imag_new_T_1
connect _stage_outputs_1_4_stage_outputs_1_4_imag_new, _stage_outputs_1_4_stage_outputs_1_4_imag_new_WIRE
connect stage_outputs_1_4.imag, _stage_outputs_1_4_stage_outputs_1_4_imag_new
node _stage_outputs_1_4_stage_outputs_1_4_real_T = shr(butterfly_outputs_1.real, 17)
wire _stage_outputs_1_4_stage_outputs_1_4_real_new : SInt<18>
wire _stage_outputs_1_4_stage_outputs_1_4_real_new_WIRE : SInt<18>
node _stage_outputs_1_4_stage_outputs_1_4_real_new_T = asUInt(_stage_outputs_1_4_stage_outputs_1_4_real_T)
node _stage_outputs_1_4_stage_outputs_1_4_real_new_T_1 = asSInt(_stage_outputs_1_4_stage_outputs_1_4_real_new_T)
connect _stage_outputs_1_4_stage_outputs_1_4_real_new_WIRE, _stage_outputs_1_4_stage_outputs_1_4_real_new_T_1
connect _stage_outputs_1_4_stage_outputs_1_4_real_new, _stage_outputs_1_4_stage_outputs_1_4_real_new_WIRE
connect stage_outputs_1_4.real, _stage_outputs_1_4_stage_outputs_1_4_real_new
wire butterfly_outputs_product_c_p_d_out_0_1 : SInt<19>
wire _butterfly_outputs_product_c_p_d_out_new_WIRE_2 : SInt<19>
node _butterfly_outputs_product_c_p_d_out_new_T_4 = asUInt(twiddle[0].real)
node _butterfly_outputs_product_c_p_d_out_new_T_5 = asSInt(_butterfly_outputs_product_c_p_d_out_new_T_4)
connect _butterfly_outputs_product_c_p_d_out_new_WIRE_2, _butterfly_outputs_product_c_p_d_out_new_T_5
connect butterfly_outputs_product_c_p_d_out_0_1, _butterfly_outputs_product_c_p_d_out_new_WIRE_2
wire butterfly_outputs_product_c_p_d_out_1_1 : SInt<19>
wire _butterfly_outputs_product_c_p_d_out_new_WIRE_3 : SInt<19>
node _butterfly_outputs_product_c_p_d_out_new_T_6 = asUInt(twiddle[0].imag)
node _butterfly_outputs_product_c_p_d_out_new_T_7 = asSInt(_butterfly_outputs_product_c_p_d_out_new_T_6)
connect _butterfly_outputs_product_c_p_d_out_new_WIRE_3, _butterfly_outputs_product_c_p_d_out_new_T_7
connect butterfly_outputs_product_c_p_d_out_1_1, _butterfly_outputs_product_c_p_d_out_new_WIRE_3
wire _butterfly_outputs_product_c_p_d_this_1 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_2 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_3 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_6 = asUInt(butterfly_outputs_product_c_p_d_out_0_1)
node _butterfly_outputs_product_c_p_d_new_T_7 = asSInt(_butterfly_outputs_product_c_p_d_new_T_6)
connect _butterfly_outputs_product_c_p_d_new_WIRE_3, _butterfly_outputs_product_c_p_d_new_T_7
connect _butterfly_outputs_product_c_p_d_new_2, _butterfly_outputs_product_c_p_d_new_WIRE_3
connect _butterfly_outputs_product_c_p_d_this_1, _butterfly_outputs_product_c_p_d_new_2
wire _butterfly_outputs_product_c_p_d_that_1 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_3 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_4 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_8 = asUInt(butterfly_outputs_product_c_p_d_out_1_1)
node _butterfly_outputs_product_c_p_d_new_T_9 = asSInt(_butterfly_outputs_product_c_p_d_new_T_8)
connect _butterfly_outputs_product_c_p_d_new_WIRE_4, _butterfly_outputs_product_c_p_d_new_T_9
connect _butterfly_outputs_product_c_p_d_new_3, _butterfly_outputs_product_c_p_d_new_WIRE_4
connect _butterfly_outputs_product_c_p_d_that_1, _butterfly_outputs_product_c_p_d_new_3
node _butterfly_outputs_product_c_p_d_T_3 = add(_butterfly_outputs_product_c_p_d_this_1, _butterfly_outputs_product_c_p_d_that_1)
node _butterfly_outputs_product_c_p_d_T_4 = tail(_butterfly_outputs_product_c_p_d_T_3, 1)
node _butterfly_outputs_product_c_p_d_T_5 = asSInt(_butterfly_outputs_product_c_p_d_T_4)
wire butterfly_outputs_product_c_p_d_1 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_5 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_10 = asUInt(_butterfly_outputs_product_c_p_d_T_5)
node _butterfly_outputs_product_c_p_d_new_T_11 = asSInt(_butterfly_outputs_product_c_p_d_new_T_10)
connect _butterfly_outputs_product_c_p_d_new_WIRE_5, _butterfly_outputs_product_c_p_d_new_T_11
connect butterfly_outputs_product_c_p_d_1, _butterfly_outputs_product_c_p_d_new_WIRE_5
wire butterfly_outputs_product_a_p_b_out_0_1 : SInt<16>
wire _butterfly_outputs_product_a_p_b_out_new_WIRE_2 : SInt<16>
node _butterfly_outputs_product_a_p_b_out_new_T_4 = asUInt(stage_outputs_0_5.real)
node _butterfly_outputs_product_a_p_b_out_new_T_5 = asSInt(_butterfly_outputs_product_a_p_b_out_new_T_4)
connect _butterfly_outputs_product_a_p_b_out_new_WIRE_2, _butterfly_outputs_product_a_p_b_out_new_T_5
connect butterfly_outputs_product_a_p_b_out_0_1, _butterfly_outputs_product_a_p_b_out_new_WIRE_2
wire butterfly_outputs_product_a_p_b_out_1_1 : SInt<16>
wire _butterfly_outputs_product_a_p_b_out_new_WIRE_3 : SInt<16>
node _butterfly_outputs_product_a_p_b_out_new_T_6 = asUInt(stage_outputs_0_5.imag)
node _butterfly_outputs_product_a_p_b_out_new_T_7 = asSInt(_butterfly_outputs_product_a_p_b_out_new_T_6)
connect _butterfly_outputs_product_a_p_b_out_new_WIRE_3, _butterfly_outputs_product_a_p_b_out_new_T_7
connect butterfly_outputs_product_a_p_b_out_1_1, _butterfly_outputs_product_a_p_b_out_new_WIRE_3
wire _butterfly_outputs_product_a_p_b_this_1 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_2 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_3 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_6 = asUInt(butterfly_outputs_product_a_p_b_out_0_1)
node _butterfly_outputs_product_a_p_b_new_T_7 = asSInt(_butterfly_outputs_product_a_p_b_new_T_6)
connect _butterfly_outputs_product_a_p_b_new_WIRE_3, _butterfly_outputs_product_a_p_b_new_T_7
connect _butterfly_outputs_product_a_p_b_new_2, _butterfly_outputs_product_a_p_b_new_WIRE_3
connect _butterfly_outputs_product_a_p_b_this_1, _butterfly_outputs_product_a_p_b_new_2
wire _butterfly_outputs_product_a_p_b_that_1 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_3 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_4 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_8 = asUInt(butterfly_outputs_product_a_p_b_out_1_1)
node _butterfly_outputs_product_a_p_b_new_T_9 = asSInt(_butterfly_outputs_product_a_p_b_new_T_8)
connect _butterfly_outputs_product_a_p_b_new_WIRE_4, _butterfly_outputs_product_a_p_b_new_T_9
connect _butterfly_outputs_product_a_p_b_new_3, _butterfly_outputs_product_a_p_b_new_WIRE_4
connect _butterfly_outputs_product_a_p_b_that_1, _butterfly_outputs_product_a_p_b_new_3
node _butterfly_outputs_product_a_p_b_T_3 = add(_butterfly_outputs_product_a_p_b_this_1, _butterfly_outputs_product_a_p_b_that_1)
node _butterfly_outputs_product_a_p_b_T_4 = tail(_butterfly_outputs_product_a_p_b_T_3, 1)
node _butterfly_outputs_product_a_p_b_T_5 = asSInt(_butterfly_outputs_product_a_p_b_T_4)
wire butterfly_outputs_product_a_p_b_1 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_5 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_10 = asUInt(_butterfly_outputs_product_a_p_b_T_5)
node _butterfly_outputs_product_a_p_b_new_T_11 = asSInt(_butterfly_outputs_product_a_p_b_new_T_10)
connect _butterfly_outputs_product_a_p_b_new_WIRE_5, _butterfly_outputs_product_a_p_b_new_T_11
connect butterfly_outputs_product_a_p_b_1, _butterfly_outputs_product_a_p_b_new_WIRE_5
wire butterfly_outputs_product_b_m_a_out_0_1 : SInt<16>
wire _butterfly_outputs_product_b_m_a_out_new_WIRE_2 : SInt<16>
node _butterfly_outputs_product_b_m_a_out_new_T_4 = asUInt(stage_outputs_0_5.imag)
node _butterfly_outputs_product_b_m_a_out_new_T_5 = asSInt(_butterfly_outputs_product_b_m_a_out_new_T_4)
connect _butterfly_outputs_product_b_m_a_out_new_WIRE_2, _butterfly_outputs_product_b_m_a_out_new_T_5
connect butterfly_outputs_product_b_m_a_out_0_1, _butterfly_outputs_product_b_m_a_out_new_WIRE_2
wire butterfly_outputs_product_b_m_a_out_1_1 : SInt<16>
wire _butterfly_outputs_product_b_m_a_out_new_WIRE_3 : SInt<16>
node _butterfly_outputs_product_b_m_a_out_new_T_6 = asUInt(stage_outputs_0_5.real)
node _butterfly_outputs_product_b_m_a_out_new_T_7 = asSInt(_butterfly_outputs_product_b_m_a_out_new_T_6)
connect _butterfly_outputs_product_b_m_a_out_new_WIRE_3, _butterfly_outputs_product_b_m_a_out_new_T_7
connect butterfly_outputs_product_b_m_a_out_1_1, _butterfly_outputs_product_b_m_a_out_new_WIRE_3
wire _butterfly_outputs_product_b_m_a_this_1 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_2 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_3 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_6 = asUInt(butterfly_outputs_product_b_m_a_out_0_1)
node _butterfly_outputs_product_b_m_a_new_T_7 = asSInt(_butterfly_outputs_product_b_m_a_new_T_6)
connect _butterfly_outputs_product_b_m_a_new_WIRE_3, _butterfly_outputs_product_b_m_a_new_T_7
connect _butterfly_outputs_product_b_m_a_new_2, _butterfly_outputs_product_b_m_a_new_WIRE_3
connect _butterfly_outputs_product_b_m_a_this_1, _butterfly_outputs_product_b_m_a_new_2
wire _butterfly_outputs_product_b_m_a_that_1 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_3 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_4 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_8 = asUInt(butterfly_outputs_product_b_m_a_out_1_1)
node _butterfly_outputs_product_b_m_a_new_T_9 = asSInt(_butterfly_outputs_product_b_m_a_new_T_8)
connect _butterfly_outputs_product_b_m_a_new_WIRE_4, _butterfly_outputs_product_b_m_a_new_T_9
connect _butterfly_outputs_product_b_m_a_new_3, _butterfly_outputs_product_b_m_a_new_WIRE_4
connect _butterfly_outputs_product_b_m_a_that_1, _butterfly_outputs_product_b_m_a_new_3
node _butterfly_outputs_product_b_m_a_T_3 = sub(_butterfly_outputs_product_b_m_a_this_1, _butterfly_outputs_product_b_m_a_that_1)
node _butterfly_outputs_product_b_m_a_T_4 = tail(_butterfly_outputs_product_b_m_a_T_3, 1)
node _butterfly_outputs_product_b_m_a_T_5 = asSInt(_butterfly_outputs_product_b_m_a_T_4)
wire butterfly_outputs_product_b_m_a_1 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_5 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_10 = asUInt(_butterfly_outputs_product_b_m_a_T_5)
node _butterfly_outputs_product_b_m_a_new_T_11 = asSInt(_butterfly_outputs_product_b_m_a_new_T_10)
connect _butterfly_outputs_product_b_m_a_new_WIRE_5, _butterfly_outputs_product_b_m_a_new_T_11
connect butterfly_outputs_product_b_m_a_1, _butterfly_outputs_product_b_m_a_new_WIRE_5
node _butterfly_outputs_product_ac_p_ad_T_1 = mul(stage_outputs_0_5.real, butterfly_outputs_product_c_p_d_1)
wire butterfly_outputs_product_ac_p_ad_1 : SInt<35>
wire _butterfly_outputs_product_ac_p_ad_new_WIRE_1 : SInt<35>
node _butterfly_outputs_product_ac_p_ad_new_T_2 = asUInt(_butterfly_outputs_product_ac_p_ad_T_1)
node _butterfly_outputs_product_ac_p_ad_new_T_3 = asSInt(_butterfly_outputs_product_ac_p_ad_new_T_2)
connect _butterfly_outputs_product_ac_p_ad_new_WIRE_1, _butterfly_outputs_product_ac_p_ad_new_T_3
connect butterfly_outputs_product_ac_p_ad_1, _butterfly_outputs_product_ac_p_ad_new_WIRE_1
node _butterfly_outputs_product_ad_p_bd_T_1 = mul(butterfly_outputs_product_a_p_b_1, twiddle[0].imag)
wire butterfly_outputs_product_ad_p_bd_1 : SInt<35>
wire _butterfly_outputs_product_ad_p_bd_new_WIRE_1 : SInt<35>
node _butterfly_outputs_product_ad_p_bd_new_T_2 = asUInt(_butterfly_outputs_product_ad_p_bd_T_1)
node _butterfly_outputs_product_ad_p_bd_new_T_3 = asSInt(_butterfly_outputs_product_ad_p_bd_new_T_2)
connect _butterfly_outputs_product_ad_p_bd_new_WIRE_1, _butterfly_outputs_product_ad_p_bd_new_T_3
connect butterfly_outputs_product_ad_p_bd_1, _butterfly_outputs_product_ad_p_bd_new_WIRE_1
node _butterfly_outputs_product_bc_m_ac_T_1 = mul(butterfly_outputs_product_b_m_a_1, twiddle[0].real)
wire butterfly_outputs_product_bc_m_ac_1 : SInt<35>
wire _butterfly_outputs_product_bc_m_ac_new_WIRE_1 : SInt<35>
node _butterfly_outputs_product_bc_m_ac_new_T_2 = asUInt(_butterfly_outputs_product_bc_m_ac_T_1)
node _butterfly_outputs_product_bc_m_ac_new_T_3 = asSInt(_butterfly_outputs_product_bc_m_ac_new_T_2)
connect _butterfly_outputs_product_bc_m_ac_new_WIRE_1, _butterfly_outputs_product_bc_m_ac_new_T_3
connect butterfly_outputs_product_bc_m_ac_1, _butterfly_outputs_product_bc_m_ac_new_WIRE_1
wire butterfly_outputs_product_out_0_2 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_4 : SInt<35>
node _butterfly_outputs_product_out_new_T_8 = asUInt(butterfly_outputs_product_ac_p_ad_1)
node _butterfly_outputs_product_out_new_T_9 = asSInt(_butterfly_outputs_product_out_new_T_8)
connect _butterfly_outputs_product_out_new_WIRE_4, _butterfly_outputs_product_out_new_T_9
connect butterfly_outputs_product_out_0_2, _butterfly_outputs_product_out_new_WIRE_4
wire butterfly_outputs_product_out_1_2 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_5 : SInt<35>
node _butterfly_outputs_product_out_new_T_10 = asUInt(butterfly_outputs_product_ad_p_bd_1)
node _butterfly_outputs_product_out_new_T_11 = asSInt(_butterfly_outputs_product_out_new_T_10)
connect _butterfly_outputs_product_out_new_WIRE_5, _butterfly_outputs_product_out_new_T_11
connect butterfly_outputs_product_out_1_2, _butterfly_outputs_product_out_new_WIRE_5
wire _butterfly_outputs_product_this_2 : SInt<35>
wire _butterfly_outputs_product_new_6 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_6 : SInt<35>
node _butterfly_outputs_product_new_T_12 = asUInt(butterfly_outputs_product_out_0_2)
node _butterfly_outputs_product_new_T_13 = asSInt(_butterfly_outputs_product_new_T_12)
connect _butterfly_outputs_product_new_WIRE_6, _butterfly_outputs_product_new_T_13
connect _butterfly_outputs_product_new_6, _butterfly_outputs_product_new_WIRE_6
connect _butterfly_outputs_product_this_2, _butterfly_outputs_product_new_6
wire _butterfly_outputs_product_that_2 : SInt<35>
wire _butterfly_outputs_product_new_7 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_7 : SInt<35>
node _butterfly_outputs_product_new_T_14 = asUInt(butterfly_outputs_product_out_1_2)
node _butterfly_outputs_product_new_T_15 = asSInt(_butterfly_outputs_product_new_T_14)
connect _butterfly_outputs_product_new_WIRE_7, _butterfly_outputs_product_new_T_15
connect _butterfly_outputs_product_new_7, _butterfly_outputs_product_new_WIRE_7
connect _butterfly_outputs_product_that_2, _butterfly_outputs_product_new_7
node _butterfly_outputs_product_T_6 = sub(_butterfly_outputs_product_this_2, _butterfly_outputs_product_that_2)
node _butterfly_outputs_product_T_7 = tail(_butterfly_outputs_product_T_6, 1)
node _butterfly_outputs_product_T_8 = asSInt(_butterfly_outputs_product_T_7)
wire _butterfly_outputs_product_new_8 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_8 : SInt<35>
node _butterfly_outputs_product_new_T_16 = asUInt(_butterfly_outputs_product_T_8)
node _butterfly_outputs_product_new_T_17 = asSInt(_butterfly_outputs_product_new_T_16)
connect _butterfly_outputs_product_new_WIRE_8, _butterfly_outputs_product_new_T_17
connect _butterfly_outputs_product_new_8, _butterfly_outputs_product_new_WIRE_8
wire butterfly_outputs_product_out_0_3 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_6 : SInt<35>
node _butterfly_outputs_product_out_new_T_12 = asUInt(butterfly_outputs_product_ac_p_ad_1)
node _butterfly_outputs_product_out_new_T_13 = asSInt(_butterfly_outputs_product_out_new_T_12)
connect _butterfly_outputs_product_out_new_WIRE_6, _butterfly_outputs_product_out_new_T_13
connect butterfly_outputs_product_out_0_3, _butterfly_outputs_product_out_new_WIRE_6
wire butterfly_outputs_product_out_1_3 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_7 : SInt<35>
node _butterfly_outputs_product_out_new_T_14 = asUInt(butterfly_outputs_product_bc_m_ac_1)
node _butterfly_outputs_product_out_new_T_15 = asSInt(_butterfly_outputs_product_out_new_T_14)
connect _butterfly_outputs_product_out_new_WIRE_7, _butterfly_outputs_product_out_new_T_15
connect butterfly_outputs_product_out_1_3, _butterfly_outputs_product_out_new_WIRE_7
wire _butterfly_outputs_product_this_3 : SInt<35>
wire _butterfly_outputs_product_new_9 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_9 : SInt<35>
node _butterfly_outputs_product_new_T_18 = asUInt(butterfly_outputs_product_out_0_3)
node _butterfly_outputs_product_new_T_19 = asSInt(_butterfly_outputs_product_new_T_18)
connect _butterfly_outputs_product_new_WIRE_9, _butterfly_outputs_product_new_T_19
connect _butterfly_outputs_product_new_9, _butterfly_outputs_product_new_WIRE_9
connect _butterfly_outputs_product_this_3, _butterfly_outputs_product_new_9
wire _butterfly_outputs_product_that_3 : SInt<35>
wire _butterfly_outputs_product_new_10 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_10 : SInt<35>
node _butterfly_outputs_product_new_T_20 = asUInt(butterfly_outputs_product_out_1_3)
node _butterfly_outputs_product_new_T_21 = asSInt(_butterfly_outputs_product_new_T_20)
connect _butterfly_outputs_product_new_WIRE_10, _butterfly_outputs_product_new_T_21
connect _butterfly_outputs_product_new_10, _butterfly_outputs_product_new_WIRE_10
connect _butterfly_outputs_product_that_3, _butterfly_outputs_product_new_10
node _butterfly_outputs_product_T_9 = add(_butterfly_outputs_product_this_3, _butterfly_outputs_product_that_3)
node _butterfly_outputs_product_T_10 = tail(_butterfly_outputs_product_T_9, 1)
node _butterfly_outputs_product_T_11 = asSInt(_butterfly_outputs_product_T_10)
wire _butterfly_outputs_product_new_11 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_11 : SInt<35>
node _butterfly_outputs_product_new_T_22 = asUInt(_butterfly_outputs_product_T_11)
node _butterfly_outputs_product_new_T_23 = asSInt(_butterfly_outputs_product_new_T_22)
connect _butterfly_outputs_product_new_WIRE_11, _butterfly_outputs_product_new_T_23
connect _butterfly_outputs_product_new_11, _butterfly_outputs_product_new_WIRE_11
wire butterfly_outputs_product_1 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_product_result_real_new_1 : SInt<35>
wire _butterfly_outputs_product_result_real_new_WIRE_1 : SInt<35>
node _butterfly_outputs_product_result_real_new_T_2 = asUInt(_butterfly_outputs_product_new_8)
node _butterfly_outputs_product_result_real_new_T_3 = asSInt(_butterfly_outputs_product_result_real_new_T_2)
connect _butterfly_outputs_product_result_real_new_WIRE_1, _butterfly_outputs_product_result_real_new_T_3
connect _butterfly_outputs_product_result_real_new_1, _butterfly_outputs_product_result_real_new_WIRE_1
connect butterfly_outputs_product_1.real, _butterfly_outputs_product_result_real_new_1
wire _butterfly_outputs_product_result_imag_new_1 : SInt<35>
wire _butterfly_outputs_product_result_imag_new_WIRE_1 : SInt<35>
node _butterfly_outputs_product_result_imag_new_T_2 = asUInt(_butterfly_outputs_product_new_11)
node _butterfly_outputs_product_result_imag_new_T_3 = asSInt(_butterfly_outputs_product_result_imag_new_T_2)
connect _butterfly_outputs_product_result_imag_new_WIRE_1, _butterfly_outputs_product_result_imag_new_T_3
connect _butterfly_outputs_product_result_imag_new_1, _butterfly_outputs_product_result_imag_new_WIRE_1
connect butterfly_outputs_product_1.imag, _butterfly_outputs_product_result_imag_new_1
node _butterfly_outputs_out_T_4 = shl(stage_outputs_0_1.real, 17)
wire butterfly_outputs_out_0_4 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_8 : SInt<35>
node _butterfly_outputs_out_new_T_16 = asUInt(_butterfly_outputs_out_T_4)
node _butterfly_outputs_out_new_T_17 = asSInt(_butterfly_outputs_out_new_T_16)
connect _butterfly_outputs_out_new_WIRE_8, _butterfly_outputs_out_new_T_17
connect butterfly_outputs_out_0_4, _butterfly_outputs_out_new_WIRE_8
wire butterfly_outputs_out_1_4 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_9 : SInt<35>
node _butterfly_outputs_out_new_T_18 = asUInt(butterfly_outputs_product_1.real)
node _butterfly_outputs_out_new_T_19 = asSInt(_butterfly_outputs_out_new_T_18)
connect _butterfly_outputs_out_new_WIRE_9, _butterfly_outputs_out_new_T_19
connect butterfly_outputs_out_1_4, _butterfly_outputs_out_new_WIRE_9
wire _butterfly_outputs_this_4 : SInt<35>
wire _butterfly_outputs_new_12 : SInt<35>
wire _butterfly_outputs_new_WIRE_12 : SInt<35>
node _butterfly_outputs_new_T_24 = asUInt(butterfly_outputs_out_0_4)
node _butterfly_outputs_new_T_25 = asSInt(_butterfly_outputs_new_T_24)
connect _butterfly_outputs_new_WIRE_12, _butterfly_outputs_new_T_25
connect _butterfly_outputs_new_12, _butterfly_outputs_new_WIRE_12
connect _butterfly_outputs_this_4, _butterfly_outputs_new_12
wire _butterfly_outputs_that_4 : SInt<35>
wire _butterfly_outputs_new_13 : SInt<35>
wire _butterfly_outputs_new_WIRE_13 : SInt<35>
node _butterfly_outputs_new_T_26 = asUInt(butterfly_outputs_out_1_4)
node _butterfly_outputs_new_T_27 = asSInt(_butterfly_outputs_new_T_26)
connect _butterfly_outputs_new_WIRE_13, _butterfly_outputs_new_T_27
connect _butterfly_outputs_new_13, _butterfly_outputs_new_WIRE_13
connect _butterfly_outputs_that_4, _butterfly_outputs_new_13
node _butterfly_outputs_T_12 = add(_butterfly_outputs_this_4, _butterfly_outputs_that_4)
node _butterfly_outputs_T_13 = tail(_butterfly_outputs_T_12, 1)
node _butterfly_outputs_T_14 = asSInt(_butterfly_outputs_T_13)
wire _butterfly_outputs_new_14 : SInt<35>
wire _butterfly_outputs_new_WIRE_14 : SInt<35>
node _butterfly_outputs_new_T_28 = asUInt(_butterfly_outputs_T_14)
node _butterfly_outputs_new_T_29 = asSInt(_butterfly_outputs_new_T_28)
connect _butterfly_outputs_new_WIRE_14, _butterfly_outputs_new_T_29
connect _butterfly_outputs_new_14, _butterfly_outputs_new_WIRE_14
node _butterfly_outputs_out_T_5 = shl(stage_outputs_0_1.imag, 17)
wire butterfly_outputs_out_0_5 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_10 : SInt<35>
node _butterfly_outputs_out_new_T_20 = asUInt(_butterfly_outputs_out_T_5)
node _butterfly_outputs_out_new_T_21 = asSInt(_butterfly_outputs_out_new_T_20)
connect _butterfly_outputs_out_new_WIRE_10, _butterfly_outputs_out_new_T_21
connect butterfly_outputs_out_0_5, _butterfly_outputs_out_new_WIRE_10
wire butterfly_outputs_out_1_5 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_11 : SInt<35>
node _butterfly_outputs_out_new_T_22 = asUInt(butterfly_outputs_product_1.imag)
node _butterfly_outputs_out_new_T_23 = asSInt(_butterfly_outputs_out_new_T_22)
connect _butterfly_outputs_out_new_WIRE_11, _butterfly_outputs_out_new_T_23
connect butterfly_outputs_out_1_5, _butterfly_outputs_out_new_WIRE_11
wire _butterfly_outputs_this_5 : SInt<35>
wire _butterfly_outputs_new_15 : SInt<35>
wire _butterfly_outputs_new_WIRE_15 : SInt<35>
node _butterfly_outputs_new_T_30 = asUInt(butterfly_outputs_out_0_5)
node _butterfly_outputs_new_T_31 = asSInt(_butterfly_outputs_new_T_30)
connect _butterfly_outputs_new_WIRE_15, _butterfly_outputs_new_T_31
connect _butterfly_outputs_new_15, _butterfly_outputs_new_WIRE_15
connect _butterfly_outputs_this_5, _butterfly_outputs_new_15
wire _butterfly_outputs_that_5 : SInt<35>
wire _butterfly_outputs_new_16 : SInt<35>
wire _butterfly_outputs_new_WIRE_16 : SInt<35>
node _butterfly_outputs_new_T_32 = asUInt(butterfly_outputs_out_1_5)
node _butterfly_outputs_new_T_33 = asSInt(_butterfly_outputs_new_T_32)
connect _butterfly_outputs_new_WIRE_16, _butterfly_outputs_new_T_33
connect _butterfly_outputs_new_16, _butterfly_outputs_new_WIRE_16
connect _butterfly_outputs_that_5, _butterfly_outputs_new_16
node _butterfly_outputs_T_15 = add(_butterfly_outputs_this_5, _butterfly_outputs_that_5)
node _butterfly_outputs_T_16 = tail(_butterfly_outputs_T_15, 1)
node _butterfly_outputs_T_17 = asSInt(_butterfly_outputs_T_16)
wire _butterfly_outputs_new_17 : SInt<35>
wire _butterfly_outputs_new_WIRE_17 : SInt<35>
node _butterfly_outputs_new_T_34 = asUInt(_butterfly_outputs_T_17)
node _butterfly_outputs_new_T_35 = asSInt(_butterfly_outputs_new_T_34)
connect _butterfly_outputs_new_WIRE_17, _butterfly_outputs_new_T_35
connect _butterfly_outputs_new_17, _butterfly_outputs_new_WIRE_17
wire butterfly_outputs_0_1 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_result_real_new_2 : SInt<35>
wire _butterfly_outputs_result_real_new_WIRE_2 : SInt<35>
node _butterfly_outputs_result_real_new_T_4 = asUInt(_butterfly_outputs_new_14)
node _butterfly_outputs_result_real_new_T_5 = asSInt(_butterfly_outputs_result_real_new_T_4)
connect _butterfly_outputs_result_real_new_WIRE_2, _butterfly_outputs_result_real_new_T_5
connect _butterfly_outputs_result_real_new_2, _butterfly_outputs_result_real_new_WIRE_2
connect butterfly_outputs_0_1.real, _butterfly_outputs_result_real_new_2
wire _butterfly_outputs_result_imag_new_2 : SInt<35>
wire _butterfly_outputs_result_imag_new_WIRE_2 : SInt<35>
node _butterfly_outputs_result_imag_new_T_4 = asUInt(_butterfly_outputs_new_17)
node _butterfly_outputs_result_imag_new_T_5 = asSInt(_butterfly_outputs_result_imag_new_T_4)
connect _butterfly_outputs_result_imag_new_WIRE_2, _butterfly_outputs_result_imag_new_T_5
connect _butterfly_outputs_result_imag_new_2, _butterfly_outputs_result_imag_new_WIRE_2
connect butterfly_outputs_0_1.imag, _butterfly_outputs_result_imag_new_2
node _butterfly_outputs_out_T_6 = shl(stage_outputs_0_1.real, 17)
wire butterfly_outputs_out_0_6 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_12 : SInt<35>
node _butterfly_outputs_out_new_T_24 = asUInt(_butterfly_outputs_out_T_6)
node _butterfly_outputs_out_new_T_25 = asSInt(_butterfly_outputs_out_new_T_24)
connect _butterfly_outputs_out_new_WIRE_12, _butterfly_outputs_out_new_T_25
connect butterfly_outputs_out_0_6, _butterfly_outputs_out_new_WIRE_12
wire butterfly_outputs_out_1_6 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_13 : SInt<35>
node _butterfly_outputs_out_new_T_26 = asUInt(butterfly_outputs_product_1.real)
node _butterfly_outputs_out_new_T_27 = asSInt(_butterfly_outputs_out_new_T_26)
connect _butterfly_outputs_out_new_WIRE_13, _butterfly_outputs_out_new_T_27
connect butterfly_outputs_out_1_6, _butterfly_outputs_out_new_WIRE_13
wire _butterfly_outputs_this_6 : SInt<35>
wire _butterfly_outputs_new_18 : SInt<35>
wire _butterfly_outputs_new_WIRE_18 : SInt<35>
node _butterfly_outputs_new_T_36 = asUInt(butterfly_outputs_out_0_6)
node _butterfly_outputs_new_T_37 = asSInt(_butterfly_outputs_new_T_36)
connect _butterfly_outputs_new_WIRE_18, _butterfly_outputs_new_T_37
connect _butterfly_outputs_new_18, _butterfly_outputs_new_WIRE_18
connect _butterfly_outputs_this_6, _butterfly_outputs_new_18
wire _butterfly_outputs_that_6 : SInt<35>
wire _butterfly_outputs_new_19 : SInt<35>
wire _butterfly_outputs_new_WIRE_19 : SInt<35>
node _butterfly_outputs_new_T_38 = asUInt(butterfly_outputs_out_1_6)
node _butterfly_outputs_new_T_39 = asSInt(_butterfly_outputs_new_T_38)
connect _butterfly_outputs_new_WIRE_19, _butterfly_outputs_new_T_39
connect _butterfly_outputs_new_19, _butterfly_outputs_new_WIRE_19
connect _butterfly_outputs_that_6, _butterfly_outputs_new_19
node _butterfly_outputs_T_18 = sub(_butterfly_outputs_this_6, _butterfly_outputs_that_6)
node _butterfly_outputs_T_19 = tail(_butterfly_outputs_T_18, 1)
node _butterfly_outputs_T_20 = asSInt(_butterfly_outputs_T_19)
wire _butterfly_outputs_new_20 : SInt<35>
wire _butterfly_outputs_new_WIRE_20 : SInt<35>
node _butterfly_outputs_new_T_40 = asUInt(_butterfly_outputs_T_20)
node _butterfly_outputs_new_T_41 = asSInt(_butterfly_outputs_new_T_40)
connect _butterfly_outputs_new_WIRE_20, _butterfly_outputs_new_T_41
connect _butterfly_outputs_new_20, _butterfly_outputs_new_WIRE_20
node _butterfly_outputs_out_T_7 = shl(stage_outputs_0_1.imag, 17)
wire butterfly_outputs_out_0_7 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_14 : SInt<35>
node _butterfly_outputs_out_new_T_28 = asUInt(_butterfly_outputs_out_T_7)
node _butterfly_outputs_out_new_T_29 = asSInt(_butterfly_outputs_out_new_T_28)
connect _butterfly_outputs_out_new_WIRE_14, _butterfly_outputs_out_new_T_29
connect butterfly_outputs_out_0_7, _butterfly_outputs_out_new_WIRE_14
wire butterfly_outputs_out_1_7 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_15 : SInt<35>
node _butterfly_outputs_out_new_T_30 = asUInt(butterfly_outputs_product_1.imag)
node _butterfly_outputs_out_new_T_31 = asSInt(_butterfly_outputs_out_new_T_30)
connect _butterfly_outputs_out_new_WIRE_15, _butterfly_outputs_out_new_T_31
connect butterfly_outputs_out_1_7, _butterfly_outputs_out_new_WIRE_15
wire _butterfly_outputs_this_7 : SInt<35>
wire _butterfly_outputs_new_21 : SInt<35>
wire _butterfly_outputs_new_WIRE_21 : SInt<35>
node _butterfly_outputs_new_T_42 = asUInt(butterfly_outputs_out_0_7)
node _butterfly_outputs_new_T_43 = asSInt(_butterfly_outputs_new_T_42)
connect _butterfly_outputs_new_WIRE_21, _butterfly_outputs_new_T_43
connect _butterfly_outputs_new_21, _butterfly_outputs_new_WIRE_21
connect _butterfly_outputs_this_7, _butterfly_outputs_new_21
wire _butterfly_outputs_that_7 : SInt<35>
wire _butterfly_outputs_new_22 : SInt<35>
wire _butterfly_outputs_new_WIRE_22 : SInt<35>
node _butterfly_outputs_new_T_44 = asUInt(butterfly_outputs_out_1_7)
node _butterfly_outputs_new_T_45 = asSInt(_butterfly_outputs_new_T_44)
connect _butterfly_outputs_new_WIRE_22, _butterfly_outputs_new_T_45
connect _butterfly_outputs_new_22, _butterfly_outputs_new_WIRE_22
connect _butterfly_outputs_that_7, _butterfly_outputs_new_22
node _butterfly_outputs_T_21 = sub(_butterfly_outputs_this_7, _butterfly_outputs_that_7)
node _butterfly_outputs_T_22 = tail(_butterfly_outputs_T_21, 1)
node _butterfly_outputs_T_23 = asSInt(_butterfly_outputs_T_22)
wire _butterfly_outputs_new_23 : SInt<35>
wire _butterfly_outputs_new_WIRE_23 : SInt<35>
node _butterfly_outputs_new_T_46 = asUInt(_butterfly_outputs_T_23)
node _butterfly_outputs_new_T_47 = asSInt(_butterfly_outputs_new_T_46)
connect _butterfly_outputs_new_WIRE_23, _butterfly_outputs_new_T_47
connect _butterfly_outputs_new_23, _butterfly_outputs_new_WIRE_23
wire butterfly_outputs_1_1 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_result_real_new_3 : SInt<35>
wire _butterfly_outputs_result_real_new_WIRE_3 : SInt<35>
node _butterfly_outputs_result_real_new_T_6 = asUInt(_butterfly_outputs_new_20)
node _butterfly_outputs_result_real_new_T_7 = asSInt(_butterfly_outputs_result_real_new_T_6)
connect _butterfly_outputs_result_real_new_WIRE_3, _butterfly_outputs_result_real_new_T_7
connect _butterfly_outputs_result_real_new_3, _butterfly_outputs_result_real_new_WIRE_3
connect butterfly_outputs_1_1.real, _butterfly_outputs_result_real_new_3
wire _butterfly_outputs_result_imag_new_3 : SInt<35>
wire _butterfly_outputs_result_imag_new_WIRE_3 : SInt<35>
node _butterfly_outputs_result_imag_new_T_6 = asUInt(_butterfly_outputs_new_23)
node _butterfly_outputs_result_imag_new_T_7 = asSInt(_butterfly_outputs_result_imag_new_T_6)
connect _butterfly_outputs_result_imag_new_WIRE_3, _butterfly_outputs_result_imag_new_T_7
connect _butterfly_outputs_result_imag_new_3, _butterfly_outputs_result_imag_new_WIRE_3
connect butterfly_outputs_1_1.imag, _butterfly_outputs_result_imag_new_3
node _stage_outputs_1_1_stage_outputs_1_1_imag_T = shr(butterfly_outputs_0_1.imag, 17)
wire _stage_outputs_1_1_stage_outputs_1_1_imag_new : SInt<18>
wire _stage_outputs_1_1_stage_outputs_1_1_imag_new_WIRE : SInt<18>
node _stage_outputs_1_1_stage_outputs_1_1_imag_new_T = asUInt(_stage_outputs_1_1_stage_outputs_1_1_imag_T)
node _stage_outputs_1_1_stage_outputs_1_1_imag_new_T_1 = asSInt(_stage_outputs_1_1_stage_outputs_1_1_imag_new_T)
connect _stage_outputs_1_1_stage_outputs_1_1_imag_new_WIRE, _stage_outputs_1_1_stage_outputs_1_1_imag_new_T_1
connect _stage_outputs_1_1_stage_outputs_1_1_imag_new, _stage_outputs_1_1_stage_outputs_1_1_imag_new_WIRE
connect stage_outputs_1_1.imag, _stage_outputs_1_1_stage_outputs_1_1_imag_new
node _stage_outputs_1_1_stage_outputs_1_1_real_T = shr(butterfly_outputs_0_1.real, 17)
wire _stage_outputs_1_1_stage_outputs_1_1_real_new : SInt<18>
wire _stage_outputs_1_1_stage_outputs_1_1_real_new_WIRE : SInt<18>
node _stage_outputs_1_1_stage_outputs_1_1_real_new_T = asUInt(_stage_outputs_1_1_stage_outputs_1_1_real_T)
node _stage_outputs_1_1_stage_outputs_1_1_real_new_T_1 = asSInt(_stage_outputs_1_1_stage_outputs_1_1_real_new_T)
connect _stage_outputs_1_1_stage_outputs_1_1_real_new_WIRE, _stage_outputs_1_1_stage_outputs_1_1_real_new_T_1
connect _stage_outputs_1_1_stage_outputs_1_1_real_new, _stage_outputs_1_1_stage_outputs_1_1_real_new_WIRE
connect stage_outputs_1_1.real, _stage_outputs_1_1_stage_outputs_1_1_real_new
node _stage_outputs_1_5_stage_outputs_1_5_imag_T = shr(butterfly_outputs_1_1.imag, 17)
wire _stage_outputs_1_5_stage_outputs_1_5_imag_new : SInt<18>
wire _stage_outputs_1_5_stage_outputs_1_5_imag_new_WIRE : SInt<18>
node _stage_outputs_1_5_stage_outputs_1_5_imag_new_T = asUInt(_stage_outputs_1_5_stage_outputs_1_5_imag_T)
node _stage_outputs_1_5_stage_outputs_1_5_imag_new_T_1 = asSInt(_stage_outputs_1_5_stage_outputs_1_5_imag_new_T)
connect _stage_outputs_1_5_stage_outputs_1_5_imag_new_WIRE, _stage_outputs_1_5_stage_outputs_1_5_imag_new_T_1
connect _stage_outputs_1_5_stage_outputs_1_5_imag_new, _stage_outputs_1_5_stage_outputs_1_5_imag_new_WIRE
connect stage_outputs_1_5.imag, _stage_outputs_1_5_stage_outputs_1_5_imag_new
node _stage_outputs_1_5_stage_outputs_1_5_real_T = shr(butterfly_outputs_1_1.real, 17)
wire _stage_outputs_1_5_stage_outputs_1_5_real_new : SInt<18>
wire _stage_outputs_1_5_stage_outputs_1_5_real_new_WIRE : SInt<18>
node _stage_outputs_1_5_stage_outputs_1_5_real_new_T = asUInt(_stage_outputs_1_5_stage_outputs_1_5_real_T)
node _stage_outputs_1_5_stage_outputs_1_5_real_new_T_1 = asSInt(_stage_outputs_1_5_stage_outputs_1_5_real_new_T)
connect _stage_outputs_1_5_stage_outputs_1_5_real_new_WIRE, _stage_outputs_1_5_stage_outputs_1_5_real_new_T_1
connect _stage_outputs_1_5_stage_outputs_1_5_real_new, _stage_outputs_1_5_stage_outputs_1_5_real_new_WIRE
connect stage_outputs_1_5.real, _stage_outputs_1_5_stage_outputs_1_5_real_new
wire butterfly_outputs_product_c_p_d_out_0_2 : SInt<19>
wire _butterfly_outputs_product_c_p_d_out_new_WIRE_4 : SInt<19>
node _butterfly_outputs_product_c_p_d_out_new_T_8 = asUInt(twiddle[0].real)
node _butterfly_outputs_product_c_p_d_out_new_T_9 = asSInt(_butterfly_outputs_product_c_p_d_out_new_T_8)
connect _butterfly_outputs_product_c_p_d_out_new_WIRE_4, _butterfly_outputs_product_c_p_d_out_new_T_9
connect butterfly_outputs_product_c_p_d_out_0_2, _butterfly_outputs_product_c_p_d_out_new_WIRE_4
wire butterfly_outputs_product_c_p_d_out_1_2 : SInt<19>
wire _butterfly_outputs_product_c_p_d_out_new_WIRE_5 : SInt<19>
node _butterfly_outputs_product_c_p_d_out_new_T_10 = asUInt(twiddle[0].imag)
node _butterfly_outputs_product_c_p_d_out_new_T_11 = asSInt(_butterfly_outputs_product_c_p_d_out_new_T_10)
connect _butterfly_outputs_product_c_p_d_out_new_WIRE_5, _butterfly_outputs_product_c_p_d_out_new_T_11
connect butterfly_outputs_product_c_p_d_out_1_2, _butterfly_outputs_product_c_p_d_out_new_WIRE_5
wire _butterfly_outputs_product_c_p_d_this_2 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_4 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_6 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_12 = asUInt(butterfly_outputs_product_c_p_d_out_0_2)
node _butterfly_outputs_product_c_p_d_new_T_13 = asSInt(_butterfly_outputs_product_c_p_d_new_T_12)
connect _butterfly_outputs_product_c_p_d_new_WIRE_6, _butterfly_outputs_product_c_p_d_new_T_13
connect _butterfly_outputs_product_c_p_d_new_4, _butterfly_outputs_product_c_p_d_new_WIRE_6
connect _butterfly_outputs_product_c_p_d_this_2, _butterfly_outputs_product_c_p_d_new_4
wire _butterfly_outputs_product_c_p_d_that_2 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_5 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_7 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_14 = asUInt(butterfly_outputs_product_c_p_d_out_1_2)
node _butterfly_outputs_product_c_p_d_new_T_15 = asSInt(_butterfly_outputs_product_c_p_d_new_T_14)
connect _butterfly_outputs_product_c_p_d_new_WIRE_7, _butterfly_outputs_product_c_p_d_new_T_15
connect _butterfly_outputs_product_c_p_d_new_5, _butterfly_outputs_product_c_p_d_new_WIRE_7
connect _butterfly_outputs_product_c_p_d_that_2, _butterfly_outputs_product_c_p_d_new_5
node _butterfly_outputs_product_c_p_d_T_6 = add(_butterfly_outputs_product_c_p_d_this_2, _butterfly_outputs_product_c_p_d_that_2)
node _butterfly_outputs_product_c_p_d_T_7 = tail(_butterfly_outputs_product_c_p_d_T_6, 1)
node _butterfly_outputs_product_c_p_d_T_8 = asSInt(_butterfly_outputs_product_c_p_d_T_7)
wire butterfly_outputs_product_c_p_d_2 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_8 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_16 = asUInt(_butterfly_outputs_product_c_p_d_T_8)
node _butterfly_outputs_product_c_p_d_new_T_17 = asSInt(_butterfly_outputs_product_c_p_d_new_T_16)
connect _butterfly_outputs_product_c_p_d_new_WIRE_8, _butterfly_outputs_product_c_p_d_new_T_17
connect butterfly_outputs_product_c_p_d_2, _butterfly_outputs_product_c_p_d_new_WIRE_8
wire butterfly_outputs_product_a_p_b_out_0_2 : SInt<16>
wire _butterfly_outputs_product_a_p_b_out_new_WIRE_4 : SInt<16>
node _butterfly_outputs_product_a_p_b_out_new_T_8 = asUInt(stage_outputs_0_6.real)
node _butterfly_outputs_product_a_p_b_out_new_T_9 = asSInt(_butterfly_outputs_product_a_p_b_out_new_T_8)
connect _butterfly_outputs_product_a_p_b_out_new_WIRE_4, _butterfly_outputs_product_a_p_b_out_new_T_9
connect butterfly_outputs_product_a_p_b_out_0_2, _butterfly_outputs_product_a_p_b_out_new_WIRE_4
wire butterfly_outputs_product_a_p_b_out_1_2 : SInt<16>
wire _butterfly_outputs_product_a_p_b_out_new_WIRE_5 : SInt<16>
node _butterfly_outputs_product_a_p_b_out_new_T_10 = asUInt(stage_outputs_0_6.imag)
node _butterfly_outputs_product_a_p_b_out_new_T_11 = asSInt(_butterfly_outputs_product_a_p_b_out_new_T_10)
connect _butterfly_outputs_product_a_p_b_out_new_WIRE_5, _butterfly_outputs_product_a_p_b_out_new_T_11
connect butterfly_outputs_product_a_p_b_out_1_2, _butterfly_outputs_product_a_p_b_out_new_WIRE_5
wire _butterfly_outputs_product_a_p_b_this_2 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_4 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_6 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_12 = asUInt(butterfly_outputs_product_a_p_b_out_0_2)
node _butterfly_outputs_product_a_p_b_new_T_13 = asSInt(_butterfly_outputs_product_a_p_b_new_T_12)
connect _butterfly_outputs_product_a_p_b_new_WIRE_6, _butterfly_outputs_product_a_p_b_new_T_13
connect _butterfly_outputs_product_a_p_b_new_4, _butterfly_outputs_product_a_p_b_new_WIRE_6
connect _butterfly_outputs_product_a_p_b_this_2, _butterfly_outputs_product_a_p_b_new_4
wire _butterfly_outputs_product_a_p_b_that_2 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_5 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_7 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_14 = asUInt(butterfly_outputs_product_a_p_b_out_1_2)
node _butterfly_outputs_product_a_p_b_new_T_15 = asSInt(_butterfly_outputs_product_a_p_b_new_T_14)
connect _butterfly_outputs_product_a_p_b_new_WIRE_7, _butterfly_outputs_product_a_p_b_new_T_15
connect _butterfly_outputs_product_a_p_b_new_5, _butterfly_outputs_product_a_p_b_new_WIRE_7
connect _butterfly_outputs_product_a_p_b_that_2, _butterfly_outputs_product_a_p_b_new_5
node _butterfly_outputs_product_a_p_b_T_6 = add(_butterfly_outputs_product_a_p_b_this_2, _butterfly_outputs_product_a_p_b_that_2)
node _butterfly_outputs_product_a_p_b_T_7 = tail(_butterfly_outputs_product_a_p_b_T_6, 1)
node _butterfly_outputs_product_a_p_b_T_8 = asSInt(_butterfly_outputs_product_a_p_b_T_7)
wire butterfly_outputs_product_a_p_b_2 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_8 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_16 = asUInt(_butterfly_outputs_product_a_p_b_T_8)
node _butterfly_outputs_product_a_p_b_new_T_17 = asSInt(_butterfly_outputs_product_a_p_b_new_T_16)
connect _butterfly_outputs_product_a_p_b_new_WIRE_8, _butterfly_outputs_product_a_p_b_new_T_17
connect butterfly_outputs_product_a_p_b_2, _butterfly_outputs_product_a_p_b_new_WIRE_8
wire butterfly_outputs_product_b_m_a_out_0_2 : SInt<16>
wire _butterfly_outputs_product_b_m_a_out_new_WIRE_4 : SInt<16>
node _butterfly_outputs_product_b_m_a_out_new_T_8 = asUInt(stage_outputs_0_6.imag)
node _butterfly_outputs_product_b_m_a_out_new_T_9 = asSInt(_butterfly_outputs_product_b_m_a_out_new_T_8)
connect _butterfly_outputs_product_b_m_a_out_new_WIRE_4, _butterfly_outputs_product_b_m_a_out_new_T_9
connect butterfly_outputs_product_b_m_a_out_0_2, _butterfly_outputs_product_b_m_a_out_new_WIRE_4
wire butterfly_outputs_product_b_m_a_out_1_2 : SInt<16>
wire _butterfly_outputs_product_b_m_a_out_new_WIRE_5 : SInt<16>
node _butterfly_outputs_product_b_m_a_out_new_T_10 = asUInt(stage_outputs_0_6.real)
node _butterfly_outputs_product_b_m_a_out_new_T_11 = asSInt(_butterfly_outputs_product_b_m_a_out_new_T_10)
connect _butterfly_outputs_product_b_m_a_out_new_WIRE_5, _butterfly_outputs_product_b_m_a_out_new_T_11
connect butterfly_outputs_product_b_m_a_out_1_2, _butterfly_outputs_product_b_m_a_out_new_WIRE_5
wire _butterfly_outputs_product_b_m_a_this_2 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_4 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_6 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_12 = asUInt(butterfly_outputs_product_b_m_a_out_0_2)
node _butterfly_outputs_product_b_m_a_new_T_13 = asSInt(_butterfly_outputs_product_b_m_a_new_T_12)
connect _butterfly_outputs_product_b_m_a_new_WIRE_6, _butterfly_outputs_product_b_m_a_new_T_13
connect _butterfly_outputs_product_b_m_a_new_4, _butterfly_outputs_product_b_m_a_new_WIRE_6
connect _butterfly_outputs_product_b_m_a_this_2, _butterfly_outputs_product_b_m_a_new_4
wire _butterfly_outputs_product_b_m_a_that_2 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_5 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_7 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_14 = asUInt(butterfly_outputs_product_b_m_a_out_1_2)
node _butterfly_outputs_product_b_m_a_new_T_15 = asSInt(_butterfly_outputs_product_b_m_a_new_T_14)
connect _butterfly_outputs_product_b_m_a_new_WIRE_7, _butterfly_outputs_product_b_m_a_new_T_15
connect _butterfly_outputs_product_b_m_a_new_5, _butterfly_outputs_product_b_m_a_new_WIRE_7
connect _butterfly_outputs_product_b_m_a_that_2, _butterfly_outputs_product_b_m_a_new_5
node _butterfly_outputs_product_b_m_a_T_6 = sub(_butterfly_outputs_product_b_m_a_this_2, _butterfly_outputs_product_b_m_a_that_2)
node _butterfly_outputs_product_b_m_a_T_7 = tail(_butterfly_outputs_product_b_m_a_T_6, 1)
node _butterfly_outputs_product_b_m_a_T_8 = asSInt(_butterfly_outputs_product_b_m_a_T_7)
wire butterfly_outputs_product_b_m_a_2 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_8 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_16 = asUInt(_butterfly_outputs_product_b_m_a_T_8)
node _butterfly_outputs_product_b_m_a_new_T_17 = asSInt(_butterfly_outputs_product_b_m_a_new_T_16)
connect _butterfly_outputs_product_b_m_a_new_WIRE_8, _butterfly_outputs_product_b_m_a_new_T_17
connect butterfly_outputs_product_b_m_a_2, _butterfly_outputs_product_b_m_a_new_WIRE_8
node _butterfly_outputs_product_ac_p_ad_T_2 = mul(stage_outputs_0_6.real, butterfly_outputs_product_c_p_d_2)
wire butterfly_outputs_product_ac_p_ad_2 : SInt<35>
wire _butterfly_outputs_product_ac_p_ad_new_WIRE_2 : SInt<35>
node _butterfly_outputs_product_ac_p_ad_new_T_4 = asUInt(_butterfly_outputs_product_ac_p_ad_T_2)
node _butterfly_outputs_product_ac_p_ad_new_T_5 = asSInt(_butterfly_outputs_product_ac_p_ad_new_T_4)
connect _butterfly_outputs_product_ac_p_ad_new_WIRE_2, _butterfly_outputs_product_ac_p_ad_new_T_5
connect butterfly_outputs_product_ac_p_ad_2, _butterfly_outputs_product_ac_p_ad_new_WIRE_2
node _butterfly_outputs_product_ad_p_bd_T_2 = mul(butterfly_outputs_product_a_p_b_2, twiddle[0].imag)
wire butterfly_outputs_product_ad_p_bd_2 : SInt<35>
wire _butterfly_outputs_product_ad_p_bd_new_WIRE_2 : SInt<35>
node _butterfly_outputs_product_ad_p_bd_new_T_4 = asUInt(_butterfly_outputs_product_ad_p_bd_T_2)
node _butterfly_outputs_product_ad_p_bd_new_T_5 = asSInt(_butterfly_outputs_product_ad_p_bd_new_T_4)
connect _butterfly_outputs_product_ad_p_bd_new_WIRE_2, _butterfly_outputs_product_ad_p_bd_new_T_5
connect butterfly_outputs_product_ad_p_bd_2, _butterfly_outputs_product_ad_p_bd_new_WIRE_2
node _butterfly_outputs_product_bc_m_ac_T_2 = mul(butterfly_outputs_product_b_m_a_2, twiddle[0].real)
wire butterfly_outputs_product_bc_m_ac_2 : SInt<35>
wire _butterfly_outputs_product_bc_m_ac_new_WIRE_2 : SInt<35>
node _butterfly_outputs_product_bc_m_ac_new_T_4 = asUInt(_butterfly_outputs_product_bc_m_ac_T_2)
node _butterfly_outputs_product_bc_m_ac_new_T_5 = asSInt(_butterfly_outputs_product_bc_m_ac_new_T_4)
connect _butterfly_outputs_product_bc_m_ac_new_WIRE_2, _butterfly_outputs_product_bc_m_ac_new_T_5
connect butterfly_outputs_product_bc_m_ac_2, _butterfly_outputs_product_bc_m_ac_new_WIRE_2
wire butterfly_outputs_product_out_0_4 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_8 : SInt<35>
node _butterfly_outputs_product_out_new_T_16 = asUInt(butterfly_outputs_product_ac_p_ad_2)
node _butterfly_outputs_product_out_new_T_17 = asSInt(_butterfly_outputs_product_out_new_T_16)
connect _butterfly_outputs_product_out_new_WIRE_8, _butterfly_outputs_product_out_new_T_17
connect butterfly_outputs_product_out_0_4, _butterfly_outputs_product_out_new_WIRE_8
wire butterfly_outputs_product_out_1_4 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_9 : SInt<35>
node _butterfly_outputs_product_out_new_T_18 = asUInt(butterfly_outputs_product_ad_p_bd_2)
node _butterfly_outputs_product_out_new_T_19 = asSInt(_butterfly_outputs_product_out_new_T_18)
connect _butterfly_outputs_product_out_new_WIRE_9, _butterfly_outputs_product_out_new_T_19
connect butterfly_outputs_product_out_1_4, _butterfly_outputs_product_out_new_WIRE_9
wire _butterfly_outputs_product_this_4 : SInt<35>
wire _butterfly_outputs_product_new_12 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_12 : SInt<35>
node _butterfly_outputs_product_new_T_24 = asUInt(butterfly_outputs_product_out_0_4)
node _butterfly_outputs_product_new_T_25 = asSInt(_butterfly_outputs_product_new_T_24)
connect _butterfly_outputs_product_new_WIRE_12, _butterfly_outputs_product_new_T_25
connect _butterfly_outputs_product_new_12, _butterfly_outputs_product_new_WIRE_12
connect _butterfly_outputs_product_this_4, _butterfly_outputs_product_new_12
wire _butterfly_outputs_product_that_4 : SInt<35>
wire _butterfly_outputs_product_new_13 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_13 : SInt<35>
node _butterfly_outputs_product_new_T_26 = asUInt(butterfly_outputs_product_out_1_4)
node _butterfly_outputs_product_new_T_27 = asSInt(_butterfly_outputs_product_new_T_26)
connect _butterfly_outputs_product_new_WIRE_13, _butterfly_outputs_product_new_T_27
connect _butterfly_outputs_product_new_13, _butterfly_outputs_product_new_WIRE_13
connect _butterfly_outputs_product_that_4, _butterfly_outputs_product_new_13
node _butterfly_outputs_product_T_12 = sub(_butterfly_outputs_product_this_4, _butterfly_outputs_product_that_4)
node _butterfly_outputs_product_T_13 = tail(_butterfly_outputs_product_T_12, 1)
node _butterfly_outputs_product_T_14 = asSInt(_butterfly_outputs_product_T_13)
wire _butterfly_outputs_product_new_14 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_14 : SInt<35>
node _butterfly_outputs_product_new_T_28 = asUInt(_butterfly_outputs_product_T_14)
node _butterfly_outputs_product_new_T_29 = asSInt(_butterfly_outputs_product_new_T_28)
connect _butterfly_outputs_product_new_WIRE_14, _butterfly_outputs_product_new_T_29
connect _butterfly_outputs_product_new_14, _butterfly_outputs_product_new_WIRE_14
wire butterfly_outputs_product_out_0_5 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_10 : SInt<35>
node _butterfly_outputs_product_out_new_T_20 = asUInt(butterfly_outputs_product_ac_p_ad_2)
node _butterfly_outputs_product_out_new_T_21 = asSInt(_butterfly_outputs_product_out_new_T_20)
connect _butterfly_outputs_product_out_new_WIRE_10, _butterfly_outputs_product_out_new_T_21
connect butterfly_outputs_product_out_0_5, _butterfly_outputs_product_out_new_WIRE_10
wire butterfly_outputs_product_out_1_5 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_11 : SInt<35>
node _butterfly_outputs_product_out_new_T_22 = asUInt(butterfly_outputs_product_bc_m_ac_2)
node _butterfly_outputs_product_out_new_T_23 = asSInt(_butterfly_outputs_product_out_new_T_22)
connect _butterfly_outputs_product_out_new_WIRE_11, _butterfly_outputs_product_out_new_T_23
connect butterfly_outputs_product_out_1_5, _butterfly_outputs_product_out_new_WIRE_11
wire _butterfly_outputs_product_this_5 : SInt<35>
wire _butterfly_outputs_product_new_15 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_15 : SInt<35>
node _butterfly_outputs_product_new_T_30 = asUInt(butterfly_outputs_product_out_0_5)
node _butterfly_outputs_product_new_T_31 = asSInt(_butterfly_outputs_product_new_T_30)
connect _butterfly_outputs_product_new_WIRE_15, _butterfly_outputs_product_new_T_31
connect _butterfly_outputs_product_new_15, _butterfly_outputs_product_new_WIRE_15
connect _butterfly_outputs_product_this_5, _butterfly_outputs_product_new_15
wire _butterfly_outputs_product_that_5 : SInt<35>
wire _butterfly_outputs_product_new_16 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_16 : SInt<35>
node _butterfly_outputs_product_new_T_32 = asUInt(butterfly_outputs_product_out_1_5)
node _butterfly_outputs_product_new_T_33 = asSInt(_butterfly_outputs_product_new_T_32)
connect _butterfly_outputs_product_new_WIRE_16, _butterfly_outputs_product_new_T_33
connect _butterfly_outputs_product_new_16, _butterfly_outputs_product_new_WIRE_16
connect _butterfly_outputs_product_that_5, _butterfly_outputs_product_new_16
node _butterfly_outputs_product_T_15 = add(_butterfly_outputs_product_this_5, _butterfly_outputs_product_that_5)
node _butterfly_outputs_product_T_16 = tail(_butterfly_outputs_product_T_15, 1)
node _butterfly_outputs_product_T_17 = asSInt(_butterfly_outputs_product_T_16)
wire _butterfly_outputs_product_new_17 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_17 : SInt<35>
node _butterfly_outputs_product_new_T_34 = asUInt(_butterfly_outputs_product_T_17)
node _butterfly_outputs_product_new_T_35 = asSInt(_butterfly_outputs_product_new_T_34)
connect _butterfly_outputs_product_new_WIRE_17, _butterfly_outputs_product_new_T_35
connect _butterfly_outputs_product_new_17, _butterfly_outputs_product_new_WIRE_17
wire butterfly_outputs_product_2 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_product_result_real_new_2 : SInt<35>
wire _butterfly_outputs_product_result_real_new_WIRE_2 : SInt<35>
node _butterfly_outputs_product_result_real_new_T_4 = asUInt(_butterfly_outputs_product_new_14)
node _butterfly_outputs_product_result_real_new_T_5 = asSInt(_butterfly_outputs_product_result_real_new_T_4)
connect _butterfly_outputs_product_result_real_new_WIRE_2, _butterfly_outputs_product_result_real_new_T_5
connect _butterfly_outputs_product_result_real_new_2, _butterfly_outputs_product_result_real_new_WIRE_2
connect butterfly_outputs_product_2.real, _butterfly_outputs_product_result_real_new_2
wire _butterfly_outputs_product_result_imag_new_2 : SInt<35>
wire _butterfly_outputs_product_result_imag_new_WIRE_2 : SInt<35>
node _butterfly_outputs_product_result_imag_new_T_4 = asUInt(_butterfly_outputs_product_new_17)
node _butterfly_outputs_product_result_imag_new_T_5 = asSInt(_butterfly_outputs_product_result_imag_new_T_4)
connect _butterfly_outputs_product_result_imag_new_WIRE_2, _butterfly_outputs_product_result_imag_new_T_5
connect _butterfly_outputs_product_result_imag_new_2, _butterfly_outputs_product_result_imag_new_WIRE_2
connect butterfly_outputs_product_2.imag, _butterfly_outputs_product_result_imag_new_2
node _butterfly_outputs_out_T_8 = shl(stage_outputs_0_2.real, 17)
wire butterfly_outputs_out_0_8 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_16 : SInt<35>
node _butterfly_outputs_out_new_T_32 = asUInt(_butterfly_outputs_out_T_8)
node _butterfly_outputs_out_new_T_33 = asSInt(_butterfly_outputs_out_new_T_32)
connect _butterfly_outputs_out_new_WIRE_16, _butterfly_outputs_out_new_T_33
connect butterfly_outputs_out_0_8, _butterfly_outputs_out_new_WIRE_16
wire butterfly_outputs_out_1_8 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_17 : SInt<35>
node _butterfly_outputs_out_new_T_34 = asUInt(butterfly_outputs_product_2.real)
node _butterfly_outputs_out_new_T_35 = asSInt(_butterfly_outputs_out_new_T_34)
connect _butterfly_outputs_out_new_WIRE_17, _butterfly_outputs_out_new_T_35
connect butterfly_outputs_out_1_8, _butterfly_outputs_out_new_WIRE_17
wire _butterfly_outputs_this_8 : SInt<35>
wire _butterfly_outputs_new_24 : SInt<35>
wire _butterfly_outputs_new_WIRE_24 : SInt<35>
node _butterfly_outputs_new_T_48 = asUInt(butterfly_outputs_out_0_8)
node _butterfly_outputs_new_T_49 = asSInt(_butterfly_outputs_new_T_48)
connect _butterfly_outputs_new_WIRE_24, _butterfly_outputs_new_T_49
connect _butterfly_outputs_new_24, _butterfly_outputs_new_WIRE_24
connect _butterfly_outputs_this_8, _butterfly_outputs_new_24
wire _butterfly_outputs_that_8 : SInt<35>
wire _butterfly_outputs_new_25 : SInt<35>
wire _butterfly_outputs_new_WIRE_25 : SInt<35>
node _butterfly_outputs_new_T_50 = asUInt(butterfly_outputs_out_1_8)
node _butterfly_outputs_new_T_51 = asSInt(_butterfly_outputs_new_T_50)
connect _butterfly_outputs_new_WIRE_25, _butterfly_outputs_new_T_51
connect _butterfly_outputs_new_25, _butterfly_outputs_new_WIRE_25
connect _butterfly_outputs_that_8, _butterfly_outputs_new_25
node _butterfly_outputs_T_24 = add(_butterfly_outputs_this_8, _butterfly_outputs_that_8)
node _butterfly_outputs_T_25 = tail(_butterfly_outputs_T_24, 1)
node _butterfly_outputs_T_26 = asSInt(_butterfly_outputs_T_25)
wire _butterfly_outputs_new_26 : SInt<35>
wire _butterfly_outputs_new_WIRE_26 : SInt<35>
node _butterfly_outputs_new_T_52 = asUInt(_butterfly_outputs_T_26)
node _butterfly_outputs_new_T_53 = asSInt(_butterfly_outputs_new_T_52)
connect _butterfly_outputs_new_WIRE_26, _butterfly_outputs_new_T_53
connect _butterfly_outputs_new_26, _butterfly_outputs_new_WIRE_26
node _butterfly_outputs_out_T_9 = shl(stage_outputs_0_2.imag, 17)
wire butterfly_outputs_out_0_9 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_18 : SInt<35>
node _butterfly_outputs_out_new_T_36 = asUInt(_butterfly_outputs_out_T_9)
node _butterfly_outputs_out_new_T_37 = asSInt(_butterfly_outputs_out_new_T_36)
connect _butterfly_outputs_out_new_WIRE_18, _butterfly_outputs_out_new_T_37
connect butterfly_outputs_out_0_9, _butterfly_outputs_out_new_WIRE_18
wire butterfly_outputs_out_1_9 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_19 : SInt<35>
node _butterfly_outputs_out_new_T_38 = asUInt(butterfly_outputs_product_2.imag)
node _butterfly_outputs_out_new_T_39 = asSInt(_butterfly_outputs_out_new_T_38)
connect _butterfly_outputs_out_new_WIRE_19, _butterfly_outputs_out_new_T_39
connect butterfly_outputs_out_1_9, _butterfly_outputs_out_new_WIRE_19
wire _butterfly_outputs_this_9 : SInt<35>
wire _butterfly_outputs_new_27 : SInt<35>
wire _butterfly_outputs_new_WIRE_27 : SInt<35>
node _butterfly_outputs_new_T_54 = asUInt(butterfly_outputs_out_0_9)
node _butterfly_outputs_new_T_55 = asSInt(_butterfly_outputs_new_T_54)
connect _butterfly_outputs_new_WIRE_27, _butterfly_outputs_new_T_55
connect _butterfly_outputs_new_27, _butterfly_outputs_new_WIRE_27
connect _butterfly_outputs_this_9, _butterfly_outputs_new_27
wire _butterfly_outputs_that_9 : SInt<35>
wire _butterfly_outputs_new_28 : SInt<35>
wire _butterfly_outputs_new_WIRE_28 : SInt<35>
node _butterfly_outputs_new_T_56 = asUInt(butterfly_outputs_out_1_9)
node _butterfly_outputs_new_T_57 = asSInt(_butterfly_outputs_new_T_56)
connect _butterfly_outputs_new_WIRE_28, _butterfly_outputs_new_T_57
connect _butterfly_outputs_new_28, _butterfly_outputs_new_WIRE_28
connect _butterfly_outputs_that_9, _butterfly_outputs_new_28
node _butterfly_outputs_T_27 = add(_butterfly_outputs_this_9, _butterfly_outputs_that_9)
node _butterfly_outputs_T_28 = tail(_butterfly_outputs_T_27, 1)
node _butterfly_outputs_T_29 = asSInt(_butterfly_outputs_T_28)
wire _butterfly_outputs_new_29 : SInt<35>
wire _butterfly_outputs_new_WIRE_29 : SInt<35>
node _butterfly_outputs_new_T_58 = asUInt(_butterfly_outputs_T_29)
node _butterfly_outputs_new_T_59 = asSInt(_butterfly_outputs_new_T_58)
connect _butterfly_outputs_new_WIRE_29, _butterfly_outputs_new_T_59
connect _butterfly_outputs_new_29, _butterfly_outputs_new_WIRE_29
wire butterfly_outputs_0_2 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_result_real_new_4 : SInt<35>
wire _butterfly_outputs_result_real_new_WIRE_4 : SInt<35>
node _butterfly_outputs_result_real_new_T_8 = asUInt(_butterfly_outputs_new_26)
node _butterfly_outputs_result_real_new_T_9 = asSInt(_butterfly_outputs_result_real_new_T_8)
connect _butterfly_outputs_result_real_new_WIRE_4, _butterfly_outputs_result_real_new_T_9
connect _butterfly_outputs_result_real_new_4, _butterfly_outputs_result_real_new_WIRE_4
connect butterfly_outputs_0_2.real, _butterfly_outputs_result_real_new_4
wire _butterfly_outputs_result_imag_new_4 : SInt<35>
wire _butterfly_outputs_result_imag_new_WIRE_4 : SInt<35>
node _butterfly_outputs_result_imag_new_T_8 = asUInt(_butterfly_outputs_new_29)
node _butterfly_outputs_result_imag_new_T_9 = asSInt(_butterfly_outputs_result_imag_new_T_8)
connect _butterfly_outputs_result_imag_new_WIRE_4, _butterfly_outputs_result_imag_new_T_9
connect _butterfly_outputs_result_imag_new_4, _butterfly_outputs_result_imag_new_WIRE_4
connect butterfly_outputs_0_2.imag, _butterfly_outputs_result_imag_new_4
node _butterfly_outputs_out_T_10 = shl(stage_outputs_0_2.real, 17)
wire butterfly_outputs_out_0_10 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_20 : SInt<35>
node _butterfly_outputs_out_new_T_40 = asUInt(_butterfly_outputs_out_T_10)
node _butterfly_outputs_out_new_T_41 = asSInt(_butterfly_outputs_out_new_T_40)
connect _butterfly_outputs_out_new_WIRE_20, _butterfly_outputs_out_new_T_41
connect butterfly_outputs_out_0_10, _butterfly_outputs_out_new_WIRE_20
wire butterfly_outputs_out_1_10 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_21 : SInt<35>
node _butterfly_outputs_out_new_T_42 = asUInt(butterfly_outputs_product_2.real)
node _butterfly_outputs_out_new_T_43 = asSInt(_butterfly_outputs_out_new_T_42)
connect _butterfly_outputs_out_new_WIRE_21, _butterfly_outputs_out_new_T_43
connect butterfly_outputs_out_1_10, _butterfly_outputs_out_new_WIRE_21
wire _butterfly_outputs_this_10 : SInt<35>
wire _butterfly_outputs_new_30 : SInt<35>
wire _butterfly_outputs_new_WIRE_30 : SInt<35>
node _butterfly_outputs_new_T_60 = asUInt(butterfly_outputs_out_0_10)
node _butterfly_outputs_new_T_61 = asSInt(_butterfly_outputs_new_T_60)
connect _butterfly_outputs_new_WIRE_30, _butterfly_outputs_new_T_61
connect _butterfly_outputs_new_30, _butterfly_outputs_new_WIRE_30
connect _butterfly_outputs_this_10, _butterfly_outputs_new_30
wire _butterfly_outputs_that_10 : SInt<35>
wire _butterfly_outputs_new_31 : SInt<35>
wire _butterfly_outputs_new_WIRE_31 : SInt<35>
node _butterfly_outputs_new_T_62 = asUInt(butterfly_outputs_out_1_10)
node _butterfly_outputs_new_T_63 = asSInt(_butterfly_outputs_new_T_62)
connect _butterfly_outputs_new_WIRE_31, _butterfly_outputs_new_T_63
connect _butterfly_outputs_new_31, _butterfly_outputs_new_WIRE_31
connect _butterfly_outputs_that_10, _butterfly_outputs_new_31
node _butterfly_outputs_T_30 = sub(_butterfly_outputs_this_10, _butterfly_outputs_that_10)
node _butterfly_outputs_T_31 = tail(_butterfly_outputs_T_30, 1)
node _butterfly_outputs_T_32 = asSInt(_butterfly_outputs_T_31)
wire _butterfly_outputs_new_32 : SInt<35>
wire _butterfly_outputs_new_WIRE_32 : SInt<35>
node _butterfly_outputs_new_T_64 = asUInt(_butterfly_outputs_T_32)
node _butterfly_outputs_new_T_65 = asSInt(_butterfly_outputs_new_T_64)
connect _butterfly_outputs_new_WIRE_32, _butterfly_outputs_new_T_65
connect _butterfly_outputs_new_32, _butterfly_outputs_new_WIRE_32
node _butterfly_outputs_out_T_11 = shl(stage_outputs_0_2.imag, 17)
wire butterfly_outputs_out_0_11 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_22 : SInt<35>
node _butterfly_outputs_out_new_T_44 = asUInt(_butterfly_outputs_out_T_11)
node _butterfly_outputs_out_new_T_45 = asSInt(_butterfly_outputs_out_new_T_44)
connect _butterfly_outputs_out_new_WIRE_22, _butterfly_outputs_out_new_T_45
connect butterfly_outputs_out_0_11, _butterfly_outputs_out_new_WIRE_22
wire butterfly_outputs_out_1_11 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_23 : SInt<35>
node _butterfly_outputs_out_new_T_46 = asUInt(butterfly_outputs_product_2.imag)
node _butterfly_outputs_out_new_T_47 = asSInt(_butterfly_outputs_out_new_T_46)
connect _butterfly_outputs_out_new_WIRE_23, _butterfly_outputs_out_new_T_47
connect butterfly_outputs_out_1_11, _butterfly_outputs_out_new_WIRE_23
wire _butterfly_outputs_this_11 : SInt<35>
wire _butterfly_outputs_new_33 : SInt<35>
wire _butterfly_outputs_new_WIRE_33 : SInt<35>
node _butterfly_outputs_new_T_66 = asUInt(butterfly_outputs_out_0_11)
node _butterfly_outputs_new_T_67 = asSInt(_butterfly_outputs_new_T_66)
connect _butterfly_outputs_new_WIRE_33, _butterfly_outputs_new_T_67
connect _butterfly_outputs_new_33, _butterfly_outputs_new_WIRE_33
connect _butterfly_outputs_this_11, _butterfly_outputs_new_33
wire _butterfly_outputs_that_11 : SInt<35>
wire _butterfly_outputs_new_34 : SInt<35>
wire _butterfly_outputs_new_WIRE_34 : SInt<35>
node _butterfly_outputs_new_T_68 = asUInt(butterfly_outputs_out_1_11)
node _butterfly_outputs_new_T_69 = asSInt(_butterfly_outputs_new_T_68)
connect _butterfly_outputs_new_WIRE_34, _butterfly_outputs_new_T_69
connect _butterfly_outputs_new_34, _butterfly_outputs_new_WIRE_34
connect _butterfly_outputs_that_11, _butterfly_outputs_new_34
node _butterfly_outputs_T_33 = sub(_butterfly_outputs_this_11, _butterfly_outputs_that_11)
node _butterfly_outputs_T_34 = tail(_butterfly_outputs_T_33, 1)
node _butterfly_outputs_T_35 = asSInt(_butterfly_outputs_T_34)
wire _butterfly_outputs_new_35 : SInt<35>
wire _butterfly_outputs_new_WIRE_35 : SInt<35>
node _butterfly_outputs_new_T_70 = asUInt(_butterfly_outputs_T_35)
node _butterfly_outputs_new_T_71 = asSInt(_butterfly_outputs_new_T_70)
connect _butterfly_outputs_new_WIRE_35, _butterfly_outputs_new_T_71
connect _butterfly_outputs_new_35, _butterfly_outputs_new_WIRE_35
wire butterfly_outputs_1_2 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_result_real_new_5 : SInt<35>
wire _butterfly_outputs_result_real_new_WIRE_5 : SInt<35>
node _butterfly_outputs_result_real_new_T_10 = asUInt(_butterfly_outputs_new_32)
node _butterfly_outputs_result_real_new_T_11 = asSInt(_butterfly_outputs_result_real_new_T_10)
connect _butterfly_outputs_result_real_new_WIRE_5, _butterfly_outputs_result_real_new_T_11
connect _butterfly_outputs_result_real_new_5, _butterfly_outputs_result_real_new_WIRE_5
connect butterfly_outputs_1_2.real, _butterfly_outputs_result_real_new_5
wire _butterfly_outputs_result_imag_new_5 : SInt<35>
wire _butterfly_outputs_result_imag_new_WIRE_5 : SInt<35>
node _butterfly_outputs_result_imag_new_T_10 = asUInt(_butterfly_outputs_new_35)
node _butterfly_outputs_result_imag_new_T_11 = asSInt(_butterfly_outputs_result_imag_new_T_10)
connect _butterfly_outputs_result_imag_new_WIRE_5, _butterfly_outputs_result_imag_new_T_11
connect _butterfly_outputs_result_imag_new_5, _butterfly_outputs_result_imag_new_WIRE_5
connect butterfly_outputs_1_2.imag, _butterfly_outputs_result_imag_new_5
node _stage_outputs_1_2_stage_outputs_1_2_imag_T = shr(butterfly_outputs_0_2.imag, 17)
wire _stage_outputs_1_2_stage_outputs_1_2_imag_new : SInt<18>
wire _stage_outputs_1_2_stage_outputs_1_2_imag_new_WIRE : SInt<18>
node _stage_outputs_1_2_stage_outputs_1_2_imag_new_T = asUInt(_stage_outputs_1_2_stage_outputs_1_2_imag_T)
node _stage_outputs_1_2_stage_outputs_1_2_imag_new_T_1 = asSInt(_stage_outputs_1_2_stage_outputs_1_2_imag_new_T)
connect _stage_outputs_1_2_stage_outputs_1_2_imag_new_WIRE, _stage_outputs_1_2_stage_outputs_1_2_imag_new_T_1
connect _stage_outputs_1_2_stage_outputs_1_2_imag_new, _stage_outputs_1_2_stage_outputs_1_2_imag_new_WIRE
connect stage_outputs_1_2.imag, _stage_outputs_1_2_stage_outputs_1_2_imag_new
node _stage_outputs_1_2_stage_outputs_1_2_real_T = shr(butterfly_outputs_0_2.real, 17)
wire _stage_outputs_1_2_stage_outputs_1_2_real_new : SInt<18>
wire _stage_outputs_1_2_stage_outputs_1_2_real_new_WIRE : SInt<18>
node _stage_outputs_1_2_stage_outputs_1_2_real_new_T = asUInt(_stage_outputs_1_2_stage_outputs_1_2_real_T)
node _stage_outputs_1_2_stage_outputs_1_2_real_new_T_1 = asSInt(_stage_outputs_1_2_stage_outputs_1_2_real_new_T)
connect _stage_outputs_1_2_stage_outputs_1_2_real_new_WIRE, _stage_outputs_1_2_stage_outputs_1_2_real_new_T_1
connect _stage_outputs_1_2_stage_outputs_1_2_real_new, _stage_outputs_1_2_stage_outputs_1_2_real_new_WIRE
connect stage_outputs_1_2.real, _stage_outputs_1_2_stage_outputs_1_2_real_new
node _stage_outputs_1_6_stage_outputs_1_6_imag_T = shr(butterfly_outputs_1_2.imag, 17)
wire _stage_outputs_1_6_stage_outputs_1_6_imag_new : SInt<18>
wire _stage_outputs_1_6_stage_outputs_1_6_imag_new_WIRE : SInt<18>
node _stage_outputs_1_6_stage_outputs_1_6_imag_new_T = asUInt(_stage_outputs_1_6_stage_outputs_1_6_imag_T)
node _stage_outputs_1_6_stage_outputs_1_6_imag_new_T_1 = asSInt(_stage_outputs_1_6_stage_outputs_1_6_imag_new_T)
connect _stage_outputs_1_6_stage_outputs_1_6_imag_new_WIRE, _stage_outputs_1_6_stage_outputs_1_6_imag_new_T_1
connect _stage_outputs_1_6_stage_outputs_1_6_imag_new, _stage_outputs_1_6_stage_outputs_1_6_imag_new_WIRE
connect stage_outputs_1_6.imag, _stage_outputs_1_6_stage_outputs_1_6_imag_new
node _stage_outputs_1_6_stage_outputs_1_6_real_T = shr(butterfly_outputs_1_2.real, 17)
wire _stage_outputs_1_6_stage_outputs_1_6_real_new : SInt<18>
wire _stage_outputs_1_6_stage_outputs_1_6_real_new_WIRE : SInt<18>
node _stage_outputs_1_6_stage_outputs_1_6_real_new_T = asUInt(_stage_outputs_1_6_stage_outputs_1_6_real_T)
node _stage_outputs_1_6_stage_outputs_1_6_real_new_T_1 = asSInt(_stage_outputs_1_6_stage_outputs_1_6_real_new_T)
connect _stage_outputs_1_6_stage_outputs_1_6_real_new_WIRE, _stage_outputs_1_6_stage_outputs_1_6_real_new_T_1
connect _stage_outputs_1_6_stage_outputs_1_6_real_new, _stage_outputs_1_6_stage_outputs_1_6_real_new_WIRE
connect stage_outputs_1_6.real, _stage_outputs_1_6_stage_outputs_1_6_real_new
wire butterfly_outputs_product_c_p_d_out_0_3 : SInt<19>
wire _butterfly_outputs_product_c_p_d_out_new_WIRE_6 : SInt<19>
node _butterfly_outputs_product_c_p_d_out_new_T_12 = asUInt(twiddle[0].real)
node _butterfly_outputs_product_c_p_d_out_new_T_13 = asSInt(_butterfly_outputs_product_c_p_d_out_new_T_12)
connect _butterfly_outputs_product_c_p_d_out_new_WIRE_6, _butterfly_outputs_product_c_p_d_out_new_T_13
connect butterfly_outputs_product_c_p_d_out_0_3, _butterfly_outputs_product_c_p_d_out_new_WIRE_6
wire butterfly_outputs_product_c_p_d_out_1_3 : SInt<19>
wire _butterfly_outputs_product_c_p_d_out_new_WIRE_7 : SInt<19>
node _butterfly_outputs_product_c_p_d_out_new_T_14 = asUInt(twiddle[0].imag)
node _butterfly_outputs_product_c_p_d_out_new_T_15 = asSInt(_butterfly_outputs_product_c_p_d_out_new_T_14)
connect _butterfly_outputs_product_c_p_d_out_new_WIRE_7, _butterfly_outputs_product_c_p_d_out_new_T_15
connect butterfly_outputs_product_c_p_d_out_1_3, _butterfly_outputs_product_c_p_d_out_new_WIRE_7
wire _butterfly_outputs_product_c_p_d_this_3 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_6 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_9 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_18 = asUInt(butterfly_outputs_product_c_p_d_out_0_3)
node _butterfly_outputs_product_c_p_d_new_T_19 = asSInt(_butterfly_outputs_product_c_p_d_new_T_18)
connect _butterfly_outputs_product_c_p_d_new_WIRE_9, _butterfly_outputs_product_c_p_d_new_T_19
connect _butterfly_outputs_product_c_p_d_new_6, _butterfly_outputs_product_c_p_d_new_WIRE_9
connect _butterfly_outputs_product_c_p_d_this_3, _butterfly_outputs_product_c_p_d_new_6
wire _butterfly_outputs_product_c_p_d_that_3 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_7 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_10 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_20 = asUInt(butterfly_outputs_product_c_p_d_out_1_3)
node _butterfly_outputs_product_c_p_d_new_T_21 = asSInt(_butterfly_outputs_product_c_p_d_new_T_20)
connect _butterfly_outputs_product_c_p_d_new_WIRE_10, _butterfly_outputs_product_c_p_d_new_T_21
connect _butterfly_outputs_product_c_p_d_new_7, _butterfly_outputs_product_c_p_d_new_WIRE_10
connect _butterfly_outputs_product_c_p_d_that_3, _butterfly_outputs_product_c_p_d_new_7
node _butterfly_outputs_product_c_p_d_T_9 = add(_butterfly_outputs_product_c_p_d_this_3, _butterfly_outputs_product_c_p_d_that_3)
node _butterfly_outputs_product_c_p_d_T_10 = tail(_butterfly_outputs_product_c_p_d_T_9, 1)
node _butterfly_outputs_product_c_p_d_T_11 = asSInt(_butterfly_outputs_product_c_p_d_T_10)
wire butterfly_outputs_product_c_p_d_3 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_11 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_22 = asUInt(_butterfly_outputs_product_c_p_d_T_11)
node _butterfly_outputs_product_c_p_d_new_T_23 = asSInt(_butterfly_outputs_product_c_p_d_new_T_22)
connect _butterfly_outputs_product_c_p_d_new_WIRE_11, _butterfly_outputs_product_c_p_d_new_T_23
connect butterfly_outputs_product_c_p_d_3, _butterfly_outputs_product_c_p_d_new_WIRE_11
wire butterfly_outputs_product_a_p_b_out_0_3 : SInt<16>
wire _butterfly_outputs_product_a_p_b_out_new_WIRE_6 : SInt<16>
node _butterfly_outputs_product_a_p_b_out_new_T_12 = asUInt(stage_outputs_0_7.real)
node _butterfly_outputs_product_a_p_b_out_new_T_13 = asSInt(_butterfly_outputs_product_a_p_b_out_new_T_12)
connect _butterfly_outputs_product_a_p_b_out_new_WIRE_6, _butterfly_outputs_product_a_p_b_out_new_T_13
connect butterfly_outputs_product_a_p_b_out_0_3, _butterfly_outputs_product_a_p_b_out_new_WIRE_6
wire butterfly_outputs_product_a_p_b_out_1_3 : SInt<16>
wire _butterfly_outputs_product_a_p_b_out_new_WIRE_7 : SInt<16>
node _butterfly_outputs_product_a_p_b_out_new_T_14 = asUInt(stage_outputs_0_7.imag)
node _butterfly_outputs_product_a_p_b_out_new_T_15 = asSInt(_butterfly_outputs_product_a_p_b_out_new_T_14)
connect _butterfly_outputs_product_a_p_b_out_new_WIRE_7, _butterfly_outputs_product_a_p_b_out_new_T_15
connect butterfly_outputs_product_a_p_b_out_1_3, _butterfly_outputs_product_a_p_b_out_new_WIRE_7
wire _butterfly_outputs_product_a_p_b_this_3 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_6 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_9 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_18 = asUInt(butterfly_outputs_product_a_p_b_out_0_3)
node _butterfly_outputs_product_a_p_b_new_T_19 = asSInt(_butterfly_outputs_product_a_p_b_new_T_18)
connect _butterfly_outputs_product_a_p_b_new_WIRE_9, _butterfly_outputs_product_a_p_b_new_T_19
connect _butterfly_outputs_product_a_p_b_new_6, _butterfly_outputs_product_a_p_b_new_WIRE_9
connect _butterfly_outputs_product_a_p_b_this_3, _butterfly_outputs_product_a_p_b_new_6
wire _butterfly_outputs_product_a_p_b_that_3 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_7 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_10 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_20 = asUInt(butterfly_outputs_product_a_p_b_out_1_3)
node _butterfly_outputs_product_a_p_b_new_T_21 = asSInt(_butterfly_outputs_product_a_p_b_new_T_20)
connect _butterfly_outputs_product_a_p_b_new_WIRE_10, _butterfly_outputs_product_a_p_b_new_T_21
connect _butterfly_outputs_product_a_p_b_new_7, _butterfly_outputs_product_a_p_b_new_WIRE_10
connect _butterfly_outputs_product_a_p_b_that_3, _butterfly_outputs_product_a_p_b_new_7
node _butterfly_outputs_product_a_p_b_T_9 = add(_butterfly_outputs_product_a_p_b_this_3, _butterfly_outputs_product_a_p_b_that_3)
node _butterfly_outputs_product_a_p_b_T_10 = tail(_butterfly_outputs_product_a_p_b_T_9, 1)
node _butterfly_outputs_product_a_p_b_T_11 = asSInt(_butterfly_outputs_product_a_p_b_T_10)
wire butterfly_outputs_product_a_p_b_3 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_11 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_22 = asUInt(_butterfly_outputs_product_a_p_b_T_11)
node _butterfly_outputs_product_a_p_b_new_T_23 = asSInt(_butterfly_outputs_product_a_p_b_new_T_22)
connect _butterfly_outputs_product_a_p_b_new_WIRE_11, _butterfly_outputs_product_a_p_b_new_T_23
connect butterfly_outputs_product_a_p_b_3, _butterfly_outputs_product_a_p_b_new_WIRE_11
wire butterfly_outputs_product_b_m_a_out_0_3 : SInt<16>
wire _butterfly_outputs_product_b_m_a_out_new_WIRE_6 : SInt<16>
node _butterfly_outputs_product_b_m_a_out_new_T_12 = asUInt(stage_outputs_0_7.imag)
node _butterfly_outputs_product_b_m_a_out_new_T_13 = asSInt(_butterfly_outputs_product_b_m_a_out_new_T_12)
connect _butterfly_outputs_product_b_m_a_out_new_WIRE_6, _butterfly_outputs_product_b_m_a_out_new_T_13
connect butterfly_outputs_product_b_m_a_out_0_3, _butterfly_outputs_product_b_m_a_out_new_WIRE_6
wire butterfly_outputs_product_b_m_a_out_1_3 : SInt<16>
wire _butterfly_outputs_product_b_m_a_out_new_WIRE_7 : SInt<16>
node _butterfly_outputs_product_b_m_a_out_new_T_14 = asUInt(stage_outputs_0_7.real)
node _butterfly_outputs_product_b_m_a_out_new_T_15 = asSInt(_butterfly_outputs_product_b_m_a_out_new_T_14)
connect _butterfly_outputs_product_b_m_a_out_new_WIRE_7, _butterfly_outputs_product_b_m_a_out_new_T_15
connect butterfly_outputs_product_b_m_a_out_1_3, _butterfly_outputs_product_b_m_a_out_new_WIRE_7
wire _butterfly_outputs_product_b_m_a_this_3 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_6 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_9 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_18 = asUInt(butterfly_outputs_product_b_m_a_out_0_3)
node _butterfly_outputs_product_b_m_a_new_T_19 = asSInt(_butterfly_outputs_product_b_m_a_new_T_18)
connect _butterfly_outputs_product_b_m_a_new_WIRE_9, _butterfly_outputs_product_b_m_a_new_T_19
connect _butterfly_outputs_product_b_m_a_new_6, _butterfly_outputs_product_b_m_a_new_WIRE_9
connect _butterfly_outputs_product_b_m_a_this_3, _butterfly_outputs_product_b_m_a_new_6
wire _butterfly_outputs_product_b_m_a_that_3 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_7 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_10 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_20 = asUInt(butterfly_outputs_product_b_m_a_out_1_3)
node _butterfly_outputs_product_b_m_a_new_T_21 = asSInt(_butterfly_outputs_product_b_m_a_new_T_20)
connect _butterfly_outputs_product_b_m_a_new_WIRE_10, _butterfly_outputs_product_b_m_a_new_T_21
connect _butterfly_outputs_product_b_m_a_new_7, _butterfly_outputs_product_b_m_a_new_WIRE_10
connect _butterfly_outputs_product_b_m_a_that_3, _butterfly_outputs_product_b_m_a_new_7
node _butterfly_outputs_product_b_m_a_T_9 = sub(_butterfly_outputs_product_b_m_a_this_3, _butterfly_outputs_product_b_m_a_that_3)
node _butterfly_outputs_product_b_m_a_T_10 = tail(_butterfly_outputs_product_b_m_a_T_9, 1)
node _butterfly_outputs_product_b_m_a_T_11 = asSInt(_butterfly_outputs_product_b_m_a_T_10)
wire butterfly_outputs_product_b_m_a_3 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_11 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_22 = asUInt(_butterfly_outputs_product_b_m_a_T_11)
node _butterfly_outputs_product_b_m_a_new_T_23 = asSInt(_butterfly_outputs_product_b_m_a_new_T_22)
connect _butterfly_outputs_product_b_m_a_new_WIRE_11, _butterfly_outputs_product_b_m_a_new_T_23
connect butterfly_outputs_product_b_m_a_3, _butterfly_outputs_product_b_m_a_new_WIRE_11
node _butterfly_outputs_product_ac_p_ad_T_3 = mul(stage_outputs_0_7.real, butterfly_outputs_product_c_p_d_3)
wire butterfly_outputs_product_ac_p_ad_3 : SInt<35>
wire _butterfly_outputs_product_ac_p_ad_new_WIRE_3 : SInt<35>
node _butterfly_outputs_product_ac_p_ad_new_T_6 = asUInt(_butterfly_outputs_product_ac_p_ad_T_3)
node _butterfly_outputs_product_ac_p_ad_new_T_7 = asSInt(_butterfly_outputs_product_ac_p_ad_new_T_6)
connect _butterfly_outputs_product_ac_p_ad_new_WIRE_3, _butterfly_outputs_product_ac_p_ad_new_T_7
connect butterfly_outputs_product_ac_p_ad_3, _butterfly_outputs_product_ac_p_ad_new_WIRE_3
node _butterfly_outputs_product_ad_p_bd_T_3 = mul(butterfly_outputs_product_a_p_b_3, twiddle[0].imag)
wire butterfly_outputs_product_ad_p_bd_3 : SInt<35>
wire _butterfly_outputs_product_ad_p_bd_new_WIRE_3 : SInt<35>
node _butterfly_outputs_product_ad_p_bd_new_T_6 = asUInt(_butterfly_outputs_product_ad_p_bd_T_3)
node _butterfly_outputs_product_ad_p_bd_new_T_7 = asSInt(_butterfly_outputs_product_ad_p_bd_new_T_6)
connect _butterfly_outputs_product_ad_p_bd_new_WIRE_3, _butterfly_outputs_product_ad_p_bd_new_T_7
connect butterfly_outputs_product_ad_p_bd_3, _butterfly_outputs_product_ad_p_bd_new_WIRE_3
node _butterfly_outputs_product_bc_m_ac_T_3 = mul(butterfly_outputs_product_b_m_a_3, twiddle[0].real)
wire butterfly_outputs_product_bc_m_ac_3 : SInt<35>
wire _butterfly_outputs_product_bc_m_ac_new_WIRE_3 : SInt<35>
node _butterfly_outputs_product_bc_m_ac_new_T_6 = asUInt(_butterfly_outputs_product_bc_m_ac_T_3)
node _butterfly_outputs_product_bc_m_ac_new_T_7 = asSInt(_butterfly_outputs_product_bc_m_ac_new_T_6)
connect _butterfly_outputs_product_bc_m_ac_new_WIRE_3, _butterfly_outputs_product_bc_m_ac_new_T_7
connect butterfly_outputs_product_bc_m_ac_3, _butterfly_outputs_product_bc_m_ac_new_WIRE_3
wire butterfly_outputs_product_out_0_6 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_12 : SInt<35>
node _butterfly_outputs_product_out_new_T_24 = asUInt(butterfly_outputs_product_ac_p_ad_3)
node _butterfly_outputs_product_out_new_T_25 = asSInt(_butterfly_outputs_product_out_new_T_24)
connect _butterfly_outputs_product_out_new_WIRE_12, _butterfly_outputs_product_out_new_T_25
connect butterfly_outputs_product_out_0_6, _butterfly_outputs_product_out_new_WIRE_12
wire butterfly_outputs_product_out_1_6 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_13 : SInt<35>
node _butterfly_outputs_product_out_new_T_26 = asUInt(butterfly_outputs_product_ad_p_bd_3)
node _butterfly_outputs_product_out_new_T_27 = asSInt(_butterfly_outputs_product_out_new_T_26)
connect _butterfly_outputs_product_out_new_WIRE_13, _butterfly_outputs_product_out_new_T_27
connect butterfly_outputs_product_out_1_6, _butterfly_outputs_product_out_new_WIRE_13
wire _butterfly_outputs_product_this_6 : SInt<35>
wire _butterfly_outputs_product_new_18 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_18 : SInt<35>
node _butterfly_outputs_product_new_T_36 = asUInt(butterfly_outputs_product_out_0_6)
node _butterfly_outputs_product_new_T_37 = asSInt(_butterfly_outputs_product_new_T_36)
connect _butterfly_outputs_product_new_WIRE_18, _butterfly_outputs_product_new_T_37
connect _butterfly_outputs_product_new_18, _butterfly_outputs_product_new_WIRE_18
connect _butterfly_outputs_product_this_6, _butterfly_outputs_product_new_18
wire _butterfly_outputs_product_that_6 : SInt<35>
wire _butterfly_outputs_product_new_19 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_19 : SInt<35>
node _butterfly_outputs_product_new_T_38 = asUInt(butterfly_outputs_product_out_1_6)
node _butterfly_outputs_product_new_T_39 = asSInt(_butterfly_outputs_product_new_T_38)
connect _butterfly_outputs_product_new_WIRE_19, _butterfly_outputs_product_new_T_39
connect _butterfly_outputs_product_new_19, _butterfly_outputs_product_new_WIRE_19
connect _butterfly_outputs_product_that_6, _butterfly_outputs_product_new_19
node _butterfly_outputs_product_T_18 = sub(_butterfly_outputs_product_this_6, _butterfly_outputs_product_that_6)
node _butterfly_outputs_product_T_19 = tail(_butterfly_outputs_product_T_18, 1)
node _butterfly_outputs_product_T_20 = asSInt(_butterfly_outputs_product_T_19)
wire _butterfly_outputs_product_new_20 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_20 : SInt<35>
node _butterfly_outputs_product_new_T_40 = asUInt(_butterfly_outputs_product_T_20)
node _butterfly_outputs_product_new_T_41 = asSInt(_butterfly_outputs_product_new_T_40)
connect _butterfly_outputs_product_new_WIRE_20, _butterfly_outputs_product_new_T_41
connect _butterfly_outputs_product_new_20, _butterfly_outputs_product_new_WIRE_20
wire butterfly_outputs_product_out_0_7 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_14 : SInt<35>
node _butterfly_outputs_product_out_new_T_28 = asUInt(butterfly_outputs_product_ac_p_ad_3)
node _butterfly_outputs_product_out_new_T_29 = asSInt(_butterfly_outputs_product_out_new_T_28)
connect _butterfly_outputs_product_out_new_WIRE_14, _butterfly_outputs_product_out_new_T_29
connect butterfly_outputs_product_out_0_7, _butterfly_outputs_product_out_new_WIRE_14
wire butterfly_outputs_product_out_1_7 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_15 : SInt<35>
node _butterfly_outputs_product_out_new_T_30 = asUInt(butterfly_outputs_product_bc_m_ac_3)
node _butterfly_outputs_product_out_new_T_31 = asSInt(_butterfly_outputs_product_out_new_T_30)
connect _butterfly_outputs_product_out_new_WIRE_15, _butterfly_outputs_product_out_new_T_31
connect butterfly_outputs_product_out_1_7, _butterfly_outputs_product_out_new_WIRE_15
wire _butterfly_outputs_product_this_7 : SInt<35>
wire _butterfly_outputs_product_new_21 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_21 : SInt<35>
node _butterfly_outputs_product_new_T_42 = asUInt(butterfly_outputs_product_out_0_7)
node _butterfly_outputs_product_new_T_43 = asSInt(_butterfly_outputs_product_new_T_42)
connect _butterfly_outputs_product_new_WIRE_21, _butterfly_outputs_product_new_T_43
connect _butterfly_outputs_product_new_21, _butterfly_outputs_product_new_WIRE_21
connect _butterfly_outputs_product_this_7, _butterfly_outputs_product_new_21
wire _butterfly_outputs_product_that_7 : SInt<35>
wire _butterfly_outputs_product_new_22 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_22 : SInt<35>
node _butterfly_outputs_product_new_T_44 = asUInt(butterfly_outputs_product_out_1_7)
node _butterfly_outputs_product_new_T_45 = asSInt(_butterfly_outputs_product_new_T_44)
connect _butterfly_outputs_product_new_WIRE_22, _butterfly_outputs_product_new_T_45
connect _butterfly_outputs_product_new_22, _butterfly_outputs_product_new_WIRE_22
connect _butterfly_outputs_product_that_7, _butterfly_outputs_product_new_22
node _butterfly_outputs_product_T_21 = add(_butterfly_outputs_product_this_7, _butterfly_outputs_product_that_7)
node _butterfly_outputs_product_T_22 = tail(_butterfly_outputs_product_T_21, 1)
node _butterfly_outputs_product_T_23 = asSInt(_butterfly_outputs_product_T_22)
wire _butterfly_outputs_product_new_23 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_23 : SInt<35>
node _butterfly_outputs_product_new_T_46 = asUInt(_butterfly_outputs_product_T_23)
node _butterfly_outputs_product_new_T_47 = asSInt(_butterfly_outputs_product_new_T_46)
connect _butterfly_outputs_product_new_WIRE_23, _butterfly_outputs_product_new_T_47
connect _butterfly_outputs_product_new_23, _butterfly_outputs_product_new_WIRE_23
wire butterfly_outputs_product_3 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_product_result_real_new_3 : SInt<35>
wire _butterfly_outputs_product_result_real_new_WIRE_3 : SInt<35>
node _butterfly_outputs_product_result_real_new_T_6 = asUInt(_butterfly_outputs_product_new_20)
node _butterfly_outputs_product_result_real_new_T_7 = asSInt(_butterfly_outputs_product_result_real_new_T_6)
connect _butterfly_outputs_product_result_real_new_WIRE_3, _butterfly_outputs_product_result_real_new_T_7
connect _butterfly_outputs_product_result_real_new_3, _butterfly_outputs_product_result_real_new_WIRE_3
connect butterfly_outputs_product_3.real, _butterfly_outputs_product_result_real_new_3
wire _butterfly_outputs_product_result_imag_new_3 : SInt<35>
wire _butterfly_outputs_product_result_imag_new_WIRE_3 : SInt<35>
node _butterfly_outputs_product_result_imag_new_T_6 = asUInt(_butterfly_outputs_product_new_23)
node _butterfly_outputs_product_result_imag_new_T_7 = asSInt(_butterfly_outputs_product_result_imag_new_T_6)
connect _butterfly_outputs_product_result_imag_new_WIRE_3, _butterfly_outputs_product_result_imag_new_T_7
connect _butterfly_outputs_product_result_imag_new_3, _butterfly_outputs_product_result_imag_new_WIRE_3
connect butterfly_outputs_product_3.imag, _butterfly_outputs_product_result_imag_new_3
node _butterfly_outputs_out_T_12 = shl(stage_outputs_0_3.real, 17)
wire butterfly_outputs_out_0_12 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_24 : SInt<35>
node _butterfly_outputs_out_new_T_48 = asUInt(_butterfly_outputs_out_T_12)
node _butterfly_outputs_out_new_T_49 = asSInt(_butterfly_outputs_out_new_T_48)
connect _butterfly_outputs_out_new_WIRE_24, _butterfly_outputs_out_new_T_49
connect butterfly_outputs_out_0_12, _butterfly_outputs_out_new_WIRE_24
wire butterfly_outputs_out_1_12 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_25 : SInt<35>
node _butterfly_outputs_out_new_T_50 = asUInt(butterfly_outputs_product_3.real)
node _butterfly_outputs_out_new_T_51 = asSInt(_butterfly_outputs_out_new_T_50)
connect _butterfly_outputs_out_new_WIRE_25, _butterfly_outputs_out_new_T_51
connect butterfly_outputs_out_1_12, _butterfly_outputs_out_new_WIRE_25
wire _butterfly_outputs_this_12 : SInt<35>
wire _butterfly_outputs_new_36 : SInt<35>
wire _butterfly_outputs_new_WIRE_36 : SInt<35>
node _butterfly_outputs_new_T_72 = asUInt(butterfly_outputs_out_0_12)
node _butterfly_outputs_new_T_73 = asSInt(_butterfly_outputs_new_T_72)
connect _butterfly_outputs_new_WIRE_36, _butterfly_outputs_new_T_73
connect _butterfly_outputs_new_36, _butterfly_outputs_new_WIRE_36
connect _butterfly_outputs_this_12, _butterfly_outputs_new_36
wire _butterfly_outputs_that_12 : SInt<35>
wire _butterfly_outputs_new_37 : SInt<35>
wire _butterfly_outputs_new_WIRE_37 : SInt<35>
node _butterfly_outputs_new_T_74 = asUInt(butterfly_outputs_out_1_12)
node _butterfly_outputs_new_T_75 = asSInt(_butterfly_outputs_new_T_74)
connect _butterfly_outputs_new_WIRE_37, _butterfly_outputs_new_T_75
connect _butterfly_outputs_new_37, _butterfly_outputs_new_WIRE_37
connect _butterfly_outputs_that_12, _butterfly_outputs_new_37
node _butterfly_outputs_T_36 = add(_butterfly_outputs_this_12, _butterfly_outputs_that_12)
node _butterfly_outputs_T_37 = tail(_butterfly_outputs_T_36, 1)
node _butterfly_outputs_T_38 = asSInt(_butterfly_outputs_T_37)
wire _butterfly_outputs_new_38 : SInt<35>
wire _butterfly_outputs_new_WIRE_38 : SInt<35>
node _butterfly_outputs_new_T_76 = asUInt(_butterfly_outputs_T_38)
node _butterfly_outputs_new_T_77 = asSInt(_butterfly_outputs_new_T_76)
connect _butterfly_outputs_new_WIRE_38, _butterfly_outputs_new_T_77
connect _butterfly_outputs_new_38, _butterfly_outputs_new_WIRE_38
node _butterfly_outputs_out_T_13 = shl(stage_outputs_0_3.imag, 17)
wire butterfly_outputs_out_0_13 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_26 : SInt<35>
node _butterfly_outputs_out_new_T_52 = asUInt(_butterfly_outputs_out_T_13)
node _butterfly_outputs_out_new_T_53 = asSInt(_butterfly_outputs_out_new_T_52)
connect _butterfly_outputs_out_new_WIRE_26, _butterfly_outputs_out_new_T_53
connect butterfly_outputs_out_0_13, _butterfly_outputs_out_new_WIRE_26
wire butterfly_outputs_out_1_13 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_27 : SInt<35>
node _butterfly_outputs_out_new_T_54 = asUInt(butterfly_outputs_product_3.imag)
node _butterfly_outputs_out_new_T_55 = asSInt(_butterfly_outputs_out_new_T_54)
connect _butterfly_outputs_out_new_WIRE_27, _butterfly_outputs_out_new_T_55
connect butterfly_outputs_out_1_13, _butterfly_outputs_out_new_WIRE_27
wire _butterfly_outputs_this_13 : SInt<35>
wire _butterfly_outputs_new_39 : SInt<35>
wire _butterfly_outputs_new_WIRE_39 : SInt<35>
node _butterfly_outputs_new_T_78 = asUInt(butterfly_outputs_out_0_13)
node _butterfly_outputs_new_T_79 = asSInt(_butterfly_outputs_new_T_78)
connect _butterfly_outputs_new_WIRE_39, _butterfly_outputs_new_T_79
connect _butterfly_outputs_new_39, _butterfly_outputs_new_WIRE_39
connect _butterfly_outputs_this_13, _butterfly_outputs_new_39
wire _butterfly_outputs_that_13 : SInt<35>
wire _butterfly_outputs_new_40 : SInt<35>
wire _butterfly_outputs_new_WIRE_40 : SInt<35>
node _butterfly_outputs_new_T_80 = asUInt(butterfly_outputs_out_1_13)
node _butterfly_outputs_new_T_81 = asSInt(_butterfly_outputs_new_T_80)
connect _butterfly_outputs_new_WIRE_40, _butterfly_outputs_new_T_81
connect _butterfly_outputs_new_40, _butterfly_outputs_new_WIRE_40
connect _butterfly_outputs_that_13, _butterfly_outputs_new_40
node _butterfly_outputs_T_39 = add(_butterfly_outputs_this_13, _butterfly_outputs_that_13)
node _butterfly_outputs_T_40 = tail(_butterfly_outputs_T_39, 1)
node _butterfly_outputs_T_41 = asSInt(_butterfly_outputs_T_40)
wire _butterfly_outputs_new_41 : SInt<35>
wire _butterfly_outputs_new_WIRE_41 : SInt<35>
node _butterfly_outputs_new_T_82 = asUInt(_butterfly_outputs_T_41)
node _butterfly_outputs_new_T_83 = asSInt(_butterfly_outputs_new_T_82)
connect _butterfly_outputs_new_WIRE_41, _butterfly_outputs_new_T_83
connect _butterfly_outputs_new_41, _butterfly_outputs_new_WIRE_41
wire butterfly_outputs_0_3 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_result_real_new_6 : SInt<35>
wire _butterfly_outputs_result_real_new_WIRE_6 : SInt<35>
node _butterfly_outputs_result_real_new_T_12 = asUInt(_butterfly_outputs_new_38)
node _butterfly_outputs_result_real_new_T_13 = asSInt(_butterfly_outputs_result_real_new_T_12)
connect _butterfly_outputs_result_real_new_WIRE_6, _butterfly_outputs_result_real_new_T_13
connect _butterfly_outputs_result_real_new_6, _butterfly_outputs_result_real_new_WIRE_6
connect butterfly_outputs_0_3.real, _butterfly_outputs_result_real_new_6
wire _butterfly_outputs_result_imag_new_6 : SInt<35>
wire _butterfly_outputs_result_imag_new_WIRE_6 : SInt<35>
node _butterfly_outputs_result_imag_new_T_12 = asUInt(_butterfly_outputs_new_41)
node _butterfly_outputs_result_imag_new_T_13 = asSInt(_butterfly_outputs_result_imag_new_T_12)
connect _butterfly_outputs_result_imag_new_WIRE_6, _butterfly_outputs_result_imag_new_T_13
connect _butterfly_outputs_result_imag_new_6, _butterfly_outputs_result_imag_new_WIRE_6
connect butterfly_outputs_0_3.imag, _butterfly_outputs_result_imag_new_6
node _butterfly_outputs_out_T_14 = shl(stage_outputs_0_3.real, 17)
wire butterfly_outputs_out_0_14 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_28 : SInt<35>
node _butterfly_outputs_out_new_T_56 = asUInt(_butterfly_outputs_out_T_14)
node _butterfly_outputs_out_new_T_57 = asSInt(_butterfly_outputs_out_new_T_56)
connect _butterfly_outputs_out_new_WIRE_28, _butterfly_outputs_out_new_T_57
connect butterfly_outputs_out_0_14, _butterfly_outputs_out_new_WIRE_28
wire butterfly_outputs_out_1_14 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_29 : SInt<35>
node _butterfly_outputs_out_new_T_58 = asUInt(butterfly_outputs_product_3.real)
node _butterfly_outputs_out_new_T_59 = asSInt(_butterfly_outputs_out_new_T_58)
connect _butterfly_outputs_out_new_WIRE_29, _butterfly_outputs_out_new_T_59
connect butterfly_outputs_out_1_14, _butterfly_outputs_out_new_WIRE_29
wire _butterfly_outputs_this_14 : SInt<35>
wire _butterfly_outputs_new_42 : SInt<35>
wire _butterfly_outputs_new_WIRE_42 : SInt<35>
node _butterfly_outputs_new_T_84 = asUInt(butterfly_outputs_out_0_14)
node _butterfly_outputs_new_T_85 = asSInt(_butterfly_outputs_new_T_84)
connect _butterfly_outputs_new_WIRE_42, _butterfly_outputs_new_T_85
connect _butterfly_outputs_new_42, _butterfly_outputs_new_WIRE_42
connect _butterfly_outputs_this_14, _butterfly_outputs_new_42
wire _butterfly_outputs_that_14 : SInt<35>
wire _butterfly_outputs_new_43 : SInt<35>
wire _butterfly_outputs_new_WIRE_43 : SInt<35>
node _butterfly_outputs_new_T_86 = asUInt(butterfly_outputs_out_1_14)
node _butterfly_outputs_new_T_87 = asSInt(_butterfly_outputs_new_T_86)
connect _butterfly_outputs_new_WIRE_43, _butterfly_outputs_new_T_87
connect _butterfly_outputs_new_43, _butterfly_outputs_new_WIRE_43
connect _butterfly_outputs_that_14, _butterfly_outputs_new_43
node _butterfly_outputs_T_42 = sub(_butterfly_outputs_this_14, _butterfly_outputs_that_14)
node _butterfly_outputs_T_43 = tail(_butterfly_outputs_T_42, 1)
node _butterfly_outputs_T_44 = asSInt(_butterfly_outputs_T_43)
wire _butterfly_outputs_new_44 : SInt<35>
wire _butterfly_outputs_new_WIRE_44 : SInt<35>
node _butterfly_outputs_new_T_88 = asUInt(_butterfly_outputs_T_44)
node _butterfly_outputs_new_T_89 = asSInt(_butterfly_outputs_new_T_88)
connect _butterfly_outputs_new_WIRE_44, _butterfly_outputs_new_T_89
connect _butterfly_outputs_new_44, _butterfly_outputs_new_WIRE_44
node _butterfly_outputs_out_T_15 = shl(stage_outputs_0_3.imag, 17)
wire butterfly_outputs_out_0_15 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_30 : SInt<35>
node _butterfly_outputs_out_new_T_60 = asUInt(_butterfly_outputs_out_T_15)
node _butterfly_outputs_out_new_T_61 = asSInt(_butterfly_outputs_out_new_T_60)
connect _butterfly_outputs_out_new_WIRE_30, _butterfly_outputs_out_new_T_61
connect butterfly_outputs_out_0_15, _butterfly_outputs_out_new_WIRE_30
wire butterfly_outputs_out_1_15 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_31 : SInt<35>
node _butterfly_outputs_out_new_T_62 = asUInt(butterfly_outputs_product_3.imag)
node _butterfly_outputs_out_new_T_63 = asSInt(_butterfly_outputs_out_new_T_62)
connect _butterfly_outputs_out_new_WIRE_31, _butterfly_outputs_out_new_T_63
connect butterfly_outputs_out_1_15, _butterfly_outputs_out_new_WIRE_31
wire _butterfly_outputs_this_15 : SInt<35>
wire _butterfly_outputs_new_45 : SInt<35>
wire _butterfly_outputs_new_WIRE_45 : SInt<35>
node _butterfly_outputs_new_T_90 = asUInt(butterfly_outputs_out_0_15)
node _butterfly_outputs_new_T_91 = asSInt(_butterfly_outputs_new_T_90)
connect _butterfly_outputs_new_WIRE_45, _butterfly_outputs_new_T_91
connect _butterfly_outputs_new_45, _butterfly_outputs_new_WIRE_45
connect _butterfly_outputs_this_15, _butterfly_outputs_new_45
wire _butterfly_outputs_that_15 : SInt<35>
wire _butterfly_outputs_new_46 : SInt<35>
wire _butterfly_outputs_new_WIRE_46 : SInt<35>
node _butterfly_outputs_new_T_92 = asUInt(butterfly_outputs_out_1_15)
node _butterfly_outputs_new_T_93 = asSInt(_butterfly_outputs_new_T_92)
connect _butterfly_outputs_new_WIRE_46, _butterfly_outputs_new_T_93
connect _butterfly_outputs_new_46, _butterfly_outputs_new_WIRE_46
connect _butterfly_outputs_that_15, _butterfly_outputs_new_46
node _butterfly_outputs_T_45 = sub(_butterfly_outputs_this_15, _butterfly_outputs_that_15)
node _butterfly_outputs_T_46 = tail(_butterfly_outputs_T_45, 1)
node _butterfly_outputs_T_47 = asSInt(_butterfly_outputs_T_46)
wire _butterfly_outputs_new_47 : SInt<35>
wire _butterfly_outputs_new_WIRE_47 : SInt<35>
node _butterfly_outputs_new_T_94 = asUInt(_butterfly_outputs_T_47)
node _butterfly_outputs_new_T_95 = asSInt(_butterfly_outputs_new_T_94)
connect _butterfly_outputs_new_WIRE_47, _butterfly_outputs_new_T_95
connect _butterfly_outputs_new_47, _butterfly_outputs_new_WIRE_47
wire butterfly_outputs_1_3 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_result_real_new_7 : SInt<35>
wire _butterfly_outputs_result_real_new_WIRE_7 : SInt<35>
node _butterfly_outputs_result_real_new_T_14 = asUInt(_butterfly_outputs_new_44)
node _butterfly_outputs_result_real_new_T_15 = asSInt(_butterfly_outputs_result_real_new_T_14)
connect _butterfly_outputs_result_real_new_WIRE_7, _butterfly_outputs_result_real_new_T_15
connect _butterfly_outputs_result_real_new_7, _butterfly_outputs_result_real_new_WIRE_7
connect butterfly_outputs_1_3.real, _butterfly_outputs_result_real_new_7
wire _butterfly_outputs_result_imag_new_7 : SInt<35>
wire _butterfly_outputs_result_imag_new_WIRE_7 : SInt<35>
node _butterfly_outputs_result_imag_new_T_14 = asUInt(_butterfly_outputs_new_47)
node _butterfly_outputs_result_imag_new_T_15 = asSInt(_butterfly_outputs_result_imag_new_T_14)
connect _butterfly_outputs_result_imag_new_WIRE_7, _butterfly_outputs_result_imag_new_T_15
connect _butterfly_outputs_result_imag_new_7, _butterfly_outputs_result_imag_new_WIRE_7
connect butterfly_outputs_1_3.imag, _butterfly_outputs_result_imag_new_7
node _stage_outputs_1_3_stage_outputs_1_3_imag_T = shr(butterfly_outputs_0_3.imag, 17)
wire _stage_outputs_1_3_stage_outputs_1_3_imag_new : SInt<18>
wire _stage_outputs_1_3_stage_outputs_1_3_imag_new_WIRE : SInt<18>
node _stage_outputs_1_3_stage_outputs_1_3_imag_new_T = asUInt(_stage_outputs_1_3_stage_outputs_1_3_imag_T)
node _stage_outputs_1_3_stage_outputs_1_3_imag_new_T_1 = asSInt(_stage_outputs_1_3_stage_outputs_1_3_imag_new_T)
connect _stage_outputs_1_3_stage_outputs_1_3_imag_new_WIRE, _stage_outputs_1_3_stage_outputs_1_3_imag_new_T_1
connect _stage_outputs_1_3_stage_outputs_1_3_imag_new, _stage_outputs_1_3_stage_outputs_1_3_imag_new_WIRE
connect stage_outputs_1_3.imag, _stage_outputs_1_3_stage_outputs_1_3_imag_new
node _stage_outputs_1_3_stage_outputs_1_3_real_T = shr(butterfly_outputs_0_3.real, 17)
wire _stage_outputs_1_3_stage_outputs_1_3_real_new : SInt<18>
wire _stage_outputs_1_3_stage_outputs_1_3_real_new_WIRE : SInt<18>
node _stage_outputs_1_3_stage_outputs_1_3_real_new_T = asUInt(_stage_outputs_1_3_stage_outputs_1_3_real_T)
node _stage_outputs_1_3_stage_outputs_1_3_real_new_T_1 = asSInt(_stage_outputs_1_3_stage_outputs_1_3_real_new_T)
connect _stage_outputs_1_3_stage_outputs_1_3_real_new_WIRE, _stage_outputs_1_3_stage_outputs_1_3_real_new_T_1
connect _stage_outputs_1_3_stage_outputs_1_3_real_new, _stage_outputs_1_3_stage_outputs_1_3_real_new_WIRE
connect stage_outputs_1_3.real, _stage_outputs_1_3_stage_outputs_1_3_real_new
node _stage_outputs_1_7_stage_outputs_1_7_imag_T = shr(butterfly_outputs_1_3.imag, 17)
wire _stage_outputs_1_7_stage_outputs_1_7_imag_new : SInt<18>
wire _stage_outputs_1_7_stage_outputs_1_7_imag_new_WIRE : SInt<18>
node _stage_outputs_1_7_stage_outputs_1_7_imag_new_T = asUInt(_stage_outputs_1_7_stage_outputs_1_7_imag_T)
node _stage_outputs_1_7_stage_outputs_1_7_imag_new_T_1 = asSInt(_stage_outputs_1_7_stage_outputs_1_7_imag_new_T)
connect _stage_outputs_1_7_stage_outputs_1_7_imag_new_WIRE, _stage_outputs_1_7_stage_outputs_1_7_imag_new_T_1
connect _stage_outputs_1_7_stage_outputs_1_7_imag_new, _stage_outputs_1_7_stage_outputs_1_7_imag_new_WIRE
connect stage_outputs_1_7.imag, _stage_outputs_1_7_stage_outputs_1_7_imag_new
node _stage_outputs_1_7_stage_outputs_1_7_real_T = shr(butterfly_outputs_1_3.real, 17)
wire _stage_outputs_1_7_stage_outputs_1_7_real_new : SInt<18>
wire _stage_outputs_1_7_stage_outputs_1_7_real_new_WIRE : SInt<18>
node _stage_outputs_1_7_stage_outputs_1_7_real_new_T = asUInt(_stage_outputs_1_7_stage_outputs_1_7_real_T)
node _stage_outputs_1_7_stage_outputs_1_7_real_new_T_1 = asSInt(_stage_outputs_1_7_stage_outputs_1_7_real_new_T)
connect _stage_outputs_1_7_stage_outputs_1_7_real_new_WIRE, _stage_outputs_1_7_stage_outputs_1_7_real_new_T_1
connect _stage_outputs_1_7_stage_outputs_1_7_real_new, _stage_outputs_1_7_stage_outputs_1_7_real_new_WIRE
connect stage_outputs_1_7.real, _stage_outputs_1_7_stage_outputs_1_7_real_new
wire butterfly_outputs_product_c_p_d_out_0_4 : SInt<19>
wire _butterfly_outputs_product_c_p_d_out_new_WIRE_8 : SInt<19>
node _butterfly_outputs_product_c_p_d_out_new_T_16 = asUInt(twiddle[1].real)
node _butterfly_outputs_product_c_p_d_out_new_T_17 = asSInt(_butterfly_outputs_product_c_p_d_out_new_T_16)
connect _butterfly_outputs_product_c_p_d_out_new_WIRE_8, _butterfly_outputs_product_c_p_d_out_new_T_17
connect butterfly_outputs_product_c_p_d_out_0_4, _butterfly_outputs_product_c_p_d_out_new_WIRE_8
wire butterfly_outputs_product_c_p_d_out_1_4 : SInt<19>
wire _butterfly_outputs_product_c_p_d_out_new_WIRE_9 : SInt<19>
node _butterfly_outputs_product_c_p_d_out_new_T_18 = asUInt(twiddle[1].imag)
node _butterfly_outputs_product_c_p_d_out_new_T_19 = asSInt(_butterfly_outputs_product_c_p_d_out_new_T_18)
connect _butterfly_outputs_product_c_p_d_out_new_WIRE_9, _butterfly_outputs_product_c_p_d_out_new_T_19
connect butterfly_outputs_product_c_p_d_out_1_4, _butterfly_outputs_product_c_p_d_out_new_WIRE_9
wire _butterfly_outputs_product_c_p_d_this_4 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_8 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_12 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_24 = asUInt(butterfly_outputs_product_c_p_d_out_0_4)
node _butterfly_outputs_product_c_p_d_new_T_25 = asSInt(_butterfly_outputs_product_c_p_d_new_T_24)
connect _butterfly_outputs_product_c_p_d_new_WIRE_12, _butterfly_outputs_product_c_p_d_new_T_25
connect _butterfly_outputs_product_c_p_d_new_8, _butterfly_outputs_product_c_p_d_new_WIRE_12
connect _butterfly_outputs_product_c_p_d_this_4, _butterfly_outputs_product_c_p_d_new_8
wire _butterfly_outputs_product_c_p_d_that_4 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_9 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_13 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_26 = asUInt(butterfly_outputs_product_c_p_d_out_1_4)
node _butterfly_outputs_product_c_p_d_new_T_27 = asSInt(_butterfly_outputs_product_c_p_d_new_T_26)
connect _butterfly_outputs_product_c_p_d_new_WIRE_13, _butterfly_outputs_product_c_p_d_new_T_27
connect _butterfly_outputs_product_c_p_d_new_9, _butterfly_outputs_product_c_p_d_new_WIRE_13
connect _butterfly_outputs_product_c_p_d_that_4, _butterfly_outputs_product_c_p_d_new_9
node _butterfly_outputs_product_c_p_d_T_12 = add(_butterfly_outputs_product_c_p_d_this_4, _butterfly_outputs_product_c_p_d_that_4)
node _butterfly_outputs_product_c_p_d_T_13 = tail(_butterfly_outputs_product_c_p_d_T_12, 1)
node _butterfly_outputs_product_c_p_d_T_14 = asSInt(_butterfly_outputs_product_c_p_d_T_13)
wire butterfly_outputs_product_c_p_d_4 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_14 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_28 = asUInt(_butterfly_outputs_product_c_p_d_T_14)
node _butterfly_outputs_product_c_p_d_new_T_29 = asSInt(_butterfly_outputs_product_c_p_d_new_T_28)
connect _butterfly_outputs_product_c_p_d_new_WIRE_14, _butterfly_outputs_product_c_p_d_new_T_29
connect butterfly_outputs_product_c_p_d_4, _butterfly_outputs_product_c_p_d_new_WIRE_14
wire butterfly_outputs_product_a_p_b_out_0_4 : SInt<16>
wire _butterfly_outputs_product_a_p_b_out_new_WIRE_8 : SInt<16>
node _butterfly_outputs_product_a_p_b_out_new_T_16 = asUInt(stage_outputs_1_2.real)
node _butterfly_outputs_product_a_p_b_out_new_T_17 = asSInt(_butterfly_outputs_product_a_p_b_out_new_T_16)
connect _butterfly_outputs_product_a_p_b_out_new_WIRE_8, _butterfly_outputs_product_a_p_b_out_new_T_17
connect butterfly_outputs_product_a_p_b_out_0_4, _butterfly_outputs_product_a_p_b_out_new_WIRE_8
wire butterfly_outputs_product_a_p_b_out_1_4 : SInt<16>
wire _butterfly_outputs_product_a_p_b_out_new_WIRE_9 : SInt<16>
node _butterfly_outputs_product_a_p_b_out_new_T_18 = asUInt(stage_outputs_1_2.imag)
node _butterfly_outputs_product_a_p_b_out_new_T_19 = asSInt(_butterfly_outputs_product_a_p_b_out_new_T_18)
connect _butterfly_outputs_product_a_p_b_out_new_WIRE_9, _butterfly_outputs_product_a_p_b_out_new_T_19
connect butterfly_outputs_product_a_p_b_out_1_4, _butterfly_outputs_product_a_p_b_out_new_WIRE_9
wire _butterfly_outputs_product_a_p_b_this_4 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_8 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_12 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_24 = asUInt(butterfly_outputs_product_a_p_b_out_0_4)
node _butterfly_outputs_product_a_p_b_new_T_25 = asSInt(_butterfly_outputs_product_a_p_b_new_T_24)
connect _butterfly_outputs_product_a_p_b_new_WIRE_12, _butterfly_outputs_product_a_p_b_new_T_25
connect _butterfly_outputs_product_a_p_b_new_8, _butterfly_outputs_product_a_p_b_new_WIRE_12
connect _butterfly_outputs_product_a_p_b_this_4, _butterfly_outputs_product_a_p_b_new_8
wire _butterfly_outputs_product_a_p_b_that_4 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_9 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_13 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_26 = asUInt(butterfly_outputs_product_a_p_b_out_1_4)
node _butterfly_outputs_product_a_p_b_new_T_27 = asSInt(_butterfly_outputs_product_a_p_b_new_T_26)
connect _butterfly_outputs_product_a_p_b_new_WIRE_13, _butterfly_outputs_product_a_p_b_new_T_27
connect _butterfly_outputs_product_a_p_b_new_9, _butterfly_outputs_product_a_p_b_new_WIRE_13
connect _butterfly_outputs_product_a_p_b_that_4, _butterfly_outputs_product_a_p_b_new_9
node _butterfly_outputs_product_a_p_b_T_12 = add(_butterfly_outputs_product_a_p_b_this_4, _butterfly_outputs_product_a_p_b_that_4)
node _butterfly_outputs_product_a_p_b_T_13 = tail(_butterfly_outputs_product_a_p_b_T_12, 1)
node _butterfly_outputs_product_a_p_b_T_14 = asSInt(_butterfly_outputs_product_a_p_b_T_13)
wire butterfly_outputs_product_a_p_b_4 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_14 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_28 = asUInt(_butterfly_outputs_product_a_p_b_T_14)
node _butterfly_outputs_product_a_p_b_new_T_29 = asSInt(_butterfly_outputs_product_a_p_b_new_T_28)
connect _butterfly_outputs_product_a_p_b_new_WIRE_14, _butterfly_outputs_product_a_p_b_new_T_29
connect butterfly_outputs_product_a_p_b_4, _butterfly_outputs_product_a_p_b_new_WIRE_14
wire butterfly_outputs_product_b_m_a_out_0_4 : SInt<16>
wire _butterfly_outputs_product_b_m_a_out_new_WIRE_8 : SInt<16>
node _butterfly_outputs_product_b_m_a_out_new_T_16 = asUInt(stage_outputs_1_2.imag)
node _butterfly_outputs_product_b_m_a_out_new_T_17 = asSInt(_butterfly_outputs_product_b_m_a_out_new_T_16)
connect _butterfly_outputs_product_b_m_a_out_new_WIRE_8, _butterfly_outputs_product_b_m_a_out_new_T_17
connect butterfly_outputs_product_b_m_a_out_0_4, _butterfly_outputs_product_b_m_a_out_new_WIRE_8
wire butterfly_outputs_product_b_m_a_out_1_4 : SInt<16>
wire _butterfly_outputs_product_b_m_a_out_new_WIRE_9 : SInt<16>
node _butterfly_outputs_product_b_m_a_out_new_T_18 = asUInt(stage_outputs_1_2.real)
node _butterfly_outputs_product_b_m_a_out_new_T_19 = asSInt(_butterfly_outputs_product_b_m_a_out_new_T_18)
connect _butterfly_outputs_product_b_m_a_out_new_WIRE_9, _butterfly_outputs_product_b_m_a_out_new_T_19
connect butterfly_outputs_product_b_m_a_out_1_4, _butterfly_outputs_product_b_m_a_out_new_WIRE_9
wire _butterfly_outputs_product_b_m_a_this_4 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_8 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_12 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_24 = asUInt(butterfly_outputs_product_b_m_a_out_0_4)
node _butterfly_outputs_product_b_m_a_new_T_25 = asSInt(_butterfly_outputs_product_b_m_a_new_T_24)
connect _butterfly_outputs_product_b_m_a_new_WIRE_12, _butterfly_outputs_product_b_m_a_new_T_25
connect _butterfly_outputs_product_b_m_a_new_8, _butterfly_outputs_product_b_m_a_new_WIRE_12
connect _butterfly_outputs_product_b_m_a_this_4, _butterfly_outputs_product_b_m_a_new_8
wire _butterfly_outputs_product_b_m_a_that_4 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_9 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_13 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_26 = asUInt(butterfly_outputs_product_b_m_a_out_1_4)
node _butterfly_outputs_product_b_m_a_new_T_27 = asSInt(_butterfly_outputs_product_b_m_a_new_T_26)
connect _butterfly_outputs_product_b_m_a_new_WIRE_13, _butterfly_outputs_product_b_m_a_new_T_27
connect _butterfly_outputs_product_b_m_a_new_9, _butterfly_outputs_product_b_m_a_new_WIRE_13
connect _butterfly_outputs_product_b_m_a_that_4, _butterfly_outputs_product_b_m_a_new_9
node _butterfly_outputs_product_b_m_a_T_12 = sub(_butterfly_outputs_product_b_m_a_this_4, _butterfly_outputs_product_b_m_a_that_4)
node _butterfly_outputs_product_b_m_a_T_13 = tail(_butterfly_outputs_product_b_m_a_T_12, 1)
node _butterfly_outputs_product_b_m_a_T_14 = asSInt(_butterfly_outputs_product_b_m_a_T_13)
wire butterfly_outputs_product_b_m_a_4 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_14 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_28 = asUInt(_butterfly_outputs_product_b_m_a_T_14)
node _butterfly_outputs_product_b_m_a_new_T_29 = asSInt(_butterfly_outputs_product_b_m_a_new_T_28)
connect _butterfly_outputs_product_b_m_a_new_WIRE_14, _butterfly_outputs_product_b_m_a_new_T_29
connect butterfly_outputs_product_b_m_a_4, _butterfly_outputs_product_b_m_a_new_WIRE_14
node _butterfly_outputs_product_ac_p_ad_T_4 = mul(stage_outputs_1_2.real, butterfly_outputs_product_c_p_d_4)
wire butterfly_outputs_product_ac_p_ad_4 : SInt<35>
wire _butterfly_outputs_product_ac_p_ad_new_WIRE_4 : SInt<35>
node _butterfly_outputs_product_ac_p_ad_new_T_8 = asUInt(_butterfly_outputs_product_ac_p_ad_T_4)
node _butterfly_outputs_product_ac_p_ad_new_T_9 = asSInt(_butterfly_outputs_product_ac_p_ad_new_T_8)
connect _butterfly_outputs_product_ac_p_ad_new_WIRE_4, _butterfly_outputs_product_ac_p_ad_new_T_9
connect butterfly_outputs_product_ac_p_ad_4, _butterfly_outputs_product_ac_p_ad_new_WIRE_4
node _butterfly_outputs_product_ad_p_bd_T_4 = mul(butterfly_outputs_product_a_p_b_4, twiddle[1].imag)
wire butterfly_outputs_product_ad_p_bd_4 : SInt<35>
wire _butterfly_outputs_product_ad_p_bd_new_WIRE_4 : SInt<35>
node _butterfly_outputs_product_ad_p_bd_new_T_8 = asUInt(_butterfly_outputs_product_ad_p_bd_T_4)
node _butterfly_outputs_product_ad_p_bd_new_T_9 = asSInt(_butterfly_outputs_product_ad_p_bd_new_T_8)
connect _butterfly_outputs_product_ad_p_bd_new_WIRE_4, _butterfly_outputs_product_ad_p_bd_new_T_9
connect butterfly_outputs_product_ad_p_bd_4, _butterfly_outputs_product_ad_p_bd_new_WIRE_4
node _butterfly_outputs_product_bc_m_ac_T_4 = mul(butterfly_outputs_product_b_m_a_4, twiddle[1].real)
wire butterfly_outputs_product_bc_m_ac_4 : SInt<35>
wire _butterfly_outputs_product_bc_m_ac_new_WIRE_4 : SInt<35>
node _butterfly_outputs_product_bc_m_ac_new_T_8 = asUInt(_butterfly_outputs_product_bc_m_ac_T_4)
node _butterfly_outputs_product_bc_m_ac_new_T_9 = asSInt(_butterfly_outputs_product_bc_m_ac_new_T_8)
connect _butterfly_outputs_product_bc_m_ac_new_WIRE_4, _butterfly_outputs_product_bc_m_ac_new_T_9
connect butterfly_outputs_product_bc_m_ac_4, _butterfly_outputs_product_bc_m_ac_new_WIRE_4
wire butterfly_outputs_product_out_0_8 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_16 : SInt<35>
node _butterfly_outputs_product_out_new_T_32 = asUInt(butterfly_outputs_product_ac_p_ad_4)
node _butterfly_outputs_product_out_new_T_33 = asSInt(_butterfly_outputs_product_out_new_T_32)
connect _butterfly_outputs_product_out_new_WIRE_16, _butterfly_outputs_product_out_new_T_33
connect butterfly_outputs_product_out_0_8, _butterfly_outputs_product_out_new_WIRE_16
wire butterfly_outputs_product_out_1_8 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_17 : SInt<35>
node _butterfly_outputs_product_out_new_T_34 = asUInt(butterfly_outputs_product_ad_p_bd_4)
node _butterfly_outputs_product_out_new_T_35 = asSInt(_butterfly_outputs_product_out_new_T_34)
connect _butterfly_outputs_product_out_new_WIRE_17, _butterfly_outputs_product_out_new_T_35
connect butterfly_outputs_product_out_1_8, _butterfly_outputs_product_out_new_WIRE_17
wire _butterfly_outputs_product_this_8 : SInt<35>
wire _butterfly_outputs_product_new_24 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_24 : SInt<35>
node _butterfly_outputs_product_new_T_48 = asUInt(butterfly_outputs_product_out_0_8)
node _butterfly_outputs_product_new_T_49 = asSInt(_butterfly_outputs_product_new_T_48)
connect _butterfly_outputs_product_new_WIRE_24, _butterfly_outputs_product_new_T_49
connect _butterfly_outputs_product_new_24, _butterfly_outputs_product_new_WIRE_24
connect _butterfly_outputs_product_this_8, _butterfly_outputs_product_new_24
wire _butterfly_outputs_product_that_8 : SInt<35>
wire _butterfly_outputs_product_new_25 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_25 : SInt<35>
node _butterfly_outputs_product_new_T_50 = asUInt(butterfly_outputs_product_out_1_8)
node _butterfly_outputs_product_new_T_51 = asSInt(_butterfly_outputs_product_new_T_50)
connect _butterfly_outputs_product_new_WIRE_25, _butterfly_outputs_product_new_T_51
connect _butterfly_outputs_product_new_25, _butterfly_outputs_product_new_WIRE_25
connect _butterfly_outputs_product_that_8, _butterfly_outputs_product_new_25
node _butterfly_outputs_product_T_24 = sub(_butterfly_outputs_product_this_8, _butterfly_outputs_product_that_8)
node _butterfly_outputs_product_T_25 = tail(_butterfly_outputs_product_T_24, 1)
node _butterfly_outputs_product_T_26 = asSInt(_butterfly_outputs_product_T_25)
wire _butterfly_outputs_product_new_26 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_26 : SInt<35>
node _butterfly_outputs_product_new_T_52 = asUInt(_butterfly_outputs_product_T_26)
node _butterfly_outputs_product_new_T_53 = asSInt(_butterfly_outputs_product_new_T_52)
connect _butterfly_outputs_product_new_WIRE_26, _butterfly_outputs_product_new_T_53
connect _butterfly_outputs_product_new_26, _butterfly_outputs_product_new_WIRE_26
wire butterfly_outputs_product_out_0_9 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_18 : SInt<35>
node _butterfly_outputs_product_out_new_T_36 = asUInt(butterfly_outputs_product_ac_p_ad_4)
node _butterfly_outputs_product_out_new_T_37 = asSInt(_butterfly_outputs_product_out_new_T_36)
connect _butterfly_outputs_product_out_new_WIRE_18, _butterfly_outputs_product_out_new_T_37
connect butterfly_outputs_product_out_0_9, _butterfly_outputs_product_out_new_WIRE_18
wire butterfly_outputs_product_out_1_9 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_19 : SInt<35>
node _butterfly_outputs_product_out_new_T_38 = asUInt(butterfly_outputs_product_bc_m_ac_4)
node _butterfly_outputs_product_out_new_T_39 = asSInt(_butterfly_outputs_product_out_new_T_38)
connect _butterfly_outputs_product_out_new_WIRE_19, _butterfly_outputs_product_out_new_T_39
connect butterfly_outputs_product_out_1_9, _butterfly_outputs_product_out_new_WIRE_19
wire _butterfly_outputs_product_this_9 : SInt<35>
wire _butterfly_outputs_product_new_27 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_27 : SInt<35>
node _butterfly_outputs_product_new_T_54 = asUInt(butterfly_outputs_product_out_0_9)
node _butterfly_outputs_product_new_T_55 = asSInt(_butterfly_outputs_product_new_T_54)
connect _butterfly_outputs_product_new_WIRE_27, _butterfly_outputs_product_new_T_55
connect _butterfly_outputs_product_new_27, _butterfly_outputs_product_new_WIRE_27
connect _butterfly_outputs_product_this_9, _butterfly_outputs_product_new_27
wire _butterfly_outputs_product_that_9 : SInt<35>
wire _butterfly_outputs_product_new_28 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_28 : SInt<35>
node _butterfly_outputs_product_new_T_56 = asUInt(butterfly_outputs_product_out_1_9)
node _butterfly_outputs_product_new_T_57 = asSInt(_butterfly_outputs_product_new_T_56)
connect _butterfly_outputs_product_new_WIRE_28, _butterfly_outputs_product_new_T_57
connect _butterfly_outputs_product_new_28, _butterfly_outputs_product_new_WIRE_28
connect _butterfly_outputs_product_that_9, _butterfly_outputs_product_new_28
node _butterfly_outputs_product_T_27 = add(_butterfly_outputs_product_this_9, _butterfly_outputs_product_that_9)
node _butterfly_outputs_product_T_28 = tail(_butterfly_outputs_product_T_27, 1)
node _butterfly_outputs_product_T_29 = asSInt(_butterfly_outputs_product_T_28)
wire _butterfly_outputs_product_new_29 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_29 : SInt<35>
node _butterfly_outputs_product_new_T_58 = asUInt(_butterfly_outputs_product_T_29)
node _butterfly_outputs_product_new_T_59 = asSInt(_butterfly_outputs_product_new_T_58)
connect _butterfly_outputs_product_new_WIRE_29, _butterfly_outputs_product_new_T_59
connect _butterfly_outputs_product_new_29, _butterfly_outputs_product_new_WIRE_29
wire butterfly_outputs_product_4 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_product_result_real_new_4 : SInt<35>
wire _butterfly_outputs_product_result_real_new_WIRE_4 : SInt<35>
node _butterfly_outputs_product_result_real_new_T_8 = asUInt(_butterfly_outputs_product_new_26)
node _butterfly_outputs_product_result_real_new_T_9 = asSInt(_butterfly_outputs_product_result_real_new_T_8)
connect _butterfly_outputs_product_result_real_new_WIRE_4, _butterfly_outputs_product_result_real_new_T_9
connect _butterfly_outputs_product_result_real_new_4, _butterfly_outputs_product_result_real_new_WIRE_4
connect butterfly_outputs_product_4.real, _butterfly_outputs_product_result_real_new_4
wire _butterfly_outputs_product_result_imag_new_4 : SInt<35>
wire _butterfly_outputs_product_result_imag_new_WIRE_4 : SInt<35>
node _butterfly_outputs_product_result_imag_new_T_8 = asUInt(_butterfly_outputs_product_new_29)
node _butterfly_outputs_product_result_imag_new_T_9 = asSInt(_butterfly_outputs_product_result_imag_new_T_8)
connect _butterfly_outputs_product_result_imag_new_WIRE_4, _butterfly_outputs_product_result_imag_new_T_9
connect _butterfly_outputs_product_result_imag_new_4, _butterfly_outputs_product_result_imag_new_WIRE_4
connect butterfly_outputs_product_4.imag, _butterfly_outputs_product_result_imag_new_4
node _butterfly_outputs_out_T_16 = shl(stage_outputs_1_0.real, 17)
wire butterfly_outputs_out_0_16 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_32 : SInt<35>
node _butterfly_outputs_out_new_T_64 = asUInt(_butterfly_outputs_out_T_16)
node _butterfly_outputs_out_new_T_65 = asSInt(_butterfly_outputs_out_new_T_64)
connect _butterfly_outputs_out_new_WIRE_32, _butterfly_outputs_out_new_T_65
connect butterfly_outputs_out_0_16, _butterfly_outputs_out_new_WIRE_32
wire butterfly_outputs_out_1_16 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_33 : SInt<35>
node _butterfly_outputs_out_new_T_66 = asUInt(butterfly_outputs_product_4.real)
node _butterfly_outputs_out_new_T_67 = asSInt(_butterfly_outputs_out_new_T_66)
connect _butterfly_outputs_out_new_WIRE_33, _butterfly_outputs_out_new_T_67
connect butterfly_outputs_out_1_16, _butterfly_outputs_out_new_WIRE_33
wire _butterfly_outputs_this_16 : SInt<35>
wire _butterfly_outputs_new_48 : SInt<35>
wire _butterfly_outputs_new_WIRE_48 : SInt<35>
node _butterfly_outputs_new_T_96 = asUInt(butterfly_outputs_out_0_16)
node _butterfly_outputs_new_T_97 = asSInt(_butterfly_outputs_new_T_96)
connect _butterfly_outputs_new_WIRE_48, _butterfly_outputs_new_T_97
connect _butterfly_outputs_new_48, _butterfly_outputs_new_WIRE_48
connect _butterfly_outputs_this_16, _butterfly_outputs_new_48
wire _butterfly_outputs_that_16 : SInt<35>
wire _butterfly_outputs_new_49 : SInt<35>
wire _butterfly_outputs_new_WIRE_49 : SInt<35>
node _butterfly_outputs_new_T_98 = asUInt(butterfly_outputs_out_1_16)
node _butterfly_outputs_new_T_99 = asSInt(_butterfly_outputs_new_T_98)
connect _butterfly_outputs_new_WIRE_49, _butterfly_outputs_new_T_99
connect _butterfly_outputs_new_49, _butterfly_outputs_new_WIRE_49
connect _butterfly_outputs_that_16, _butterfly_outputs_new_49
node _butterfly_outputs_T_48 = add(_butterfly_outputs_this_16, _butterfly_outputs_that_16)
node _butterfly_outputs_T_49 = tail(_butterfly_outputs_T_48, 1)
node _butterfly_outputs_T_50 = asSInt(_butterfly_outputs_T_49)
wire _butterfly_outputs_new_50 : SInt<35>
wire _butterfly_outputs_new_WIRE_50 : SInt<35>
node _butterfly_outputs_new_T_100 = asUInt(_butterfly_outputs_T_50)
node _butterfly_outputs_new_T_101 = asSInt(_butterfly_outputs_new_T_100)
connect _butterfly_outputs_new_WIRE_50, _butterfly_outputs_new_T_101
connect _butterfly_outputs_new_50, _butterfly_outputs_new_WIRE_50
node _butterfly_outputs_out_T_17 = shl(stage_outputs_1_0.imag, 17)
wire butterfly_outputs_out_0_17 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_34 : SInt<35>
node _butterfly_outputs_out_new_T_68 = asUInt(_butterfly_outputs_out_T_17)
node _butterfly_outputs_out_new_T_69 = asSInt(_butterfly_outputs_out_new_T_68)
connect _butterfly_outputs_out_new_WIRE_34, _butterfly_outputs_out_new_T_69
connect butterfly_outputs_out_0_17, _butterfly_outputs_out_new_WIRE_34
wire butterfly_outputs_out_1_17 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_35 : SInt<35>
node _butterfly_outputs_out_new_T_70 = asUInt(butterfly_outputs_product_4.imag)
node _butterfly_outputs_out_new_T_71 = asSInt(_butterfly_outputs_out_new_T_70)
connect _butterfly_outputs_out_new_WIRE_35, _butterfly_outputs_out_new_T_71
connect butterfly_outputs_out_1_17, _butterfly_outputs_out_new_WIRE_35
wire _butterfly_outputs_this_17 : SInt<35>
wire _butterfly_outputs_new_51 : SInt<35>
wire _butterfly_outputs_new_WIRE_51 : SInt<35>
node _butterfly_outputs_new_T_102 = asUInt(butterfly_outputs_out_0_17)
node _butterfly_outputs_new_T_103 = asSInt(_butterfly_outputs_new_T_102)
connect _butterfly_outputs_new_WIRE_51, _butterfly_outputs_new_T_103
connect _butterfly_outputs_new_51, _butterfly_outputs_new_WIRE_51
connect _butterfly_outputs_this_17, _butterfly_outputs_new_51
wire _butterfly_outputs_that_17 : SInt<35>
wire _butterfly_outputs_new_52 : SInt<35>
wire _butterfly_outputs_new_WIRE_52 : SInt<35>
node _butterfly_outputs_new_T_104 = asUInt(butterfly_outputs_out_1_17)
node _butterfly_outputs_new_T_105 = asSInt(_butterfly_outputs_new_T_104)
connect _butterfly_outputs_new_WIRE_52, _butterfly_outputs_new_T_105
connect _butterfly_outputs_new_52, _butterfly_outputs_new_WIRE_52
connect _butterfly_outputs_that_17, _butterfly_outputs_new_52
node _butterfly_outputs_T_51 = add(_butterfly_outputs_this_17, _butterfly_outputs_that_17)
node _butterfly_outputs_T_52 = tail(_butterfly_outputs_T_51, 1)
node _butterfly_outputs_T_53 = asSInt(_butterfly_outputs_T_52)
wire _butterfly_outputs_new_53 : SInt<35>
wire _butterfly_outputs_new_WIRE_53 : SInt<35>
node _butterfly_outputs_new_T_106 = asUInt(_butterfly_outputs_T_53)
node _butterfly_outputs_new_T_107 = asSInt(_butterfly_outputs_new_T_106)
connect _butterfly_outputs_new_WIRE_53, _butterfly_outputs_new_T_107
connect _butterfly_outputs_new_53, _butterfly_outputs_new_WIRE_53
wire butterfly_outputs_0_4 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_result_real_new_8 : SInt<35>
wire _butterfly_outputs_result_real_new_WIRE_8 : SInt<35>
node _butterfly_outputs_result_real_new_T_16 = asUInt(_butterfly_outputs_new_50)
node _butterfly_outputs_result_real_new_T_17 = asSInt(_butterfly_outputs_result_real_new_T_16)
connect _butterfly_outputs_result_real_new_WIRE_8, _butterfly_outputs_result_real_new_T_17
connect _butterfly_outputs_result_real_new_8, _butterfly_outputs_result_real_new_WIRE_8
connect butterfly_outputs_0_4.real, _butterfly_outputs_result_real_new_8
wire _butterfly_outputs_result_imag_new_8 : SInt<35>
wire _butterfly_outputs_result_imag_new_WIRE_8 : SInt<35>
node _butterfly_outputs_result_imag_new_T_16 = asUInt(_butterfly_outputs_new_53)
node _butterfly_outputs_result_imag_new_T_17 = asSInt(_butterfly_outputs_result_imag_new_T_16)
connect _butterfly_outputs_result_imag_new_WIRE_8, _butterfly_outputs_result_imag_new_T_17
connect _butterfly_outputs_result_imag_new_8, _butterfly_outputs_result_imag_new_WIRE_8
connect butterfly_outputs_0_4.imag, _butterfly_outputs_result_imag_new_8
node _butterfly_outputs_out_T_18 = shl(stage_outputs_1_0.real, 17)
wire butterfly_outputs_out_0_18 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_36 : SInt<35>
node _butterfly_outputs_out_new_T_72 = asUInt(_butterfly_outputs_out_T_18)
node _butterfly_outputs_out_new_T_73 = asSInt(_butterfly_outputs_out_new_T_72)
connect _butterfly_outputs_out_new_WIRE_36, _butterfly_outputs_out_new_T_73
connect butterfly_outputs_out_0_18, _butterfly_outputs_out_new_WIRE_36
wire butterfly_outputs_out_1_18 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_37 : SInt<35>
node _butterfly_outputs_out_new_T_74 = asUInt(butterfly_outputs_product_4.real)
node _butterfly_outputs_out_new_T_75 = asSInt(_butterfly_outputs_out_new_T_74)
connect _butterfly_outputs_out_new_WIRE_37, _butterfly_outputs_out_new_T_75
connect butterfly_outputs_out_1_18, _butterfly_outputs_out_new_WIRE_37
wire _butterfly_outputs_this_18 : SInt<35>
wire _butterfly_outputs_new_54 : SInt<35>
wire _butterfly_outputs_new_WIRE_54 : SInt<35>
node _butterfly_outputs_new_T_108 = asUInt(butterfly_outputs_out_0_18)
node _butterfly_outputs_new_T_109 = asSInt(_butterfly_outputs_new_T_108)
connect _butterfly_outputs_new_WIRE_54, _butterfly_outputs_new_T_109
connect _butterfly_outputs_new_54, _butterfly_outputs_new_WIRE_54
connect _butterfly_outputs_this_18, _butterfly_outputs_new_54
wire _butterfly_outputs_that_18 : SInt<35>
wire _butterfly_outputs_new_55 : SInt<35>
wire _butterfly_outputs_new_WIRE_55 : SInt<35>
node _butterfly_outputs_new_T_110 = asUInt(butterfly_outputs_out_1_18)
node _butterfly_outputs_new_T_111 = asSInt(_butterfly_outputs_new_T_110)
connect _butterfly_outputs_new_WIRE_55, _butterfly_outputs_new_T_111
connect _butterfly_outputs_new_55, _butterfly_outputs_new_WIRE_55
connect _butterfly_outputs_that_18, _butterfly_outputs_new_55
node _butterfly_outputs_T_54 = sub(_butterfly_outputs_this_18, _butterfly_outputs_that_18)
node _butterfly_outputs_T_55 = tail(_butterfly_outputs_T_54, 1)
node _butterfly_outputs_T_56 = asSInt(_butterfly_outputs_T_55)
wire _butterfly_outputs_new_56 : SInt<35>
wire _butterfly_outputs_new_WIRE_56 : SInt<35>
node _butterfly_outputs_new_T_112 = asUInt(_butterfly_outputs_T_56)
node _butterfly_outputs_new_T_113 = asSInt(_butterfly_outputs_new_T_112)
connect _butterfly_outputs_new_WIRE_56, _butterfly_outputs_new_T_113
connect _butterfly_outputs_new_56, _butterfly_outputs_new_WIRE_56
node _butterfly_outputs_out_T_19 = shl(stage_outputs_1_0.imag, 17)
wire butterfly_outputs_out_0_19 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_38 : SInt<35>
node _butterfly_outputs_out_new_T_76 = asUInt(_butterfly_outputs_out_T_19)
node _butterfly_outputs_out_new_T_77 = asSInt(_butterfly_outputs_out_new_T_76)
connect _butterfly_outputs_out_new_WIRE_38, _butterfly_outputs_out_new_T_77
connect butterfly_outputs_out_0_19, _butterfly_outputs_out_new_WIRE_38
wire butterfly_outputs_out_1_19 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_39 : SInt<35>
node _butterfly_outputs_out_new_T_78 = asUInt(butterfly_outputs_product_4.imag)
node _butterfly_outputs_out_new_T_79 = asSInt(_butterfly_outputs_out_new_T_78)
connect _butterfly_outputs_out_new_WIRE_39, _butterfly_outputs_out_new_T_79
connect butterfly_outputs_out_1_19, _butterfly_outputs_out_new_WIRE_39
wire _butterfly_outputs_this_19 : SInt<35>
wire _butterfly_outputs_new_57 : SInt<35>
wire _butterfly_outputs_new_WIRE_57 : SInt<35>
node _butterfly_outputs_new_T_114 = asUInt(butterfly_outputs_out_0_19)
node _butterfly_outputs_new_T_115 = asSInt(_butterfly_outputs_new_T_114)
connect _butterfly_outputs_new_WIRE_57, _butterfly_outputs_new_T_115
connect _butterfly_outputs_new_57, _butterfly_outputs_new_WIRE_57
connect _butterfly_outputs_this_19, _butterfly_outputs_new_57
wire _butterfly_outputs_that_19 : SInt<35>
wire _butterfly_outputs_new_58 : SInt<35>
wire _butterfly_outputs_new_WIRE_58 : SInt<35>
node _butterfly_outputs_new_T_116 = asUInt(butterfly_outputs_out_1_19)
node _butterfly_outputs_new_T_117 = asSInt(_butterfly_outputs_new_T_116)
connect _butterfly_outputs_new_WIRE_58, _butterfly_outputs_new_T_117
connect _butterfly_outputs_new_58, _butterfly_outputs_new_WIRE_58
connect _butterfly_outputs_that_19, _butterfly_outputs_new_58
node _butterfly_outputs_T_57 = sub(_butterfly_outputs_this_19, _butterfly_outputs_that_19)
node _butterfly_outputs_T_58 = tail(_butterfly_outputs_T_57, 1)
node _butterfly_outputs_T_59 = asSInt(_butterfly_outputs_T_58)
wire _butterfly_outputs_new_59 : SInt<35>
wire _butterfly_outputs_new_WIRE_59 : SInt<35>
node _butterfly_outputs_new_T_118 = asUInt(_butterfly_outputs_T_59)
node _butterfly_outputs_new_T_119 = asSInt(_butterfly_outputs_new_T_118)
connect _butterfly_outputs_new_WIRE_59, _butterfly_outputs_new_T_119
connect _butterfly_outputs_new_59, _butterfly_outputs_new_WIRE_59
wire butterfly_outputs_1_4 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_result_real_new_9 : SInt<35>
wire _butterfly_outputs_result_real_new_WIRE_9 : SInt<35>
node _butterfly_outputs_result_real_new_T_18 = asUInt(_butterfly_outputs_new_56)
node _butterfly_outputs_result_real_new_T_19 = asSInt(_butterfly_outputs_result_real_new_T_18)
connect _butterfly_outputs_result_real_new_WIRE_9, _butterfly_outputs_result_real_new_T_19
connect _butterfly_outputs_result_real_new_9, _butterfly_outputs_result_real_new_WIRE_9
connect butterfly_outputs_1_4.real, _butterfly_outputs_result_real_new_9
wire _butterfly_outputs_result_imag_new_9 : SInt<35>
wire _butterfly_outputs_result_imag_new_WIRE_9 : SInt<35>
node _butterfly_outputs_result_imag_new_T_18 = asUInt(_butterfly_outputs_new_59)
node _butterfly_outputs_result_imag_new_T_19 = asSInt(_butterfly_outputs_result_imag_new_T_18)
connect _butterfly_outputs_result_imag_new_WIRE_9, _butterfly_outputs_result_imag_new_T_19
connect _butterfly_outputs_result_imag_new_9, _butterfly_outputs_result_imag_new_WIRE_9
connect butterfly_outputs_1_4.imag, _butterfly_outputs_result_imag_new_9
node _stage_outputs_2_0_stage_outputs_2_0_imag_T = shr(butterfly_outputs_0_4.imag, 17)
wire _stage_outputs_2_0_stage_outputs_2_0_imag_new : SInt<18>
wire _stage_outputs_2_0_stage_outputs_2_0_imag_new_WIRE : SInt<18>
node _stage_outputs_2_0_stage_outputs_2_0_imag_new_T = asUInt(_stage_outputs_2_0_stage_outputs_2_0_imag_T)
node _stage_outputs_2_0_stage_outputs_2_0_imag_new_T_1 = asSInt(_stage_outputs_2_0_stage_outputs_2_0_imag_new_T)
connect _stage_outputs_2_0_stage_outputs_2_0_imag_new_WIRE, _stage_outputs_2_0_stage_outputs_2_0_imag_new_T_1
connect _stage_outputs_2_0_stage_outputs_2_0_imag_new, _stage_outputs_2_0_stage_outputs_2_0_imag_new_WIRE
connect stage_outputs_2_0.imag, _stage_outputs_2_0_stage_outputs_2_0_imag_new
node _stage_outputs_2_0_stage_outputs_2_0_real_T = shr(butterfly_outputs_0_4.real, 17)
wire _stage_outputs_2_0_stage_outputs_2_0_real_new : SInt<18>
wire _stage_outputs_2_0_stage_outputs_2_0_real_new_WIRE : SInt<18>
node _stage_outputs_2_0_stage_outputs_2_0_real_new_T = asUInt(_stage_outputs_2_0_stage_outputs_2_0_real_T)
node _stage_outputs_2_0_stage_outputs_2_0_real_new_T_1 = asSInt(_stage_outputs_2_0_stage_outputs_2_0_real_new_T)
connect _stage_outputs_2_0_stage_outputs_2_0_real_new_WIRE, _stage_outputs_2_0_stage_outputs_2_0_real_new_T_1
connect _stage_outputs_2_0_stage_outputs_2_0_real_new, _stage_outputs_2_0_stage_outputs_2_0_real_new_WIRE
connect stage_outputs_2_0.real, _stage_outputs_2_0_stage_outputs_2_0_real_new
node _stage_outputs_2_2_stage_outputs_2_2_imag_T = shr(butterfly_outputs_1_4.imag, 17)
wire _stage_outputs_2_2_stage_outputs_2_2_imag_new : SInt<18>
wire _stage_outputs_2_2_stage_outputs_2_2_imag_new_WIRE : SInt<18>
node _stage_outputs_2_2_stage_outputs_2_2_imag_new_T = asUInt(_stage_outputs_2_2_stage_outputs_2_2_imag_T)
node _stage_outputs_2_2_stage_outputs_2_2_imag_new_T_1 = asSInt(_stage_outputs_2_2_stage_outputs_2_2_imag_new_T)
connect _stage_outputs_2_2_stage_outputs_2_2_imag_new_WIRE, _stage_outputs_2_2_stage_outputs_2_2_imag_new_T_1
connect _stage_outputs_2_2_stage_outputs_2_2_imag_new, _stage_outputs_2_2_stage_outputs_2_2_imag_new_WIRE
connect stage_outputs_2_2.imag, _stage_outputs_2_2_stage_outputs_2_2_imag_new
node _stage_outputs_2_2_stage_outputs_2_2_real_T = shr(butterfly_outputs_1_4.real, 17)
wire _stage_outputs_2_2_stage_outputs_2_2_real_new : SInt<18>
wire _stage_outputs_2_2_stage_outputs_2_2_real_new_WIRE : SInt<18>
node _stage_outputs_2_2_stage_outputs_2_2_real_new_T = asUInt(_stage_outputs_2_2_stage_outputs_2_2_real_T)
node _stage_outputs_2_2_stage_outputs_2_2_real_new_T_1 = asSInt(_stage_outputs_2_2_stage_outputs_2_2_real_new_T)
connect _stage_outputs_2_2_stage_outputs_2_2_real_new_WIRE, _stage_outputs_2_2_stage_outputs_2_2_real_new_T_1
connect _stage_outputs_2_2_stage_outputs_2_2_real_new, _stage_outputs_2_2_stage_outputs_2_2_real_new_WIRE
connect stage_outputs_2_2.real, _stage_outputs_2_2_stage_outputs_2_2_real_new
wire butterfly_outputs_product_c_p_d_out_0_5 : SInt<19>
wire _butterfly_outputs_product_c_p_d_out_new_WIRE_10 : SInt<19>
node _butterfly_outputs_product_c_p_d_out_new_T_20 = asUInt(twiddle[1].real)
node _butterfly_outputs_product_c_p_d_out_new_T_21 = asSInt(_butterfly_outputs_product_c_p_d_out_new_T_20)
connect _butterfly_outputs_product_c_p_d_out_new_WIRE_10, _butterfly_outputs_product_c_p_d_out_new_T_21
connect butterfly_outputs_product_c_p_d_out_0_5, _butterfly_outputs_product_c_p_d_out_new_WIRE_10
wire butterfly_outputs_product_c_p_d_out_1_5 : SInt<19>
wire _butterfly_outputs_product_c_p_d_out_new_WIRE_11 : SInt<19>
node _butterfly_outputs_product_c_p_d_out_new_T_22 = asUInt(twiddle[1].imag)
node _butterfly_outputs_product_c_p_d_out_new_T_23 = asSInt(_butterfly_outputs_product_c_p_d_out_new_T_22)
connect _butterfly_outputs_product_c_p_d_out_new_WIRE_11, _butterfly_outputs_product_c_p_d_out_new_T_23
connect butterfly_outputs_product_c_p_d_out_1_5, _butterfly_outputs_product_c_p_d_out_new_WIRE_11
wire _butterfly_outputs_product_c_p_d_this_5 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_10 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_15 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_30 = asUInt(butterfly_outputs_product_c_p_d_out_0_5)
node _butterfly_outputs_product_c_p_d_new_T_31 = asSInt(_butterfly_outputs_product_c_p_d_new_T_30)
connect _butterfly_outputs_product_c_p_d_new_WIRE_15, _butterfly_outputs_product_c_p_d_new_T_31
connect _butterfly_outputs_product_c_p_d_new_10, _butterfly_outputs_product_c_p_d_new_WIRE_15
connect _butterfly_outputs_product_c_p_d_this_5, _butterfly_outputs_product_c_p_d_new_10
wire _butterfly_outputs_product_c_p_d_that_5 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_11 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_16 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_32 = asUInt(butterfly_outputs_product_c_p_d_out_1_5)
node _butterfly_outputs_product_c_p_d_new_T_33 = asSInt(_butterfly_outputs_product_c_p_d_new_T_32)
connect _butterfly_outputs_product_c_p_d_new_WIRE_16, _butterfly_outputs_product_c_p_d_new_T_33
connect _butterfly_outputs_product_c_p_d_new_11, _butterfly_outputs_product_c_p_d_new_WIRE_16
connect _butterfly_outputs_product_c_p_d_that_5, _butterfly_outputs_product_c_p_d_new_11
node _butterfly_outputs_product_c_p_d_T_15 = add(_butterfly_outputs_product_c_p_d_this_5, _butterfly_outputs_product_c_p_d_that_5)
node _butterfly_outputs_product_c_p_d_T_16 = tail(_butterfly_outputs_product_c_p_d_T_15, 1)
node _butterfly_outputs_product_c_p_d_T_17 = asSInt(_butterfly_outputs_product_c_p_d_T_16)
wire butterfly_outputs_product_c_p_d_5 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_17 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_34 = asUInt(_butterfly_outputs_product_c_p_d_T_17)
node _butterfly_outputs_product_c_p_d_new_T_35 = asSInt(_butterfly_outputs_product_c_p_d_new_T_34)
connect _butterfly_outputs_product_c_p_d_new_WIRE_17, _butterfly_outputs_product_c_p_d_new_T_35
connect butterfly_outputs_product_c_p_d_5, _butterfly_outputs_product_c_p_d_new_WIRE_17
wire butterfly_outputs_product_a_p_b_out_0_5 : SInt<16>
wire _butterfly_outputs_product_a_p_b_out_new_WIRE_10 : SInt<16>
node _butterfly_outputs_product_a_p_b_out_new_T_20 = asUInt(stage_outputs_1_3.real)
node _butterfly_outputs_product_a_p_b_out_new_T_21 = asSInt(_butterfly_outputs_product_a_p_b_out_new_T_20)
connect _butterfly_outputs_product_a_p_b_out_new_WIRE_10, _butterfly_outputs_product_a_p_b_out_new_T_21
connect butterfly_outputs_product_a_p_b_out_0_5, _butterfly_outputs_product_a_p_b_out_new_WIRE_10
wire butterfly_outputs_product_a_p_b_out_1_5 : SInt<16>
wire _butterfly_outputs_product_a_p_b_out_new_WIRE_11 : SInt<16>
node _butterfly_outputs_product_a_p_b_out_new_T_22 = asUInt(stage_outputs_1_3.imag)
node _butterfly_outputs_product_a_p_b_out_new_T_23 = asSInt(_butterfly_outputs_product_a_p_b_out_new_T_22)
connect _butterfly_outputs_product_a_p_b_out_new_WIRE_11, _butterfly_outputs_product_a_p_b_out_new_T_23
connect butterfly_outputs_product_a_p_b_out_1_5, _butterfly_outputs_product_a_p_b_out_new_WIRE_11
wire _butterfly_outputs_product_a_p_b_this_5 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_10 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_15 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_30 = asUInt(butterfly_outputs_product_a_p_b_out_0_5)
node _butterfly_outputs_product_a_p_b_new_T_31 = asSInt(_butterfly_outputs_product_a_p_b_new_T_30)
connect _butterfly_outputs_product_a_p_b_new_WIRE_15, _butterfly_outputs_product_a_p_b_new_T_31
connect _butterfly_outputs_product_a_p_b_new_10, _butterfly_outputs_product_a_p_b_new_WIRE_15
connect _butterfly_outputs_product_a_p_b_this_5, _butterfly_outputs_product_a_p_b_new_10
wire _butterfly_outputs_product_a_p_b_that_5 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_11 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_16 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_32 = asUInt(butterfly_outputs_product_a_p_b_out_1_5)
node _butterfly_outputs_product_a_p_b_new_T_33 = asSInt(_butterfly_outputs_product_a_p_b_new_T_32)
connect _butterfly_outputs_product_a_p_b_new_WIRE_16, _butterfly_outputs_product_a_p_b_new_T_33
connect _butterfly_outputs_product_a_p_b_new_11, _butterfly_outputs_product_a_p_b_new_WIRE_16
connect _butterfly_outputs_product_a_p_b_that_5, _butterfly_outputs_product_a_p_b_new_11
node _butterfly_outputs_product_a_p_b_T_15 = add(_butterfly_outputs_product_a_p_b_this_5, _butterfly_outputs_product_a_p_b_that_5)
node _butterfly_outputs_product_a_p_b_T_16 = tail(_butterfly_outputs_product_a_p_b_T_15, 1)
node _butterfly_outputs_product_a_p_b_T_17 = asSInt(_butterfly_outputs_product_a_p_b_T_16)
wire butterfly_outputs_product_a_p_b_5 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_17 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_34 = asUInt(_butterfly_outputs_product_a_p_b_T_17)
node _butterfly_outputs_product_a_p_b_new_T_35 = asSInt(_butterfly_outputs_product_a_p_b_new_T_34)
connect _butterfly_outputs_product_a_p_b_new_WIRE_17, _butterfly_outputs_product_a_p_b_new_T_35
connect butterfly_outputs_product_a_p_b_5, _butterfly_outputs_product_a_p_b_new_WIRE_17
wire butterfly_outputs_product_b_m_a_out_0_5 : SInt<16>
wire _butterfly_outputs_product_b_m_a_out_new_WIRE_10 : SInt<16>
node _butterfly_outputs_product_b_m_a_out_new_T_20 = asUInt(stage_outputs_1_3.imag)
node _butterfly_outputs_product_b_m_a_out_new_T_21 = asSInt(_butterfly_outputs_product_b_m_a_out_new_T_20)
connect _butterfly_outputs_product_b_m_a_out_new_WIRE_10, _butterfly_outputs_product_b_m_a_out_new_T_21
connect butterfly_outputs_product_b_m_a_out_0_5, _butterfly_outputs_product_b_m_a_out_new_WIRE_10
wire butterfly_outputs_product_b_m_a_out_1_5 : SInt<16>
wire _butterfly_outputs_product_b_m_a_out_new_WIRE_11 : SInt<16>
node _butterfly_outputs_product_b_m_a_out_new_T_22 = asUInt(stage_outputs_1_3.real)
node _butterfly_outputs_product_b_m_a_out_new_T_23 = asSInt(_butterfly_outputs_product_b_m_a_out_new_T_22)
connect _butterfly_outputs_product_b_m_a_out_new_WIRE_11, _butterfly_outputs_product_b_m_a_out_new_T_23
connect butterfly_outputs_product_b_m_a_out_1_5, _butterfly_outputs_product_b_m_a_out_new_WIRE_11
wire _butterfly_outputs_product_b_m_a_this_5 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_10 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_15 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_30 = asUInt(butterfly_outputs_product_b_m_a_out_0_5)
node _butterfly_outputs_product_b_m_a_new_T_31 = asSInt(_butterfly_outputs_product_b_m_a_new_T_30)
connect _butterfly_outputs_product_b_m_a_new_WIRE_15, _butterfly_outputs_product_b_m_a_new_T_31
connect _butterfly_outputs_product_b_m_a_new_10, _butterfly_outputs_product_b_m_a_new_WIRE_15
connect _butterfly_outputs_product_b_m_a_this_5, _butterfly_outputs_product_b_m_a_new_10
wire _butterfly_outputs_product_b_m_a_that_5 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_11 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_16 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_32 = asUInt(butterfly_outputs_product_b_m_a_out_1_5)
node _butterfly_outputs_product_b_m_a_new_T_33 = asSInt(_butterfly_outputs_product_b_m_a_new_T_32)
connect _butterfly_outputs_product_b_m_a_new_WIRE_16, _butterfly_outputs_product_b_m_a_new_T_33
connect _butterfly_outputs_product_b_m_a_new_11, _butterfly_outputs_product_b_m_a_new_WIRE_16
connect _butterfly_outputs_product_b_m_a_that_5, _butterfly_outputs_product_b_m_a_new_11
node _butterfly_outputs_product_b_m_a_T_15 = sub(_butterfly_outputs_product_b_m_a_this_5, _butterfly_outputs_product_b_m_a_that_5)
node _butterfly_outputs_product_b_m_a_T_16 = tail(_butterfly_outputs_product_b_m_a_T_15, 1)
node _butterfly_outputs_product_b_m_a_T_17 = asSInt(_butterfly_outputs_product_b_m_a_T_16)
wire butterfly_outputs_product_b_m_a_5 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_17 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_34 = asUInt(_butterfly_outputs_product_b_m_a_T_17)
node _butterfly_outputs_product_b_m_a_new_T_35 = asSInt(_butterfly_outputs_product_b_m_a_new_T_34)
connect _butterfly_outputs_product_b_m_a_new_WIRE_17, _butterfly_outputs_product_b_m_a_new_T_35
connect butterfly_outputs_product_b_m_a_5, _butterfly_outputs_product_b_m_a_new_WIRE_17
node _butterfly_outputs_product_ac_p_ad_T_5 = mul(stage_outputs_1_3.real, butterfly_outputs_product_c_p_d_5)
wire butterfly_outputs_product_ac_p_ad_5 : SInt<35>
wire _butterfly_outputs_product_ac_p_ad_new_WIRE_5 : SInt<35>
node _butterfly_outputs_product_ac_p_ad_new_T_10 = asUInt(_butterfly_outputs_product_ac_p_ad_T_5)
node _butterfly_outputs_product_ac_p_ad_new_T_11 = asSInt(_butterfly_outputs_product_ac_p_ad_new_T_10)
connect _butterfly_outputs_product_ac_p_ad_new_WIRE_5, _butterfly_outputs_product_ac_p_ad_new_T_11
connect butterfly_outputs_product_ac_p_ad_5, _butterfly_outputs_product_ac_p_ad_new_WIRE_5
node _butterfly_outputs_product_ad_p_bd_T_5 = mul(butterfly_outputs_product_a_p_b_5, twiddle[1].imag)
wire butterfly_outputs_product_ad_p_bd_5 : SInt<35>
wire _butterfly_outputs_product_ad_p_bd_new_WIRE_5 : SInt<35>
node _butterfly_outputs_product_ad_p_bd_new_T_10 = asUInt(_butterfly_outputs_product_ad_p_bd_T_5)
node _butterfly_outputs_product_ad_p_bd_new_T_11 = asSInt(_butterfly_outputs_product_ad_p_bd_new_T_10)
connect _butterfly_outputs_product_ad_p_bd_new_WIRE_5, _butterfly_outputs_product_ad_p_bd_new_T_11
connect butterfly_outputs_product_ad_p_bd_5, _butterfly_outputs_product_ad_p_bd_new_WIRE_5
node _butterfly_outputs_product_bc_m_ac_T_5 = mul(butterfly_outputs_product_b_m_a_5, twiddle[1].real)
wire butterfly_outputs_product_bc_m_ac_5 : SInt<35>
wire _butterfly_outputs_product_bc_m_ac_new_WIRE_5 : SInt<35>
node _butterfly_outputs_product_bc_m_ac_new_T_10 = asUInt(_butterfly_outputs_product_bc_m_ac_T_5)
node _butterfly_outputs_product_bc_m_ac_new_T_11 = asSInt(_butterfly_outputs_product_bc_m_ac_new_T_10)
connect _butterfly_outputs_product_bc_m_ac_new_WIRE_5, _butterfly_outputs_product_bc_m_ac_new_T_11
connect butterfly_outputs_product_bc_m_ac_5, _butterfly_outputs_product_bc_m_ac_new_WIRE_5
wire butterfly_outputs_product_out_0_10 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_20 : SInt<35>
node _butterfly_outputs_product_out_new_T_40 = asUInt(butterfly_outputs_product_ac_p_ad_5)
node _butterfly_outputs_product_out_new_T_41 = asSInt(_butterfly_outputs_product_out_new_T_40)
connect _butterfly_outputs_product_out_new_WIRE_20, _butterfly_outputs_product_out_new_T_41
connect butterfly_outputs_product_out_0_10, _butterfly_outputs_product_out_new_WIRE_20
wire butterfly_outputs_product_out_1_10 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_21 : SInt<35>
node _butterfly_outputs_product_out_new_T_42 = asUInt(butterfly_outputs_product_ad_p_bd_5)
node _butterfly_outputs_product_out_new_T_43 = asSInt(_butterfly_outputs_product_out_new_T_42)
connect _butterfly_outputs_product_out_new_WIRE_21, _butterfly_outputs_product_out_new_T_43
connect butterfly_outputs_product_out_1_10, _butterfly_outputs_product_out_new_WIRE_21
wire _butterfly_outputs_product_this_10 : SInt<35>
wire _butterfly_outputs_product_new_30 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_30 : SInt<35>
node _butterfly_outputs_product_new_T_60 = asUInt(butterfly_outputs_product_out_0_10)
node _butterfly_outputs_product_new_T_61 = asSInt(_butterfly_outputs_product_new_T_60)
connect _butterfly_outputs_product_new_WIRE_30, _butterfly_outputs_product_new_T_61
connect _butterfly_outputs_product_new_30, _butterfly_outputs_product_new_WIRE_30
connect _butterfly_outputs_product_this_10, _butterfly_outputs_product_new_30
wire _butterfly_outputs_product_that_10 : SInt<35>
wire _butterfly_outputs_product_new_31 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_31 : SInt<35>
node _butterfly_outputs_product_new_T_62 = asUInt(butterfly_outputs_product_out_1_10)
node _butterfly_outputs_product_new_T_63 = asSInt(_butterfly_outputs_product_new_T_62)
connect _butterfly_outputs_product_new_WIRE_31, _butterfly_outputs_product_new_T_63
connect _butterfly_outputs_product_new_31, _butterfly_outputs_product_new_WIRE_31
connect _butterfly_outputs_product_that_10, _butterfly_outputs_product_new_31
node _butterfly_outputs_product_T_30 = sub(_butterfly_outputs_product_this_10, _butterfly_outputs_product_that_10)
node _butterfly_outputs_product_T_31 = tail(_butterfly_outputs_product_T_30, 1)
node _butterfly_outputs_product_T_32 = asSInt(_butterfly_outputs_product_T_31)
wire _butterfly_outputs_product_new_32 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_32 : SInt<35>
node _butterfly_outputs_product_new_T_64 = asUInt(_butterfly_outputs_product_T_32)
node _butterfly_outputs_product_new_T_65 = asSInt(_butterfly_outputs_product_new_T_64)
connect _butterfly_outputs_product_new_WIRE_32, _butterfly_outputs_product_new_T_65
connect _butterfly_outputs_product_new_32, _butterfly_outputs_product_new_WIRE_32
wire butterfly_outputs_product_out_0_11 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_22 : SInt<35>
node _butterfly_outputs_product_out_new_T_44 = asUInt(butterfly_outputs_product_ac_p_ad_5)
node _butterfly_outputs_product_out_new_T_45 = asSInt(_butterfly_outputs_product_out_new_T_44)
connect _butterfly_outputs_product_out_new_WIRE_22, _butterfly_outputs_product_out_new_T_45
connect butterfly_outputs_product_out_0_11, _butterfly_outputs_product_out_new_WIRE_22
wire butterfly_outputs_product_out_1_11 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_23 : SInt<35>
node _butterfly_outputs_product_out_new_T_46 = asUInt(butterfly_outputs_product_bc_m_ac_5)
node _butterfly_outputs_product_out_new_T_47 = asSInt(_butterfly_outputs_product_out_new_T_46)
connect _butterfly_outputs_product_out_new_WIRE_23, _butterfly_outputs_product_out_new_T_47
connect butterfly_outputs_product_out_1_11, _butterfly_outputs_product_out_new_WIRE_23
wire _butterfly_outputs_product_this_11 : SInt<35>
wire _butterfly_outputs_product_new_33 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_33 : SInt<35>
node _butterfly_outputs_product_new_T_66 = asUInt(butterfly_outputs_product_out_0_11)
node _butterfly_outputs_product_new_T_67 = asSInt(_butterfly_outputs_product_new_T_66)
connect _butterfly_outputs_product_new_WIRE_33, _butterfly_outputs_product_new_T_67
connect _butterfly_outputs_product_new_33, _butterfly_outputs_product_new_WIRE_33
connect _butterfly_outputs_product_this_11, _butterfly_outputs_product_new_33
wire _butterfly_outputs_product_that_11 : SInt<35>
wire _butterfly_outputs_product_new_34 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_34 : SInt<35>
node _butterfly_outputs_product_new_T_68 = asUInt(butterfly_outputs_product_out_1_11)
node _butterfly_outputs_product_new_T_69 = asSInt(_butterfly_outputs_product_new_T_68)
connect _butterfly_outputs_product_new_WIRE_34, _butterfly_outputs_product_new_T_69
connect _butterfly_outputs_product_new_34, _butterfly_outputs_product_new_WIRE_34
connect _butterfly_outputs_product_that_11, _butterfly_outputs_product_new_34
node _butterfly_outputs_product_T_33 = add(_butterfly_outputs_product_this_11, _butterfly_outputs_product_that_11)
node _butterfly_outputs_product_T_34 = tail(_butterfly_outputs_product_T_33, 1)
node _butterfly_outputs_product_T_35 = asSInt(_butterfly_outputs_product_T_34)
wire _butterfly_outputs_product_new_35 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_35 : SInt<35>
node _butterfly_outputs_product_new_T_70 = asUInt(_butterfly_outputs_product_T_35)
node _butterfly_outputs_product_new_T_71 = asSInt(_butterfly_outputs_product_new_T_70)
connect _butterfly_outputs_product_new_WIRE_35, _butterfly_outputs_product_new_T_71
connect _butterfly_outputs_product_new_35, _butterfly_outputs_product_new_WIRE_35
wire butterfly_outputs_product_5 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_product_result_real_new_5 : SInt<35>
wire _butterfly_outputs_product_result_real_new_WIRE_5 : SInt<35>
node _butterfly_outputs_product_result_real_new_T_10 = asUInt(_butterfly_outputs_product_new_32)
node _butterfly_outputs_product_result_real_new_T_11 = asSInt(_butterfly_outputs_product_result_real_new_T_10)
connect _butterfly_outputs_product_result_real_new_WIRE_5, _butterfly_outputs_product_result_real_new_T_11
connect _butterfly_outputs_product_result_real_new_5, _butterfly_outputs_product_result_real_new_WIRE_5
connect butterfly_outputs_product_5.real, _butterfly_outputs_product_result_real_new_5
wire _butterfly_outputs_product_result_imag_new_5 : SInt<35>
wire _butterfly_outputs_product_result_imag_new_WIRE_5 : SInt<35>
node _butterfly_outputs_product_result_imag_new_T_10 = asUInt(_butterfly_outputs_product_new_35)
node _butterfly_outputs_product_result_imag_new_T_11 = asSInt(_butterfly_outputs_product_result_imag_new_T_10)
connect _butterfly_outputs_product_result_imag_new_WIRE_5, _butterfly_outputs_product_result_imag_new_T_11
connect _butterfly_outputs_product_result_imag_new_5, _butterfly_outputs_product_result_imag_new_WIRE_5
connect butterfly_outputs_product_5.imag, _butterfly_outputs_product_result_imag_new_5
node _butterfly_outputs_out_T_20 = shl(stage_outputs_1_1.real, 17)
wire butterfly_outputs_out_0_20 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_40 : SInt<35>
node _butterfly_outputs_out_new_T_80 = asUInt(_butterfly_outputs_out_T_20)
node _butterfly_outputs_out_new_T_81 = asSInt(_butterfly_outputs_out_new_T_80)
connect _butterfly_outputs_out_new_WIRE_40, _butterfly_outputs_out_new_T_81
connect butterfly_outputs_out_0_20, _butterfly_outputs_out_new_WIRE_40
wire butterfly_outputs_out_1_20 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_41 : SInt<35>
node _butterfly_outputs_out_new_T_82 = asUInt(butterfly_outputs_product_5.real)
node _butterfly_outputs_out_new_T_83 = asSInt(_butterfly_outputs_out_new_T_82)
connect _butterfly_outputs_out_new_WIRE_41, _butterfly_outputs_out_new_T_83
connect butterfly_outputs_out_1_20, _butterfly_outputs_out_new_WIRE_41
wire _butterfly_outputs_this_20 : SInt<35>
wire _butterfly_outputs_new_60 : SInt<35>
wire _butterfly_outputs_new_WIRE_60 : SInt<35>
node _butterfly_outputs_new_T_120 = asUInt(butterfly_outputs_out_0_20)
node _butterfly_outputs_new_T_121 = asSInt(_butterfly_outputs_new_T_120)
connect _butterfly_outputs_new_WIRE_60, _butterfly_outputs_new_T_121
connect _butterfly_outputs_new_60, _butterfly_outputs_new_WIRE_60
connect _butterfly_outputs_this_20, _butterfly_outputs_new_60
wire _butterfly_outputs_that_20 : SInt<35>
wire _butterfly_outputs_new_61 : SInt<35>
wire _butterfly_outputs_new_WIRE_61 : SInt<35>
node _butterfly_outputs_new_T_122 = asUInt(butterfly_outputs_out_1_20)
node _butterfly_outputs_new_T_123 = asSInt(_butterfly_outputs_new_T_122)
connect _butterfly_outputs_new_WIRE_61, _butterfly_outputs_new_T_123
connect _butterfly_outputs_new_61, _butterfly_outputs_new_WIRE_61
connect _butterfly_outputs_that_20, _butterfly_outputs_new_61
node _butterfly_outputs_T_60 = add(_butterfly_outputs_this_20, _butterfly_outputs_that_20)
node _butterfly_outputs_T_61 = tail(_butterfly_outputs_T_60, 1)
node _butterfly_outputs_T_62 = asSInt(_butterfly_outputs_T_61)
wire _butterfly_outputs_new_62 : SInt<35>
wire _butterfly_outputs_new_WIRE_62 : SInt<35>
node _butterfly_outputs_new_T_124 = asUInt(_butterfly_outputs_T_62)
node _butterfly_outputs_new_T_125 = asSInt(_butterfly_outputs_new_T_124)
connect _butterfly_outputs_new_WIRE_62, _butterfly_outputs_new_T_125
connect _butterfly_outputs_new_62, _butterfly_outputs_new_WIRE_62
node _butterfly_outputs_out_T_21 = shl(stage_outputs_1_1.imag, 17)
wire butterfly_outputs_out_0_21 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_42 : SInt<35>
node _butterfly_outputs_out_new_T_84 = asUInt(_butterfly_outputs_out_T_21)
node _butterfly_outputs_out_new_T_85 = asSInt(_butterfly_outputs_out_new_T_84)
connect _butterfly_outputs_out_new_WIRE_42, _butterfly_outputs_out_new_T_85
connect butterfly_outputs_out_0_21, _butterfly_outputs_out_new_WIRE_42
wire butterfly_outputs_out_1_21 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_43 : SInt<35>
node _butterfly_outputs_out_new_T_86 = asUInt(butterfly_outputs_product_5.imag)
node _butterfly_outputs_out_new_T_87 = asSInt(_butterfly_outputs_out_new_T_86)
connect _butterfly_outputs_out_new_WIRE_43, _butterfly_outputs_out_new_T_87
connect butterfly_outputs_out_1_21, _butterfly_outputs_out_new_WIRE_43
wire _butterfly_outputs_this_21 : SInt<35>
wire _butterfly_outputs_new_63 : SInt<35>
wire _butterfly_outputs_new_WIRE_63 : SInt<35>
node _butterfly_outputs_new_T_126 = asUInt(butterfly_outputs_out_0_21)
node _butterfly_outputs_new_T_127 = asSInt(_butterfly_outputs_new_T_126)
connect _butterfly_outputs_new_WIRE_63, _butterfly_outputs_new_T_127
connect _butterfly_outputs_new_63, _butterfly_outputs_new_WIRE_63
connect _butterfly_outputs_this_21, _butterfly_outputs_new_63
wire _butterfly_outputs_that_21 : SInt<35>
wire _butterfly_outputs_new_64 : SInt<35>
wire _butterfly_outputs_new_WIRE_64 : SInt<35>
node _butterfly_outputs_new_T_128 = asUInt(butterfly_outputs_out_1_21)
node _butterfly_outputs_new_T_129 = asSInt(_butterfly_outputs_new_T_128)
connect _butterfly_outputs_new_WIRE_64, _butterfly_outputs_new_T_129
connect _butterfly_outputs_new_64, _butterfly_outputs_new_WIRE_64
connect _butterfly_outputs_that_21, _butterfly_outputs_new_64
node _butterfly_outputs_T_63 = add(_butterfly_outputs_this_21, _butterfly_outputs_that_21)
node _butterfly_outputs_T_64 = tail(_butterfly_outputs_T_63, 1)
node _butterfly_outputs_T_65 = asSInt(_butterfly_outputs_T_64)
wire _butterfly_outputs_new_65 : SInt<35>
wire _butterfly_outputs_new_WIRE_65 : SInt<35>
node _butterfly_outputs_new_T_130 = asUInt(_butterfly_outputs_T_65)
node _butterfly_outputs_new_T_131 = asSInt(_butterfly_outputs_new_T_130)
connect _butterfly_outputs_new_WIRE_65, _butterfly_outputs_new_T_131
connect _butterfly_outputs_new_65, _butterfly_outputs_new_WIRE_65
wire butterfly_outputs_0_5 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_result_real_new_10 : SInt<35>
wire _butterfly_outputs_result_real_new_WIRE_10 : SInt<35>
node _butterfly_outputs_result_real_new_T_20 = asUInt(_butterfly_outputs_new_62)
node _butterfly_outputs_result_real_new_T_21 = asSInt(_butterfly_outputs_result_real_new_T_20)
connect _butterfly_outputs_result_real_new_WIRE_10, _butterfly_outputs_result_real_new_T_21
connect _butterfly_outputs_result_real_new_10, _butterfly_outputs_result_real_new_WIRE_10
connect butterfly_outputs_0_5.real, _butterfly_outputs_result_real_new_10
wire _butterfly_outputs_result_imag_new_10 : SInt<35>
wire _butterfly_outputs_result_imag_new_WIRE_10 : SInt<35>
node _butterfly_outputs_result_imag_new_T_20 = asUInt(_butterfly_outputs_new_65)
node _butterfly_outputs_result_imag_new_T_21 = asSInt(_butterfly_outputs_result_imag_new_T_20)
connect _butterfly_outputs_result_imag_new_WIRE_10, _butterfly_outputs_result_imag_new_T_21
connect _butterfly_outputs_result_imag_new_10, _butterfly_outputs_result_imag_new_WIRE_10
connect butterfly_outputs_0_5.imag, _butterfly_outputs_result_imag_new_10
node _butterfly_outputs_out_T_22 = shl(stage_outputs_1_1.real, 17)
wire butterfly_outputs_out_0_22 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_44 : SInt<35>
node _butterfly_outputs_out_new_T_88 = asUInt(_butterfly_outputs_out_T_22)
node _butterfly_outputs_out_new_T_89 = asSInt(_butterfly_outputs_out_new_T_88)
connect _butterfly_outputs_out_new_WIRE_44, _butterfly_outputs_out_new_T_89
connect butterfly_outputs_out_0_22, _butterfly_outputs_out_new_WIRE_44
wire butterfly_outputs_out_1_22 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_45 : SInt<35>
node _butterfly_outputs_out_new_T_90 = asUInt(butterfly_outputs_product_5.real)
node _butterfly_outputs_out_new_T_91 = asSInt(_butterfly_outputs_out_new_T_90)
connect _butterfly_outputs_out_new_WIRE_45, _butterfly_outputs_out_new_T_91
connect butterfly_outputs_out_1_22, _butterfly_outputs_out_new_WIRE_45
wire _butterfly_outputs_this_22 : SInt<35>
wire _butterfly_outputs_new_66 : SInt<35>
wire _butterfly_outputs_new_WIRE_66 : SInt<35>
node _butterfly_outputs_new_T_132 = asUInt(butterfly_outputs_out_0_22)
node _butterfly_outputs_new_T_133 = asSInt(_butterfly_outputs_new_T_132)
connect _butterfly_outputs_new_WIRE_66, _butterfly_outputs_new_T_133
connect _butterfly_outputs_new_66, _butterfly_outputs_new_WIRE_66
connect _butterfly_outputs_this_22, _butterfly_outputs_new_66
wire _butterfly_outputs_that_22 : SInt<35>
wire _butterfly_outputs_new_67 : SInt<35>
wire _butterfly_outputs_new_WIRE_67 : SInt<35>
node _butterfly_outputs_new_T_134 = asUInt(butterfly_outputs_out_1_22)
node _butterfly_outputs_new_T_135 = asSInt(_butterfly_outputs_new_T_134)
connect _butterfly_outputs_new_WIRE_67, _butterfly_outputs_new_T_135
connect _butterfly_outputs_new_67, _butterfly_outputs_new_WIRE_67
connect _butterfly_outputs_that_22, _butterfly_outputs_new_67
node _butterfly_outputs_T_66 = sub(_butterfly_outputs_this_22, _butterfly_outputs_that_22)
node _butterfly_outputs_T_67 = tail(_butterfly_outputs_T_66, 1)
node _butterfly_outputs_T_68 = asSInt(_butterfly_outputs_T_67)
wire _butterfly_outputs_new_68 : SInt<35>
wire _butterfly_outputs_new_WIRE_68 : SInt<35>
node _butterfly_outputs_new_T_136 = asUInt(_butterfly_outputs_T_68)
node _butterfly_outputs_new_T_137 = asSInt(_butterfly_outputs_new_T_136)
connect _butterfly_outputs_new_WIRE_68, _butterfly_outputs_new_T_137
connect _butterfly_outputs_new_68, _butterfly_outputs_new_WIRE_68
node _butterfly_outputs_out_T_23 = shl(stage_outputs_1_1.imag, 17)
wire butterfly_outputs_out_0_23 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_46 : SInt<35>
node _butterfly_outputs_out_new_T_92 = asUInt(_butterfly_outputs_out_T_23)
node _butterfly_outputs_out_new_T_93 = asSInt(_butterfly_outputs_out_new_T_92)
connect _butterfly_outputs_out_new_WIRE_46, _butterfly_outputs_out_new_T_93
connect butterfly_outputs_out_0_23, _butterfly_outputs_out_new_WIRE_46
wire butterfly_outputs_out_1_23 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_47 : SInt<35>
node _butterfly_outputs_out_new_T_94 = asUInt(butterfly_outputs_product_5.imag)
node _butterfly_outputs_out_new_T_95 = asSInt(_butterfly_outputs_out_new_T_94)
connect _butterfly_outputs_out_new_WIRE_47, _butterfly_outputs_out_new_T_95
connect butterfly_outputs_out_1_23, _butterfly_outputs_out_new_WIRE_47
wire _butterfly_outputs_this_23 : SInt<35>
wire _butterfly_outputs_new_69 : SInt<35>
wire _butterfly_outputs_new_WIRE_69 : SInt<35>
node _butterfly_outputs_new_T_138 = asUInt(butterfly_outputs_out_0_23)
node _butterfly_outputs_new_T_139 = asSInt(_butterfly_outputs_new_T_138)
connect _butterfly_outputs_new_WIRE_69, _butterfly_outputs_new_T_139
connect _butterfly_outputs_new_69, _butterfly_outputs_new_WIRE_69
connect _butterfly_outputs_this_23, _butterfly_outputs_new_69
wire _butterfly_outputs_that_23 : SInt<35>
wire _butterfly_outputs_new_70 : SInt<35>
wire _butterfly_outputs_new_WIRE_70 : SInt<35>
node _butterfly_outputs_new_T_140 = asUInt(butterfly_outputs_out_1_23)
node _butterfly_outputs_new_T_141 = asSInt(_butterfly_outputs_new_T_140)
connect _butterfly_outputs_new_WIRE_70, _butterfly_outputs_new_T_141
connect _butterfly_outputs_new_70, _butterfly_outputs_new_WIRE_70
connect _butterfly_outputs_that_23, _butterfly_outputs_new_70
node _butterfly_outputs_T_69 = sub(_butterfly_outputs_this_23, _butterfly_outputs_that_23)
node _butterfly_outputs_T_70 = tail(_butterfly_outputs_T_69, 1)
node _butterfly_outputs_T_71 = asSInt(_butterfly_outputs_T_70)
wire _butterfly_outputs_new_71 : SInt<35>
wire _butterfly_outputs_new_WIRE_71 : SInt<35>
node _butterfly_outputs_new_T_142 = asUInt(_butterfly_outputs_T_71)
node _butterfly_outputs_new_T_143 = asSInt(_butterfly_outputs_new_T_142)
connect _butterfly_outputs_new_WIRE_71, _butterfly_outputs_new_T_143
connect _butterfly_outputs_new_71, _butterfly_outputs_new_WIRE_71
wire butterfly_outputs_1_5 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_result_real_new_11 : SInt<35>
wire _butterfly_outputs_result_real_new_WIRE_11 : SInt<35>
node _butterfly_outputs_result_real_new_T_22 = asUInt(_butterfly_outputs_new_68)
node _butterfly_outputs_result_real_new_T_23 = asSInt(_butterfly_outputs_result_real_new_T_22)
connect _butterfly_outputs_result_real_new_WIRE_11, _butterfly_outputs_result_real_new_T_23
connect _butterfly_outputs_result_real_new_11, _butterfly_outputs_result_real_new_WIRE_11
connect butterfly_outputs_1_5.real, _butterfly_outputs_result_real_new_11
wire _butterfly_outputs_result_imag_new_11 : SInt<35>
wire _butterfly_outputs_result_imag_new_WIRE_11 : SInt<35>
node _butterfly_outputs_result_imag_new_T_22 = asUInt(_butterfly_outputs_new_71)
node _butterfly_outputs_result_imag_new_T_23 = asSInt(_butterfly_outputs_result_imag_new_T_22)
connect _butterfly_outputs_result_imag_new_WIRE_11, _butterfly_outputs_result_imag_new_T_23
connect _butterfly_outputs_result_imag_new_11, _butterfly_outputs_result_imag_new_WIRE_11
connect butterfly_outputs_1_5.imag, _butterfly_outputs_result_imag_new_11
node _stage_outputs_2_1_stage_outputs_2_1_imag_T = shr(butterfly_outputs_0_5.imag, 17)
wire _stage_outputs_2_1_stage_outputs_2_1_imag_new : SInt<18>
wire _stage_outputs_2_1_stage_outputs_2_1_imag_new_WIRE : SInt<18>
node _stage_outputs_2_1_stage_outputs_2_1_imag_new_T = asUInt(_stage_outputs_2_1_stage_outputs_2_1_imag_T)
node _stage_outputs_2_1_stage_outputs_2_1_imag_new_T_1 = asSInt(_stage_outputs_2_1_stage_outputs_2_1_imag_new_T)
connect _stage_outputs_2_1_stage_outputs_2_1_imag_new_WIRE, _stage_outputs_2_1_stage_outputs_2_1_imag_new_T_1
connect _stage_outputs_2_1_stage_outputs_2_1_imag_new, _stage_outputs_2_1_stage_outputs_2_1_imag_new_WIRE
connect stage_outputs_2_1.imag, _stage_outputs_2_1_stage_outputs_2_1_imag_new
node _stage_outputs_2_1_stage_outputs_2_1_real_T = shr(butterfly_outputs_0_5.real, 17)
wire _stage_outputs_2_1_stage_outputs_2_1_real_new : SInt<18>
wire _stage_outputs_2_1_stage_outputs_2_1_real_new_WIRE : SInt<18>
node _stage_outputs_2_1_stage_outputs_2_1_real_new_T = asUInt(_stage_outputs_2_1_stage_outputs_2_1_real_T)
node _stage_outputs_2_1_stage_outputs_2_1_real_new_T_1 = asSInt(_stage_outputs_2_1_stage_outputs_2_1_real_new_T)
connect _stage_outputs_2_1_stage_outputs_2_1_real_new_WIRE, _stage_outputs_2_1_stage_outputs_2_1_real_new_T_1
connect _stage_outputs_2_1_stage_outputs_2_1_real_new, _stage_outputs_2_1_stage_outputs_2_1_real_new_WIRE
connect stage_outputs_2_1.real, _stage_outputs_2_1_stage_outputs_2_1_real_new
node _stage_outputs_2_3_stage_outputs_2_3_imag_T = shr(butterfly_outputs_1_5.imag, 17)
wire _stage_outputs_2_3_stage_outputs_2_3_imag_new : SInt<18>
wire _stage_outputs_2_3_stage_outputs_2_3_imag_new_WIRE : SInt<18>
node _stage_outputs_2_3_stage_outputs_2_3_imag_new_T = asUInt(_stage_outputs_2_3_stage_outputs_2_3_imag_T)
node _stage_outputs_2_3_stage_outputs_2_3_imag_new_T_1 = asSInt(_stage_outputs_2_3_stage_outputs_2_3_imag_new_T)
connect _stage_outputs_2_3_stage_outputs_2_3_imag_new_WIRE, _stage_outputs_2_3_stage_outputs_2_3_imag_new_T_1
connect _stage_outputs_2_3_stage_outputs_2_3_imag_new, _stage_outputs_2_3_stage_outputs_2_3_imag_new_WIRE
connect stage_outputs_2_3.imag, _stage_outputs_2_3_stage_outputs_2_3_imag_new
node _stage_outputs_2_3_stage_outputs_2_3_real_T = shr(butterfly_outputs_1_5.real, 17)
wire _stage_outputs_2_3_stage_outputs_2_3_real_new : SInt<18>
wire _stage_outputs_2_3_stage_outputs_2_3_real_new_WIRE : SInt<18>
node _stage_outputs_2_3_stage_outputs_2_3_real_new_T = asUInt(_stage_outputs_2_3_stage_outputs_2_3_real_T)
node _stage_outputs_2_3_stage_outputs_2_3_real_new_T_1 = asSInt(_stage_outputs_2_3_stage_outputs_2_3_real_new_T)
connect _stage_outputs_2_3_stage_outputs_2_3_real_new_WIRE, _stage_outputs_2_3_stage_outputs_2_3_real_new_T_1
connect _stage_outputs_2_3_stage_outputs_2_3_real_new, _stage_outputs_2_3_stage_outputs_2_3_real_new_WIRE
connect stage_outputs_2_3.real, _stage_outputs_2_3_stage_outputs_2_3_real_new
wire butterfly_outputs_product_c_p_d_out_0_6 : SInt<19>
wire _butterfly_outputs_product_c_p_d_out_new_WIRE_12 : SInt<19>
node _butterfly_outputs_product_c_p_d_out_new_T_24 = asUInt(twiddle[4].real)
node _butterfly_outputs_product_c_p_d_out_new_T_25 = asSInt(_butterfly_outputs_product_c_p_d_out_new_T_24)
connect _butterfly_outputs_product_c_p_d_out_new_WIRE_12, _butterfly_outputs_product_c_p_d_out_new_T_25
connect butterfly_outputs_product_c_p_d_out_0_6, _butterfly_outputs_product_c_p_d_out_new_WIRE_12
wire butterfly_outputs_product_c_p_d_out_1_6 : SInt<19>
wire _butterfly_outputs_product_c_p_d_out_new_WIRE_13 : SInt<19>
node _butterfly_outputs_product_c_p_d_out_new_T_26 = asUInt(twiddle[4].imag)
node _butterfly_outputs_product_c_p_d_out_new_T_27 = asSInt(_butterfly_outputs_product_c_p_d_out_new_T_26)
connect _butterfly_outputs_product_c_p_d_out_new_WIRE_13, _butterfly_outputs_product_c_p_d_out_new_T_27
connect butterfly_outputs_product_c_p_d_out_1_6, _butterfly_outputs_product_c_p_d_out_new_WIRE_13
wire _butterfly_outputs_product_c_p_d_this_6 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_12 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_18 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_36 = asUInt(butterfly_outputs_product_c_p_d_out_0_6)
node _butterfly_outputs_product_c_p_d_new_T_37 = asSInt(_butterfly_outputs_product_c_p_d_new_T_36)
connect _butterfly_outputs_product_c_p_d_new_WIRE_18, _butterfly_outputs_product_c_p_d_new_T_37
connect _butterfly_outputs_product_c_p_d_new_12, _butterfly_outputs_product_c_p_d_new_WIRE_18
connect _butterfly_outputs_product_c_p_d_this_6, _butterfly_outputs_product_c_p_d_new_12
wire _butterfly_outputs_product_c_p_d_that_6 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_13 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_19 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_38 = asUInt(butterfly_outputs_product_c_p_d_out_1_6)
node _butterfly_outputs_product_c_p_d_new_T_39 = asSInt(_butterfly_outputs_product_c_p_d_new_T_38)
connect _butterfly_outputs_product_c_p_d_new_WIRE_19, _butterfly_outputs_product_c_p_d_new_T_39
connect _butterfly_outputs_product_c_p_d_new_13, _butterfly_outputs_product_c_p_d_new_WIRE_19
connect _butterfly_outputs_product_c_p_d_that_6, _butterfly_outputs_product_c_p_d_new_13
node _butterfly_outputs_product_c_p_d_T_18 = add(_butterfly_outputs_product_c_p_d_this_6, _butterfly_outputs_product_c_p_d_that_6)
node _butterfly_outputs_product_c_p_d_T_19 = tail(_butterfly_outputs_product_c_p_d_T_18, 1)
node _butterfly_outputs_product_c_p_d_T_20 = asSInt(_butterfly_outputs_product_c_p_d_T_19)
wire butterfly_outputs_product_c_p_d_6 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_20 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_40 = asUInt(_butterfly_outputs_product_c_p_d_T_20)
node _butterfly_outputs_product_c_p_d_new_T_41 = asSInt(_butterfly_outputs_product_c_p_d_new_T_40)
connect _butterfly_outputs_product_c_p_d_new_WIRE_20, _butterfly_outputs_product_c_p_d_new_T_41
connect butterfly_outputs_product_c_p_d_6, _butterfly_outputs_product_c_p_d_new_WIRE_20
wire butterfly_outputs_product_a_p_b_out_0_6 : SInt<16>
wire _butterfly_outputs_product_a_p_b_out_new_WIRE_12 : SInt<16>
node _butterfly_outputs_product_a_p_b_out_new_T_24 = asUInt(stage_outputs_1_6.real)
node _butterfly_outputs_product_a_p_b_out_new_T_25 = asSInt(_butterfly_outputs_product_a_p_b_out_new_T_24)
connect _butterfly_outputs_product_a_p_b_out_new_WIRE_12, _butterfly_outputs_product_a_p_b_out_new_T_25
connect butterfly_outputs_product_a_p_b_out_0_6, _butterfly_outputs_product_a_p_b_out_new_WIRE_12
wire butterfly_outputs_product_a_p_b_out_1_6 : SInt<16>
wire _butterfly_outputs_product_a_p_b_out_new_WIRE_13 : SInt<16>
node _butterfly_outputs_product_a_p_b_out_new_T_26 = asUInt(stage_outputs_1_6.imag)
node _butterfly_outputs_product_a_p_b_out_new_T_27 = asSInt(_butterfly_outputs_product_a_p_b_out_new_T_26)
connect _butterfly_outputs_product_a_p_b_out_new_WIRE_13, _butterfly_outputs_product_a_p_b_out_new_T_27
connect butterfly_outputs_product_a_p_b_out_1_6, _butterfly_outputs_product_a_p_b_out_new_WIRE_13
wire _butterfly_outputs_product_a_p_b_this_6 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_12 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_18 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_36 = asUInt(butterfly_outputs_product_a_p_b_out_0_6)
node _butterfly_outputs_product_a_p_b_new_T_37 = asSInt(_butterfly_outputs_product_a_p_b_new_T_36)
connect _butterfly_outputs_product_a_p_b_new_WIRE_18, _butterfly_outputs_product_a_p_b_new_T_37
connect _butterfly_outputs_product_a_p_b_new_12, _butterfly_outputs_product_a_p_b_new_WIRE_18
connect _butterfly_outputs_product_a_p_b_this_6, _butterfly_outputs_product_a_p_b_new_12
wire _butterfly_outputs_product_a_p_b_that_6 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_13 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_19 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_38 = asUInt(butterfly_outputs_product_a_p_b_out_1_6)
node _butterfly_outputs_product_a_p_b_new_T_39 = asSInt(_butterfly_outputs_product_a_p_b_new_T_38)
connect _butterfly_outputs_product_a_p_b_new_WIRE_19, _butterfly_outputs_product_a_p_b_new_T_39
connect _butterfly_outputs_product_a_p_b_new_13, _butterfly_outputs_product_a_p_b_new_WIRE_19
connect _butterfly_outputs_product_a_p_b_that_6, _butterfly_outputs_product_a_p_b_new_13
node _butterfly_outputs_product_a_p_b_T_18 = add(_butterfly_outputs_product_a_p_b_this_6, _butterfly_outputs_product_a_p_b_that_6)
node _butterfly_outputs_product_a_p_b_T_19 = tail(_butterfly_outputs_product_a_p_b_T_18, 1)
node _butterfly_outputs_product_a_p_b_T_20 = asSInt(_butterfly_outputs_product_a_p_b_T_19)
wire butterfly_outputs_product_a_p_b_6 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_20 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_40 = asUInt(_butterfly_outputs_product_a_p_b_T_20)
node _butterfly_outputs_product_a_p_b_new_T_41 = asSInt(_butterfly_outputs_product_a_p_b_new_T_40)
connect _butterfly_outputs_product_a_p_b_new_WIRE_20, _butterfly_outputs_product_a_p_b_new_T_41
connect butterfly_outputs_product_a_p_b_6, _butterfly_outputs_product_a_p_b_new_WIRE_20
wire butterfly_outputs_product_b_m_a_out_0_6 : SInt<16>
wire _butterfly_outputs_product_b_m_a_out_new_WIRE_12 : SInt<16>
node _butterfly_outputs_product_b_m_a_out_new_T_24 = asUInt(stage_outputs_1_6.imag)
node _butterfly_outputs_product_b_m_a_out_new_T_25 = asSInt(_butterfly_outputs_product_b_m_a_out_new_T_24)
connect _butterfly_outputs_product_b_m_a_out_new_WIRE_12, _butterfly_outputs_product_b_m_a_out_new_T_25
connect butterfly_outputs_product_b_m_a_out_0_6, _butterfly_outputs_product_b_m_a_out_new_WIRE_12
wire butterfly_outputs_product_b_m_a_out_1_6 : SInt<16>
wire _butterfly_outputs_product_b_m_a_out_new_WIRE_13 : SInt<16>
node _butterfly_outputs_product_b_m_a_out_new_T_26 = asUInt(stage_outputs_1_6.real)
node _butterfly_outputs_product_b_m_a_out_new_T_27 = asSInt(_butterfly_outputs_product_b_m_a_out_new_T_26)
connect _butterfly_outputs_product_b_m_a_out_new_WIRE_13, _butterfly_outputs_product_b_m_a_out_new_T_27
connect butterfly_outputs_product_b_m_a_out_1_6, _butterfly_outputs_product_b_m_a_out_new_WIRE_13
wire _butterfly_outputs_product_b_m_a_this_6 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_12 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_18 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_36 = asUInt(butterfly_outputs_product_b_m_a_out_0_6)
node _butterfly_outputs_product_b_m_a_new_T_37 = asSInt(_butterfly_outputs_product_b_m_a_new_T_36)
connect _butterfly_outputs_product_b_m_a_new_WIRE_18, _butterfly_outputs_product_b_m_a_new_T_37
connect _butterfly_outputs_product_b_m_a_new_12, _butterfly_outputs_product_b_m_a_new_WIRE_18
connect _butterfly_outputs_product_b_m_a_this_6, _butterfly_outputs_product_b_m_a_new_12
wire _butterfly_outputs_product_b_m_a_that_6 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_13 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_19 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_38 = asUInt(butterfly_outputs_product_b_m_a_out_1_6)
node _butterfly_outputs_product_b_m_a_new_T_39 = asSInt(_butterfly_outputs_product_b_m_a_new_T_38)
connect _butterfly_outputs_product_b_m_a_new_WIRE_19, _butterfly_outputs_product_b_m_a_new_T_39
connect _butterfly_outputs_product_b_m_a_new_13, _butterfly_outputs_product_b_m_a_new_WIRE_19
connect _butterfly_outputs_product_b_m_a_that_6, _butterfly_outputs_product_b_m_a_new_13
node _butterfly_outputs_product_b_m_a_T_18 = sub(_butterfly_outputs_product_b_m_a_this_6, _butterfly_outputs_product_b_m_a_that_6)
node _butterfly_outputs_product_b_m_a_T_19 = tail(_butterfly_outputs_product_b_m_a_T_18, 1)
node _butterfly_outputs_product_b_m_a_T_20 = asSInt(_butterfly_outputs_product_b_m_a_T_19)
wire butterfly_outputs_product_b_m_a_6 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_20 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_40 = asUInt(_butterfly_outputs_product_b_m_a_T_20)
node _butterfly_outputs_product_b_m_a_new_T_41 = asSInt(_butterfly_outputs_product_b_m_a_new_T_40)
connect _butterfly_outputs_product_b_m_a_new_WIRE_20, _butterfly_outputs_product_b_m_a_new_T_41
connect butterfly_outputs_product_b_m_a_6, _butterfly_outputs_product_b_m_a_new_WIRE_20
node _butterfly_outputs_product_ac_p_ad_T_6 = mul(stage_outputs_1_6.real, butterfly_outputs_product_c_p_d_6)
wire butterfly_outputs_product_ac_p_ad_6 : SInt<35>
wire _butterfly_outputs_product_ac_p_ad_new_WIRE_6 : SInt<35>
node _butterfly_outputs_product_ac_p_ad_new_T_12 = asUInt(_butterfly_outputs_product_ac_p_ad_T_6)
node _butterfly_outputs_product_ac_p_ad_new_T_13 = asSInt(_butterfly_outputs_product_ac_p_ad_new_T_12)
connect _butterfly_outputs_product_ac_p_ad_new_WIRE_6, _butterfly_outputs_product_ac_p_ad_new_T_13
connect butterfly_outputs_product_ac_p_ad_6, _butterfly_outputs_product_ac_p_ad_new_WIRE_6
node _butterfly_outputs_product_ad_p_bd_T_6 = mul(butterfly_outputs_product_a_p_b_6, twiddle[4].imag)
wire butterfly_outputs_product_ad_p_bd_6 : SInt<35>
wire _butterfly_outputs_product_ad_p_bd_new_WIRE_6 : SInt<35>
node _butterfly_outputs_product_ad_p_bd_new_T_12 = asUInt(_butterfly_outputs_product_ad_p_bd_T_6)
node _butterfly_outputs_product_ad_p_bd_new_T_13 = asSInt(_butterfly_outputs_product_ad_p_bd_new_T_12)
connect _butterfly_outputs_product_ad_p_bd_new_WIRE_6, _butterfly_outputs_product_ad_p_bd_new_T_13
connect butterfly_outputs_product_ad_p_bd_6, _butterfly_outputs_product_ad_p_bd_new_WIRE_6
node _butterfly_outputs_product_bc_m_ac_T_6 = mul(butterfly_outputs_product_b_m_a_6, twiddle[4].real)
wire butterfly_outputs_product_bc_m_ac_6 : SInt<35>
wire _butterfly_outputs_product_bc_m_ac_new_WIRE_6 : SInt<35>
node _butterfly_outputs_product_bc_m_ac_new_T_12 = asUInt(_butterfly_outputs_product_bc_m_ac_T_6)
node _butterfly_outputs_product_bc_m_ac_new_T_13 = asSInt(_butterfly_outputs_product_bc_m_ac_new_T_12)
connect _butterfly_outputs_product_bc_m_ac_new_WIRE_6, _butterfly_outputs_product_bc_m_ac_new_T_13
connect butterfly_outputs_product_bc_m_ac_6, _butterfly_outputs_product_bc_m_ac_new_WIRE_6
wire butterfly_outputs_product_out_0_12 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_24 : SInt<35>
node _butterfly_outputs_product_out_new_T_48 = asUInt(butterfly_outputs_product_ac_p_ad_6)
node _butterfly_outputs_product_out_new_T_49 = asSInt(_butterfly_outputs_product_out_new_T_48)
connect _butterfly_outputs_product_out_new_WIRE_24, _butterfly_outputs_product_out_new_T_49
connect butterfly_outputs_product_out_0_12, _butterfly_outputs_product_out_new_WIRE_24
wire butterfly_outputs_product_out_1_12 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_25 : SInt<35>
node _butterfly_outputs_product_out_new_T_50 = asUInt(butterfly_outputs_product_ad_p_bd_6)
node _butterfly_outputs_product_out_new_T_51 = asSInt(_butterfly_outputs_product_out_new_T_50)
connect _butterfly_outputs_product_out_new_WIRE_25, _butterfly_outputs_product_out_new_T_51
connect butterfly_outputs_product_out_1_12, _butterfly_outputs_product_out_new_WIRE_25
wire _butterfly_outputs_product_this_12 : SInt<35>
wire _butterfly_outputs_product_new_36 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_36 : SInt<35>
node _butterfly_outputs_product_new_T_72 = asUInt(butterfly_outputs_product_out_0_12)
node _butterfly_outputs_product_new_T_73 = asSInt(_butterfly_outputs_product_new_T_72)
connect _butterfly_outputs_product_new_WIRE_36, _butterfly_outputs_product_new_T_73
connect _butterfly_outputs_product_new_36, _butterfly_outputs_product_new_WIRE_36
connect _butterfly_outputs_product_this_12, _butterfly_outputs_product_new_36
wire _butterfly_outputs_product_that_12 : SInt<35>
wire _butterfly_outputs_product_new_37 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_37 : SInt<35>
node _butterfly_outputs_product_new_T_74 = asUInt(butterfly_outputs_product_out_1_12)
node _butterfly_outputs_product_new_T_75 = asSInt(_butterfly_outputs_product_new_T_74)
connect _butterfly_outputs_product_new_WIRE_37, _butterfly_outputs_product_new_T_75
connect _butterfly_outputs_product_new_37, _butterfly_outputs_product_new_WIRE_37
connect _butterfly_outputs_product_that_12, _butterfly_outputs_product_new_37
node _butterfly_outputs_product_T_36 = sub(_butterfly_outputs_product_this_12, _butterfly_outputs_product_that_12)
node _butterfly_outputs_product_T_37 = tail(_butterfly_outputs_product_T_36, 1)
node _butterfly_outputs_product_T_38 = asSInt(_butterfly_outputs_product_T_37)
wire _butterfly_outputs_product_new_38 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_38 : SInt<35>
node _butterfly_outputs_product_new_T_76 = asUInt(_butterfly_outputs_product_T_38)
node _butterfly_outputs_product_new_T_77 = asSInt(_butterfly_outputs_product_new_T_76)
connect _butterfly_outputs_product_new_WIRE_38, _butterfly_outputs_product_new_T_77
connect _butterfly_outputs_product_new_38, _butterfly_outputs_product_new_WIRE_38
wire butterfly_outputs_product_out_0_13 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_26 : SInt<35>
node _butterfly_outputs_product_out_new_T_52 = asUInt(butterfly_outputs_product_ac_p_ad_6)
node _butterfly_outputs_product_out_new_T_53 = asSInt(_butterfly_outputs_product_out_new_T_52)
connect _butterfly_outputs_product_out_new_WIRE_26, _butterfly_outputs_product_out_new_T_53
connect butterfly_outputs_product_out_0_13, _butterfly_outputs_product_out_new_WIRE_26
wire butterfly_outputs_product_out_1_13 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_27 : SInt<35>
node _butterfly_outputs_product_out_new_T_54 = asUInt(butterfly_outputs_product_bc_m_ac_6)
node _butterfly_outputs_product_out_new_T_55 = asSInt(_butterfly_outputs_product_out_new_T_54)
connect _butterfly_outputs_product_out_new_WIRE_27, _butterfly_outputs_product_out_new_T_55
connect butterfly_outputs_product_out_1_13, _butterfly_outputs_product_out_new_WIRE_27
wire _butterfly_outputs_product_this_13 : SInt<35>
wire _butterfly_outputs_product_new_39 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_39 : SInt<35>
node _butterfly_outputs_product_new_T_78 = asUInt(butterfly_outputs_product_out_0_13)
node _butterfly_outputs_product_new_T_79 = asSInt(_butterfly_outputs_product_new_T_78)
connect _butterfly_outputs_product_new_WIRE_39, _butterfly_outputs_product_new_T_79
connect _butterfly_outputs_product_new_39, _butterfly_outputs_product_new_WIRE_39
connect _butterfly_outputs_product_this_13, _butterfly_outputs_product_new_39
wire _butterfly_outputs_product_that_13 : SInt<35>
wire _butterfly_outputs_product_new_40 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_40 : SInt<35>
node _butterfly_outputs_product_new_T_80 = asUInt(butterfly_outputs_product_out_1_13)
node _butterfly_outputs_product_new_T_81 = asSInt(_butterfly_outputs_product_new_T_80)
connect _butterfly_outputs_product_new_WIRE_40, _butterfly_outputs_product_new_T_81
connect _butterfly_outputs_product_new_40, _butterfly_outputs_product_new_WIRE_40
connect _butterfly_outputs_product_that_13, _butterfly_outputs_product_new_40
node _butterfly_outputs_product_T_39 = add(_butterfly_outputs_product_this_13, _butterfly_outputs_product_that_13)
node _butterfly_outputs_product_T_40 = tail(_butterfly_outputs_product_T_39, 1)
node _butterfly_outputs_product_T_41 = asSInt(_butterfly_outputs_product_T_40)
wire _butterfly_outputs_product_new_41 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_41 : SInt<35>
node _butterfly_outputs_product_new_T_82 = asUInt(_butterfly_outputs_product_T_41)
node _butterfly_outputs_product_new_T_83 = asSInt(_butterfly_outputs_product_new_T_82)
connect _butterfly_outputs_product_new_WIRE_41, _butterfly_outputs_product_new_T_83
connect _butterfly_outputs_product_new_41, _butterfly_outputs_product_new_WIRE_41
wire butterfly_outputs_product_6 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_product_result_real_new_6 : SInt<35>
wire _butterfly_outputs_product_result_real_new_WIRE_6 : SInt<35>
node _butterfly_outputs_product_result_real_new_T_12 = asUInt(_butterfly_outputs_product_new_38)
node _butterfly_outputs_product_result_real_new_T_13 = asSInt(_butterfly_outputs_product_result_real_new_T_12)
connect _butterfly_outputs_product_result_real_new_WIRE_6, _butterfly_outputs_product_result_real_new_T_13
connect _butterfly_outputs_product_result_real_new_6, _butterfly_outputs_product_result_real_new_WIRE_6
connect butterfly_outputs_product_6.real, _butterfly_outputs_product_result_real_new_6
wire _butterfly_outputs_product_result_imag_new_6 : SInt<35>
wire _butterfly_outputs_product_result_imag_new_WIRE_6 : SInt<35>
node _butterfly_outputs_product_result_imag_new_T_12 = asUInt(_butterfly_outputs_product_new_41)
node _butterfly_outputs_product_result_imag_new_T_13 = asSInt(_butterfly_outputs_product_result_imag_new_T_12)
connect _butterfly_outputs_product_result_imag_new_WIRE_6, _butterfly_outputs_product_result_imag_new_T_13
connect _butterfly_outputs_product_result_imag_new_6, _butterfly_outputs_product_result_imag_new_WIRE_6
connect butterfly_outputs_product_6.imag, _butterfly_outputs_product_result_imag_new_6
node _butterfly_outputs_out_T_24 = shl(stage_outputs_1_4.real, 17)
wire butterfly_outputs_out_0_24 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_48 : SInt<35>
node _butterfly_outputs_out_new_T_96 = asUInt(_butterfly_outputs_out_T_24)
node _butterfly_outputs_out_new_T_97 = asSInt(_butterfly_outputs_out_new_T_96)
connect _butterfly_outputs_out_new_WIRE_48, _butterfly_outputs_out_new_T_97
connect butterfly_outputs_out_0_24, _butterfly_outputs_out_new_WIRE_48
wire butterfly_outputs_out_1_24 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_49 : SInt<35>
node _butterfly_outputs_out_new_T_98 = asUInt(butterfly_outputs_product_6.real)
node _butterfly_outputs_out_new_T_99 = asSInt(_butterfly_outputs_out_new_T_98)
connect _butterfly_outputs_out_new_WIRE_49, _butterfly_outputs_out_new_T_99
connect butterfly_outputs_out_1_24, _butterfly_outputs_out_new_WIRE_49
wire _butterfly_outputs_this_24 : SInt<35>
wire _butterfly_outputs_new_72 : SInt<35>
wire _butterfly_outputs_new_WIRE_72 : SInt<35>
node _butterfly_outputs_new_T_144 = asUInt(butterfly_outputs_out_0_24)
node _butterfly_outputs_new_T_145 = asSInt(_butterfly_outputs_new_T_144)
connect _butterfly_outputs_new_WIRE_72, _butterfly_outputs_new_T_145
connect _butterfly_outputs_new_72, _butterfly_outputs_new_WIRE_72
connect _butterfly_outputs_this_24, _butterfly_outputs_new_72
wire _butterfly_outputs_that_24 : SInt<35>
wire _butterfly_outputs_new_73 : SInt<35>
wire _butterfly_outputs_new_WIRE_73 : SInt<35>
node _butterfly_outputs_new_T_146 = asUInt(butterfly_outputs_out_1_24)
node _butterfly_outputs_new_T_147 = asSInt(_butterfly_outputs_new_T_146)
connect _butterfly_outputs_new_WIRE_73, _butterfly_outputs_new_T_147
connect _butterfly_outputs_new_73, _butterfly_outputs_new_WIRE_73
connect _butterfly_outputs_that_24, _butterfly_outputs_new_73
node _butterfly_outputs_T_72 = add(_butterfly_outputs_this_24, _butterfly_outputs_that_24)
node _butterfly_outputs_T_73 = tail(_butterfly_outputs_T_72, 1)
node _butterfly_outputs_T_74 = asSInt(_butterfly_outputs_T_73)
wire _butterfly_outputs_new_74 : SInt<35>
wire _butterfly_outputs_new_WIRE_74 : SInt<35>
node _butterfly_outputs_new_T_148 = asUInt(_butterfly_outputs_T_74)
node _butterfly_outputs_new_T_149 = asSInt(_butterfly_outputs_new_T_148)
connect _butterfly_outputs_new_WIRE_74, _butterfly_outputs_new_T_149
connect _butterfly_outputs_new_74, _butterfly_outputs_new_WIRE_74
node _butterfly_outputs_out_T_25 = shl(stage_outputs_1_4.imag, 17)
wire butterfly_outputs_out_0_25 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_50 : SInt<35>
node _butterfly_outputs_out_new_T_100 = asUInt(_butterfly_outputs_out_T_25)
node _butterfly_outputs_out_new_T_101 = asSInt(_butterfly_outputs_out_new_T_100)
connect _butterfly_outputs_out_new_WIRE_50, _butterfly_outputs_out_new_T_101
connect butterfly_outputs_out_0_25, _butterfly_outputs_out_new_WIRE_50
wire butterfly_outputs_out_1_25 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_51 : SInt<35>
node _butterfly_outputs_out_new_T_102 = asUInt(butterfly_outputs_product_6.imag)
node _butterfly_outputs_out_new_T_103 = asSInt(_butterfly_outputs_out_new_T_102)
connect _butterfly_outputs_out_new_WIRE_51, _butterfly_outputs_out_new_T_103
connect butterfly_outputs_out_1_25, _butterfly_outputs_out_new_WIRE_51
wire _butterfly_outputs_this_25 : SInt<35>
wire _butterfly_outputs_new_75 : SInt<35>
wire _butterfly_outputs_new_WIRE_75 : SInt<35>
node _butterfly_outputs_new_T_150 = asUInt(butterfly_outputs_out_0_25)
node _butterfly_outputs_new_T_151 = asSInt(_butterfly_outputs_new_T_150)
connect _butterfly_outputs_new_WIRE_75, _butterfly_outputs_new_T_151
connect _butterfly_outputs_new_75, _butterfly_outputs_new_WIRE_75
connect _butterfly_outputs_this_25, _butterfly_outputs_new_75
wire _butterfly_outputs_that_25 : SInt<35>
wire _butterfly_outputs_new_76 : SInt<35>
wire _butterfly_outputs_new_WIRE_76 : SInt<35>
node _butterfly_outputs_new_T_152 = asUInt(butterfly_outputs_out_1_25)
node _butterfly_outputs_new_T_153 = asSInt(_butterfly_outputs_new_T_152)
connect _butterfly_outputs_new_WIRE_76, _butterfly_outputs_new_T_153
connect _butterfly_outputs_new_76, _butterfly_outputs_new_WIRE_76
connect _butterfly_outputs_that_25, _butterfly_outputs_new_76
node _butterfly_outputs_T_75 = add(_butterfly_outputs_this_25, _butterfly_outputs_that_25)
node _butterfly_outputs_T_76 = tail(_butterfly_outputs_T_75, 1)
node _butterfly_outputs_T_77 = asSInt(_butterfly_outputs_T_76)
wire _butterfly_outputs_new_77 : SInt<35>
wire _butterfly_outputs_new_WIRE_77 : SInt<35>
node _butterfly_outputs_new_T_154 = asUInt(_butterfly_outputs_T_77)
node _butterfly_outputs_new_T_155 = asSInt(_butterfly_outputs_new_T_154)
connect _butterfly_outputs_new_WIRE_77, _butterfly_outputs_new_T_155
connect _butterfly_outputs_new_77, _butterfly_outputs_new_WIRE_77
wire butterfly_outputs_0_6 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_result_real_new_12 : SInt<35>
wire _butterfly_outputs_result_real_new_WIRE_12 : SInt<35>
node _butterfly_outputs_result_real_new_T_24 = asUInt(_butterfly_outputs_new_74)
node _butterfly_outputs_result_real_new_T_25 = asSInt(_butterfly_outputs_result_real_new_T_24)
connect _butterfly_outputs_result_real_new_WIRE_12, _butterfly_outputs_result_real_new_T_25
connect _butterfly_outputs_result_real_new_12, _butterfly_outputs_result_real_new_WIRE_12
connect butterfly_outputs_0_6.real, _butterfly_outputs_result_real_new_12
wire _butterfly_outputs_result_imag_new_12 : SInt<35>
wire _butterfly_outputs_result_imag_new_WIRE_12 : SInt<35>
node _butterfly_outputs_result_imag_new_T_24 = asUInt(_butterfly_outputs_new_77)
node _butterfly_outputs_result_imag_new_T_25 = asSInt(_butterfly_outputs_result_imag_new_T_24)
connect _butterfly_outputs_result_imag_new_WIRE_12, _butterfly_outputs_result_imag_new_T_25
connect _butterfly_outputs_result_imag_new_12, _butterfly_outputs_result_imag_new_WIRE_12
connect butterfly_outputs_0_6.imag, _butterfly_outputs_result_imag_new_12
node _butterfly_outputs_out_T_26 = shl(stage_outputs_1_4.real, 17)
wire butterfly_outputs_out_0_26 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_52 : SInt<35>
node _butterfly_outputs_out_new_T_104 = asUInt(_butterfly_outputs_out_T_26)
node _butterfly_outputs_out_new_T_105 = asSInt(_butterfly_outputs_out_new_T_104)
connect _butterfly_outputs_out_new_WIRE_52, _butterfly_outputs_out_new_T_105
connect butterfly_outputs_out_0_26, _butterfly_outputs_out_new_WIRE_52
wire butterfly_outputs_out_1_26 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_53 : SInt<35>
node _butterfly_outputs_out_new_T_106 = asUInt(butterfly_outputs_product_6.real)
node _butterfly_outputs_out_new_T_107 = asSInt(_butterfly_outputs_out_new_T_106)
connect _butterfly_outputs_out_new_WIRE_53, _butterfly_outputs_out_new_T_107
connect butterfly_outputs_out_1_26, _butterfly_outputs_out_new_WIRE_53
wire _butterfly_outputs_this_26 : SInt<35>
wire _butterfly_outputs_new_78 : SInt<35>
wire _butterfly_outputs_new_WIRE_78 : SInt<35>
node _butterfly_outputs_new_T_156 = asUInt(butterfly_outputs_out_0_26)
node _butterfly_outputs_new_T_157 = asSInt(_butterfly_outputs_new_T_156)
connect _butterfly_outputs_new_WIRE_78, _butterfly_outputs_new_T_157
connect _butterfly_outputs_new_78, _butterfly_outputs_new_WIRE_78
connect _butterfly_outputs_this_26, _butterfly_outputs_new_78
wire _butterfly_outputs_that_26 : SInt<35>
wire _butterfly_outputs_new_79 : SInt<35>
wire _butterfly_outputs_new_WIRE_79 : SInt<35>
node _butterfly_outputs_new_T_158 = asUInt(butterfly_outputs_out_1_26)
node _butterfly_outputs_new_T_159 = asSInt(_butterfly_outputs_new_T_158)
connect _butterfly_outputs_new_WIRE_79, _butterfly_outputs_new_T_159
connect _butterfly_outputs_new_79, _butterfly_outputs_new_WIRE_79
connect _butterfly_outputs_that_26, _butterfly_outputs_new_79
node _butterfly_outputs_T_78 = sub(_butterfly_outputs_this_26, _butterfly_outputs_that_26)
node _butterfly_outputs_T_79 = tail(_butterfly_outputs_T_78, 1)
node _butterfly_outputs_T_80 = asSInt(_butterfly_outputs_T_79)
wire _butterfly_outputs_new_80 : SInt<35>
wire _butterfly_outputs_new_WIRE_80 : SInt<35>
node _butterfly_outputs_new_T_160 = asUInt(_butterfly_outputs_T_80)
node _butterfly_outputs_new_T_161 = asSInt(_butterfly_outputs_new_T_160)
connect _butterfly_outputs_new_WIRE_80, _butterfly_outputs_new_T_161
connect _butterfly_outputs_new_80, _butterfly_outputs_new_WIRE_80
node _butterfly_outputs_out_T_27 = shl(stage_outputs_1_4.imag, 17)
wire butterfly_outputs_out_0_27 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_54 : SInt<35>
node _butterfly_outputs_out_new_T_108 = asUInt(_butterfly_outputs_out_T_27)
node _butterfly_outputs_out_new_T_109 = asSInt(_butterfly_outputs_out_new_T_108)
connect _butterfly_outputs_out_new_WIRE_54, _butterfly_outputs_out_new_T_109
connect butterfly_outputs_out_0_27, _butterfly_outputs_out_new_WIRE_54
wire butterfly_outputs_out_1_27 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_55 : SInt<35>
node _butterfly_outputs_out_new_T_110 = asUInt(butterfly_outputs_product_6.imag)
node _butterfly_outputs_out_new_T_111 = asSInt(_butterfly_outputs_out_new_T_110)
connect _butterfly_outputs_out_new_WIRE_55, _butterfly_outputs_out_new_T_111
connect butterfly_outputs_out_1_27, _butterfly_outputs_out_new_WIRE_55
wire _butterfly_outputs_this_27 : SInt<35>
wire _butterfly_outputs_new_81 : SInt<35>
wire _butterfly_outputs_new_WIRE_81 : SInt<35>
node _butterfly_outputs_new_T_162 = asUInt(butterfly_outputs_out_0_27)
node _butterfly_outputs_new_T_163 = asSInt(_butterfly_outputs_new_T_162)
connect _butterfly_outputs_new_WIRE_81, _butterfly_outputs_new_T_163
connect _butterfly_outputs_new_81, _butterfly_outputs_new_WIRE_81
connect _butterfly_outputs_this_27, _butterfly_outputs_new_81
wire _butterfly_outputs_that_27 : SInt<35>
wire _butterfly_outputs_new_82 : SInt<35>
wire _butterfly_outputs_new_WIRE_82 : SInt<35>
node _butterfly_outputs_new_T_164 = asUInt(butterfly_outputs_out_1_27)
node _butterfly_outputs_new_T_165 = asSInt(_butterfly_outputs_new_T_164)
connect _butterfly_outputs_new_WIRE_82, _butterfly_outputs_new_T_165
connect _butterfly_outputs_new_82, _butterfly_outputs_new_WIRE_82
connect _butterfly_outputs_that_27, _butterfly_outputs_new_82
node _butterfly_outputs_T_81 = sub(_butterfly_outputs_this_27, _butterfly_outputs_that_27)
node _butterfly_outputs_T_82 = tail(_butterfly_outputs_T_81, 1)
node _butterfly_outputs_T_83 = asSInt(_butterfly_outputs_T_82)
wire _butterfly_outputs_new_83 : SInt<35>
wire _butterfly_outputs_new_WIRE_83 : SInt<35>
node _butterfly_outputs_new_T_166 = asUInt(_butterfly_outputs_T_83)
node _butterfly_outputs_new_T_167 = asSInt(_butterfly_outputs_new_T_166)
connect _butterfly_outputs_new_WIRE_83, _butterfly_outputs_new_T_167
connect _butterfly_outputs_new_83, _butterfly_outputs_new_WIRE_83
wire butterfly_outputs_1_6 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_result_real_new_13 : SInt<35>
wire _butterfly_outputs_result_real_new_WIRE_13 : SInt<35>
node _butterfly_outputs_result_real_new_T_26 = asUInt(_butterfly_outputs_new_80)
node _butterfly_outputs_result_real_new_T_27 = asSInt(_butterfly_outputs_result_real_new_T_26)
connect _butterfly_outputs_result_real_new_WIRE_13, _butterfly_outputs_result_real_new_T_27
connect _butterfly_outputs_result_real_new_13, _butterfly_outputs_result_real_new_WIRE_13
connect butterfly_outputs_1_6.real, _butterfly_outputs_result_real_new_13
wire _butterfly_outputs_result_imag_new_13 : SInt<35>
wire _butterfly_outputs_result_imag_new_WIRE_13 : SInt<35>
node _butterfly_outputs_result_imag_new_T_26 = asUInt(_butterfly_outputs_new_83)
node _butterfly_outputs_result_imag_new_T_27 = asSInt(_butterfly_outputs_result_imag_new_T_26)
connect _butterfly_outputs_result_imag_new_WIRE_13, _butterfly_outputs_result_imag_new_T_27
connect _butterfly_outputs_result_imag_new_13, _butterfly_outputs_result_imag_new_WIRE_13
connect butterfly_outputs_1_6.imag, _butterfly_outputs_result_imag_new_13
node _stage_outputs_2_4_stage_outputs_2_4_imag_T = shr(butterfly_outputs_0_6.imag, 17)
wire _stage_outputs_2_4_stage_outputs_2_4_imag_new : SInt<18>
wire _stage_outputs_2_4_stage_outputs_2_4_imag_new_WIRE : SInt<18>
node _stage_outputs_2_4_stage_outputs_2_4_imag_new_T = asUInt(_stage_outputs_2_4_stage_outputs_2_4_imag_T)
node _stage_outputs_2_4_stage_outputs_2_4_imag_new_T_1 = asSInt(_stage_outputs_2_4_stage_outputs_2_4_imag_new_T)
connect _stage_outputs_2_4_stage_outputs_2_4_imag_new_WIRE, _stage_outputs_2_4_stage_outputs_2_4_imag_new_T_1
connect _stage_outputs_2_4_stage_outputs_2_4_imag_new, _stage_outputs_2_4_stage_outputs_2_4_imag_new_WIRE
connect stage_outputs_2_4.imag, _stage_outputs_2_4_stage_outputs_2_4_imag_new
node _stage_outputs_2_4_stage_outputs_2_4_real_T = shr(butterfly_outputs_0_6.real, 17)
wire _stage_outputs_2_4_stage_outputs_2_4_real_new : SInt<18>
wire _stage_outputs_2_4_stage_outputs_2_4_real_new_WIRE : SInt<18>
node _stage_outputs_2_4_stage_outputs_2_4_real_new_T = asUInt(_stage_outputs_2_4_stage_outputs_2_4_real_T)
node _stage_outputs_2_4_stage_outputs_2_4_real_new_T_1 = asSInt(_stage_outputs_2_4_stage_outputs_2_4_real_new_T)
connect _stage_outputs_2_4_stage_outputs_2_4_real_new_WIRE, _stage_outputs_2_4_stage_outputs_2_4_real_new_T_1
connect _stage_outputs_2_4_stage_outputs_2_4_real_new, _stage_outputs_2_4_stage_outputs_2_4_real_new_WIRE
connect stage_outputs_2_4.real, _stage_outputs_2_4_stage_outputs_2_4_real_new
node _stage_outputs_2_6_stage_outputs_2_6_imag_T = shr(butterfly_outputs_1_6.imag, 17)
wire _stage_outputs_2_6_stage_outputs_2_6_imag_new : SInt<18>
wire _stage_outputs_2_6_stage_outputs_2_6_imag_new_WIRE : SInt<18>
node _stage_outputs_2_6_stage_outputs_2_6_imag_new_T = asUInt(_stage_outputs_2_6_stage_outputs_2_6_imag_T)
node _stage_outputs_2_6_stage_outputs_2_6_imag_new_T_1 = asSInt(_stage_outputs_2_6_stage_outputs_2_6_imag_new_T)
connect _stage_outputs_2_6_stage_outputs_2_6_imag_new_WIRE, _stage_outputs_2_6_stage_outputs_2_6_imag_new_T_1
connect _stage_outputs_2_6_stage_outputs_2_6_imag_new, _stage_outputs_2_6_stage_outputs_2_6_imag_new_WIRE
connect stage_outputs_2_6.imag, _stage_outputs_2_6_stage_outputs_2_6_imag_new
node _stage_outputs_2_6_stage_outputs_2_6_real_T = shr(butterfly_outputs_1_6.real, 17)
wire _stage_outputs_2_6_stage_outputs_2_6_real_new : SInt<18>
wire _stage_outputs_2_6_stage_outputs_2_6_real_new_WIRE : SInt<18>
node _stage_outputs_2_6_stage_outputs_2_6_real_new_T = asUInt(_stage_outputs_2_6_stage_outputs_2_6_real_T)
node _stage_outputs_2_6_stage_outputs_2_6_real_new_T_1 = asSInt(_stage_outputs_2_6_stage_outputs_2_6_real_new_T)
connect _stage_outputs_2_6_stage_outputs_2_6_real_new_WIRE, _stage_outputs_2_6_stage_outputs_2_6_real_new_T_1
connect _stage_outputs_2_6_stage_outputs_2_6_real_new, _stage_outputs_2_6_stage_outputs_2_6_real_new_WIRE
connect stage_outputs_2_6.real, _stage_outputs_2_6_stage_outputs_2_6_real_new
wire butterfly_outputs_product_c_p_d_out_0_7 : SInt<19>
wire _butterfly_outputs_product_c_p_d_out_new_WIRE_14 : SInt<19>
node _butterfly_outputs_product_c_p_d_out_new_T_28 = asUInt(twiddle[4].real)
node _butterfly_outputs_product_c_p_d_out_new_T_29 = asSInt(_butterfly_outputs_product_c_p_d_out_new_T_28)
connect _butterfly_outputs_product_c_p_d_out_new_WIRE_14, _butterfly_outputs_product_c_p_d_out_new_T_29
connect butterfly_outputs_product_c_p_d_out_0_7, _butterfly_outputs_product_c_p_d_out_new_WIRE_14
wire butterfly_outputs_product_c_p_d_out_1_7 : SInt<19>
wire _butterfly_outputs_product_c_p_d_out_new_WIRE_15 : SInt<19>
node _butterfly_outputs_product_c_p_d_out_new_T_30 = asUInt(twiddle[4].imag)
node _butterfly_outputs_product_c_p_d_out_new_T_31 = asSInt(_butterfly_outputs_product_c_p_d_out_new_T_30)
connect _butterfly_outputs_product_c_p_d_out_new_WIRE_15, _butterfly_outputs_product_c_p_d_out_new_T_31
connect butterfly_outputs_product_c_p_d_out_1_7, _butterfly_outputs_product_c_p_d_out_new_WIRE_15
wire _butterfly_outputs_product_c_p_d_this_7 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_14 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_21 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_42 = asUInt(butterfly_outputs_product_c_p_d_out_0_7)
node _butterfly_outputs_product_c_p_d_new_T_43 = asSInt(_butterfly_outputs_product_c_p_d_new_T_42)
connect _butterfly_outputs_product_c_p_d_new_WIRE_21, _butterfly_outputs_product_c_p_d_new_T_43
connect _butterfly_outputs_product_c_p_d_new_14, _butterfly_outputs_product_c_p_d_new_WIRE_21
connect _butterfly_outputs_product_c_p_d_this_7, _butterfly_outputs_product_c_p_d_new_14
wire _butterfly_outputs_product_c_p_d_that_7 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_15 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_22 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_44 = asUInt(butterfly_outputs_product_c_p_d_out_1_7)
node _butterfly_outputs_product_c_p_d_new_T_45 = asSInt(_butterfly_outputs_product_c_p_d_new_T_44)
connect _butterfly_outputs_product_c_p_d_new_WIRE_22, _butterfly_outputs_product_c_p_d_new_T_45
connect _butterfly_outputs_product_c_p_d_new_15, _butterfly_outputs_product_c_p_d_new_WIRE_22
connect _butterfly_outputs_product_c_p_d_that_7, _butterfly_outputs_product_c_p_d_new_15
node _butterfly_outputs_product_c_p_d_T_21 = add(_butterfly_outputs_product_c_p_d_this_7, _butterfly_outputs_product_c_p_d_that_7)
node _butterfly_outputs_product_c_p_d_T_22 = tail(_butterfly_outputs_product_c_p_d_T_21, 1)
node _butterfly_outputs_product_c_p_d_T_23 = asSInt(_butterfly_outputs_product_c_p_d_T_22)
wire butterfly_outputs_product_c_p_d_7 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_23 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_46 = asUInt(_butterfly_outputs_product_c_p_d_T_23)
node _butterfly_outputs_product_c_p_d_new_T_47 = asSInt(_butterfly_outputs_product_c_p_d_new_T_46)
connect _butterfly_outputs_product_c_p_d_new_WIRE_23, _butterfly_outputs_product_c_p_d_new_T_47
connect butterfly_outputs_product_c_p_d_7, _butterfly_outputs_product_c_p_d_new_WIRE_23
wire butterfly_outputs_product_a_p_b_out_0_7 : SInt<16>
wire _butterfly_outputs_product_a_p_b_out_new_WIRE_14 : SInt<16>
node _butterfly_outputs_product_a_p_b_out_new_T_28 = asUInt(stage_outputs_1_7.real)
node _butterfly_outputs_product_a_p_b_out_new_T_29 = asSInt(_butterfly_outputs_product_a_p_b_out_new_T_28)
connect _butterfly_outputs_product_a_p_b_out_new_WIRE_14, _butterfly_outputs_product_a_p_b_out_new_T_29
connect butterfly_outputs_product_a_p_b_out_0_7, _butterfly_outputs_product_a_p_b_out_new_WIRE_14
wire butterfly_outputs_product_a_p_b_out_1_7 : SInt<16>
wire _butterfly_outputs_product_a_p_b_out_new_WIRE_15 : SInt<16>
node _butterfly_outputs_product_a_p_b_out_new_T_30 = asUInt(stage_outputs_1_7.imag)
node _butterfly_outputs_product_a_p_b_out_new_T_31 = asSInt(_butterfly_outputs_product_a_p_b_out_new_T_30)
connect _butterfly_outputs_product_a_p_b_out_new_WIRE_15, _butterfly_outputs_product_a_p_b_out_new_T_31
connect butterfly_outputs_product_a_p_b_out_1_7, _butterfly_outputs_product_a_p_b_out_new_WIRE_15
wire _butterfly_outputs_product_a_p_b_this_7 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_14 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_21 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_42 = asUInt(butterfly_outputs_product_a_p_b_out_0_7)
node _butterfly_outputs_product_a_p_b_new_T_43 = asSInt(_butterfly_outputs_product_a_p_b_new_T_42)
connect _butterfly_outputs_product_a_p_b_new_WIRE_21, _butterfly_outputs_product_a_p_b_new_T_43
connect _butterfly_outputs_product_a_p_b_new_14, _butterfly_outputs_product_a_p_b_new_WIRE_21
connect _butterfly_outputs_product_a_p_b_this_7, _butterfly_outputs_product_a_p_b_new_14
wire _butterfly_outputs_product_a_p_b_that_7 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_15 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_22 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_44 = asUInt(butterfly_outputs_product_a_p_b_out_1_7)
node _butterfly_outputs_product_a_p_b_new_T_45 = asSInt(_butterfly_outputs_product_a_p_b_new_T_44)
connect _butterfly_outputs_product_a_p_b_new_WIRE_22, _butterfly_outputs_product_a_p_b_new_T_45
connect _butterfly_outputs_product_a_p_b_new_15, _butterfly_outputs_product_a_p_b_new_WIRE_22
connect _butterfly_outputs_product_a_p_b_that_7, _butterfly_outputs_product_a_p_b_new_15
node _butterfly_outputs_product_a_p_b_T_21 = add(_butterfly_outputs_product_a_p_b_this_7, _butterfly_outputs_product_a_p_b_that_7)
node _butterfly_outputs_product_a_p_b_T_22 = tail(_butterfly_outputs_product_a_p_b_T_21, 1)
node _butterfly_outputs_product_a_p_b_T_23 = asSInt(_butterfly_outputs_product_a_p_b_T_22)
wire butterfly_outputs_product_a_p_b_7 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_23 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_46 = asUInt(_butterfly_outputs_product_a_p_b_T_23)
node _butterfly_outputs_product_a_p_b_new_T_47 = asSInt(_butterfly_outputs_product_a_p_b_new_T_46)
connect _butterfly_outputs_product_a_p_b_new_WIRE_23, _butterfly_outputs_product_a_p_b_new_T_47
connect butterfly_outputs_product_a_p_b_7, _butterfly_outputs_product_a_p_b_new_WIRE_23
wire butterfly_outputs_product_b_m_a_out_0_7 : SInt<16>
wire _butterfly_outputs_product_b_m_a_out_new_WIRE_14 : SInt<16>
node _butterfly_outputs_product_b_m_a_out_new_T_28 = asUInt(stage_outputs_1_7.imag)
node _butterfly_outputs_product_b_m_a_out_new_T_29 = asSInt(_butterfly_outputs_product_b_m_a_out_new_T_28)
connect _butterfly_outputs_product_b_m_a_out_new_WIRE_14, _butterfly_outputs_product_b_m_a_out_new_T_29
connect butterfly_outputs_product_b_m_a_out_0_7, _butterfly_outputs_product_b_m_a_out_new_WIRE_14
wire butterfly_outputs_product_b_m_a_out_1_7 : SInt<16>
wire _butterfly_outputs_product_b_m_a_out_new_WIRE_15 : SInt<16>
node _butterfly_outputs_product_b_m_a_out_new_T_30 = asUInt(stage_outputs_1_7.real)
node _butterfly_outputs_product_b_m_a_out_new_T_31 = asSInt(_butterfly_outputs_product_b_m_a_out_new_T_30)
connect _butterfly_outputs_product_b_m_a_out_new_WIRE_15, _butterfly_outputs_product_b_m_a_out_new_T_31
connect butterfly_outputs_product_b_m_a_out_1_7, _butterfly_outputs_product_b_m_a_out_new_WIRE_15
wire _butterfly_outputs_product_b_m_a_this_7 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_14 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_21 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_42 = asUInt(butterfly_outputs_product_b_m_a_out_0_7)
node _butterfly_outputs_product_b_m_a_new_T_43 = asSInt(_butterfly_outputs_product_b_m_a_new_T_42)
connect _butterfly_outputs_product_b_m_a_new_WIRE_21, _butterfly_outputs_product_b_m_a_new_T_43
connect _butterfly_outputs_product_b_m_a_new_14, _butterfly_outputs_product_b_m_a_new_WIRE_21
connect _butterfly_outputs_product_b_m_a_this_7, _butterfly_outputs_product_b_m_a_new_14
wire _butterfly_outputs_product_b_m_a_that_7 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_15 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_22 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_44 = asUInt(butterfly_outputs_product_b_m_a_out_1_7)
node _butterfly_outputs_product_b_m_a_new_T_45 = asSInt(_butterfly_outputs_product_b_m_a_new_T_44)
connect _butterfly_outputs_product_b_m_a_new_WIRE_22, _butterfly_outputs_product_b_m_a_new_T_45
connect _butterfly_outputs_product_b_m_a_new_15, _butterfly_outputs_product_b_m_a_new_WIRE_22
connect _butterfly_outputs_product_b_m_a_that_7, _butterfly_outputs_product_b_m_a_new_15
node _butterfly_outputs_product_b_m_a_T_21 = sub(_butterfly_outputs_product_b_m_a_this_7, _butterfly_outputs_product_b_m_a_that_7)
node _butterfly_outputs_product_b_m_a_T_22 = tail(_butterfly_outputs_product_b_m_a_T_21, 1)
node _butterfly_outputs_product_b_m_a_T_23 = asSInt(_butterfly_outputs_product_b_m_a_T_22)
wire butterfly_outputs_product_b_m_a_7 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_23 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_46 = asUInt(_butterfly_outputs_product_b_m_a_T_23)
node _butterfly_outputs_product_b_m_a_new_T_47 = asSInt(_butterfly_outputs_product_b_m_a_new_T_46)
connect _butterfly_outputs_product_b_m_a_new_WIRE_23, _butterfly_outputs_product_b_m_a_new_T_47
connect butterfly_outputs_product_b_m_a_7, _butterfly_outputs_product_b_m_a_new_WIRE_23
node _butterfly_outputs_product_ac_p_ad_T_7 = mul(stage_outputs_1_7.real, butterfly_outputs_product_c_p_d_7)
wire butterfly_outputs_product_ac_p_ad_7 : SInt<35>
wire _butterfly_outputs_product_ac_p_ad_new_WIRE_7 : SInt<35>
node _butterfly_outputs_product_ac_p_ad_new_T_14 = asUInt(_butterfly_outputs_product_ac_p_ad_T_7)
node _butterfly_outputs_product_ac_p_ad_new_T_15 = asSInt(_butterfly_outputs_product_ac_p_ad_new_T_14)
connect _butterfly_outputs_product_ac_p_ad_new_WIRE_7, _butterfly_outputs_product_ac_p_ad_new_T_15
connect butterfly_outputs_product_ac_p_ad_7, _butterfly_outputs_product_ac_p_ad_new_WIRE_7
node _butterfly_outputs_product_ad_p_bd_T_7 = mul(butterfly_outputs_product_a_p_b_7, twiddle[4].imag)
wire butterfly_outputs_product_ad_p_bd_7 : SInt<35>
wire _butterfly_outputs_product_ad_p_bd_new_WIRE_7 : SInt<35>
node _butterfly_outputs_product_ad_p_bd_new_T_14 = asUInt(_butterfly_outputs_product_ad_p_bd_T_7)
node _butterfly_outputs_product_ad_p_bd_new_T_15 = asSInt(_butterfly_outputs_product_ad_p_bd_new_T_14)
connect _butterfly_outputs_product_ad_p_bd_new_WIRE_7, _butterfly_outputs_product_ad_p_bd_new_T_15
connect butterfly_outputs_product_ad_p_bd_7, _butterfly_outputs_product_ad_p_bd_new_WIRE_7
node _butterfly_outputs_product_bc_m_ac_T_7 = mul(butterfly_outputs_product_b_m_a_7, twiddle[4].real)
wire butterfly_outputs_product_bc_m_ac_7 : SInt<35>
wire _butterfly_outputs_product_bc_m_ac_new_WIRE_7 : SInt<35>
node _butterfly_outputs_product_bc_m_ac_new_T_14 = asUInt(_butterfly_outputs_product_bc_m_ac_T_7)
node _butterfly_outputs_product_bc_m_ac_new_T_15 = asSInt(_butterfly_outputs_product_bc_m_ac_new_T_14)
connect _butterfly_outputs_product_bc_m_ac_new_WIRE_7, _butterfly_outputs_product_bc_m_ac_new_T_15
connect butterfly_outputs_product_bc_m_ac_7, _butterfly_outputs_product_bc_m_ac_new_WIRE_7
wire butterfly_outputs_product_out_0_14 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_28 : SInt<35>
node _butterfly_outputs_product_out_new_T_56 = asUInt(butterfly_outputs_product_ac_p_ad_7)
node _butterfly_outputs_product_out_new_T_57 = asSInt(_butterfly_outputs_product_out_new_T_56)
connect _butterfly_outputs_product_out_new_WIRE_28, _butterfly_outputs_product_out_new_T_57
connect butterfly_outputs_product_out_0_14, _butterfly_outputs_product_out_new_WIRE_28
wire butterfly_outputs_product_out_1_14 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_29 : SInt<35>
node _butterfly_outputs_product_out_new_T_58 = asUInt(butterfly_outputs_product_ad_p_bd_7)
node _butterfly_outputs_product_out_new_T_59 = asSInt(_butterfly_outputs_product_out_new_T_58)
connect _butterfly_outputs_product_out_new_WIRE_29, _butterfly_outputs_product_out_new_T_59
connect butterfly_outputs_product_out_1_14, _butterfly_outputs_product_out_new_WIRE_29
wire _butterfly_outputs_product_this_14 : SInt<35>
wire _butterfly_outputs_product_new_42 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_42 : SInt<35>
node _butterfly_outputs_product_new_T_84 = asUInt(butterfly_outputs_product_out_0_14)
node _butterfly_outputs_product_new_T_85 = asSInt(_butterfly_outputs_product_new_T_84)
connect _butterfly_outputs_product_new_WIRE_42, _butterfly_outputs_product_new_T_85
connect _butterfly_outputs_product_new_42, _butterfly_outputs_product_new_WIRE_42
connect _butterfly_outputs_product_this_14, _butterfly_outputs_product_new_42
wire _butterfly_outputs_product_that_14 : SInt<35>
wire _butterfly_outputs_product_new_43 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_43 : SInt<35>
node _butterfly_outputs_product_new_T_86 = asUInt(butterfly_outputs_product_out_1_14)
node _butterfly_outputs_product_new_T_87 = asSInt(_butterfly_outputs_product_new_T_86)
connect _butterfly_outputs_product_new_WIRE_43, _butterfly_outputs_product_new_T_87
connect _butterfly_outputs_product_new_43, _butterfly_outputs_product_new_WIRE_43
connect _butterfly_outputs_product_that_14, _butterfly_outputs_product_new_43
node _butterfly_outputs_product_T_42 = sub(_butterfly_outputs_product_this_14, _butterfly_outputs_product_that_14)
node _butterfly_outputs_product_T_43 = tail(_butterfly_outputs_product_T_42, 1)
node _butterfly_outputs_product_T_44 = asSInt(_butterfly_outputs_product_T_43)
wire _butterfly_outputs_product_new_44 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_44 : SInt<35>
node _butterfly_outputs_product_new_T_88 = asUInt(_butterfly_outputs_product_T_44)
node _butterfly_outputs_product_new_T_89 = asSInt(_butterfly_outputs_product_new_T_88)
connect _butterfly_outputs_product_new_WIRE_44, _butterfly_outputs_product_new_T_89
connect _butterfly_outputs_product_new_44, _butterfly_outputs_product_new_WIRE_44
wire butterfly_outputs_product_out_0_15 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_30 : SInt<35>
node _butterfly_outputs_product_out_new_T_60 = asUInt(butterfly_outputs_product_ac_p_ad_7)
node _butterfly_outputs_product_out_new_T_61 = asSInt(_butterfly_outputs_product_out_new_T_60)
connect _butterfly_outputs_product_out_new_WIRE_30, _butterfly_outputs_product_out_new_T_61
connect butterfly_outputs_product_out_0_15, _butterfly_outputs_product_out_new_WIRE_30
wire butterfly_outputs_product_out_1_15 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_31 : SInt<35>
node _butterfly_outputs_product_out_new_T_62 = asUInt(butterfly_outputs_product_bc_m_ac_7)
node _butterfly_outputs_product_out_new_T_63 = asSInt(_butterfly_outputs_product_out_new_T_62)
connect _butterfly_outputs_product_out_new_WIRE_31, _butterfly_outputs_product_out_new_T_63
connect butterfly_outputs_product_out_1_15, _butterfly_outputs_product_out_new_WIRE_31
wire _butterfly_outputs_product_this_15 : SInt<35>
wire _butterfly_outputs_product_new_45 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_45 : SInt<35>
node _butterfly_outputs_product_new_T_90 = asUInt(butterfly_outputs_product_out_0_15)
node _butterfly_outputs_product_new_T_91 = asSInt(_butterfly_outputs_product_new_T_90)
connect _butterfly_outputs_product_new_WIRE_45, _butterfly_outputs_product_new_T_91
connect _butterfly_outputs_product_new_45, _butterfly_outputs_product_new_WIRE_45
connect _butterfly_outputs_product_this_15, _butterfly_outputs_product_new_45
wire _butterfly_outputs_product_that_15 : SInt<35>
wire _butterfly_outputs_product_new_46 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_46 : SInt<35>
node _butterfly_outputs_product_new_T_92 = asUInt(butterfly_outputs_product_out_1_15)
node _butterfly_outputs_product_new_T_93 = asSInt(_butterfly_outputs_product_new_T_92)
connect _butterfly_outputs_product_new_WIRE_46, _butterfly_outputs_product_new_T_93
connect _butterfly_outputs_product_new_46, _butterfly_outputs_product_new_WIRE_46
connect _butterfly_outputs_product_that_15, _butterfly_outputs_product_new_46
node _butterfly_outputs_product_T_45 = add(_butterfly_outputs_product_this_15, _butterfly_outputs_product_that_15)
node _butterfly_outputs_product_T_46 = tail(_butterfly_outputs_product_T_45, 1)
node _butterfly_outputs_product_T_47 = asSInt(_butterfly_outputs_product_T_46)
wire _butterfly_outputs_product_new_47 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_47 : SInt<35>
node _butterfly_outputs_product_new_T_94 = asUInt(_butterfly_outputs_product_T_47)
node _butterfly_outputs_product_new_T_95 = asSInt(_butterfly_outputs_product_new_T_94)
connect _butterfly_outputs_product_new_WIRE_47, _butterfly_outputs_product_new_T_95
connect _butterfly_outputs_product_new_47, _butterfly_outputs_product_new_WIRE_47
wire butterfly_outputs_product_7 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_product_result_real_new_7 : SInt<35>
wire _butterfly_outputs_product_result_real_new_WIRE_7 : SInt<35>
node _butterfly_outputs_product_result_real_new_T_14 = asUInt(_butterfly_outputs_product_new_44)
node _butterfly_outputs_product_result_real_new_T_15 = asSInt(_butterfly_outputs_product_result_real_new_T_14)
connect _butterfly_outputs_product_result_real_new_WIRE_7, _butterfly_outputs_product_result_real_new_T_15
connect _butterfly_outputs_product_result_real_new_7, _butterfly_outputs_product_result_real_new_WIRE_7
connect butterfly_outputs_product_7.real, _butterfly_outputs_product_result_real_new_7
wire _butterfly_outputs_product_result_imag_new_7 : SInt<35>
wire _butterfly_outputs_product_result_imag_new_WIRE_7 : SInt<35>
node _butterfly_outputs_product_result_imag_new_T_14 = asUInt(_butterfly_outputs_product_new_47)
node _butterfly_outputs_product_result_imag_new_T_15 = asSInt(_butterfly_outputs_product_result_imag_new_T_14)
connect _butterfly_outputs_product_result_imag_new_WIRE_7, _butterfly_outputs_product_result_imag_new_T_15
connect _butterfly_outputs_product_result_imag_new_7, _butterfly_outputs_product_result_imag_new_WIRE_7
connect butterfly_outputs_product_7.imag, _butterfly_outputs_product_result_imag_new_7
node _butterfly_outputs_out_T_28 = shl(stage_outputs_1_5.real, 17)
wire butterfly_outputs_out_0_28 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_56 : SInt<35>
node _butterfly_outputs_out_new_T_112 = asUInt(_butterfly_outputs_out_T_28)
node _butterfly_outputs_out_new_T_113 = asSInt(_butterfly_outputs_out_new_T_112)
connect _butterfly_outputs_out_new_WIRE_56, _butterfly_outputs_out_new_T_113
connect butterfly_outputs_out_0_28, _butterfly_outputs_out_new_WIRE_56
wire butterfly_outputs_out_1_28 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_57 : SInt<35>
node _butterfly_outputs_out_new_T_114 = asUInt(butterfly_outputs_product_7.real)
node _butterfly_outputs_out_new_T_115 = asSInt(_butterfly_outputs_out_new_T_114)
connect _butterfly_outputs_out_new_WIRE_57, _butterfly_outputs_out_new_T_115
connect butterfly_outputs_out_1_28, _butterfly_outputs_out_new_WIRE_57
wire _butterfly_outputs_this_28 : SInt<35>
wire _butterfly_outputs_new_84 : SInt<35>
wire _butterfly_outputs_new_WIRE_84 : SInt<35>
node _butterfly_outputs_new_T_168 = asUInt(butterfly_outputs_out_0_28)
node _butterfly_outputs_new_T_169 = asSInt(_butterfly_outputs_new_T_168)
connect _butterfly_outputs_new_WIRE_84, _butterfly_outputs_new_T_169
connect _butterfly_outputs_new_84, _butterfly_outputs_new_WIRE_84
connect _butterfly_outputs_this_28, _butterfly_outputs_new_84
wire _butterfly_outputs_that_28 : SInt<35>
wire _butterfly_outputs_new_85 : SInt<35>
wire _butterfly_outputs_new_WIRE_85 : SInt<35>
node _butterfly_outputs_new_T_170 = asUInt(butterfly_outputs_out_1_28)
node _butterfly_outputs_new_T_171 = asSInt(_butterfly_outputs_new_T_170)
connect _butterfly_outputs_new_WIRE_85, _butterfly_outputs_new_T_171
connect _butterfly_outputs_new_85, _butterfly_outputs_new_WIRE_85
connect _butterfly_outputs_that_28, _butterfly_outputs_new_85
node _butterfly_outputs_T_84 = add(_butterfly_outputs_this_28, _butterfly_outputs_that_28)
node _butterfly_outputs_T_85 = tail(_butterfly_outputs_T_84, 1)
node _butterfly_outputs_T_86 = asSInt(_butterfly_outputs_T_85)
wire _butterfly_outputs_new_86 : SInt<35>
wire _butterfly_outputs_new_WIRE_86 : SInt<35>
node _butterfly_outputs_new_T_172 = asUInt(_butterfly_outputs_T_86)
node _butterfly_outputs_new_T_173 = asSInt(_butterfly_outputs_new_T_172)
connect _butterfly_outputs_new_WIRE_86, _butterfly_outputs_new_T_173
connect _butterfly_outputs_new_86, _butterfly_outputs_new_WIRE_86
node _butterfly_outputs_out_T_29 = shl(stage_outputs_1_5.imag, 17)
wire butterfly_outputs_out_0_29 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_58 : SInt<35>
node _butterfly_outputs_out_new_T_116 = asUInt(_butterfly_outputs_out_T_29)
node _butterfly_outputs_out_new_T_117 = asSInt(_butterfly_outputs_out_new_T_116)
connect _butterfly_outputs_out_new_WIRE_58, _butterfly_outputs_out_new_T_117
connect butterfly_outputs_out_0_29, _butterfly_outputs_out_new_WIRE_58
wire butterfly_outputs_out_1_29 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_59 : SInt<35>
node _butterfly_outputs_out_new_T_118 = asUInt(butterfly_outputs_product_7.imag)
node _butterfly_outputs_out_new_T_119 = asSInt(_butterfly_outputs_out_new_T_118)
connect _butterfly_outputs_out_new_WIRE_59, _butterfly_outputs_out_new_T_119
connect butterfly_outputs_out_1_29, _butterfly_outputs_out_new_WIRE_59
wire _butterfly_outputs_this_29 : SInt<35>
wire _butterfly_outputs_new_87 : SInt<35>
wire _butterfly_outputs_new_WIRE_87 : SInt<35>
node _butterfly_outputs_new_T_174 = asUInt(butterfly_outputs_out_0_29)
node _butterfly_outputs_new_T_175 = asSInt(_butterfly_outputs_new_T_174)
connect _butterfly_outputs_new_WIRE_87, _butterfly_outputs_new_T_175
connect _butterfly_outputs_new_87, _butterfly_outputs_new_WIRE_87
connect _butterfly_outputs_this_29, _butterfly_outputs_new_87
wire _butterfly_outputs_that_29 : SInt<35>
wire _butterfly_outputs_new_88 : SInt<35>
wire _butterfly_outputs_new_WIRE_88 : SInt<35>
node _butterfly_outputs_new_T_176 = asUInt(butterfly_outputs_out_1_29)
node _butterfly_outputs_new_T_177 = asSInt(_butterfly_outputs_new_T_176)
connect _butterfly_outputs_new_WIRE_88, _butterfly_outputs_new_T_177
connect _butterfly_outputs_new_88, _butterfly_outputs_new_WIRE_88
connect _butterfly_outputs_that_29, _butterfly_outputs_new_88
node _butterfly_outputs_T_87 = add(_butterfly_outputs_this_29, _butterfly_outputs_that_29)
node _butterfly_outputs_T_88 = tail(_butterfly_outputs_T_87, 1)
node _butterfly_outputs_T_89 = asSInt(_butterfly_outputs_T_88)
wire _butterfly_outputs_new_89 : SInt<35>
wire _butterfly_outputs_new_WIRE_89 : SInt<35>
node _butterfly_outputs_new_T_178 = asUInt(_butterfly_outputs_T_89)
node _butterfly_outputs_new_T_179 = asSInt(_butterfly_outputs_new_T_178)
connect _butterfly_outputs_new_WIRE_89, _butterfly_outputs_new_T_179
connect _butterfly_outputs_new_89, _butterfly_outputs_new_WIRE_89
wire butterfly_outputs_0_7 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_result_real_new_14 : SInt<35>
wire _butterfly_outputs_result_real_new_WIRE_14 : SInt<35>
node _butterfly_outputs_result_real_new_T_28 = asUInt(_butterfly_outputs_new_86)
node _butterfly_outputs_result_real_new_T_29 = asSInt(_butterfly_outputs_result_real_new_T_28)
connect _butterfly_outputs_result_real_new_WIRE_14, _butterfly_outputs_result_real_new_T_29
connect _butterfly_outputs_result_real_new_14, _butterfly_outputs_result_real_new_WIRE_14
connect butterfly_outputs_0_7.real, _butterfly_outputs_result_real_new_14
wire _butterfly_outputs_result_imag_new_14 : SInt<35>
wire _butterfly_outputs_result_imag_new_WIRE_14 : SInt<35>
node _butterfly_outputs_result_imag_new_T_28 = asUInt(_butterfly_outputs_new_89)
node _butterfly_outputs_result_imag_new_T_29 = asSInt(_butterfly_outputs_result_imag_new_T_28)
connect _butterfly_outputs_result_imag_new_WIRE_14, _butterfly_outputs_result_imag_new_T_29
connect _butterfly_outputs_result_imag_new_14, _butterfly_outputs_result_imag_new_WIRE_14
connect butterfly_outputs_0_7.imag, _butterfly_outputs_result_imag_new_14
node _butterfly_outputs_out_T_30 = shl(stage_outputs_1_5.real, 17)
wire butterfly_outputs_out_0_30 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_60 : SInt<35>
node _butterfly_outputs_out_new_T_120 = asUInt(_butterfly_outputs_out_T_30)
node _butterfly_outputs_out_new_T_121 = asSInt(_butterfly_outputs_out_new_T_120)
connect _butterfly_outputs_out_new_WIRE_60, _butterfly_outputs_out_new_T_121
connect butterfly_outputs_out_0_30, _butterfly_outputs_out_new_WIRE_60
wire butterfly_outputs_out_1_30 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_61 : SInt<35>
node _butterfly_outputs_out_new_T_122 = asUInt(butterfly_outputs_product_7.real)
node _butterfly_outputs_out_new_T_123 = asSInt(_butterfly_outputs_out_new_T_122)
connect _butterfly_outputs_out_new_WIRE_61, _butterfly_outputs_out_new_T_123
connect butterfly_outputs_out_1_30, _butterfly_outputs_out_new_WIRE_61
wire _butterfly_outputs_this_30 : SInt<35>
wire _butterfly_outputs_new_90 : SInt<35>
wire _butterfly_outputs_new_WIRE_90 : SInt<35>
node _butterfly_outputs_new_T_180 = asUInt(butterfly_outputs_out_0_30)
node _butterfly_outputs_new_T_181 = asSInt(_butterfly_outputs_new_T_180)
connect _butterfly_outputs_new_WIRE_90, _butterfly_outputs_new_T_181
connect _butterfly_outputs_new_90, _butterfly_outputs_new_WIRE_90
connect _butterfly_outputs_this_30, _butterfly_outputs_new_90
wire _butterfly_outputs_that_30 : SInt<35>
wire _butterfly_outputs_new_91 : SInt<35>
wire _butterfly_outputs_new_WIRE_91 : SInt<35>
node _butterfly_outputs_new_T_182 = asUInt(butterfly_outputs_out_1_30)
node _butterfly_outputs_new_T_183 = asSInt(_butterfly_outputs_new_T_182)
connect _butterfly_outputs_new_WIRE_91, _butterfly_outputs_new_T_183
connect _butterfly_outputs_new_91, _butterfly_outputs_new_WIRE_91
connect _butterfly_outputs_that_30, _butterfly_outputs_new_91
node _butterfly_outputs_T_90 = sub(_butterfly_outputs_this_30, _butterfly_outputs_that_30)
node _butterfly_outputs_T_91 = tail(_butterfly_outputs_T_90, 1)
node _butterfly_outputs_T_92 = asSInt(_butterfly_outputs_T_91)
wire _butterfly_outputs_new_92 : SInt<35>
wire _butterfly_outputs_new_WIRE_92 : SInt<35>
node _butterfly_outputs_new_T_184 = asUInt(_butterfly_outputs_T_92)
node _butterfly_outputs_new_T_185 = asSInt(_butterfly_outputs_new_T_184)
connect _butterfly_outputs_new_WIRE_92, _butterfly_outputs_new_T_185
connect _butterfly_outputs_new_92, _butterfly_outputs_new_WIRE_92
node _butterfly_outputs_out_T_31 = shl(stage_outputs_1_5.imag, 17)
wire butterfly_outputs_out_0_31 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_62 : SInt<35>
node _butterfly_outputs_out_new_T_124 = asUInt(_butterfly_outputs_out_T_31)
node _butterfly_outputs_out_new_T_125 = asSInt(_butterfly_outputs_out_new_T_124)
connect _butterfly_outputs_out_new_WIRE_62, _butterfly_outputs_out_new_T_125
connect butterfly_outputs_out_0_31, _butterfly_outputs_out_new_WIRE_62
wire butterfly_outputs_out_1_31 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_63 : SInt<35>
node _butterfly_outputs_out_new_T_126 = asUInt(butterfly_outputs_product_7.imag)
node _butterfly_outputs_out_new_T_127 = asSInt(_butterfly_outputs_out_new_T_126)
connect _butterfly_outputs_out_new_WIRE_63, _butterfly_outputs_out_new_T_127
connect butterfly_outputs_out_1_31, _butterfly_outputs_out_new_WIRE_63
wire _butterfly_outputs_this_31 : SInt<35>
wire _butterfly_outputs_new_93 : SInt<35>
wire _butterfly_outputs_new_WIRE_93 : SInt<35>
node _butterfly_outputs_new_T_186 = asUInt(butterfly_outputs_out_0_31)
node _butterfly_outputs_new_T_187 = asSInt(_butterfly_outputs_new_T_186)
connect _butterfly_outputs_new_WIRE_93, _butterfly_outputs_new_T_187
connect _butterfly_outputs_new_93, _butterfly_outputs_new_WIRE_93
connect _butterfly_outputs_this_31, _butterfly_outputs_new_93
wire _butterfly_outputs_that_31 : SInt<35>
wire _butterfly_outputs_new_94 : SInt<35>
wire _butterfly_outputs_new_WIRE_94 : SInt<35>
node _butterfly_outputs_new_T_188 = asUInt(butterfly_outputs_out_1_31)
node _butterfly_outputs_new_T_189 = asSInt(_butterfly_outputs_new_T_188)
connect _butterfly_outputs_new_WIRE_94, _butterfly_outputs_new_T_189
connect _butterfly_outputs_new_94, _butterfly_outputs_new_WIRE_94
connect _butterfly_outputs_that_31, _butterfly_outputs_new_94
node _butterfly_outputs_T_93 = sub(_butterfly_outputs_this_31, _butterfly_outputs_that_31)
node _butterfly_outputs_T_94 = tail(_butterfly_outputs_T_93, 1)
node _butterfly_outputs_T_95 = asSInt(_butterfly_outputs_T_94)
wire _butterfly_outputs_new_95 : SInt<35>
wire _butterfly_outputs_new_WIRE_95 : SInt<35>
node _butterfly_outputs_new_T_190 = asUInt(_butterfly_outputs_T_95)
node _butterfly_outputs_new_T_191 = asSInt(_butterfly_outputs_new_T_190)
connect _butterfly_outputs_new_WIRE_95, _butterfly_outputs_new_T_191
connect _butterfly_outputs_new_95, _butterfly_outputs_new_WIRE_95
wire butterfly_outputs_1_7 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_result_real_new_15 : SInt<35>
wire _butterfly_outputs_result_real_new_WIRE_15 : SInt<35>
node _butterfly_outputs_result_real_new_T_30 = asUInt(_butterfly_outputs_new_92)
node _butterfly_outputs_result_real_new_T_31 = asSInt(_butterfly_outputs_result_real_new_T_30)
connect _butterfly_outputs_result_real_new_WIRE_15, _butterfly_outputs_result_real_new_T_31
connect _butterfly_outputs_result_real_new_15, _butterfly_outputs_result_real_new_WIRE_15
connect butterfly_outputs_1_7.real, _butterfly_outputs_result_real_new_15
wire _butterfly_outputs_result_imag_new_15 : SInt<35>
wire _butterfly_outputs_result_imag_new_WIRE_15 : SInt<35>
node _butterfly_outputs_result_imag_new_T_30 = asUInt(_butterfly_outputs_new_95)
node _butterfly_outputs_result_imag_new_T_31 = asSInt(_butterfly_outputs_result_imag_new_T_30)
connect _butterfly_outputs_result_imag_new_WIRE_15, _butterfly_outputs_result_imag_new_T_31
connect _butterfly_outputs_result_imag_new_15, _butterfly_outputs_result_imag_new_WIRE_15
connect butterfly_outputs_1_7.imag, _butterfly_outputs_result_imag_new_15
node _stage_outputs_2_5_stage_outputs_2_5_imag_T = shr(butterfly_outputs_0_7.imag, 17)
wire _stage_outputs_2_5_stage_outputs_2_5_imag_new : SInt<18>
wire _stage_outputs_2_5_stage_outputs_2_5_imag_new_WIRE : SInt<18>
node _stage_outputs_2_5_stage_outputs_2_5_imag_new_T = asUInt(_stage_outputs_2_5_stage_outputs_2_5_imag_T)
node _stage_outputs_2_5_stage_outputs_2_5_imag_new_T_1 = asSInt(_stage_outputs_2_5_stage_outputs_2_5_imag_new_T)
connect _stage_outputs_2_5_stage_outputs_2_5_imag_new_WIRE, _stage_outputs_2_5_stage_outputs_2_5_imag_new_T_1
connect _stage_outputs_2_5_stage_outputs_2_5_imag_new, _stage_outputs_2_5_stage_outputs_2_5_imag_new_WIRE
connect stage_outputs_2_5.imag, _stage_outputs_2_5_stage_outputs_2_5_imag_new
node _stage_outputs_2_5_stage_outputs_2_5_real_T = shr(butterfly_outputs_0_7.real, 17)
wire _stage_outputs_2_5_stage_outputs_2_5_real_new : SInt<18>
wire _stage_outputs_2_5_stage_outputs_2_5_real_new_WIRE : SInt<18>
node _stage_outputs_2_5_stage_outputs_2_5_real_new_T = asUInt(_stage_outputs_2_5_stage_outputs_2_5_real_T)
node _stage_outputs_2_5_stage_outputs_2_5_real_new_T_1 = asSInt(_stage_outputs_2_5_stage_outputs_2_5_real_new_T)
connect _stage_outputs_2_5_stage_outputs_2_5_real_new_WIRE, _stage_outputs_2_5_stage_outputs_2_5_real_new_T_1
connect _stage_outputs_2_5_stage_outputs_2_5_real_new, _stage_outputs_2_5_stage_outputs_2_5_real_new_WIRE
connect stage_outputs_2_5.real, _stage_outputs_2_5_stage_outputs_2_5_real_new
node _stage_outputs_2_7_stage_outputs_2_7_imag_T = shr(butterfly_outputs_1_7.imag, 17)
wire _stage_outputs_2_7_stage_outputs_2_7_imag_new : SInt<18>
wire _stage_outputs_2_7_stage_outputs_2_7_imag_new_WIRE : SInt<18>
node _stage_outputs_2_7_stage_outputs_2_7_imag_new_T = asUInt(_stage_outputs_2_7_stage_outputs_2_7_imag_T)
node _stage_outputs_2_7_stage_outputs_2_7_imag_new_T_1 = asSInt(_stage_outputs_2_7_stage_outputs_2_7_imag_new_T)
connect _stage_outputs_2_7_stage_outputs_2_7_imag_new_WIRE, _stage_outputs_2_7_stage_outputs_2_7_imag_new_T_1
connect _stage_outputs_2_7_stage_outputs_2_7_imag_new, _stage_outputs_2_7_stage_outputs_2_7_imag_new_WIRE
connect stage_outputs_2_7.imag, _stage_outputs_2_7_stage_outputs_2_7_imag_new
node _stage_outputs_2_7_stage_outputs_2_7_real_T = shr(butterfly_outputs_1_7.real, 17)
wire _stage_outputs_2_7_stage_outputs_2_7_real_new : SInt<18>
wire _stage_outputs_2_7_stage_outputs_2_7_real_new_WIRE : SInt<18>
node _stage_outputs_2_7_stage_outputs_2_7_real_new_T = asUInt(_stage_outputs_2_7_stage_outputs_2_7_real_T)
node _stage_outputs_2_7_stage_outputs_2_7_real_new_T_1 = asSInt(_stage_outputs_2_7_stage_outputs_2_7_real_new_T)
connect _stage_outputs_2_7_stage_outputs_2_7_real_new_WIRE, _stage_outputs_2_7_stage_outputs_2_7_real_new_T_1
connect _stage_outputs_2_7_stage_outputs_2_7_real_new, _stage_outputs_2_7_stage_outputs_2_7_real_new_WIRE
connect stage_outputs_2_7.real, _stage_outputs_2_7_stage_outputs_2_7_real_new
wire butterfly_outputs_product_c_p_d_out_0_8 : SInt<19>
wire _butterfly_outputs_product_c_p_d_out_new_WIRE_16 : SInt<19>
node _butterfly_outputs_product_c_p_d_out_new_T_32 = asUInt(twiddle[2].real)
node _butterfly_outputs_product_c_p_d_out_new_T_33 = asSInt(_butterfly_outputs_product_c_p_d_out_new_T_32)
connect _butterfly_outputs_product_c_p_d_out_new_WIRE_16, _butterfly_outputs_product_c_p_d_out_new_T_33
connect butterfly_outputs_product_c_p_d_out_0_8, _butterfly_outputs_product_c_p_d_out_new_WIRE_16
wire butterfly_outputs_product_c_p_d_out_1_8 : SInt<19>
wire _butterfly_outputs_product_c_p_d_out_new_WIRE_17 : SInt<19>
node _butterfly_outputs_product_c_p_d_out_new_T_34 = asUInt(twiddle[2].imag)
node _butterfly_outputs_product_c_p_d_out_new_T_35 = asSInt(_butterfly_outputs_product_c_p_d_out_new_T_34)
connect _butterfly_outputs_product_c_p_d_out_new_WIRE_17, _butterfly_outputs_product_c_p_d_out_new_T_35
connect butterfly_outputs_product_c_p_d_out_1_8, _butterfly_outputs_product_c_p_d_out_new_WIRE_17
wire _butterfly_outputs_product_c_p_d_this_8 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_16 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_24 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_48 = asUInt(butterfly_outputs_product_c_p_d_out_0_8)
node _butterfly_outputs_product_c_p_d_new_T_49 = asSInt(_butterfly_outputs_product_c_p_d_new_T_48)
connect _butterfly_outputs_product_c_p_d_new_WIRE_24, _butterfly_outputs_product_c_p_d_new_T_49
connect _butterfly_outputs_product_c_p_d_new_16, _butterfly_outputs_product_c_p_d_new_WIRE_24
connect _butterfly_outputs_product_c_p_d_this_8, _butterfly_outputs_product_c_p_d_new_16
wire _butterfly_outputs_product_c_p_d_that_8 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_17 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_25 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_50 = asUInt(butterfly_outputs_product_c_p_d_out_1_8)
node _butterfly_outputs_product_c_p_d_new_T_51 = asSInt(_butterfly_outputs_product_c_p_d_new_T_50)
connect _butterfly_outputs_product_c_p_d_new_WIRE_25, _butterfly_outputs_product_c_p_d_new_T_51
connect _butterfly_outputs_product_c_p_d_new_17, _butterfly_outputs_product_c_p_d_new_WIRE_25
connect _butterfly_outputs_product_c_p_d_that_8, _butterfly_outputs_product_c_p_d_new_17
node _butterfly_outputs_product_c_p_d_T_24 = add(_butterfly_outputs_product_c_p_d_this_8, _butterfly_outputs_product_c_p_d_that_8)
node _butterfly_outputs_product_c_p_d_T_25 = tail(_butterfly_outputs_product_c_p_d_T_24, 1)
node _butterfly_outputs_product_c_p_d_T_26 = asSInt(_butterfly_outputs_product_c_p_d_T_25)
wire butterfly_outputs_product_c_p_d_8 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_26 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_52 = asUInt(_butterfly_outputs_product_c_p_d_T_26)
node _butterfly_outputs_product_c_p_d_new_T_53 = asSInt(_butterfly_outputs_product_c_p_d_new_T_52)
connect _butterfly_outputs_product_c_p_d_new_WIRE_26, _butterfly_outputs_product_c_p_d_new_T_53
connect butterfly_outputs_product_c_p_d_8, _butterfly_outputs_product_c_p_d_new_WIRE_26
wire butterfly_outputs_product_a_p_b_out_0_8 : SInt<16>
wire _butterfly_outputs_product_a_p_b_out_new_WIRE_16 : SInt<16>
node _butterfly_outputs_product_a_p_b_out_new_T_32 = asUInt(stage_outputs_2_1.real)
node _butterfly_outputs_product_a_p_b_out_new_T_33 = asSInt(_butterfly_outputs_product_a_p_b_out_new_T_32)
connect _butterfly_outputs_product_a_p_b_out_new_WIRE_16, _butterfly_outputs_product_a_p_b_out_new_T_33
connect butterfly_outputs_product_a_p_b_out_0_8, _butterfly_outputs_product_a_p_b_out_new_WIRE_16
wire butterfly_outputs_product_a_p_b_out_1_8 : SInt<16>
wire _butterfly_outputs_product_a_p_b_out_new_WIRE_17 : SInt<16>
node _butterfly_outputs_product_a_p_b_out_new_T_34 = asUInt(stage_outputs_2_1.imag)
node _butterfly_outputs_product_a_p_b_out_new_T_35 = asSInt(_butterfly_outputs_product_a_p_b_out_new_T_34)
connect _butterfly_outputs_product_a_p_b_out_new_WIRE_17, _butterfly_outputs_product_a_p_b_out_new_T_35
connect butterfly_outputs_product_a_p_b_out_1_8, _butterfly_outputs_product_a_p_b_out_new_WIRE_17
wire _butterfly_outputs_product_a_p_b_this_8 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_16 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_24 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_48 = asUInt(butterfly_outputs_product_a_p_b_out_0_8)
node _butterfly_outputs_product_a_p_b_new_T_49 = asSInt(_butterfly_outputs_product_a_p_b_new_T_48)
connect _butterfly_outputs_product_a_p_b_new_WIRE_24, _butterfly_outputs_product_a_p_b_new_T_49
connect _butterfly_outputs_product_a_p_b_new_16, _butterfly_outputs_product_a_p_b_new_WIRE_24
connect _butterfly_outputs_product_a_p_b_this_8, _butterfly_outputs_product_a_p_b_new_16
wire _butterfly_outputs_product_a_p_b_that_8 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_17 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_25 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_50 = asUInt(butterfly_outputs_product_a_p_b_out_1_8)
node _butterfly_outputs_product_a_p_b_new_T_51 = asSInt(_butterfly_outputs_product_a_p_b_new_T_50)
connect _butterfly_outputs_product_a_p_b_new_WIRE_25, _butterfly_outputs_product_a_p_b_new_T_51
connect _butterfly_outputs_product_a_p_b_new_17, _butterfly_outputs_product_a_p_b_new_WIRE_25
connect _butterfly_outputs_product_a_p_b_that_8, _butterfly_outputs_product_a_p_b_new_17
node _butterfly_outputs_product_a_p_b_T_24 = add(_butterfly_outputs_product_a_p_b_this_8, _butterfly_outputs_product_a_p_b_that_8)
node _butterfly_outputs_product_a_p_b_T_25 = tail(_butterfly_outputs_product_a_p_b_T_24, 1)
node _butterfly_outputs_product_a_p_b_T_26 = asSInt(_butterfly_outputs_product_a_p_b_T_25)
wire butterfly_outputs_product_a_p_b_8 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_26 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_52 = asUInt(_butterfly_outputs_product_a_p_b_T_26)
node _butterfly_outputs_product_a_p_b_new_T_53 = asSInt(_butterfly_outputs_product_a_p_b_new_T_52)
connect _butterfly_outputs_product_a_p_b_new_WIRE_26, _butterfly_outputs_product_a_p_b_new_T_53
connect butterfly_outputs_product_a_p_b_8, _butterfly_outputs_product_a_p_b_new_WIRE_26
wire butterfly_outputs_product_b_m_a_out_0_8 : SInt<16>
wire _butterfly_outputs_product_b_m_a_out_new_WIRE_16 : SInt<16>
node _butterfly_outputs_product_b_m_a_out_new_T_32 = asUInt(stage_outputs_2_1.imag)
node _butterfly_outputs_product_b_m_a_out_new_T_33 = asSInt(_butterfly_outputs_product_b_m_a_out_new_T_32)
connect _butterfly_outputs_product_b_m_a_out_new_WIRE_16, _butterfly_outputs_product_b_m_a_out_new_T_33
connect butterfly_outputs_product_b_m_a_out_0_8, _butterfly_outputs_product_b_m_a_out_new_WIRE_16
wire butterfly_outputs_product_b_m_a_out_1_8 : SInt<16>
wire _butterfly_outputs_product_b_m_a_out_new_WIRE_17 : SInt<16>
node _butterfly_outputs_product_b_m_a_out_new_T_34 = asUInt(stage_outputs_2_1.real)
node _butterfly_outputs_product_b_m_a_out_new_T_35 = asSInt(_butterfly_outputs_product_b_m_a_out_new_T_34)
connect _butterfly_outputs_product_b_m_a_out_new_WIRE_17, _butterfly_outputs_product_b_m_a_out_new_T_35
connect butterfly_outputs_product_b_m_a_out_1_8, _butterfly_outputs_product_b_m_a_out_new_WIRE_17
wire _butterfly_outputs_product_b_m_a_this_8 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_16 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_24 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_48 = asUInt(butterfly_outputs_product_b_m_a_out_0_8)
node _butterfly_outputs_product_b_m_a_new_T_49 = asSInt(_butterfly_outputs_product_b_m_a_new_T_48)
connect _butterfly_outputs_product_b_m_a_new_WIRE_24, _butterfly_outputs_product_b_m_a_new_T_49
connect _butterfly_outputs_product_b_m_a_new_16, _butterfly_outputs_product_b_m_a_new_WIRE_24
connect _butterfly_outputs_product_b_m_a_this_8, _butterfly_outputs_product_b_m_a_new_16
wire _butterfly_outputs_product_b_m_a_that_8 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_17 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_25 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_50 = asUInt(butterfly_outputs_product_b_m_a_out_1_8)
node _butterfly_outputs_product_b_m_a_new_T_51 = asSInt(_butterfly_outputs_product_b_m_a_new_T_50)
connect _butterfly_outputs_product_b_m_a_new_WIRE_25, _butterfly_outputs_product_b_m_a_new_T_51
connect _butterfly_outputs_product_b_m_a_new_17, _butterfly_outputs_product_b_m_a_new_WIRE_25
connect _butterfly_outputs_product_b_m_a_that_8, _butterfly_outputs_product_b_m_a_new_17
node _butterfly_outputs_product_b_m_a_T_24 = sub(_butterfly_outputs_product_b_m_a_this_8, _butterfly_outputs_product_b_m_a_that_8)
node _butterfly_outputs_product_b_m_a_T_25 = tail(_butterfly_outputs_product_b_m_a_T_24, 1)
node _butterfly_outputs_product_b_m_a_T_26 = asSInt(_butterfly_outputs_product_b_m_a_T_25)
wire butterfly_outputs_product_b_m_a_8 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_26 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_52 = asUInt(_butterfly_outputs_product_b_m_a_T_26)
node _butterfly_outputs_product_b_m_a_new_T_53 = asSInt(_butterfly_outputs_product_b_m_a_new_T_52)
connect _butterfly_outputs_product_b_m_a_new_WIRE_26, _butterfly_outputs_product_b_m_a_new_T_53
connect butterfly_outputs_product_b_m_a_8, _butterfly_outputs_product_b_m_a_new_WIRE_26
node _butterfly_outputs_product_ac_p_ad_T_8 = mul(stage_outputs_2_1.real, butterfly_outputs_product_c_p_d_8)
wire butterfly_outputs_product_ac_p_ad_8 : SInt<35>
wire _butterfly_outputs_product_ac_p_ad_new_WIRE_8 : SInt<35>
node _butterfly_outputs_product_ac_p_ad_new_T_16 = asUInt(_butterfly_outputs_product_ac_p_ad_T_8)
node _butterfly_outputs_product_ac_p_ad_new_T_17 = asSInt(_butterfly_outputs_product_ac_p_ad_new_T_16)
connect _butterfly_outputs_product_ac_p_ad_new_WIRE_8, _butterfly_outputs_product_ac_p_ad_new_T_17
connect butterfly_outputs_product_ac_p_ad_8, _butterfly_outputs_product_ac_p_ad_new_WIRE_8
node _butterfly_outputs_product_ad_p_bd_T_8 = mul(butterfly_outputs_product_a_p_b_8, twiddle[2].imag)
wire butterfly_outputs_product_ad_p_bd_8 : SInt<35>
wire _butterfly_outputs_product_ad_p_bd_new_WIRE_8 : SInt<35>
node _butterfly_outputs_product_ad_p_bd_new_T_16 = asUInt(_butterfly_outputs_product_ad_p_bd_T_8)
node _butterfly_outputs_product_ad_p_bd_new_T_17 = asSInt(_butterfly_outputs_product_ad_p_bd_new_T_16)
connect _butterfly_outputs_product_ad_p_bd_new_WIRE_8, _butterfly_outputs_product_ad_p_bd_new_T_17
connect butterfly_outputs_product_ad_p_bd_8, _butterfly_outputs_product_ad_p_bd_new_WIRE_8
node _butterfly_outputs_product_bc_m_ac_T_8 = mul(butterfly_outputs_product_b_m_a_8, twiddle[2].real)
wire butterfly_outputs_product_bc_m_ac_8 : SInt<35>
wire _butterfly_outputs_product_bc_m_ac_new_WIRE_8 : SInt<35>
node _butterfly_outputs_product_bc_m_ac_new_T_16 = asUInt(_butterfly_outputs_product_bc_m_ac_T_8)
node _butterfly_outputs_product_bc_m_ac_new_T_17 = asSInt(_butterfly_outputs_product_bc_m_ac_new_T_16)
connect _butterfly_outputs_product_bc_m_ac_new_WIRE_8, _butterfly_outputs_product_bc_m_ac_new_T_17
connect butterfly_outputs_product_bc_m_ac_8, _butterfly_outputs_product_bc_m_ac_new_WIRE_8
wire butterfly_outputs_product_out_0_16 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_32 : SInt<35>
node _butterfly_outputs_product_out_new_T_64 = asUInt(butterfly_outputs_product_ac_p_ad_8)
node _butterfly_outputs_product_out_new_T_65 = asSInt(_butterfly_outputs_product_out_new_T_64)
connect _butterfly_outputs_product_out_new_WIRE_32, _butterfly_outputs_product_out_new_T_65
connect butterfly_outputs_product_out_0_16, _butterfly_outputs_product_out_new_WIRE_32
wire butterfly_outputs_product_out_1_16 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_33 : SInt<35>
node _butterfly_outputs_product_out_new_T_66 = asUInt(butterfly_outputs_product_ad_p_bd_8)
node _butterfly_outputs_product_out_new_T_67 = asSInt(_butterfly_outputs_product_out_new_T_66)
connect _butterfly_outputs_product_out_new_WIRE_33, _butterfly_outputs_product_out_new_T_67
connect butterfly_outputs_product_out_1_16, _butterfly_outputs_product_out_new_WIRE_33
wire _butterfly_outputs_product_this_16 : SInt<35>
wire _butterfly_outputs_product_new_48 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_48 : SInt<35>
node _butterfly_outputs_product_new_T_96 = asUInt(butterfly_outputs_product_out_0_16)
node _butterfly_outputs_product_new_T_97 = asSInt(_butterfly_outputs_product_new_T_96)
connect _butterfly_outputs_product_new_WIRE_48, _butterfly_outputs_product_new_T_97
connect _butterfly_outputs_product_new_48, _butterfly_outputs_product_new_WIRE_48
connect _butterfly_outputs_product_this_16, _butterfly_outputs_product_new_48
wire _butterfly_outputs_product_that_16 : SInt<35>
wire _butterfly_outputs_product_new_49 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_49 : SInt<35>
node _butterfly_outputs_product_new_T_98 = asUInt(butterfly_outputs_product_out_1_16)
node _butterfly_outputs_product_new_T_99 = asSInt(_butterfly_outputs_product_new_T_98)
connect _butterfly_outputs_product_new_WIRE_49, _butterfly_outputs_product_new_T_99
connect _butterfly_outputs_product_new_49, _butterfly_outputs_product_new_WIRE_49
connect _butterfly_outputs_product_that_16, _butterfly_outputs_product_new_49
node _butterfly_outputs_product_T_48 = sub(_butterfly_outputs_product_this_16, _butterfly_outputs_product_that_16)
node _butterfly_outputs_product_T_49 = tail(_butterfly_outputs_product_T_48, 1)
node _butterfly_outputs_product_T_50 = asSInt(_butterfly_outputs_product_T_49)
wire _butterfly_outputs_product_new_50 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_50 : SInt<35>
node _butterfly_outputs_product_new_T_100 = asUInt(_butterfly_outputs_product_T_50)
node _butterfly_outputs_product_new_T_101 = asSInt(_butterfly_outputs_product_new_T_100)
connect _butterfly_outputs_product_new_WIRE_50, _butterfly_outputs_product_new_T_101
connect _butterfly_outputs_product_new_50, _butterfly_outputs_product_new_WIRE_50
wire butterfly_outputs_product_out_0_17 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_34 : SInt<35>
node _butterfly_outputs_product_out_new_T_68 = asUInt(butterfly_outputs_product_ac_p_ad_8)
node _butterfly_outputs_product_out_new_T_69 = asSInt(_butterfly_outputs_product_out_new_T_68)
connect _butterfly_outputs_product_out_new_WIRE_34, _butterfly_outputs_product_out_new_T_69
connect butterfly_outputs_product_out_0_17, _butterfly_outputs_product_out_new_WIRE_34
wire butterfly_outputs_product_out_1_17 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_35 : SInt<35>
node _butterfly_outputs_product_out_new_T_70 = asUInt(butterfly_outputs_product_bc_m_ac_8)
node _butterfly_outputs_product_out_new_T_71 = asSInt(_butterfly_outputs_product_out_new_T_70)
connect _butterfly_outputs_product_out_new_WIRE_35, _butterfly_outputs_product_out_new_T_71
connect butterfly_outputs_product_out_1_17, _butterfly_outputs_product_out_new_WIRE_35
wire _butterfly_outputs_product_this_17 : SInt<35>
wire _butterfly_outputs_product_new_51 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_51 : SInt<35>
node _butterfly_outputs_product_new_T_102 = asUInt(butterfly_outputs_product_out_0_17)
node _butterfly_outputs_product_new_T_103 = asSInt(_butterfly_outputs_product_new_T_102)
connect _butterfly_outputs_product_new_WIRE_51, _butterfly_outputs_product_new_T_103
connect _butterfly_outputs_product_new_51, _butterfly_outputs_product_new_WIRE_51
connect _butterfly_outputs_product_this_17, _butterfly_outputs_product_new_51
wire _butterfly_outputs_product_that_17 : SInt<35>
wire _butterfly_outputs_product_new_52 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_52 : SInt<35>
node _butterfly_outputs_product_new_T_104 = asUInt(butterfly_outputs_product_out_1_17)
node _butterfly_outputs_product_new_T_105 = asSInt(_butterfly_outputs_product_new_T_104)
connect _butterfly_outputs_product_new_WIRE_52, _butterfly_outputs_product_new_T_105
connect _butterfly_outputs_product_new_52, _butterfly_outputs_product_new_WIRE_52
connect _butterfly_outputs_product_that_17, _butterfly_outputs_product_new_52
node _butterfly_outputs_product_T_51 = add(_butterfly_outputs_product_this_17, _butterfly_outputs_product_that_17)
node _butterfly_outputs_product_T_52 = tail(_butterfly_outputs_product_T_51, 1)
node _butterfly_outputs_product_T_53 = asSInt(_butterfly_outputs_product_T_52)
wire _butterfly_outputs_product_new_53 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_53 : SInt<35>
node _butterfly_outputs_product_new_T_106 = asUInt(_butterfly_outputs_product_T_53)
node _butterfly_outputs_product_new_T_107 = asSInt(_butterfly_outputs_product_new_T_106)
connect _butterfly_outputs_product_new_WIRE_53, _butterfly_outputs_product_new_T_107
connect _butterfly_outputs_product_new_53, _butterfly_outputs_product_new_WIRE_53
wire butterfly_outputs_product_8 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_product_result_real_new_8 : SInt<35>
wire _butterfly_outputs_product_result_real_new_WIRE_8 : SInt<35>
node _butterfly_outputs_product_result_real_new_T_16 = asUInt(_butterfly_outputs_product_new_50)
node _butterfly_outputs_product_result_real_new_T_17 = asSInt(_butterfly_outputs_product_result_real_new_T_16)
connect _butterfly_outputs_product_result_real_new_WIRE_8, _butterfly_outputs_product_result_real_new_T_17
connect _butterfly_outputs_product_result_real_new_8, _butterfly_outputs_product_result_real_new_WIRE_8
connect butterfly_outputs_product_8.real, _butterfly_outputs_product_result_real_new_8
wire _butterfly_outputs_product_result_imag_new_8 : SInt<35>
wire _butterfly_outputs_product_result_imag_new_WIRE_8 : SInt<35>
node _butterfly_outputs_product_result_imag_new_T_16 = asUInt(_butterfly_outputs_product_new_53)
node _butterfly_outputs_product_result_imag_new_T_17 = asSInt(_butterfly_outputs_product_result_imag_new_T_16)
connect _butterfly_outputs_product_result_imag_new_WIRE_8, _butterfly_outputs_product_result_imag_new_T_17
connect _butterfly_outputs_product_result_imag_new_8, _butterfly_outputs_product_result_imag_new_WIRE_8
connect butterfly_outputs_product_8.imag, _butterfly_outputs_product_result_imag_new_8
node _butterfly_outputs_out_T_32 = shl(stage_outputs_2_0.real, 17)
wire butterfly_outputs_out_0_32 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_64 : SInt<35>
node _butterfly_outputs_out_new_T_128 = asUInt(_butterfly_outputs_out_T_32)
node _butterfly_outputs_out_new_T_129 = asSInt(_butterfly_outputs_out_new_T_128)
connect _butterfly_outputs_out_new_WIRE_64, _butterfly_outputs_out_new_T_129
connect butterfly_outputs_out_0_32, _butterfly_outputs_out_new_WIRE_64
wire butterfly_outputs_out_1_32 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_65 : SInt<35>
node _butterfly_outputs_out_new_T_130 = asUInt(butterfly_outputs_product_8.real)
node _butterfly_outputs_out_new_T_131 = asSInt(_butterfly_outputs_out_new_T_130)
connect _butterfly_outputs_out_new_WIRE_65, _butterfly_outputs_out_new_T_131
connect butterfly_outputs_out_1_32, _butterfly_outputs_out_new_WIRE_65
wire _butterfly_outputs_this_32 : SInt<35>
wire _butterfly_outputs_new_96 : SInt<35>
wire _butterfly_outputs_new_WIRE_96 : SInt<35>
node _butterfly_outputs_new_T_192 = asUInt(butterfly_outputs_out_0_32)
node _butterfly_outputs_new_T_193 = asSInt(_butterfly_outputs_new_T_192)
connect _butterfly_outputs_new_WIRE_96, _butterfly_outputs_new_T_193
connect _butterfly_outputs_new_96, _butterfly_outputs_new_WIRE_96
connect _butterfly_outputs_this_32, _butterfly_outputs_new_96
wire _butterfly_outputs_that_32 : SInt<35>
wire _butterfly_outputs_new_97 : SInt<35>
wire _butterfly_outputs_new_WIRE_97 : SInt<35>
node _butterfly_outputs_new_T_194 = asUInt(butterfly_outputs_out_1_32)
node _butterfly_outputs_new_T_195 = asSInt(_butterfly_outputs_new_T_194)
connect _butterfly_outputs_new_WIRE_97, _butterfly_outputs_new_T_195
connect _butterfly_outputs_new_97, _butterfly_outputs_new_WIRE_97
connect _butterfly_outputs_that_32, _butterfly_outputs_new_97
node _butterfly_outputs_T_96 = add(_butterfly_outputs_this_32, _butterfly_outputs_that_32)
node _butterfly_outputs_T_97 = tail(_butterfly_outputs_T_96, 1)
node _butterfly_outputs_T_98 = asSInt(_butterfly_outputs_T_97)
wire _butterfly_outputs_new_98 : SInt<35>
wire _butterfly_outputs_new_WIRE_98 : SInt<35>
node _butterfly_outputs_new_T_196 = asUInt(_butterfly_outputs_T_98)
node _butterfly_outputs_new_T_197 = asSInt(_butterfly_outputs_new_T_196)
connect _butterfly_outputs_new_WIRE_98, _butterfly_outputs_new_T_197
connect _butterfly_outputs_new_98, _butterfly_outputs_new_WIRE_98
node _butterfly_outputs_out_T_33 = shl(stage_outputs_2_0.imag, 17)
wire butterfly_outputs_out_0_33 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_66 : SInt<35>
node _butterfly_outputs_out_new_T_132 = asUInt(_butterfly_outputs_out_T_33)
node _butterfly_outputs_out_new_T_133 = asSInt(_butterfly_outputs_out_new_T_132)
connect _butterfly_outputs_out_new_WIRE_66, _butterfly_outputs_out_new_T_133
connect butterfly_outputs_out_0_33, _butterfly_outputs_out_new_WIRE_66
wire butterfly_outputs_out_1_33 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_67 : SInt<35>
node _butterfly_outputs_out_new_T_134 = asUInt(butterfly_outputs_product_8.imag)
node _butterfly_outputs_out_new_T_135 = asSInt(_butterfly_outputs_out_new_T_134)
connect _butterfly_outputs_out_new_WIRE_67, _butterfly_outputs_out_new_T_135
connect butterfly_outputs_out_1_33, _butterfly_outputs_out_new_WIRE_67
wire _butterfly_outputs_this_33 : SInt<35>
wire _butterfly_outputs_new_99 : SInt<35>
wire _butterfly_outputs_new_WIRE_99 : SInt<35>
node _butterfly_outputs_new_T_198 = asUInt(butterfly_outputs_out_0_33)
node _butterfly_outputs_new_T_199 = asSInt(_butterfly_outputs_new_T_198)
connect _butterfly_outputs_new_WIRE_99, _butterfly_outputs_new_T_199
connect _butterfly_outputs_new_99, _butterfly_outputs_new_WIRE_99
connect _butterfly_outputs_this_33, _butterfly_outputs_new_99
wire _butterfly_outputs_that_33 : SInt<35>
wire _butterfly_outputs_new_100 : SInt<35>
wire _butterfly_outputs_new_WIRE_100 : SInt<35>
node _butterfly_outputs_new_T_200 = asUInt(butterfly_outputs_out_1_33)
node _butterfly_outputs_new_T_201 = asSInt(_butterfly_outputs_new_T_200)
connect _butterfly_outputs_new_WIRE_100, _butterfly_outputs_new_T_201
connect _butterfly_outputs_new_100, _butterfly_outputs_new_WIRE_100
connect _butterfly_outputs_that_33, _butterfly_outputs_new_100
node _butterfly_outputs_T_99 = add(_butterfly_outputs_this_33, _butterfly_outputs_that_33)
node _butterfly_outputs_T_100 = tail(_butterfly_outputs_T_99, 1)
node _butterfly_outputs_T_101 = asSInt(_butterfly_outputs_T_100)
wire _butterfly_outputs_new_101 : SInt<35>
wire _butterfly_outputs_new_WIRE_101 : SInt<35>
node _butterfly_outputs_new_T_202 = asUInt(_butterfly_outputs_T_101)
node _butterfly_outputs_new_T_203 = asSInt(_butterfly_outputs_new_T_202)
connect _butterfly_outputs_new_WIRE_101, _butterfly_outputs_new_T_203
connect _butterfly_outputs_new_101, _butterfly_outputs_new_WIRE_101
wire butterfly_outputs_0_8 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_result_real_new_16 : SInt<35>
wire _butterfly_outputs_result_real_new_WIRE_16 : SInt<35>
node _butterfly_outputs_result_real_new_T_32 = asUInt(_butterfly_outputs_new_98)
node _butterfly_outputs_result_real_new_T_33 = asSInt(_butterfly_outputs_result_real_new_T_32)
connect _butterfly_outputs_result_real_new_WIRE_16, _butterfly_outputs_result_real_new_T_33
connect _butterfly_outputs_result_real_new_16, _butterfly_outputs_result_real_new_WIRE_16
connect butterfly_outputs_0_8.real, _butterfly_outputs_result_real_new_16
wire _butterfly_outputs_result_imag_new_16 : SInt<35>
wire _butterfly_outputs_result_imag_new_WIRE_16 : SInt<35>
node _butterfly_outputs_result_imag_new_T_32 = asUInt(_butterfly_outputs_new_101)
node _butterfly_outputs_result_imag_new_T_33 = asSInt(_butterfly_outputs_result_imag_new_T_32)
connect _butterfly_outputs_result_imag_new_WIRE_16, _butterfly_outputs_result_imag_new_T_33
connect _butterfly_outputs_result_imag_new_16, _butterfly_outputs_result_imag_new_WIRE_16
connect butterfly_outputs_0_8.imag, _butterfly_outputs_result_imag_new_16
node _butterfly_outputs_out_T_34 = shl(stage_outputs_2_0.real, 17)
wire butterfly_outputs_out_0_34 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_68 : SInt<35>
node _butterfly_outputs_out_new_T_136 = asUInt(_butterfly_outputs_out_T_34)
node _butterfly_outputs_out_new_T_137 = asSInt(_butterfly_outputs_out_new_T_136)
connect _butterfly_outputs_out_new_WIRE_68, _butterfly_outputs_out_new_T_137
connect butterfly_outputs_out_0_34, _butterfly_outputs_out_new_WIRE_68
wire butterfly_outputs_out_1_34 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_69 : SInt<35>
node _butterfly_outputs_out_new_T_138 = asUInt(butterfly_outputs_product_8.real)
node _butterfly_outputs_out_new_T_139 = asSInt(_butterfly_outputs_out_new_T_138)
connect _butterfly_outputs_out_new_WIRE_69, _butterfly_outputs_out_new_T_139
connect butterfly_outputs_out_1_34, _butterfly_outputs_out_new_WIRE_69
wire _butterfly_outputs_this_34 : SInt<35>
wire _butterfly_outputs_new_102 : SInt<35>
wire _butterfly_outputs_new_WIRE_102 : SInt<35>
node _butterfly_outputs_new_T_204 = asUInt(butterfly_outputs_out_0_34)
node _butterfly_outputs_new_T_205 = asSInt(_butterfly_outputs_new_T_204)
connect _butterfly_outputs_new_WIRE_102, _butterfly_outputs_new_T_205
connect _butterfly_outputs_new_102, _butterfly_outputs_new_WIRE_102
connect _butterfly_outputs_this_34, _butterfly_outputs_new_102
wire _butterfly_outputs_that_34 : SInt<35>
wire _butterfly_outputs_new_103 : SInt<35>
wire _butterfly_outputs_new_WIRE_103 : SInt<35>
node _butterfly_outputs_new_T_206 = asUInt(butterfly_outputs_out_1_34)
node _butterfly_outputs_new_T_207 = asSInt(_butterfly_outputs_new_T_206)
connect _butterfly_outputs_new_WIRE_103, _butterfly_outputs_new_T_207
connect _butterfly_outputs_new_103, _butterfly_outputs_new_WIRE_103
connect _butterfly_outputs_that_34, _butterfly_outputs_new_103
node _butterfly_outputs_T_102 = sub(_butterfly_outputs_this_34, _butterfly_outputs_that_34)
node _butterfly_outputs_T_103 = tail(_butterfly_outputs_T_102, 1)
node _butterfly_outputs_T_104 = asSInt(_butterfly_outputs_T_103)
wire _butterfly_outputs_new_104 : SInt<35>
wire _butterfly_outputs_new_WIRE_104 : SInt<35>
node _butterfly_outputs_new_T_208 = asUInt(_butterfly_outputs_T_104)
node _butterfly_outputs_new_T_209 = asSInt(_butterfly_outputs_new_T_208)
connect _butterfly_outputs_new_WIRE_104, _butterfly_outputs_new_T_209
connect _butterfly_outputs_new_104, _butterfly_outputs_new_WIRE_104
node _butterfly_outputs_out_T_35 = shl(stage_outputs_2_0.imag, 17)
wire butterfly_outputs_out_0_35 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_70 : SInt<35>
node _butterfly_outputs_out_new_T_140 = asUInt(_butterfly_outputs_out_T_35)
node _butterfly_outputs_out_new_T_141 = asSInt(_butterfly_outputs_out_new_T_140)
connect _butterfly_outputs_out_new_WIRE_70, _butterfly_outputs_out_new_T_141
connect butterfly_outputs_out_0_35, _butterfly_outputs_out_new_WIRE_70
wire butterfly_outputs_out_1_35 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_71 : SInt<35>
node _butterfly_outputs_out_new_T_142 = asUInt(butterfly_outputs_product_8.imag)
node _butterfly_outputs_out_new_T_143 = asSInt(_butterfly_outputs_out_new_T_142)
connect _butterfly_outputs_out_new_WIRE_71, _butterfly_outputs_out_new_T_143
connect butterfly_outputs_out_1_35, _butterfly_outputs_out_new_WIRE_71
wire _butterfly_outputs_this_35 : SInt<35>
wire _butterfly_outputs_new_105 : SInt<35>
wire _butterfly_outputs_new_WIRE_105 : SInt<35>
node _butterfly_outputs_new_T_210 = asUInt(butterfly_outputs_out_0_35)
node _butterfly_outputs_new_T_211 = asSInt(_butterfly_outputs_new_T_210)
connect _butterfly_outputs_new_WIRE_105, _butterfly_outputs_new_T_211
connect _butterfly_outputs_new_105, _butterfly_outputs_new_WIRE_105
connect _butterfly_outputs_this_35, _butterfly_outputs_new_105
wire _butterfly_outputs_that_35 : SInt<35>
wire _butterfly_outputs_new_106 : SInt<35>
wire _butterfly_outputs_new_WIRE_106 : SInt<35>
node _butterfly_outputs_new_T_212 = asUInt(butterfly_outputs_out_1_35)
node _butterfly_outputs_new_T_213 = asSInt(_butterfly_outputs_new_T_212)
connect _butterfly_outputs_new_WIRE_106, _butterfly_outputs_new_T_213
connect _butterfly_outputs_new_106, _butterfly_outputs_new_WIRE_106
connect _butterfly_outputs_that_35, _butterfly_outputs_new_106
node _butterfly_outputs_T_105 = sub(_butterfly_outputs_this_35, _butterfly_outputs_that_35)
node _butterfly_outputs_T_106 = tail(_butterfly_outputs_T_105, 1)
node _butterfly_outputs_T_107 = asSInt(_butterfly_outputs_T_106)
wire _butterfly_outputs_new_107 : SInt<35>
wire _butterfly_outputs_new_WIRE_107 : SInt<35>
node _butterfly_outputs_new_T_214 = asUInt(_butterfly_outputs_T_107)
node _butterfly_outputs_new_T_215 = asSInt(_butterfly_outputs_new_T_214)
connect _butterfly_outputs_new_WIRE_107, _butterfly_outputs_new_T_215
connect _butterfly_outputs_new_107, _butterfly_outputs_new_WIRE_107
wire butterfly_outputs_1_8 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_result_real_new_17 : SInt<35>
wire _butterfly_outputs_result_real_new_WIRE_17 : SInt<35>
node _butterfly_outputs_result_real_new_T_34 = asUInt(_butterfly_outputs_new_104)
node _butterfly_outputs_result_real_new_T_35 = asSInt(_butterfly_outputs_result_real_new_T_34)
connect _butterfly_outputs_result_real_new_WIRE_17, _butterfly_outputs_result_real_new_T_35
connect _butterfly_outputs_result_real_new_17, _butterfly_outputs_result_real_new_WIRE_17
connect butterfly_outputs_1_8.real, _butterfly_outputs_result_real_new_17
wire _butterfly_outputs_result_imag_new_17 : SInt<35>
wire _butterfly_outputs_result_imag_new_WIRE_17 : SInt<35>
node _butterfly_outputs_result_imag_new_T_34 = asUInt(_butterfly_outputs_new_107)
node _butterfly_outputs_result_imag_new_T_35 = asSInt(_butterfly_outputs_result_imag_new_T_34)
connect _butterfly_outputs_result_imag_new_WIRE_17, _butterfly_outputs_result_imag_new_T_35
connect _butterfly_outputs_result_imag_new_17, _butterfly_outputs_result_imag_new_WIRE_17
connect butterfly_outputs_1_8.imag, _butterfly_outputs_result_imag_new_17
node _stage_outputs_3_0_stage_outputs_3_0_imag_T = shr(butterfly_outputs_0_8.imag, 17)
wire _stage_outputs_3_0_stage_outputs_3_0_imag_new : SInt<18>
wire _stage_outputs_3_0_stage_outputs_3_0_imag_new_WIRE : SInt<18>
node _stage_outputs_3_0_stage_outputs_3_0_imag_new_T = asUInt(_stage_outputs_3_0_stage_outputs_3_0_imag_T)
node _stage_outputs_3_0_stage_outputs_3_0_imag_new_T_1 = asSInt(_stage_outputs_3_0_stage_outputs_3_0_imag_new_T)
connect _stage_outputs_3_0_stage_outputs_3_0_imag_new_WIRE, _stage_outputs_3_0_stage_outputs_3_0_imag_new_T_1
connect _stage_outputs_3_0_stage_outputs_3_0_imag_new, _stage_outputs_3_0_stage_outputs_3_0_imag_new_WIRE
connect stage_outputs_3_0.imag, _stage_outputs_3_0_stage_outputs_3_0_imag_new
node _stage_outputs_3_0_stage_outputs_3_0_real_T = shr(butterfly_outputs_0_8.real, 17)
wire _stage_outputs_3_0_stage_outputs_3_0_real_new : SInt<18>
wire _stage_outputs_3_0_stage_outputs_3_0_real_new_WIRE : SInt<18>
node _stage_outputs_3_0_stage_outputs_3_0_real_new_T = asUInt(_stage_outputs_3_0_stage_outputs_3_0_real_T)
node _stage_outputs_3_0_stage_outputs_3_0_real_new_T_1 = asSInt(_stage_outputs_3_0_stage_outputs_3_0_real_new_T)
connect _stage_outputs_3_0_stage_outputs_3_0_real_new_WIRE, _stage_outputs_3_0_stage_outputs_3_0_real_new_T_1
connect _stage_outputs_3_0_stage_outputs_3_0_real_new, _stage_outputs_3_0_stage_outputs_3_0_real_new_WIRE
connect stage_outputs_3_0.real, _stage_outputs_3_0_stage_outputs_3_0_real_new
node _stage_outputs_3_1_stage_outputs_3_1_imag_T = shr(butterfly_outputs_1_8.imag, 17)
wire _stage_outputs_3_1_stage_outputs_3_1_imag_new : SInt<18>
wire _stage_outputs_3_1_stage_outputs_3_1_imag_new_WIRE : SInt<18>
node _stage_outputs_3_1_stage_outputs_3_1_imag_new_T = asUInt(_stage_outputs_3_1_stage_outputs_3_1_imag_T)
node _stage_outputs_3_1_stage_outputs_3_1_imag_new_T_1 = asSInt(_stage_outputs_3_1_stage_outputs_3_1_imag_new_T)
connect _stage_outputs_3_1_stage_outputs_3_1_imag_new_WIRE, _stage_outputs_3_1_stage_outputs_3_1_imag_new_T_1
connect _stage_outputs_3_1_stage_outputs_3_1_imag_new, _stage_outputs_3_1_stage_outputs_3_1_imag_new_WIRE
connect stage_outputs_3_1.imag, _stage_outputs_3_1_stage_outputs_3_1_imag_new
node _stage_outputs_3_1_stage_outputs_3_1_real_T = shr(butterfly_outputs_1_8.real, 17)
wire _stage_outputs_3_1_stage_outputs_3_1_real_new : SInt<18>
wire _stage_outputs_3_1_stage_outputs_3_1_real_new_WIRE : SInt<18>
node _stage_outputs_3_1_stage_outputs_3_1_real_new_T = asUInt(_stage_outputs_3_1_stage_outputs_3_1_real_T)
node _stage_outputs_3_1_stage_outputs_3_1_real_new_T_1 = asSInt(_stage_outputs_3_1_stage_outputs_3_1_real_new_T)
connect _stage_outputs_3_1_stage_outputs_3_1_real_new_WIRE, _stage_outputs_3_1_stage_outputs_3_1_real_new_T_1
connect _stage_outputs_3_1_stage_outputs_3_1_real_new, _stage_outputs_3_1_stage_outputs_3_1_real_new_WIRE
connect stage_outputs_3_1.real, _stage_outputs_3_1_stage_outputs_3_1_real_new
wire butterfly_outputs_product_c_p_d_out_0_9 : SInt<19>
wire _butterfly_outputs_product_c_p_d_out_new_WIRE_18 : SInt<19>
node _butterfly_outputs_product_c_p_d_out_new_T_36 = asUInt(twiddle[3].real)
node _butterfly_outputs_product_c_p_d_out_new_T_37 = asSInt(_butterfly_outputs_product_c_p_d_out_new_T_36)
connect _butterfly_outputs_product_c_p_d_out_new_WIRE_18, _butterfly_outputs_product_c_p_d_out_new_T_37
connect butterfly_outputs_product_c_p_d_out_0_9, _butterfly_outputs_product_c_p_d_out_new_WIRE_18
wire butterfly_outputs_product_c_p_d_out_1_9 : SInt<19>
wire _butterfly_outputs_product_c_p_d_out_new_WIRE_19 : SInt<19>
node _butterfly_outputs_product_c_p_d_out_new_T_38 = asUInt(twiddle[3].imag)
node _butterfly_outputs_product_c_p_d_out_new_T_39 = asSInt(_butterfly_outputs_product_c_p_d_out_new_T_38)
connect _butterfly_outputs_product_c_p_d_out_new_WIRE_19, _butterfly_outputs_product_c_p_d_out_new_T_39
connect butterfly_outputs_product_c_p_d_out_1_9, _butterfly_outputs_product_c_p_d_out_new_WIRE_19
wire _butterfly_outputs_product_c_p_d_this_9 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_18 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_27 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_54 = asUInt(butterfly_outputs_product_c_p_d_out_0_9)
node _butterfly_outputs_product_c_p_d_new_T_55 = asSInt(_butterfly_outputs_product_c_p_d_new_T_54)
connect _butterfly_outputs_product_c_p_d_new_WIRE_27, _butterfly_outputs_product_c_p_d_new_T_55
connect _butterfly_outputs_product_c_p_d_new_18, _butterfly_outputs_product_c_p_d_new_WIRE_27
connect _butterfly_outputs_product_c_p_d_this_9, _butterfly_outputs_product_c_p_d_new_18
wire _butterfly_outputs_product_c_p_d_that_9 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_19 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_28 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_56 = asUInt(butterfly_outputs_product_c_p_d_out_1_9)
node _butterfly_outputs_product_c_p_d_new_T_57 = asSInt(_butterfly_outputs_product_c_p_d_new_T_56)
connect _butterfly_outputs_product_c_p_d_new_WIRE_28, _butterfly_outputs_product_c_p_d_new_T_57
connect _butterfly_outputs_product_c_p_d_new_19, _butterfly_outputs_product_c_p_d_new_WIRE_28
connect _butterfly_outputs_product_c_p_d_that_9, _butterfly_outputs_product_c_p_d_new_19
node _butterfly_outputs_product_c_p_d_T_27 = add(_butterfly_outputs_product_c_p_d_this_9, _butterfly_outputs_product_c_p_d_that_9)
node _butterfly_outputs_product_c_p_d_T_28 = tail(_butterfly_outputs_product_c_p_d_T_27, 1)
node _butterfly_outputs_product_c_p_d_T_29 = asSInt(_butterfly_outputs_product_c_p_d_T_28)
wire butterfly_outputs_product_c_p_d_9 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_29 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_58 = asUInt(_butterfly_outputs_product_c_p_d_T_29)
node _butterfly_outputs_product_c_p_d_new_T_59 = asSInt(_butterfly_outputs_product_c_p_d_new_T_58)
connect _butterfly_outputs_product_c_p_d_new_WIRE_29, _butterfly_outputs_product_c_p_d_new_T_59
connect butterfly_outputs_product_c_p_d_9, _butterfly_outputs_product_c_p_d_new_WIRE_29
wire butterfly_outputs_product_a_p_b_out_0_9 : SInt<16>
wire _butterfly_outputs_product_a_p_b_out_new_WIRE_18 : SInt<16>
node _butterfly_outputs_product_a_p_b_out_new_T_36 = asUInt(stage_outputs_2_3.real)
node _butterfly_outputs_product_a_p_b_out_new_T_37 = asSInt(_butterfly_outputs_product_a_p_b_out_new_T_36)
connect _butterfly_outputs_product_a_p_b_out_new_WIRE_18, _butterfly_outputs_product_a_p_b_out_new_T_37
connect butterfly_outputs_product_a_p_b_out_0_9, _butterfly_outputs_product_a_p_b_out_new_WIRE_18
wire butterfly_outputs_product_a_p_b_out_1_9 : SInt<16>
wire _butterfly_outputs_product_a_p_b_out_new_WIRE_19 : SInt<16>
node _butterfly_outputs_product_a_p_b_out_new_T_38 = asUInt(stage_outputs_2_3.imag)
node _butterfly_outputs_product_a_p_b_out_new_T_39 = asSInt(_butterfly_outputs_product_a_p_b_out_new_T_38)
connect _butterfly_outputs_product_a_p_b_out_new_WIRE_19, _butterfly_outputs_product_a_p_b_out_new_T_39
connect butterfly_outputs_product_a_p_b_out_1_9, _butterfly_outputs_product_a_p_b_out_new_WIRE_19
wire _butterfly_outputs_product_a_p_b_this_9 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_18 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_27 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_54 = asUInt(butterfly_outputs_product_a_p_b_out_0_9)
node _butterfly_outputs_product_a_p_b_new_T_55 = asSInt(_butterfly_outputs_product_a_p_b_new_T_54)
connect _butterfly_outputs_product_a_p_b_new_WIRE_27, _butterfly_outputs_product_a_p_b_new_T_55
connect _butterfly_outputs_product_a_p_b_new_18, _butterfly_outputs_product_a_p_b_new_WIRE_27
connect _butterfly_outputs_product_a_p_b_this_9, _butterfly_outputs_product_a_p_b_new_18
wire _butterfly_outputs_product_a_p_b_that_9 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_19 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_28 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_56 = asUInt(butterfly_outputs_product_a_p_b_out_1_9)
node _butterfly_outputs_product_a_p_b_new_T_57 = asSInt(_butterfly_outputs_product_a_p_b_new_T_56)
connect _butterfly_outputs_product_a_p_b_new_WIRE_28, _butterfly_outputs_product_a_p_b_new_T_57
connect _butterfly_outputs_product_a_p_b_new_19, _butterfly_outputs_product_a_p_b_new_WIRE_28
connect _butterfly_outputs_product_a_p_b_that_9, _butterfly_outputs_product_a_p_b_new_19
node _butterfly_outputs_product_a_p_b_T_27 = add(_butterfly_outputs_product_a_p_b_this_9, _butterfly_outputs_product_a_p_b_that_9)
node _butterfly_outputs_product_a_p_b_T_28 = tail(_butterfly_outputs_product_a_p_b_T_27, 1)
node _butterfly_outputs_product_a_p_b_T_29 = asSInt(_butterfly_outputs_product_a_p_b_T_28)
wire butterfly_outputs_product_a_p_b_9 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_29 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_58 = asUInt(_butterfly_outputs_product_a_p_b_T_29)
node _butterfly_outputs_product_a_p_b_new_T_59 = asSInt(_butterfly_outputs_product_a_p_b_new_T_58)
connect _butterfly_outputs_product_a_p_b_new_WIRE_29, _butterfly_outputs_product_a_p_b_new_T_59
connect butterfly_outputs_product_a_p_b_9, _butterfly_outputs_product_a_p_b_new_WIRE_29
wire butterfly_outputs_product_b_m_a_out_0_9 : SInt<16>
wire _butterfly_outputs_product_b_m_a_out_new_WIRE_18 : SInt<16>
node _butterfly_outputs_product_b_m_a_out_new_T_36 = asUInt(stage_outputs_2_3.imag)
node _butterfly_outputs_product_b_m_a_out_new_T_37 = asSInt(_butterfly_outputs_product_b_m_a_out_new_T_36)
connect _butterfly_outputs_product_b_m_a_out_new_WIRE_18, _butterfly_outputs_product_b_m_a_out_new_T_37
connect butterfly_outputs_product_b_m_a_out_0_9, _butterfly_outputs_product_b_m_a_out_new_WIRE_18
wire butterfly_outputs_product_b_m_a_out_1_9 : SInt<16>
wire _butterfly_outputs_product_b_m_a_out_new_WIRE_19 : SInt<16>
node _butterfly_outputs_product_b_m_a_out_new_T_38 = asUInt(stage_outputs_2_3.real)
node _butterfly_outputs_product_b_m_a_out_new_T_39 = asSInt(_butterfly_outputs_product_b_m_a_out_new_T_38)
connect _butterfly_outputs_product_b_m_a_out_new_WIRE_19, _butterfly_outputs_product_b_m_a_out_new_T_39
connect butterfly_outputs_product_b_m_a_out_1_9, _butterfly_outputs_product_b_m_a_out_new_WIRE_19
wire _butterfly_outputs_product_b_m_a_this_9 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_18 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_27 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_54 = asUInt(butterfly_outputs_product_b_m_a_out_0_9)
node _butterfly_outputs_product_b_m_a_new_T_55 = asSInt(_butterfly_outputs_product_b_m_a_new_T_54)
connect _butterfly_outputs_product_b_m_a_new_WIRE_27, _butterfly_outputs_product_b_m_a_new_T_55
connect _butterfly_outputs_product_b_m_a_new_18, _butterfly_outputs_product_b_m_a_new_WIRE_27
connect _butterfly_outputs_product_b_m_a_this_9, _butterfly_outputs_product_b_m_a_new_18
wire _butterfly_outputs_product_b_m_a_that_9 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_19 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_28 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_56 = asUInt(butterfly_outputs_product_b_m_a_out_1_9)
node _butterfly_outputs_product_b_m_a_new_T_57 = asSInt(_butterfly_outputs_product_b_m_a_new_T_56)
connect _butterfly_outputs_product_b_m_a_new_WIRE_28, _butterfly_outputs_product_b_m_a_new_T_57
connect _butterfly_outputs_product_b_m_a_new_19, _butterfly_outputs_product_b_m_a_new_WIRE_28
connect _butterfly_outputs_product_b_m_a_that_9, _butterfly_outputs_product_b_m_a_new_19
node _butterfly_outputs_product_b_m_a_T_27 = sub(_butterfly_outputs_product_b_m_a_this_9, _butterfly_outputs_product_b_m_a_that_9)
node _butterfly_outputs_product_b_m_a_T_28 = tail(_butterfly_outputs_product_b_m_a_T_27, 1)
node _butterfly_outputs_product_b_m_a_T_29 = asSInt(_butterfly_outputs_product_b_m_a_T_28)
wire butterfly_outputs_product_b_m_a_9 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_29 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_58 = asUInt(_butterfly_outputs_product_b_m_a_T_29)
node _butterfly_outputs_product_b_m_a_new_T_59 = asSInt(_butterfly_outputs_product_b_m_a_new_T_58)
connect _butterfly_outputs_product_b_m_a_new_WIRE_29, _butterfly_outputs_product_b_m_a_new_T_59
connect butterfly_outputs_product_b_m_a_9, _butterfly_outputs_product_b_m_a_new_WIRE_29
node _butterfly_outputs_product_ac_p_ad_T_9 = mul(stage_outputs_2_3.real, butterfly_outputs_product_c_p_d_9)
wire butterfly_outputs_product_ac_p_ad_9 : SInt<35>
wire _butterfly_outputs_product_ac_p_ad_new_WIRE_9 : SInt<35>
node _butterfly_outputs_product_ac_p_ad_new_T_18 = asUInt(_butterfly_outputs_product_ac_p_ad_T_9)
node _butterfly_outputs_product_ac_p_ad_new_T_19 = asSInt(_butterfly_outputs_product_ac_p_ad_new_T_18)
connect _butterfly_outputs_product_ac_p_ad_new_WIRE_9, _butterfly_outputs_product_ac_p_ad_new_T_19
connect butterfly_outputs_product_ac_p_ad_9, _butterfly_outputs_product_ac_p_ad_new_WIRE_9
node _butterfly_outputs_product_ad_p_bd_T_9 = mul(butterfly_outputs_product_a_p_b_9, twiddle[3].imag)
wire butterfly_outputs_product_ad_p_bd_9 : SInt<35>
wire _butterfly_outputs_product_ad_p_bd_new_WIRE_9 : SInt<35>
node _butterfly_outputs_product_ad_p_bd_new_T_18 = asUInt(_butterfly_outputs_product_ad_p_bd_T_9)
node _butterfly_outputs_product_ad_p_bd_new_T_19 = asSInt(_butterfly_outputs_product_ad_p_bd_new_T_18)
connect _butterfly_outputs_product_ad_p_bd_new_WIRE_9, _butterfly_outputs_product_ad_p_bd_new_T_19
connect butterfly_outputs_product_ad_p_bd_9, _butterfly_outputs_product_ad_p_bd_new_WIRE_9
node _butterfly_outputs_product_bc_m_ac_T_9 = mul(butterfly_outputs_product_b_m_a_9, twiddle[3].real)
wire butterfly_outputs_product_bc_m_ac_9 : SInt<35>
wire _butterfly_outputs_product_bc_m_ac_new_WIRE_9 : SInt<35>
node _butterfly_outputs_product_bc_m_ac_new_T_18 = asUInt(_butterfly_outputs_product_bc_m_ac_T_9)
node _butterfly_outputs_product_bc_m_ac_new_T_19 = asSInt(_butterfly_outputs_product_bc_m_ac_new_T_18)
connect _butterfly_outputs_product_bc_m_ac_new_WIRE_9, _butterfly_outputs_product_bc_m_ac_new_T_19
connect butterfly_outputs_product_bc_m_ac_9, _butterfly_outputs_product_bc_m_ac_new_WIRE_9
wire butterfly_outputs_product_out_0_18 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_36 : SInt<35>
node _butterfly_outputs_product_out_new_T_72 = asUInt(butterfly_outputs_product_ac_p_ad_9)
node _butterfly_outputs_product_out_new_T_73 = asSInt(_butterfly_outputs_product_out_new_T_72)
connect _butterfly_outputs_product_out_new_WIRE_36, _butterfly_outputs_product_out_new_T_73
connect butterfly_outputs_product_out_0_18, _butterfly_outputs_product_out_new_WIRE_36
wire butterfly_outputs_product_out_1_18 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_37 : SInt<35>
node _butterfly_outputs_product_out_new_T_74 = asUInt(butterfly_outputs_product_ad_p_bd_9)
node _butterfly_outputs_product_out_new_T_75 = asSInt(_butterfly_outputs_product_out_new_T_74)
connect _butterfly_outputs_product_out_new_WIRE_37, _butterfly_outputs_product_out_new_T_75
connect butterfly_outputs_product_out_1_18, _butterfly_outputs_product_out_new_WIRE_37
wire _butterfly_outputs_product_this_18 : SInt<35>
wire _butterfly_outputs_product_new_54 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_54 : SInt<35>
node _butterfly_outputs_product_new_T_108 = asUInt(butterfly_outputs_product_out_0_18)
node _butterfly_outputs_product_new_T_109 = asSInt(_butterfly_outputs_product_new_T_108)
connect _butterfly_outputs_product_new_WIRE_54, _butterfly_outputs_product_new_T_109
connect _butterfly_outputs_product_new_54, _butterfly_outputs_product_new_WIRE_54
connect _butterfly_outputs_product_this_18, _butterfly_outputs_product_new_54
wire _butterfly_outputs_product_that_18 : SInt<35>
wire _butterfly_outputs_product_new_55 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_55 : SInt<35>
node _butterfly_outputs_product_new_T_110 = asUInt(butterfly_outputs_product_out_1_18)
node _butterfly_outputs_product_new_T_111 = asSInt(_butterfly_outputs_product_new_T_110)
connect _butterfly_outputs_product_new_WIRE_55, _butterfly_outputs_product_new_T_111
connect _butterfly_outputs_product_new_55, _butterfly_outputs_product_new_WIRE_55
connect _butterfly_outputs_product_that_18, _butterfly_outputs_product_new_55
node _butterfly_outputs_product_T_54 = sub(_butterfly_outputs_product_this_18, _butterfly_outputs_product_that_18)
node _butterfly_outputs_product_T_55 = tail(_butterfly_outputs_product_T_54, 1)
node _butterfly_outputs_product_T_56 = asSInt(_butterfly_outputs_product_T_55)
wire _butterfly_outputs_product_new_56 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_56 : SInt<35>
node _butterfly_outputs_product_new_T_112 = asUInt(_butterfly_outputs_product_T_56)
node _butterfly_outputs_product_new_T_113 = asSInt(_butterfly_outputs_product_new_T_112)
connect _butterfly_outputs_product_new_WIRE_56, _butterfly_outputs_product_new_T_113
connect _butterfly_outputs_product_new_56, _butterfly_outputs_product_new_WIRE_56
wire butterfly_outputs_product_out_0_19 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_38 : SInt<35>
node _butterfly_outputs_product_out_new_T_76 = asUInt(butterfly_outputs_product_ac_p_ad_9)
node _butterfly_outputs_product_out_new_T_77 = asSInt(_butterfly_outputs_product_out_new_T_76)
connect _butterfly_outputs_product_out_new_WIRE_38, _butterfly_outputs_product_out_new_T_77
connect butterfly_outputs_product_out_0_19, _butterfly_outputs_product_out_new_WIRE_38
wire butterfly_outputs_product_out_1_19 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_39 : SInt<35>
node _butterfly_outputs_product_out_new_T_78 = asUInt(butterfly_outputs_product_bc_m_ac_9)
node _butterfly_outputs_product_out_new_T_79 = asSInt(_butterfly_outputs_product_out_new_T_78)
connect _butterfly_outputs_product_out_new_WIRE_39, _butterfly_outputs_product_out_new_T_79
connect butterfly_outputs_product_out_1_19, _butterfly_outputs_product_out_new_WIRE_39
wire _butterfly_outputs_product_this_19 : SInt<35>
wire _butterfly_outputs_product_new_57 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_57 : SInt<35>
node _butterfly_outputs_product_new_T_114 = asUInt(butterfly_outputs_product_out_0_19)
node _butterfly_outputs_product_new_T_115 = asSInt(_butterfly_outputs_product_new_T_114)
connect _butterfly_outputs_product_new_WIRE_57, _butterfly_outputs_product_new_T_115
connect _butterfly_outputs_product_new_57, _butterfly_outputs_product_new_WIRE_57
connect _butterfly_outputs_product_this_19, _butterfly_outputs_product_new_57
wire _butterfly_outputs_product_that_19 : SInt<35>
wire _butterfly_outputs_product_new_58 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_58 : SInt<35>
node _butterfly_outputs_product_new_T_116 = asUInt(butterfly_outputs_product_out_1_19)
node _butterfly_outputs_product_new_T_117 = asSInt(_butterfly_outputs_product_new_T_116)
connect _butterfly_outputs_product_new_WIRE_58, _butterfly_outputs_product_new_T_117
connect _butterfly_outputs_product_new_58, _butterfly_outputs_product_new_WIRE_58
connect _butterfly_outputs_product_that_19, _butterfly_outputs_product_new_58
node _butterfly_outputs_product_T_57 = add(_butterfly_outputs_product_this_19, _butterfly_outputs_product_that_19)
node _butterfly_outputs_product_T_58 = tail(_butterfly_outputs_product_T_57, 1)
node _butterfly_outputs_product_T_59 = asSInt(_butterfly_outputs_product_T_58)
wire _butterfly_outputs_product_new_59 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_59 : SInt<35>
node _butterfly_outputs_product_new_T_118 = asUInt(_butterfly_outputs_product_T_59)
node _butterfly_outputs_product_new_T_119 = asSInt(_butterfly_outputs_product_new_T_118)
connect _butterfly_outputs_product_new_WIRE_59, _butterfly_outputs_product_new_T_119
connect _butterfly_outputs_product_new_59, _butterfly_outputs_product_new_WIRE_59
wire butterfly_outputs_product_9 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_product_result_real_new_9 : SInt<35>
wire _butterfly_outputs_product_result_real_new_WIRE_9 : SInt<35>
node _butterfly_outputs_product_result_real_new_T_18 = asUInt(_butterfly_outputs_product_new_56)
node _butterfly_outputs_product_result_real_new_T_19 = asSInt(_butterfly_outputs_product_result_real_new_T_18)
connect _butterfly_outputs_product_result_real_new_WIRE_9, _butterfly_outputs_product_result_real_new_T_19
connect _butterfly_outputs_product_result_real_new_9, _butterfly_outputs_product_result_real_new_WIRE_9
connect butterfly_outputs_product_9.real, _butterfly_outputs_product_result_real_new_9
wire _butterfly_outputs_product_result_imag_new_9 : SInt<35>
wire _butterfly_outputs_product_result_imag_new_WIRE_9 : SInt<35>
node _butterfly_outputs_product_result_imag_new_T_18 = asUInt(_butterfly_outputs_product_new_59)
node _butterfly_outputs_product_result_imag_new_T_19 = asSInt(_butterfly_outputs_product_result_imag_new_T_18)
connect _butterfly_outputs_product_result_imag_new_WIRE_9, _butterfly_outputs_product_result_imag_new_T_19
connect _butterfly_outputs_product_result_imag_new_9, _butterfly_outputs_product_result_imag_new_WIRE_9
connect butterfly_outputs_product_9.imag, _butterfly_outputs_product_result_imag_new_9
node _butterfly_outputs_out_T_36 = shl(stage_outputs_2_2.real, 17)
wire butterfly_outputs_out_0_36 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_72 : SInt<35>
node _butterfly_outputs_out_new_T_144 = asUInt(_butterfly_outputs_out_T_36)
node _butterfly_outputs_out_new_T_145 = asSInt(_butterfly_outputs_out_new_T_144)
connect _butterfly_outputs_out_new_WIRE_72, _butterfly_outputs_out_new_T_145
connect butterfly_outputs_out_0_36, _butterfly_outputs_out_new_WIRE_72
wire butterfly_outputs_out_1_36 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_73 : SInt<35>
node _butterfly_outputs_out_new_T_146 = asUInt(butterfly_outputs_product_9.real)
node _butterfly_outputs_out_new_T_147 = asSInt(_butterfly_outputs_out_new_T_146)
connect _butterfly_outputs_out_new_WIRE_73, _butterfly_outputs_out_new_T_147
connect butterfly_outputs_out_1_36, _butterfly_outputs_out_new_WIRE_73
wire _butterfly_outputs_this_36 : SInt<35>
wire _butterfly_outputs_new_108 : SInt<35>
wire _butterfly_outputs_new_WIRE_108 : SInt<35>
node _butterfly_outputs_new_T_216 = asUInt(butterfly_outputs_out_0_36)
node _butterfly_outputs_new_T_217 = asSInt(_butterfly_outputs_new_T_216)
connect _butterfly_outputs_new_WIRE_108, _butterfly_outputs_new_T_217
connect _butterfly_outputs_new_108, _butterfly_outputs_new_WIRE_108
connect _butterfly_outputs_this_36, _butterfly_outputs_new_108
wire _butterfly_outputs_that_36 : SInt<35>
wire _butterfly_outputs_new_109 : SInt<35>
wire _butterfly_outputs_new_WIRE_109 : SInt<35>
node _butterfly_outputs_new_T_218 = asUInt(butterfly_outputs_out_1_36)
node _butterfly_outputs_new_T_219 = asSInt(_butterfly_outputs_new_T_218)
connect _butterfly_outputs_new_WIRE_109, _butterfly_outputs_new_T_219
connect _butterfly_outputs_new_109, _butterfly_outputs_new_WIRE_109
connect _butterfly_outputs_that_36, _butterfly_outputs_new_109
node _butterfly_outputs_T_108 = add(_butterfly_outputs_this_36, _butterfly_outputs_that_36)
node _butterfly_outputs_T_109 = tail(_butterfly_outputs_T_108, 1)
node _butterfly_outputs_T_110 = asSInt(_butterfly_outputs_T_109)
wire _butterfly_outputs_new_110 : SInt<35>
wire _butterfly_outputs_new_WIRE_110 : SInt<35>
node _butterfly_outputs_new_T_220 = asUInt(_butterfly_outputs_T_110)
node _butterfly_outputs_new_T_221 = asSInt(_butterfly_outputs_new_T_220)
connect _butterfly_outputs_new_WIRE_110, _butterfly_outputs_new_T_221
connect _butterfly_outputs_new_110, _butterfly_outputs_new_WIRE_110
node _butterfly_outputs_out_T_37 = shl(stage_outputs_2_2.imag, 17)
wire butterfly_outputs_out_0_37 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_74 : SInt<35>
node _butterfly_outputs_out_new_T_148 = asUInt(_butterfly_outputs_out_T_37)
node _butterfly_outputs_out_new_T_149 = asSInt(_butterfly_outputs_out_new_T_148)
connect _butterfly_outputs_out_new_WIRE_74, _butterfly_outputs_out_new_T_149
connect butterfly_outputs_out_0_37, _butterfly_outputs_out_new_WIRE_74
wire butterfly_outputs_out_1_37 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_75 : SInt<35>
node _butterfly_outputs_out_new_T_150 = asUInt(butterfly_outputs_product_9.imag)
node _butterfly_outputs_out_new_T_151 = asSInt(_butterfly_outputs_out_new_T_150)
connect _butterfly_outputs_out_new_WIRE_75, _butterfly_outputs_out_new_T_151
connect butterfly_outputs_out_1_37, _butterfly_outputs_out_new_WIRE_75
wire _butterfly_outputs_this_37 : SInt<35>
wire _butterfly_outputs_new_111 : SInt<35>
wire _butterfly_outputs_new_WIRE_111 : SInt<35>
node _butterfly_outputs_new_T_222 = asUInt(butterfly_outputs_out_0_37)
node _butterfly_outputs_new_T_223 = asSInt(_butterfly_outputs_new_T_222)
connect _butterfly_outputs_new_WIRE_111, _butterfly_outputs_new_T_223
connect _butterfly_outputs_new_111, _butterfly_outputs_new_WIRE_111
connect _butterfly_outputs_this_37, _butterfly_outputs_new_111
wire _butterfly_outputs_that_37 : SInt<35>
wire _butterfly_outputs_new_112 : SInt<35>
wire _butterfly_outputs_new_WIRE_112 : SInt<35>
node _butterfly_outputs_new_T_224 = asUInt(butterfly_outputs_out_1_37)
node _butterfly_outputs_new_T_225 = asSInt(_butterfly_outputs_new_T_224)
connect _butterfly_outputs_new_WIRE_112, _butterfly_outputs_new_T_225
connect _butterfly_outputs_new_112, _butterfly_outputs_new_WIRE_112
connect _butterfly_outputs_that_37, _butterfly_outputs_new_112
node _butterfly_outputs_T_111 = add(_butterfly_outputs_this_37, _butterfly_outputs_that_37)
node _butterfly_outputs_T_112 = tail(_butterfly_outputs_T_111, 1)
node _butterfly_outputs_T_113 = asSInt(_butterfly_outputs_T_112)
wire _butterfly_outputs_new_113 : SInt<35>
wire _butterfly_outputs_new_WIRE_113 : SInt<35>
node _butterfly_outputs_new_T_226 = asUInt(_butterfly_outputs_T_113)
node _butterfly_outputs_new_T_227 = asSInt(_butterfly_outputs_new_T_226)
connect _butterfly_outputs_new_WIRE_113, _butterfly_outputs_new_T_227
connect _butterfly_outputs_new_113, _butterfly_outputs_new_WIRE_113
wire butterfly_outputs_0_9 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_result_real_new_18 : SInt<35>
wire _butterfly_outputs_result_real_new_WIRE_18 : SInt<35>
node _butterfly_outputs_result_real_new_T_36 = asUInt(_butterfly_outputs_new_110)
node _butterfly_outputs_result_real_new_T_37 = asSInt(_butterfly_outputs_result_real_new_T_36)
connect _butterfly_outputs_result_real_new_WIRE_18, _butterfly_outputs_result_real_new_T_37
connect _butterfly_outputs_result_real_new_18, _butterfly_outputs_result_real_new_WIRE_18
connect butterfly_outputs_0_9.real, _butterfly_outputs_result_real_new_18
wire _butterfly_outputs_result_imag_new_18 : SInt<35>
wire _butterfly_outputs_result_imag_new_WIRE_18 : SInt<35>
node _butterfly_outputs_result_imag_new_T_36 = asUInt(_butterfly_outputs_new_113)
node _butterfly_outputs_result_imag_new_T_37 = asSInt(_butterfly_outputs_result_imag_new_T_36)
connect _butterfly_outputs_result_imag_new_WIRE_18, _butterfly_outputs_result_imag_new_T_37
connect _butterfly_outputs_result_imag_new_18, _butterfly_outputs_result_imag_new_WIRE_18
connect butterfly_outputs_0_9.imag, _butterfly_outputs_result_imag_new_18
node _butterfly_outputs_out_T_38 = shl(stage_outputs_2_2.real, 17)
wire butterfly_outputs_out_0_38 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_76 : SInt<35>
node _butterfly_outputs_out_new_T_152 = asUInt(_butterfly_outputs_out_T_38)
node _butterfly_outputs_out_new_T_153 = asSInt(_butterfly_outputs_out_new_T_152)
connect _butterfly_outputs_out_new_WIRE_76, _butterfly_outputs_out_new_T_153
connect butterfly_outputs_out_0_38, _butterfly_outputs_out_new_WIRE_76
wire butterfly_outputs_out_1_38 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_77 : SInt<35>
node _butterfly_outputs_out_new_T_154 = asUInt(butterfly_outputs_product_9.real)
node _butterfly_outputs_out_new_T_155 = asSInt(_butterfly_outputs_out_new_T_154)
connect _butterfly_outputs_out_new_WIRE_77, _butterfly_outputs_out_new_T_155
connect butterfly_outputs_out_1_38, _butterfly_outputs_out_new_WIRE_77
wire _butterfly_outputs_this_38 : SInt<35>
wire _butterfly_outputs_new_114 : SInt<35>
wire _butterfly_outputs_new_WIRE_114 : SInt<35>
node _butterfly_outputs_new_T_228 = asUInt(butterfly_outputs_out_0_38)
node _butterfly_outputs_new_T_229 = asSInt(_butterfly_outputs_new_T_228)
connect _butterfly_outputs_new_WIRE_114, _butterfly_outputs_new_T_229
connect _butterfly_outputs_new_114, _butterfly_outputs_new_WIRE_114
connect _butterfly_outputs_this_38, _butterfly_outputs_new_114
wire _butterfly_outputs_that_38 : SInt<35>
wire _butterfly_outputs_new_115 : SInt<35>
wire _butterfly_outputs_new_WIRE_115 : SInt<35>
node _butterfly_outputs_new_T_230 = asUInt(butterfly_outputs_out_1_38)
node _butterfly_outputs_new_T_231 = asSInt(_butterfly_outputs_new_T_230)
connect _butterfly_outputs_new_WIRE_115, _butterfly_outputs_new_T_231
connect _butterfly_outputs_new_115, _butterfly_outputs_new_WIRE_115
connect _butterfly_outputs_that_38, _butterfly_outputs_new_115
node _butterfly_outputs_T_114 = sub(_butterfly_outputs_this_38, _butterfly_outputs_that_38)
node _butterfly_outputs_T_115 = tail(_butterfly_outputs_T_114, 1)
node _butterfly_outputs_T_116 = asSInt(_butterfly_outputs_T_115)
wire _butterfly_outputs_new_116 : SInt<35>
wire _butterfly_outputs_new_WIRE_116 : SInt<35>
node _butterfly_outputs_new_T_232 = asUInt(_butterfly_outputs_T_116)
node _butterfly_outputs_new_T_233 = asSInt(_butterfly_outputs_new_T_232)
connect _butterfly_outputs_new_WIRE_116, _butterfly_outputs_new_T_233
connect _butterfly_outputs_new_116, _butterfly_outputs_new_WIRE_116
node _butterfly_outputs_out_T_39 = shl(stage_outputs_2_2.imag, 17)
wire butterfly_outputs_out_0_39 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_78 : SInt<35>
node _butterfly_outputs_out_new_T_156 = asUInt(_butterfly_outputs_out_T_39)
node _butterfly_outputs_out_new_T_157 = asSInt(_butterfly_outputs_out_new_T_156)
connect _butterfly_outputs_out_new_WIRE_78, _butterfly_outputs_out_new_T_157
connect butterfly_outputs_out_0_39, _butterfly_outputs_out_new_WIRE_78
wire butterfly_outputs_out_1_39 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_79 : SInt<35>
node _butterfly_outputs_out_new_T_158 = asUInt(butterfly_outputs_product_9.imag)
node _butterfly_outputs_out_new_T_159 = asSInt(_butterfly_outputs_out_new_T_158)
connect _butterfly_outputs_out_new_WIRE_79, _butterfly_outputs_out_new_T_159
connect butterfly_outputs_out_1_39, _butterfly_outputs_out_new_WIRE_79
wire _butterfly_outputs_this_39 : SInt<35>
wire _butterfly_outputs_new_117 : SInt<35>
wire _butterfly_outputs_new_WIRE_117 : SInt<35>
node _butterfly_outputs_new_T_234 = asUInt(butterfly_outputs_out_0_39)
node _butterfly_outputs_new_T_235 = asSInt(_butterfly_outputs_new_T_234)
connect _butterfly_outputs_new_WIRE_117, _butterfly_outputs_new_T_235
connect _butterfly_outputs_new_117, _butterfly_outputs_new_WIRE_117
connect _butterfly_outputs_this_39, _butterfly_outputs_new_117
wire _butterfly_outputs_that_39 : SInt<35>
wire _butterfly_outputs_new_118 : SInt<35>
wire _butterfly_outputs_new_WIRE_118 : SInt<35>
node _butterfly_outputs_new_T_236 = asUInt(butterfly_outputs_out_1_39)
node _butterfly_outputs_new_T_237 = asSInt(_butterfly_outputs_new_T_236)
connect _butterfly_outputs_new_WIRE_118, _butterfly_outputs_new_T_237
connect _butterfly_outputs_new_118, _butterfly_outputs_new_WIRE_118
connect _butterfly_outputs_that_39, _butterfly_outputs_new_118
node _butterfly_outputs_T_117 = sub(_butterfly_outputs_this_39, _butterfly_outputs_that_39)
node _butterfly_outputs_T_118 = tail(_butterfly_outputs_T_117, 1)
node _butterfly_outputs_T_119 = asSInt(_butterfly_outputs_T_118)
wire _butterfly_outputs_new_119 : SInt<35>
wire _butterfly_outputs_new_WIRE_119 : SInt<35>
node _butterfly_outputs_new_T_238 = asUInt(_butterfly_outputs_T_119)
node _butterfly_outputs_new_T_239 = asSInt(_butterfly_outputs_new_T_238)
connect _butterfly_outputs_new_WIRE_119, _butterfly_outputs_new_T_239
connect _butterfly_outputs_new_119, _butterfly_outputs_new_WIRE_119
wire butterfly_outputs_1_9 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_result_real_new_19 : SInt<35>
wire _butterfly_outputs_result_real_new_WIRE_19 : SInt<35>
node _butterfly_outputs_result_real_new_T_38 = asUInt(_butterfly_outputs_new_116)
node _butterfly_outputs_result_real_new_T_39 = asSInt(_butterfly_outputs_result_real_new_T_38)
connect _butterfly_outputs_result_real_new_WIRE_19, _butterfly_outputs_result_real_new_T_39
connect _butterfly_outputs_result_real_new_19, _butterfly_outputs_result_real_new_WIRE_19
connect butterfly_outputs_1_9.real, _butterfly_outputs_result_real_new_19
wire _butterfly_outputs_result_imag_new_19 : SInt<35>
wire _butterfly_outputs_result_imag_new_WIRE_19 : SInt<35>
node _butterfly_outputs_result_imag_new_T_38 = asUInt(_butterfly_outputs_new_119)
node _butterfly_outputs_result_imag_new_T_39 = asSInt(_butterfly_outputs_result_imag_new_T_38)
connect _butterfly_outputs_result_imag_new_WIRE_19, _butterfly_outputs_result_imag_new_T_39
connect _butterfly_outputs_result_imag_new_19, _butterfly_outputs_result_imag_new_WIRE_19
connect butterfly_outputs_1_9.imag, _butterfly_outputs_result_imag_new_19
node _stage_outputs_3_2_stage_outputs_3_2_imag_T = shr(butterfly_outputs_0_9.imag, 17)
wire _stage_outputs_3_2_stage_outputs_3_2_imag_new : SInt<18>
wire _stage_outputs_3_2_stage_outputs_3_2_imag_new_WIRE : SInt<18>
node _stage_outputs_3_2_stage_outputs_3_2_imag_new_T = asUInt(_stage_outputs_3_2_stage_outputs_3_2_imag_T)
node _stage_outputs_3_2_stage_outputs_3_2_imag_new_T_1 = asSInt(_stage_outputs_3_2_stage_outputs_3_2_imag_new_T)
connect _stage_outputs_3_2_stage_outputs_3_2_imag_new_WIRE, _stage_outputs_3_2_stage_outputs_3_2_imag_new_T_1
connect _stage_outputs_3_2_stage_outputs_3_2_imag_new, _stage_outputs_3_2_stage_outputs_3_2_imag_new_WIRE
connect stage_outputs_3_2.imag, _stage_outputs_3_2_stage_outputs_3_2_imag_new
node _stage_outputs_3_2_stage_outputs_3_2_real_T = shr(butterfly_outputs_0_9.real, 17)
wire _stage_outputs_3_2_stage_outputs_3_2_real_new : SInt<18>
wire _stage_outputs_3_2_stage_outputs_3_2_real_new_WIRE : SInt<18>
node _stage_outputs_3_2_stage_outputs_3_2_real_new_T = asUInt(_stage_outputs_3_2_stage_outputs_3_2_real_T)
node _stage_outputs_3_2_stage_outputs_3_2_real_new_T_1 = asSInt(_stage_outputs_3_2_stage_outputs_3_2_real_new_T)
connect _stage_outputs_3_2_stage_outputs_3_2_real_new_WIRE, _stage_outputs_3_2_stage_outputs_3_2_real_new_T_1
connect _stage_outputs_3_2_stage_outputs_3_2_real_new, _stage_outputs_3_2_stage_outputs_3_2_real_new_WIRE
connect stage_outputs_3_2.real, _stage_outputs_3_2_stage_outputs_3_2_real_new
node _stage_outputs_3_3_stage_outputs_3_3_imag_T = shr(butterfly_outputs_1_9.imag, 17)
wire _stage_outputs_3_3_stage_outputs_3_3_imag_new : SInt<18>
wire _stage_outputs_3_3_stage_outputs_3_3_imag_new_WIRE : SInt<18>
node _stage_outputs_3_3_stage_outputs_3_3_imag_new_T = asUInt(_stage_outputs_3_3_stage_outputs_3_3_imag_T)
node _stage_outputs_3_3_stage_outputs_3_3_imag_new_T_1 = asSInt(_stage_outputs_3_3_stage_outputs_3_3_imag_new_T)
connect _stage_outputs_3_3_stage_outputs_3_3_imag_new_WIRE, _stage_outputs_3_3_stage_outputs_3_3_imag_new_T_1
connect _stage_outputs_3_3_stage_outputs_3_3_imag_new, _stage_outputs_3_3_stage_outputs_3_3_imag_new_WIRE
connect stage_outputs_3_3.imag, _stage_outputs_3_3_stage_outputs_3_3_imag_new
node _stage_outputs_3_3_stage_outputs_3_3_real_T = shr(butterfly_outputs_1_9.real, 17)
wire _stage_outputs_3_3_stage_outputs_3_3_real_new : SInt<18>
wire _stage_outputs_3_3_stage_outputs_3_3_real_new_WIRE : SInt<18>
node _stage_outputs_3_3_stage_outputs_3_3_real_new_T = asUInt(_stage_outputs_3_3_stage_outputs_3_3_real_T)
node _stage_outputs_3_3_stage_outputs_3_3_real_new_T_1 = asSInt(_stage_outputs_3_3_stage_outputs_3_3_real_new_T)
connect _stage_outputs_3_3_stage_outputs_3_3_real_new_WIRE, _stage_outputs_3_3_stage_outputs_3_3_real_new_T_1
connect _stage_outputs_3_3_stage_outputs_3_3_real_new, _stage_outputs_3_3_stage_outputs_3_3_real_new_WIRE
connect stage_outputs_3_3.real, _stage_outputs_3_3_stage_outputs_3_3_real_new
wire butterfly_outputs_product_c_p_d_out_0_10 : SInt<19>
wire _butterfly_outputs_product_c_p_d_out_new_WIRE_20 : SInt<19>
node _butterfly_outputs_product_c_p_d_out_new_T_40 = asUInt(twiddle[5].real)
node _butterfly_outputs_product_c_p_d_out_new_T_41 = asSInt(_butterfly_outputs_product_c_p_d_out_new_T_40)
connect _butterfly_outputs_product_c_p_d_out_new_WIRE_20, _butterfly_outputs_product_c_p_d_out_new_T_41
connect butterfly_outputs_product_c_p_d_out_0_10, _butterfly_outputs_product_c_p_d_out_new_WIRE_20
wire butterfly_outputs_product_c_p_d_out_1_10 : SInt<19>
wire _butterfly_outputs_product_c_p_d_out_new_WIRE_21 : SInt<19>
node _butterfly_outputs_product_c_p_d_out_new_T_42 = asUInt(twiddle[5].imag)
node _butterfly_outputs_product_c_p_d_out_new_T_43 = asSInt(_butterfly_outputs_product_c_p_d_out_new_T_42)
connect _butterfly_outputs_product_c_p_d_out_new_WIRE_21, _butterfly_outputs_product_c_p_d_out_new_T_43
connect butterfly_outputs_product_c_p_d_out_1_10, _butterfly_outputs_product_c_p_d_out_new_WIRE_21
wire _butterfly_outputs_product_c_p_d_this_10 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_20 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_30 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_60 = asUInt(butterfly_outputs_product_c_p_d_out_0_10)
node _butterfly_outputs_product_c_p_d_new_T_61 = asSInt(_butterfly_outputs_product_c_p_d_new_T_60)
connect _butterfly_outputs_product_c_p_d_new_WIRE_30, _butterfly_outputs_product_c_p_d_new_T_61
connect _butterfly_outputs_product_c_p_d_new_20, _butterfly_outputs_product_c_p_d_new_WIRE_30
connect _butterfly_outputs_product_c_p_d_this_10, _butterfly_outputs_product_c_p_d_new_20
wire _butterfly_outputs_product_c_p_d_that_10 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_21 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_31 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_62 = asUInt(butterfly_outputs_product_c_p_d_out_1_10)
node _butterfly_outputs_product_c_p_d_new_T_63 = asSInt(_butterfly_outputs_product_c_p_d_new_T_62)
connect _butterfly_outputs_product_c_p_d_new_WIRE_31, _butterfly_outputs_product_c_p_d_new_T_63
connect _butterfly_outputs_product_c_p_d_new_21, _butterfly_outputs_product_c_p_d_new_WIRE_31
connect _butterfly_outputs_product_c_p_d_that_10, _butterfly_outputs_product_c_p_d_new_21
node _butterfly_outputs_product_c_p_d_T_30 = add(_butterfly_outputs_product_c_p_d_this_10, _butterfly_outputs_product_c_p_d_that_10)
node _butterfly_outputs_product_c_p_d_T_31 = tail(_butterfly_outputs_product_c_p_d_T_30, 1)
node _butterfly_outputs_product_c_p_d_T_32 = asSInt(_butterfly_outputs_product_c_p_d_T_31)
wire butterfly_outputs_product_c_p_d_10 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_32 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_64 = asUInt(_butterfly_outputs_product_c_p_d_T_32)
node _butterfly_outputs_product_c_p_d_new_T_65 = asSInt(_butterfly_outputs_product_c_p_d_new_T_64)
connect _butterfly_outputs_product_c_p_d_new_WIRE_32, _butterfly_outputs_product_c_p_d_new_T_65
connect butterfly_outputs_product_c_p_d_10, _butterfly_outputs_product_c_p_d_new_WIRE_32
wire butterfly_outputs_product_a_p_b_out_0_10 : SInt<16>
wire _butterfly_outputs_product_a_p_b_out_new_WIRE_20 : SInt<16>
node _butterfly_outputs_product_a_p_b_out_new_T_40 = asUInt(stage_outputs_2_5.real)
node _butterfly_outputs_product_a_p_b_out_new_T_41 = asSInt(_butterfly_outputs_product_a_p_b_out_new_T_40)
connect _butterfly_outputs_product_a_p_b_out_new_WIRE_20, _butterfly_outputs_product_a_p_b_out_new_T_41
connect butterfly_outputs_product_a_p_b_out_0_10, _butterfly_outputs_product_a_p_b_out_new_WIRE_20
wire butterfly_outputs_product_a_p_b_out_1_10 : SInt<16>
wire _butterfly_outputs_product_a_p_b_out_new_WIRE_21 : SInt<16>
node _butterfly_outputs_product_a_p_b_out_new_T_42 = asUInt(stage_outputs_2_5.imag)
node _butterfly_outputs_product_a_p_b_out_new_T_43 = asSInt(_butterfly_outputs_product_a_p_b_out_new_T_42)
connect _butterfly_outputs_product_a_p_b_out_new_WIRE_21, _butterfly_outputs_product_a_p_b_out_new_T_43
connect butterfly_outputs_product_a_p_b_out_1_10, _butterfly_outputs_product_a_p_b_out_new_WIRE_21
wire _butterfly_outputs_product_a_p_b_this_10 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_20 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_30 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_60 = asUInt(butterfly_outputs_product_a_p_b_out_0_10)
node _butterfly_outputs_product_a_p_b_new_T_61 = asSInt(_butterfly_outputs_product_a_p_b_new_T_60)
connect _butterfly_outputs_product_a_p_b_new_WIRE_30, _butterfly_outputs_product_a_p_b_new_T_61
connect _butterfly_outputs_product_a_p_b_new_20, _butterfly_outputs_product_a_p_b_new_WIRE_30
connect _butterfly_outputs_product_a_p_b_this_10, _butterfly_outputs_product_a_p_b_new_20
wire _butterfly_outputs_product_a_p_b_that_10 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_21 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_31 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_62 = asUInt(butterfly_outputs_product_a_p_b_out_1_10)
node _butterfly_outputs_product_a_p_b_new_T_63 = asSInt(_butterfly_outputs_product_a_p_b_new_T_62)
connect _butterfly_outputs_product_a_p_b_new_WIRE_31, _butterfly_outputs_product_a_p_b_new_T_63
connect _butterfly_outputs_product_a_p_b_new_21, _butterfly_outputs_product_a_p_b_new_WIRE_31
connect _butterfly_outputs_product_a_p_b_that_10, _butterfly_outputs_product_a_p_b_new_21
node _butterfly_outputs_product_a_p_b_T_30 = add(_butterfly_outputs_product_a_p_b_this_10, _butterfly_outputs_product_a_p_b_that_10)
node _butterfly_outputs_product_a_p_b_T_31 = tail(_butterfly_outputs_product_a_p_b_T_30, 1)
node _butterfly_outputs_product_a_p_b_T_32 = asSInt(_butterfly_outputs_product_a_p_b_T_31)
wire butterfly_outputs_product_a_p_b_10 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_32 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_64 = asUInt(_butterfly_outputs_product_a_p_b_T_32)
node _butterfly_outputs_product_a_p_b_new_T_65 = asSInt(_butterfly_outputs_product_a_p_b_new_T_64)
connect _butterfly_outputs_product_a_p_b_new_WIRE_32, _butterfly_outputs_product_a_p_b_new_T_65
connect butterfly_outputs_product_a_p_b_10, _butterfly_outputs_product_a_p_b_new_WIRE_32
wire butterfly_outputs_product_b_m_a_out_0_10 : SInt<16>
wire _butterfly_outputs_product_b_m_a_out_new_WIRE_20 : SInt<16>
node _butterfly_outputs_product_b_m_a_out_new_T_40 = asUInt(stage_outputs_2_5.imag)
node _butterfly_outputs_product_b_m_a_out_new_T_41 = asSInt(_butterfly_outputs_product_b_m_a_out_new_T_40)
connect _butterfly_outputs_product_b_m_a_out_new_WIRE_20, _butterfly_outputs_product_b_m_a_out_new_T_41
connect butterfly_outputs_product_b_m_a_out_0_10, _butterfly_outputs_product_b_m_a_out_new_WIRE_20
wire butterfly_outputs_product_b_m_a_out_1_10 : SInt<16>
wire _butterfly_outputs_product_b_m_a_out_new_WIRE_21 : SInt<16>
node _butterfly_outputs_product_b_m_a_out_new_T_42 = asUInt(stage_outputs_2_5.real)
node _butterfly_outputs_product_b_m_a_out_new_T_43 = asSInt(_butterfly_outputs_product_b_m_a_out_new_T_42)
connect _butterfly_outputs_product_b_m_a_out_new_WIRE_21, _butterfly_outputs_product_b_m_a_out_new_T_43
connect butterfly_outputs_product_b_m_a_out_1_10, _butterfly_outputs_product_b_m_a_out_new_WIRE_21
wire _butterfly_outputs_product_b_m_a_this_10 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_20 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_30 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_60 = asUInt(butterfly_outputs_product_b_m_a_out_0_10)
node _butterfly_outputs_product_b_m_a_new_T_61 = asSInt(_butterfly_outputs_product_b_m_a_new_T_60)
connect _butterfly_outputs_product_b_m_a_new_WIRE_30, _butterfly_outputs_product_b_m_a_new_T_61
connect _butterfly_outputs_product_b_m_a_new_20, _butterfly_outputs_product_b_m_a_new_WIRE_30
connect _butterfly_outputs_product_b_m_a_this_10, _butterfly_outputs_product_b_m_a_new_20
wire _butterfly_outputs_product_b_m_a_that_10 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_21 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_31 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_62 = asUInt(butterfly_outputs_product_b_m_a_out_1_10)
node _butterfly_outputs_product_b_m_a_new_T_63 = asSInt(_butterfly_outputs_product_b_m_a_new_T_62)
connect _butterfly_outputs_product_b_m_a_new_WIRE_31, _butterfly_outputs_product_b_m_a_new_T_63
connect _butterfly_outputs_product_b_m_a_new_21, _butterfly_outputs_product_b_m_a_new_WIRE_31
connect _butterfly_outputs_product_b_m_a_that_10, _butterfly_outputs_product_b_m_a_new_21
node _butterfly_outputs_product_b_m_a_T_30 = sub(_butterfly_outputs_product_b_m_a_this_10, _butterfly_outputs_product_b_m_a_that_10)
node _butterfly_outputs_product_b_m_a_T_31 = tail(_butterfly_outputs_product_b_m_a_T_30, 1)
node _butterfly_outputs_product_b_m_a_T_32 = asSInt(_butterfly_outputs_product_b_m_a_T_31)
wire butterfly_outputs_product_b_m_a_10 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_32 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_64 = asUInt(_butterfly_outputs_product_b_m_a_T_32)
node _butterfly_outputs_product_b_m_a_new_T_65 = asSInt(_butterfly_outputs_product_b_m_a_new_T_64)
connect _butterfly_outputs_product_b_m_a_new_WIRE_32, _butterfly_outputs_product_b_m_a_new_T_65
connect butterfly_outputs_product_b_m_a_10, _butterfly_outputs_product_b_m_a_new_WIRE_32
node _butterfly_outputs_product_ac_p_ad_T_10 = mul(stage_outputs_2_5.real, butterfly_outputs_product_c_p_d_10)
wire butterfly_outputs_product_ac_p_ad_10 : SInt<35>
wire _butterfly_outputs_product_ac_p_ad_new_WIRE_10 : SInt<35>
node _butterfly_outputs_product_ac_p_ad_new_T_20 = asUInt(_butterfly_outputs_product_ac_p_ad_T_10)
node _butterfly_outputs_product_ac_p_ad_new_T_21 = asSInt(_butterfly_outputs_product_ac_p_ad_new_T_20)
connect _butterfly_outputs_product_ac_p_ad_new_WIRE_10, _butterfly_outputs_product_ac_p_ad_new_T_21
connect butterfly_outputs_product_ac_p_ad_10, _butterfly_outputs_product_ac_p_ad_new_WIRE_10
node _butterfly_outputs_product_ad_p_bd_T_10 = mul(butterfly_outputs_product_a_p_b_10, twiddle[5].imag)
wire butterfly_outputs_product_ad_p_bd_10 : SInt<35>
wire _butterfly_outputs_product_ad_p_bd_new_WIRE_10 : SInt<35>
node _butterfly_outputs_product_ad_p_bd_new_T_20 = asUInt(_butterfly_outputs_product_ad_p_bd_T_10)
node _butterfly_outputs_product_ad_p_bd_new_T_21 = asSInt(_butterfly_outputs_product_ad_p_bd_new_T_20)
connect _butterfly_outputs_product_ad_p_bd_new_WIRE_10, _butterfly_outputs_product_ad_p_bd_new_T_21
connect butterfly_outputs_product_ad_p_bd_10, _butterfly_outputs_product_ad_p_bd_new_WIRE_10
node _butterfly_outputs_product_bc_m_ac_T_10 = mul(butterfly_outputs_product_b_m_a_10, twiddle[5].real)
wire butterfly_outputs_product_bc_m_ac_10 : SInt<35>
wire _butterfly_outputs_product_bc_m_ac_new_WIRE_10 : SInt<35>
node _butterfly_outputs_product_bc_m_ac_new_T_20 = asUInt(_butterfly_outputs_product_bc_m_ac_T_10)
node _butterfly_outputs_product_bc_m_ac_new_T_21 = asSInt(_butterfly_outputs_product_bc_m_ac_new_T_20)
connect _butterfly_outputs_product_bc_m_ac_new_WIRE_10, _butterfly_outputs_product_bc_m_ac_new_T_21
connect butterfly_outputs_product_bc_m_ac_10, _butterfly_outputs_product_bc_m_ac_new_WIRE_10
wire butterfly_outputs_product_out_0_20 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_40 : SInt<35>
node _butterfly_outputs_product_out_new_T_80 = asUInt(butterfly_outputs_product_ac_p_ad_10)
node _butterfly_outputs_product_out_new_T_81 = asSInt(_butterfly_outputs_product_out_new_T_80)
connect _butterfly_outputs_product_out_new_WIRE_40, _butterfly_outputs_product_out_new_T_81
connect butterfly_outputs_product_out_0_20, _butterfly_outputs_product_out_new_WIRE_40
wire butterfly_outputs_product_out_1_20 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_41 : SInt<35>
node _butterfly_outputs_product_out_new_T_82 = asUInt(butterfly_outputs_product_ad_p_bd_10)
node _butterfly_outputs_product_out_new_T_83 = asSInt(_butterfly_outputs_product_out_new_T_82)
connect _butterfly_outputs_product_out_new_WIRE_41, _butterfly_outputs_product_out_new_T_83
connect butterfly_outputs_product_out_1_20, _butterfly_outputs_product_out_new_WIRE_41
wire _butterfly_outputs_product_this_20 : SInt<35>
wire _butterfly_outputs_product_new_60 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_60 : SInt<35>
node _butterfly_outputs_product_new_T_120 = asUInt(butterfly_outputs_product_out_0_20)
node _butterfly_outputs_product_new_T_121 = asSInt(_butterfly_outputs_product_new_T_120)
connect _butterfly_outputs_product_new_WIRE_60, _butterfly_outputs_product_new_T_121
connect _butterfly_outputs_product_new_60, _butterfly_outputs_product_new_WIRE_60
connect _butterfly_outputs_product_this_20, _butterfly_outputs_product_new_60
wire _butterfly_outputs_product_that_20 : SInt<35>
wire _butterfly_outputs_product_new_61 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_61 : SInt<35>
node _butterfly_outputs_product_new_T_122 = asUInt(butterfly_outputs_product_out_1_20)
node _butterfly_outputs_product_new_T_123 = asSInt(_butterfly_outputs_product_new_T_122)
connect _butterfly_outputs_product_new_WIRE_61, _butterfly_outputs_product_new_T_123
connect _butterfly_outputs_product_new_61, _butterfly_outputs_product_new_WIRE_61
connect _butterfly_outputs_product_that_20, _butterfly_outputs_product_new_61
node _butterfly_outputs_product_T_60 = sub(_butterfly_outputs_product_this_20, _butterfly_outputs_product_that_20)
node _butterfly_outputs_product_T_61 = tail(_butterfly_outputs_product_T_60, 1)
node _butterfly_outputs_product_T_62 = asSInt(_butterfly_outputs_product_T_61)
wire _butterfly_outputs_product_new_62 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_62 : SInt<35>
node _butterfly_outputs_product_new_T_124 = asUInt(_butterfly_outputs_product_T_62)
node _butterfly_outputs_product_new_T_125 = asSInt(_butterfly_outputs_product_new_T_124)
connect _butterfly_outputs_product_new_WIRE_62, _butterfly_outputs_product_new_T_125
connect _butterfly_outputs_product_new_62, _butterfly_outputs_product_new_WIRE_62
wire butterfly_outputs_product_out_0_21 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_42 : SInt<35>
node _butterfly_outputs_product_out_new_T_84 = asUInt(butterfly_outputs_product_ac_p_ad_10)
node _butterfly_outputs_product_out_new_T_85 = asSInt(_butterfly_outputs_product_out_new_T_84)
connect _butterfly_outputs_product_out_new_WIRE_42, _butterfly_outputs_product_out_new_T_85
connect butterfly_outputs_product_out_0_21, _butterfly_outputs_product_out_new_WIRE_42
wire butterfly_outputs_product_out_1_21 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_43 : SInt<35>
node _butterfly_outputs_product_out_new_T_86 = asUInt(butterfly_outputs_product_bc_m_ac_10)
node _butterfly_outputs_product_out_new_T_87 = asSInt(_butterfly_outputs_product_out_new_T_86)
connect _butterfly_outputs_product_out_new_WIRE_43, _butterfly_outputs_product_out_new_T_87
connect butterfly_outputs_product_out_1_21, _butterfly_outputs_product_out_new_WIRE_43
wire _butterfly_outputs_product_this_21 : SInt<35>
wire _butterfly_outputs_product_new_63 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_63 : SInt<35>
node _butterfly_outputs_product_new_T_126 = asUInt(butterfly_outputs_product_out_0_21)
node _butterfly_outputs_product_new_T_127 = asSInt(_butterfly_outputs_product_new_T_126)
connect _butterfly_outputs_product_new_WIRE_63, _butterfly_outputs_product_new_T_127
connect _butterfly_outputs_product_new_63, _butterfly_outputs_product_new_WIRE_63
connect _butterfly_outputs_product_this_21, _butterfly_outputs_product_new_63
wire _butterfly_outputs_product_that_21 : SInt<35>
wire _butterfly_outputs_product_new_64 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_64 : SInt<35>
node _butterfly_outputs_product_new_T_128 = asUInt(butterfly_outputs_product_out_1_21)
node _butterfly_outputs_product_new_T_129 = asSInt(_butterfly_outputs_product_new_T_128)
connect _butterfly_outputs_product_new_WIRE_64, _butterfly_outputs_product_new_T_129
connect _butterfly_outputs_product_new_64, _butterfly_outputs_product_new_WIRE_64
connect _butterfly_outputs_product_that_21, _butterfly_outputs_product_new_64
node _butterfly_outputs_product_T_63 = add(_butterfly_outputs_product_this_21, _butterfly_outputs_product_that_21)
node _butterfly_outputs_product_T_64 = tail(_butterfly_outputs_product_T_63, 1)
node _butterfly_outputs_product_T_65 = asSInt(_butterfly_outputs_product_T_64)
wire _butterfly_outputs_product_new_65 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_65 : SInt<35>
node _butterfly_outputs_product_new_T_130 = asUInt(_butterfly_outputs_product_T_65)
node _butterfly_outputs_product_new_T_131 = asSInt(_butterfly_outputs_product_new_T_130)
connect _butterfly_outputs_product_new_WIRE_65, _butterfly_outputs_product_new_T_131
connect _butterfly_outputs_product_new_65, _butterfly_outputs_product_new_WIRE_65
wire butterfly_outputs_product_10 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_product_result_real_new_10 : SInt<35>
wire _butterfly_outputs_product_result_real_new_WIRE_10 : SInt<35>
node _butterfly_outputs_product_result_real_new_T_20 = asUInt(_butterfly_outputs_product_new_62)
node _butterfly_outputs_product_result_real_new_T_21 = asSInt(_butterfly_outputs_product_result_real_new_T_20)
connect _butterfly_outputs_product_result_real_new_WIRE_10, _butterfly_outputs_product_result_real_new_T_21
connect _butterfly_outputs_product_result_real_new_10, _butterfly_outputs_product_result_real_new_WIRE_10
connect butterfly_outputs_product_10.real, _butterfly_outputs_product_result_real_new_10
wire _butterfly_outputs_product_result_imag_new_10 : SInt<35>
wire _butterfly_outputs_product_result_imag_new_WIRE_10 : SInt<35>
node _butterfly_outputs_product_result_imag_new_T_20 = asUInt(_butterfly_outputs_product_new_65)
node _butterfly_outputs_product_result_imag_new_T_21 = asSInt(_butterfly_outputs_product_result_imag_new_T_20)
connect _butterfly_outputs_product_result_imag_new_WIRE_10, _butterfly_outputs_product_result_imag_new_T_21
connect _butterfly_outputs_product_result_imag_new_10, _butterfly_outputs_product_result_imag_new_WIRE_10
connect butterfly_outputs_product_10.imag, _butterfly_outputs_product_result_imag_new_10
node _butterfly_outputs_out_T_40 = shl(stage_outputs_2_4.real, 17)
wire butterfly_outputs_out_0_40 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_80 : SInt<35>
node _butterfly_outputs_out_new_T_160 = asUInt(_butterfly_outputs_out_T_40)
node _butterfly_outputs_out_new_T_161 = asSInt(_butterfly_outputs_out_new_T_160)
connect _butterfly_outputs_out_new_WIRE_80, _butterfly_outputs_out_new_T_161
connect butterfly_outputs_out_0_40, _butterfly_outputs_out_new_WIRE_80
wire butterfly_outputs_out_1_40 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_81 : SInt<35>
node _butterfly_outputs_out_new_T_162 = asUInt(butterfly_outputs_product_10.real)
node _butterfly_outputs_out_new_T_163 = asSInt(_butterfly_outputs_out_new_T_162)
connect _butterfly_outputs_out_new_WIRE_81, _butterfly_outputs_out_new_T_163
connect butterfly_outputs_out_1_40, _butterfly_outputs_out_new_WIRE_81
wire _butterfly_outputs_this_40 : SInt<35>
wire _butterfly_outputs_new_120 : SInt<35>
wire _butterfly_outputs_new_WIRE_120 : SInt<35>
node _butterfly_outputs_new_T_240 = asUInt(butterfly_outputs_out_0_40)
node _butterfly_outputs_new_T_241 = asSInt(_butterfly_outputs_new_T_240)
connect _butterfly_outputs_new_WIRE_120, _butterfly_outputs_new_T_241
connect _butterfly_outputs_new_120, _butterfly_outputs_new_WIRE_120
connect _butterfly_outputs_this_40, _butterfly_outputs_new_120
wire _butterfly_outputs_that_40 : SInt<35>
wire _butterfly_outputs_new_121 : SInt<35>
wire _butterfly_outputs_new_WIRE_121 : SInt<35>
node _butterfly_outputs_new_T_242 = asUInt(butterfly_outputs_out_1_40)
node _butterfly_outputs_new_T_243 = asSInt(_butterfly_outputs_new_T_242)
connect _butterfly_outputs_new_WIRE_121, _butterfly_outputs_new_T_243
connect _butterfly_outputs_new_121, _butterfly_outputs_new_WIRE_121
connect _butterfly_outputs_that_40, _butterfly_outputs_new_121
node _butterfly_outputs_T_120 = add(_butterfly_outputs_this_40, _butterfly_outputs_that_40)
node _butterfly_outputs_T_121 = tail(_butterfly_outputs_T_120, 1)
node _butterfly_outputs_T_122 = asSInt(_butterfly_outputs_T_121)
wire _butterfly_outputs_new_122 : SInt<35>
wire _butterfly_outputs_new_WIRE_122 : SInt<35>
node _butterfly_outputs_new_T_244 = asUInt(_butterfly_outputs_T_122)
node _butterfly_outputs_new_T_245 = asSInt(_butterfly_outputs_new_T_244)
connect _butterfly_outputs_new_WIRE_122, _butterfly_outputs_new_T_245
connect _butterfly_outputs_new_122, _butterfly_outputs_new_WIRE_122
node _butterfly_outputs_out_T_41 = shl(stage_outputs_2_4.imag, 17)
wire butterfly_outputs_out_0_41 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_82 : SInt<35>
node _butterfly_outputs_out_new_T_164 = asUInt(_butterfly_outputs_out_T_41)
node _butterfly_outputs_out_new_T_165 = asSInt(_butterfly_outputs_out_new_T_164)
connect _butterfly_outputs_out_new_WIRE_82, _butterfly_outputs_out_new_T_165
connect butterfly_outputs_out_0_41, _butterfly_outputs_out_new_WIRE_82
wire butterfly_outputs_out_1_41 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_83 : SInt<35>
node _butterfly_outputs_out_new_T_166 = asUInt(butterfly_outputs_product_10.imag)
node _butterfly_outputs_out_new_T_167 = asSInt(_butterfly_outputs_out_new_T_166)
connect _butterfly_outputs_out_new_WIRE_83, _butterfly_outputs_out_new_T_167
connect butterfly_outputs_out_1_41, _butterfly_outputs_out_new_WIRE_83
wire _butterfly_outputs_this_41 : SInt<35>
wire _butterfly_outputs_new_123 : SInt<35>
wire _butterfly_outputs_new_WIRE_123 : SInt<35>
node _butterfly_outputs_new_T_246 = asUInt(butterfly_outputs_out_0_41)
node _butterfly_outputs_new_T_247 = asSInt(_butterfly_outputs_new_T_246)
connect _butterfly_outputs_new_WIRE_123, _butterfly_outputs_new_T_247
connect _butterfly_outputs_new_123, _butterfly_outputs_new_WIRE_123
connect _butterfly_outputs_this_41, _butterfly_outputs_new_123
wire _butterfly_outputs_that_41 : SInt<35>
wire _butterfly_outputs_new_124 : SInt<35>
wire _butterfly_outputs_new_WIRE_124 : SInt<35>
node _butterfly_outputs_new_T_248 = asUInt(butterfly_outputs_out_1_41)
node _butterfly_outputs_new_T_249 = asSInt(_butterfly_outputs_new_T_248)
connect _butterfly_outputs_new_WIRE_124, _butterfly_outputs_new_T_249
connect _butterfly_outputs_new_124, _butterfly_outputs_new_WIRE_124
connect _butterfly_outputs_that_41, _butterfly_outputs_new_124
node _butterfly_outputs_T_123 = add(_butterfly_outputs_this_41, _butterfly_outputs_that_41)
node _butterfly_outputs_T_124 = tail(_butterfly_outputs_T_123, 1)
node _butterfly_outputs_T_125 = asSInt(_butterfly_outputs_T_124)
wire _butterfly_outputs_new_125 : SInt<35>
wire _butterfly_outputs_new_WIRE_125 : SInt<35>
node _butterfly_outputs_new_T_250 = asUInt(_butterfly_outputs_T_125)
node _butterfly_outputs_new_T_251 = asSInt(_butterfly_outputs_new_T_250)
connect _butterfly_outputs_new_WIRE_125, _butterfly_outputs_new_T_251
connect _butterfly_outputs_new_125, _butterfly_outputs_new_WIRE_125
wire butterfly_outputs_0_10 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_result_real_new_20 : SInt<35>
wire _butterfly_outputs_result_real_new_WIRE_20 : SInt<35>
node _butterfly_outputs_result_real_new_T_40 = asUInt(_butterfly_outputs_new_122)
node _butterfly_outputs_result_real_new_T_41 = asSInt(_butterfly_outputs_result_real_new_T_40)
connect _butterfly_outputs_result_real_new_WIRE_20, _butterfly_outputs_result_real_new_T_41
connect _butterfly_outputs_result_real_new_20, _butterfly_outputs_result_real_new_WIRE_20
connect butterfly_outputs_0_10.real, _butterfly_outputs_result_real_new_20
wire _butterfly_outputs_result_imag_new_20 : SInt<35>
wire _butterfly_outputs_result_imag_new_WIRE_20 : SInt<35>
node _butterfly_outputs_result_imag_new_T_40 = asUInt(_butterfly_outputs_new_125)
node _butterfly_outputs_result_imag_new_T_41 = asSInt(_butterfly_outputs_result_imag_new_T_40)
connect _butterfly_outputs_result_imag_new_WIRE_20, _butterfly_outputs_result_imag_new_T_41
connect _butterfly_outputs_result_imag_new_20, _butterfly_outputs_result_imag_new_WIRE_20
connect butterfly_outputs_0_10.imag, _butterfly_outputs_result_imag_new_20
node _butterfly_outputs_out_T_42 = shl(stage_outputs_2_4.real, 17)
wire butterfly_outputs_out_0_42 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_84 : SInt<35>
node _butterfly_outputs_out_new_T_168 = asUInt(_butterfly_outputs_out_T_42)
node _butterfly_outputs_out_new_T_169 = asSInt(_butterfly_outputs_out_new_T_168)
connect _butterfly_outputs_out_new_WIRE_84, _butterfly_outputs_out_new_T_169
connect butterfly_outputs_out_0_42, _butterfly_outputs_out_new_WIRE_84
wire butterfly_outputs_out_1_42 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_85 : SInt<35>
node _butterfly_outputs_out_new_T_170 = asUInt(butterfly_outputs_product_10.real)
node _butterfly_outputs_out_new_T_171 = asSInt(_butterfly_outputs_out_new_T_170)
connect _butterfly_outputs_out_new_WIRE_85, _butterfly_outputs_out_new_T_171
connect butterfly_outputs_out_1_42, _butterfly_outputs_out_new_WIRE_85
wire _butterfly_outputs_this_42 : SInt<35>
wire _butterfly_outputs_new_126 : SInt<35>
wire _butterfly_outputs_new_WIRE_126 : SInt<35>
node _butterfly_outputs_new_T_252 = asUInt(butterfly_outputs_out_0_42)
node _butterfly_outputs_new_T_253 = asSInt(_butterfly_outputs_new_T_252)
connect _butterfly_outputs_new_WIRE_126, _butterfly_outputs_new_T_253
connect _butterfly_outputs_new_126, _butterfly_outputs_new_WIRE_126
connect _butterfly_outputs_this_42, _butterfly_outputs_new_126
wire _butterfly_outputs_that_42 : SInt<35>
wire _butterfly_outputs_new_127 : SInt<35>
wire _butterfly_outputs_new_WIRE_127 : SInt<35>
node _butterfly_outputs_new_T_254 = asUInt(butterfly_outputs_out_1_42)
node _butterfly_outputs_new_T_255 = asSInt(_butterfly_outputs_new_T_254)
connect _butterfly_outputs_new_WIRE_127, _butterfly_outputs_new_T_255
connect _butterfly_outputs_new_127, _butterfly_outputs_new_WIRE_127
connect _butterfly_outputs_that_42, _butterfly_outputs_new_127
node _butterfly_outputs_T_126 = sub(_butterfly_outputs_this_42, _butterfly_outputs_that_42)
node _butterfly_outputs_T_127 = tail(_butterfly_outputs_T_126, 1)
node _butterfly_outputs_T_128 = asSInt(_butterfly_outputs_T_127)
wire _butterfly_outputs_new_128 : SInt<35>
wire _butterfly_outputs_new_WIRE_128 : SInt<35>
node _butterfly_outputs_new_T_256 = asUInt(_butterfly_outputs_T_128)
node _butterfly_outputs_new_T_257 = asSInt(_butterfly_outputs_new_T_256)
connect _butterfly_outputs_new_WIRE_128, _butterfly_outputs_new_T_257
connect _butterfly_outputs_new_128, _butterfly_outputs_new_WIRE_128
node _butterfly_outputs_out_T_43 = shl(stage_outputs_2_4.imag, 17)
wire butterfly_outputs_out_0_43 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_86 : SInt<35>
node _butterfly_outputs_out_new_T_172 = asUInt(_butterfly_outputs_out_T_43)
node _butterfly_outputs_out_new_T_173 = asSInt(_butterfly_outputs_out_new_T_172)
connect _butterfly_outputs_out_new_WIRE_86, _butterfly_outputs_out_new_T_173
connect butterfly_outputs_out_0_43, _butterfly_outputs_out_new_WIRE_86
wire butterfly_outputs_out_1_43 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_87 : SInt<35>
node _butterfly_outputs_out_new_T_174 = asUInt(butterfly_outputs_product_10.imag)
node _butterfly_outputs_out_new_T_175 = asSInt(_butterfly_outputs_out_new_T_174)
connect _butterfly_outputs_out_new_WIRE_87, _butterfly_outputs_out_new_T_175
connect butterfly_outputs_out_1_43, _butterfly_outputs_out_new_WIRE_87
wire _butterfly_outputs_this_43 : SInt<35>
wire _butterfly_outputs_new_129 : SInt<35>
wire _butterfly_outputs_new_WIRE_129 : SInt<35>
node _butterfly_outputs_new_T_258 = asUInt(butterfly_outputs_out_0_43)
node _butterfly_outputs_new_T_259 = asSInt(_butterfly_outputs_new_T_258)
connect _butterfly_outputs_new_WIRE_129, _butterfly_outputs_new_T_259
connect _butterfly_outputs_new_129, _butterfly_outputs_new_WIRE_129
connect _butterfly_outputs_this_43, _butterfly_outputs_new_129
wire _butterfly_outputs_that_43 : SInt<35>
wire _butterfly_outputs_new_130 : SInt<35>
wire _butterfly_outputs_new_WIRE_130 : SInt<35>
node _butterfly_outputs_new_T_260 = asUInt(butterfly_outputs_out_1_43)
node _butterfly_outputs_new_T_261 = asSInt(_butterfly_outputs_new_T_260)
connect _butterfly_outputs_new_WIRE_130, _butterfly_outputs_new_T_261
connect _butterfly_outputs_new_130, _butterfly_outputs_new_WIRE_130
connect _butterfly_outputs_that_43, _butterfly_outputs_new_130
node _butterfly_outputs_T_129 = sub(_butterfly_outputs_this_43, _butterfly_outputs_that_43)
node _butterfly_outputs_T_130 = tail(_butterfly_outputs_T_129, 1)
node _butterfly_outputs_T_131 = asSInt(_butterfly_outputs_T_130)
wire _butterfly_outputs_new_131 : SInt<35>
wire _butterfly_outputs_new_WIRE_131 : SInt<35>
node _butterfly_outputs_new_T_262 = asUInt(_butterfly_outputs_T_131)
node _butterfly_outputs_new_T_263 = asSInt(_butterfly_outputs_new_T_262)
connect _butterfly_outputs_new_WIRE_131, _butterfly_outputs_new_T_263
connect _butterfly_outputs_new_131, _butterfly_outputs_new_WIRE_131
wire butterfly_outputs_1_10 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_result_real_new_21 : SInt<35>
wire _butterfly_outputs_result_real_new_WIRE_21 : SInt<35>
node _butterfly_outputs_result_real_new_T_42 = asUInt(_butterfly_outputs_new_128)
node _butterfly_outputs_result_real_new_T_43 = asSInt(_butterfly_outputs_result_real_new_T_42)
connect _butterfly_outputs_result_real_new_WIRE_21, _butterfly_outputs_result_real_new_T_43
connect _butterfly_outputs_result_real_new_21, _butterfly_outputs_result_real_new_WIRE_21
connect butterfly_outputs_1_10.real, _butterfly_outputs_result_real_new_21
wire _butterfly_outputs_result_imag_new_21 : SInt<35>
wire _butterfly_outputs_result_imag_new_WIRE_21 : SInt<35>
node _butterfly_outputs_result_imag_new_T_42 = asUInt(_butterfly_outputs_new_131)
node _butterfly_outputs_result_imag_new_T_43 = asSInt(_butterfly_outputs_result_imag_new_T_42)
connect _butterfly_outputs_result_imag_new_WIRE_21, _butterfly_outputs_result_imag_new_T_43
connect _butterfly_outputs_result_imag_new_21, _butterfly_outputs_result_imag_new_WIRE_21
connect butterfly_outputs_1_10.imag, _butterfly_outputs_result_imag_new_21
node _stage_outputs_3_4_stage_outputs_3_4_imag_T = shr(butterfly_outputs_0_10.imag, 17)
wire _stage_outputs_3_4_stage_outputs_3_4_imag_new : SInt<18>
wire _stage_outputs_3_4_stage_outputs_3_4_imag_new_WIRE : SInt<18>
node _stage_outputs_3_4_stage_outputs_3_4_imag_new_T = asUInt(_stage_outputs_3_4_stage_outputs_3_4_imag_T)
node _stage_outputs_3_4_stage_outputs_3_4_imag_new_T_1 = asSInt(_stage_outputs_3_4_stage_outputs_3_4_imag_new_T)
connect _stage_outputs_3_4_stage_outputs_3_4_imag_new_WIRE, _stage_outputs_3_4_stage_outputs_3_4_imag_new_T_1
connect _stage_outputs_3_4_stage_outputs_3_4_imag_new, _stage_outputs_3_4_stage_outputs_3_4_imag_new_WIRE
connect stage_outputs_3_4.imag, _stage_outputs_3_4_stage_outputs_3_4_imag_new
node _stage_outputs_3_4_stage_outputs_3_4_real_T = shr(butterfly_outputs_0_10.real, 17)
wire _stage_outputs_3_4_stage_outputs_3_4_real_new : SInt<18>
wire _stage_outputs_3_4_stage_outputs_3_4_real_new_WIRE : SInt<18>
node _stage_outputs_3_4_stage_outputs_3_4_real_new_T = asUInt(_stage_outputs_3_4_stage_outputs_3_4_real_T)
node _stage_outputs_3_4_stage_outputs_3_4_real_new_T_1 = asSInt(_stage_outputs_3_4_stage_outputs_3_4_real_new_T)
connect _stage_outputs_3_4_stage_outputs_3_4_real_new_WIRE, _stage_outputs_3_4_stage_outputs_3_4_real_new_T_1
connect _stage_outputs_3_4_stage_outputs_3_4_real_new, _stage_outputs_3_4_stage_outputs_3_4_real_new_WIRE
connect stage_outputs_3_4.real, _stage_outputs_3_4_stage_outputs_3_4_real_new
node _stage_outputs_3_5_stage_outputs_3_5_imag_T = shr(butterfly_outputs_1_10.imag, 17)
wire _stage_outputs_3_5_stage_outputs_3_5_imag_new : SInt<18>
wire _stage_outputs_3_5_stage_outputs_3_5_imag_new_WIRE : SInt<18>
node _stage_outputs_3_5_stage_outputs_3_5_imag_new_T = asUInt(_stage_outputs_3_5_stage_outputs_3_5_imag_T)
node _stage_outputs_3_5_stage_outputs_3_5_imag_new_T_1 = asSInt(_stage_outputs_3_5_stage_outputs_3_5_imag_new_T)
connect _stage_outputs_3_5_stage_outputs_3_5_imag_new_WIRE, _stage_outputs_3_5_stage_outputs_3_5_imag_new_T_1
connect _stage_outputs_3_5_stage_outputs_3_5_imag_new, _stage_outputs_3_5_stage_outputs_3_5_imag_new_WIRE
connect stage_outputs_3_5.imag, _stage_outputs_3_5_stage_outputs_3_5_imag_new
node _stage_outputs_3_5_stage_outputs_3_5_real_T = shr(butterfly_outputs_1_10.real, 17)
wire _stage_outputs_3_5_stage_outputs_3_5_real_new : SInt<18>
wire _stage_outputs_3_5_stage_outputs_3_5_real_new_WIRE : SInt<18>
node _stage_outputs_3_5_stage_outputs_3_5_real_new_T = asUInt(_stage_outputs_3_5_stage_outputs_3_5_real_T)
node _stage_outputs_3_5_stage_outputs_3_5_real_new_T_1 = asSInt(_stage_outputs_3_5_stage_outputs_3_5_real_new_T)
connect _stage_outputs_3_5_stage_outputs_3_5_real_new_WIRE, _stage_outputs_3_5_stage_outputs_3_5_real_new_T_1
connect _stage_outputs_3_5_stage_outputs_3_5_real_new, _stage_outputs_3_5_stage_outputs_3_5_real_new_WIRE
connect stage_outputs_3_5.real, _stage_outputs_3_5_stage_outputs_3_5_real_new
wire butterfly_outputs_product_c_p_d_out_0_11 : SInt<19>
wire _butterfly_outputs_product_c_p_d_out_new_WIRE_22 : SInt<19>
node _butterfly_outputs_product_c_p_d_out_new_T_44 = asUInt(twiddle[6].real)
node _butterfly_outputs_product_c_p_d_out_new_T_45 = asSInt(_butterfly_outputs_product_c_p_d_out_new_T_44)
connect _butterfly_outputs_product_c_p_d_out_new_WIRE_22, _butterfly_outputs_product_c_p_d_out_new_T_45
connect butterfly_outputs_product_c_p_d_out_0_11, _butterfly_outputs_product_c_p_d_out_new_WIRE_22
wire butterfly_outputs_product_c_p_d_out_1_11 : SInt<19>
wire _butterfly_outputs_product_c_p_d_out_new_WIRE_23 : SInt<19>
node _butterfly_outputs_product_c_p_d_out_new_T_46 = asUInt(twiddle[6].imag)
node _butterfly_outputs_product_c_p_d_out_new_T_47 = asSInt(_butterfly_outputs_product_c_p_d_out_new_T_46)
connect _butterfly_outputs_product_c_p_d_out_new_WIRE_23, _butterfly_outputs_product_c_p_d_out_new_T_47
connect butterfly_outputs_product_c_p_d_out_1_11, _butterfly_outputs_product_c_p_d_out_new_WIRE_23
wire _butterfly_outputs_product_c_p_d_this_11 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_22 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_33 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_66 = asUInt(butterfly_outputs_product_c_p_d_out_0_11)
node _butterfly_outputs_product_c_p_d_new_T_67 = asSInt(_butterfly_outputs_product_c_p_d_new_T_66)
connect _butterfly_outputs_product_c_p_d_new_WIRE_33, _butterfly_outputs_product_c_p_d_new_T_67
connect _butterfly_outputs_product_c_p_d_new_22, _butterfly_outputs_product_c_p_d_new_WIRE_33
connect _butterfly_outputs_product_c_p_d_this_11, _butterfly_outputs_product_c_p_d_new_22
wire _butterfly_outputs_product_c_p_d_that_11 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_23 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_34 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_68 = asUInt(butterfly_outputs_product_c_p_d_out_1_11)
node _butterfly_outputs_product_c_p_d_new_T_69 = asSInt(_butterfly_outputs_product_c_p_d_new_T_68)
connect _butterfly_outputs_product_c_p_d_new_WIRE_34, _butterfly_outputs_product_c_p_d_new_T_69
connect _butterfly_outputs_product_c_p_d_new_23, _butterfly_outputs_product_c_p_d_new_WIRE_34
connect _butterfly_outputs_product_c_p_d_that_11, _butterfly_outputs_product_c_p_d_new_23
node _butterfly_outputs_product_c_p_d_T_33 = add(_butterfly_outputs_product_c_p_d_this_11, _butterfly_outputs_product_c_p_d_that_11)
node _butterfly_outputs_product_c_p_d_T_34 = tail(_butterfly_outputs_product_c_p_d_T_33, 1)
node _butterfly_outputs_product_c_p_d_T_35 = asSInt(_butterfly_outputs_product_c_p_d_T_34)
wire butterfly_outputs_product_c_p_d_11 : SInt<19>
wire _butterfly_outputs_product_c_p_d_new_WIRE_35 : SInt<19>
node _butterfly_outputs_product_c_p_d_new_T_70 = asUInt(_butterfly_outputs_product_c_p_d_T_35)
node _butterfly_outputs_product_c_p_d_new_T_71 = asSInt(_butterfly_outputs_product_c_p_d_new_T_70)
connect _butterfly_outputs_product_c_p_d_new_WIRE_35, _butterfly_outputs_product_c_p_d_new_T_71
connect butterfly_outputs_product_c_p_d_11, _butterfly_outputs_product_c_p_d_new_WIRE_35
wire butterfly_outputs_product_a_p_b_out_0_11 : SInt<16>
wire _butterfly_outputs_product_a_p_b_out_new_WIRE_22 : SInt<16>
node _butterfly_outputs_product_a_p_b_out_new_T_44 = asUInt(stage_outputs_2_7.real)
node _butterfly_outputs_product_a_p_b_out_new_T_45 = asSInt(_butterfly_outputs_product_a_p_b_out_new_T_44)
connect _butterfly_outputs_product_a_p_b_out_new_WIRE_22, _butterfly_outputs_product_a_p_b_out_new_T_45
connect butterfly_outputs_product_a_p_b_out_0_11, _butterfly_outputs_product_a_p_b_out_new_WIRE_22
wire butterfly_outputs_product_a_p_b_out_1_11 : SInt<16>
wire _butterfly_outputs_product_a_p_b_out_new_WIRE_23 : SInt<16>
node _butterfly_outputs_product_a_p_b_out_new_T_46 = asUInt(stage_outputs_2_7.imag)
node _butterfly_outputs_product_a_p_b_out_new_T_47 = asSInt(_butterfly_outputs_product_a_p_b_out_new_T_46)
connect _butterfly_outputs_product_a_p_b_out_new_WIRE_23, _butterfly_outputs_product_a_p_b_out_new_T_47
connect butterfly_outputs_product_a_p_b_out_1_11, _butterfly_outputs_product_a_p_b_out_new_WIRE_23
wire _butterfly_outputs_product_a_p_b_this_11 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_22 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_33 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_66 = asUInt(butterfly_outputs_product_a_p_b_out_0_11)
node _butterfly_outputs_product_a_p_b_new_T_67 = asSInt(_butterfly_outputs_product_a_p_b_new_T_66)
connect _butterfly_outputs_product_a_p_b_new_WIRE_33, _butterfly_outputs_product_a_p_b_new_T_67
connect _butterfly_outputs_product_a_p_b_new_22, _butterfly_outputs_product_a_p_b_new_WIRE_33
connect _butterfly_outputs_product_a_p_b_this_11, _butterfly_outputs_product_a_p_b_new_22
wire _butterfly_outputs_product_a_p_b_that_11 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_23 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_34 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_68 = asUInt(butterfly_outputs_product_a_p_b_out_1_11)
node _butterfly_outputs_product_a_p_b_new_T_69 = asSInt(_butterfly_outputs_product_a_p_b_new_T_68)
connect _butterfly_outputs_product_a_p_b_new_WIRE_34, _butterfly_outputs_product_a_p_b_new_T_69
connect _butterfly_outputs_product_a_p_b_new_23, _butterfly_outputs_product_a_p_b_new_WIRE_34
connect _butterfly_outputs_product_a_p_b_that_11, _butterfly_outputs_product_a_p_b_new_23
node _butterfly_outputs_product_a_p_b_T_33 = add(_butterfly_outputs_product_a_p_b_this_11, _butterfly_outputs_product_a_p_b_that_11)
node _butterfly_outputs_product_a_p_b_T_34 = tail(_butterfly_outputs_product_a_p_b_T_33, 1)
node _butterfly_outputs_product_a_p_b_T_35 = asSInt(_butterfly_outputs_product_a_p_b_T_34)
wire butterfly_outputs_product_a_p_b_11 : SInt<16>
wire _butterfly_outputs_product_a_p_b_new_WIRE_35 : SInt<16>
node _butterfly_outputs_product_a_p_b_new_T_70 = asUInt(_butterfly_outputs_product_a_p_b_T_35)
node _butterfly_outputs_product_a_p_b_new_T_71 = asSInt(_butterfly_outputs_product_a_p_b_new_T_70)
connect _butterfly_outputs_product_a_p_b_new_WIRE_35, _butterfly_outputs_product_a_p_b_new_T_71
connect butterfly_outputs_product_a_p_b_11, _butterfly_outputs_product_a_p_b_new_WIRE_35
wire butterfly_outputs_product_b_m_a_out_0_11 : SInt<16>
wire _butterfly_outputs_product_b_m_a_out_new_WIRE_22 : SInt<16>
node _butterfly_outputs_product_b_m_a_out_new_T_44 = asUInt(stage_outputs_2_7.imag)
node _butterfly_outputs_product_b_m_a_out_new_T_45 = asSInt(_butterfly_outputs_product_b_m_a_out_new_T_44)
connect _butterfly_outputs_product_b_m_a_out_new_WIRE_22, _butterfly_outputs_product_b_m_a_out_new_T_45
connect butterfly_outputs_product_b_m_a_out_0_11, _butterfly_outputs_product_b_m_a_out_new_WIRE_22
wire butterfly_outputs_product_b_m_a_out_1_11 : SInt<16>
wire _butterfly_outputs_product_b_m_a_out_new_WIRE_23 : SInt<16>
node _butterfly_outputs_product_b_m_a_out_new_T_46 = asUInt(stage_outputs_2_7.real)
node _butterfly_outputs_product_b_m_a_out_new_T_47 = asSInt(_butterfly_outputs_product_b_m_a_out_new_T_46)
connect _butterfly_outputs_product_b_m_a_out_new_WIRE_23, _butterfly_outputs_product_b_m_a_out_new_T_47
connect butterfly_outputs_product_b_m_a_out_1_11, _butterfly_outputs_product_b_m_a_out_new_WIRE_23
wire _butterfly_outputs_product_b_m_a_this_11 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_22 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_33 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_66 = asUInt(butterfly_outputs_product_b_m_a_out_0_11)
node _butterfly_outputs_product_b_m_a_new_T_67 = asSInt(_butterfly_outputs_product_b_m_a_new_T_66)
connect _butterfly_outputs_product_b_m_a_new_WIRE_33, _butterfly_outputs_product_b_m_a_new_T_67
connect _butterfly_outputs_product_b_m_a_new_22, _butterfly_outputs_product_b_m_a_new_WIRE_33
connect _butterfly_outputs_product_b_m_a_this_11, _butterfly_outputs_product_b_m_a_new_22
wire _butterfly_outputs_product_b_m_a_that_11 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_23 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_34 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_68 = asUInt(butterfly_outputs_product_b_m_a_out_1_11)
node _butterfly_outputs_product_b_m_a_new_T_69 = asSInt(_butterfly_outputs_product_b_m_a_new_T_68)
connect _butterfly_outputs_product_b_m_a_new_WIRE_34, _butterfly_outputs_product_b_m_a_new_T_69
connect _butterfly_outputs_product_b_m_a_new_23, _butterfly_outputs_product_b_m_a_new_WIRE_34
connect _butterfly_outputs_product_b_m_a_that_11, _butterfly_outputs_product_b_m_a_new_23
node _butterfly_outputs_product_b_m_a_T_33 = sub(_butterfly_outputs_product_b_m_a_this_11, _butterfly_outputs_product_b_m_a_that_11)
node _butterfly_outputs_product_b_m_a_T_34 = tail(_butterfly_outputs_product_b_m_a_T_33, 1)
node _butterfly_outputs_product_b_m_a_T_35 = asSInt(_butterfly_outputs_product_b_m_a_T_34)
wire butterfly_outputs_product_b_m_a_11 : SInt<16>
wire _butterfly_outputs_product_b_m_a_new_WIRE_35 : SInt<16>
node _butterfly_outputs_product_b_m_a_new_T_70 = asUInt(_butterfly_outputs_product_b_m_a_T_35)
node _butterfly_outputs_product_b_m_a_new_T_71 = asSInt(_butterfly_outputs_product_b_m_a_new_T_70)
connect _butterfly_outputs_product_b_m_a_new_WIRE_35, _butterfly_outputs_product_b_m_a_new_T_71
connect butterfly_outputs_product_b_m_a_11, _butterfly_outputs_product_b_m_a_new_WIRE_35
node _butterfly_outputs_product_ac_p_ad_T_11 = mul(stage_outputs_2_7.real, butterfly_outputs_product_c_p_d_11)
wire butterfly_outputs_product_ac_p_ad_11 : SInt<35>
wire _butterfly_outputs_product_ac_p_ad_new_WIRE_11 : SInt<35>
node _butterfly_outputs_product_ac_p_ad_new_T_22 = asUInt(_butterfly_outputs_product_ac_p_ad_T_11)
node _butterfly_outputs_product_ac_p_ad_new_T_23 = asSInt(_butterfly_outputs_product_ac_p_ad_new_T_22)
connect _butterfly_outputs_product_ac_p_ad_new_WIRE_11, _butterfly_outputs_product_ac_p_ad_new_T_23
connect butterfly_outputs_product_ac_p_ad_11, _butterfly_outputs_product_ac_p_ad_new_WIRE_11
node _butterfly_outputs_product_ad_p_bd_T_11 = mul(butterfly_outputs_product_a_p_b_11, twiddle[6].imag)
wire butterfly_outputs_product_ad_p_bd_11 : SInt<35>
wire _butterfly_outputs_product_ad_p_bd_new_WIRE_11 : SInt<35>
node _butterfly_outputs_product_ad_p_bd_new_T_22 = asUInt(_butterfly_outputs_product_ad_p_bd_T_11)
node _butterfly_outputs_product_ad_p_bd_new_T_23 = asSInt(_butterfly_outputs_product_ad_p_bd_new_T_22)
connect _butterfly_outputs_product_ad_p_bd_new_WIRE_11, _butterfly_outputs_product_ad_p_bd_new_T_23
connect butterfly_outputs_product_ad_p_bd_11, _butterfly_outputs_product_ad_p_bd_new_WIRE_11
node _butterfly_outputs_product_bc_m_ac_T_11 = mul(butterfly_outputs_product_b_m_a_11, twiddle[6].real)
wire butterfly_outputs_product_bc_m_ac_11 : SInt<35>
wire _butterfly_outputs_product_bc_m_ac_new_WIRE_11 : SInt<35>
node _butterfly_outputs_product_bc_m_ac_new_T_22 = asUInt(_butterfly_outputs_product_bc_m_ac_T_11)
node _butterfly_outputs_product_bc_m_ac_new_T_23 = asSInt(_butterfly_outputs_product_bc_m_ac_new_T_22)
connect _butterfly_outputs_product_bc_m_ac_new_WIRE_11, _butterfly_outputs_product_bc_m_ac_new_T_23
connect butterfly_outputs_product_bc_m_ac_11, _butterfly_outputs_product_bc_m_ac_new_WIRE_11
wire butterfly_outputs_product_out_0_22 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_44 : SInt<35>
node _butterfly_outputs_product_out_new_T_88 = asUInt(butterfly_outputs_product_ac_p_ad_11)
node _butterfly_outputs_product_out_new_T_89 = asSInt(_butterfly_outputs_product_out_new_T_88)
connect _butterfly_outputs_product_out_new_WIRE_44, _butterfly_outputs_product_out_new_T_89
connect butterfly_outputs_product_out_0_22, _butterfly_outputs_product_out_new_WIRE_44
wire butterfly_outputs_product_out_1_22 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_45 : SInt<35>
node _butterfly_outputs_product_out_new_T_90 = asUInt(butterfly_outputs_product_ad_p_bd_11)
node _butterfly_outputs_product_out_new_T_91 = asSInt(_butterfly_outputs_product_out_new_T_90)
connect _butterfly_outputs_product_out_new_WIRE_45, _butterfly_outputs_product_out_new_T_91
connect butterfly_outputs_product_out_1_22, _butterfly_outputs_product_out_new_WIRE_45
wire _butterfly_outputs_product_this_22 : SInt<35>
wire _butterfly_outputs_product_new_66 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_66 : SInt<35>
node _butterfly_outputs_product_new_T_132 = asUInt(butterfly_outputs_product_out_0_22)
node _butterfly_outputs_product_new_T_133 = asSInt(_butterfly_outputs_product_new_T_132)
connect _butterfly_outputs_product_new_WIRE_66, _butterfly_outputs_product_new_T_133
connect _butterfly_outputs_product_new_66, _butterfly_outputs_product_new_WIRE_66
connect _butterfly_outputs_product_this_22, _butterfly_outputs_product_new_66
wire _butterfly_outputs_product_that_22 : SInt<35>
wire _butterfly_outputs_product_new_67 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_67 : SInt<35>
node _butterfly_outputs_product_new_T_134 = asUInt(butterfly_outputs_product_out_1_22)
node _butterfly_outputs_product_new_T_135 = asSInt(_butterfly_outputs_product_new_T_134)
connect _butterfly_outputs_product_new_WIRE_67, _butterfly_outputs_product_new_T_135
connect _butterfly_outputs_product_new_67, _butterfly_outputs_product_new_WIRE_67
connect _butterfly_outputs_product_that_22, _butterfly_outputs_product_new_67
node _butterfly_outputs_product_T_66 = sub(_butterfly_outputs_product_this_22, _butterfly_outputs_product_that_22)
node _butterfly_outputs_product_T_67 = tail(_butterfly_outputs_product_T_66, 1)
node _butterfly_outputs_product_T_68 = asSInt(_butterfly_outputs_product_T_67)
wire _butterfly_outputs_product_new_68 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_68 : SInt<35>
node _butterfly_outputs_product_new_T_136 = asUInt(_butterfly_outputs_product_T_68)
node _butterfly_outputs_product_new_T_137 = asSInt(_butterfly_outputs_product_new_T_136)
connect _butterfly_outputs_product_new_WIRE_68, _butterfly_outputs_product_new_T_137
connect _butterfly_outputs_product_new_68, _butterfly_outputs_product_new_WIRE_68
wire butterfly_outputs_product_out_0_23 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_46 : SInt<35>
node _butterfly_outputs_product_out_new_T_92 = asUInt(butterfly_outputs_product_ac_p_ad_11)
node _butterfly_outputs_product_out_new_T_93 = asSInt(_butterfly_outputs_product_out_new_T_92)
connect _butterfly_outputs_product_out_new_WIRE_46, _butterfly_outputs_product_out_new_T_93
connect butterfly_outputs_product_out_0_23, _butterfly_outputs_product_out_new_WIRE_46
wire butterfly_outputs_product_out_1_23 : SInt<35>
wire _butterfly_outputs_product_out_new_WIRE_47 : SInt<35>
node _butterfly_outputs_product_out_new_T_94 = asUInt(butterfly_outputs_product_bc_m_ac_11)
node _butterfly_outputs_product_out_new_T_95 = asSInt(_butterfly_outputs_product_out_new_T_94)
connect _butterfly_outputs_product_out_new_WIRE_47, _butterfly_outputs_product_out_new_T_95
connect butterfly_outputs_product_out_1_23, _butterfly_outputs_product_out_new_WIRE_47
wire _butterfly_outputs_product_this_23 : SInt<35>
wire _butterfly_outputs_product_new_69 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_69 : SInt<35>
node _butterfly_outputs_product_new_T_138 = asUInt(butterfly_outputs_product_out_0_23)
node _butterfly_outputs_product_new_T_139 = asSInt(_butterfly_outputs_product_new_T_138)
connect _butterfly_outputs_product_new_WIRE_69, _butterfly_outputs_product_new_T_139
connect _butterfly_outputs_product_new_69, _butterfly_outputs_product_new_WIRE_69
connect _butterfly_outputs_product_this_23, _butterfly_outputs_product_new_69
wire _butterfly_outputs_product_that_23 : SInt<35>
wire _butterfly_outputs_product_new_70 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_70 : SInt<35>
node _butterfly_outputs_product_new_T_140 = asUInt(butterfly_outputs_product_out_1_23)
node _butterfly_outputs_product_new_T_141 = asSInt(_butterfly_outputs_product_new_T_140)
connect _butterfly_outputs_product_new_WIRE_70, _butterfly_outputs_product_new_T_141
connect _butterfly_outputs_product_new_70, _butterfly_outputs_product_new_WIRE_70
connect _butterfly_outputs_product_that_23, _butterfly_outputs_product_new_70
node _butterfly_outputs_product_T_69 = add(_butterfly_outputs_product_this_23, _butterfly_outputs_product_that_23)
node _butterfly_outputs_product_T_70 = tail(_butterfly_outputs_product_T_69, 1)
node _butterfly_outputs_product_T_71 = asSInt(_butterfly_outputs_product_T_70)
wire _butterfly_outputs_product_new_71 : SInt<35>
wire _butterfly_outputs_product_new_WIRE_71 : SInt<35>
node _butterfly_outputs_product_new_T_142 = asUInt(_butterfly_outputs_product_T_71)
node _butterfly_outputs_product_new_T_143 = asSInt(_butterfly_outputs_product_new_T_142)
connect _butterfly_outputs_product_new_WIRE_71, _butterfly_outputs_product_new_T_143
connect _butterfly_outputs_product_new_71, _butterfly_outputs_product_new_WIRE_71
wire butterfly_outputs_product_11 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_product_result_real_new_11 : SInt<35>
wire _butterfly_outputs_product_result_real_new_WIRE_11 : SInt<35>
node _butterfly_outputs_product_result_real_new_T_22 = asUInt(_butterfly_outputs_product_new_68)
node _butterfly_outputs_product_result_real_new_T_23 = asSInt(_butterfly_outputs_product_result_real_new_T_22)
connect _butterfly_outputs_product_result_real_new_WIRE_11, _butterfly_outputs_product_result_real_new_T_23
connect _butterfly_outputs_product_result_real_new_11, _butterfly_outputs_product_result_real_new_WIRE_11
connect butterfly_outputs_product_11.real, _butterfly_outputs_product_result_real_new_11
wire _butterfly_outputs_product_result_imag_new_11 : SInt<35>
wire _butterfly_outputs_product_result_imag_new_WIRE_11 : SInt<35>
node _butterfly_outputs_product_result_imag_new_T_22 = asUInt(_butterfly_outputs_product_new_71)
node _butterfly_outputs_product_result_imag_new_T_23 = asSInt(_butterfly_outputs_product_result_imag_new_T_22)
connect _butterfly_outputs_product_result_imag_new_WIRE_11, _butterfly_outputs_product_result_imag_new_T_23
connect _butterfly_outputs_product_result_imag_new_11, _butterfly_outputs_product_result_imag_new_WIRE_11
connect butterfly_outputs_product_11.imag, _butterfly_outputs_product_result_imag_new_11
node _butterfly_outputs_out_T_44 = shl(stage_outputs_2_6.real, 17)
wire butterfly_outputs_out_0_44 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_88 : SInt<35>
node _butterfly_outputs_out_new_T_176 = asUInt(_butterfly_outputs_out_T_44)
node _butterfly_outputs_out_new_T_177 = asSInt(_butterfly_outputs_out_new_T_176)
connect _butterfly_outputs_out_new_WIRE_88, _butterfly_outputs_out_new_T_177
connect butterfly_outputs_out_0_44, _butterfly_outputs_out_new_WIRE_88
wire butterfly_outputs_out_1_44 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_89 : SInt<35>
node _butterfly_outputs_out_new_T_178 = asUInt(butterfly_outputs_product_11.real)
node _butterfly_outputs_out_new_T_179 = asSInt(_butterfly_outputs_out_new_T_178)
connect _butterfly_outputs_out_new_WIRE_89, _butterfly_outputs_out_new_T_179
connect butterfly_outputs_out_1_44, _butterfly_outputs_out_new_WIRE_89
wire _butterfly_outputs_this_44 : SInt<35>
wire _butterfly_outputs_new_132 : SInt<35>
wire _butterfly_outputs_new_WIRE_132 : SInt<35>
node _butterfly_outputs_new_T_264 = asUInt(butterfly_outputs_out_0_44)
node _butterfly_outputs_new_T_265 = asSInt(_butterfly_outputs_new_T_264)
connect _butterfly_outputs_new_WIRE_132, _butterfly_outputs_new_T_265
connect _butterfly_outputs_new_132, _butterfly_outputs_new_WIRE_132
connect _butterfly_outputs_this_44, _butterfly_outputs_new_132
wire _butterfly_outputs_that_44 : SInt<35>
wire _butterfly_outputs_new_133 : SInt<35>
wire _butterfly_outputs_new_WIRE_133 : SInt<35>
node _butterfly_outputs_new_T_266 = asUInt(butterfly_outputs_out_1_44)
node _butterfly_outputs_new_T_267 = asSInt(_butterfly_outputs_new_T_266)
connect _butterfly_outputs_new_WIRE_133, _butterfly_outputs_new_T_267
connect _butterfly_outputs_new_133, _butterfly_outputs_new_WIRE_133
connect _butterfly_outputs_that_44, _butterfly_outputs_new_133
node _butterfly_outputs_T_132 = add(_butterfly_outputs_this_44, _butterfly_outputs_that_44)
node _butterfly_outputs_T_133 = tail(_butterfly_outputs_T_132, 1)
node _butterfly_outputs_T_134 = asSInt(_butterfly_outputs_T_133)
wire _butterfly_outputs_new_134 : SInt<35>
wire _butterfly_outputs_new_WIRE_134 : SInt<35>
node _butterfly_outputs_new_T_268 = asUInt(_butterfly_outputs_T_134)
node _butterfly_outputs_new_T_269 = asSInt(_butterfly_outputs_new_T_268)
connect _butterfly_outputs_new_WIRE_134, _butterfly_outputs_new_T_269
connect _butterfly_outputs_new_134, _butterfly_outputs_new_WIRE_134
node _butterfly_outputs_out_T_45 = shl(stage_outputs_2_6.imag, 17)
wire butterfly_outputs_out_0_45 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_90 : SInt<35>
node _butterfly_outputs_out_new_T_180 = asUInt(_butterfly_outputs_out_T_45)
node _butterfly_outputs_out_new_T_181 = asSInt(_butterfly_outputs_out_new_T_180)
connect _butterfly_outputs_out_new_WIRE_90, _butterfly_outputs_out_new_T_181
connect butterfly_outputs_out_0_45, _butterfly_outputs_out_new_WIRE_90
wire butterfly_outputs_out_1_45 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_91 : SInt<35>
node _butterfly_outputs_out_new_T_182 = asUInt(butterfly_outputs_product_11.imag)
node _butterfly_outputs_out_new_T_183 = asSInt(_butterfly_outputs_out_new_T_182)
connect _butterfly_outputs_out_new_WIRE_91, _butterfly_outputs_out_new_T_183
connect butterfly_outputs_out_1_45, _butterfly_outputs_out_new_WIRE_91
wire _butterfly_outputs_this_45 : SInt<35>
wire _butterfly_outputs_new_135 : SInt<35>
wire _butterfly_outputs_new_WIRE_135 : SInt<35>
node _butterfly_outputs_new_T_270 = asUInt(butterfly_outputs_out_0_45)
node _butterfly_outputs_new_T_271 = asSInt(_butterfly_outputs_new_T_270)
connect _butterfly_outputs_new_WIRE_135, _butterfly_outputs_new_T_271
connect _butterfly_outputs_new_135, _butterfly_outputs_new_WIRE_135
connect _butterfly_outputs_this_45, _butterfly_outputs_new_135
wire _butterfly_outputs_that_45 : SInt<35>
wire _butterfly_outputs_new_136 : SInt<35>
wire _butterfly_outputs_new_WIRE_136 : SInt<35>
node _butterfly_outputs_new_T_272 = asUInt(butterfly_outputs_out_1_45)
node _butterfly_outputs_new_T_273 = asSInt(_butterfly_outputs_new_T_272)
connect _butterfly_outputs_new_WIRE_136, _butterfly_outputs_new_T_273
connect _butterfly_outputs_new_136, _butterfly_outputs_new_WIRE_136
connect _butterfly_outputs_that_45, _butterfly_outputs_new_136
node _butterfly_outputs_T_135 = add(_butterfly_outputs_this_45, _butterfly_outputs_that_45)
node _butterfly_outputs_T_136 = tail(_butterfly_outputs_T_135, 1)
node _butterfly_outputs_T_137 = asSInt(_butterfly_outputs_T_136)
wire _butterfly_outputs_new_137 : SInt<35>
wire _butterfly_outputs_new_WIRE_137 : SInt<35>
node _butterfly_outputs_new_T_274 = asUInt(_butterfly_outputs_T_137)
node _butterfly_outputs_new_T_275 = asSInt(_butterfly_outputs_new_T_274)
connect _butterfly_outputs_new_WIRE_137, _butterfly_outputs_new_T_275
connect _butterfly_outputs_new_137, _butterfly_outputs_new_WIRE_137
wire butterfly_outputs_0_11 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_result_real_new_22 : SInt<35>
wire _butterfly_outputs_result_real_new_WIRE_22 : SInt<35>
node _butterfly_outputs_result_real_new_T_44 = asUInt(_butterfly_outputs_new_134)
node _butterfly_outputs_result_real_new_T_45 = asSInt(_butterfly_outputs_result_real_new_T_44)
connect _butterfly_outputs_result_real_new_WIRE_22, _butterfly_outputs_result_real_new_T_45
connect _butterfly_outputs_result_real_new_22, _butterfly_outputs_result_real_new_WIRE_22
connect butterfly_outputs_0_11.real, _butterfly_outputs_result_real_new_22
wire _butterfly_outputs_result_imag_new_22 : SInt<35>
wire _butterfly_outputs_result_imag_new_WIRE_22 : SInt<35>
node _butterfly_outputs_result_imag_new_T_44 = asUInt(_butterfly_outputs_new_137)
node _butterfly_outputs_result_imag_new_T_45 = asSInt(_butterfly_outputs_result_imag_new_T_44)
connect _butterfly_outputs_result_imag_new_WIRE_22, _butterfly_outputs_result_imag_new_T_45
connect _butterfly_outputs_result_imag_new_22, _butterfly_outputs_result_imag_new_WIRE_22
connect butterfly_outputs_0_11.imag, _butterfly_outputs_result_imag_new_22
node _butterfly_outputs_out_T_46 = shl(stage_outputs_2_6.real, 17)
wire butterfly_outputs_out_0_46 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_92 : SInt<35>
node _butterfly_outputs_out_new_T_184 = asUInt(_butterfly_outputs_out_T_46)
node _butterfly_outputs_out_new_T_185 = asSInt(_butterfly_outputs_out_new_T_184)
connect _butterfly_outputs_out_new_WIRE_92, _butterfly_outputs_out_new_T_185
connect butterfly_outputs_out_0_46, _butterfly_outputs_out_new_WIRE_92
wire butterfly_outputs_out_1_46 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_93 : SInt<35>
node _butterfly_outputs_out_new_T_186 = asUInt(butterfly_outputs_product_11.real)
node _butterfly_outputs_out_new_T_187 = asSInt(_butterfly_outputs_out_new_T_186)
connect _butterfly_outputs_out_new_WIRE_93, _butterfly_outputs_out_new_T_187
connect butterfly_outputs_out_1_46, _butterfly_outputs_out_new_WIRE_93
wire _butterfly_outputs_this_46 : SInt<35>
wire _butterfly_outputs_new_138 : SInt<35>
wire _butterfly_outputs_new_WIRE_138 : SInt<35>
node _butterfly_outputs_new_T_276 = asUInt(butterfly_outputs_out_0_46)
node _butterfly_outputs_new_T_277 = asSInt(_butterfly_outputs_new_T_276)
connect _butterfly_outputs_new_WIRE_138, _butterfly_outputs_new_T_277
connect _butterfly_outputs_new_138, _butterfly_outputs_new_WIRE_138
connect _butterfly_outputs_this_46, _butterfly_outputs_new_138
wire _butterfly_outputs_that_46 : SInt<35>
wire _butterfly_outputs_new_139 : SInt<35>
wire _butterfly_outputs_new_WIRE_139 : SInt<35>
node _butterfly_outputs_new_T_278 = asUInt(butterfly_outputs_out_1_46)
node _butterfly_outputs_new_T_279 = asSInt(_butterfly_outputs_new_T_278)
connect _butterfly_outputs_new_WIRE_139, _butterfly_outputs_new_T_279
connect _butterfly_outputs_new_139, _butterfly_outputs_new_WIRE_139
connect _butterfly_outputs_that_46, _butterfly_outputs_new_139
node _butterfly_outputs_T_138 = sub(_butterfly_outputs_this_46, _butterfly_outputs_that_46)
node _butterfly_outputs_T_139 = tail(_butterfly_outputs_T_138, 1)
node _butterfly_outputs_T_140 = asSInt(_butterfly_outputs_T_139)
wire _butterfly_outputs_new_140 : SInt<35>
wire _butterfly_outputs_new_WIRE_140 : SInt<35>
node _butterfly_outputs_new_T_280 = asUInt(_butterfly_outputs_T_140)
node _butterfly_outputs_new_T_281 = asSInt(_butterfly_outputs_new_T_280)
connect _butterfly_outputs_new_WIRE_140, _butterfly_outputs_new_T_281
connect _butterfly_outputs_new_140, _butterfly_outputs_new_WIRE_140
node _butterfly_outputs_out_T_47 = shl(stage_outputs_2_6.imag, 17)
wire butterfly_outputs_out_0_47 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_94 : SInt<35>
node _butterfly_outputs_out_new_T_188 = asUInt(_butterfly_outputs_out_T_47)
node _butterfly_outputs_out_new_T_189 = asSInt(_butterfly_outputs_out_new_T_188)
connect _butterfly_outputs_out_new_WIRE_94, _butterfly_outputs_out_new_T_189
connect butterfly_outputs_out_0_47, _butterfly_outputs_out_new_WIRE_94
wire butterfly_outputs_out_1_47 : SInt<35>
wire _butterfly_outputs_out_new_WIRE_95 : SInt<35>
node _butterfly_outputs_out_new_T_190 = asUInt(butterfly_outputs_product_11.imag)
node _butterfly_outputs_out_new_T_191 = asSInt(_butterfly_outputs_out_new_T_190)
connect _butterfly_outputs_out_new_WIRE_95, _butterfly_outputs_out_new_T_191
connect butterfly_outputs_out_1_47, _butterfly_outputs_out_new_WIRE_95
wire _butterfly_outputs_this_47 : SInt<35>
wire _butterfly_outputs_new_141 : SInt<35>
wire _butterfly_outputs_new_WIRE_141 : SInt<35>
node _butterfly_outputs_new_T_282 = asUInt(butterfly_outputs_out_0_47)
node _butterfly_outputs_new_T_283 = asSInt(_butterfly_outputs_new_T_282)
connect _butterfly_outputs_new_WIRE_141, _butterfly_outputs_new_T_283
connect _butterfly_outputs_new_141, _butterfly_outputs_new_WIRE_141
connect _butterfly_outputs_this_47, _butterfly_outputs_new_141
wire _butterfly_outputs_that_47 : SInt<35>
wire _butterfly_outputs_new_142 : SInt<35>
wire _butterfly_outputs_new_WIRE_142 : SInt<35>
node _butterfly_outputs_new_T_284 = asUInt(butterfly_outputs_out_1_47)
node _butterfly_outputs_new_T_285 = asSInt(_butterfly_outputs_new_T_284)
connect _butterfly_outputs_new_WIRE_142, _butterfly_outputs_new_T_285
connect _butterfly_outputs_new_142, _butterfly_outputs_new_WIRE_142
connect _butterfly_outputs_that_47, _butterfly_outputs_new_142
node _butterfly_outputs_T_141 = sub(_butterfly_outputs_this_47, _butterfly_outputs_that_47)
node _butterfly_outputs_T_142 = tail(_butterfly_outputs_T_141, 1)
node _butterfly_outputs_T_143 = asSInt(_butterfly_outputs_T_142)
wire _butterfly_outputs_new_143 : SInt<35>
wire _butterfly_outputs_new_WIRE_143 : SInt<35>
node _butterfly_outputs_new_T_286 = asUInt(_butterfly_outputs_T_143)
node _butterfly_outputs_new_T_287 = asSInt(_butterfly_outputs_new_T_286)
connect _butterfly_outputs_new_WIRE_143, _butterfly_outputs_new_T_287
connect _butterfly_outputs_new_143, _butterfly_outputs_new_WIRE_143
wire butterfly_outputs_1_11 : { real : SInt<35>, imag : SInt<35>}
wire _butterfly_outputs_result_real_new_23 : SInt<35>
wire _butterfly_outputs_result_real_new_WIRE_23 : SInt<35>
node _butterfly_outputs_result_real_new_T_46 = asUInt(_butterfly_outputs_new_140)
node _butterfly_outputs_result_real_new_T_47 = asSInt(_butterfly_outputs_result_real_new_T_46)
connect _butterfly_outputs_result_real_new_WIRE_23, _butterfly_outputs_result_real_new_T_47
connect _butterfly_outputs_result_real_new_23, _butterfly_outputs_result_real_new_WIRE_23
connect butterfly_outputs_1_11.real, _butterfly_outputs_result_real_new_23
wire _butterfly_outputs_result_imag_new_23 : SInt<35>
wire _butterfly_outputs_result_imag_new_WIRE_23 : SInt<35>
node _butterfly_outputs_result_imag_new_T_46 = asUInt(_butterfly_outputs_new_143)
node _butterfly_outputs_result_imag_new_T_47 = asSInt(_butterfly_outputs_result_imag_new_T_46)
connect _butterfly_outputs_result_imag_new_WIRE_23, _butterfly_outputs_result_imag_new_T_47
connect _butterfly_outputs_result_imag_new_23, _butterfly_outputs_result_imag_new_WIRE_23
connect butterfly_outputs_1_11.imag, _butterfly_outputs_result_imag_new_23
node _stage_outputs_3_6_stage_outputs_3_6_imag_T = shr(butterfly_outputs_0_11.imag, 17)
wire _stage_outputs_3_6_stage_outputs_3_6_imag_new : SInt<18>
wire _stage_outputs_3_6_stage_outputs_3_6_imag_new_WIRE : SInt<18>
node _stage_outputs_3_6_stage_outputs_3_6_imag_new_T = asUInt(_stage_outputs_3_6_stage_outputs_3_6_imag_T)
node _stage_outputs_3_6_stage_outputs_3_6_imag_new_T_1 = asSInt(_stage_outputs_3_6_stage_outputs_3_6_imag_new_T)
connect _stage_outputs_3_6_stage_outputs_3_6_imag_new_WIRE, _stage_outputs_3_6_stage_outputs_3_6_imag_new_T_1
connect _stage_outputs_3_6_stage_outputs_3_6_imag_new, _stage_outputs_3_6_stage_outputs_3_6_imag_new_WIRE
connect stage_outputs_3_6.imag, _stage_outputs_3_6_stage_outputs_3_6_imag_new
node _stage_outputs_3_6_stage_outputs_3_6_real_T = shr(butterfly_outputs_0_11.real, 17)
wire _stage_outputs_3_6_stage_outputs_3_6_real_new : SInt<18>
wire _stage_outputs_3_6_stage_outputs_3_6_real_new_WIRE : SInt<18>
node _stage_outputs_3_6_stage_outputs_3_6_real_new_T = asUInt(_stage_outputs_3_6_stage_outputs_3_6_real_T)
node _stage_outputs_3_6_stage_outputs_3_6_real_new_T_1 = asSInt(_stage_outputs_3_6_stage_outputs_3_6_real_new_T)
connect _stage_outputs_3_6_stage_outputs_3_6_real_new_WIRE, _stage_outputs_3_6_stage_outputs_3_6_real_new_T_1
connect _stage_outputs_3_6_stage_outputs_3_6_real_new, _stage_outputs_3_6_stage_outputs_3_6_real_new_WIRE
connect stage_outputs_3_6.real, _stage_outputs_3_6_stage_outputs_3_6_real_new
node _stage_outputs_3_7_stage_outputs_3_7_imag_T = shr(butterfly_outputs_1_11.imag, 17)
wire _stage_outputs_3_7_stage_outputs_3_7_imag_new : SInt<18>
wire _stage_outputs_3_7_stage_outputs_3_7_imag_new_WIRE : SInt<18>
node _stage_outputs_3_7_stage_outputs_3_7_imag_new_T = asUInt(_stage_outputs_3_7_stage_outputs_3_7_imag_T)
node _stage_outputs_3_7_stage_outputs_3_7_imag_new_T_1 = asSInt(_stage_outputs_3_7_stage_outputs_3_7_imag_new_T)
connect _stage_outputs_3_7_stage_outputs_3_7_imag_new_WIRE, _stage_outputs_3_7_stage_outputs_3_7_imag_new_T_1
connect _stage_outputs_3_7_stage_outputs_3_7_imag_new, _stage_outputs_3_7_stage_outputs_3_7_imag_new_WIRE
connect stage_outputs_3_7.imag, _stage_outputs_3_7_stage_outputs_3_7_imag_new
node _stage_outputs_3_7_stage_outputs_3_7_real_T = shr(butterfly_outputs_1_11.real, 17)
wire _stage_outputs_3_7_stage_outputs_3_7_real_new : SInt<18>
wire _stage_outputs_3_7_stage_outputs_3_7_real_new_WIRE : SInt<18>
node _stage_outputs_3_7_stage_outputs_3_7_real_new_T = asUInt(_stage_outputs_3_7_stage_outputs_3_7_real_T)
node _stage_outputs_3_7_stage_outputs_3_7_real_new_T_1 = asSInt(_stage_outputs_3_7_stage_outputs_3_7_real_new_T)
connect _stage_outputs_3_7_stage_outputs_3_7_real_new_WIRE, _stage_outputs_3_7_stage_outputs_3_7_real_new_T_1
connect _stage_outputs_3_7_stage_outputs_3_7_real_new, _stage_outputs_3_7_stage_outputs_3_7_real_new_WIRE
connect stage_outputs_3_7.real, _stage_outputs_3_7_stage_outputs_3_7_real_new
wire _io_out_bits_0_io_out_bits_0_imag_new : SInt<16>
wire _io_out_bits_0_io_out_bits_0_imag_new_WIRE : SInt<16>
node _io_out_bits_0_io_out_bits_0_imag_new_T = asUInt(stage_outputs_3_0.imag)
node _io_out_bits_0_io_out_bits_0_imag_new_T_1 = asSInt(_io_out_bits_0_io_out_bits_0_imag_new_T)
connect _io_out_bits_0_io_out_bits_0_imag_new_WIRE, _io_out_bits_0_io_out_bits_0_imag_new_T_1
connect _io_out_bits_0_io_out_bits_0_imag_new, _io_out_bits_0_io_out_bits_0_imag_new_WIRE
connect io.out.bits[0].imag, _io_out_bits_0_io_out_bits_0_imag_new
wire _io_out_bits_0_io_out_bits_0_real_new : SInt<16>
wire _io_out_bits_0_io_out_bits_0_real_new_WIRE : SInt<16>
node _io_out_bits_0_io_out_bits_0_real_new_T = asUInt(stage_outputs_3_0.real)
node _io_out_bits_0_io_out_bits_0_real_new_T_1 = asSInt(_io_out_bits_0_io_out_bits_0_real_new_T)
connect _io_out_bits_0_io_out_bits_0_real_new_WIRE, _io_out_bits_0_io_out_bits_0_real_new_T_1
connect _io_out_bits_0_io_out_bits_0_real_new, _io_out_bits_0_io_out_bits_0_real_new_WIRE
connect io.out.bits[0].real, _io_out_bits_0_io_out_bits_0_real_new
wire _io_out_bits_1_io_out_bits_1_imag_new : SInt<16>
wire _io_out_bits_1_io_out_bits_1_imag_new_WIRE : SInt<16>
node _io_out_bits_1_io_out_bits_1_imag_new_T = asUInt(stage_outputs_3_1.imag)
node _io_out_bits_1_io_out_bits_1_imag_new_T_1 = asSInt(_io_out_bits_1_io_out_bits_1_imag_new_T)
connect _io_out_bits_1_io_out_bits_1_imag_new_WIRE, _io_out_bits_1_io_out_bits_1_imag_new_T_1
connect _io_out_bits_1_io_out_bits_1_imag_new, _io_out_bits_1_io_out_bits_1_imag_new_WIRE
connect io.out.bits[1].imag, _io_out_bits_1_io_out_bits_1_imag_new
wire _io_out_bits_1_io_out_bits_1_real_new : SInt<16>
wire _io_out_bits_1_io_out_bits_1_real_new_WIRE : SInt<16>
node _io_out_bits_1_io_out_bits_1_real_new_T = asUInt(stage_outputs_3_1.real)
node _io_out_bits_1_io_out_bits_1_real_new_T_1 = asSInt(_io_out_bits_1_io_out_bits_1_real_new_T)
connect _io_out_bits_1_io_out_bits_1_real_new_WIRE, _io_out_bits_1_io_out_bits_1_real_new_T_1
connect _io_out_bits_1_io_out_bits_1_real_new, _io_out_bits_1_io_out_bits_1_real_new_WIRE
connect io.out.bits[1].real, _io_out_bits_1_io_out_bits_1_real_new
wire _io_out_bits_2_io_out_bits_2_imag_new : SInt<16>
wire _io_out_bits_2_io_out_bits_2_imag_new_WIRE : SInt<16>
node _io_out_bits_2_io_out_bits_2_imag_new_T = asUInt(stage_outputs_3_2.imag)
node _io_out_bits_2_io_out_bits_2_imag_new_T_1 = asSInt(_io_out_bits_2_io_out_bits_2_imag_new_T)
connect _io_out_bits_2_io_out_bits_2_imag_new_WIRE, _io_out_bits_2_io_out_bits_2_imag_new_T_1
connect _io_out_bits_2_io_out_bits_2_imag_new, _io_out_bits_2_io_out_bits_2_imag_new_WIRE
connect io.out.bits[2].imag, _io_out_bits_2_io_out_bits_2_imag_new
wire _io_out_bits_2_io_out_bits_2_real_new : SInt<16>
wire _io_out_bits_2_io_out_bits_2_real_new_WIRE : SInt<16>
node _io_out_bits_2_io_out_bits_2_real_new_T = asUInt(stage_outputs_3_2.real)
node _io_out_bits_2_io_out_bits_2_real_new_T_1 = asSInt(_io_out_bits_2_io_out_bits_2_real_new_T)
connect _io_out_bits_2_io_out_bits_2_real_new_WIRE, _io_out_bits_2_io_out_bits_2_real_new_T_1
connect _io_out_bits_2_io_out_bits_2_real_new, _io_out_bits_2_io_out_bits_2_real_new_WIRE
connect io.out.bits[2].real, _io_out_bits_2_io_out_bits_2_real_new
wire _io_out_bits_3_io_out_bits_3_imag_new : SInt<16>
wire _io_out_bits_3_io_out_bits_3_imag_new_WIRE : SInt<16>
node _io_out_bits_3_io_out_bits_3_imag_new_T = asUInt(stage_outputs_3_3.imag)
node _io_out_bits_3_io_out_bits_3_imag_new_T_1 = asSInt(_io_out_bits_3_io_out_bits_3_imag_new_T)
connect _io_out_bits_3_io_out_bits_3_imag_new_WIRE, _io_out_bits_3_io_out_bits_3_imag_new_T_1
connect _io_out_bits_3_io_out_bits_3_imag_new, _io_out_bits_3_io_out_bits_3_imag_new_WIRE
connect io.out.bits[3].imag, _io_out_bits_3_io_out_bits_3_imag_new
wire _io_out_bits_3_io_out_bits_3_real_new : SInt<16>
wire _io_out_bits_3_io_out_bits_3_real_new_WIRE : SInt<16>
node _io_out_bits_3_io_out_bits_3_real_new_T = asUInt(stage_outputs_3_3.real)
node _io_out_bits_3_io_out_bits_3_real_new_T_1 = asSInt(_io_out_bits_3_io_out_bits_3_real_new_T)
connect _io_out_bits_3_io_out_bits_3_real_new_WIRE, _io_out_bits_3_io_out_bits_3_real_new_T_1
connect _io_out_bits_3_io_out_bits_3_real_new, _io_out_bits_3_io_out_bits_3_real_new_WIRE
connect io.out.bits[3].real, _io_out_bits_3_io_out_bits_3_real_new
wire _io_out_bits_4_io_out_bits_4_imag_new : SInt<16>
wire _io_out_bits_4_io_out_bits_4_imag_new_WIRE : SInt<16>
node _io_out_bits_4_io_out_bits_4_imag_new_T = asUInt(stage_outputs_3_4.imag)
node _io_out_bits_4_io_out_bits_4_imag_new_T_1 = asSInt(_io_out_bits_4_io_out_bits_4_imag_new_T)
connect _io_out_bits_4_io_out_bits_4_imag_new_WIRE, _io_out_bits_4_io_out_bits_4_imag_new_T_1
connect _io_out_bits_4_io_out_bits_4_imag_new, _io_out_bits_4_io_out_bits_4_imag_new_WIRE
connect io.out.bits[4].imag, _io_out_bits_4_io_out_bits_4_imag_new
wire _io_out_bits_4_io_out_bits_4_real_new : SInt<16>
wire _io_out_bits_4_io_out_bits_4_real_new_WIRE : SInt<16>
node _io_out_bits_4_io_out_bits_4_real_new_T = asUInt(stage_outputs_3_4.real)
node _io_out_bits_4_io_out_bits_4_real_new_T_1 = asSInt(_io_out_bits_4_io_out_bits_4_real_new_T)
connect _io_out_bits_4_io_out_bits_4_real_new_WIRE, _io_out_bits_4_io_out_bits_4_real_new_T_1
connect _io_out_bits_4_io_out_bits_4_real_new, _io_out_bits_4_io_out_bits_4_real_new_WIRE
connect io.out.bits[4].real, _io_out_bits_4_io_out_bits_4_real_new
wire _io_out_bits_5_io_out_bits_5_imag_new : SInt<16>
wire _io_out_bits_5_io_out_bits_5_imag_new_WIRE : SInt<16>
node _io_out_bits_5_io_out_bits_5_imag_new_T = asUInt(stage_outputs_3_5.imag)
node _io_out_bits_5_io_out_bits_5_imag_new_T_1 = asSInt(_io_out_bits_5_io_out_bits_5_imag_new_T)
connect _io_out_bits_5_io_out_bits_5_imag_new_WIRE, _io_out_bits_5_io_out_bits_5_imag_new_T_1
connect _io_out_bits_5_io_out_bits_5_imag_new, _io_out_bits_5_io_out_bits_5_imag_new_WIRE
connect io.out.bits[5].imag, _io_out_bits_5_io_out_bits_5_imag_new
wire _io_out_bits_5_io_out_bits_5_real_new : SInt<16>
wire _io_out_bits_5_io_out_bits_5_real_new_WIRE : SInt<16>
node _io_out_bits_5_io_out_bits_5_real_new_T = asUInt(stage_outputs_3_5.real)
node _io_out_bits_5_io_out_bits_5_real_new_T_1 = asSInt(_io_out_bits_5_io_out_bits_5_real_new_T)
connect _io_out_bits_5_io_out_bits_5_real_new_WIRE, _io_out_bits_5_io_out_bits_5_real_new_T_1
connect _io_out_bits_5_io_out_bits_5_real_new, _io_out_bits_5_io_out_bits_5_real_new_WIRE
connect io.out.bits[5].real, _io_out_bits_5_io_out_bits_5_real_new
wire _io_out_bits_6_io_out_bits_6_imag_new : SInt<16>
wire _io_out_bits_6_io_out_bits_6_imag_new_WIRE : SInt<16>
node _io_out_bits_6_io_out_bits_6_imag_new_T = asUInt(stage_outputs_3_6.imag)
node _io_out_bits_6_io_out_bits_6_imag_new_T_1 = asSInt(_io_out_bits_6_io_out_bits_6_imag_new_T)
connect _io_out_bits_6_io_out_bits_6_imag_new_WIRE, _io_out_bits_6_io_out_bits_6_imag_new_T_1
connect _io_out_bits_6_io_out_bits_6_imag_new, _io_out_bits_6_io_out_bits_6_imag_new_WIRE
connect io.out.bits[6].imag, _io_out_bits_6_io_out_bits_6_imag_new
wire _io_out_bits_6_io_out_bits_6_real_new : SInt<16>
wire _io_out_bits_6_io_out_bits_6_real_new_WIRE : SInt<16>
node _io_out_bits_6_io_out_bits_6_real_new_T = asUInt(stage_outputs_3_6.real)
node _io_out_bits_6_io_out_bits_6_real_new_T_1 = asSInt(_io_out_bits_6_io_out_bits_6_real_new_T)
connect _io_out_bits_6_io_out_bits_6_real_new_WIRE, _io_out_bits_6_io_out_bits_6_real_new_T_1
connect _io_out_bits_6_io_out_bits_6_real_new, _io_out_bits_6_io_out_bits_6_real_new_WIRE
connect io.out.bits[6].real, _io_out_bits_6_io_out_bits_6_real_new
wire _io_out_bits_7_io_out_bits_7_imag_new : SInt<16>
wire _io_out_bits_7_io_out_bits_7_imag_new_WIRE : SInt<16>
node _io_out_bits_7_io_out_bits_7_imag_new_T = asUInt(stage_outputs_3_7.imag)
node _io_out_bits_7_io_out_bits_7_imag_new_T_1 = asSInt(_io_out_bits_7_io_out_bits_7_imag_new_T)
connect _io_out_bits_7_io_out_bits_7_imag_new_WIRE, _io_out_bits_7_io_out_bits_7_imag_new_T_1
connect _io_out_bits_7_io_out_bits_7_imag_new, _io_out_bits_7_io_out_bits_7_imag_new_WIRE
connect io.out.bits[7].imag, _io_out_bits_7_io_out_bits_7_imag_new
wire _io_out_bits_7_io_out_bits_7_real_new : SInt<16>
wire _io_out_bits_7_io_out_bits_7_real_new_WIRE : SInt<16>
node _io_out_bits_7_io_out_bits_7_real_new_T = asUInt(stage_outputs_3_7.real)
node _io_out_bits_7_io_out_bits_7_real_new_T_1 = asSInt(_io_out_bits_7_io_out_bits_7_real_new_T)
connect _io_out_bits_7_io_out_bits_7_real_new_WIRE, _io_out_bits_7_io_out_bits_7_real_new_T_1
connect _io_out_bits_7_io_out_bits_7_real_new, _io_out_bits_7_io_out_bits_7_real_new_WIRE
connect io.out.bits[7].real, _io_out_bits_7_io_out_bits_7_real_new | module DirectFFT( // @[FFT.scala:31:7]
input io_in_valid, // @[FFT.scala:32:14]
input [15:0] io_in_bits_0_real, // @[FFT.scala:32:14]
input [15:0] io_in_bits_0_imag, // @[FFT.scala:32:14]
input [15:0] io_in_bits_1_real, // @[FFT.scala:32:14]
input [15:0] io_in_bits_1_imag, // @[FFT.scala:32:14]
input [15:0] io_in_bits_2_real, // @[FFT.scala:32:14]
input [15:0] io_in_bits_2_imag, // @[FFT.scala:32:14]
input [15:0] io_in_bits_3_real, // @[FFT.scala:32:14]
input [15:0] io_in_bits_3_imag, // @[FFT.scala:32:14]
input [15:0] io_in_bits_4_real, // @[FFT.scala:32:14]
input [15:0] io_in_bits_4_imag, // @[FFT.scala:32:14]
input [15:0] io_in_bits_5_real, // @[FFT.scala:32:14]
input [15:0] io_in_bits_5_imag, // @[FFT.scala:32:14]
input [15:0] io_in_bits_6_real, // @[FFT.scala:32:14]
input [15:0] io_in_bits_6_imag, // @[FFT.scala:32:14]
input [15:0] io_in_bits_7_real, // @[FFT.scala:32:14]
input [15:0] io_in_bits_7_imag, // @[FFT.scala:32:14]
output io_out_valid, // @[FFT.scala:32:14]
output [15:0] io_out_bits_0_real, // @[FFT.scala:32:14]
output [15:0] io_out_bits_0_imag, // @[FFT.scala:32:14]
output [15:0] io_out_bits_1_real, // @[FFT.scala:32:14]
output [15:0] io_out_bits_1_imag, // @[FFT.scala:32:14]
output [15:0] io_out_bits_2_real, // @[FFT.scala:32:14]
output [15:0] io_out_bits_2_imag, // @[FFT.scala:32:14]
output [15:0] io_out_bits_3_real, // @[FFT.scala:32:14]
output [15:0] io_out_bits_3_imag, // @[FFT.scala:32:14]
output [15:0] io_out_bits_4_real, // @[FFT.scala:32:14]
output [15:0] io_out_bits_4_imag, // @[FFT.scala:32:14]
output [15:0] io_out_bits_5_real, // @[FFT.scala:32:14]
output [15:0] io_out_bits_5_imag, // @[FFT.scala:32:14]
output [15:0] io_out_bits_6_real, // @[FFT.scala:32:14]
output [15:0] io_out_bits_6_imag, // @[FFT.scala:32:14]
output [15:0] io_out_bits_7_real, // @[FFT.scala:32:14]
output [15:0] io_out_bits_7_imag // @[FFT.scala:32:14]
);
wire [32:0] _GEN = {io_in_bits_4_real, 17'h0}; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_product_T_3 = _GEN + {io_in_bits_4_imag - io_in_bits_4_real, 17'h0}; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _GEN_0 = {io_in_bits_0_real, 17'h0}; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_T = _GEN_0 + _GEN; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _GEN_1 = {io_in_bits_0_imag, 17'h0}; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_T_3 = _GEN_1 + _butterfly_outputs_product_T_3; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_T_6 = _GEN_0 - _GEN; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _butterfly_outputs_T_9 = _GEN_1 - _butterfly_outputs_product_T_3; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _GEN_2 = {io_in_bits_5_real, 17'h0}; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_product_T_9 = _GEN_2 + {io_in_bits_5_imag - io_in_bits_5_real, 17'h0}; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _GEN_3 = {io_in_bits_1_real, 17'h0}; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_T_12 = _GEN_3 + _GEN_2; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _GEN_4 = {io_in_bits_1_imag, 17'h0}; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_T_15 = _GEN_4 + _butterfly_outputs_product_T_9; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_T_18 = _GEN_3 - _GEN_2; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _butterfly_outputs_T_21 = _GEN_4 - _butterfly_outputs_product_T_9; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _GEN_5 = {io_in_bits_6_real, 17'h0}; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_product_T_15 = _GEN_5 + {io_in_bits_6_imag - io_in_bits_6_real, 17'h0}; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _GEN_6 = {io_in_bits_2_real, 17'h0}; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_T_24 = _GEN_6 + _GEN_5; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _GEN_7 = {io_in_bits_2_imag, 17'h0}; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_T_27 = _GEN_7 + _butterfly_outputs_product_T_15; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_T_30 = _GEN_6 - _GEN_5; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _butterfly_outputs_T_33 = _GEN_7 - _butterfly_outputs_product_T_15; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _GEN_8 = {io_in_bits_7_real, 17'h0}; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_product_T_21 = _GEN_8 + {io_in_bits_7_imag - io_in_bits_7_real, 17'h0}; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _GEN_9 = {io_in_bits_3_real, 17'h0}; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_T_36 = _GEN_9 + _GEN_8; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _GEN_10 = {io_in_bits_3_imag, 17'h0}; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_T_39 = _GEN_10 + _butterfly_outputs_product_T_21; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_T_42 = _GEN_9 - _GEN_8; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _butterfly_outputs_T_45 = _GEN_10 - _butterfly_outputs_product_T_21; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _GEN_11 = {_butterfly_outputs_T_24[32:17], 17'h0}; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_product_T_27 = _GEN_11 + {_butterfly_outputs_T_27[32:17] - _butterfly_outputs_T_24[32:17], 17'h0}; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _GEN_12 = {_butterfly_outputs_T[32:17], 17'h0}; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_T_48 = _GEN_12 + _GEN_11; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _GEN_13 = {_butterfly_outputs_T_3[32:17], 17'h0}; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_T_51 = _GEN_13 + _butterfly_outputs_product_T_27; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_T_54 = _GEN_12 - _GEN_11; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _butterfly_outputs_T_57 = _GEN_13 - _butterfly_outputs_product_T_27; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _GEN_14 = {_butterfly_outputs_T_36[32:17], 17'h0}; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_product_T_33 = _GEN_14 + {_butterfly_outputs_T_39[32:17] - _butterfly_outputs_T_36[32:17], 17'h0}; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _GEN_15 = {_butterfly_outputs_T_12[32:17], 17'h0}; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_T_60 = _GEN_15 + _GEN_14; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _GEN_16 = {_butterfly_outputs_T_15[32:17], 17'h0}; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_T_63 = _GEN_16 + _butterfly_outputs_product_T_33; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_T_66 = _GEN_15 - _GEN_14; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _butterfly_outputs_T_69 = _GEN_16 - _butterfly_outputs_product_T_33; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [15:0] _butterfly_outputs_product_a_p_b_T_18 = _butterfly_outputs_T_30[32:17] + _butterfly_outputs_T_33[32:17]; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _butterfly_outputs_product_ac_p_ad_new_T_13 = {{17{_butterfly_outputs_T_30[32]}}, _butterfly_outputs_T_30[32:17]} * 33'h1FFFE0000; // @[FixedPointTypeClass.scala:30:68, :42:59]
wire [32:0] _butterfly_outputs_product_T_36 = _butterfly_outputs_product_ac_p_ad_new_T_13 - {{17{_butterfly_outputs_product_a_p_b_T_18[15]}}, _butterfly_outputs_product_a_p_b_T_18} * 33'h1FFFE0000; // @[FixedPointTypeClass.scala:20:58, :30:68, :42:59]
wire [32:0] _GEN_17 = {_butterfly_outputs_T_6[32:17], 17'h0}; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _butterfly_outputs_T_72 = _GEN_17 + _butterfly_outputs_product_T_36; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _GEN_18 = {_butterfly_outputs_T_9[32:17], 17'h0}; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _butterfly_outputs_T_75 = _GEN_18 + _butterfly_outputs_product_ac_p_ad_new_T_13; // @[FixedPointTypeClass.scala:20:58, :42:59]
wire [32:0] _butterfly_outputs_T_78 = _GEN_17 - _butterfly_outputs_product_T_36; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _butterfly_outputs_T_81 = _GEN_18 - _butterfly_outputs_product_ac_p_ad_new_T_13; // @[FixedPointTypeClass.scala:20:58, :30:68, :42:59]
wire [15:0] _butterfly_outputs_product_a_p_b_T_21 = _butterfly_outputs_T_42[32:17] + _butterfly_outputs_T_45[32:17]; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _butterfly_outputs_product_ac_p_ad_new_T_15 = {{17{_butterfly_outputs_T_42[32]}}, _butterfly_outputs_T_42[32:17]} * 33'h1FFFE0000; // @[FixedPointTypeClass.scala:30:68, :42:59]
wire [32:0] _butterfly_outputs_product_T_42 = _butterfly_outputs_product_ac_p_ad_new_T_15 - {{17{_butterfly_outputs_product_a_p_b_T_21[15]}}, _butterfly_outputs_product_a_p_b_T_21} * 33'h1FFFE0000; // @[FixedPointTypeClass.scala:20:58, :30:68, :42:59]
wire [32:0] _GEN_19 = {_butterfly_outputs_T_18[32:17], 17'h0}; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _butterfly_outputs_T_84 = _GEN_19 + _butterfly_outputs_product_T_42; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _GEN_20 = {_butterfly_outputs_T_21[32:17], 17'h0}; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _butterfly_outputs_T_87 = _GEN_20 + _butterfly_outputs_product_ac_p_ad_new_T_15; // @[FixedPointTypeClass.scala:20:58, :42:59]
wire [32:0] _butterfly_outputs_T_90 = _GEN_19 - _butterfly_outputs_product_T_42; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _butterfly_outputs_T_93 = _GEN_20 - _butterfly_outputs_product_ac_p_ad_new_T_15; // @[FixedPointTypeClass.scala:20:58, :30:68, :42:59]
wire [32:0] _GEN_21 = {_butterfly_outputs_T_60[32:17], 17'h0}; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_product_T_51 = _GEN_21 + {_butterfly_outputs_T_63[32:17] - _butterfly_outputs_T_60[32:17], 17'h0}; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _GEN_22 = {_butterfly_outputs_T_48[32:17], 17'h0}; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_T_96 = _GEN_22 + _GEN_21; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _GEN_23 = {_butterfly_outputs_T_51[32:17], 17'h0}; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_T_99 = _GEN_23 + _butterfly_outputs_product_T_51; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_T_102 = _GEN_22 - _GEN_21; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _butterfly_outputs_T_105 = _GEN_23 - _butterfly_outputs_product_T_51; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [15:0] _butterfly_outputs_product_a_p_b_T_27 = _butterfly_outputs_T_66[32:17] + _butterfly_outputs_T_69[32:17]; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _butterfly_outputs_product_ac_p_ad_new_T_19 = {{17{_butterfly_outputs_T_66[32]}}, _butterfly_outputs_T_66[32:17]} * 33'h1FFFE0000; // @[FixedPointTypeClass.scala:30:68, :42:59]
wire [32:0] _butterfly_outputs_product_T_54 = _butterfly_outputs_product_ac_p_ad_new_T_19 - {{17{_butterfly_outputs_product_a_p_b_T_27[15]}}, _butterfly_outputs_product_a_p_b_T_27} * 33'h1FFFE0000; // @[FixedPointTypeClass.scala:20:58, :30:68, :42:59]
wire [32:0] _GEN_24 = {_butterfly_outputs_T_54[32:17], 17'h0}; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _butterfly_outputs_T_108 = _GEN_24 + _butterfly_outputs_product_T_54; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _GEN_25 = {_butterfly_outputs_T_57[32:17], 17'h0}; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _butterfly_outputs_T_111 = _GEN_25 + _butterfly_outputs_product_ac_p_ad_new_T_19; // @[FixedPointTypeClass.scala:20:58, :42:59]
wire [32:0] _butterfly_outputs_T_114 = _GEN_24 - _butterfly_outputs_product_T_54; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _butterfly_outputs_T_117 = _GEN_25 - _butterfly_outputs_product_ac_p_ad_new_T_19; // @[FixedPointTypeClass.scala:20:58, :30:68, :42:59]
wire [15:0] _butterfly_outputs_product_a_p_b_T_30 = _butterfly_outputs_T_84[32:17] + _butterfly_outputs_T_87[32:17]; // @[FixedPointTypeClass.scala:20:58]
wire [15:0] _butterfly_outputs_product_b_m_a_T_30 = _butterfly_outputs_T_87[32:17] - _butterfly_outputs_T_84[32:17]; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _butterfly_outputs_product_bc_m_ac_new_T_21 = {{17{_butterfly_outputs_product_b_m_a_T_30[15]}}, _butterfly_outputs_product_b_m_a_T_30} * 33'h16A0A; // @[FixedPointTypeClass.scala:30:68, :42:59]
wire [32:0] _butterfly_outputs_product_T_60 = 33'h0 - {{17{_butterfly_outputs_product_a_p_b_T_30[15]}}, _butterfly_outputs_product_a_p_b_T_30} * 33'h1FFFE95F6; // @[FixedPointTypeClass.scala:20:58, :30:68, :42:59]
wire [32:0] _GEN_26 = {_butterfly_outputs_T_72[32:17], 17'h0}; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_T_120 = _GEN_26 + _butterfly_outputs_product_T_60; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _GEN_27 = {_butterfly_outputs_T_75[32:17], 17'h0}; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_T_123 = _GEN_27 + _butterfly_outputs_product_bc_m_ac_new_T_21; // @[FixedPointTypeClass.scala:20:58, :42:59]
wire [32:0] _butterfly_outputs_T_126 = _GEN_26 - _butterfly_outputs_product_T_60; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _butterfly_outputs_T_129 = _GEN_27 - _butterfly_outputs_product_bc_m_ac_new_T_21; // @[FixedPointTypeClass.scala:20:58, :30:68, :42:59]
wire [15:0] _butterfly_outputs_product_a_p_b_T_33 = _butterfly_outputs_T_90[32:17] + _butterfly_outputs_T_93[32:17]; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [15:0] _butterfly_outputs_product_b_m_a_T_33 = _butterfly_outputs_T_93[32:17] - _butterfly_outputs_T_90[32:17]; // @[FixedPointTypeClass.scala:30:68]
wire [32:0] _butterfly_outputs_product_ac_p_ad_new_T_23 = {{17{_butterfly_outputs_T_90[32]}}, _butterfly_outputs_T_90[32:17]} * 33'h1FFFD2BEC; // @[FixedPointTypeClass.scala:30:68, :42:59]
wire [32:0] _butterfly_outputs_product_T_66 = _butterfly_outputs_product_ac_p_ad_new_T_23 - {{17{_butterfly_outputs_product_a_p_b_T_33[15]}}, _butterfly_outputs_product_a_p_b_T_33} * 33'h1FFFE95F6; // @[FixedPointTypeClass.scala:20:58, :30:68, :42:59]
wire [32:0] _butterfly_outputs_product_T_69 = _butterfly_outputs_product_ac_p_ad_new_T_23 + {{17{_butterfly_outputs_product_b_m_a_T_33[15]}}, _butterfly_outputs_product_b_m_a_T_33} * 33'h1FFFE95F6; // @[FixedPointTypeClass.scala:20:58, :30:68, :42:59]
wire [32:0] _GEN_28 = {_butterfly_outputs_T_78[32:17], 17'h0}; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _butterfly_outputs_T_132 = _GEN_28 + _butterfly_outputs_product_T_66; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _GEN_29 = {_butterfly_outputs_T_81[32:17], 17'h0}; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _butterfly_outputs_T_135 = _GEN_29 + _butterfly_outputs_product_T_69; // @[FixedPointTypeClass.scala:20:58]
wire [32:0] _butterfly_outputs_T_138 = _GEN_28 - _butterfly_outputs_product_T_66; // @[FixedPointTypeClass.scala:20:58, :30:68]
wire [32:0] _butterfly_outputs_T_141 = _GEN_29 - _butterfly_outputs_product_T_69; // @[FixedPointTypeClass.scala:20:58, :30:68]
assign io_out_valid = io_in_valid; // @[FFT.scala:31:7]
assign io_out_bits_0_real = _butterfly_outputs_T_96[32:17]; // @[FixedPointTypeClass.scala:20:58]
assign io_out_bits_0_imag = _butterfly_outputs_T_99[32:17]; // @[FixedPointTypeClass.scala:20:58]
assign io_out_bits_1_real = _butterfly_outputs_T_102[32:17]; // @[FixedPointTypeClass.scala:30:68]
assign io_out_bits_1_imag = _butterfly_outputs_T_105[32:17]; // @[FixedPointTypeClass.scala:30:68]
assign io_out_bits_2_real = _butterfly_outputs_T_108[32:17]; // @[FixedPointTypeClass.scala:20:58]
assign io_out_bits_2_imag = _butterfly_outputs_T_111[32:17]; // @[FixedPointTypeClass.scala:20:58]
assign io_out_bits_3_real = _butterfly_outputs_T_114[32:17]; // @[FixedPointTypeClass.scala:30:68]
assign io_out_bits_3_imag = _butterfly_outputs_T_117[32:17]; // @[FixedPointTypeClass.scala:30:68]
assign io_out_bits_4_real = _butterfly_outputs_T_120[32:17]; // @[FixedPointTypeClass.scala:20:58]
assign io_out_bits_4_imag = _butterfly_outputs_T_123[32:17]; // @[FixedPointTypeClass.scala:20:58]
assign io_out_bits_5_real = _butterfly_outputs_T_126[32:17]; // @[FixedPointTypeClass.scala:30:68]
assign io_out_bits_5_imag = _butterfly_outputs_T_129[32:17]; // @[FixedPointTypeClass.scala:30:68]
assign io_out_bits_6_real = _butterfly_outputs_T_132[32:17]; // @[FixedPointTypeClass.scala:20:58]
assign io_out_bits_6_imag = _butterfly_outputs_T_135[32:17]; // @[FixedPointTypeClass.scala:20:58]
assign io_out_bits_7_real = _butterfly_outputs_T_138[32:17]; // @[FixedPointTypeClass.scala:30:68]
assign io_out_bits_7_imag = _butterfly_outputs_T_141[32:17]; // @[FixedPointTypeClass.scala:30:68]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_22 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 2)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<4>(0h8))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<2>(0h2))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[9]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_31
connect _source_ok_WIRE[7], _source_ok_T_32
connect _source_ok_WIRE[8], _source_ok_T_33
node _source_ok_T_34 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[2])
node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[3])
node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[4])
node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[5])
node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[6])
node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[7])
node source_ok = or(_source_ok_T_40, _source_ok_WIRE[8])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_64 = shr(io.in.a.bits.source, 2)
node _T_65 = eq(_T_64, UInt<4>(0h8))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<2>(0h2))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_80 = cvt(_T_79)
node _T_81 = and(_T_80, asSInt(UInt<1>(0h0)))
node _T_82 = asSInt(_T_81)
node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0)))
node _T_84 = or(_T_78, _T_83)
node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_88 = cvt(_T_87)
node _T_89 = and(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = asSInt(_T_89)
node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0)))
node _T_92 = or(_T_86, _T_91)
node _T_93 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_94 = eq(_T_93, UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<1>(0h0)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = or(_T_94, _T_99)
node _T_101 = and(_T_11, _T_24)
node _T_102 = and(_T_101, _T_37)
node _T_103 = and(_T_102, _T_50)
node _T_104 = and(_T_103, _T_63)
node _T_105 = and(_T_104, _T_76)
node _T_106 = and(_T_105, _T_84)
node _T_107 = and(_T_106, _T_92)
node _T_108 = and(_T_107, _T_100)
node _T_109 = asUInt(reset)
node _T_110 = eq(_T_109, UInt<1>(0h0))
when _T_110 :
node _T_111 = eq(_T_108, UInt<1>(0h0))
when _T_111 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_108, UInt<1>(0h1), "") : assert_1
node _T_112 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_112 :
node _T_113 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_114 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_115 = and(_T_113, _T_114)
node _T_116 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_117 = shr(io.in.a.bits.source, 2)
node _T_118 = eq(_T_117, UInt<1>(0h0))
node _T_119 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_120 = and(_T_118, _T_119)
node _T_121 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_122 = and(_T_120, _T_121)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_123 = shr(io.in.a.bits.source, 2)
node _T_124 = eq(_T_123, UInt<1>(0h1))
node _T_125 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_126 = and(_T_124, _T_125)
node _T_127 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_128 = and(_T_126, _T_127)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_129 = shr(io.in.a.bits.source, 2)
node _T_130 = eq(_T_129, UInt<2>(0h2))
node _T_131 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_132 = and(_T_130, _T_131)
node _T_133 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_134 = and(_T_132, _T_133)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_135 = shr(io.in.a.bits.source, 2)
node _T_136 = eq(_T_135, UInt<2>(0h3))
node _T_137 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_138 = and(_T_136, _T_137)
node _T_139 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_140 = and(_T_138, _T_139)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_141 = shr(io.in.a.bits.source, 2)
node _T_142 = eq(_T_141, UInt<4>(0h8))
node _T_143 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_144 = and(_T_142, _T_143)
node _T_145 = leq(uncommonBits_9, UInt<2>(0h2))
node _T_146 = and(_T_144, _T_145)
node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_150 = or(_T_116, _T_122)
node _T_151 = or(_T_150, _T_128)
node _T_152 = or(_T_151, _T_134)
node _T_153 = or(_T_152, _T_140)
node _T_154 = or(_T_153, _T_146)
node _T_155 = or(_T_154, _T_147)
node _T_156 = or(_T_155, _T_148)
node _T_157 = or(_T_156, _T_149)
node _T_158 = and(_T_115, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_161 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_162 = cvt(_T_161)
node _T_163 = and(_T_162, asSInt(UInt<13>(0h1000)))
node _T_164 = asSInt(_T_163)
node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0)))
node _T_166 = and(_T_160, _T_165)
node _T_167 = or(UInt<1>(0h0), _T_166)
node _T_168 = and(_T_159, _T_167)
node _T_169 = asUInt(reset)
node _T_170 = eq(_T_169, UInt<1>(0h0))
when _T_170 :
node _T_171 = eq(_T_168, UInt<1>(0h0))
when _T_171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_168, UInt<1>(0h1), "") : assert_2
node _T_172 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_173 = shr(io.in.a.bits.source, 2)
node _T_174 = eq(_T_173, UInt<1>(0h0))
node _T_175 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_176 = and(_T_174, _T_175)
node _T_177 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_178 = and(_T_176, _T_177)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_179 = shr(io.in.a.bits.source, 2)
node _T_180 = eq(_T_179, UInt<1>(0h1))
node _T_181 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_182 = and(_T_180, _T_181)
node _T_183 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_184 = and(_T_182, _T_183)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_185 = shr(io.in.a.bits.source, 2)
node _T_186 = eq(_T_185, UInt<2>(0h2))
node _T_187 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_188 = and(_T_186, _T_187)
node _T_189 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_190 = and(_T_188, _T_189)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_191 = shr(io.in.a.bits.source, 2)
node _T_192 = eq(_T_191, UInt<2>(0h3))
node _T_193 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_194 = and(_T_192, _T_193)
node _T_195 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_196 = and(_T_194, _T_195)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_197 = shr(io.in.a.bits.source, 2)
node _T_198 = eq(_T_197, UInt<4>(0h8))
node _T_199 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_200 = and(_T_198, _T_199)
node _T_201 = leq(uncommonBits_14, UInt<2>(0h2))
node _T_202 = and(_T_200, _T_201)
node _T_203 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_204 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_205 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[9]
connect _WIRE[0], _T_172
connect _WIRE[1], _T_178
connect _WIRE[2], _T_184
connect _WIRE[3], _T_190
connect _WIRE[4], _T_196
connect _WIRE[5], _T_202
connect _WIRE[6], _T_203
connect _WIRE[7], _T_204
connect _WIRE[8], _T_205
node _T_206 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_207 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_208 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_209 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_210 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_211 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_212 = mux(_WIRE[5], _T_206, UInt<1>(0h0))
node _T_213 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_214 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_215 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_216 = or(_T_207, _T_208)
node _T_217 = or(_T_216, _T_209)
node _T_218 = or(_T_217, _T_210)
node _T_219 = or(_T_218, _T_211)
node _T_220 = or(_T_219, _T_212)
node _T_221 = or(_T_220, _T_213)
node _T_222 = or(_T_221, _T_214)
node _T_223 = or(_T_222, _T_215)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_223
node _T_224 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_225 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_226 = and(_T_224, _T_225)
node _T_227 = or(UInt<1>(0h0), _T_226)
node _T_228 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_229 = cvt(_T_228)
node _T_230 = and(_T_229, asSInt(UInt<13>(0h1000)))
node _T_231 = asSInt(_T_230)
node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0)))
node _T_233 = and(_T_227, _T_232)
node _T_234 = or(UInt<1>(0h0), _T_233)
node _T_235 = and(_WIRE_1, _T_234)
node _T_236 = asUInt(reset)
node _T_237 = eq(_T_236, UInt<1>(0h0))
when _T_237 :
node _T_238 = eq(_T_235, UInt<1>(0h0))
when _T_238 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_235, UInt<1>(0h1), "") : assert_3
node _T_239 = asUInt(reset)
node _T_240 = eq(_T_239, UInt<1>(0h0))
when _T_240 :
node _T_241 = eq(source_ok, UInt<1>(0h0))
when _T_241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_242 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_243 = asUInt(reset)
node _T_244 = eq(_T_243, UInt<1>(0h0))
when _T_244 :
node _T_245 = eq(_T_242, UInt<1>(0h0))
when _T_245 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_242, UInt<1>(0h1), "") : assert_5
node _T_246 = asUInt(reset)
node _T_247 = eq(_T_246, UInt<1>(0h0))
when _T_247 :
node _T_248 = eq(is_aligned, UInt<1>(0h0))
when _T_248 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_249 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_250 = asUInt(reset)
node _T_251 = eq(_T_250, UInt<1>(0h0))
when _T_251 :
node _T_252 = eq(_T_249, UInt<1>(0h0))
when _T_252 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_249, UInt<1>(0h1), "") : assert_7
node _T_253 = not(io.in.a.bits.mask)
node _T_254 = eq(_T_253, UInt<1>(0h0))
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_254, UInt<1>(0h1), "") : assert_8
node _T_258 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_259 = asUInt(reset)
node _T_260 = eq(_T_259, UInt<1>(0h0))
when _T_260 :
node _T_261 = eq(_T_258, UInt<1>(0h0))
when _T_261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_258, UInt<1>(0h1), "") : assert_9
node _T_262 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_262 :
node _T_263 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_264 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_265 = and(_T_263, _T_264)
node _T_266 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_267 = shr(io.in.a.bits.source, 2)
node _T_268 = eq(_T_267, UInt<1>(0h0))
node _T_269 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_270 = and(_T_268, _T_269)
node _T_271 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_272 = and(_T_270, _T_271)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_273 = shr(io.in.a.bits.source, 2)
node _T_274 = eq(_T_273, UInt<1>(0h1))
node _T_275 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_276 = and(_T_274, _T_275)
node _T_277 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_278 = and(_T_276, _T_277)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_279 = shr(io.in.a.bits.source, 2)
node _T_280 = eq(_T_279, UInt<2>(0h2))
node _T_281 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_282 = and(_T_280, _T_281)
node _T_283 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_284 = and(_T_282, _T_283)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_285 = shr(io.in.a.bits.source, 2)
node _T_286 = eq(_T_285, UInt<2>(0h3))
node _T_287 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_288 = and(_T_286, _T_287)
node _T_289 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_291 = shr(io.in.a.bits.source, 2)
node _T_292 = eq(_T_291, UInt<4>(0h8))
node _T_293 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_294 = and(_T_292, _T_293)
node _T_295 = leq(uncommonBits_19, UInt<2>(0h2))
node _T_296 = and(_T_294, _T_295)
node _T_297 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_298 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_299 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_300 = or(_T_266, _T_272)
node _T_301 = or(_T_300, _T_278)
node _T_302 = or(_T_301, _T_284)
node _T_303 = or(_T_302, _T_290)
node _T_304 = or(_T_303, _T_296)
node _T_305 = or(_T_304, _T_297)
node _T_306 = or(_T_305, _T_298)
node _T_307 = or(_T_306, _T_299)
node _T_308 = and(_T_265, _T_307)
node _T_309 = or(UInt<1>(0h0), _T_308)
node _T_310 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_311 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_312 = cvt(_T_311)
node _T_313 = and(_T_312, asSInt(UInt<13>(0h1000)))
node _T_314 = asSInt(_T_313)
node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0)))
node _T_316 = and(_T_310, _T_315)
node _T_317 = or(UInt<1>(0h0), _T_316)
node _T_318 = and(_T_309, _T_317)
node _T_319 = asUInt(reset)
node _T_320 = eq(_T_319, UInt<1>(0h0))
when _T_320 :
node _T_321 = eq(_T_318, UInt<1>(0h0))
when _T_321 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_318, UInt<1>(0h1), "") : assert_10
node _T_322 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_323 = shr(io.in.a.bits.source, 2)
node _T_324 = eq(_T_323, UInt<1>(0h0))
node _T_325 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_326 = and(_T_324, _T_325)
node _T_327 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_328 = and(_T_326, _T_327)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_329 = shr(io.in.a.bits.source, 2)
node _T_330 = eq(_T_329, UInt<1>(0h1))
node _T_331 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_332 = and(_T_330, _T_331)
node _T_333 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_335 = shr(io.in.a.bits.source, 2)
node _T_336 = eq(_T_335, UInt<2>(0h2))
node _T_337 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_338 = and(_T_336, _T_337)
node _T_339 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_340 = and(_T_338, _T_339)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_341 = shr(io.in.a.bits.source, 2)
node _T_342 = eq(_T_341, UInt<2>(0h3))
node _T_343 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_344 = and(_T_342, _T_343)
node _T_345 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_346 = and(_T_344, _T_345)
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_347 = shr(io.in.a.bits.source, 2)
node _T_348 = eq(_T_347, UInt<4>(0h8))
node _T_349 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_350 = and(_T_348, _T_349)
node _T_351 = leq(uncommonBits_24, UInt<2>(0h2))
node _T_352 = and(_T_350, _T_351)
node _T_353 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_354 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_355 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[9]
connect _WIRE_2[0], _T_322
connect _WIRE_2[1], _T_328
connect _WIRE_2[2], _T_334
connect _WIRE_2[3], _T_340
connect _WIRE_2[4], _T_346
connect _WIRE_2[5], _T_352
connect _WIRE_2[6], _T_353
connect _WIRE_2[7], _T_354
connect _WIRE_2[8], _T_355
node _T_356 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_357 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_358 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_359 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_360 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_361 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_362 = mux(_WIRE_2[5], _T_356, UInt<1>(0h0))
node _T_363 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_364 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_365 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_366 = or(_T_357, _T_358)
node _T_367 = or(_T_366, _T_359)
node _T_368 = or(_T_367, _T_360)
node _T_369 = or(_T_368, _T_361)
node _T_370 = or(_T_369, _T_362)
node _T_371 = or(_T_370, _T_363)
node _T_372 = or(_T_371, _T_364)
node _T_373 = or(_T_372, _T_365)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_373
node _T_374 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_375 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_376 = and(_T_374, _T_375)
node _T_377 = or(UInt<1>(0h0), _T_376)
node _T_378 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_379 = cvt(_T_378)
node _T_380 = and(_T_379, asSInt(UInt<13>(0h1000)))
node _T_381 = asSInt(_T_380)
node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0)))
node _T_383 = and(_T_377, _T_382)
node _T_384 = or(UInt<1>(0h0), _T_383)
node _T_385 = and(_WIRE_3, _T_384)
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_385, UInt<1>(0h1), "") : assert_11
node _T_389 = asUInt(reset)
node _T_390 = eq(_T_389, UInt<1>(0h0))
when _T_390 :
node _T_391 = eq(source_ok, UInt<1>(0h0))
when _T_391 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_392 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_393 = asUInt(reset)
node _T_394 = eq(_T_393, UInt<1>(0h0))
when _T_394 :
node _T_395 = eq(_T_392, UInt<1>(0h0))
when _T_395 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_392, UInt<1>(0h1), "") : assert_13
node _T_396 = asUInt(reset)
node _T_397 = eq(_T_396, UInt<1>(0h0))
when _T_397 :
node _T_398 = eq(is_aligned, UInt<1>(0h0))
when _T_398 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_399 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_400 = asUInt(reset)
node _T_401 = eq(_T_400, UInt<1>(0h0))
when _T_401 :
node _T_402 = eq(_T_399, UInt<1>(0h0))
when _T_402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_399, UInt<1>(0h1), "") : assert_15
node _T_403 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_404 = asUInt(reset)
node _T_405 = eq(_T_404, UInt<1>(0h0))
when _T_405 :
node _T_406 = eq(_T_403, UInt<1>(0h0))
when _T_406 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_403, UInt<1>(0h1), "") : assert_16
node _T_407 = not(io.in.a.bits.mask)
node _T_408 = eq(_T_407, UInt<1>(0h0))
node _T_409 = asUInt(reset)
node _T_410 = eq(_T_409, UInt<1>(0h0))
when _T_410 :
node _T_411 = eq(_T_408, UInt<1>(0h0))
when _T_411 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_408, UInt<1>(0h1), "") : assert_17
node _T_412 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_413 = asUInt(reset)
node _T_414 = eq(_T_413, UInt<1>(0h0))
when _T_414 :
node _T_415 = eq(_T_412, UInt<1>(0h0))
when _T_415 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_412, UInt<1>(0h1), "") : assert_18
node _T_416 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_416 :
node _T_417 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_418 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_419 = and(_T_417, _T_418)
node _T_420 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_421 = shr(io.in.a.bits.source, 2)
node _T_422 = eq(_T_421, UInt<1>(0h0))
node _T_423 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_424 = and(_T_422, _T_423)
node _T_425 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_426 = and(_T_424, _T_425)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_427 = shr(io.in.a.bits.source, 2)
node _T_428 = eq(_T_427, UInt<1>(0h1))
node _T_429 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_430 = and(_T_428, _T_429)
node _T_431 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_432 = and(_T_430, _T_431)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_433 = shr(io.in.a.bits.source, 2)
node _T_434 = eq(_T_433, UInt<2>(0h2))
node _T_435 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_436 = and(_T_434, _T_435)
node _T_437 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_438 = and(_T_436, _T_437)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_439 = shr(io.in.a.bits.source, 2)
node _T_440 = eq(_T_439, UInt<2>(0h3))
node _T_441 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_442 = and(_T_440, _T_441)
node _T_443 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_444 = and(_T_442, _T_443)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_445 = shr(io.in.a.bits.source, 2)
node _T_446 = eq(_T_445, UInt<4>(0h8))
node _T_447 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_448 = and(_T_446, _T_447)
node _T_449 = leq(uncommonBits_29, UInt<2>(0h2))
node _T_450 = and(_T_448, _T_449)
node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_453 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_454 = or(_T_420, _T_426)
node _T_455 = or(_T_454, _T_432)
node _T_456 = or(_T_455, _T_438)
node _T_457 = or(_T_456, _T_444)
node _T_458 = or(_T_457, _T_450)
node _T_459 = or(_T_458, _T_451)
node _T_460 = or(_T_459, _T_452)
node _T_461 = or(_T_460, _T_453)
node _T_462 = and(_T_419, _T_461)
node _T_463 = or(UInt<1>(0h0), _T_462)
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_463, UInt<1>(0h1), "") : assert_19
node _T_467 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_468 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_469 = and(_T_467, _T_468)
node _T_470 = or(UInt<1>(0h0), _T_469)
node _T_471 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_472 = cvt(_T_471)
node _T_473 = and(_T_472, asSInt(UInt<13>(0h1000)))
node _T_474 = asSInt(_T_473)
node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0)))
node _T_476 = and(_T_470, _T_475)
node _T_477 = or(UInt<1>(0h0), _T_476)
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_477, UInt<1>(0h1), "") : assert_20
node _T_481 = asUInt(reset)
node _T_482 = eq(_T_481, UInt<1>(0h0))
when _T_482 :
node _T_483 = eq(source_ok, UInt<1>(0h0))
when _T_483 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_484 = asUInt(reset)
node _T_485 = eq(_T_484, UInt<1>(0h0))
when _T_485 :
node _T_486 = eq(is_aligned, UInt<1>(0h0))
when _T_486 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_487 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_488 = asUInt(reset)
node _T_489 = eq(_T_488, UInt<1>(0h0))
when _T_489 :
node _T_490 = eq(_T_487, UInt<1>(0h0))
when _T_490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_487, UInt<1>(0h1), "") : assert_23
node _T_491 = eq(io.in.a.bits.mask, mask)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_491, UInt<1>(0h1), "") : assert_24
node _T_495 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_495, UInt<1>(0h1), "") : assert_25
node _T_499 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_499 :
node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_501 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_502 = and(_T_500, _T_501)
node _T_503 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_504 = shr(io.in.a.bits.source, 2)
node _T_505 = eq(_T_504, UInt<1>(0h0))
node _T_506 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_507 = and(_T_505, _T_506)
node _T_508 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_509 = and(_T_507, _T_508)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_510 = shr(io.in.a.bits.source, 2)
node _T_511 = eq(_T_510, UInt<1>(0h1))
node _T_512 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_513 = and(_T_511, _T_512)
node _T_514 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_515 = and(_T_513, _T_514)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_516 = shr(io.in.a.bits.source, 2)
node _T_517 = eq(_T_516, UInt<2>(0h2))
node _T_518 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_519 = and(_T_517, _T_518)
node _T_520 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_522 = shr(io.in.a.bits.source, 2)
node _T_523 = eq(_T_522, UInt<2>(0h3))
node _T_524 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_525 = and(_T_523, _T_524)
node _T_526 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_527 = and(_T_525, _T_526)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_528 = shr(io.in.a.bits.source, 2)
node _T_529 = eq(_T_528, UInt<4>(0h8))
node _T_530 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_531 = and(_T_529, _T_530)
node _T_532 = leq(uncommonBits_34, UInt<2>(0h2))
node _T_533 = and(_T_531, _T_532)
node _T_534 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_536 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_537 = or(_T_503, _T_509)
node _T_538 = or(_T_537, _T_515)
node _T_539 = or(_T_538, _T_521)
node _T_540 = or(_T_539, _T_527)
node _T_541 = or(_T_540, _T_533)
node _T_542 = or(_T_541, _T_534)
node _T_543 = or(_T_542, _T_535)
node _T_544 = or(_T_543, _T_536)
node _T_545 = and(_T_502, _T_544)
node _T_546 = or(UInt<1>(0h0), _T_545)
node _T_547 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_548 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_549 = and(_T_547, _T_548)
node _T_550 = or(UInt<1>(0h0), _T_549)
node _T_551 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_552 = cvt(_T_551)
node _T_553 = and(_T_552, asSInt(UInt<13>(0h1000)))
node _T_554 = asSInt(_T_553)
node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0)))
node _T_556 = and(_T_550, _T_555)
node _T_557 = or(UInt<1>(0h0), _T_556)
node _T_558 = and(_T_546, _T_557)
node _T_559 = asUInt(reset)
node _T_560 = eq(_T_559, UInt<1>(0h0))
when _T_560 :
node _T_561 = eq(_T_558, UInt<1>(0h0))
when _T_561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_558, UInt<1>(0h1), "") : assert_26
node _T_562 = asUInt(reset)
node _T_563 = eq(_T_562, UInt<1>(0h0))
when _T_563 :
node _T_564 = eq(source_ok, UInt<1>(0h0))
when _T_564 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_565 = asUInt(reset)
node _T_566 = eq(_T_565, UInt<1>(0h0))
when _T_566 :
node _T_567 = eq(is_aligned, UInt<1>(0h0))
when _T_567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_568 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_568, UInt<1>(0h1), "") : assert_29
node _T_572 = eq(io.in.a.bits.mask, mask)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_572, UInt<1>(0h1), "") : assert_30
node _T_576 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_576 :
node _T_577 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_578 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_579 = and(_T_577, _T_578)
node _T_580 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_581 = shr(io.in.a.bits.source, 2)
node _T_582 = eq(_T_581, UInt<1>(0h0))
node _T_583 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_584 = and(_T_582, _T_583)
node _T_585 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_586 = and(_T_584, _T_585)
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_587 = shr(io.in.a.bits.source, 2)
node _T_588 = eq(_T_587, UInt<1>(0h1))
node _T_589 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_590 = and(_T_588, _T_589)
node _T_591 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_592 = and(_T_590, _T_591)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_593 = shr(io.in.a.bits.source, 2)
node _T_594 = eq(_T_593, UInt<2>(0h2))
node _T_595 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_596 = and(_T_594, _T_595)
node _T_597 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_598 = and(_T_596, _T_597)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_599 = shr(io.in.a.bits.source, 2)
node _T_600 = eq(_T_599, UInt<2>(0h3))
node _T_601 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_602 = and(_T_600, _T_601)
node _T_603 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_604 = and(_T_602, _T_603)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_605 = shr(io.in.a.bits.source, 2)
node _T_606 = eq(_T_605, UInt<4>(0h8))
node _T_607 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_608 = and(_T_606, _T_607)
node _T_609 = leq(uncommonBits_39, UInt<2>(0h2))
node _T_610 = and(_T_608, _T_609)
node _T_611 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_612 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_613 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_614 = or(_T_580, _T_586)
node _T_615 = or(_T_614, _T_592)
node _T_616 = or(_T_615, _T_598)
node _T_617 = or(_T_616, _T_604)
node _T_618 = or(_T_617, _T_610)
node _T_619 = or(_T_618, _T_611)
node _T_620 = or(_T_619, _T_612)
node _T_621 = or(_T_620, _T_613)
node _T_622 = and(_T_579, _T_621)
node _T_623 = or(UInt<1>(0h0), _T_622)
node _T_624 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_625 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_626 = and(_T_624, _T_625)
node _T_627 = or(UInt<1>(0h0), _T_626)
node _T_628 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_629 = cvt(_T_628)
node _T_630 = and(_T_629, asSInt(UInt<13>(0h1000)))
node _T_631 = asSInt(_T_630)
node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0)))
node _T_633 = and(_T_627, _T_632)
node _T_634 = or(UInt<1>(0h0), _T_633)
node _T_635 = and(_T_623, _T_634)
node _T_636 = asUInt(reset)
node _T_637 = eq(_T_636, UInt<1>(0h0))
when _T_637 :
node _T_638 = eq(_T_635, UInt<1>(0h0))
when _T_638 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_635, UInt<1>(0h1), "") : assert_31
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(source_ok, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_642 = asUInt(reset)
node _T_643 = eq(_T_642, UInt<1>(0h0))
when _T_643 :
node _T_644 = eq(is_aligned, UInt<1>(0h0))
when _T_644 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_645 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_646 = asUInt(reset)
node _T_647 = eq(_T_646, UInt<1>(0h0))
when _T_647 :
node _T_648 = eq(_T_645, UInt<1>(0h0))
when _T_648 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_645, UInt<1>(0h1), "") : assert_34
node _T_649 = not(mask)
node _T_650 = and(io.in.a.bits.mask, _T_649)
node _T_651 = eq(_T_650, UInt<1>(0h0))
node _T_652 = asUInt(reset)
node _T_653 = eq(_T_652, UInt<1>(0h0))
when _T_653 :
node _T_654 = eq(_T_651, UInt<1>(0h0))
when _T_654 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_651, UInt<1>(0h1), "") : assert_35
node _T_655 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_655 :
node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_657 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_658 = and(_T_656, _T_657)
node _T_659 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_660 = shr(io.in.a.bits.source, 2)
node _T_661 = eq(_T_660, UInt<1>(0h0))
node _T_662 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_663 = and(_T_661, _T_662)
node _T_664 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_665 = and(_T_663, _T_664)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_666 = shr(io.in.a.bits.source, 2)
node _T_667 = eq(_T_666, UInt<1>(0h1))
node _T_668 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_669 = and(_T_667, _T_668)
node _T_670 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_671 = and(_T_669, _T_670)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_672 = shr(io.in.a.bits.source, 2)
node _T_673 = eq(_T_672, UInt<2>(0h2))
node _T_674 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_675 = and(_T_673, _T_674)
node _T_676 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_677 = and(_T_675, _T_676)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_678 = shr(io.in.a.bits.source, 2)
node _T_679 = eq(_T_678, UInt<2>(0h3))
node _T_680 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_681 = and(_T_679, _T_680)
node _T_682 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_683 = and(_T_681, _T_682)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_684 = shr(io.in.a.bits.source, 2)
node _T_685 = eq(_T_684, UInt<4>(0h8))
node _T_686 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_687 = and(_T_685, _T_686)
node _T_688 = leq(uncommonBits_44, UInt<2>(0h2))
node _T_689 = and(_T_687, _T_688)
node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_692 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_693 = or(_T_659, _T_665)
node _T_694 = or(_T_693, _T_671)
node _T_695 = or(_T_694, _T_677)
node _T_696 = or(_T_695, _T_683)
node _T_697 = or(_T_696, _T_689)
node _T_698 = or(_T_697, _T_690)
node _T_699 = or(_T_698, _T_691)
node _T_700 = or(_T_699, _T_692)
node _T_701 = and(_T_658, _T_700)
node _T_702 = or(UInt<1>(0h0), _T_701)
node _T_703 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_704 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_705 = cvt(_T_704)
node _T_706 = and(_T_705, asSInt(UInt<13>(0h1000)))
node _T_707 = asSInt(_T_706)
node _T_708 = eq(_T_707, asSInt(UInt<1>(0h0)))
node _T_709 = and(_T_703, _T_708)
node _T_710 = or(UInt<1>(0h0), _T_709)
node _T_711 = and(_T_702, _T_710)
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(_T_711, UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_711, UInt<1>(0h1), "") : assert_36
node _T_715 = asUInt(reset)
node _T_716 = eq(_T_715, UInt<1>(0h0))
when _T_716 :
node _T_717 = eq(source_ok, UInt<1>(0h0))
when _T_717 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_718 = asUInt(reset)
node _T_719 = eq(_T_718, UInt<1>(0h0))
when _T_719 :
node _T_720 = eq(is_aligned, UInt<1>(0h0))
when _T_720 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_721 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_722 = asUInt(reset)
node _T_723 = eq(_T_722, UInt<1>(0h0))
when _T_723 :
node _T_724 = eq(_T_721, UInt<1>(0h0))
when _T_724 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_721, UInt<1>(0h1), "") : assert_39
node _T_725 = eq(io.in.a.bits.mask, mask)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_725, UInt<1>(0h1), "") : assert_40
node _T_729 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_729 :
node _T_730 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_731 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_732 = and(_T_730, _T_731)
node _T_733 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_734 = shr(io.in.a.bits.source, 2)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_737 = and(_T_735, _T_736)
node _T_738 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_739 = and(_T_737, _T_738)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0)
node _T_740 = shr(io.in.a.bits.source, 2)
node _T_741 = eq(_T_740, UInt<1>(0h1))
node _T_742 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_743 = and(_T_741, _T_742)
node _T_744 = leq(uncommonBits_46, UInt<2>(0h3))
node _T_745 = and(_T_743, _T_744)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0)
node _T_746 = shr(io.in.a.bits.source, 2)
node _T_747 = eq(_T_746, UInt<2>(0h2))
node _T_748 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_749 = and(_T_747, _T_748)
node _T_750 = leq(uncommonBits_47, UInt<2>(0h3))
node _T_751 = and(_T_749, _T_750)
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_752 = shr(io.in.a.bits.source, 2)
node _T_753 = eq(_T_752, UInt<2>(0h3))
node _T_754 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_755 = and(_T_753, _T_754)
node _T_756 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_757 = and(_T_755, _T_756)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_758 = shr(io.in.a.bits.source, 2)
node _T_759 = eq(_T_758, UInt<4>(0h8))
node _T_760 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_761 = and(_T_759, _T_760)
node _T_762 = leq(uncommonBits_49, UInt<2>(0h2))
node _T_763 = and(_T_761, _T_762)
node _T_764 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_765 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_766 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_767 = or(_T_733, _T_739)
node _T_768 = or(_T_767, _T_745)
node _T_769 = or(_T_768, _T_751)
node _T_770 = or(_T_769, _T_757)
node _T_771 = or(_T_770, _T_763)
node _T_772 = or(_T_771, _T_764)
node _T_773 = or(_T_772, _T_765)
node _T_774 = or(_T_773, _T_766)
node _T_775 = and(_T_732, _T_774)
node _T_776 = or(UInt<1>(0h0), _T_775)
node _T_777 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_778 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_779 = cvt(_T_778)
node _T_780 = and(_T_779, asSInt(UInt<13>(0h1000)))
node _T_781 = asSInt(_T_780)
node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0)))
node _T_783 = and(_T_777, _T_782)
node _T_784 = or(UInt<1>(0h0), _T_783)
node _T_785 = and(_T_776, _T_784)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_785, UInt<1>(0h1), "") : assert_41
node _T_789 = asUInt(reset)
node _T_790 = eq(_T_789, UInt<1>(0h0))
when _T_790 :
node _T_791 = eq(source_ok, UInt<1>(0h0))
when _T_791 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_792 = asUInt(reset)
node _T_793 = eq(_T_792, UInt<1>(0h0))
when _T_793 :
node _T_794 = eq(is_aligned, UInt<1>(0h0))
when _T_794 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_795 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_796 = asUInt(reset)
node _T_797 = eq(_T_796, UInt<1>(0h0))
when _T_797 :
node _T_798 = eq(_T_795, UInt<1>(0h0))
when _T_798 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_795, UInt<1>(0h1), "") : assert_44
node _T_799 = eq(io.in.a.bits.mask, mask)
node _T_800 = asUInt(reset)
node _T_801 = eq(_T_800, UInt<1>(0h0))
when _T_801 :
node _T_802 = eq(_T_799, UInt<1>(0h0))
when _T_802 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_799, UInt<1>(0h1), "") : assert_45
node _T_803 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_803 :
node _T_804 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_805 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_806 = and(_T_804, _T_805)
node _T_807 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_808 = shr(io.in.a.bits.source, 2)
node _T_809 = eq(_T_808, UInt<1>(0h0))
node _T_810 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_811 = and(_T_809, _T_810)
node _T_812 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_813 = and(_T_811, _T_812)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_814 = shr(io.in.a.bits.source, 2)
node _T_815 = eq(_T_814, UInt<1>(0h1))
node _T_816 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_817 = and(_T_815, _T_816)
node _T_818 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_819 = and(_T_817, _T_818)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0)
node _T_820 = shr(io.in.a.bits.source, 2)
node _T_821 = eq(_T_820, UInt<2>(0h2))
node _T_822 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_823 = and(_T_821, _T_822)
node _T_824 = leq(uncommonBits_52, UInt<2>(0h3))
node _T_825 = and(_T_823, _T_824)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0)
node _T_826 = shr(io.in.a.bits.source, 2)
node _T_827 = eq(_T_826, UInt<2>(0h3))
node _T_828 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_829 = and(_T_827, _T_828)
node _T_830 = leq(uncommonBits_53, UInt<2>(0h3))
node _T_831 = and(_T_829, _T_830)
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0)
node _T_832 = shr(io.in.a.bits.source, 2)
node _T_833 = eq(_T_832, UInt<4>(0h8))
node _T_834 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_835 = and(_T_833, _T_834)
node _T_836 = leq(uncommonBits_54, UInt<2>(0h2))
node _T_837 = and(_T_835, _T_836)
node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_839 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_840 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_841 = or(_T_807, _T_813)
node _T_842 = or(_T_841, _T_819)
node _T_843 = or(_T_842, _T_825)
node _T_844 = or(_T_843, _T_831)
node _T_845 = or(_T_844, _T_837)
node _T_846 = or(_T_845, _T_838)
node _T_847 = or(_T_846, _T_839)
node _T_848 = or(_T_847, _T_840)
node _T_849 = and(_T_806, _T_848)
node _T_850 = or(UInt<1>(0h0), _T_849)
node _T_851 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_852 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_853 = cvt(_T_852)
node _T_854 = and(_T_853, asSInt(UInt<13>(0h1000)))
node _T_855 = asSInt(_T_854)
node _T_856 = eq(_T_855, asSInt(UInt<1>(0h0)))
node _T_857 = and(_T_851, _T_856)
node _T_858 = or(UInt<1>(0h0), _T_857)
node _T_859 = and(_T_850, _T_858)
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(_T_859, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_859, UInt<1>(0h1), "") : assert_46
node _T_863 = asUInt(reset)
node _T_864 = eq(_T_863, UInt<1>(0h0))
when _T_864 :
node _T_865 = eq(source_ok, UInt<1>(0h0))
when _T_865 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_866 = asUInt(reset)
node _T_867 = eq(_T_866, UInt<1>(0h0))
when _T_867 :
node _T_868 = eq(is_aligned, UInt<1>(0h0))
when _T_868 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_869 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_869, UInt<1>(0h1), "") : assert_49
node _T_873 = eq(io.in.a.bits.mask, mask)
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(_T_873, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_873, UInt<1>(0h1), "") : assert_50
node _T_877 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_878 = asUInt(reset)
node _T_879 = eq(_T_878, UInt<1>(0h0))
when _T_879 :
node _T_880 = eq(_T_877, UInt<1>(0h0))
when _T_880 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_877, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_881 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_882 = asUInt(reset)
node _T_883 = eq(_T_882, UInt<1>(0h0))
when _T_883 :
node _T_884 = eq(_T_881, UInt<1>(0h0))
when _T_884 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_881, UInt<1>(0h1), "") : assert_52
node _source_ok_T_41 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_42 = shr(io.in.d.bits.source, 2)
node _source_ok_T_43 = eq(_source_ok_T_42, UInt<1>(0h0))
node _source_ok_T_44 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44)
node _source_ok_T_46 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_48 = shr(io.in.d.bits.source, 2)
node _source_ok_T_49 = eq(_source_ok_T_48, UInt<1>(0h1))
node _source_ok_T_50 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50)
node _source_ok_T_52 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_53 = and(_source_ok_T_51, _source_ok_T_52)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_54 = shr(io.in.d.bits.source, 2)
node _source_ok_T_55 = eq(_source_ok_T_54, UInt<2>(0h2))
node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56)
node _source_ok_T_58 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_60 = shr(io.in.d.bits.source, 2)
node _source_ok_T_61 = eq(_source_ok_T_60, UInt<2>(0h3))
node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62)
node _source_ok_T_64 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_66 = shr(io.in.d.bits.source, 2)
node _source_ok_T_67 = eq(_source_ok_T_66, UInt<4>(0h8))
node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68)
node _source_ok_T_70 = leq(source_ok_uncommonBits_9, UInt<2>(0h2))
node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70)
node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h23))
node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<6>(0h24))
node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[9]
connect _source_ok_WIRE_1[0], _source_ok_T_41
connect _source_ok_WIRE_1[1], _source_ok_T_47
connect _source_ok_WIRE_1[2], _source_ok_T_53
connect _source_ok_WIRE_1[3], _source_ok_T_59
connect _source_ok_WIRE_1[4], _source_ok_T_65
connect _source_ok_WIRE_1[5], _source_ok_T_71
connect _source_ok_WIRE_1[6], _source_ok_T_72
connect _source_ok_WIRE_1[7], _source_ok_T_73
connect _source_ok_WIRE_1[8], _source_ok_T_74
node _source_ok_T_75 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[2])
node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[3])
node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[4])
node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[5])
node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[6])
node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[7])
node source_ok_1 = or(_source_ok_T_81, _source_ok_WIRE_1[8])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_885 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_885 :
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(source_ok_1, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_889 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_890 = asUInt(reset)
node _T_891 = eq(_T_890, UInt<1>(0h0))
when _T_891 :
node _T_892 = eq(_T_889, UInt<1>(0h0))
when _T_892 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_889, UInt<1>(0h1), "") : assert_54
node _T_893 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_894 = asUInt(reset)
node _T_895 = eq(_T_894, UInt<1>(0h0))
when _T_895 :
node _T_896 = eq(_T_893, UInt<1>(0h0))
when _T_896 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_893, UInt<1>(0h1), "") : assert_55
node _T_897 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_898 = asUInt(reset)
node _T_899 = eq(_T_898, UInt<1>(0h0))
when _T_899 :
node _T_900 = eq(_T_897, UInt<1>(0h0))
when _T_900 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_897, UInt<1>(0h1), "") : assert_56
node _T_901 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_902 = asUInt(reset)
node _T_903 = eq(_T_902, UInt<1>(0h0))
when _T_903 :
node _T_904 = eq(_T_901, UInt<1>(0h0))
when _T_904 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_901, UInt<1>(0h1), "") : assert_57
node _T_905 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_905 :
node _T_906 = asUInt(reset)
node _T_907 = eq(_T_906, UInt<1>(0h0))
when _T_907 :
node _T_908 = eq(source_ok_1, UInt<1>(0h0))
when _T_908 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_909 = asUInt(reset)
node _T_910 = eq(_T_909, UInt<1>(0h0))
when _T_910 :
node _T_911 = eq(sink_ok, UInt<1>(0h0))
when _T_911 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_912 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_913 = asUInt(reset)
node _T_914 = eq(_T_913, UInt<1>(0h0))
when _T_914 :
node _T_915 = eq(_T_912, UInt<1>(0h0))
when _T_915 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_912, UInt<1>(0h1), "") : assert_60
node _T_916 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_917 = asUInt(reset)
node _T_918 = eq(_T_917, UInt<1>(0h0))
when _T_918 :
node _T_919 = eq(_T_916, UInt<1>(0h0))
when _T_919 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_916, UInt<1>(0h1), "") : assert_61
node _T_920 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_921 = asUInt(reset)
node _T_922 = eq(_T_921, UInt<1>(0h0))
when _T_922 :
node _T_923 = eq(_T_920, UInt<1>(0h0))
when _T_923 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_920, UInt<1>(0h1), "") : assert_62
node _T_924 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_925 = asUInt(reset)
node _T_926 = eq(_T_925, UInt<1>(0h0))
when _T_926 :
node _T_927 = eq(_T_924, UInt<1>(0h0))
when _T_927 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_924, UInt<1>(0h1), "") : assert_63
node _T_928 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_929 = or(UInt<1>(0h0), _T_928)
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_929, UInt<1>(0h1), "") : assert_64
node _T_933 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_933 :
node _T_934 = asUInt(reset)
node _T_935 = eq(_T_934, UInt<1>(0h0))
when _T_935 :
node _T_936 = eq(source_ok_1, UInt<1>(0h0))
when _T_936 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_937 = asUInt(reset)
node _T_938 = eq(_T_937, UInt<1>(0h0))
when _T_938 :
node _T_939 = eq(sink_ok, UInt<1>(0h0))
when _T_939 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_940 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_941 = asUInt(reset)
node _T_942 = eq(_T_941, UInt<1>(0h0))
when _T_942 :
node _T_943 = eq(_T_940, UInt<1>(0h0))
when _T_943 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_940, UInt<1>(0h1), "") : assert_67
node _T_944 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_945 = asUInt(reset)
node _T_946 = eq(_T_945, UInt<1>(0h0))
when _T_946 :
node _T_947 = eq(_T_944, UInt<1>(0h0))
when _T_947 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_944, UInt<1>(0h1), "") : assert_68
node _T_948 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_949 = asUInt(reset)
node _T_950 = eq(_T_949, UInt<1>(0h0))
when _T_950 :
node _T_951 = eq(_T_948, UInt<1>(0h0))
when _T_951 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_948, UInt<1>(0h1), "") : assert_69
node _T_952 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_953 = or(_T_952, io.in.d.bits.corrupt)
node _T_954 = asUInt(reset)
node _T_955 = eq(_T_954, UInt<1>(0h0))
when _T_955 :
node _T_956 = eq(_T_953, UInt<1>(0h0))
when _T_956 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_953, UInt<1>(0h1), "") : assert_70
node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_958 = or(UInt<1>(0h0), _T_957)
node _T_959 = asUInt(reset)
node _T_960 = eq(_T_959, UInt<1>(0h0))
when _T_960 :
node _T_961 = eq(_T_958, UInt<1>(0h0))
when _T_961 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_958, UInt<1>(0h1), "") : assert_71
node _T_962 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_962 :
node _T_963 = asUInt(reset)
node _T_964 = eq(_T_963, UInt<1>(0h0))
when _T_964 :
node _T_965 = eq(source_ok_1, UInt<1>(0h0))
when _T_965 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_966 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_967 = asUInt(reset)
node _T_968 = eq(_T_967, UInt<1>(0h0))
when _T_968 :
node _T_969 = eq(_T_966, UInt<1>(0h0))
when _T_969 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_966, UInt<1>(0h1), "") : assert_73
node _T_970 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_971 = asUInt(reset)
node _T_972 = eq(_T_971, UInt<1>(0h0))
when _T_972 :
node _T_973 = eq(_T_970, UInt<1>(0h0))
when _T_973 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_970, UInt<1>(0h1), "") : assert_74
node _T_974 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_975 = or(UInt<1>(0h0), _T_974)
node _T_976 = asUInt(reset)
node _T_977 = eq(_T_976, UInt<1>(0h0))
when _T_977 :
node _T_978 = eq(_T_975, UInt<1>(0h0))
when _T_978 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_975, UInt<1>(0h1), "") : assert_75
node _T_979 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_979 :
node _T_980 = asUInt(reset)
node _T_981 = eq(_T_980, UInt<1>(0h0))
when _T_981 :
node _T_982 = eq(source_ok_1, UInt<1>(0h0))
when _T_982 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_983 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_984 = asUInt(reset)
node _T_985 = eq(_T_984, UInt<1>(0h0))
when _T_985 :
node _T_986 = eq(_T_983, UInt<1>(0h0))
when _T_986 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_983, UInt<1>(0h1), "") : assert_77
node _T_987 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_988 = or(_T_987, io.in.d.bits.corrupt)
node _T_989 = asUInt(reset)
node _T_990 = eq(_T_989, UInt<1>(0h0))
when _T_990 :
node _T_991 = eq(_T_988, UInt<1>(0h0))
when _T_991 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_988, UInt<1>(0h1), "") : assert_78
node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_993 = or(UInt<1>(0h0), _T_992)
node _T_994 = asUInt(reset)
node _T_995 = eq(_T_994, UInt<1>(0h0))
when _T_995 :
node _T_996 = eq(_T_993, UInt<1>(0h0))
when _T_996 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_993, UInt<1>(0h1), "") : assert_79
node _T_997 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_997 :
node _T_998 = asUInt(reset)
node _T_999 = eq(_T_998, UInt<1>(0h0))
when _T_999 :
node _T_1000 = eq(source_ok_1, UInt<1>(0h0))
when _T_1000 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1001 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1002 = asUInt(reset)
node _T_1003 = eq(_T_1002, UInt<1>(0h0))
when _T_1003 :
node _T_1004 = eq(_T_1001, UInt<1>(0h0))
when _T_1004 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1001, UInt<1>(0h1), "") : assert_81
node _T_1005 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1006 = asUInt(reset)
node _T_1007 = eq(_T_1006, UInt<1>(0h0))
when _T_1007 :
node _T_1008 = eq(_T_1005, UInt<1>(0h0))
when _T_1008 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1005, UInt<1>(0h1), "") : assert_82
node _T_1009 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1010 = or(UInt<1>(0h0), _T_1009)
node _T_1011 = asUInt(reset)
node _T_1012 = eq(_T_1011, UInt<1>(0h0))
when _T_1012 :
node _T_1013 = eq(_T_1010, UInt<1>(0h0))
when _T_1013 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1010, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<26>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1014 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1015 = asUInt(reset)
node _T_1016 = eq(_T_1015, UInt<1>(0h0))
when _T_1016 :
node _T_1017 = eq(_T_1014, UInt<1>(0h0))
when _T_1017 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1014, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<26>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1018 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1019 = asUInt(reset)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
node _T_1021 = eq(_T_1018, UInt<1>(0h0))
when _T_1021 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1018, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1022 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1023 = asUInt(reset)
node _T_1024 = eq(_T_1023, UInt<1>(0h0))
when _T_1024 :
node _T_1025 = eq(_T_1022, UInt<1>(0h0))
when _T_1025 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1022, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1026 = eq(a_first, UInt<1>(0h0))
node _T_1027 = and(io.in.a.valid, _T_1026)
when _T_1027 :
node _T_1028 = eq(io.in.a.bits.opcode, opcode)
node _T_1029 = asUInt(reset)
node _T_1030 = eq(_T_1029, UInt<1>(0h0))
when _T_1030 :
node _T_1031 = eq(_T_1028, UInt<1>(0h0))
when _T_1031 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1028, UInt<1>(0h1), "") : assert_87
node _T_1032 = eq(io.in.a.bits.param, param)
node _T_1033 = asUInt(reset)
node _T_1034 = eq(_T_1033, UInt<1>(0h0))
when _T_1034 :
node _T_1035 = eq(_T_1032, UInt<1>(0h0))
when _T_1035 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1032, UInt<1>(0h1), "") : assert_88
node _T_1036 = eq(io.in.a.bits.size, size)
node _T_1037 = asUInt(reset)
node _T_1038 = eq(_T_1037, UInt<1>(0h0))
when _T_1038 :
node _T_1039 = eq(_T_1036, UInt<1>(0h0))
when _T_1039 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1036, UInt<1>(0h1), "") : assert_89
node _T_1040 = eq(io.in.a.bits.source, source)
node _T_1041 = asUInt(reset)
node _T_1042 = eq(_T_1041, UInt<1>(0h0))
when _T_1042 :
node _T_1043 = eq(_T_1040, UInt<1>(0h0))
when _T_1043 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1040, UInt<1>(0h1), "") : assert_90
node _T_1044 = eq(io.in.a.bits.address, address)
node _T_1045 = asUInt(reset)
node _T_1046 = eq(_T_1045, UInt<1>(0h0))
when _T_1046 :
node _T_1047 = eq(_T_1044, UInt<1>(0h0))
when _T_1047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1044, UInt<1>(0h1), "") : assert_91
node _T_1048 = and(io.in.a.ready, io.in.a.valid)
node _T_1049 = and(_T_1048, a_first)
when _T_1049 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1050 = eq(d_first, UInt<1>(0h0))
node _T_1051 = and(io.in.d.valid, _T_1050)
when _T_1051 :
node _T_1052 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1053 = asUInt(reset)
node _T_1054 = eq(_T_1053, UInt<1>(0h0))
when _T_1054 :
node _T_1055 = eq(_T_1052, UInt<1>(0h0))
when _T_1055 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1052, UInt<1>(0h1), "") : assert_92
node _T_1056 = eq(io.in.d.bits.param, param_1)
node _T_1057 = asUInt(reset)
node _T_1058 = eq(_T_1057, UInt<1>(0h0))
when _T_1058 :
node _T_1059 = eq(_T_1056, UInt<1>(0h0))
when _T_1059 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1056, UInt<1>(0h1), "") : assert_93
node _T_1060 = eq(io.in.d.bits.size, size_1)
node _T_1061 = asUInt(reset)
node _T_1062 = eq(_T_1061, UInt<1>(0h0))
when _T_1062 :
node _T_1063 = eq(_T_1060, UInt<1>(0h0))
when _T_1063 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1060, UInt<1>(0h1), "") : assert_94
node _T_1064 = eq(io.in.d.bits.source, source_1)
node _T_1065 = asUInt(reset)
node _T_1066 = eq(_T_1065, UInt<1>(0h0))
when _T_1066 :
node _T_1067 = eq(_T_1064, UInt<1>(0h0))
when _T_1067 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1064, UInt<1>(0h1), "") : assert_95
node _T_1068 = eq(io.in.d.bits.sink, sink)
node _T_1069 = asUInt(reset)
node _T_1070 = eq(_T_1069, UInt<1>(0h0))
when _T_1070 :
node _T_1071 = eq(_T_1068, UInt<1>(0h0))
when _T_1071 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1068, UInt<1>(0h1), "") : assert_96
node _T_1072 = eq(io.in.d.bits.denied, denied)
node _T_1073 = asUInt(reset)
node _T_1074 = eq(_T_1073, UInt<1>(0h0))
when _T_1074 :
node _T_1075 = eq(_T_1072, UInt<1>(0h0))
when _T_1075 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1072, UInt<1>(0h1), "") : assert_97
node _T_1076 = and(io.in.d.ready, io.in.d.valid)
node _T_1077 = and(_T_1076, d_first)
when _T_1077 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1078 = and(io.in.a.valid, a_first_1)
node _T_1079 = and(_T_1078, UInt<1>(0h1))
when _T_1079 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1080 = and(io.in.a.ready, io.in.a.valid)
node _T_1081 = and(_T_1080, a_first_1)
node _T_1082 = and(_T_1081, UInt<1>(0h1))
when _T_1082 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1083 = dshr(inflight, io.in.a.bits.source)
node _T_1084 = bits(_T_1083, 0, 0)
node _T_1085 = eq(_T_1084, UInt<1>(0h0))
node _T_1086 = asUInt(reset)
node _T_1087 = eq(_T_1086, UInt<1>(0h0))
when _T_1087 :
node _T_1088 = eq(_T_1085, UInt<1>(0h0))
when _T_1088 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1085, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1089 = and(io.in.d.valid, d_first_1)
node _T_1090 = and(_T_1089, UInt<1>(0h1))
node _T_1091 = eq(d_release_ack, UInt<1>(0h0))
node _T_1092 = and(_T_1090, _T_1091)
when _T_1092 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1093 = and(io.in.d.ready, io.in.d.valid)
node _T_1094 = and(_T_1093, d_first_1)
node _T_1095 = and(_T_1094, UInt<1>(0h1))
node _T_1096 = eq(d_release_ack, UInt<1>(0h0))
node _T_1097 = and(_T_1095, _T_1096)
when _T_1097 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1098 = and(io.in.d.valid, d_first_1)
node _T_1099 = and(_T_1098, UInt<1>(0h1))
node _T_1100 = eq(d_release_ack, UInt<1>(0h0))
node _T_1101 = and(_T_1099, _T_1100)
when _T_1101 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1102 = dshr(inflight, io.in.d.bits.source)
node _T_1103 = bits(_T_1102, 0, 0)
node _T_1104 = or(_T_1103, same_cycle_resp)
node _T_1105 = asUInt(reset)
node _T_1106 = eq(_T_1105, UInt<1>(0h0))
when _T_1106 :
node _T_1107 = eq(_T_1104, UInt<1>(0h0))
when _T_1107 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1104, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1108 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1109 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1110 = or(_T_1108, _T_1109)
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(_T_1110, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1110, UInt<1>(0h1), "") : assert_100
node _T_1114 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(_T_1114, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1114, UInt<1>(0h1), "") : assert_101
else :
node _T_1118 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1119 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1120 = or(_T_1118, _T_1119)
node _T_1121 = asUInt(reset)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = eq(_T_1120, UInt<1>(0h0))
when _T_1123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1120, UInt<1>(0h1), "") : assert_102
node _T_1124 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1125 = asUInt(reset)
node _T_1126 = eq(_T_1125, UInt<1>(0h0))
when _T_1126 :
node _T_1127 = eq(_T_1124, UInt<1>(0h0))
when _T_1127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1124, UInt<1>(0h1), "") : assert_103
node _T_1128 = and(io.in.d.valid, d_first_1)
node _T_1129 = and(_T_1128, a_first_1)
node _T_1130 = and(_T_1129, io.in.a.valid)
node _T_1131 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1132 = and(_T_1130, _T_1131)
node _T_1133 = eq(d_release_ack, UInt<1>(0h0))
node _T_1134 = and(_T_1132, _T_1133)
when _T_1134 :
node _T_1135 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1136 = or(_T_1135, io.in.a.ready)
node _T_1137 = asUInt(reset)
node _T_1138 = eq(_T_1137, UInt<1>(0h0))
when _T_1138 :
node _T_1139 = eq(_T_1136, UInt<1>(0h0))
when _T_1139 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1136, UInt<1>(0h1), "") : assert_104
node _T_1140 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1141 = orr(a_set_wo_ready)
node _T_1142 = eq(_T_1141, UInt<1>(0h0))
node _T_1143 = or(_T_1140, _T_1142)
node _T_1144 = asUInt(reset)
node _T_1145 = eq(_T_1144, UInt<1>(0h0))
when _T_1145 :
node _T_1146 = eq(_T_1143, UInt<1>(0h0))
when _T_1146 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1143, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_44
node _T_1147 = orr(inflight)
node _T_1148 = eq(_T_1147, UInt<1>(0h0))
node _T_1149 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1150 = or(_T_1148, _T_1149)
node _T_1151 = lt(watchdog, plusarg_reader.out)
node _T_1152 = or(_T_1150, _T_1151)
node _T_1153 = asUInt(reset)
node _T_1154 = eq(_T_1153, UInt<1>(0h0))
when _T_1154 :
node _T_1155 = eq(_T_1152, UInt<1>(0h0))
when _T_1155 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1152, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1156 = and(io.in.a.ready, io.in.a.valid)
node _T_1157 = and(io.in.d.ready, io.in.d.valid)
node _T_1158 = or(_T_1156, _T_1157)
when _T_1158 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<26>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<26>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<26>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1159 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<26>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1160 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1161 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1162 = and(_T_1160, _T_1161)
node _T_1163 = and(_T_1159, _T_1162)
when _T_1163 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<26>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1164 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1165 = and(_T_1164, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<26>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1166 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1167 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1168 = and(_T_1166, _T_1167)
node _T_1169 = and(_T_1165, _T_1168)
when _T_1169 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<26>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1170 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1171 = bits(_T_1170, 0, 0)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
node _T_1173 = asUInt(reset)
node _T_1174 = eq(_T_1173, UInt<1>(0h0))
when _T_1174 :
node _T_1175 = eq(_T_1172, UInt<1>(0h0))
when _T_1175 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1172, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1176 = and(io.in.d.valid, d_first_2)
node _T_1177 = and(_T_1176, UInt<1>(0h1))
node _T_1178 = and(_T_1177, d_release_ack_1)
when _T_1178 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1179 = and(io.in.d.ready, io.in.d.valid)
node _T_1180 = and(_T_1179, d_first_2)
node _T_1181 = and(_T_1180, UInt<1>(0h1))
node _T_1182 = and(_T_1181, d_release_ack_1)
when _T_1182 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1183 = and(io.in.d.valid, d_first_2)
node _T_1184 = and(_T_1183, UInt<1>(0h1))
node _T_1185 = and(_T_1184, d_release_ack_1)
when _T_1185 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1186 = dshr(inflight_1, io.in.d.bits.source)
node _T_1187 = bits(_T_1186, 0, 0)
node _T_1188 = or(_T_1187, same_cycle_resp_1)
node _T_1189 = asUInt(reset)
node _T_1190 = eq(_T_1189, UInt<1>(0h0))
when _T_1190 :
node _T_1191 = eq(_T_1188, UInt<1>(0h0))
when _T_1191 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1188, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<26>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1192 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1193 = asUInt(reset)
node _T_1194 = eq(_T_1193, UInt<1>(0h0))
when _T_1194 :
node _T_1195 = eq(_T_1192, UInt<1>(0h0))
when _T_1195 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1192, UInt<1>(0h1), "") : assert_109
else :
node _T_1196 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1197 = asUInt(reset)
node _T_1198 = eq(_T_1197, UInt<1>(0h0))
when _T_1198 :
node _T_1199 = eq(_T_1196, UInt<1>(0h0))
when _T_1199 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1196, UInt<1>(0h1), "") : assert_110
node _T_1200 = and(io.in.d.valid, d_first_2)
node _T_1201 = and(_T_1200, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<26>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1202 = and(_T_1201, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<26>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1203 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1204 = and(_T_1202, _T_1203)
node _T_1205 = and(_T_1204, d_release_ack_1)
node _T_1206 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1207 = and(_T_1205, _T_1206)
when _T_1207 :
node _T_1208 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<26>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1209 = or(_T_1208, _WIRE_27.ready)
node _T_1210 = asUInt(reset)
node _T_1211 = eq(_T_1210, UInt<1>(0h0))
when _T_1211 :
node _T_1212 = eq(_T_1209, UInt<1>(0h0))
when _T_1212 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1209, UInt<1>(0h1), "") : assert_111
node _T_1213 = orr(c_set_wo_ready)
when _T_1213 :
node _T_1214 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1215 = asUInt(reset)
node _T_1216 = eq(_T_1215, UInt<1>(0h0))
when _T_1216 :
node _T_1217 = eq(_T_1214, UInt<1>(0h0))
when _T_1217 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1214, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_45
node _T_1218 = orr(inflight_1)
node _T_1219 = eq(_T_1218, UInt<1>(0h0))
node _T_1220 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1221 = or(_T_1219, _T_1220)
node _T_1222 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1223 = or(_T_1221, _T_1222)
node _T_1224 = asUInt(reset)
node _T_1225 = eq(_T_1224, UInt<1>(0h0))
when _T_1225 :
node _T_1226 = eq(_T_1223, UInt<1>(0h0))
when _T_1226 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1223, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<26>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1227 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1228 = and(io.in.d.ready, io.in.d.valid)
node _T_1229 = or(_T_1227, _T_1228)
when _T_1229 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_22( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_26 = _source_ok_T_25 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_29 = source_ok_uncommonBits_4 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h23; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31]
wire _source_ok_T_34 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_40 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [25:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_66 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_67 = _source_ok_T_66 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_70 = source_ok_uncommonBits_9 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31]
wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h23; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31]
wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31]
wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire _source_ok_T_75 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_81 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1156 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1156; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1156; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [25:0] address; // @[Monitor.scala:391:22]
wire _T_1229 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1229; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1229; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1229; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1082 = _T_1156 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1082 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1082 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1082 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1082 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1082 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1128 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1128 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1097 = _T_1229 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1097 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1097 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1097 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1200 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1200 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1182 = _T_1229 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1182 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1182 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1182 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLAToNoC_8 :
input clock : Clock
input reset : Reset
output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
inst q of Queue1_TLBundleA_a32d64s6k5z4c_8
connect q.clock, clock
connect q.reset, reset
wire has_body : UInt<1>
node _head_T = and(q.io.deq.ready, q.io.deq.valid)
node _head_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size)
node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 11, 0)
node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1)
node head_beats1_decode = shr(_head_beats1_decode_T_2, 3)
node _head_beats1_opdata_T = bits(q.io.deq.bits.opcode, 2, 2)
node head_beats1_opdata = eq(_head_beats1_opdata_T, UInt<1>(0h0))
node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0))
regreset head_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _head_counter1_T = sub(head_counter, UInt<1>(0h1))
node head_counter1 = tail(_head_counter1_T, 1)
node head = eq(head_counter, UInt<1>(0h0))
node _head_last_T = eq(head_counter, UInt<1>(0h1))
node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0))
node head_last = or(_head_last_T, _head_last_T_1)
node head_done = and(head_last, _head_T)
node _head_count_T = not(head_counter1)
node head_count = and(head_beats1, _head_count_T)
when _head_T :
node _head_counter_T = mux(head, head_beats1, head_counter1)
connect head_counter, _head_counter_T
node _tail_T = and(q.io.deq.ready, q.io.deq.valid)
node _tail_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size)
node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 11, 0)
node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1)
node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 3)
node _tail_beats1_opdata_T = bits(q.io.deq.bits.opcode, 2, 2)
node tail_beats1_opdata = eq(_tail_beats1_opdata_T, UInt<1>(0h0))
node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0))
regreset tail_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1))
node tail_counter1 = tail(_tail_counter1_T, 1)
node tail_first = eq(tail_counter, UInt<1>(0h0))
node _tail_last_T = eq(tail_counter, UInt<1>(0h1))
node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0))
node tail = or(_tail_last_T, _tail_last_T_1)
node tail_done = and(tail, _tail_T)
node _tail_count_T = not(tail_counter1)
node tail_count = and(tail_beats1, _tail_count_T)
when _tail_T :
node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1)
connect tail_counter, _tail_counter_T
node body_hi = cat(q.io.deq.bits.mask, q.io.deq.bits.data)
node body = cat(body_hi, q.io.deq.bits.corrupt)
node const_lo = cat(q.io.deq.bits.source, q.io.deq.bits.address)
node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param)
node const_hi = cat(const_hi_hi, q.io.deq.bits.size)
node const = cat(const_hi, const_lo)
regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0)
connect io.flit.valid, q.io.deq.valid
node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0))
node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T)
node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1)
connect q.io.deq.ready, _q_io_deq_ready_T_2
node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0))
node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T)
connect io.flit.bits.head, _io_flit_bits_head_T_1
node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0))
node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T)
node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1)
connect io.flit.bits.tail, _io_flit_bits_tail_T_2
node _io_flit_bits_egress_id_requestOH_T = xor(q.io.deq.bits.address, UInt<1>(0h0))
node _io_flit_bits_egress_id_requestOH_T_1 = cvt(_io_flit_bits_egress_id_requestOH_T)
node _io_flit_bits_egress_id_requestOH_T_2 = and(_io_flit_bits_egress_id_requestOH_T_1, asSInt(UInt<33>(0h8c000000)))
node _io_flit_bits_egress_id_requestOH_T_3 = asSInt(_io_flit_bits_egress_id_requestOH_T_2)
node _io_flit_bits_egress_id_requestOH_T_4 = eq(_io_flit_bits_egress_id_requestOH_T_3, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_5 = xor(q.io.deq.bits.address, UInt<17>(0h10000))
node _io_flit_bits_egress_id_requestOH_T_6 = cvt(_io_flit_bits_egress_id_requestOH_T_5)
node _io_flit_bits_egress_id_requestOH_T_7 = and(_io_flit_bits_egress_id_requestOH_T_6, asSInt(UInt<33>(0h8c011000)))
node _io_flit_bits_egress_id_requestOH_T_8 = asSInt(_io_flit_bits_egress_id_requestOH_T_7)
node _io_flit_bits_egress_id_requestOH_T_9 = eq(_io_flit_bits_egress_id_requestOH_T_8, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_10 = xor(q.io.deq.bits.address, UInt<28>(0hc000000))
node _io_flit_bits_egress_id_requestOH_T_11 = cvt(_io_flit_bits_egress_id_requestOH_T_10)
node _io_flit_bits_egress_id_requestOH_T_12 = and(_io_flit_bits_egress_id_requestOH_T_11, asSInt(UInt<33>(0h8c000000)))
node _io_flit_bits_egress_id_requestOH_T_13 = asSInt(_io_flit_bits_egress_id_requestOH_T_12)
node _io_flit_bits_egress_id_requestOH_T_14 = eq(_io_flit_bits_egress_id_requestOH_T_13, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_15 = or(_io_flit_bits_egress_id_requestOH_T_4, _io_flit_bits_egress_id_requestOH_T_9)
node _io_flit_bits_egress_id_requestOH_T_16 = or(_io_flit_bits_egress_id_requestOH_T_15, _io_flit_bits_egress_id_requestOH_T_14)
node _io_flit_bits_egress_id_requestOH_T_17 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_16)
node io_flit_bits_egress_id_requestOH_0 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_17)
node _io_flit_bits_egress_id_requestOH_T_18 = xor(q.io.deq.bits.address, UInt<28>(0h8000000))
node _io_flit_bits_egress_id_requestOH_T_19 = cvt(_io_flit_bits_egress_id_requestOH_T_18)
node _io_flit_bits_egress_id_requestOH_T_20 = and(_io_flit_bits_egress_id_requestOH_T_19, asSInt(UInt<33>(0h8c0100c0)))
node _io_flit_bits_egress_id_requestOH_T_21 = asSInt(_io_flit_bits_egress_id_requestOH_T_20)
node _io_flit_bits_egress_id_requestOH_T_22 = eq(_io_flit_bits_egress_id_requestOH_T_21, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_23 = xor(q.io.deq.bits.address, UInt<32>(0h80000000))
node _io_flit_bits_egress_id_requestOH_T_24 = cvt(_io_flit_bits_egress_id_requestOH_T_23)
node _io_flit_bits_egress_id_requestOH_T_25 = and(_io_flit_bits_egress_id_requestOH_T_24, asSInt(UInt<33>(0h800000c0)))
node _io_flit_bits_egress_id_requestOH_T_26 = asSInt(_io_flit_bits_egress_id_requestOH_T_25)
node _io_flit_bits_egress_id_requestOH_T_27 = eq(_io_flit_bits_egress_id_requestOH_T_26, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_28 = or(_io_flit_bits_egress_id_requestOH_T_22, _io_flit_bits_egress_id_requestOH_T_27)
node _io_flit_bits_egress_id_requestOH_T_29 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_28)
node io_flit_bits_egress_id_requestOH_1 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_29)
node _io_flit_bits_egress_id_requestOH_T_30 = xor(q.io.deq.bits.address, UInt<28>(0h8000040))
node _io_flit_bits_egress_id_requestOH_T_31 = cvt(_io_flit_bits_egress_id_requestOH_T_30)
node _io_flit_bits_egress_id_requestOH_T_32 = and(_io_flit_bits_egress_id_requestOH_T_31, asSInt(UInt<33>(0h8c0100c0)))
node _io_flit_bits_egress_id_requestOH_T_33 = asSInt(_io_flit_bits_egress_id_requestOH_T_32)
node _io_flit_bits_egress_id_requestOH_T_34 = eq(_io_flit_bits_egress_id_requestOH_T_33, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_35 = xor(q.io.deq.bits.address, UInt<32>(0h80000040))
node _io_flit_bits_egress_id_requestOH_T_36 = cvt(_io_flit_bits_egress_id_requestOH_T_35)
node _io_flit_bits_egress_id_requestOH_T_37 = and(_io_flit_bits_egress_id_requestOH_T_36, asSInt(UInt<33>(0h800000c0)))
node _io_flit_bits_egress_id_requestOH_T_38 = asSInt(_io_flit_bits_egress_id_requestOH_T_37)
node _io_flit_bits_egress_id_requestOH_T_39 = eq(_io_flit_bits_egress_id_requestOH_T_38, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_40 = or(_io_flit_bits_egress_id_requestOH_T_34, _io_flit_bits_egress_id_requestOH_T_39)
node _io_flit_bits_egress_id_requestOH_T_41 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_40)
node io_flit_bits_egress_id_requestOH_2 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_41)
node _io_flit_bits_egress_id_requestOH_T_42 = xor(q.io.deq.bits.address, UInt<28>(0h8000080))
node _io_flit_bits_egress_id_requestOH_T_43 = cvt(_io_flit_bits_egress_id_requestOH_T_42)
node _io_flit_bits_egress_id_requestOH_T_44 = and(_io_flit_bits_egress_id_requestOH_T_43, asSInt(UInt<33>(0h8c0100c0)))
node _io_flit_bits_egress_id_requestOH_T_45 = asSInt(_io_flit_bits_egress_id_requestOH_T_44)
node _io_flit_bits_egress_id_requestOH_T_46 = eq(_io_flit_bits_egress_id_requestOH_T_45, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_47 = xor(q.io.deq.bits.address, UInt<32>(0h80000080))
node _io_flit_bits_egress_id_requestOH_T_48 = cvt(_io_flit_bits_egress_id_requestOH_T_47)
node _io_flit_bits_egress_id_requestOH_T_49 = and(_io_flit_bits_egress_id_requestOH_T_48, asSInt(UInt<33>(0h800000c0)))
node _io_flit_bits_egress_id_requestOH_T_50 = asSInt(_io_flit_bits_egress_id_requestOH_T_49)
node _io_flit_bits_egress_id_requestOH_T_51 = eq(_io_flit_bits_egress_id_requestOH_T_50, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_52 = or(_io_flit_bits_egress_id_requestOH_T_46, _io_flit_bits_egress_id_requestOH_T_51)
node _io_flit_bits_egress_id_requestOH_T_53 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_52)
node io_flit_bits_egress_id_requestOH_3 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_53)
node _io_flit_bits_egress_id_requestOH_T_54 = xor(q.io.deq.bits.address, UInt<28>(0h80000c0))
node _io_flit_bits_egress_id_requestOH_T_55 = cvt(_io_flit_bits_egress_id_requestOH_T_54)
node _io_flit_bits_egress_id_requestOH_T_56 = and(_io_flit_bits_egress_id_requestOH_T_55, asSInt(UInt<33>(0h8c0100c0)))
node _io_flit_bits_egress_id_requestOH_T_57 = asSInt(_io_flit_bits_egress_id_requestOH_T_56)
node _io_flit_bits_egress_id_requestOH_T_58 = eq(_io_flit_bits_egress_id_requestOH_T_57, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_59 = xor(q.io.deq.bits.address, UInt<32>(0h800000c0))
node _io_flit_bits_egress_id_requestOH_T_60 = cvt(_io_flit_bits_egress_id_requestOH_T_59)
node _io_flit_bits_egress_id_requestOH_T_61 = and(_io_flit_bits_egress_id_requestOH_T_60, asSInt(UInt<33>(0h800000c0)))
node _io_flit_bits_egress_id_requestOH_T_62 = asSInt(_io_flit_bits_egress_id_requestOH_T_61)
node _io_flit_bits_egress_id_requestOH_T_63 = eq(_io_flit_bits_egress_id_requestOH_T_62, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_64 = or(_io_flit_bits_egress_id_requestOH_T_58, _io_flit_bits_egress_id_requestOH_T_63)
node _io_flit_bits_egress_id_requestOH_T_65 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_64)
node io_flit_bits_egress_id_requestOH_4 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_65)
node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<4>(0h9), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<4>(0hb), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<4>(0hd), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<4>(0hf), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<5>(0h11), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_5 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1)
node _io_flit_bits_egress_id_T_6 = or(_io_flit_bits_egress_id_T_5, _io_flit_bits_egress_id_T_2)
node _io_flit_bits_egress_id_T_7 = or(_io_flit_bits_egress_id_T_6, _io_flit_bits_egress_id_T_3)
node _io_flit_bits_egress_id_T_8 = or(_io_flit_bits_egress_id_T_7, _io_flit_bits_egress_id_T_4)
wire _io_flit_bits_egress_id_WIRE : UInt<5>
connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_8
connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE
node _io_flit_bits_payload_T = mux(is_body, body, const)
connect io.flit.bits.payload, _io_flit_bits_payload_T
node _T = and(io.flit.ready, io.flit.valid)
node _T_1 = and(_T, io.flit.bits.head)
when _T_1 :
connect is_body, UInt<1>(0h1)
node _T_2 = and(io.flit.ready, io.flit.valid)
node _T_3 = and(_T_2, io.flit.bits.tail)
when _T_3 :
connect is_body, UInt<1>(0h0)
node _has_body_opdata_T = bits(q.io.deq.bits.opcode, 2, 2)
node has_body_opdata = eq(_has_body_opdata_T, UInt<1>(0h0))
node _has_body_T = not(q.io.deq.bits.mask)
node _has_body_T_1 = neq(_has_body_T, UInt<1>(0h0))
node _has_body_T_2 = or(has_body_opdata, _has_body_T_1)
connect has_body, _has_body_T_2
connect q.io.enq, io.protocol
node _q_io_enq_bits_source_T = or(io.protocol.bits.source, UInt<6>(0h20))
connect q.io.enq.bits.source, _q_io_enq_bits_source_T | module TLAToNoC_8( // @[TilelinkAdapters.scala:112:7]
input clock, // @[TilelinkAdapters.scala:112:7]
input reset, // @[TilelinkAdapters.scala:112:7]
output io_protocol_ready, // @[TilelinkAdapters.scala:19:14]
input io_protocol_valid, // @[TilelinkAdapters.scala:19:14]
input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14]
input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14]
input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14]
input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14]
input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14]
input [7:0] io_protocol_bits_mask, // @[TilelinkAdapters.scala:19:14]
input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14]
input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14]
input io_flit_ready, // @[TilelinkAdapters.scala:19:14]
output io_flit_valid, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14]
output [72:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14]
output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14]
);
wire [8:0] _GEN; // @[TilelinkAdapters.scala:119:{45,69}]
wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17]
wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17]
wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17]
wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17]
wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17]
wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17]
wire [7:0] _q_io_deq_bits_mask; // @[TilelinkAdapters.scala:26:17]
wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17]
wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17]
wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71]
reg [8:0] head_counter; // @[Edges.scala:229:27]
wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire [8:0] tail_beats1 = _q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3]); // @[package.scala:243:{46,71,76}]
reg [8:0] tail_counter; // @[Edges.scala:229:27]
reg is_body; // @[TilelinkAdapters.scala:39:24]
wire _io_flit_bits_tail_T = _GEN == 9'h0; // @[TilelinkAdapters.scala:119:{45,69}]
wire q_io_deq_ready = io_flit_ready & (is_body | _io_flit_bits_tail_T); // @[TilelinkAdapters.scala:39:24, :41:{35,47}, :119:{45,69}]
wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25]
wire io_flit_bits_tail_0 = (tail_counter == 9'h1 | tail_beats1 == 9'h0) & (is_body | _io_flit_bits_tail_T); // @[Edges.scala:221:14, :229:27, :232:{25,33,43}]
wire [21:0] _GEN_0 = _q_io_deq_bits_address[27:6] ^ 22'h200001; // @[Parameters.scala:137:31]
wire [25:0] _io_flit_bits_egress_id_requestOH_T_35 = _q_io_deq_bits_address[31:6] ^ 26'h2000001; // @[Parameters.scala:137:31]
wire [21:0] _GEN_1 = _q_io_deq_bits_address[27:6] ^ 22'h200002; // @[Parameters.scala:137:31]
wire [25:0] _io_flit_bits_egress_id_requestOH_T_47 = _q_io_deq_bits_address[31:6] ^ 26'h2000002; // @[Parameters.scala:137:31]
wire [21:0] _GEN_2 = _q_io_deq_bits_address[27:6] ^ 22'h200003; // @[Parameters.scala:137:31]
wire [25:0] _io_flit_bits_egress_id_requestOH_T_59 = _q_io_deq_bits_address[31:6] ^ 26'h2000003; // @[Parameters.scala:137:31]
assign _GEN = {~(_q_io_deq_bits_opcode[2]), ~_q_io_deq_bits_mask}; // @[Edges.scala:92:{28,37}]
wire _GEN_3 = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TilelinkAdapters.scala:112:7]
if (reset) begin // @[TilelinkAdapters.scala:112:7]
head_counter <= 9'h0; // @[Edges.scala:229:27]
tail_counter <= 9'h0; // @[Edges.scala:229:27]
is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :112:7]
end
else begin // @[TilelinkAdapters.scala:112:7]
if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35]
head_counter <= head ? (_q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3])) : head_counter - 9'h1; // @[package.scala:243:{46,71,76}]
tail_counter <= tail_counter == 9'h0 ? tail_beats1 : tail_counter - 9'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21]
end
is_body <= ~(_GEN_3 & io_flit_bits_tail_0) & (_GEN_3 & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35]
end
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_227 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_227( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RegisterFileSynthesizable :
input clock : Clock
input reset : Reset
output io : { read_ports : { flip addr : UInt<6>, data : UInt<65>}[3], flip write_ports : { valid : UInt<1>, bits : { addr : UInt<6>, data : UInt<65>}}[2]}
cmem regfile : UInt<65> [48]
wire read_data : UInt<65>[3]
reg read_addrs_0 : UInt, clock
connect read_addrs_0, io.read_ports[0].addr
reg read_addrs_1 : UInt, clock
connect read_addrs_1, io.read_ports[1].addr
reg read_addrs_2 : UInt, clock
connect read_addrs_2, io.read_ports[2].addr
node _read_data_0_T = or(read_addrs_0, UInt<6>(0h0))
node _read_data_0_T_1 = bits(_read_data_0_T, 5, 0)
infer mport read_data_0_MPORT = regfile[_read_data_0_T_1], clock
connect read_data[0], read_data_0_MPORT
node _read_data_1_T = or(read_addrs_1, UInt<6>(0h0))
node _read_data_1_T_1 = bits(_read_data_1_T, 5, 0)
infer mport read_data_1_MPORT = regfile[_read_data_1_T_1], clock
connect read_data[1], read_data_1_MPORT
node _read_data_2_T = or(read_addrs_2, UInt<6>(0h0))
node _read_data_2_T_1 = bits(_read_data_2_T, 5, 0)
infer mport read_data_2_MPORT = regfile[_read_data_2_T_1], clock
connect read_data[2], read_data_2_MPORT
connect io.read_ports[0].data, read_data[0]
connect io.read_ports[1].data, read_data[1]
connect io.read_ports[2].data, read_data[2]
when io.write_ports[0].valid :
infer mport MPORT = regfile[io.write_ports[0].bits.addr], clock
connect MPORT, io.write_ports[0].bits.data
when io.write_ports[1].valid :
infer mport MPORT_1 = regfile[io.write_ports[1].bits.addr], clock
connect MPORT_1, io.write_ports[1].bits.data
node _T = eq(io.write_ports[0].valid, UInt<1>(0h0))
node _T_1 = eq(io.write_ports[1].valid, UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = neq(io.write_ports[0].bits.addr, io.write_ports[1].bits.addr)
node _T_4 = or(_T_2, _T_3)
node _T_5 = eq(io.write_ports[0].bits.addr, UInt<1>(0h0))
node _T_6 = or(_T_4, _T_5)
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:171 assert(!io.write_ports(i).valid ||\n") : printf
assert(clock, _T_6, UInt<1>(0h1), "") : assert | module RegisterFileSynthesizable( // @[regfile.scala:106:7]
input clock, // @[regfile.scala:106:7]
input reset, // @[regfile.scala:106:7]
input [5:0] io_read_ports_0_addr, // @[regfile.scala:82:14]
output [64:0] io_read_ports_0_data, // @[regfile.scala:82:14]
input [5:0] io_read_ports_1_addr, // @[regfile.scala:82:14]
output [64:0] io_read_ports_1_data, // @[regfile.scala:82:14]
input [5:0] io_read_ports_2_addr, // @[regfile.scala:82:14]
output [64:0] io_read_ports_2_data, // @[regfile.scala:82:14]
input io_write_ports_0_valid, // @[regfile.scala:82:14]
input [5:0] io_write_ports_0_bits_addr, // @[regfile.scala:82:14]
input [64:0] io_write_ports_0_bits_data, // @[regfile.scala:82:14]
input io_write_ports_1_valid, // @[regfile.scala:82:14]
input [5:0] io_write_ports_1_bits_addr, // @[regfile.scala:82:14]
input [64:0] io_write_ports_1_bits_data // @[regfile.scala:82:14]
);
wire [5:0] io_read_ports_0_addr_0 = io_read_ports_0_addr; // @[regfile.scala:106:7]
wire [5:0] io_read_ports_1_addr_0 = io_read_ports_1_addr; // @[regfile.scala:106:7]
wire [5:0] io_read_ports_2_addr_0 = io_read_ports_2_addr; // @[regfile.scala:106:7]
wire io_write_ports_0_valid_0 = io_write_ports_0_valid; // @[regfile.scala:106:7]
wire [5:0] io_write_ports_0_bits_addr_0 = io_write_ports_0_bits_addr; // @[regfile.scala:106:7]
wire [64:0] io_write_ports_0_bits_data_0 = io_write_ports_0_bits_data; // @[regfile.scala:106:7]
wire io_write_ports_1_valid_0 = io_write_ports_1_valid; // @[regfile.scala:106:7]
wire [5:0] io_write_ports_1_bits_addr_0 = io_write_ports_1_bits_addr; // @[regfile.scala:106:7]
wire [64:0] io_write_ports_1_bits_data_0 = io_write_ports_1_bits_data; // @[regfile.scala:106:7]
wire [64:0] read_data_0; // @[regfile.scala:122:23]
wire [64:0] read_data_1; // @[regfile.scala:122:23]
wire [64:0] read_data_2; // @[regfile.scala:122:23]
wire [64:0] io_read_ports_0_data_0; // @[regfile.scala:106:7]
wire [64:0] io_read_ports_1_data_0; // @[regfile.scala:106:7]
wire [64:0] io_read_ports_2_data_0; // @[regfile.scala:106:7]
assign io_read_ports_0_data_0 = read_data_0; // @[regfile.scala:106:7, :122:23]
assign io_read_ports_1_data_0 = read_data_1; // @[regfile.scala:106:7, :122:23]
assign io_read_ports_2_data_0 = read_data_2; // @[regfile.scala:106:7, :122:23]
reg [5:0] read_addrs_0; // @[regfile.scala:125:50]
wire [5:0] _read_data_0_T = read_addrs_0; // @[regfile.scala:125:50, :128:28]
reg [5:0] read_addrs_1; // @[regfile.scala:125:50]
wire [5:0] _read_data_1_T = read_addrs_1; // @[regfile.scala:125:50, :128:28]
reg [5:0] read_addrs_2; // @[regfile.scala:125:50]
wire [5:0] _read_data_2_T = read_addrs_2; // @[regfile.scala:125:50, :128:28]
wire [5:0] _read_data_0_T_1 = _read_data_0_T; // @[regfile.scala:128:28]
wire [5:0] _read_data_1_T_1 = _read_data_1_T; // @[regfile.scala:128:28]
wire [5:0] _read_data_2_T_1 = _read_data_2_T; // @[regfile.scala:128:28] |
Generate the Verilog code corresponding to this FIRRTL code module LatencyInjectionQueue_15 :
input clock : Clock
input reset : Reset
output io : { flip latency_cycles : UInt<64>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}
regreset cur_cycle : UInt<64>, clock, reset, UInt<64>(0h0)
node _cur_cycle_T = add(cur_cycle, UInt<1>(0h1))
node _cur_cycle_T_1 = tail(_cur_cycle_T, 1)
connect cur_cycle, _cur_cycle_T_1
inst queue of Queue64_TLBundleD_a32d256s5k3z4u_5
connect queue.clock, clock
connect queue.reset, reset
inst release_ready_cycle_q of Queue64_UInt64_11
connect release_ready_cycle_q.clock, clock
connect release_ready_cycle_q.reset, reset
node _release_ready_cycle_q_io_enq_bits_T = add(cur_cycle, io.latency_cycles)
node _release_ready_cycle_q_io_enq_bits_T_1 = tail(_release_ready_cycle_q_io_enq_bits_T, 1)
connect release_ready_cycle_q.io.enq.bits, _release_ready_cycle_q_io_enq_bits_T_1
connect queue.io.enq.bits.corrupt, io.enq.bits.corrupt
connect queue.io.enq.bits.data, io.enq.bits.data
connect queue.io.enq.bits.denied, io.enq.bits.denied
connect queue.io.enq.bits.sink, io.enq.bits.sink
connect queue.io.enq.bits.source, io.enq.bits.source
connect queue.io.enq.bits.size, io.enq.bits.size
connect queue.io.enq.bits.param, io.enq.bits.param
connect queue.io.enq.bits.opcode, io.enq.bits.opcode
connect io.deq.bits, queue.io.deq.bits
node _queue_io_enq_valid_T = and(release_ready_cycle_q.io.enq.ready, io.enq.valid)
connect queue.io.enq.valid, _queue_io_enq_valid_T
node _release_ready_cycle_q_io_enq_valid_T = and(queue.io.enq.ready, io.enq.valid)
connect release_ready_cycle_q.io.enq.valid, _release_ready_cycle_q_io_enq_valid_T
node _io_enq_ready_T = and(queue.io.enq.ready, release_ready_cycle_q.io.enq.ready)
connect io.enq.ready, _io_enq_ready_T
node _T = leq(release_ready_cycle_q.io.deq.bits, cur_cycle)
node _queue_io_deq_ready_T = and(release_ready_cycle_q.io.deq.valid, _T)
node _queue_io_deq_ready_T_1 = and(_queue_io_deq_ready_T, io.deq.ready)
connect queue.io.deq.ready, _queue_io_deq_ready_T_1
node _release_ready_cycle_q_io_deq_ready_T = and(queue.io.deq.valid, _T)
node _release_ready_cycle_q_io_deq_ready_T_1 = and(_release_ready_cycle_q_io_deq_ready_T, io.deq.ready)
connect release_ready_cycle_q.io.deq.ready, _release_ready_cycle_q_io_deq_ready_T_1
node _io_deq_valid_T = and(queue.io.deq.valid, release_ready_cycle_q.io.deq.valid)
node _io_deq_valid_T_1 = and(_io_deq_valid_T, _T)
connect io.deq.valid, _io_deq_valid_T_1 | module LatencyInjectionQueue_15( // @[LatencyInjectionQueue.scala:9:7]
input clock, // @[LatencyInjectionQueue.scala:9:7]
input reset, // @[LatencyInjectionQueue.scala:9:7]
input [63:0] io_latency_cycles, // @[LatencyInjectionQueue.scala:10:14]
output io_enq_ready, // @[LatencyInjectionQueue.scala:10:14]
input io_enq_valid, // @[LatencyInjectionQueue.scala:10:14]
input [2:0] io_enq_bits_opcode, // @[LatencyInjectionQueue.scala:10:14]
input [1:0] io_enq_bits_param, // @[LatencyInjectionQueue.scala:10:14]
input [3:0] io_enq_bits_size, // @[LatencyInjectionQueue.scala:10:14]
input [4:0] io_enq_bits_source, // @[LatencyInjectionQueue.scala:10:14]
input [2:0] io_enq_bits_sink, // @[LatencyInjectionQueue.scala:10:14]
input io_enq_bits_denied, // @[LatencyInjectionQueue.scala:10:14]
input [255:0] io_enq_bits_data, // @[LatencyInjectionQueue.scala:10:14]
input io_enq_bits_corrupt, // @[LatencyInjectionQueue.scala:10:14]
input io_deq_ready, // @[LatencyInjectionQueue.scala:10:14]
output io_deq_valid, // @[LatencyInjectionQueue.scala:10:14]
output [4:0] io_deq_bits_source, // @[LatencyInjectionQueue.scala:10:14]
output [255:0] io_deq_bits_data // @[LatencyInjectionQueue.scala:10:14]
);
wire _release_ready_cycle_q_io_enq_ready; // @[LatencyInjectionQueue.scala:19:37]
wire _release_ready_cycle_q_io_deq_valid; // @[LatencyInjectionQueue.scala:19:37]
wire [63:0] _release_ready_cycle_q_io_deq_bits; // @[LatencyInjectionQueue.scala:19:37]
wire _queue_io_enq_ready; // @[LatencyInjectionQueue.scala:18:21]
wire _queue_io_deq_valid; // @[LatencyInjectionQueue.scala:18:21]
wire [63:0] io_latency_cycles_0 = io_latency_cycles; // @[LatencyInjectionQueue.scala:9:7]
wire io_enq_valid_0 = io_enq_valid; // @[LatencyInjectionQueue.scala:9:7]
wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[LatencyInjectionQueue.scala:9:7]
wire [1:0] io_enq_bits_param_0 = io_enq_bits_param; // @[LatencyInjectionQueue.scala:9:7]
wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[LatencyInjectionQueue.scala:9:7]
wire [4:0] io_enq_bits_source_0 = io_enq_bits_source; // @[LatencyInjectionQueue.scala:9:7]
wire [2:0] io_enq_bits_sink_0 = io_enq_bits_sink; // @[LatencyInjectionQueue.scala:9:7]
wire io_enq_bits_denied_0 = io_enq_bits_denied; // @[LatencyInjectionQueue.scala:9:7]
wire [255:0] io_enq_bits_data_0 = io_enq_bits_data; // @[LatencyInjectionQueue.scala:9:7]
wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[LatencyInjectionQueue.scala:9:7]
wire io_deq_ready_0 = io_deq_ready; // @[LatencyInjectionQueue.scala:9:7]
wire _io_enq_ready_T; // @[Misc.scala:26:53]
wire _io_deq_valid_T_1; // @[Misc.scala:26:53]
wire io_enq_ready_0; // @[LatencyInjectionQueue.scala:9:7]
wire [2:0] io_deq_bits_opcode; // @[LatencyInjectionQueue.scala:9:7]
wire [1:0] io_deq_bits_param; // @[LatencyInjectionQueue.scala:9:7]
wire [3:0] io_deq_bits_size; // @[LatencyInjectionQueue.scala:9:7]
wire [4:0] io_deq_bits_source_0; // @[LatencyInjectionQueue.scala:9:7]
wire [2:0] io_deq_bits_sink; // @[LatencyInjectionQueue.scala:9:7]
wire io_deq_bits_denied; // @[LatencyInjectionQueue.scala:9:7]
wire [255:0] io_deq_bits_data_0; // @[LatencyInjectionQueue.scala:9:7]
wire io_deq_bits_corrupt; // @[LatencyInjectionQueue.scala:9:7]
wire io_deq_valid_0; // @[LatencyInjectionQueue.scala:9:7]
reg [63:0] cur_cycle; // @[LatencyInjectionQueue.scala:16:26]
wire [64:0] _GEN = {1'h0, cur_cycle}; // @[LatencyInjectionQueue.scala:16:26, :17:26]
wire [64:0] _cur_cycle_T = _GEN + 65'h1; // @[LatencyInjectionQueue.scala:17:26]
wire [63:0] _cur_cycle_T_1 = _cur_cycle_T[63:0]; // @[LatencyInjectionQueue.scala:17:26]
wire [64:0] _release_ready_cycle_q_io_enq_bits_T = _GEN + {1'h0, io_latency_cycles_0}; // @[LatencyInjectionQueue.scala:9:7, :17:26, :21:50]
wire [63:0] _release_ready_cycle_q_io_enq_bits_T_1 = _release_ready_cycle_q_io_enq_bits_T[63:0]; // @[LatencyInjectionQueue.scala:21:50]
wire _queue_io_enq_valid_T = _release_ready_cycle_q_io_enq_ready & io_enq_valid_0; // @[Misc.scala:26:53]
wire _release_ready_cycle_q_io_enq_valid_T = _queue_io_enq_ready & io_enq_valid_0; // @[Misc.scala:26:53]
assign _io_enq_ready_T = _queue_io_enq_ready & _release_ready_cycle_q_io_enq_ready; // @[Misc.scala:26:53]
assign io_enq_ready_0 = _io_enq_ready_T; // @[Misc.scala:26:53]
wire _T = _release_ready_cycle_q_io_deq_bits <= cur_cycle; // @[LatencyInjectionQueue.scala:16:26, :19:37, :38:39]
wire _queue_io_deq_ready_T = _release_ready_cycle_q_io_deq_valid & _T; // @[Misc.scala:26:53]
wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & io_deq_ready_0; // @[Misc.scala:26:53]
wire _release_ready_cycle_q_io_deq_ready_T = _queue_io_deq_valid & _T; // @[Misc.scala:26:53]
wire _release_ready_cycle_q_io_deq_ready_T_1 = _release_ready_cycle_q_io_deq_ready_T & io_deq_ready_0; // @[Misc.scala:26:53]
wire _io_deq_valid_T = _queue_io_deq_valid & _release_ready_cycle_q_io_deq_valid; // @[Misc.scala:26:53]
assign _io_deq_valid_T_1 = _io_deq_valid_T & _T; // @[Misc.scala:26:53]
assign io_deq_valid_0 = _io_deq_valid_T_1; // @[Misc.scala:26:53]
always @(posedge clock) begin // @[LatencyInjectionQueue.scala:9:7]
if (reset) // @[LatencyInjectionQueue.scala:9:7]
cur_cycle <= 64'h0; // @[LatencyInjectionQueue.scala:16:26]
else // @[LatencyInjectionQueue.scala:9:7]
cur_cycle <= _cur_cycle_T_1; // @[LatencyInjectionQueue.scala:16:26, :17:26]
always @(posedge)
Queue64_TLBundleD_a32d256s5k3z4u_5 queue ( // @[LatencyInjectionQueue.scala:18:21]
.clock (clock),
.reset (reset),
.io_enq_ready (_queue_io_enq_ready),
.io_enq_valid (_queue_io_enq_valid_T), // @[Misc.scala:26:53]
.io_enq_bits_opcode (io_enq_bits_opcode_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_param (io_enq_bits_param_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_size (io_enq_bits_size_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_source (io_enq_bits_source_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_sink (io_enq_bits_sink_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_denied (io_enq_bits_denied_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_data (io_enq_bits_data_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_corrupt (io_enq_bits_corrupt_0), // @[LatencyInjectionQueue.scala:9:7]
.io_deq_ready (_queue_io_deq_ready_T_1), // @[Misc.scala:26:53]
.io_deq_valid (_queue_io_deq_valid),
.io_deq_bits_opcode (io_deq_bits_opcode),
.io_deq_bits_param (io_deq_bits_param),
.io_deq_bits_size (io_deq_bits_size),
.io_deq_bits_source (io_deq_bits_source_0),
.io_deq_bits_sink (io_deq_bits_sink),
.io_deq_bits_denied (io_deq_bits_denied),
.io_deq_bits_data (io_deq_bits_data_0),
.io_deq_bits_corrupt (io_deq_bits_corrupt)
); // @[LatencyInjectionQueue.scala:18:21]
Queue64_UInt64_11 release_ready_cycle_q ( // @[LatencyInjectionQueue.scala:19:37]
.clock (clock),
.reset (reset),
.io_enq_ready (_release_ready_cycle_q_io_enq_ready),
.io_enq_valid (_release_ready_cycle_q_io_enq_valid_T), // @[Misc.scala:26:53]
.io_enq_bits (_release_ready_cycle_q_io_enq_bits_T_1), // @[LatencyInjectionQueue.scala:21:50]
.io_deq_ready (_release_ready_cycle_q_io_deq_ready_T_1), // @[Misc.scala:26:53]
.io_deq_valid (_release_ready_cycle_q_io_deq_valid),
.io_deq_bits (_release_ready_cycle_q_io_deq_bits)
); // @[LatencyInjectionQueue.scala:19:37]
assign io_enq_ready = io_enq_ready_0; // @[LatencyInjectionQueue.scala:9:7]
assign io_deq_valid = io_deq_valid_0; // @[LatencyInjectionQueue.scala:9:7]
assign io_deq_bits_source = io_deq_bits_source_0; // @[LatencyInjectionQueue.scala:9:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[LatencyInjectionQueue.scala:9:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module GenericFIR :
input clock : Clock
input reset : Reset
output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : SInt<8>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : SInt<8>}}}
wire _directCells_new : SInt<1>
wire _directCells_new_WIRE : SInt<1>
connect _directCells_new_WIRE, asSInt(UInt<1>(0h1))
connect _directCells_new, _directCells_new_WIRE
wire _directCells_new_1 : SInt<2>
wire _directCells_new_WIRE_1 : SInt<2>
connect _directCells_new_WIRE_1, asSInt(UInt<2>(0h2))
connect _directCells_new_1, _directCells_new_WIRE_1
wire _directCells_new_2 : SInt<2>
wire _directCells_new_WIRE_2 : SInt<2>
connect _directCells_new_WIRE_2, asSInt(UInt<2>(0h3))
connect _directCells_new_2, _directCells_new_WIRE_2
inst GenericFIRDirectCell of GenericFIRDirectCell
connect GenericFIRDirectCell.clock, clock
connect GenericFIRDirectCell.reset, reset
inst GenericFIRDirectCell_1 of GenericFIRDirectCell_1
connect GenericFIRDirectCell_1.clock, clock
connect GenericFIRDirectCell_1.reset, reset
inst GenericFIRDirectCell_2 of GenericFIRDirectCell_2
connect GenericFIRDirectCell_2.clock, clock
connect GenericFIRDirectCell_2.reset, reset
wire _new : SInt<1>
wire _new_WIRE : SInt<1>
connect _new_WIRE, asSInt(UInt<1>(0h1))
connect _new, _new_WIRE
wire _new_1 : SInt<2>
wire _new_WIRE_1 : SInt<2>
connect _new_WIRE_1, asSInt(UInt<2>(0h2))
connect _new_1, _new_WIRE_1
wire _new_2 : SInt<2>
wire _new_WIRE_2 : SInt<2>
connect _new_WIRE_2, asSInt(UInt<2>(0h3))
connect _new_2, _new_WIRE_2
node _T = shl(_new, 3)
wire _new_3 : SInt<4>
wire _new_WIRE_3 : SInt<4>
node _new_T = asUInt(_T)
node _new_T_1 = asSInt(_new_T)
connect _new_WIRE_3, _new_T_1
connect _new_3, _new_WIRE_3
connect GenericFIRDirectCell.io.coeff, _new_3
node _T_1 = shl(_new_1, 3)
wire _new_4 : SInt<5>
wire _new_WIRE_4 : SInt<5>
node _new_T_2 = asUInt(_T_1)
node _new_T_3 = asSInt(_new_T_2)
connect _new_WIRE_4, _new_T_3
connect _new_4, _new_WIRE_4
connect GenericFIRDirectCell_1.io.coeff, _new_4
node _T_2 = shl(_new_2, 3)
wire _new_5 : SInt<5>
wire _new_WIRE_5 : SInt<5>
node _new_T_4 = asUInt(_T_2)
node _new_T_5 = asSInt(_new_T_4)
connect _new_WIRE_5, _new_T_5
connect _new_5, _new_WIRE_5
connect GenericFIRDirectCell_2.io.coeff, _new_5
wire _new_6 : SInt<8>
wire _new_WIRE_6 : SInt<8>
node _new_T_6 = asUInt(io.in.bits.data)
node _new_T_7 = asSInt(_new_T_6)
connect _new_WIRE_6, _new_T_7
connect _new_6, _new_WIRE_6
connect GenericFIRDirectCell.io.in.bits.data, _new_6
node _T_3 = shl(asSInt(UInt<1>(0h0)), 3)
wire _new_7 : SInt<4>
wire _new_WIRE_7 : SInt<4>
node _new_T_8 = asUInt(_T_3)
node _new_T_9 = asSInt(_new_T_8)
connect _new_WIRE_7, _new_T_9
connect _new_7, _new_WIRE_7
connect GenericFIRDirectCell.io.in.bits.carry, _new_7
connect GenericFIRDirectCell.io.in.valid, io.in.valid
connect io.in.ready, GenericFIRDirectCell.io.in.ready
connect GenericFIRDirectCell_1.io.in.bits.carry, GenericFIRDirectCell.io.out.bits.carry
connect GenericFIRDirectCell_1.io.in.bits.data, GenericFIRDirectCell.io.out.bits.data
connect GenericFIRDirectCell_1.io.in.valid, GenericFIRDirectCell.io.out.valid
connect GenericFIRDirectCell.io.out.ready, GenericFIRDirectCell_1.io.in.ready
connect GenericFIRDirectCell_2.io.in.bits.carry, GenericFIRDirectCell_1.io.out.bits.carry
connect GenericFIRDirectCell_2.io.in.bits.data, GenericFIRDirectCell_1.io.out.bits.data
connect GenericFIRDirectCell_2.io.in.valid, GenericFIRDirectCell_1.io.out.valid
connect GenericFIRDirectCell_1.io.out.ready, GenericFIRDirectCell_2.io.in.ready
wire _io_out_bits_data_new : SInt<8>
wire _io_out_bits_data_new_WIRE : SInt<8>
node _io_out_bits_data_new_T = asUInt(GenericFIRDirectCell_2.io.out.bits.carry)
node _io_out_bits_data_new_T_1 = asSInt(_io_out_bits_data_new_T)
connect _io_out_bits_data_new_WIRE, _io_out_bits_data_new_T_1
connect _io_out_bits_data_new, _io_out_bits_data_new_WIRE
connect io.out.bits.data, _io_out_bits_data_new
connect GenericFIRDirectCell_2.io.out.ready, io.out.ready
connect io.out.valid, GenericFIRDirectCell_2.io.out.valid | module GenericFIR( // @[GenericFIR.scala:60:7]
input clock, // @[GenericFIR.scala:60:7]
input reset, // @[GenericFIR.scala:60:7]
output io_in_ready, // @[GenericFIR.scala:61:14]
input io_in_valid, // @[GenericFIR.scala:61:14]
input [7:0] io_in_bits_data, // @[GenericFIR.scala:61:14]
input io_out_ready, // @[GenericFIR.scala:61:14]
output io_out_valid, // @[GenericFIR.scala:61:14]
output [7:0] io_out_bits_data // @[GenericFIR.scala:61:14]
);
wire _GenericFIRDirectCell_2_io_in_ready; // @[GenericFIR.scala:64:52]
wire _GenericFIRDirectCell_1_io_in_ready; // @[GenericFIR.scala:64:52]
wire _GenericFIRDirectCell_1_io_out_valid; // @[GenericFIR.scala:64:52]
wire [7:0] _GenericFIRDirectCell_1_io_out_bits_data; // @[GenericFIR.scala:64:52]
wire [7:0] _GenericFIRDirectCell_1_io_out_bits_carry; // @[GenericFIR.scala:64:52]
wire _GenericFIRDirectCell_io_out_valid; // @[GenericFIR.scala:64:52]
wire [7:0] _GenericFIRDirectCell_io_out_bits_data; // @[GenericFIR.scala:64:52]
wire [7:0] _GenericFIRDirectCell_io_out_bits_carry; // @[GenericFIR.scala:64:52]
GenericFIRDirectCell GenericFIRDirectCell ( // @[GenericFIR.scala:64:52]
.clock (clock),
.reset (reset),
.io_coeff (8'hF8),
.io_in_ready (io_in_ready),
.io_in_valid (io_in_valid),
.io_in_bits_data (io_in_bits_data),
.io_in_bits_carry (8'h0), // @[GenericFIR.scala:73:34]
.io_out_ready (_GenericFIRDirectCell_1_io_in_ready), // @[GenericFIR.scala:64:52]
.io_out_valid (_GenericFIRDirectCell_io_out_valid),
.io_out_bits_data (_GenericFIRDirectCell_io_out_bits_data),
.io_out_bits_carry (_GenericFIRDirectCell_io_out_bits_carry)
); // @[GenericFIR.scala:64:52]
GenericFIRDirectCell GenericFIRDirectCell_1 ( // @[GenericFIR.scala:64:52]
.clock (clock),
.reset (reset),
.io_coeff (8'hF0), // @[GenericFIR.scala:68:16]
.io_in_ready (_GenericFIRDirectCell_1_io_in_ready),
.io_in_valid (_GenericFIRDirectCell_io_out_valid), // @[GenericFIR.scala:64:52]
.io_in_bits_data (_GenericFIRDirectCell_io_out_bits_data), // @[GenericFIR.scala:64:52]
.io_in_bits_carry (_GenericFIRDirectCell_io_out_bits_carry), // @[GenericFIR.scala:64:52]
.io_out_ready (_GenericFIRDirectCell_2_io_in_ready), // @[GenericFIR.scala:64:52]
.io_out_valid (_GenericFIRDirectCell_1_io_out_valid),
.io_out_bits_data (_GenericFIRDirectCell_1_io_out_bits_data),
.io_out_bits_carry (_GenericFIRDirectCell_1_io_out_bits_carry)
); // @[GenericFIR.scala:64:52]
GenericFIRDirectCell GenericFIRDirectCell_2 ( // @[GenericFIR.scala:64:52]
.clock (clock),
.reset (reset),
.io_coeff (8'hF8),
.io_in_ready (_GenericFIRDirectCell_2_io_in_ready),
.io_in_valid (_GenericFIRDirectCell_1_io_out_valid), // @[GenericFIR.scala:64:52]
.io_in_bits_data (_GenericFIRDirectCell_1_io_out_bits_data), // @[GenericFIR.scala:64:52]
.io_in_bits_carry (_GenericFIRDirectCell_1_io_out_bits_carry), // @[GenericFIR.scala:64:52]
.io_out_ready (io_out_ready),
.io_out_valid (io_out_valid),
.io_out_bits_data (/* unused */),
.io_out_bits_carry (io_out_bits_data)
); // @[GenericFIR.scala:64:52]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_85 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_173
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_85( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_173 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_47 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_47( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s2k3z4c_2 :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeIn.e.bits.sink
invalidate nodeIn.e.valid
invalidate nodeIn.e.ready
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.c.bits.corrupt
invalidate nodeIn.c.bits.data
invalidate nodeIn.c.bits.address
invalidate nodeIn.c.bits.source
invalidate nodeIn.c.bits.size
invalidate nodeIn.c.bits.param
invalidate nodeIn.c.bits.opcode
invalidate nodeIn.c.valid
invalidate nodeIn.c.ready
invalidate nodeIn.b.bits.corrupt
invalidate nodeIn.b.bits.data
invalidate nodeIn.b.bits.mask
invalidate nodeIn.b.bits.address
invalidate nodeIn.b.bits.source
invalidate nodeIn.b.bits.size
invalidate nodeIn.b.bits.param
invalidate nodeIn.b.bits.opcode
invalidate nodeIn.b.valid
invalidate nodeIn.b.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_47
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink
connect monitor.io.in.e.valid, nodeIn.e.valid
connect monitor.io.in.e.ready, nodeIn.e.ready
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt
connect monitor.io.in.c.bits.data, nodeIn.c.bits.data
connect monitor.io.in.c.bits.address, nodeIn.c.bits.address
connect monitor.io.in.c.bits.source, nodeIn.c.bits.source
connect monitor.io.in.c.bits.size, nodeIn.c.bits.size
connect monitor.io.in.c.bits.param, nodeIn.c.bits.param
connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode
connect monitor.io.in.c.valid, nodeIn.c.valid
connect monitor.io.in.c.ready, nodeIn.c.ready
connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt
connect monitor.io.in.b.bits.data, nodeIn.b.bits.data
connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask
connect monitor.io.in.b.bits.address, nodeIn.b.bits.address
connect monitor.io.in.b.bits.source, nodeIn.b.bits.source
connect monitor.io.in.b.bits.size, nodeIn.b.bits.size
connect monitor.io.in.b.bits.param, nodeIn.b.bits.param
connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode
connect monitor.io.in.b.valid, nodeIn.b.valid
connect monitor.io.in.b.ready, nodeIn.b.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeOut.e.bits.sink
invalidate nodeOut.e.valid
invalidate nodeOut.e.ready
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.c.bits.corrupt
invalidate nodeOut.c.bits.data
invalidate nodeOut.c.bits.address
invalidate nodeOut.c.bits.source
invalidate nodeOut.c.bits.size
invalidate nodeOut.c.bits.param
invalidate nodeOut.c.bits.opcode
invalidate nodeOut.c.valid
invalidate nodeOut.c.ready
invalidate nodeOut.b.bits.corrupt
invalidate nodeOut.b.bits.data
invalidate nodeOut.b.bits.mask
invalidate nodeOut.b.bits.address
invalidate nodeOut.b.bits.source
invalidate nodeOut.b.bits.size
invalidate nodeOut.b.bits.param
invalidate nodeOut.b.bits.opcode
invalidate nodeOut.b.valid
invalidate nodeOut.b.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a32d64s2k3z4c_1
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a32d64s2k3z4c_1
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
inst nodeIn_b_q of Queue2_TLBundleB_a32d64s2k3z4c_1
connect nodeIn_b_q.clock, clock
connect nodeIn_b_q.reset, reset
connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid
connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt
connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data
connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask
connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address
connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source
connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size
connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param
connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode
connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready
connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits
connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid
connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready
inst nodeOut_c_q of Queue2_TLBundleC_a32d64s2k3z4c_1
connect nodeOut_c_q.clock, clock
connect nodeOut_c_q.reset, reset
connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid
connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt
connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data
connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address
connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source
connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size
connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param
connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode
connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready
connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits
connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid
connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready
inst nodeOut_e_q of Queue2_TLBundleE_a32d64s2k3z4c_1
connect nodeOut_e_q.clock, clock
connect nodeOut_e_q.reset, reset
connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid
connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink
connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready
connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits
connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid
connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready | module TLBuffer_a32d64s2k3z4c_2( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [1:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9]
wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [1:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire auto_in_c_bits_corrupt_0 = auto_in_c_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9]
wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9]
wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9]
wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_out_e_ready = 1'h1; // @[Decoupled.scala:362:21]
wire nodeOut_e_ready = 1'h1; // @[Decoupled.scala:362:21]
wire auto_out_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire [63:0] auto_out_b_bits_data = 64'h0; // @[Decoupled.scala:362:21]
wire [63:0] nodeOut_b_bits_data = 64'h0; // @[Decoupled.scala:362:21]
wire [7:0] auto_out_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21]
wire [7:0] nodeOut_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21]
wire [1:0] auto_out_b_bits_source = 2'h1; // @[Decoupled.scala:362:21]
wire [1:0] nodeOut_b_bits_source = 2'h1; // @[Decoupled.scala:362:21]
wire [3:0] auto_out_b_bits_size = 4'h6; // @[Decoupled.scala:362:21]
wire [3:0] nodeOut_b_bits_size = 4'h6; // @[Decoupled.scala:362:21]
wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_c_bits_corrupt = auto_in_c_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_e_ready; // @[MixedNode.scala:551:17]
wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9]
wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9]
wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_b_valid_0; // @[Buffer.scala:40:9]
wire auto_in_c_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire auto_in_e_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_b_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_c_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9]
assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9]
TLMonitor_47 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17]
.io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17]
.io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17]
.io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17]
.io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17]
.io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17]
.io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17]
.io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_in_c_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17]
.io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d64s2k3z4c_1 nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d64s2k3z4c_1 nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleB_a32d64s2k3z4c_1 nodeIn_b_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_b_ready),
.io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_b_valid),
.io_deq_bits_opcode (nodeIn_b_bits_opcode),
.io_deq_bits_param (nodeIn_b_bits_param),
.io_deq_bits_size (nodeIn_b_bits_size),
.io_deq_bits_source (nodeIn_b_bits_source),
.io_deq_bits_address (nodeIn_b_bits_address),
.io_deq_bits_mask (nodeIn_b_bits_mask),
.io_deq_bits_data (nodeIn_b_bits_data),
.io_deq_bits_corrupt (nodeIn_b_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleC_a32d64s2k3z4c_1 nodeOut_c_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_c_ready),
.io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_c_valid),
.io_deq_bits_opcode (nodeOut_c_bits_opcode),
.io_deq_bits_param (nodeOut_c_bits_param),
.io_deq_bits_size (nodeOut_c_bits_size),
.io_deq_bits_source (nodeOut_c_bits_source),
.io_deq_bits_address (nodeOut_c_bits_address),
.io_deq_bits_data (nodeOut_c_bits_data),
.io_deq_bits_corrupt (nodeOut_c_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleE_a32d64s2k3z4c_1 nodeOut_e_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_e_ready),
.io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeOut_e_valid),
.io_deq_bits_sink (nodeOut_e_bits_sink)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9]
assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_45 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[3]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[3]}}}, flip vcalloc_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[3]}}, flip out_credit_available : { `1` : UInt<1>[1], `0` : UInt<1>[3]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<2>, sa_stall : UInt<2>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}}
inst input_buffer of InputBuffer_45
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
connect input_buffer.io.deq[2].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter3_RouteComputerReq_45
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[3]}, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<3>}[3], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hf))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id)
when _T_9 :
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h1)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1))
connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T
connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id
connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node
connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id
connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node
connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id
connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0)
node _T_10 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid)
when _T_10 :
connect states[0].g, UInt<3>(0h2)
connect route_arbiter.io.in[1].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[1].bits.flow.egress_node_id
invalidate route_arbiter.io.in[1].bits.flow.egress_node
invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[1].bits.flow.ingress_node
invalidate route_arbiter.io.in[1].bits.flow.vnet_id
invalidate route_arbiter.io.in[1].bits.src_virt_id
connect route_arbiter.io.in[2].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[2].bits.flow.egress_node_id
invalidate route_arbiter.io.in[2].bits.flow.egress_node
invalidate route_arbiter.io.in[2].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[2].bits.flow.ingress_node
invalidate route_arbiter.io.in[2].bits.flow.vnet_id
invalidate route_arbiter.io.in[2].bits.src_virt_id
node _T_11 = and(io.router_req.ready, io.router_req.valid)
when _T_11 :
node _T_12 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_13 = asUInt(reset)
node _T_14 = eq(_T_13, UInt<1>(0h0))
when _T_14 :
node _T_15 = eq(_T_12, UInt<1>(0h0))
when _T_15 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_12, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_16 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_16 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
node _T_17 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_17 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
node _T_18 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id)
when _T_18 :
connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
regreset mask : UInt<3>, clock, reset, UInt<3>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[3]}}[3]
wire vcalloc_vals : UInt<1>[3]
node vcalloc_filter_hi = cat(vcalloc_vals[2], vcalloc_vals[1])
node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_vals[0])
node vcalloc_filter_hi_1 = cat(vcalloc_vals[2], vcalloc_vals[1])
node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_vals[0])
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4)
node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5)
node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_10, UInt<6>(0h20), UInt<6>(0h0))
node _vcalloc_filter_T_12 = mux(_vcalloc_filter_T_9, UInt<6>(0h10), _vcalloc_filter_T_11)
node _vcalloc_filter_T_13 = mux(_vcalloc_filter_T_8, UInt<6>(0h8), _vcalloc_filter_T_12)
node _vcalloc_filter_T_14 = mux(_vcalloc_filter_T_7, UInt<6>(0h4), _vcalloc_filter_T_13)
node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_6, UInt<6>(0h2), _vcalloc_filter_T_14)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<6>(0h1), _vcalloc_filter_T_15)
node _vcalloc_sel_T = bits(vcalloc_filter, 2, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 3)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_19 = and(io.router_req.ready, io.router_req.valid)
when _T_19 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_20 = or(vcalloc_vals[0], vcalloc_vals[1])
node _T_21 = or(_T_20, vcalloc_vals[2])
when _T_21 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = not(UInt<3>(0h0))
node _mask_T_6 = bits(vcalloc_sel, 0, 0)
node _mask_T_7 = bits(vcalloc_sel, 1, 1)
node _mask_T_8 = bits(vcalloc_sel, 2, 2)
node _mask_T_9 = mux(_mask_T_6, _mask_T_3, UInt<1>(0h0))
node _mask_T_10 = mux(_mask_T_7, _mask_T_4, UInt<1>(0h0))
node _mask_T_11 = mux(_mask_T_8, _mask_T_5, UInt<1>(0h0))
node _mask_T_12 = or(_mask_T_9, _mask_T_10)
node _mask_T_13 = or(_mask_T_12, _mask_T_11)
wire _mask_WIRE : UInt<3>
connect _mask_WIRE, _mask_T_13
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_1
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[3]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `1` : UInt<1>[1], `0` : UInt<1>[3]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[3]
node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_4 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_6 = or(_io_vcalloc_req_bits_T_3, _io_vcalloc_req_bits_T_4)
node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_6, _io_vcalloc_req_bits_T_5)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_7
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_11 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9)
node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_10)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_12
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_13, _io_vcalloc_req_bits_T_14)
node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_15)
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_17
connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>[1]
node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_19)
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_20)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_22
connect _io_vcalloc_req_bits_WIRE_6[0], _io_vcalloc_req_bits_WIRE_7
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_6
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24)
node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_25)
wire _io_vcalloc_req_bits_WIRE_8 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_27
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_8
wire _io_vcalloc_req_bits_WIRE_9 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_29)
node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_30)
wire _io_vcalloc_req_bits_WIRE_10 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_32
connect _io_vcalloc_req_bits_WIRE_9.egress_node_id, _io_vcalloc_req_bits_WIRE_10
node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_34)
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_35)
wire _io_vcalloc_req_bits_WIRE_11 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_37
connect _io_vcalloc_req_bits_WIRE_9.egress_node, _io_vcalloc_req_bits_WIRE_11
node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39)
node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_40)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_42
connect _io_vcalloc_req_bits_WIRE_9.ingress_node_id, _io_vcalloc_req_bits_WIRE_12
node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_44)
node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_45)
wire _io_vcalloc_req_bits_WIRE_13 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_47
connect _io_vcalloc_req_bits_WIRE_9.ingress_node, _io_vcalloc_req_bits_WIRE_13
node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49)
node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_50)
wire _io_vcalloc_req_bits_WIRE_14 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_52
connect _io_vcalloc_req_bits_WIRE_9.vnet_id, _io_vcalloc_req_bits_WIRE_14
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_9
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2))
node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1)
connect vcalloc_vals[0], _vcalloc_vals_0_T_2
connect vcalloc_reqs[0].in_vc, UInt<1>(0h0)
connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0`
connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1`
connect vcalloc_reqs[0].flow, states[0].flow
node _T_22 = bits(vcalloc_sel, 0, 0)
node _T_23 = and(vcalloc_vals[0], _T_22)
node _T_24 = and(_T_23, io.vcalloc_req.ready)
when _T_24 :
connect states[0].g, UInt<3>(0h3)
node _T_25 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid)
when _T_25 :
connect vcalloc_vals[0], UInt<1>(0h1)
connect vcalloc_reqs[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect vcalloc_reqs[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect vcalloc_vals[1], UInt<1>(0h0)
invalidate vcalloc_reqs[1].vc_sel.`0`[0]
invalidate vcalloc_reqs[1].vc_sel.`0`[1]
invalidate vcalloc_reqs[1].vc_sel.`0`[2]
invalidate vcalloc_reqs[1].vc_sel.`1`[0]
invalidate vcalloc_reqs[1].in_vc
invalidate vcalloc_reqs[1].flow.egress_node_id
invalidate vcalloc_reqs[1].flow.egress_node
invalidate vcalloc_reqs[1].flow.ingress_node_id
invalidate vcalloc_reqs[1].flow.ingress_node
invalidate vcalloc_reqs[1].flow.vnet_id
connect vcalloc_vals[2], UInt<1>(0h0)
invalidate vcalloc_reqs[2].vc_sel.`0`[0]
invalidate vcalloc_reqs[2].vc_sel.`0`[1]
invalidate vcalloc_reqs[2].vc_sel.`0`[2]
invalidate vcalloc_reqs[2].vc_sel.`1`[0]
invalidate vcalloc_reqs[2].in_vc
invalidate vcalloc_reqs[2].flow.egress_node_id
invalidate vcalloc_reqs[2].flow.egress_node
invalidate vcalloc_reqs[2].flow.ingress_node_id
invalidate vcalloc_reqs[2].flow.ingress_node
invalidate vcalloc_reqs[2].flow.vnet_id
node _io_debug_va_stall_T = add(vcalloc_vals[1], vcalloc_vals[2])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = add(vcalloc_vals[0], _io_debug_va_stall_T_1)
node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0)
node _io_debug_va_stall_T_4 = sub(_io_debug_va_stall_T_3, io.vcalloc_req.ready)
node _io_debug_va_stall_T_5 = tail(_io_debug_va_stall_T_4, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_5
node _T_26 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_26 :
node _T_27 = bits(vcalloc_sel, 0, 0)
when _T_27 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].g, UInt<3>(0h3)
node _T_28 = bits(vcalloc_sel, 1, 1)
when _T_28 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].g, UInt<3>(0h3)
node _T_29 = bits(vcalloc_sel, 2, 2)
when _T_29 :
connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[2].g, UInt<3>(0h3)
inst salloc_arb of SwitchArbiter_112
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
node credit_available_hi = cat(states[0].vc_sel.`0`[2], states[0].vc_sel.`0`[1])
node _credit_available_T = cat(credit_available_hi, states[0].vc_sel.`0`[0])
node _credit_available_T_1 = cat(states[0].vc_sel.`1`[0], _credit_available_T)
node credit_available_hi_1 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1])
node _credit_available_T_2 = cat(credit_available_hi_1, io.out_credit_available.`0`[0])
node _credit_available_T_3 = cat(io.out_credit_available.`1`[0], _credit_available_T_2)
node _credit_available_T_4 = and(_credit_available_T_1, _credit_available_T_3)
node credit_available = neq(_credit_available_T_4, UInt<1>(0h0))
node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3))
node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available)
node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid)
connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2
connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0]
connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail
node _T_30 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid)
node _T_31 = and(_T_30, input_buffer.io.deq[0].bits.tail)
when _T_31 :
connect states[0].g, UInt<3>(0h0)
connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready
connect salloc_arb.io.in[1].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[1].bits.tail
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0]
connect salloc_arb.io.in[2].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[2].bits.tail
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[0]
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4)
node _io_debug_sa_stall_T_6 = add(_io_debug_sa_stall_T_3, _io_debug_sa_stall_T_5)
node _io_debug_sa_stall_T_7 = bits(_io_debug_sa_stall_T_6, 1, 0)
node _io_debug_sa_stall_T_8 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_7)
node _io_debug_sa_stall_T_9 = bits(_io_debug_sa_stall_T_8, 1, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_9
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
wire salloc_outs : { valid : UInt<1>, vid : UInt<2>, out_vid : UInt<2>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1]
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_5 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_7 = or(_io_in_vc_free_T_4, _io_in_vc_free_T_5)
node _io_in_vc_free_T_8 = or(_io_in_vc_free_T_7, _io_in_vc_free_T_6)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_8
node _io_in_vc_free_T_9 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_9, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_10
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 1, 0)
node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi)
node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo)
node _salloc_outs_0_vid_T_2 = bits(_salloc_outs_0_vid_T_1, 1, 1)
node _salloc_outs_0_vid_T_3 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_2)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T_3
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
wire vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[3]}
wire _vc_sel_WIRE : UInt<1>[3]
node _vc_sel_T_3 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_4 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_5 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_6 = or(_vc_sel_T_3, _vc_sel_T_4)
node _vc_sel_T_7 = or(_vc_sel_T_6, _vc_sel_T_5)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_7
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_11 = or(_vc_sel_T_8, _vc_sel_T_9)
node _vc_sel_T_12 = or(_vc_sel_T_11, _vc_sel_T_10)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_12
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
node _vc_sel_T_13 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_14 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_15 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_16 = or(_vc_sel_T_13, _vc_sel_T_14)
node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_15)
wire _vc_sel_WIRE_3 : UInt<1>
connect _vc_sel_WIRE_3, _vc_sel_T_17
connect _vc_sel_WIRE[2], _vc_sel_WIRE_3
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_4 : UInt<1>[1]
node _vc_sel_T_18 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_19 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_20 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_21 = or(_vc_sel_T_18, _vc_sel_T_19)
node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_20)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_22
connect _vc_sel_WIRE_4[0], _vc_sel_WIRE_5
connect vc_sel.`1`, _vc_sel_WIRE_4
node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1])
node channel_oh_0 = or(_channel_oh_T, vc_sel.`0`[2])
node virt_channel_hi = cat(vc_sel.`0`[2], vc_sel.`0`[1])
node _virt_channel_T = cat(virt_channel_hi, vc_sel.`0`[0])
node virt_channel_hi_1 = bits(_virt_channel_T, 2, 2)
node virt_channel_lo = bits(_virt_channel_T, 1, 0)
node _virt_channel_T_1 = orr(virt_channel_hi_1)
node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo)
node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1)
node _virt_channel_T_4 = cat(_virt_channel_T_1, _virt_channel_T_3)
node _virt_channel_T_5 = mux(channel_oh_0, _virt_channel_T_4, UInt<1>(0h0))
node _virt_channel_T_6 = mux(vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0))
node _virt_channel_T_7 = or(_virt_channel_T_5, _virt_channel_T_6)
wire virt_channel : UInt<2>
connect virt_channel, _virt_channel_T_7
node _T_32 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_32 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_4 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_6 = or(_salloc_outs_0_flit_payload_T_3, _salloc_outs_0_flit_payload_T_4)
node _salloc_outs_0_flit_payload_T_7 = or(_salloc_outs_0_flit_payload_T_6, _salloc_outs_0_flit_payload_T_5)
wire _salloc_outs_0_flit_payload_WIRE : UInt<145>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_7
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_4 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_6 = or(_salloc_outs_0_flit_head_T_3, _salloc_outs_0_flit_head_T_4)
node _salloc_outs_0_flit_head_T_7 = or(_salloc_outs_0_flit_head_T_6, _salloc_outs_0_flit_head_T_5)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_7
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_4 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_6 = or(_salloc_outs_0_flit_tail_T_3, _salloc_outs_0_flit_tail_T_4)
node _salloc_outs_0_flit_tail_T_7 = or(_salloc_outs_0_flit_tail_T_6, _salloc_outs_0_flit_tail_T_5)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_7
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_4 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_6 = or(_salloc_outs_0_flit_flow_T_3, _salloc_outs_0_flit_flow_T_4)
node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_6, _salloc_outs_0_flit_flow_T_5)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_7
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_11 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9)
node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_10)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_12
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_13, _salloc_outs_0_flit_flow_T_14)
node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_15)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<3>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_17
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_20 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_19)
node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_20)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_22
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24)
node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_25)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_27
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
connect states[0].vc_sel.`0`[0], UInt<1>(0h0)
connect states[0].vc_sel.`0`[1], UInt<1>(0h0)
connect states[0].vc_sel.`0`[2], UInt<1>(0h0)
invalidate states[1].fifo_deps
invalidate states[1].flow.egress_node_id
invalidate states[1].flow.egress_node
invalidate states[1].flow.ingress_node_id
invalidate states[1].flow.ingress_node
invalidate states[1].flow.vnet_id
invalidate states[1].vc_sel.`0`[0]
invalidate states[1].vc_sel.`0`[1]
invalidate states[1].vc_sel.`0`[2]
invalidate states[1].vc_sel.`1`[0]
invalidate states[1].g
invalidate states[2].fifo_deps
invalidate states[2].flow.egress_node_id
invalidate states[2].flow.egress_node
invalidate states[2].flow.ingress_node_id
invalidate states[2].flow.ingress_node
invalidate states[2].flow.vnet_id
invalidate states[2].vc_sel.`0`[0]
invalidate states[2].vc_sel.`0`[1]
invalidate states[2].vc_sel.`0`[2]
invalidate states[2].vc_sel.`1`[0]
invalidate states[2].g
node _T_33 = asUInt(reset)
when _T_33 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0)
connect states[2].g, UInt<3>(0h0) | module InputUnit_45( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_2, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [144:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [1:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [1:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [144:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [2:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [2:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire _GEN; // @[MixedVec.scala:116:9]
wire vcalloc_vals_0; // @[InputUnit.scala:266:25, :272:46, :273:29]
wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [2:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [1:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [144:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [144:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [144:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_0_g; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN_0 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_101 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node adjustedSig = shl(io.in.sig, 0)
node doShiftSigDown1 = bits(adjustedSig, 26, 26)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _roundMask_T = bits(io.in.sExp, 8, 0)
node _roundMask_T_1 = not(_roundMask_T)
node roundMask_msb = bits(_roundMask_T_1, 8, 8)
node roundMask_lsbs = bits(_roundMask_T_1, 7, 0)
node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7)
node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0)
node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2)
node _roundMask_T_2 = bits(roundMask_shift, 63, 42)
node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0)
node _roundMask_T_4 = shl(UInt<8>(0hff), 8)
node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4)
node _roundMask_T_6 = shr(_roundMask_T_3, 8)
node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5)
node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0)
node _roundMask_T_9 = shl(_roundMask_T_8, 8)
node _roundMask_T_10 = not(_roundMask_T_5)
node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10)
node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11)
node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0)
node _roundMask_T_14 = shl(_roundMask_T_13, 4)
node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14)
node _roundMask_T_16 = shr(_roundMask_T_12, 4)
node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15)
node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0)
node _roundMask_T_19 = shl(_roundMask_T_18, 4)
node _roundMask_T_20 = not(_roundMask_T_15)
node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20)
node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21)
node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0)
node _roundMask_T_24 = shl(_roundMask_T_23, 2)
node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24)
node _roundMask_T_26 = shr(_roundMask_T_22, 2)
node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25)
node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0)
node _roundMask_T_29 = shl(_roundMask_T_28, 2)
node _roundMask_T_30 = not(_roundMask_T_25)
node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30)
node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31)
node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0)
node _roundMask_T_34 = shl(_roundMask_T_33, 1)
node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34)
node _roundMask_T_36 = shr(_roundMask_T_32, 1)
node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35)
node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0)
node _roundMask_T_39 = shl(_roundMask_T_38, 1)
node _roundMask_T_40 = not(_roundMask_T_35)
node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40)
node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41)
node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16)
node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0)
node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0)
node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0)
node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1)
node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47)
node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2)
node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0)
node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1)
node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51)
node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52)
node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4)
node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0)
node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1)
node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56)
node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57)
node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58)
node _roundMask_T_60 = not(_roundMask_T_59)
node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60)
node _roundMask_T_62 = not(_roundMask_T_61)
node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7))
node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3)
node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0)
node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0)
node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0)
node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1)
node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67)
node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2)
node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69)
node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0))
node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71)
node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0))
node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1)
node roundMask = cat(_roundMask_T_74, UInt<2>(0h3))
node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask)
node shiftedRoundMask = shr(_shiftedRoundMask_T, 1)
node _roundPosMask_T = not(shiftedRoundMask)
node roundPosMask = and(_roundPosMask_T, roundMask)
node _roundPosBit_T = and(adjustedSig, roundPosMask)
node roundPosBit = orr(_roundPosBit_T)
node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask)
node anyRoundExtra = orr(_anyRoundExtra_T)
node anyRound = or(roundPosBit, anyRoundExtra)
node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit)
node _roundIncr_T_2 = and(roundMagUp, anyRound)
node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2)
node _roundedSig_T = or(adjustedSig, roundMask)
node _roundedSig_T_1 = shr(_roundedSig_T, 2)
node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1))
node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit)
node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0))
node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4)
node _roundedSig_T_6 = shr(roundMask, 1)
node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0))
node _roundedSig_T_8 = not(_roundedSig_T_7)
node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8)
node _roundedSig_T_10 = not(roundMask)
node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10)
node _roundedSig_T_12 = shr(_roundedSig_T_11, 2)
node _roundedSig_T_13 = and(roundingMode_odd, anyRound)
node _roundedSig_T_14 = shr(roundPosMask, 1)
node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0))
node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15)
node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16)
node _sRoundedExp_T = shr(roundedSig, 24)
node _sRoundedExp_T_1 = cvt(_sRoundedExp_T)
node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1)
node _common_expOut_T = bits(sRoundedExp, 8, 0)
connect common_expOut, _common_expOut_T
node _common_fractOut_T = bits(roundedSig, 23, 1)
node _common_fractOut_T_1 = bits(roundedSig, 22, 0)
node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
node _common_overflow_T = shr(sRoundedExp, 7)
node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3)))
connect common_overflow, _common_overflow_T_1
node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b)))
connect common_totalUnderflow, _common_totalUnderflow_T
node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2)
node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1)
node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1)
node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2)
node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T)
node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0)
node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2)
node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3)
node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit)
node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound)
node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2)
node _roundCarry_T = bits(roundedSig, 25, 25)
node _roundCarry_T_1 = bits(roundedSig, 24, 24)
node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1)
node _common_underflow_T = shr(io.in.sExp, 8)
node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0)))
node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1)
node _common_underflow_T_3 = bits(roundMask, 3, 3)
node _common_underflow_T_4 = bits(roundMask, 2, 2)
node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4)
node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5)
node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1))
node _common_underflow_T_8 = bits(roundMask, 4, 4)
node _common_underflow_T_9 = bits(roundMask, 3, 3)
node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9)
node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0))
node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11)
node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry)
node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit)
node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr)
node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0))
node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16)
node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17)
connect common_underflow, _common_underflow_T_18
node _common_inexact_T = or(common_totalUnderflow, anyRound)
connect common_inexact, _common_inexact_T
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_101( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20]
wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53]
wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38]
wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29]
wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42]
wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25]
wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26]
wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56]
wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22]
wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22]
wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20]
wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20]
wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20]
wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20]
wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20]
wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20]
wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}]
wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}]
wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17]
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56]
wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22]
wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20]
wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20]
wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20]
wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58]
wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24]
wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24]
wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67]
wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49]
wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31]
wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}]
wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46]
wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]
wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]
wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]
wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]
wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_54 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_EntryData_54( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_g, // @[package.scala:268:18]
output io_y_ae, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c, // @[package.scala:268:18]
output io_y_fragmented_superpage // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_g = io_y_g_0; // @[package.scala:267:30]
assign io_y_ae = io_y_ae_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_363 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_107
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<8>, clock
reg c2 : SInt<8>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h0), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node _c1_T = bits(io.in_d, 7, 0)
node _c1_T_1 = asSInt(_c1_T)
connect c1, _c1_T_1
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node _c2_T = bits(io.in_d, 7, 0)
node _c2_T_1 = asSInt(_c2_T)
connect c2, _c2_T_1
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h0), _T_4)
node _T_6 = or(UInt<1>(0h1), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_363( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_107 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_58 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_58( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
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