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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:34:41 10/06/2010
-- Design Name:
-- Module Name: SelAnodo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SelAnodo is
port (
Sel : in STD_LOGIC_VECTOR (1 downto 0);
Anodo : out STD_LOGIC_VECTOR (3 downto 0));
end SelAnodo;
architecture Behavioral of SelAnodo is
begin
--Seleccion de display
with Sel select
Anodo <= "1110" when "00",
"1101" when "01",
"1011" when "10",
"0111" when others;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:34:41 10/06/2010
-- Design Name:
-- Module Name: SelAnodo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SelAnodo is
port (
Sel : in STD_LOGIC_VECTOR (1 downto 0);
Anodo : out STD_LOGIC_VECTOR (3 downto 0));
end SelAnodo;
architecture Behavioral of SelAnodo is
begin
--Seleccion de display
with Sel select
Anodo <= "1110" when "00",
"1101" when "01",
"1011" when "10",
"0111" when others;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:34:41 10/06/2010
-- Design Name:
-- Module Name: SelAnodo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SelAnodo is
port (
Sel : in STD_LOGIC_VECTOR (1 downto 0);
Anodo : out STD_LOGIC_VECTOR (3 downto 0));
end SelAnodo;
architecture Behavioral of SelAnodo is
begin
--Seleccion de display
with Sel select
Anodo <= "1110" when "00",
"1101" when "01",
"1011" when "10",
"0111" when others;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:34:41 10/06/2010
-- Design Name:
-- Module Name: SelAnodo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SelAnodo is
port (
Sel : in STD_LOGIC_VECTOR (1 downto 0);
Anodo : out STD_LOGIC_VECTOR (3 downto 0));
end SelAnodo;
architecture Behavioral of SelAnodo is
begin
--Seleccion de display
with Sel select
Anodo <= "1110" when "00",
"1101" when "01",
"1011" when "10",
"0111" when others;
end Behavioral;
|
-- Revision history:
-- 2015-08-12 Lukas Jaeger created
-- 2015-08-16 Lukas Jaeger fixed all bugs and made it working with the cpu
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library WORK;
use WORK.all;
entity cpu_control is
port(
clk : in std_logic;
rst : in std_logic;
rd_mask : out std_logic_vector(3 downto 0);
wr_mask : out std_logic_vector(3 downto 0);
instr_stall : in std_logic;
data_stall : in std_logic;
instr_in : in std_logic_vector(31 downto 0);
alu_op : out std_logic_vector(5 downto 0);
exc_mux1 : out std_logic_vector(1 downto 0);
exc_mux2 : out std_logic_vector(1 downto 0);
exc_alu_zero : in std_logic_vector(0 downto 0);
memstg_mux : out std_logic;
id_regdest_mux : out std_logic_vector (1 downto 0);
id_regshift_mux : out std_logic_vector (1 downto 0);
id_enable_regs : out std_logic;
in_mux_pc : out std_logic;
stage_control : out std_logic_vector (4 downto 0)
);
end entity cpu_control;
architecture structure_cpu_control of cpu_control is
signal instr_1, instr_2, instr_3, instr_4: std_logic_vector (31 downto 0);
begin
pipeline: process(clk, rst) is
begin
if (rst = '1') then
instr_1 <= x"00000000";
instr_2 <= x"00000000";
instr_3 <= x"00000000";
instr_4 <= x"00000000";
elsif (rising_edge(clk) and instr_stall /= '1' and data_stall /= '1') then
instr_1 <= instr_in;
instr_2 <= instr_1;
instr_3 <= instr_2;
instr_4 <= instr_3;
end if;
end process;
id: process (instr_1) is
begin
if (instr_1(31 downto 26) = "000000") then -- R-type instructions
id_regdest_mux <= "00";
id_regshift_mux <= "00";
if (instr_1(20 downto 0) = "000000000000000001000") then -- JR-instruction
in_mux_pc <= '1';
else
in_mux_pc <= '0';
end if;
else -- I-Type- and J-Type instructions. They can go together, because nobody cares about
-- the alu-result of a J-Type, so it does not matter, which value is yielded to ex
id_regdest_mux <= "10";
if (instr_1(31 downto 26) = "001111") then -- LUI needs a shift
id_regshift_mux <= "01";
elsif ((instr_1(31 downto 26) = "000010") -- J
or (instr_1 (31 downto 26) = "000011") -- JAL
or (instr_1 (31 downto 26) = "011101") -- JALX
or (instr_1 (31 downto 26) = "000100") -- BEQ
or (instr_1 (31 downto 26) = "000001") -- BGEZ
or (instr_1 (31 downto 26) = "000111") -- BGTZ
or (instr_1 (31 downto 26) = "000110") -- BLEZ
or (instr_1 (31 downto 26) = "000101") -- BEQZ
) then
id_regshift_mux <= "00";
in_mux_pc <= '1';
else
id_regshift_mux <= "00";
in_mux_pc <= '0';
end if;
end if;
end process;
ex: process (instr_2) is
begin
if (instr_2 (31 downto 26) = "001111") then --LUI
exc_mux1 <= "00";
exc_mux2 <= "01";
alu_op <="000100";
elsif ((instr_2 (31 downto 26) = "001001") --ADDIU
or (instr_2 (31 downto 26) = "100011") --LW
or (instr_2 (31 downto 26) = "101011") --SW
or (instr_2 (31 downto 26) = "101000") --SB
or (instr_2 (31 downto 26) = "100100") --LBU
)then
exc_mux1 <="10";
exc_mux2 <="01";
alu_op <="100000";
elsif (instr_2 (31 downto 26) = "001010") then --SLTI
exc_mux1 <="10";
exc_mux2 <="01";
alu_op <="001000";
elsif (instr_2 (31 downto 26) = "001100") then --ANDI
exc_mux1 <="10";
exc_mux2 <="01";
alu_op <="100100";
elsif (instr_2 (31 downto 26) = "001101") then --ORI
exc_mux1 <="10";
exc_mux2 <="01";
alu_op <="100101";
elsif ((instr_2 (31 downto 26) = "000000") and (instr_2(10 downto 0) = "00000101010")) then
exc_mux1 <= "10";
exc_mux2 <= "00";
alu_op <= "001000";
else --if (instr_2 (31 downto 26) = "000000") then -- NOP and other R-types and Ops, where the result does not matter
exc_mux1 <= "10";
exc_mux2 <= "00";
alu_op <= "000100";
end if;
end process;
mem: process (instr_3) is
begin
if (instr_3 (31 downto 26) = "100011") then --LW
memstg_mux <= '1';
rd_mask <= "1111";
wr_mask <= "0000";
elsif (instr_3 (31 downto 26) = "100100") then --LBU
memstg_mux <= '1';
rd_mask <= "0001";
wr_mask <= "0000";
elsif (instr_3 (31 downto 26) = "101011") then --SW
memstg_mux <= '0';
rd_mask <= "0000";
wr_mask <= "1111";
elsif (instr_3 (31 downto 26) = "101000") then --SB
memstg_mux <= '0';
rd_mask <= "0000";
wr_mask <= "0001";
else
memstg_mux <= '0';
rd_mask <= "0000";
wr_mask <= "0000";
end if;
end process;
wb: process (instr_4) is
begin
if ((instr_4 (31 downto 26) = "001111") or --LUI
(instr_4 (31 downto 26) = "001001") or --ADDIU
(instr_4 (31 downto 26) = "100011") or --LW
(instr_4 (31 downto 26) = "100100") or --LBU
(instr_4 (31 downto 26) = "001010") or --SLTI
(instr_4 (31 downto 26) = "001100") or --ANDI
(instr_4 (31 downto 26) = "001101") or --ORI
(instr_4 (31 downto 26) = "000000") and (instr_4(10 downto 0) = "00000101010")) --SLT
) then
id_enable_regs <= '1';
else
id_enable_regs <= '0';
end if;
end process;
stall: process (data_stall, instr_stall) is
begin
if (data_stall = '1' or instr_stall = '1') then
stage_control <= "00000";
else
stage_control <= "11111";
end if;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1425.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s06b00x00p05n01i01425ent IS
END c08s06b00x00p05n01i01425ent;
ARCHITECTURE c08s06b00x00p05n01i01425arch OF c08s06b00x00p05n01i01425ent IS
procedure assert_same_int ( variable v1, v2 : in integer := 0 ) is
--
-- This procedure compares the value of the first argument
-- into the second argument and prints an assertion message
-- if they are the same.
--
begin
assert NOT(v1 = v2)
report "***PASSED TEST: c08s06b00x00p05n01i01425"
severity NOTE;
assert (v1 = v2)
report "***FAILED TEST: c08s06b00x00p05n01i01425 - Procedure call without an actual parameter part is permitted."
severity ERROR;
end assert_same_int;
BEGIN
TESTING : PROCESS
variable v1 : integer := 1;
BEGIN
--
-- Try without any parameters; the procedure should
-- use the default values for the arguments.
--
v1 := 5;
assert_same_int;
wait;
END PROCESS TESTING;
END c08s06b00x00p05n01i01425arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1425.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s06b00x00p05n01i01425ent IS
END c08s06b00x00p05n01i01425ent;
ARCHITECTURE c08s06b00x00p05n01i01425arch OF c08s06b00x00p05n01i01425ent IS
procedure assert_same_int ( variable v1, v2 : in integer := 0 ) is
--
-- This procedure compares the value of the first argument
-- into the second argument and prints an assertion message
-- if they are the same.
--
begin
assert NOT(v1 = v2)
report "***PASSED TEST: c08s06b00x00p05n01i01425"
severity NOTE;
assert (v1 = v2)
report "***FAILED TEST: c08s06b00x00p05n01i01425 - Procedure call without an actual parameter part is permitted."
severity ERROR;
end assert_same_int;
BEGIN
TESTING : PROCESS
variable v1 : integer := 1;
BEGIN
--
-- Try without any parameters; the procedure should
-- use the default values for the arguments.
--
v1 := 5;
assert_same_int;
wait;
END PROCESS TESTING;
END c08s06b00x00p05n01i01425arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1425.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s06b00x00p05n01i01425ent IS
END c08s06b00x00p05n01i01425ent;
ARCHITECTURE c08s06b00x00p05n01i01425arch OF c08s06b00x00p05n01i01425ent IS
procedure assert_same_int ( variable v1, v2 : in integer := 0 ) is
--
-- This procedure compares the value of the first argument
-- into the second argument and prints an assertion message
-- if they are the same.
--
begin
assert NOT(v1 = v2)
report "***PASSED TEST: c08s06b00x00p05n01i01425"
severity NOTE;
assert (v1 = v2)
report "***FAILED TEST: c08s06b00x00p05n01i01425 - Procedure call without an actual parameter part is permitted."
severity ERROR;
end assert_same_int;
BEGIN
TESTING : PROCESS
variable v1 : integer := 1;
BEGIN
--
-- Try without any parameters; the procedure should
-- use the default values for the arguments.
--
v1 := 5;
assert_same_int;
wait;
END PROCESS TESTING;
END c08s06b00x00p05n01i01425arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 16:20:42 06/01/2011
-- Design Name:
-- Module Name: IPv4_TX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP TX
-- doesnt handle segmentation
-- dest MAC addr resolution through ARP layer
-- Handle IPv4 protocol
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - fixed up setting of tx_result control defaults
-- Revision 0.03 - Added data_out_first
-- Revision 0.04 - Added handling of broadcast address
-- Revision 0.05 - Fix cks calc when add of high bits causes another ovf
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity IPv4_TX is
port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
-- system signals
clk : in std_logic; -- same clock used to clock mac data and ip data
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- ARP lookup signals
arp_req_req : out arp_req_req_type;
arp_req_rslt : in arp_req_rslt_type;
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
mac_data_out_ready : in std_logic; -- indicates system ready to consume data
mac_data_out_valid : out std_logic; -- indicates data out is valid
mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
);
end IPv4_TX;
architecture Behavioral of IPv4_TX is
type tx_state_type is (
IDLE,
WAIT_MAC, -- waiting for response from ARP for mac lookup
WAIT_CHN, -- waiting for tx access to MAC channel
SEND_ETH_HDR, -- sending the ethernet header
SEND_IP_HDR, -- sending the IP header
SEND_USER_DATA -- sending the users data
);
type crc_state_type is (IDLE, TOT_LEN, ID, FLAGS, TTL, CKS, SAH, SAL, DAH, DAL, ADDOVF, FINAL, WAIT_END);
type count_mode_type is (RST, INCR, HOLD);
type settable_cnt_type is (RST, SET, INCR, HOLD);
type set_clr_type is (SET, CLR, HOLD);
-- Configuration
constant IP_TTL : std_logic_vector (7 downto 0) := x"80";
-- TX state variables
signal tx_state : tx_state_type;
signal tx_count : unsigned (11 downto 0);
signal tx_result_reg : std_logic_vector (1 downto 0);
signal tx_mac : std_logic_vector (47 downto 0);
signal tx_mac_chn_reqd : std_logic;
signal tx_hdr_cks : std_logic_vector (23 downto 0);
signal mac_lookup_req : std_logic;
signal crc_state : crc_state_type;
signal arp_req_ip_reg : std_logic_vector (31 downto 0);
signal mac_data_out_ready_reg : std_logic;
-- tx control signals
signal next_tx_state : tx_state_type;
signal set_tx_state : std_logic;
signal next_tx_result : std_logic_vector (1 downto 0);
signal set_tx_result : std_logic;
signal tx_mac_value : std_logic_vector (47 downto 0);
signal set_tx_mac : std_logic;
signal tx_count_val : unsigned (11 downto 0);
signal tx_count_mode : settable_cnt_type;
signal tx_data : std_logic_vector (7 downto 0);
signal set_last : std_logic;
signal set_chn_reqd : set_clr_type;
signal set_mac_lku_req : set_clr_type;
signal tx_data_valid : std_logic; -- indicates whether data is valid to tx or not
-- tx temp signals
signal total_length : std_logic_vector (15 downto 0); -- computed combinatorially from header size
function inv_if_one(s1 : std_logic_vector; en : std_logic) return std_logic_vector is
--this function inverts all the bits of a vector if
--'en' is '1'.
variable Z : std_logic_vector(s1'high downto s1'low);
begin
for i in (s1'low) to s1'high loop
Z(i) := en xor s1(i);
end loop;
return Z;
end inv_if_one; -- end function
-- IP datagram header format
--
-- 0 4 8 16 19 24 31
-- --------------------------------------------------------------------------------------------
-- | Version | *Header | Service Type | Total Length including header |
-- | (4) | Length | (ignored) | (in bytes) |
-- --------------------------------------------------------------------------------------------
-- | Identification | Flags | Fragment Offset |
-- | | | (in 32 bit words) |
-- --------------------------------------------------------------------------------------------
-- | Time To Live | Protocol | Header Checksum |
-- | (ignored) | | |
-- --------------------------------------------------------------------------------------------
-- | Source IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Destination IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Options (if any - ignored) | Padding |
-- | | (if needed) |
-- --------------------------------------------------------------------------------------------
-- | Data |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
--
-- * - in 32 bit words
begin
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
tx_combinatorial : process(
-- input signals
ip_tx_start, ip_tx, our_ip_address, our_mac_address, arp_req_rslt, --clk,
mac_tx_granted, mac_data_out_ready,
-- state variables
tx_state, tx_count, tx_result_reg, tx_mac, tx_mac_chn_reqd,
mac_lookup_req, tx_hdr_cks, arp_req_ip_reg, mac_data_out_ready_reg,
-- control signals
next_tx_state, set_tx_state, next_tx_result, set_tx_result, tx_mac_value, set_tx_mac, tx_count_mode,
tx_data, set_last, set_chn_reqd, set_mac_lku_req, total_length,
tx_data_valid, tx_count_val
)
begin
-- set output followers
ip_tx_result <= tx_result_reg;
mac_tx_req <= tx_mac_chn_reqd;
arp_req_req.lookup_req <= mac_lookup_req;
arp_req_req.ip <= arp_req_ip_reg;
-- set initial values for combinatorial outputs
mac_data_out_first <= '0';
case tx_state is
when SEND_ETH_HDR | SEND_IP_HDR =>
mac_data_out <= tx_data;
tx_data_valid <= mac_data_out_ready; -- generated internally
mac_data_out_last <= set_last;
when SEND_USER_DATA =>
mac_data_out <= ip_tx.data.data_out;
tx_data_valid <= ip_tx.data.data_out_valid;
mac_data_out_last <= ip_tx.data.data_out_last;
when others =>
mac_data_out <= (others => '0');
tx_data_valid <= '0'; -- not transmitting during this phase
mac_data_out_last <= '0';
end case;
mac_data_out_valid <= tx_data_valid and mac_data_out_ready;
-- set signal defaults
next_tx_state <= IDLE;
set_tx_state <= '0';
tx_count_mode <= HOLD;
tx_data <= x"00";
set_last <= '0';
set_tx_mac <= '0';
set_chn_reqd <= HOLD;
set_mac_lku_req <= HOLD;
next_tx_result <= IPTX_RESULT_NONE;
set_tx_result <= '0';
tx_count_val <= (others => '0');
tx_mac_value <= (others => '0');
-- set temp signals
total_length <= std_logic_vector(unsigned(ip_tx.hdr.data_length) + 20); -- total length = user data length + header length (bytes)
-- TX FSM
case tx_state is
when IDLE =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
tx_count_mode <= RST;
set_chn_reqd <= CLR;
if ip_tx_start = '1' then
-- check header count for error if too high
if unsigned(ip_tx.hdr.data_length) > 8980 then --1480
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
else
next_tx_result <= IPTX_RESULT_SENDING;
set_tx_result <= '1';
-- TODO - check if we already have the mac addr for this ip, if so, bypass the WAIT_MAC state
if ip_tx.hdr.dst_ip_addr = IP_BC_ADDR then
-- for IP broadcast, dont need to look up the MAC addr
tx_mac_value <= MAC_BC_ADDR;
set_tx_mac <= '1';
next_tx_state <= WAIT_CHN;
set_tx_state <= '1';
else
-- need to req the mac address for this ip
set_mac_lku_req <= SET;
next_tx_state <= WAIT_MAC;
set_tx_state <= '1';
end if;
end if;
else
set_mac_lku_req <= CLR;
end if;
when WAIT_MAC =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
set_mac_lku_req <= CLR; -- clear the request - will have been latched in the ARP layer
-- if arp_req_rslt.got_mac = '1' then
-- save the MAC we got back from the ARP lookup
tx_mac_value <= arp_req_rslt.mac;
set_tx_mac <= '1';
set_chn_reqd <= SET;
-- check for optimise when already have the channel
-- if mac_tx_granted = '1' then
-- ready to send data
next_tx_state <= SEND_ETH_HDR;
set_tx_state <= '1';
-- else
-- next_tx_state <= WAIT_CHN;
-- set_tx_state <= '1';
-- end if;
-- elsif arp_req_rslt.got_err = '1' then
-- set_mac_lku_req <= CLR;
-- next_tx_result <= IPTX_RESULT_ERR;
-- set_tx_result <= '1';
-- next_tx_state <= IDLE;
-- set_tx_state <= '1';
-- end if;
when WAIT_CHN =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if mac_tx_granted = '1' then
-- ready to send data
next_tx_state <= SEND_ETH_HDR;
set_tx_state <= '1';
end if;
-- probably should handle a timeout here
when SEND_ETH_HDR =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if mac_data_out_ready = '1' then
if tx_count = x"00d" then
tx_count_mode <= RST;
next_tx_state <= SEND_IP_HDR;
set_tx_state <= '1';
else
tx_count_mode <= INCR;
end if;
case tx_count is
when x"000" =>
mac_data_out_first <= mac_data_out_ready;
tx_data <= tx_mac (47 downto 40); -- trg = mac from ARP lookup
when x"001" => tx_data <= tx_mac (39 downto 32);
when x"002" => tx_data <= tx_mac (31 downto 24);
when x"003" => tx_data <= tx_mac (23 downto 16);
when x"004" => tx_data <= tx_mac (15 downto 8);
when x"005" => tx_data <= tx_mac (7 downto 0);
when x"006" => tx_data <= our_mac_address (47 downto 40); -- src = our mac
when x"007" => tx_data <= our_mac_address (39 downto 32);
when x"008" => tx_data <= our_mac_address (31 downto 24);
when x"009" => tx_data <= our_mac_address (23 downto 16);
when x"00a" => tx_data <= our_mac_address (15 downto 8);
when x"00b" => tx_data <= our_mac_address (7 downto 0);
when x"00c" => tx_data <= x"08"; -- pkt type = 0800 : IP
when x"00d" => tx_data <= x"00";
when others =>
-- shouldnt get here - handle as error
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
end case;
end if;
when SEND_IP_HDR =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if mac_data_out_ready = '1' then
if tx_count = x"013" then
tx_count_val <= x"001";
tx_count_mode <= SET;
next_tx_state <= SEND_USER_DATA;
set_tx_state <= '1';
else
tx_count_mode <= INCR;
end if;
case tx_count is
when x"000" => tx_data <= x"45"; -- v4, 5 words in hdr
when x"001" => tx_data <= x"00"; -- service type
when x"002" => tx_data <= total_length (15 downto 8); -- total length
when x"003" => tx_data <= total_length (7 downto 0);
when x"004" => tx_data <= x"00"; -- identification
when x"005" => tx_data <= x"00";
when x"006" => tx_data <= x"00"; -- flags and fragment offset
when x"007" => tx_data <= x"00";
when x"008" => tx_data <= IP_TTL; -- TTL
when x"009" => tx_data <= ip_tx.hdr.protocol; -- protocol
when x"00a" => tx_data <= tx_hdr_cks (15 downto 8); -- HDR checksum
when x"00b" => tx_data <= tx_hdr_cks (7 downto 0); -- HDR checksum
when x"00c" => tx_data <= our_ip_address (31 downto 24); -- src ip
when x"00d" => tx_data <= our_ip_address (23 downto 16);
when x"00e" => tx_data <= our_ip_address (15 downto 8);
when x"00f" => tx_data <= our_ip_address (7 downto 0);
when x"010" => tx_data <= ip_tx.hdr.dst_ip_addr (31 downto 24); -- dst ip
when x"011" => tx_data <= ip_tx.hdr.dst_ip_addr (23 downto 16);
when x"012" => tx_data <= ip_tx.hdr.dst_ip_addr (15 downto 8);
when x"013" => tx_data <= ip_tx.hdr.dst_ip_addr (7 downto 0);
when others =>
-- shouldnt get here - handle as error
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
end case;
end if;
when SEND_USER_DATA =>
ip_tx_data_out_ready <= mac_data_out_ready;-- and mac_data_out_ready_reg; -- in this state, we are always ready to accept user data for tx
if mac_data_out_ready = '1' then
if ip_tx.data.data_out_valid = '1' or tx_count = x"000" then
-- only increment if ready and valid has been subsequently established, otherwise data count moves on too fast
if unsigned(tx_count) = unsigned(ip_tx.hdr.data_length) then
-- TX terminated due to count - end normally
set_last <= '1';
set_chn_reqd <= CLR;
tx_data <= ip_tx.data.data_out;
next_tx_result <= IPTX_RESULT_SENT;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
if ip_tx.data.data_out_last = '0' then
next_tx_result <= IPTX_RESULT_ERR;
end if;
elsif ip_tx.data.data_out_last = '1' then
-- TX terminated due to receiving last indication from upstream - end with error
set_last <= '1';
set_chn_reqd <= CLR;
tx_data <= ip_tx.data.data_out;
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
else
-- TX continues
tx_count_mode <= INCR;
tx_data <= ip_tx.data.data_out;
end if;
end if;
end if;
end case;
end process;
-----------------------------------------------------------------------------
-- sequential process to action control signals and change states and outputs
-----------------------------------------------------------------------------
tx_sequential : process (clk)--, reset, mac_data_out_ready_reg)
begin
-- if rising_edge(clk) then
-- mac_data_out_ready_reg <= mac_data_out_ready;
-- else
-- mac_data_out_ready_reg <= mac_data_out_ready_reg;
-- end if;
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
tx_state <= IDLE;
tx_count <= x"000";
tx_result_reg <= IPTX_RESULT_NONE;
tx_mac <= (others => '0');
tx_mac_chn_reqd <= '0';
mac_lookup_req <= '0';
else
-- Next tx_state processing
if set_tx_state = '1' then
tx_state <= next_tx_state;
else
tx_state <= tx_state;
end if;
-- tx result processing
if set_tx_result = '1' then
tx_result_reg <= next_tx_result;
else
tx_result_reg <= tx_result_reg;
end if;
-- control arp lookup request
case set_mac_lku_req is
when SET =>
arp_req_ip_reg <= ip_tx.hdr.dst_ip_addr;
mac_lookup_req <= '1';
when CLR =>
mac_lookup_req <= '0';
arp_req_ip_reg <= arp_req_ip_reg;
when HOLD =>
mac_lookup_req <= mac_lookup_req;
arp_req_ip_reg <= arp_req_ip_reg;
end case;
-- save MAC
if set_tx_mac = '1' then
tx_mac <= tx_mac_value;
else
tx_mac <= tx_mac;
end if;
-- control access request to mac tx chn
case set_chn_reqd is
when SET => tx_mac_chn_reqd <= '1';
when CLR => tx_mac_chn_reqd <= '0';
when HOLD => tx_mac_chn_reqd <= tx_mac_chn_reqd;
end case;
-- tx_count processing
case tx_count_mode is
when RST => tx_count <= x"000";
when SET => tx_count <= tx_count_val;
when INCR => tx_count <= tx_count + 1;
when HOLD => tx_count <= tx_count;
end case;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Process to calculate CRC in parallel with pkt out processing
-- this process must yield a valid CRC before it is required to be used in the hdr
-----------------------------------------------------------------------------
crc : process (clk)--, reset)
begin
if rising_edge(clk) then
case crc_state is
when IDLE =>
if ip_tx_start = '1' then
tx_hdr_cks <= x"004500"; -- vers & hdr len & service
crc_state <= TOT_LEN;
end if;
when TOT_LEN =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(total_length));
crc_state <= ID;
when ID =>
tx_hdr_cks <= tx_hdr_cks;
crc_state <= FLAGS;
when FLAGS =>
tx_hdr_cks <= tx_hdr_cks;
crc_state <= TTL;
when TTL =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(IP_TTL & ip_tx.hdr.protocol));
crc_state <= CKS;
when CKS =>
tx_hdr_cks <= tx_hdr_cks;
crc_state <= SAH;
when SAH =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(our_ip_address(31 downto 16)));
crc_state <= SAL;
when SAL =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(our_ip_address(15 downto 0)));
crc_state <= DAH;
when DAH =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(ip_tx.hdr.dst_ip_addr(31 downto 16)));
crc_state <= DAL;
when DAL =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(ip_tx.hdr.dst_ip_addr(15 downto 0)));
crc_state <= ADDOVF;
when ADDOVF =>
tx_hdr_cks <= std_logic_vector ((unsigned(tx_hdr_cks) and x"00ffff")+ unsigned(tx_hdr_cks(23 downto 16)));
crc_state <= FINAL;
when FINAL =>
tx_hdr_cks <= inv_if_one(std_logic_vector (unsigned(tx_hdr_cks) + unsigned(tx_hdr_cks(23 downto 16))), '1');
crc_state <= WAIT_END;
when WAIT_END =>
tx_hdr_cks <= tx_hdr_cks;
if ip_tx_start = '0' then
crc_state <= IDLE;
else
crc_state <= WAIT_END;
end if;
end case;
end if;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file xsd_ram.vhd when simulating
-- the core, xsd_ram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY xsd_ram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END xsd_ram;
ARCHITECTURE xsd_ram_a OF xsd_ram IS
-- synthesis translate_off
COMPONENT wrapped_xsd_ram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_xsd_ram USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 11,
c_addrb_width => 11,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 2048,
c_read_depth_b => 2048,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 2048,
c_write_depth_b => 2048,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_xsd_ram
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END xsd_ram_a;
|
architecture RTL of FIFO is
attribute Component_symbol of Comp_1 [name1, name2 return integer], Comp2 [name3, name4 return std_logic], Comp3 [name5, name6 return std_logic_vector] : component is "Counter_16";
attribute Component_symbol of Comp_1 [name1, name2 return integer] : component is "Counter_16";
attribute Component_symbol of Comp_1 : component is "Counter_16";
attribute Coordinate of Comp_1: component is (0.0, 17.5);
attribute Pin_code of Sig_1: signal is 17;
attribute Max_delay of Const_1: constant is 10 ns;
begin
end architecture RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2915.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p03n01i02915ent IS
END c02s01b01x02p03n01i02915ent;
ARCHITECTURE c02s01b01x02p03n01i02915arch OF c02s01b01x02p03n01i02915ent IS
procedure proc1 (signal S1: out bit) is
variable V1 : boolean;
begin
-- Failure_here : attribute STABLE may not be read within a procedure
V1 := S1'STABLE;
end proc1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x02p03n01i02915 - The attribute STABLE of formal signal parameters can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p03n01i02915arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2915.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p03n01i02915ent IS
END c02s01b01x02p03n01i02915ent;
ARCHITECTURE c02s01b01x02p03n01i02915arch OF c02s01b01x02p03n01i02915ent IS
procedure proc1 (signal S1: out bit) is
variable V1 : boolean;
begin
-- Failure_here : attribute STABLE may not be read within a procedure
V1 := S1'STABLE;
end proc1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x02p03n01i02915 - The attribute STABLE of formal signal parameters can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p03n01i02915arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2915.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p03n01i02915ent IS
END c02s01b01x02p03n01i02915ent;
ARCHITECTURE c02s01b01x02p03n01i02915arch OF c02s01b01x02p03n01i02915ent IS
procedure proc1 (signal S1: out bit) is
variable V1 : boolean;
begin
-- Failure_here : attribute STABLE may not be read within a procedure
V1 := S1'STABLE;
end proc1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x02p03n01i02915 - The attribute STABLE of formal signal parameters can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p03n01i02915arch;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Mon Sep 25 13:52:36 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_ila_stub.vhdl
-- Design : dbg_ila
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe6 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe7 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe8 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe9 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe10 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe11 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe12 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe13 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe14 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe15 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe16 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe17 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe18 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe19 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe20 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe21 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe22 : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[7:0],probe19[7:0],probe20[0:0],probe21[31:0],probe22[31:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2016.3";
begin
end;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
rst_s_wr3 <= '0';
rst_s_rd <= '0';
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 64,
C_DOUT_WIDTH => 64,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 64,
C_DIN_WIDTH => 64,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 64,
C_DIN_WIDTH => 64,
C_WR_PNTR_WIDTH => 10,
C_RD_PNTR_WIDTH => 10,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : fifo_fwft_64x1024_top
PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter_BCD is
port( clock_enable: in std_logic;
clock: in std_logic;
reset: in std_logic;
output: out std_logic_vector(0 to 3));
end counter_BCD;
architecture behavioral of counter_BCD is
signal temp: std_logic_vector(0 to 3);
begin
process(clock, reset)
begin
if reset='1' then
temp <= "0000";
elsif(clock'event and clock='1') then
if (clock_enable = '0') then
if temp = "1010" then
temp <= "0000";
else
temp <= temp + 1;
end if;
end if;
end if;
end process;
output <= temp;
end behavioral; |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:48:20 04/08/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/Project1/ALU_tb.vhd
-- Project Name: Project1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ALU_Toplevel
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ALU_tb IS
END ALU_tb;
ARCHITECTURE behavior OF ALU_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU_Toplevel
PORT(
RA : IN std_logic_vector(15 downto 0);
RB : IN std_logic_vector(15 downto 0);
OP : IN std_logic_vector(3 downto 0);
CLK : IN std_logic;
ALU_OUT : OUT std_logic_vector(15 downto 0);
SREG : OUT std_logic_vector(3 downto 0);
LDST_DAT : OUT std_logic_vector(15 downto 0);
LDST_ADR : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal RA : std_logic_vector(15 downto 0) := (others => '0');
signal RB : std_logic_vector(15 downto 0) := (others => '0');
signal OP : std_logic_vector(3 downto 0) := (others => '0');
signal CLK : std_logic := '0';
--Outputs
signal ALU_OUT : std_logic_vector(15 downto 0);
signal SREG : std_logic_vector(3 downto 0);
signal LDST_DAT : std_logic_vector(15 downto 0);
signal LDST_ADR : std_logic_vector(15 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU_Toplevel PORT MAP (
RA => RA,
RB => RB,
OP => OP,
CLK => CLK,
ALU_OUT => ALU_OUT,
SREG => SREG,
LDST_DAT => LDST_DAT,
LDST_ADR => LDST_ADR
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK_period*10;
OP <= "0000";
RA <= X"0001";
RB <= X"0004";
wait for CLK_period;
OP <= X"A";
wait for CLK_period;
OP <= X"9";
-- insert stimulus here
wait;
end process;
END;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity WDT_MOD is
generic (
-- IO-REQ: 1 DWORD
WB_CONF_OFFSET: std_logic_vector(15 downto 2) := "00000000000000";
WB_CONF_DATA: std_logic_vector(15 downto 0) := "0000000000000001";
WB_ADDR_OFFSET: std_logic_vector(15 downto 2) := "00000000000000"
);
port (
WB_CLK: in std_logic;
WB_RST: in std_logic;
WB_ADDR: in std_logic_vector(15 downto 2);
WB_DATA_OUT: out std_logic_vector(31 downto 0);
WB_DATA_IN: in std_logic_vector(31 downto 0);
WB_STB_RD: in std_logic;
WB_STB_WR: in std_logic;
RUN: out std_logic;
OUT_EN: out std_logic
);
end;
architecture rtl of WDT_MOD is
constant RAND_SEED: std_logic_vector(15 downto 0) := "1111111111111000";
signal wb_data_mux : std_logic_vector(31 downto 0);
signal rand: std_logic_vector(15 downto 0) := RAND_SEED;
signal rand_ok: std_logic;
signal out_en_reg: std_logic;
signal timer: std_logic_vector(19 downto 0);
signal timeout: std_logic;
signal cycle_cnt: std_logic_vector(3 downto 0) := (others => '1');
signal cycle_ok: std_logic;
begin
----------------------------------------------------------
--- bus logic
----------------------------------------------------------
P_WB_RD : process(WB_ADDR)
begin
case WB_ADDR is
when WB_CONF_OFFSET =>
wb_data_mux(15 downto 0) <= WB_CONF_DATA;
wb_data_mux(31 downto 16) <= WB_ADDR_OFFSET & "00";
when WB_ADDR_OFFSET =>
wb_data_mux <= (others => '0');
wb_data_mux(15 downto 0) <= rand;
wb_data_mux(16) <= out_en_reg;
when others =>
wb_data_mux <= (others => '0');
end case;
end process;
P_WB_RD_REG : process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
WB_DATA_OUT <= (others => '0');
elsif rising_edge(WB_CLK) then
if WB_STB_RD = '1' then
WB_DATA_OUT <= wb_data_mux;
end if;
end if;
end process;
P_PE_REG_WR : process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
out_en_reg <= '0';
rand <= RAND_SEED;
rand_ok <= '0';
elsif rising_edge(WB_CLK) then
rand_ok <= '0';
if WB_STB_WR = '1' then
case WB_ADDR is
when WB_ADDR_OFFSET =>
out_en_reg <= WB_DATA_IN(16);
if (WB_DATA_IN(15 downto 0) = rand) then
rand_ok <= '1';
end if;
rand <= rand(14 downto 0) & (rand(15) xor rand(10));
when others =>
end case;
end if;
end if;
end process;
----------------------------------------------------------
--- watchdog
----------------------------------------------------------
-- Timeout
P_WDT: process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
timer <= (others => '0');
elsif rising_edge(WB_CLK) then
if rand_ok = '1' then
timer <= (others => '1');
elsif timeout = '0' then
timer <= timer - 1;
end if;
end if;
end process;
timeout <= '1' when timer = 0 else '0';
-- initial cycle counter
P_CYCLE_CNT: process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
cycle_cnt <= (others => '1');
elsif rising_edge(WB_CLK) then
if timeout = '1' then
cycle_cnt <= (others => '1');
elsif rand_ok = '1' and cycle_ok = '0' then
cycle_cnt <= cycle_cnt - 1;
end if;
end if;
end process;
cycle_ok <= '1' when cycle_cnt = 0 else '0';
-- set outputs
RUN <= cycle_ok;
OUT_EN <= out_en_reg and cycle_ok;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
|
-- Copyright 2018 Google LLC
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- Adapter component so that elk_interface doesn't have to deal directly with
-- the ext_* signals on the cpu_socket_expansion board.
entity main_to_elk is
port (
-- 55-116MHz clock for FPGA's internal flash
fast_clock : in std_logic;
debug_uart_txd : out std_logic;
debug_a : out std_logic;
debug_b : out std_logic;
ext_uart_rxd : in std_logic;
ext_uart_txd : out std_logic;
-- connections to the cpu_socket_expansion board
ext_A : in std_logic_vector(15 downto 0);
ext_D : inout std_logic_vector(7 downto 0);
ext_GP0 : in std_logic; -- PHI2
ext_GP1 : out std_logic; -- n_global_enable
ext_GP2 : in std_logic; -- 16MHz
ext_GP3 : out std_logic; -- dbuf_nOE
ext_GP4 : out std_logic; -- n_accessing_shadow_ram
ext_GP5 : out std_logic; -- n_cpu_is_external
ext_GP6 : in std_logic; -- RnW
ext_GP7 : in std_logic; -- nRESET
ext_GP8 : in std_logic; -- READY
ext_GP9 : in std_logic; -- /NMI
ext_GP10 : in std_logic; -- /IRQ
ext_GP11 : out std_logic := '1'; -- dbuf_driven_by_cpu
ext_GP12 : in std_logic
);
end main_to_elk;
architecture rtl of main_to_elk is
component elk_interface is
port (
debug_uart_txd : out std_logic;
debug_a : out std_logic;
debug_b : out std_logic;
ext_uart_rxd : in std_logic;
ext_uart_txd : out std_logic;
fast_clock : in std_logic; -- pass through for FPGA's internal flash
elk_A : in std_logic_vector(15 downto 0);
elk_D : inout std_logic_vector(7 downto 0);
elk_PHI0 : in std_logic;
elk_16MHz : in std_logic;
elk_nEN : out std_logic; -- global enable
elk_nDBUF_OE : out std_logic; -- /OE for DBUF chip
elk_nSHADOW : out std_logic; -- '0' when shadowing memory
elk_nCPU_IS_EXTERNAL : out std_logic; -- '0' for external cpu
elk_RnW : in std_logic; -- input
elk_nRESET : in std_logic; -- input
elk_READY : in std_logic; -- input
elk_nNMI : in std_logic; -- input
elk_nIRQ : in std_logic; -- input
elk_CPU_DBUF : out std_logic -- '0' when we're driving the bus, '1' when the cpu is
);
end component;
begin
exp0: component elk_interface port map (
debug_uart_txd => debug_uart_txd,
debug_a => debug_a,
debug_b => debug_b,
ext_uart_txd => ext_uart_txd,
ext_uart_rxd => ext_uart_rxd,
fast_clock => fast_clock,
elk_A => ext_A,
elk_D => ext_D,
elk_PHI0 => ext_GP0,
elk_nEN => ext_GP1,
elk_16MHz => ext_GP2,
elk_nDBUF_OE => ext_GP3,
elk_nSHADOW => ext_GP4,
elk_nCPU_IS_EXTERNAL => ext_GP5,
elk_RnW => ext_GP6,
elk_nRESET => ext_GP7,
elk_READY => ext_GP8,
elk_nNMI => ext_GP9,
elk_nIRQ => ext_GP10,
elk_CPU_DBUF => ext_GP11
);
end rtl;
|
entity ee is end entity;
architecture aa of ee is
signal x, a, b, c : bit;
signal foo, bar : boolean;
signal y : integer;
signal v : bit_vector(1 to 2);
procedure pcall(x : in bit; y : in integer);
procedure xxx;
begin
x <= a or b;
postponed x <= '1' when foo
else '1' when bar
else '0';
with y select x <=
'0' when 6,
'1' when 5,
'1' when others;
pcall(x, y);
assert y = 5;
(a, b) <= v;
xxx;
b1: block is
generic ( g1 : integer; g2 : bit := '1' );
generic map ( g1 => 5 );
port ( p1 : integer );
port map ( p1 => y );
begin
end block;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2966.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b01x00p01n01i02966ent IS
END c02s03b01x00p01n01i02966ent;
ARCHITECTURE c02s03b01x00p01n01i02966arch OF c02s03b01x00p01n01i02966ent IS
BEGIN
TESTING: PROCESS
function "and" (a, b: in integer) return boolean is
begin
return false;
end;
variable i1, i2 :integer := 2;
variable b1, b2 :boolean := true;
variable q1 :boolean ;
variable q2 :boolean ;
variable q3 :boolean ;
BEGIN
q1 := i1 and i2;
q2 := b1 and b2;
q3 := "and" (i1, i2);
wait for 5 ns;
assert NOT( q1=false and q2=true and q3=false )
report "***PASSED TEST: c02s03b01x00p01n01i02966"
severity NOTE;
assert ( q1=false and q2=true and q3=false )
report "***FAILED TEST: c02s03b01x00p01n01i02966 - Function overload test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b01x00p01n01i02966arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2966.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b01x00p01n01i02966ent IS
END c02s03b01x00p01n01i02966ent;
ARCHITECTURE c02s03b01x00p01n01i02966arch OF c02s03b01x00p01n01i02966ent IS
BEGIN
TESTING: PROCESS
function "and" (a, b: in integer) return boolean is
begin
return false;
end;
variable i1, i2 :integer := 2;
variable b1, b2 :boolean := true;
variable q1 :boolean ;
variable q2 :boolean ;
variable q3 :boolean ;
BEGIN
q1 := i1 and i2;
q2 := b1 and b2;
q3 := "and" (i1, i2);
wait for 5 ns;
assert NOT( q1=false and q2=true and q3=false )
report "***PASSED TEST: c02s03b01x00p01n01i02966"
severity NOTE;
assert ( q1=false and q2=true and q3=false )
report "***FAILED TEST: c02s03b01x00p01n01i02966 - Function overload test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b01x00p01n01i02966arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2966.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b01x00p01n01i02966ent IS
END c02s03b01x00p01n01i02966ent;
ARCHITECTURE c02s03b01x00p01n01i02966arch OF c02s03b01x00p01n01i02966ent IS
BEGIN
TESTING: PROCESS
function "and" (a, b: in integer) return boolean is
begin
return false;
end;
variable i1, i2 :integer := 2;
variable b1, b2 :boolean := true;
variable q1 :boolean ;
variable q2 :boolean ;
variable q3 :boolean ;
BEGIN
q1 := i1 and i2;
q2 := b1 and b2;
q3 := "and" (i1, i2);
wait for 5 ns;
assert NOT( q1=false and q2=true and q3=false )
report "***PASSED TEST: c02s03b01x00p01n01i02966"
severity NOTE;
assert ( q1=false and q2=true and q3=false )
report "***FAILED TEST: c02s03b01x00p01n01i02966 - Function overload test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b01x00p01n01i02966arch;
|
signal name: TYPE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: pulse_regen_v6_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity pulse_regen_v6_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(1-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(1-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end pulse_regen_v6_top_wrapper;
architecture xilinx of pulse_regen_v6_top_wrapper is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component pulse_regen_v6_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_i <= wr_clk;
rd_clk_i <= rd_clk;
fg1 : pulse_regen_v6_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
-- LEON3 Statistics Module
constant CFG_L3S_ENABLE : integer := CONFIG_L3S_ENABLE;
constant CFG_L3S_CNT : integer := CONFIG_L3S_CNT;
constant CFG_L3S_NMAX : integer := CONFIG_L3S_NMAX;
|
--Part of Mano Basic Computer
--Behzad Mokhtari; [email protected]
--Sahand University of Technology; sut.ac.ir
--Licensed under GPLv3
--Timer
Library IEEE; use IEEE.std_logic_1164.ALL, IEEE.numeric_std.all;
Library manoBasic; use manoBasic.defines.all, manoBasic.devices.all;
entity Timer is
port(
CLK: in std_logic;
CLR: in std_logic :='1';
EN : in std_logic := '1';
T: out std_logic_vector(7 downto 0)
);
end Timer;
architecture Structure of Timer is
signal count: std_logic_vector(2 downto 0);
begin
counter: reg
generic map(width => 3)
port map(INC=>'1', CLR=>CLR, CLK=>CLK, Do=>count, Di => "000", LD=>'0');
decode:decoder
generic map(n => 3)
port map(I=>count, E=>EN, Q=>T);
end Structure; |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: VGA_BUFFER_RAM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY VGA_BUFFER_RAM_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE VGA_BUFFER_RAM_synth_ARCH OF VGA_BUFFER_RAM_synth IS
COMPONENT VGA_BUFFER_RAM_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ADDRB: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => clkb_in_i,
RST => RSTB,
EN => CHECKER_EN_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(0)
);
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
IF(RSTB='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => clk_in_i,
CLKB => clkb_in_i,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
ADDRB => ADDRB,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: VGA_BUFFER_RAM_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
CLKA => CLKA,
--Port B
ADDRB => ADDRB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: VGA_BUFFER_RAM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY VGA_BUFFER_RAM_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE VGA_BUFFER_RAM_synth_ARCH OF VGA_BUFFER_RAM_synth IS
COMPONENT VGA_BUFFER_RAM_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ADDRB: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => clkb_in_i,
RST => RSTB,
EN => CHECKER_EN_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(0)
);
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
IF(RSTB='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => clk_in_i,
CLKB => clkb_in_i,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
ADDRB => ADDRB,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: VGA_BUFFER_RAM_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
CLKA => CLKA,
--Port B
ADDRB => ADDRB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: VGA_BUFFER_RAM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY VGA_BUFFER_RAM_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE VGA_BUFFER_RAM_synth_ARCH OF VGA_BUFFER_RAM_synth IS
COMPONENT VGA_BUFFER_RAM_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ADDRB: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => clkb_in_i,
RST => RSTB,
EN => CHECKER_EN_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(0)
);
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
IF(RSTB='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => clk_in_i,
CLKB => clkb_in_i,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
ADDRB => ADDRB,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: VGA_BUFFER_RAM_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
CLKA => CLKA,
--Port B
ADDRB => ADDRB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: VGA_BUFFER_RAM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY VGA_BUFFER_RAM_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE VGA_BUFFER_RAM_synth_ARCH OF VGA_BUFFER_RAM_synth IS
COMPONENT VGA_BUFFER_RAM_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ADDRB: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => clkb_in_i,
RST => RSTB,
EN => CHECKER_EN_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(0)
);
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
IF(RSTB='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => clk_in_i,
CLKB => clkb_in_i,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
ADDRB => ADDRB,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: VGA_BUFFER_RAM_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
CLKA => CLKA,
--Port B
ADDRB => ADDRB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: VGA_BUFFER_RAM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY VGA_BUFFER_RAM_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE VGA_BUFFER_RAM_synth_ARCH OF VGA_BUFFER_RAM_synth IS
COMPONENT VGA_BUFFER_RAM_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ADDRB: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => clkb_in_i,
RST => RSTB,
EN => CHECKER_EN_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(0)
);
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
IF(RSTB='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => clk_in_i,
CLKB => clkb_in_i,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
ADDRB => ADDRB,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: VGA_BUFFER_RAM_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
CLKA => CLKA,
--Port B
ADDRB => ADDRB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: VGA_BUFFER_RAM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY VGA_BUFFER_RAM_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE VGA_BUFFER_RAM_synth_ARCH OF VGA_BUFFER_RAM_synth IS
COMPONENT VGA_BUFFER_RAM_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ADDRB: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => clkb_in_i,
RST => RSTB,
EN => CHECKER_EN_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(0)
);
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
IF(RSTB='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => clk_in_i,
CLKB => clkb_in_i,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
ADDRB => ADDRB,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: VGA_BUFFER_RAM_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
CLKA => CLKA,
--Port B
ADDRB => ADDRB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: VGA_BUFFER_RAM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY VGA_BUFFER_RAM_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE VGA_BUFFER_RAM_synth_ARCH OF VGA_BUFFER_RAM_synth IS
COMPONENT VGA_BUFFER_RAM_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ADDRB: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => clkb_in_i,
RST => RSTB,
EN => CHECKER_EN_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(0)
);
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
IF(RSTB='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => clk_in_i,
CLKB => clkb_in_i,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
ADDRB => ADDRB,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: VGA_BUFFER_RAM_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
CLKA => CLKA,
--Port B
ADDRB => ADDRB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: VGA_BUFFER_RAM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY VGA_BUFFER_RAM_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE VGA_BUFFER_RAM_synth_ARCH OF VGA_BUFFER_RAM_synth IS
COMPONENT VGA_BUFFER_RAM_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ADDRB: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => clkb_in_i,
RST => RSTB,
EN => CHECKER_EN_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(0)
);
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
IF(RSTB='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => clk_in_i,
CLKB => clkb_in_i,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
ADDRB => ADDRB,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: VGA_BUFFER_RAM_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
CLKA => CLKA,
--Port B
ADDRB => ADDRB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
|
----------------------------------------------------------------------------------------------------
-- ENTITY - Elliptic Curve Point Addition
--
-- Ports:
-- clk_i - Clock
-- rst_i - Reset flag
-- enable_i - Enable computation
-- x1_i - X part of first point
-- y1_i - Y part of first point
-- x2_i - X part of seccond point
-- y2_i - Y part of thirs point
-- x3_io - X part of output point
-- y3_o - Y part of output point
-- ready_o - Ready flag
--
-- Math:
-- s = (py-qy)/(px-qx)
-- rx = s^2 - s - (px-qx)
-- ry = s * (px - rx) - rx - py
--
-- Based on:
-- http://arithmetic-circuits.org/finite-field/vhdl_Models/chapter10_codes/VHDL/K-163/K163_addition.vhd
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 27.06.2017
----------------------------------------------------------------------------------------------------
------------------------------------------------------------
-- GF(2^M) elliptic curve point addition
------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.tld_ecdsa_package.all;
ENTITY e_gf2m_point_addition IS
GENERIC (
MODULO : std_logic_vector(M DOWNTO 0) := ONE
);
PORT(
-- Clock, reset, enable
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
-- Input signals
x1_i: IN std_logic_vector(M-1 DOWNTO 0);
y1_i: IN std_logic_vector(M-1 DOWNTO 0);
x2_i: IN std_logic_vector(M-1 DOWNTO 0);
y2_i: IN std_logic_vector(M-1 DOWNTO 0);
-- Output signals
x3_io: INOUT std_logic_vector(M-1 DOWNTO 0);
y3_o: OUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
END e_gf2m_point_addition;
ARCHITECTURE rtl of e_gf2m_point_addition IS
-- Import entity e_gf2m_divider
COMPONENT e_gf2m_divider IS
GENERIC (
MODULO : std_logic_vector(M DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
g_i: IN std_logic_vector(M-1 DOWNTO 0);
h_i: IN std_logic_vector(M-1 DOWNTO 0);
z_o: OUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
end COMPONENT;
-- Import entity e_gf2m_classic_squarer
COMPONENT e_gf2m_classic_squarer IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT(
a_i: IN std_logic_vector(M-1 DOWNTO 0);
c_o: OUT std_logic_vector(M-1 DOWNTO 0)
);
end COMPONENT;
-- Import entity e_gf2m_interleaved_multiplier
COMPONENT e_gf2m_interleaved_multiplier IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
a_i: IN std_logic_vector (M-1 DOWNTO 0);
b_i: IN std_logic_vector (M-1 DOWNTO 0);
z_o: OUT std_logic_vector (M-1 DOWNTO 0);
ready_o: OUT std_logic
);
end COMPONENT;
-- Temporary signals for divider and multiplier
SIGNAL div_in1, div_in2, lambda, lambda_square, mult_in2, mult_out: std_logic_vector(M-1 DOWNTO 0);
SIGNAL x3_tmp, y3_tmp, next_xq, next_yq: std_logic_vector(M-1 DOWNTO 0);
-- Signals to switch between multiplier and divider
SIGNAL start_div, div_done, start_mult, mult_done: std_logic;
SIGNAL load, ch_q: std_logic;
SIGNAL sel: std_logic_vector(1 DOWNTO 0);
-- Define all available states
subtype states IS natural RANGE 0 TO 10;
SIGNAL current_state: states;
BEGIN
-- Output register
register_q: PROCESS(clk_i)
BEGIN
IF clk_i' event and clk_i = '1' THEN
IF load = '1' THEN
x3_io <= (OTHERS=>'1');
y3_o <= (OTHERS=>'1');
ELSIF ch_q = '1' THEN
x3_io <= next_xq;
y3_o <= next_yq;
END IF;
END IF;
END PROCESS;
-- Instantiate divider entity
-- Calculate s = (py-qy)/(px-qx)
divider: e_gf2m_divider GENERIC MAP (
MODULO => MODULO
) PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable_i => start_div,
g_i => div_in1,
h_i => div_in2,
z_o => lambda,
ready_o => div_done
);
-- Instantiate squarer
-- Calculate s^2
lambda_square_computation: e_gf2m_classic_squarer GENERIC MAP (
MODULO => MODULO(M-1 DOWNTO 0)
) PORT MAP(
a_i => lambda,
c_o => lambda_square
);
-- Instantiate multiplier entity
-- Calculate s * (px - rx)
multiplier: e_gf2m_interleaved_multiplier GENERIC MAP (
MODULO => MODULO(M-1 DOWNTO 0)
) PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable_i => start_mult,
a_i => lambda,
b_i => mult_in2,
z_o => mult_out,
ready_o => mult_done
);
-- Set divider input from entity input
-- Calculate (py-qy) and (px-qx)
divider_inputs: FOR i IN 0 TO M-1 GENERATE
div_in1(i) <= y1_i(i) xor y2_i(i);
div_in2(i) <= x1_i(i) xor x2_i(i);
END GENERATE;
-- Set multiplier input from entity input
-- Calculate (px - rx)
multiplier_inputs: FOR i IN 0 TO M-1 GENERATE
mult_in2(i) <= x1_i(i) xor x3_tmp(i);
END GENERATE;
-- Set x3(0)
--x3_tmp(0) <= not(lambda_square(0) xor lambda(0) xor div_in2(0));
-- Set output
-- Calculate rx = s^2 - s - (px-qx)
x_output: FOR i IN 0 TO M-1 GENERATE
x3_tmp(i) <= lambda_square(i) xor lambda(i) xor div_in2(i) xor a(i);
END GENERATE;
-- Calculate ry = s * (px - rx) - rx - py
y_output: FOR i IN 0 TO M-1 GENERATE
y3_tmp(i) <= mult_out(i) xor x3_tmp(i) xor y1_i(i);
END GENERATE;
WITH sel SELECT next_yq <= y3_tmp WHEN "00", y1_i WHEN "01", y2_i WHEN OTHERS;
WITH sel SELECT next_xq <= x3_tmp WHEN "00", x1_i WHEN "01", x2_i WHEN OTHERS;
-- State machine
control_unit: PROCESS(clk_i, rst_i, current_state)
BEGIN
-- Handle current state
-- 0,1 : Default state
-- 2,3 : Calculate s = (py-qy)/(px-qx), s^2
-- 4,5,6 : Calculate rx/ry
CASE current_state IS
WHEN 0 TO 1 => load <= '0'; sel <= "00"; ch_q <= '0'; start_div <= '0'; start_mult <= '0'; ready_o <= '1';
WHEN 2 => load <= '1'; sel <= "00"; ch_q <= '0'; start_div <= '0'; start_mult <= '0'; ready_o <= '0';
WHEN 3 => load <= '0'; sel <= "00"; ch_q <= '0'; start_div <= '0'; start_mult <= '0'; ready_o <= '0';
WHEN 4 => load <= '0'; sel <= "00"; ch_q <= '0'; start_div <= '1'; start_mult <= '0'; ready_o <= '0';
WHEN 5 => load <= '0'; sel <= "00"; ch_q <= '0'; start_div <= '0'; start_mult <= '0'; ready_o <= '0';
WHEN 6 => load <= '0'; sel <= "00"; ch_q <= '0'; start_div <= '0'; start_mult <= '1'; ready_o <= '0';
WHEN 7 => load <= '0'; sel <= "00"; ch_q <= '0'; start_div <= '0'; start_mult <= '0'; ready_o <= '0';
WHEN 8 => load <= '0'; sel <= "00"; ch_q <= '1'; start_div <= '0'; start_mult <= '0'; ready_o <= '0';
WHEN 9 => load <= '0'; sel <= "11"; ch_q <= '1'; start_div <= '0'; start_mult <= '0'; ready_o <= '0';
WHEN 10 => load <= '0'; sel <= "01"; ch_q <= '1'; start_div <= '0'; start_mult <= '0'; ready_o <= '0';
END CASE;
IF rst_i = '1' THEN
-- Reset state if reset is high
current_state <= 0;
ELSIF clk_i'event and clk_i = '1' THEN
-- Set next state
CASE current_state IS
WHEN 0 =>
IF enable_i = '0' THEN
current_state <= 1;
END IF;
WHEN 1 =>
IF enable_i = '1' THEN
current_state <= 2;
END IF;
WHEN 2 =>
current_state <= 3;
WHEN 3 =>
IF (x1_i = ONES) OR (y1_i = ONES) THEN
current_state <= 9;
ELSIF (x2_i = ONES) OR (y2_i = ONES) THEN
current_state <= 10;
ELSE
current_state <= 4;
END IF;
WHEN 4 =>
current_state <= 5;
WHEN 5 =>
IF div_done = '1' THEN
current_state <= 6;
END IF;
WHEN 6 =>
current_state <= 7;
WHEN 7 =>
IF mult_done = '1' THEN
current_state <= 8;
END IF;
WHEN 8 =>
current_state <= 0;
WHEN 9 =>
current_state <= 0;
WHEN 10 =>
current_state <= 0;
END CASE;
END IF;
END PROCESS;
END rtl;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity limiter is
generic ( limit_high : real := 4.8; -- upper limit
limit_low : real := -4.8 ); -- lower limit
port ( quantity input : in real;
quantity output : out real);
end entity limiter;
----------------------------------------------------------------
architecture simple of limiter is
constant slope : real := 1.0e-4;
begin
if input > limit_high use -- upper limit exceeded, so limit input signal
output == limit_high + slope*(input - limit_high);
elsif input < limit_low use -- lower limit exceeded, so limit input signal
output == limit_low + slope*(input - limit_low);
else -- no limit exceeded, so pass input signal as is
output == input;
end use;
break on input'above(limit_high), input'above(limit_low);
end architecture simple;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity limiter is
generic ( limit_high : real := 4.8; -- upper limit
limit_low : real := -4.8 ); -- lower limit
port ( quantity input : in real;
quantity output : out real);
end entity limiter;
----------------------------------------------------------------
architecture simple of limiter is
constant slope : real := 1.0e-4;
begin
if input > limit_high use -- upper limit exceeded, so limit input signal
output == limit_high + slope*(input - limit_high);
elsif input < limit_low use -- lower limit exceeded, so limit input signal
output == limit_low + slope*(input - limit_low);
else -- no limit exceeded, so pass input signal as is
output == input;
end use;
break on input'above(limit_high), input'above(limit_low);
end architecture simple;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity limiter is
generic ( limit_high : real := 4.8; -- upper limit
limit_low : real := -4.8 ); -- lower limit
port ( quantity input : in real;
quantity output : out real);
end entity limiter;
----------------------------------------------------------------
architecture simple of limiter is
constant slope : real := 1.0e-4;
begin
if input > limit_high use -- upper limit exceeded, so limit input signal
output == limit_high + slope*(input - limit_high);
elsif input < limit_low use -- lower limit exceeded, so limit input signal
output == limit_low + slope*(input - limit_low);
else -- no limit exceeded, so pass input signal as is
output == input;
end use;
break on input'above(limit_high), input'above(limit_low);
end architecture simple;
|
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Author: Andrzej Paluch
--
-- Create Date: 23:50:53 11/16/2011
-- Design Name: MemoryBlock
-- Module Name: J:/projekty/elektronika/USB_to_HPIB/usbToHpib/src/test/MemoryBlock_Test.vhd
-- Project Name: usbToGpib
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: MemoryBlock
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.helperComponents.all;
ENTITY MemoryBlock_Test_vhd IS
END MemoryBlock_Test_vhd;
ARCHITECTURE behavior OF MemoryBlock_Test_vhd IS
constant clk_period : time := 1us;
SIGNAL reset : std_logic := '0';
SIGNAL clk : std_logic := '0';
-------------------------------------------------
SIGNAL p1_addr : std_logic_vector(10 downto 0) := (others => '0');
SIGNAL p1_data_in : std_logic_vector(7 downto 0) := (others => '0');
SIGNAL p1_data_out : std_logic_vector(7 downto 0);
SIGNAL p1_strobe : std_logic := '0';
-------------------------------------------------
SIGNAL p2_addr : std_logic_vector(10 downto 0) := (others => '0');
SIGNAL p2_data_in : std_logic_vector(7 downto 0) := (others => '0');
SIGNAL p2_data_out : std_logic_vector(7 downto 0);
SIGNAL p2_strobe : std_logic := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MemoryBlock port map (
reset => reset,
clk => clk,
-------------------------------------------------
p1_addr => p1_addr,
p1_data_in => p1_data_in,
p1_strobe => p1_strobe,
p1_data_out => p1_data_out,
-------------------------------------------------
p2_addr => p2_addr,
p2_data_in => p2_data_in,
p2_strobe => p2_strobe,
p2_data_out => p2_data_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stim_proc: PROCESS
BEGIN
reset <= '1';
wait for clk_period*4;
reset <= '0';
wait for clk_period*20;
p1_addr <= "00000000000";
p2_addr <= "00000000000";
p1_data_in <= "10101010";
wait for clk_period/2;
p1_strobe <= '1';
wait for clk_period;
p1_strobe <= '0';
wait for clk_period*4;
p2_addr <= "00000000101";
p2_data_in <= "11010101";
wait for clk_period;
p2_strobe <= '1';
wait for clk_period;
p2_strobe <= '0';
wait for clk_period*4;
p1_addr <= "00000000101";
wait; -- will wait forever
END PROCESS;
END;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15376)
`protect data_block
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|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: QDGoppa
-- Module Name: RAM Generator Matrix
-- Project Name: QDGoppa
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Circuit to simulate the behavior of a RAM Bank behavioral, where it can output
-- number_of_memories at once, with different address for each memory. Only used for tests.
--
-- The circuits parameters
--
-- number_of_memories :
--
-- Number of memories in the RAM Bank
--
-- ram_address_size :
-- Address size of the RAM bank used on the circuit.
--
-- ram_word_size :
-- The size of internal word on the RAM Bank.
--
-- file_ram_word_size :
-- The size of the word used in the file to be loaded on the RAM Bank.(ARCH: FILE_LOAD)
--
-- load_file_name :
-- The name of file to be loaded.(ARCH: FILE_LOAD)
--
-- dump_file_name :
-- The name of the file to be used to dump the memory.
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD.ALL;
-- IEEE.STD_LOGIC_TEXTIO.ALL;
-- STD.TEXTIO.ALL;
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
library STD;
use STD.TEXTIO.ALL;
entity ram_generator_matrix is
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR (((ram_address_size)*(number_of_memories) - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end ram_generator_matrix;
architecture simple of ram_generator_matrix is
type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0);
procedure dump_ram (ram_file_name : in string; memory_ram : in ramtype) is
FILE ram_file : text is out ram_file_name;
variable line_n : line;
begin
for I in ramtype'range loop
write (line_n, memory_ram(I));
writeline (ram_file, line_n);
end loop;
end procedure;
signal memory_ram : ramtype;
begin
process (clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
for I in ramtype'range loop
memory_ram(I) <= rst_value;
end loop;
end if;
if dump = '1' then
dump_ram(dump_file_name, memory_ram);
end if;
if rw = '1' then
for index in 0 to (number_of_memories - 1) loop
memory_ram(to_integer(unsigned(address(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index))))) <= data_in(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index));
end loop;
end if;
for index in 0 to (number_of_memories - 1) loop
data_out(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index)))));
end loop;
end if;
end process;
end simple;
|
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`protect end_protected
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:02:34 07/20/2006
-- Design Name:
-- Module Name: icapFIFO - icapFIFO_rtl
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity icapFIFO is
generic (
C_FIFO_DEPTH : integer := 64;
C_DIN_WIDTH : integer := 64;
C_DOUT_WIDTH : integer := 8
);
port (
clk : in std_logic;
reset : in std_logic;
wEn_i : in std_logic;
wData_i : in std_logic_vector(C_DIN_WIDTH-1 downto 0);
rEn_i : in std_logic;
rData_o : out std_logic_vector(C_DOUT_WIDTH-1 downto 0);
full_o : out std_logic;
empty_o : out std_logic
);
end icapFIFO;
architecture icapFIFO_rtl of icapFIFO is
-- A synthesizable function that returns the integer part of the base 2 logarithm for a positive number
-- is (uses recursion) from http://tams-www.informatik.uni-hamburg.de/vhdl/doc/faq/FAQ1.html
function log2(x:positive) return natural is
begin
if(x<=1) then
return 0;
else
return log2(x/2)+1;
end if;
end function log2;
constant C_AIN_WIDTH : integer := log2(C_FIFO_DEPTH); -- 6 in this case
constant C_AOUT_WIDTH : integer := log2(C_FIFO_DEPTH*C_DIN_WIDTH/C_DOUT_WIDTH); -- 9 in this case
constant C_AOUT_SPLIT : integer := C_AOUT_WIDTH - C_AIN_WIDTH; -- 3 in this case
type fifo_type is array(C_FIFO_DEPTH-1 downto 0) of std_logic_vector(C_DIN_WIDTH-1 downto 0);
signal fifo : fifo_type;
signal head, head_n : std_logic_vector(C_AIN_WIDTH-1 downto 0);
signal tail, tail_n : std_logic_vector(C_AOUT_WIDTH-1 downto 0);
signal empty, empty_p : std_logic;
-- Add keep attribute to tail_n to prevent synthesis of both counter and adder
attribute keep : string;
attribute keep of tail_n : signal is "true";
signal fData : std_logic_vector(C_DIN_WIDTH-1 downto 0);
type fMux_type is array(C_DIN_WIDTH/C_DOUT_WIDTH-1 downto 0) of std_logic_vector(C_DOUT_WIDTH-1 downto 0);
signal fMux : fMux_type;
begin
head_n <= head+1 when(wEn_i='1') else head;
tail_n <= tail+1 when(rEn_i='1') else tail;
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
head <= (others=>'0');
tail <= (others=>'0');
else
head <= head_n;
tail <= tail_n;
end if;
-- if wEn_i ='1' write wData_i to Address specified by head pointer.
if(wEn_i='1') then
fifo(CONV_INTEGER(UNSIGNED(head))) <= wData_i;
end if;
-- if(wEn_i='1' and tail_n(C_AOUT_WIDTH-1 downto C_AOUT_WIDTH-C_AIN_WIDTH)=head) then
-- fData <= wData_i;
-- else
fData <= fifo(CONV_INTEGER(UNSIGNED(tail_n(C_AOUT_WIDTH-1 downto C_AOUT_SPLIT)))); -- tail_n(8 downto 3)
-- ???
-- end if;
end if;
end process;
--empty signal one cycle delayed, because no write through is supported
empty <= '1' when(tail(C_AOUT_WIDTH-1 downto C_AOUT_SPLIT) = head) else '0'; -- tail(8 downto 3)
process(clk) begin
if(clk='1' and clk'event) then
empty_p <= empty;
end if;
end process;
empty_o <= '0' when(empty='0' and empty_p='0') else '1';
-- Generate the full signal
-- asserted whenever the fifo memory is 3/4 full
-- here is an example when the fifo memory is 3/4 full (fMSB = 1100)
-- 00 01 10 11 00 01 10 <- MSBs from head and tail
-- |________|________|________|________|________|________|________|
--
-- ^ ^
-- | |
-- Tail Head
--
-- The fifo is 3/4 full when fMSB equals (0001, 0110, 1011, 1100)
-- These processes generate the full and the empty signal
process(head, tail)
variable fMSB : std_logic_vector(3 downto 0);
begin
-- in this case fMSB is composed of head(5) & head (4) & tail(8) & tail(7)
fMSB := head(C_AIN_WIDTH-1)&head(C_AIN_WIDTH-2)&tail(C_AOUT_WIDTH-1)&tail(C_AOUT_WIDTH-2);
case(fMSB) is
when "0000" => full_o <= '0';
when "0001" => full_o <= '1';
when "0010" => full_o <= '0';
when "0011" => full_o <= '0';
when "0100" => full_o <= '0';
when "0101" => full_o <= '0';
when "0110" => full_o <= '1';
when "0111" => full_o <= '0';
when "1000" => full_o <= '0';
when "1001" => full_o <= '0';
when "1010" => full_o <= '0';
when "1011" => full_o <= '1';
when "1100" => full_o <= '1';
when "1101" => full_o <= '0';
when "1110" => full_o <= '0';
when "1111" => full_o <= '0';
when others => full_o <= '0';
end case;
end process;
process(fData) begin
for i in 0 to C_DIN_WIDTH/C_DOUT_WIDTH-1 loop
-- BUG: fMux(C_DIN_WIDTH/C_DOUT_WIDTH-1-i) <= fData((i+1)*(C_DIN_WIDTH/C_DOUT_WIDTH)-1 downto i*(C_DIN_WIDTH/C_DOUT_WIDTH));
fMux(C_DIN_WIDTH/C_DOUT_WIDTH-1-i) <= fData((i+1)*C_DOUT_WIDTH-1 downto i*C_DOUT_WIDTH);
end loop;
end process;
rData_o <= fMux(CONV_INTEGER(UNSIGNED(tail(C_AOUT_SPLIT-1 downto 0)))); -- tail(2 downto 0)
end icapFIFO_rtl;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:02:34 07/20/2006
-- Design Name:
-- Module Name: icapFIFO - icapFIFO_rtl
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity icapFIFO is
generic (
C_FIFO_DEPTH : integer := 64;
C_DIN_WIDTH : integer := 64;
C_DOUT_WIDTH : integer := 8
);
port (
clk : in std_logic;
reset : in std_logic;
wEn_i : in std_logic;
wData_i : in std_logic_vector(C_DIN_WIDTH-1 downto 0);
rEn_i : in std_logic;
rData_o : out std_logic_vector(C_DOUT_WIDTH-1 downto 0);
full_o : out std_logic;
empty_o : out std_logic
);
end icapFIFO;
architecture icapFIFO_rtl of icapFIFO is
-- A synthesizable function that returns the integer part of the base 2 logarithm for a positive number
-- is (uses recursion) from http://tams-www.informatik.uni-hamburg.de/vhdl/doc/faq/FAQ1.html
function log2(x:positive) return natural is
begin
if(x<=1) then
return 0;
else
return log2(x/2)+1;
end if;
end function log2;
constant C_AIN_WIDTH : integer := log2(C_FIFO_DEPTH); -- 6 in this case
constant C_AOUT_WIDTH : integer := log2(C_FIFO_DEPTH*C_DIN_WIDTH/C_DOUT_WIDTH); -- 9 in this case
constant C_AOUT_SPLIT : integer := C_AOUT_WIDTH - C_AIN_WIDTH; -- 3 in this case
type fifo_type is array(C_FIFO_DEPTH-1 downto 0) of std_logic_vector(C_DIN_WIDTH-1 downto 0);
signal fifo : fifo_type;
signal head, head_n : std_logic_vector(C_AIN_WIDTH-1 downto 0);
signal tail, tail_n : std_logic_vector(C_AOUT_WIDTH-1 downto 0);
signal empty, empty_p : std_logic;
-- Add keep attribute to tail_n to prevent synthesis of both counter and adder
attribute keep : string;
attribute keep of tail_n : signal is "true";
signal fData : std_logic_vector(C_DIN_WIDTH-1 downto 0);
type fMux_type is array(C_DIN_WIDTH/C_DOUT_WIDTH-1 downto 0) of std_logic_vector(C_DOUT_WIDTH-1 downto 0);
signal fMux : fMux_type;
begin
head_n <= head+1 when(wEn_i='1') else head;
tail_n <= tail+1 when(rEn_i='1') else tail;
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
head <= (others=>'0');
tail <= (others=>'0');
else
head <= head_n;
tail <= tail_n;
end if;
-- if wEn_i ='1' write wData_i to Address specified by head pointer.
if(wEn_i='1') then
fifo(CONV_INTEGER(UNSIGNED(head))) <= wData_i;
end if;
-- if(wEn_i='1' and tail_n(C_AOUT_WIDTH-1 downto C_AOUT_WIDTH-C_AIN_WIDTH)=head) then
-- fData <= wData_i;
-- else
fData <= fifo(CONV_INTEGER(UNSIGNED(tail_n(C_AOUT_WIDTH-1 downto C_AOUT_SPLIT)))); -- tail_n(8 downto 3)
-- ???
-- end if;
end if;
end process;
--empty signal one cycle delayed, because no write through is supported
empty <= '1' when(tail(C_AOUT_WIDTH-1 downto C_AOUT_SPLIT) = head) else '0'; -- tail(8 downto 3)
process(clk) begin
if(clk='1' and clk'event) then
empty_p <= empty;
end if;
end process;
empty_o <= '0' when(empty='0' and empty_p='0') else '1';
-- Generate the full signal
-- asserted whenever the fifo memory is 3/4 full
-- here is an example when the fifo memory is 3/4 full (fMSB = 1100)
-- 00 01 10 11 00 01 10 <- MSBs from head and tail
-- |________|________|________|________|________|________|________|
--
-- ^ ^
-- | |
-- Tail Head
--
-- The fifo is 3/4 full when fMSB equals (0001, 0110, 1011, 1100)
-- These processes generate the full and the empty signal
process(head, tail)
variable fMSB : std_logic_vector(3 downto 0);
begin
-- in this case fMSB is composed of head(5) & head (4) & tail(8) & tail(7)
fMSB := head(C_AIN_WIDTH-1)&head(C_AIN_WIDTH-2)&tail(C_AOUT_WIDTH-1)&tail(C_AOUT_WIDTH-2);
case(fMSB) is
when "0000" => full_o <= '0';
when "0001" => full_o <= '1';
when "0010" => full_o <= '0';
when "0011" => full_o <= '0';
when "0100" => full_o <= '0';
when "0101" => full_o <= '0';
when "0110" => full_o <= '1';
when "0111" => full_o <= '0';
when "1000" => full_o <= '0';
when "1001" => full_o <= '0';
when "1010" => full_o <= '0';
when "1011" => full_o <= '1';
when "1100" => full_o <= '1';
when "1101" => full_o <= '0';
when "1110" => full_o <= '0';
when "1111" => full_o <= '0';
when others => full_o <= '0';
end case;
end process;
process(fData) begin
for i in 0 to C_DIN_WIDTH/C_DOUT_WIDTH-1 loop
-- BUG: fMux(C_DIN_WIDTH/C_DOUT_WIDTH-1-i) <= fData((i+1)*(C_DIN_WIDTH/C_DOUT_WIDTH)-1 downto i*(C_DIN_WIDTH/C_DOUT_WIDTH));
fMux(C_DIN_WIDTH/C_DOUT_WIDTH-1-i) <= fData((i+1)*C_DOUT_WIDTH-1 downto i*C_DOUT_WIDTH);
end loop;
end process;
rData_o <= fMux(CONV_INTEGER(UNSIGNED(tail(C_AOUT_SPLIT-1 downto 0)))); -- tail(2 downto 0)
end icapFIFO_rtl;
|
--========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_generic_queue_pkg;
use work.generic_sb_support_pkg.all;
package generic_sb_pkg is
generic (type t_element;
function element_match(received_element : t_element;
expected_element : t_element) return boolean;
function to_string_element(element : t_element) return string;
constant sb_config_default : t_sb_config := C_SB_CONFIG_DEFAULT;
constant GC_QUEUE_COUNT_MAX : natural := 1000;
constant GC_QUEUE_COUNT_THRESHOLD : natural := 950);
type t_generic_sb is protected
procedure config(
constant sb_config_array : in t_sb_config_array;
constant msg : in string := "");
procedure config(
constant instance : in integer;
constant sb_config : in t_sb_config;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure config(
constant sb_config : in t_sb_config;
constant msg : in string := "");
procedure enable(
constant instance : in integer;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure enable(
constant msg : in string);
procedure enable(
constant void : in t_void);
procedure disable(
constant instance : in integer;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure disable(
constant msg : in string);
procedure disable(
constant void : in t_void);
procedure add_expected(
constant instance : in integer;
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant source : in string := "";
constant ext_proc_call : in string := "");
procedure add_expected(
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant source : in string := "");
procedure add_expected(
constant expected_element : in t_element;
constant msg : in string := "";
constant source : in string := "");
procedure add_expected(
constant instance : in integer;
constant expected_element : in t_element;
constant msg : in string := "";
constant source : in string := "");
procedure check_received(
constant instance : in integer;
constant received_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure check_received(
constant received_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "");
procedure check_received(
constant instance : in integer;
constant received_element : in t_element;
constant msg : in string := "");
procedure check_received(
constant received_element : in t_element;
constant msg : in string := "");
procedure flush(
constant instance : in integer;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure flush(
constant msg : in string);
procedure flush(
constant void : in t_void);
procedure reset(
constant instance : in integer;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure reset(
constant msg : in string);
procedure reset(
constant void : in t_void);
impure function is_empty(
constant instance : in integer) return boolean;
impure function is_empty(
constant void : in t_void) return boolean;
impure function get_entered_count(
constant instance : in integer) return integer;
impure function get_entered_count(
constant void : in t_void) return integer;
impure function get_pending_count(
constant instance : in integer) return integer;
impure function get_pending_count(
constant void : in t_void) return integer;
impure function get_match_count(
constant instance : in integer) return integer;
impure function get_match_count(
constant void : in t_void) return integer;
impure function get_mismatch_count(
constant instance : in integer) return integer;
impure function get_mismatch_count(
constant void : in t_void) return integer;
impure function get_drop_count(
constant instance : in integer) return integer;
impure function get_drop_count(
constant void : in t_void) return integer;
impure function get_initial_garbage_count(
constant instance : in integer) return integer;
impure function get_initial_garbage_count(
constant void : in t_void) return integer;
impure function get_delete_count(
constant instance : in integer) return integer;
impure function get_delete_count(
constant void : in t_void) return integer;
impure function get_overdue_check_count(
constant instance : in integer) return integer;
impure function get_overdue_check_count(
constant void : in t_void) return integer;
procedure set_scope(
constant scope : in string);
impure function get_scope(
constant void : in t_void) return string;
procedure enable_log_msg(
constant instance : in integer;
constant msg_id : in t_msg_id;
constant ext_proc_call : in string := "");
procedure enable_log_msg(
constant msg_id : in t_msg_id);
procedure disable_log_msg(
constant instance : in integer;
constant msg_id : in t_msg_id;
constant ext_proc_call : in string := "");
procedure disable_log_msg(
constant msg_id : in t_msg_id);
procedure report_counters(
constant instance : in integer;
constant ext_proc_call : in string := "");
procedure report_counters(
constant void : in t_void);
procedure insert_expected(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant source : in string := "";
constant ext_proc_call : in string := "");
procedure insert_expected(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant source : in string := "");
procedure delete_expected(
constant instance : in integer;
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure delete_expected(
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "");
procedure delete_expected(
constant instance : in integer;
constant expected_element : in t_element;
constant msg : in string := "");
procedure delete_expected(
constant expected_element : in t_element;
constant msg : in string := "");
procedure delete_expected(
constant instance : in integer;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure delete_expected(
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "");
procedure delete_expected(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure delete_expected(
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive;
constant msg : in string := "");
procedure delete_expected(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure delete_expected(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option;
constant msg : in string := "");
impure function find_expected_entry_num(
constant instance : in integer;
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string) return integer;
impure function find_expected_entry_num(
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string) return integer;
impure function find_expected_entry_num(
constant instance : in integer;
constant expected_element : in t_element) return integer;
impure function find_expected_entry_num(
constant expected_element : in t_element) return integer;
impure function find_expected_entry_num(
constant instance : in integer;
constant tag_usage : in t_tag_usage;
constant tag : in string) return integer;
impure function find_expected_entry_num(
constant tag_usage : in t_tag_usage;
constant tag : in string) return integer;
impure function find_expected_position(
constant instance : in integer;
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string) return integer;
impure function find_expected_position(
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string) return integer;
impure function find_expected_position(
constant instance : in integer;
constant expected_element : in t_element) return integer;
impure function find_expected_position(
constant expected_element : in t_element) return integer;
impure function find_expected_position(
constant instance : in integer;
constant tag_usage : in t_tag_usage;
constant tag : in string) return integer;
impure function find_expected_position(
constant tag_usage : in t_tag_usage;
constant tag : in string) return integer;
impure function peek_expected(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive) return t_element;
impure function peek_expected(
constant identifier_option : t_identifier_option;
constant identifier : positive) return t_element;
impure function peek_expected(
constant instance : integer) return t_element;
impure function peek_expected(
constant void : t_void) return t_element;
impure function peek_source(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive) return string;
impure function peek_source(
constant identifier_option : t_identifier_option;
constant identifier : positive) return string;
impure function peek_source(
constant instance : integer) return string;
impure function peek_source(
constant void : t_void) return string;
impure function peek_tag(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive) return string;
impure function peek_tag(
constant identifier_option : t_identifier_option;
constant identifier : positive) return string;
impure function peek_tag(
constant instance : integer) return string;
impure function peek_tag(
constant void : t_void) return string;
impure function fetch_expected(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "";
constant ext_proc_call : string := "") return t_element;
impure function fetch_expected(
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "") return t_element;
impure function fetch_expected(
constant instance : integer;
constant msg : string := "") return t_element;
impure function fetch_expected(
constant msg : string) return t_element;
impure function fetch_expected(
constant void : t_void) return t_element;
impure function fetch_source(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "";
constant ext_proc_call : string := "") return string;
impure function fetch_source(
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "") return string;
impure function fetch_source(
constant instance : integer;
constant msg : string := "") return string;
impure function fetch_source(
constant msg : string) return string;
impure function fetch_source(
constant void : t_void) return string;
impure function fetch_tag(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "";
constant ext_proc_call : string := "") return string;
impure function fetch_tag(
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "") return string;
impure function fetch_tag(
constant instance : integer;
constant msg : string := "") return string;
impure function fetch_tag(
constant msg : string) return string;
impure function fetch_tag(
constant void : t_void) return string;
impure function exists(
constant instance : integer;
constant expected_element : t_element;
constant tag_usage : t_tag_usage := NO_TAG;
constant tag : string := "") return boolean;
impure function exists(
constant expected_element : t_element;
constant tag_usage : t_tag_usage := NO_TAG;
constant tag : string := "") return boolean;
impure function exists(
constant instance : integer;
constant tag_usage : t_tag_usage;
constant tag : string) return boolean;
impure function exists(
constant tag_usage : t_tag_usage;
constant tag : string) return boolean;
end protected t_generic_sb;
end package generic_sb_pkg;
package body generic_sb_pkg is
-- SB type declaration
type t_sb_entry is record
expected_element : t_element;
source : string(1 to C_SB_SOURCE_WIDTH);
tag : string(1 to C_SB_TAG_WIDTH);
entry_time : time;
end record;
-- Declaration of sb_queue_pkg used to store all entries
package sb_queue_pkg is new uvvm_vvc_framework.ti_generic_queue_pkg
generic map (
t_generic_element => t_sb_entry,
scope => "SB_queue",
GC_QUEUE_COUNT_MAX => 1000,
GC_QUEUE_COUNT_THRESHOLD => 750);
use sb_queue_pkg.all;
type t_generic_sb is protected body
----------------------------------------------------------------------------------------------------
-- Variables
----------------------------------------------------------------------------------------------------
variable vr_scope : string(1 to C_LOG_SCOPE_WIDTH) := (1 to 4 => "?_SB", others => NUL);
variable vr_config : t_sb_config_array(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => sb_config_default);
variable vr_instance_enabled : boolean_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => false);
variable vr_sb_queue : sb_queue_pkg.t_generic_queue;
type t_msg_id_panel_array is array(0 to C_MAX_QUEUE_INSTANCE_NUM) of t_msg_id_panel;
variable vr_msg_id_panel_array : t_msg_id_panel_array := (others => C_SB_MSG_ID_PANEL_DEFAULT);
-- Counters
variable vr_entered_cnt : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => -1);
variable vr_match_cnt : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => -1);
variable vr_mismatch_cnt : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => -1);
variable vr_drop_cnt : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => -1);
variable vr_initial_garbage_cnt : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => -1);
variable vr_delete_cnt : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => -1);
variable vr_overdue_check_cnt : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => -1);
--==================================================================================================
-- NON PUBLIC METHODS
--==================================================================================================
procedure check_instance_in_range(
constant instance : in integer
) is
begin
check_value_in_range(instance, 0, C_MAX_QUEUE_INSTANCE_NUM, TB_ERROR,
"Instance must be within range 0 to C_MAX_QUEUE_INSTANCE_NUM, " & to_string(C_MAX_QUEUE_INSTANCE_NUM) & ".", vr_scope, ID_NEVER);
end procedure check_instance_in_range;
procedure check_instance_enabled(
constant instance : in integer
) is
begin
check_value(vr_instance_enabled(instance), TB_ERROR, "The instance is not enabled", vr_scope, ID_NEVER);
end procedure check_instance_enabled;
procedure check_queue_empty(
constant instance : in natural
) is
begin
check_value(not vr_sb_queue.is_empty(instance), TB_ERROR, "The queue is empty", vr_scope, ID_NEVER);
end procedure check_queue_empty;
procedure check_config_validity(
constant config : in t_sb_config
) is
begin
check_value(config.allow_out_of_order and config.allow_lossy, false, TB_ERROR,
"allow_out_of_order and allow_lossy cannot both be enabled. Se documentation for how to handle both modes.", vr_scope, ID_NEVER);
check_value(config.overdue_check_time_limit >= 0 ns, TB_ERROR,
"overdue_check_time_limit cannot be less than 0 ns.", vr_scope, ID_NEVER);
end procedure;
impure function match_received_vs_entry (
constant received_element : in t_element;
constant sb_entry : in t_sb_entry;
constant tag_usage : in t_tag_usage;
constant tag : in string
) return boolean is
begin
-- If TAG then check if tag match
if tag_usage = uvvm_util.types_pkg.TAG then
if pad_string(tag, NUL, C_SB_TAG_WIDTH) /= sb_entry.tag then
return false;
end if;
end if;
return element_match(received_element, sb_entry.expected_element);
end function match_received_vs_entry;
impure function match_expected_vs_entry (
constant expected_element : in t_element;
constant sb_entry : in t_sb_entry;
constant tag_usage : in t_tag_usage;
constant tag : in string
) return boolean is
begin
-- If TAG then check if tag match
if tag_usage = uvvm_util.types_pkg.TAG then
if pad_string(tag, NUL, C_SB_TAG_WIDTH) /= sb_entry.tag then
return false;
end if;
end if;
return expected_element = sb_entry.expected_element;
end function match_expected_vs_entry;
procedure log(
instance : natural;
msg_id : t_msg_id;
msg : string;
scope : string
) is
begin
if vr_msg_id_panel_array(instance)(msg_id) = ENABLED then
log(msg_id, msg, scope, C_MSG_ID_PANEL_DEFAULT);
end if;
end procedure;
--==================================================================================================
-- PUBLIC METHODS
--==================================================================================================
----------------------------------------------------------------------------------------------------
--
-- config
--
-- Sets config for each instance, by array or instance parameter
--
----------------------------------------------------------------------------------------------------
procedure config(
constant sb_config_array : in t_sb_config_array;
constant msg : in string := ""
) is
begin
-- Check if range is within limits
check_value(sb_config_array'low >= 0 and sb_config_array'high <= C_MAX_QUEUE_INSTANCE_NUM, TB_ERROR,
"Configuration array must be within range 0 to C_MAX_QUEUE_INSTANCE_NUM, " & to_string(C_MAX_QUEUE_INSTANCE_NUM) & ".", vr_scope, ID_NEVER);
-- Apply config to the defined range
for i in sb_config_array'low to sb_config_array'high loop
check_config_validity(sb_config_array(i));
log(i, ID_CTRL, "config: config applied to instance " & to_string(i) & "." & add_msg_delimiter(msg), vr_scope);
vr_config(i) := sb_config_array(i);
end loop;
end procedure config;
procedure config(
constant instance : in integer;
constant sb_config : in t_sb_config;
constant msg : in string := "";
constant ext_proc_call : in string := "" -- not proc???
) is
constant proc_name : string := "config";
begin
-- Sanity checks
check_instance_in_range(instance);
check_config_validity(sb_config);
if ext_proc_call = "" then
-- Called directly from sequencer/VVC.
log(instance, ID_CTRL, proc_name & ": config applied to instance " & to_string(instance) & "." & add_msg_delimiter(msg), vr_scope);
else
-- Called from other SB method
log(instance, ID_CTRL, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
vr_config(instance) := sb_config;
end procedure config;
procedure config(
constant sb_config : in t_sb_config;
constant msg : in string := ""
) is
begin
config(1, sb_config, msg, "config: config applied to SB.");
end procedure config;
----------------------------------------------------------------------------------------------------
--
-- enable
--
-- Enable one instance or all instances. Counters is set froom -1 to 0 When enabled for the
-- first time.
--
----------------------------------------------------------------------------------------------------
procedure enable(
constant instance : in integer;
constant msg : in string := "";
constant ext_proc_call : in string := "" -- not proc???
) is
constant proc_name : string := "enable";
begin
-- Check if instance is within range
if instance /= ALL_INSTANCES then
check_instance_in_range(instance);
end if;
if ext_proc_call = "" then
-- Called directly from sequencer/VVC.
if instance = ALL_INSTANCES then
log(ID_CTRL, proc_name & ": all instances enabled." & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_CTRL, proc_name & ": instance " & to_string(instance) & " enabled." & add_msg_delimiter(msg), vr_scope);
end if;
else
-- Called from other SB method
log(instance, ID_CTRL, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
if instance = ALL_INSTANCES then
vr_instance_enabled := (others => true);
for i in 0 to C_MAX_QUEUE_INSTANCE_NUM loop
if vr_entered_cnt(i) = -1 then
vr_entered_cnt(i) := 0;
vr_match_cnt(i) := 0;
vr_mismatch_cnt(i) := 0;
vr_drop_cnt(i) := 0;
vr_initial_garbage_cnt(i) := 0;
vr_delete_cnt(i) := 0;
vr_overdue_check_cnt(i) := 0;
end if;
end loop;
else
vr_instance_enabled(instance) := true;
if vr_entered_cnt(instance) = -1 then
vr_entered_cnt(instance) := 0;
vr_match_cnt(instance) := 0;
vr_mismatch_cnt(instance) := 0;
vr_drop_cnt(instance) := 0;
vr_initial_garbage_cnt(instance) := 0;
vr_delete_cnt(instance) := 0;
vr_overdue_check_cnt(instance) := 0;
end if;
end if;
vr_sb_queue.set_scope(instance, "SB queue");
end procedure enable;
procedure enable(
constant msg : in string
) is
begin
enable(1, msg, "enable: SB enabled.");
end procedure enable;
procedure enable(
constant void : in t_void
) is
begin
enable(1, "", "enable: SB enabled.");
end procedure enable;
----------------------------------------------------------------------------------------------------
--
-- disable
--
-- Disable one instance or all instances.
--
----------------------------------------------------------------------------------------------------
procedure disable(
constant instance : in integer;
constant msg : in string := "";
constant ext_proc_call : in string := "" -- not proc???
) is
begin
-- Check if instance is within range
if instance /= ALL_INSTANCES then
check_instance_in_range(instance);
end if;
if instance = ALL_INSTANCES then
vr_instance_enabled := (others => false);
else
vr_instance_enabled(instance) := false;
end if;
if ext_proc_call = "" then
-- Called directly from sequencer/VVC.
if instance = ALL_INSTANCES then
log(ID_CTRL, "disable: all instances disabled." & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_CTRL, "disable: instance " & to_string(instance) & " disabled." & add_msg_delimiter(msg), vr_scope);
end if;
else
-- Called from other SB method
log(instance, ID_CTRL, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
end procedure disable;
procedure disable(
constant msg : in string
) is
begin
disable(1, msg, "disable: SB disabled.");
end procedure disable;
procedure disable(
constant void : in t_void
) is
begin
disable(1, "", "disable: SB disabled.");
end procedure disable;
----------------------------------------------------------------------------------------------------
--
-- add_expected
--
-- Adds expected element at the back of queue. Optional tag and source.
--
----------------------------------------------------------------------------------------------------
procedure add_expected(
constant instance : in integer;
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant source : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "add_expected";
variable v_sb_entry : t_sb_entry;
begin
v_sb_entry := (expected_element => expected_element,
source => pad_string(source, NUL, C_SB_SOURCE_WIDTH),
tag => pad_string(tag, NUL, C_SB_TAG_WIDTH),
entry_time => now);
if instance = ALL_ENABLED_INSTANCES then
for i in 0 to C_MAX_QUEUE_INSTANCE_NUM loop
if vr_instance_enabled(i) then
-- add entry
vr_sb_queue.add(i, v_sb_entry);
-- increment counters
vr_entered_cnt(i) := vr_entered_cnt(i)+1;
if tag_usage = NO_TAG then
log(i, ID_DATA, proc_name & "() => instance " & to_string(instance) & ", value: " & to_string_element(expected_element) &
". " & add_msg_delimiter(msg), vr_scope);
else
log(i, ID_DATA, proc_name & "() => instance " & to_string(instance) & ", value: " & to_string_element(expected_element) & ", tag: " & to_string(tag) &
". " & add_msg_delimiter(msg), vr_scope);
end if;
end if;
end loop;
else
-- Sanity checks
check_instance_in_range(instance);
check_instance_enabled(instance);
-- add entry
vr_sb_queue.add(instance, v_sb_entry);
-- increment counters
vr_entered_cnt(instance) := vr_entered_cnt(instance)+1;
if ext_proc_call = "" then
if tag_usage = NO_TAG then
log(instance, ID_DATA, proc_name & "() => instance " & to_string(instance) & ", value: " & to_string_element(expected_element) &
". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, proc_name & "() => instance " & to_string(instance) & ", value: " & to_string_element(expected_element) & ", tag: " & to_string(tag) &
". " & add_msg_delimiter(msg), vr_scope);
end if;
else
-- Called from other SB method
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
end if;
end procedure add_expected;
procedure add_expected(
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant source : in string := ""
) is
begin
if tag_usage = NO_TAG then
add_expected(1, expected_element, tag_usage, tag, msg, source, "add_expected() => expected: " & to_string_element(expected_element) & ". ");
else
add_expected(1, expected_element, tag_usage, tag, msg, source, "add_expected() => expected: " & to_string_element(expected_element) & ", tag: " & to_string(tag) & ". ");
end if;
end procedure add_expected;
procedure add_expected(
constant instance : in integer;
constant expected_element : in t_element;
constant msg : in string := "";
constant source : in string := ""
) is
begin
add_expected(instance, expected_element, NO_TAG, "", msg, source);
end procedure add_expected;
procedure add_expected(
constant expected_element : in t_element;
constant msg : in string := "";
constant source : in string := ""
) is
begin
add_expected(expected_element, NO_TAG, "", msg, source);
end procedure add_expected;
----------------------------------------------------------------------------------------------------
--
-- check_received
--
-- Checks received against expected. Updates counters acording to match/mismatch and configuration.
--
----------------------------------------------------------------------------------------------------
procedure check_received(
constant instance : in integer;
constant received_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "check_received";
procedure check_pending_exists(
constant instance : in integer
) is
begin
check_value(not vr_sb_queue.is_empty(instance), TB_ERROR, "instance " & to_string(instance) & ": no pending entries to check.", vr_scope, ID_NEVER);
end procedure check_pending_exists;
procedure check_received_instance(
constant instance : in integer
) is
variable v_matched : boolean := false;
variable v_entry : t_sb_entry;
variable v_dropped_num : natural := 0;
begin
check_pending_exists(instance);
-- If OOB
if vr_config(instance).allow_out_of_order then
-- Loop through entries in queue until match
for i in 1 to get_pending_count(instance) loop
v_entry := vr_sb_queue.peek(instance, POSITION, i);
if match_received_vs_entry(received_element, v_entry, tag_usage, tag) then
v_matched := true;
-- Delete entry
vr_sb_queue.delete(instance, POSITION, i, SINGLE);
exit;
end if;
end loop;
-- If LOSSY
elsif vr_config(instance).allow_lossy then
-- Loop through entries in queue until match
for i in 1 to get_pending_count(instance) loop
v_entry := vr_sb_queue.peek(instance, POSITION, i);
if match_received_vs_entry(received_element, v_entry, tag_usage, tag) then
v_matched := true;
-- Delete matching entry and preceding entries
for j in i downto 1 loop
vr_sb_queue.delete(instance, POSITION, j, SINGLE);
end loop;
v_dropped_num := i - 1;
exit;
end if;
end loop;
-- Not OOB or LOSSY
else
v_entry := vr_sb_queue.peek(instance);
if match_received_vs_entry(received_element, v_entry, tag_usage, tag) then
v_matched := true;
-- delete entry
vr_sb_queue.delete(instance, POSITION, 1, SINGLE);
elsif not(vr_match_cnt(instance) = 0 and vr_config(instance).ignore_initial_garbage) then
vr_sb_queue.delete(instance, POSITION, 1, SINGLE);
end if;
end if;
-- Update counters
vr_drop_cnt(instance) := vr_drop_cnt(instance) + v_dropped_num;
if v_matched then
vr_match_cnt(instance) := vr_match_cnt(instance) + 1;
elsif vr_match_cnt(instance) = 0 and vr_config(instance).ignore_initial_garbage then
vr_initial_garbage_cnt(instance) := vr_initial_garbage_cnt(instance) + 1;
else
vr_mismatch_cnt(instance) := vr_mismatch_cnt(instance) + 1;
end if;
-- Check if overdue time
if v_matched and (vr_config(instance).overdue_check_time_limit /= 0 ns) and (now-v_entry.entry_time > vr_config(instance).overdue_check_time_limit) then
if ext_proc_call = "" then
alert(vr_config(instance).overdue_check_alert_level, proc_name & "() instance " & to_string(instance) &" => TIME LIMIT OVERDUE: time limit is "
& to_string(vr_config(instance).overdue_check_time_limit) & ", time from entry is " & to_string(now-v_entry.entry_time) & ". " & add_msg_delimiter(msg) , vr_scope);
else
alert(vr_config(instance).overdue_check_alert_level, ext_proc_call & " => TIME LIMIT OVERDUE: time limit is " & to_string(vr_config(instance).overdue_check_time_limit) &
", time from entry is " & to_string(now-v_entry.entry_time) & ". " & add_msg_delimiter(msg) , vr_scope);
end if;
-- Update counter
vr_overdue_check_cnt(instance) := vr_overdue_check_cnt(instance) + 1;
end if;
-- Logging
if v_matched then
if ext_proc_call = "" then
if tag_usage = NO_TAG then
log(instance, ID_DATA, proc_name & "() instance " & to_string(instance) & " => MATCH, for value: " & to_string_element(v_entry.expected_element) &
". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, proc_name & "() instance " & to_string(instance) & " => MATCH, for value: " & to_string_element(v_entry.expected_element) &
". tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
end if;
-- Called from other SB method
else
if tag_usage = NO_TAG then
log(instance, ID_DATA, ext_proc_call & " => MATCH, for received: " & to_string_element(received_element) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & " => MATCH, for received: " & to_string_element(received_element) & ", tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
end if;
end if;
-- Initial garbage
elsif not(vr_match_cnt(instance) = 0 and vr_config(instance).ignore_initial_garbage) then
if ext_proc_call = "" then
if tag_usage = NO_TAG then
alert(vr_config(instance).mismatch_alert_level, proc_name & "() instance " & to_string(instance) & " => MISMATCH, expected: " & to_string_element(v_entry.expected_element) &
"; received: " & to_string_element(received_element) & ". " & add_msg_delimiter(msg), vr_scope);
else
alert(vr_config(instance).mismatch_alert_level, proc_name & "() instance " & to_string(instance) & " => MISMATCH, expected: " & to_string_element(v_entry.expected_element) & ", tag: '" & to_string(v_entry.tag) &
"'; received: " & to_string_element(received_element) & ", tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
end if;
else
if tag_usage = NO_TAG then
alert(vr_config(instance).mismatch_alert_level, ext_proc_call & " => MISMATCH, expected: " & to_string_element(v_entry.expected_element) &
"; received: " & to_string_element(received_element) & add_msg_delimiter(msg), vr_scope);
else
alert(vr_config(instance).mismatch_alert_level, ext_proc_call & " => MISMATCH, expected: " & to_string_element(v_entry.expected_element) & ", tag: " & to_string(v_entry.tag) &
"; received: " & to_string_element(received_element) & ", tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
end if;
end if;
end if;
end procedure check_received_instance;
begin
-- Check if instance is within range
if instance /= ALL_ENABLED_INSTANCES then
check_instance_in_range(instance);
end if;
if instance = ALL_ENABLED_INSTANCES then
for i in 0 to C_MAX_QUEUE_INSTANCE_NUM loop
if vr_instance_enabled(i) then
check_received_instance(i);
end if;
end loop;
else
check_instance_enabled(instance);
check_received_instance(instance);
end if;
end procedure check_received;
procedure check_received(
constant received_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := ""
) is
begin
check_received(1, received_element, tag_usage, tag, msg, "check_received()");
end procedure check_received;
procedure check_received(
constant instance : in integer;
constant received_element : in t_element;
constant msg : in string := ""
) is
begin
check_received(instance, received_element, NO_TAG, "", msg);
end procedure check_received;
procedure check_received(
constant received_element : in t_element;
constant msg : in string := ""
) is
begin
check_received(received_element, NO_TAG, "", msg);
end procedure check_received;
----------------------------------------------------------------------------------------------------
--
-- flush
--
-- Deletes all entries in queue and updates delete counter.
--
----------------------------------------------------------------------------------------------------
procedure flush(
constant instance : in integer;
constant msg : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "flush";
begin
if instance = ALL_INSTANCES then
log(ID_DATA, proc_name & ": flushing all instances." & add_msg_delimiter(msg), vr_scope);
for i in 0 to C_MAX_QUEUE_INSTANCE_NUM loop
-- update counters
vr_delete_cnt(i) := vr_delete_cnt(i) + vr_sb_queue.get_count(i);
-- flush queue
vr_sb_queue.flush(i);
end loop;
elsif instance = ALL_ENABLED_INSTANCES then
log(ID_DATA, proc_name & ": flushing all enabled instances." & add_msg_delimiter(msg), vr_scope);
for i in 0 to C_MAX_QUEUE_INSTANCE_NUM loop
if vr_instance_enabled(i) then
-- update counters
vr_delete_cnt(i) := vr_delete_cnt(i) + vr_sb_queue.get_count(i);
-- flush queue
vr_sb_queue.flush(i);
end if;
end loop;
else
if ext_proc_call = "" then
log(instance, ID_DATA, proc_name & ": flushing instance " & to_string(instance) & "." & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
check_instance_in_range(instance);
check_instance_enabled(instance);
-- update counters
vr_delete_cnt(instance) := vr_delete_cnt(instance) + vr_sb_queue.get_count(instance);
-- flush queue
vr_sb_queue.flush(instance);
end if;
end procedure flush;
procedure flush(
constant msg : in string
) is
begin
flush(1, msg, "flush: flushing SB.");
end procedure flush;
procedure flush(
constant void : in t_void
) is
begin
flush("");
end procedure flush;
----------------------------------------------------------------------------------------------------
--
-- reset
--
-- Resets all counters and flushes queue. Also resets entry number count.
--
----------------------------------------------------------------------------------------------------
procedure reset(
constant instance : in integer;
constant msg : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "reset";
procedure reset_instance(
constant instance : natural
) is
begin
-- reset instance 0 only if it is used
if not(vr_sb_queue.is_empty(0)) or (instance > 0) then
vr_sb_queue.reset(instance);
vr_entered_cnt(instance) := 0;
vr_match_cnt(instance) := 0;
vr_mismatch_cnt(instance) := 0;
vr_drop_cnt(instance) := 0;
vr_initial_garbage_cnt(instance) := 0;
vr_delete_cnt(instance) := 0;
vr_overdue_check_cnt(instance) := 0;
end if;
end procedure reset_instance;
begin
if instance = ALL_INSTANCES then
log(ID_CTRL, proc_name & ": reseting all instances. " & add_msg_delimiter(msg), vr_scope);
for i in 0 to C_MAX_QUEUE_INSTANCE_NUM loop
reset_instance(i);
end loop;
elsif instance = ALL_ENABLED_INSTANCES then
log(ID_CTRL, proc_name & ": reseting all enabled instances. " & add_msg_delimiter(msg), vr_scope);
for i in 0 to C_MAX_QUEUE_INSTANCE_NUM loop
if vr_instance_enabled(i) then
reset_instance(i);
end if;
end loop;
else
if ext_proc_call = "" then
log(instance, ID_CTRL, proc_name & ": reseting instance " & to_string(instance) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_CTRL, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
check_instance_in_range(instance);
check_instance_enabled(instance);
reset_instance(instance);
end if;
end procedure reset;
procedure reset(
constant msg : in string
) is
begin
reset(1, msg, "reset: reseting SB.");
end procedure reset;
procedure reset(
constant void : in t_void
) is
begin
reset("");
end procedure reset;
----------------------------------------------------------------------------------------------------
--
-- is_empty
--
-- Returns true if scoreboard instance is empty, false if not.
--
----------------------------------------------------------------------------------------------------
impure function is_empty(
constant instance : in integer
) return boolean is
begin
return vr_sb_queue.is_empty(instance);
end function is_empty;
impure function is_empty(
constant void : in t_void
) return boolean is
begin
return is_empty(1);
end function is_empty;
----------------------------------------------------------------------------------------------------
--
-- get_entered_count
--
-- Returns total number of entries made to scoreboard instance.
-- Added + inserted.
--
----------------------------------------------------------------------------------------------------
impure function get_entered_count(
constant instance : in integer
) return integer is
begin
return vr_entered_cnt(instance);
end function get_entered_count;
impure function get_entered_count(
constant void : in t_void
) return integer is
begin
return get_entered_count(1);
end function get_entered_count;
----------------------------------------------------------------------------------------------------
--
-- get_pending_count
--
-- Returns number of entries en scoreboard instance at the moment.
-- Added + inserted - checked - deleted.
--
----------------------------------------------------------------------------------------------------
impure function get_pending_count(
constant instance : in integer
) return integer is
begin
if vr_entered_cnt(instance) = -1 then
return -1;
else
return vr_sb_queue.get_count(instance);
end if;
end function get_pending_count;
impure function get_pending_count(
constant void : in t_void
) return integer is
begin
return get_pending_count(1);
end function get_pending_count;
----------------------------------------------------------------------------------------------------
--
-- get_match_count
--
-- Returns number of entries checked and matched against a received.
--
----------------------------------------------------------------------------------------------------
impure function get_match_count(
constant instance : in integer
) return integer is
begin
return vr_match_cnt(instance);
end function get_match_count;
impure function get_match_count(
constant void : in t_void
) return integer is
begin
return get_match_count(1);
end function get_match_count;
----------------------------------------------------------------------------------------------------
--
-- get_mismatch_count
--
-- Returns number of entries checked and not matched against a received.
--
----------------------------------------------------------------------------------------------------
impure function get_mismatch_count(
constant instance : in integer
) return integer is
begin
return vr_mismatch_cnt(instance);
end function get_mismatch_count;
impure function get_mismatch_count(
constant void : in t_void
) return integer is
begin
return get_mismatch_count(1);
end function get_mismatch_count;
----------------------------------------------------------------------------------------------------
--
-- get_drop_count
--
-- Returns number of entries dropped, total number of preceding entries before match.
-- Only relevant during lossy mode.
--
----------------------------------------------------------------------------------------------------
impure function get_drop_count(
constant instance : in integer
) return integer is
begin
return vr_drop_cnt(instance);
end function get_drop_count;
impure function get_drop_count(
constant void : in t_void
) return integer is
begin
return get_drop_count(1);
end function get_drop_count;
----------------------------------------------------------------------------------------------------
--
-- get_initial_garbage_count
--
-- Returns number of received checked before first match.
-- Only relevant when allow_initial_garbage is enabled.
--
----------------------------------------------------------------------------------------------------
impure function get_initial_garbage_count(
constant instance : in integer
) return integer is
begin
return vr_initial_garbage_cnt(instance);
end function get_initial_garbage_count;
impure function get_initial_garbage_count(
constant void : in t_void
) return integer is
begin
return get_initial_garbage_count(1);
end function get_initial_garbage_count;
----------------------------------------------------------------------------------------------------
--
-- get_delete_count
--
-- Returns number of deleted entries.
-- Delete + fetch + flush.
--
----------------------------------------------------------------------------------------------------
impure function get_delete_count(
constant instance : in integer
) return integer is
begin
return vr_delete_cnt(instance);
end function get_delete_count;
impure function get_delete_count(
constant void : in t_void
) return integer is
begin
return get_delete_count(1);
end function get_delete_count;
----------------------------------------------------------------------------------------------------
--
-- get_overdue_check_count
--
-- Returns number of received checked when time limit is overdue.
-- Only relevant when overdue_check_time_limit is set.
--
----------------------------------------------------------------------------------------------------
impure function get_overdue_check_count(
constant instance : in integer
) return integer is
begin
return vr_overdue_check_cnt(instance);
end function get_overdue_check_count;
impure function get_overdue_check_count(
constant void : in t_void
) return integer is
begin
return get_overdue_check_count(1);
end function get_overdue_check_count;
----------------------------------------------------------------------------------------------------
--
-- set_scope / get_scope
--
-- Set/Get the scope of the scoreboard.
--
----------------------------------------------------------------------------------------------------
procedure set_scope(
constant scope : in string
) is
begin
vr_scope := pad_string(scope, NUL, C_LOG_SCOPE_WIDTH);
end procedure set_scope;
impure function get_scope(
constant void : in t_void
) return string is
begin
return vr_scope;
end function get_scope;
----------------------------------------------------------------------------------------------------
--
-- enable_log_msg
--
-- Enables the specified message id for the instance.
--
----------------------------------------------------------------------------------------------------
procedure enable_log_msg(
constant instance : in integer;
constant msg_id : in t_msg_id;
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "enable_log_msg";
begin
if instance = ALL_INSTANCES then
log(ID_CTRL, proc_name & ": message id " & to_string(msg_id) & " enabled for all instances", vr_scope);
for i in 0 to C_MAX_QUEUE_INSTANCE_NUM loop
vr_msg_id_panel_array(i)(msg_id) := ENABLED;
end loop;
else
if ext_proc_call = "" then
log(instance, ID_CTRL, proc_name & ": message id " & to_string(msg_id) & " enabled for instance " & to_string(instance), vr_scope);
else
log(instance, ID_CTRL, ext_proc_call, vr_scope);
end if;
vr_msg_id_panel_array(instance)(msg_id) := ENABLED;
end if;
end procedure enable_log_msg;
procedure enable_log_msg(
constant msg_id : in t_msg_id
) is
begin
enable_log_msg(1, msg_id, "enable_log_msg: "& ": message id " & to_string(msg_id) & " enabled");
end procedure enable_log_msg;
----------------------------------------------------------------------------------------------------
--
-- disable_log_msg
--
-- Disables the specified message id for the instance.
--
----------------------------------------------------------------------------------------------------
procedure disable_log_msg(
constant instance : in integer;
constant msg_id : in t_msg_id;
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "disable_log_msg";
begin
if instance = ALL_INSTANCES then
log(ID_CTRL, proc_name & ": message id " & to_string(msg_id) & " disabled for all instances", vr_scope);
for i in 0 to C_MAX_QUEUE_INSTANCE_NUM loop
vr_msg_id_panel_array(i)(msg_id) := DISABLED;
end loop;
else
if ext_proc_call = "" then
log(instance, ID_CTRL, proc_name & ": message id " & to_string(msg_id) & " disabled for instance " & to_string(instance), vr_scope);
else
log(instance, ID_CTRL, ext_proc_call, vr_scope);
end if;
vr_msg_id_panel_array(instance)(msg_id) := DISABLED;
end if;
end procedure disable_log_msg;
procedure disable_log_msg(
constant msg_id : in t_msg_id
) is
begin
disable_log_msg(1, msg_id, "disable_log_msg: "& ": message id " & to_string(msg_id) & " disabled");
end procedure disable_log_msg;
----------------------------------------------------------------------------------------------------
--
-- report_conters
--
-- Prints a report of all counters to transcript for either specified instance, all enabled
-- instances or all instances.
--
----------------------------------------------------------------------------------------------------
procedure report_counters(
constant instance : in integer;
constant ext_proc_call : in string := ""
) is
variable v_line : line;
variable v_line_copy : line;
variable v_status_failed : boolean := true;
variable v_mismatch : boolean := false;
constant C_HEADER : string := "*** SCOREBOARD COUNTERS SUMMARY: " & to_string(vr_scope) & " ***";
constant prefix : string := C_LOG_PREFIX & " ";
constant log_counter_width : positive := 8; -- shouldn't be smaller than 8 due to the counters names
variable v_log_extra_space : integer := 0;
-- add simulation time stamp to scoreboard report header
impure function timestamp_header(value : time; txt : string) return string is
variable v_line : line;
variable v_delimiter_pos : natural;
variable v_timestamp_width : natural;
variable v_result : string(1 to 50);
variable v_return : string(1 to txt'length) := txt;
begin
-- get a time stamp
write(v_line, value, LEFT, 0, C_LOG_TIME_BASE);
v_timestamp_width := v_line'length;
v_result(1 to v_timestamp_width) := v_line.all;
deallocate(v_line);
v_delimiter_pos := pos_of_leftmost('.', v_result(1 to v_timestamp_width), 0);
-- truncate decimals and add units
if C_LOG_TIME_BASE = ns then
v_result(v_delimiter_pos+2 to v_delimiter_pos+5) := " ns ";
else
v_result(v_delimiter_pos+2 to v_delimiter_pos+5) := " ps ";
end if;
v_timestamp_width := v_delimiter_pos + 5;
-- add time string to return string
v_return := v_result(1 to v_timestamp_width) & txt(1 to txt'length-v_timestamp_width);
return v_return(1 to txt'length);
end function timestamp_header;
begin
-- Calculate how much space we can insert between the columns of the report
v_log_extra_space := (C_LOG_LINE_WIDTH - prefix'length - 20 - log_counter_width*6 - 15 - 13)/8;
if v_log_extra_space < 1 then
alert(TB_WARNING, "C_LOG_LINE_WIDTH is too small, the report will not be properly aligned.", vr_scope);
v_log_extra_space := 1;
end if;
write(v_line,
LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
timestamp_header(now, justify(C_HEADER, LEFT, C_LOG_LINE_WIDTH - prefix'length, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE)) & LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
write(v_line,
justify(
fill_string(' ', 16) &
justify("ENTERED" , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("PENDING" , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("MATCH" , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("MISMATCH" , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("DROP" , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("INITIAL_GARBAGE", center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("DELETE" , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("OVERDUE_CHECK" , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),
left, C_LOG_LINE_WIDTH - prefix'length, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF);
if instance = ALL_INSTANCES or instance = ALL_ENABLED_INSTANCES then
for i in 1 to C_MAX_QUEUE_INSTANCE_NUM loop
if instance = ALL_INSTANCES or (instance = ALL_ENABLED_INSTANCES and vr_instance_enabled(i)) then
write(v_line,
justify(
"instance: " &
justify(to_string(i), right, to_string(C_MAX_QUEUE_INSTANCE_NUM)'length, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
fill_string(' ', 20-4-10-to_string(C_MAX_QUEUE_INSTANCE_NUM)'length) &
justify(to_string(get_entered_count(i)) , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_pending_count(i)) , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_match_count(i)) , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_mismatch_count(i)) , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_drop_count(i)) , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_initial_garbage_count(i)), center, 15, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_delete_count(i)) , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_overdue_check_count(i)) , center, 13, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),
left, C_LOG_LINE_WIDTH - prefix'length, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF);
end if;
end loop;
else
write(v_line,
justify(
"instance: " &
justify(to_string(instance), right, to_string(C_MAX_QUEUE_INSTANCE_NUM)'length, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
fill_string(' ', 20-4-10-to_string(C_MAX_QUEUE_INSTANCE_NUM)'length) &
justify(to_string(get_entered_count(instance)) , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_pending_count(instance)) , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_match_count(instance)) , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_mismatch_count(instance)) , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_drop_count(instance)) , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_initial_garbage_count(instance)), center, 15, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_delete_count(instance)) , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_overdue_check_count(instance)) , center, 13, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),
left, C_LOG_LINE_WIDTH - prefix'length, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF);
end if;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF & LF);
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to transcript
write (v_line_copy, v_line.all); -- copy line
writeline(OUTPUT, v_line);
writeline(LOG_FILE, v_line_copy);
end procedure report_counters;
procedure report_counters(
constant void : in t_void
) is
begin
report_counters(1, "no instance label");
end procedure report_counters;
--==================================================================================================
-- ADVANCED METHODS
--==================================================================================================
----------------------------------------------------------------------------------------------------
--
-- insert_expected
--
-- Inserts expected element to the queue based on position or entry number
--
----------------------------------------------------------------------------------------------------
procedure insert_expected(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant source : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "insert_expected";
variable v_sb_entry : t_sb_entry;
begin
-- Check if instance is within range
if instance /= ALL_ENABLED_INSTANCES then
check_instance_in_range(instance);
end if;
v_sb_entry := (expected_element => expected_element,
source => pad_string(source, NUL, C_SB_SOURCE_WIDTH),
tag => pad_string(tag, NUL, C_SB_TAG_WIDTH),
entry_time => now);
if instance = ALL_ENABLED_INSTANCES then
for i in 0 to C_MAX_QUEUE_INSTANCE_NUM loop
if vr_instance_enabled(i) then
-- Check that instance is enabled
check_queue_empty(instance);
-- add entry
vr_sb_queue.insert(i, identifier_option, identifier, v_sb_entry);
-- increment counters
vr_entered_cnt(i) := vr_entered_cnt(i)+1;
end if;
end loop;
else
-- Check that instance is in valid range and enabled
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
-- add entry
vr_sb_queue.insert(instance, identifier_option, identifier, v_sb_entry);
-- increment counters
vr_entered_cnt(instance) := vr_entered_cnt(instance)+1;
end if;
-- Logging
if ext_proc_call = "" then
if instance = ALL_ENABLED_INSTANCES then
if identifier_option = POSITION then
if tag_usage = NO_TAG then
log(instance, ID_DATA, proc_name & "() inserted expected after entry with position " & to_string(identifier) & " for all enabled instances. Expected: "
& to_string_element(expected_element) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, proc_name & "() inserted expected after entry with position " & to_string(identifier) & " for all enabled instances. Expected: "
& to_string_element(expected_element) & ", tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
end if;
else
if tag_usage = NO_TAG then
log(instance, ID_DATA, proc_name & "() inserted expected after entry with entry number " & to_string(identifier) & " for all enabled instances. Expected: "
& to_string_element(expected_element) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, proc_name & "() inserted expected after entry with entry number " & to_string(identifier) & " for all enabled instances. Expected: "
& to_string_element(expected_element) & ", tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
end if;
end if;
else
if identifier_option = POSITION then
log(instance, ID_DATA, proc_name & "() inserted expected after entry with position " & to_string(identifier) & " for instance " & to_string(instance) & "." & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, proc_name & "() inserted expected after entry with entry number " & to_string(identifier) & " for instance " & to_string(instance) & "." & add_msg_delimiter(msg), vr_scope);
end if;
end if;
else
if tag_usage = NO_TAG then
log(instance, ID_DATA, ext_proc_call & " Expected: " & to_string_element(expected_element) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & " Expected: " & to_string_element(expected_element) & ", tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
end if;
end if;
end procedure insert_expected;
procedure insert_expected(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant source : in string := ""
) is
begin
if identifier_option = POSITION then
insert_expected(1, identifier_option, identifier, expected_element, tag_usage, tag, msg, source, "insert_expected() inserted expected after entry with position " & to_string(identifier) & ".");
else
insert_expected(1, identifier_option, identifier, expected_element, tag_usage, tag, msg, source, "insert_expected() inserted expected after entry with entry number " & to_string(identifier) & ".");
end if;
end procedure insert_expected;
----------------------------------------------------------------------------------------------------
--
-- find_expected_entry_num
--
-- Returns entry number of matching entry, no match returns -1
--
----------------------------------------------------------------------------------------------------
impure function find_expected_entry_num(
constant instance : in integer;
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string
) return integer is
variable v_sb_entry : t_sb_entry;
begin
-- Sanity check
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
for i in 1 to get_pending_count(instance) loop
-- get entry i
v_sb_entry := vr_sb_queue.peek(instance, POSITION, i);
-- check if match
if match_expected_vs_entry(expected_element, v_sb_entry, tag_usage, tag) then
return vr_sb_queue.get_entry_num(instance, i);
end if;
end loop;
return -1;
end function find_expected_entry_num;
impure function find_expected_entry_num(
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string
) return integer is
begin
return find_expected_entry_num(1, expected_element, tag_usage, tag);
end function find_expected_entry_num;
impure function find_expected_entry_num(
constant instance : in integer;
constant expected_element : in t_element
) return integer is
begin
return find_expected_entry_num(instance, expected_element, NO_TAG, "");
end function find_expected_entry_num;
impure function find_expected_entry_num(
constant expected_element : in t_element
) return integer is
begin
return find_expected_entry_num(1, expected_element, NO_TAG, "");
end function find_expected_entry_num;
impure function find_expected_entry_num(
constant instance : in integer;
constant tag_usage : in t_tag_usage;
constant tag : in string
) return integer is
variable v_sb_entry : t_sb_entry;
begin
-- Sanity check
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
for i in 1 to get_pending_count(instance) loop
-- get entry i
v_sb_entry := vr_sb_queue.peek(instance, POSITION, i);
-- check if match
if v_sb_entry.tag = pad_string(tag, NUL, C_SB_TAG_WIDTH) then
return vr_sb_queue.get_entry_num(instance, i);
end if;
end loop;
return -1;
end function find_expected_entry_num;
impure function find_expected_entry_num(
constant tag_usage : in t_tag_usage;
constant tag : in string
) return integer is
begin
return find_expected_entry_num(1, tag_usage, tag);
end function find_expected_entry_num;
----------------------------------------------------------------------------------------------------
--
-- find_expected_position
--
-- Returns position of matching entry, no match returns -1
--
----------------------------------------------------------------------------------------------------
impure function find_expected_position(
constant instance : in integer;
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string
) return integer is
variable v_sb_entry : t_sb_entry;
begin
-- Sanity check
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
for i in 1 to get_pending_count(instance) loop
-- get entry i
v_sb_entry := vr_sb_queue.peek(instance, POSITION, i);
-- check if match
if match_expected_vs_entry(expected_element, v_sb_entry, tag_usage, tag) then
return i;
end if;
end loop;
return -1;
end function find_expected_position;
impure function find_expected_position(
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string
) return integer is
begin
return find_expected_position(1, expected_element, tag_usage, tag);
end function find_expected_position;
impure function find_expected_position(
constant instance : in integer;
constant expected_element : in t_element
) return integer is
begin
return find_expected_position(instance, expected_element, NO_TAG, "");
end function find_expected_position;
impure function find_expected_position(
constant expected_element : in t_element
) return integer is
begin
return find_expected_position(1, expected_element, NO_TAG, "");
end function find_expected_position;
impure function find_expected_position(
constant instance : in integer;
constant tag_usage : in t_tag_usage;
constant tag : in string
) return integer is
variable v_sb_entry : t_sb_entry;
begin
-- Sanity check
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
for i in 1 to get_pending_count(instance) loop
-- get entry i
v_sb_entry := vr_sb_queue.peek(instance, POSITION, i);
-- check if match
if v_sb_entry.tag = pad_string(tag, NUL, C_SB_TAG_WIDTH) then
return i;
end if;
end loop;
return -1;
end function find_expected_position;
impure function find_expected_position(
constant tag_usage : in t_tag_usage;
constant tag : in string
) return integer is
begin
return find_expected_position(1, tag_usage, tag);
end function find_expected_position;
----------------------------------------------------------------------------------------------------
--
-- delete_expected
--
-- Deletes expected element in queue based on specified element, position or entry number
--
----------------------------------------------------------------------------------------------------
procedure delete_expected(
constant instance : in integer;
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "delete_expected";
variable v_position : integer;
begin
-- Sanity checks done in find_expected_position
v_position := find_expected_position(instance, expected_element, tag_usage, tag);
if v_position /= -1 then
vr_sb_queue.delete(instance, POSITION, v_position, SINGLE);
vr_delete_cnt(instance) := vr_delete_cnt(instance) + 1;
if ext_proc_call = "" then
log(instance, ID_DATA, proc_name & ": instance " & to_string(instance) & ", value: " & to_string_element(expected_element) & ", tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
else
log(instance, ID_DATA, proc_name & ": NO DELETION. Did not find matching entry. " & add_msg_delimiter(msg), vr_scope);
end if;
end procedure delete_expected;
procedure delete_expected(
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := ""
) is
begin
delete_expected(1, expected_element, tag_usage, tag, msg, "delete_expected: value: " & to_string_element(expected_element) & ", tag: '" & to_string(tag) & "'. ");
end procedure delete_expected;
procedure delete_expected(
constant instance : in integer;
constant expected_element : in t_element;
constant msg : in string := ""
) is
begin
delete_expected(instance, expected_element, NO_TAG, "", msg, "delete_expected: instance " & to_string(instance) & ", value: " & to_string_element(expected_element) & ". ");
end procedure delete_expected;
procedure delete_expected(
constant expected_element : in t_element;
constant msg : in string := ""
) is
begin
delete_expected(1, expected_element, NO_TAG, "", msg, "delete_expected: instance value: " & to_string_element(expected_element) & ". ");
end procedure delete_expected;
procedure delete_expected(
constant instance : in integer;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "delete_expected";
variable v_position : integer;
begin
-- Sanity checks done in find_expected_position
v_position := find_expected_position(instance, tag_usage, tag);
if v_position /= -1 then
vr_sb_queue.delete(instance, POSITION, v_position, SINGLE);
vr_delete_cnt(instance) := vr_delete_cnt(instance) + 1;
if ext_proc_call = "" then
log(instance, ID_DATA, proc_name & ": instance " & to_string(instance) & ", tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
else
log(instance, ID_DATA, proc_name & ": NO DELETION. Did not find matching entry. " & add_msg_delimiter(msg), vr_scope);
end if;
end procedure delete_expected;
procedure delete_expected(
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := ""
) is
begin
delete_expected(1, tag_usage, tag, msg, "delete_expected: tag: '" & to_string(tag) & "'. ");
end procedure delete_expected;
procedure delete_expected(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive;
constant msg : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "delete_expected";
constant C_PRE_DELETE_PENDING_CNT : natural := vr_sb_queue.get_count(instance);
variable v_num_deleted : natural;
begin
-- Sanity check
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
-- Delete entries
vr_sb_queue.delete(instance, identifier_option, identifier_min, identifier_max);
v_num_deleted := C_PRE_DELETE_PENDING_CNT - vr_sb_queue.get_count(instance);
vr_delete_cnt(instance) := vr_delete_cnt(instance) + v_num_deleted;
-- If error
if v_num_deleted = 0 then
log(instance, ID_DATA, proc_name & ": NO DELETION. Did not find matching entry. " & add_msg_delimiter(msg), vr_scope);
else
if ext_proc_call = "" then
log(instance, ID_DATA, proc_name & ": instance " & to_string(instance) & ", entries with identifier " & to_string(identifier_option) &
" range " & to_string(identifier_min) & " to " & to_string(identifier_max) & " deleted. " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
end if;
end procedure delete_expected;
procedure delete_expected(
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive;
constant msg : in string := ""
) is
begin
delete_expected(1, identifier_option, identifier_min, identifier_max, msg, "delete_expected: entries with identifier " & to_string(identifier_option) &
" range " & to_string(identifier_min) & " to " & to_string(identifier_max) & " deleted. ");
end procedure delete_expected;
procedure delete_expected(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option;
constant msg : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "delete_expected";
constant C_PRE_DELETE_PENDING_CNT : natural := vr_sb_queue.get_count(instance);
variable v_num_deleted : natural;
begin
-- Sanity check
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
-- Delete entries
vr_sb_queue.delete(instance, identifier_option, identifier, range_option);
v_num_deleted := C_PRE_DELETE_PENDING_CNT - vr_sb_queue.get_count(instance);
vr_delete_cnt(instance) := vr_delete_cnt(instance) + v_num_deleted;
-- If error
if v_num_deleted = 0 then
log(instance, ID_DATA, proc_name & ": NO DELETION. Did not find matching entry. " & add_msg_delimiter(msg), vr_scope);
else
if ext_proc_call = "" then
if range_option = SINGLE then
log(instance, ID_DATA, proc_name & ": instance " & to_string(instance) & ", entry with identifier " & to_string(identifier_option) &
" " & to_string(identifier) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, proc_name & ": instance " & to_string(instance) & ", entries with identifier " & to_string(identifier_option) &
" range " & to_string(identifier) & " " & to_string(range_option) & " deleted. " & add_msg_delimiter(msg), vr_scope);
end if;
else
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
end if;
end procedure delete_expected;
procedure delete_expected(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option;
constant msg : in string := ""
) is
begin
if range_option = SINGLE then
delete_expected(1, identifier_option, identifier, range_option, msg, "delete_expected: entry with identifier '" & to_string(identifier_option) &
" " & to_string(identifier) & " deleted. ");
else
delete_expected(1, identifier_option, identifier, range_option, msg, "delete_expected: entries with identifier '" & to_string(identifier_option) &
" range " & to_string(identifier) & " to " & to_string(range_option) & " deleted. ");
end if;
end procedure delete_expected;
----------------------------------------------------------------------------------------------------
-- non public local_entry
-- Used by all peek functions
----------------------------------------------------------------------------------------------------
impure function peek_entry(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive
) return t_sb_entry is
begin
-- Check that instance is in valid range and enabled
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
return vr_sb_queue.peek(instance, identifier_option, identifier);
end function peek_entry;
----------------------------------------------------------------------------------------------------
--
-- peek_expected
--
-- Returns expected element from queue entry based on position or entry number without deleting entry
--
----------------------------------------------------------------------------------------------------
impure function peek_expected(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive
) return t_element is
begin
return peek_entry(instance, identifier_option, identifier).expected_element;
end function peek_expected;
impure function peek_expected(
constant identifier_option : t_identifier_option;
constant identifier : positive
) return t_element is
begin
return peek_entry(1, identifier_option, identifier).expected_element;
end function peek_expected;
impure function peek_expected(
constant instance : integer
) return t_element is
begin
return peek_entry(instance, POSITION, 1).expected_element;
end function peek_expected;
impure function peek_expected(
constant void : t_void
) return t_element is
begin
return peek_entry(1, POSITION, 1).expected_element;
end function peek_expected;
----------------------------------------------------------------------------------------------------
--
-- peek_source
--
-- Returns source element from queue entry based on position or entry number without deleting entry
--
----------------------------------------------------------------------------------------------------
impure function peek_source(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive
) return string is
begin
return to_string(peek_entry(instance, identifier_option, identifier).source);
end function peek_source;
impure function peek_source(
constant identifier_option : t_identifier_option;
constant identifier : positive
) return string is
begin
return peek_source(1, identifier_option, identifier);
end function peek_source;
impure function peek_source(
constant instance : integer
) return string is
begin
return peek_source(instance, POSITION, 1);
end function peek_source;
impure function peek_source(
constant void : t_void
) return string is
begin
return peek_source(1, POSITION, 1);
end function peek_source;
----------------------------------------------------------------------------------------------------
--
-- peek_tag
--
-- Returns tag from queue entry based on position or entry number without deleting entry
--
----------------------------------------------------------------------------------------------------
impure function peek_tag(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive
) return string is
begin
return to_string(peek_entry(instance, identifier_option, identifier).tag);
end function peek_tag;
impure function peek_tag(
constant identifier_option : t_identifier_option;
constant identifier : positive
) return string is
begin
return peek_tag(1, identifier_option, identifier);
end function peek_tag;
impure function peek_tag(
constant instance : integer
) return string is
begin
return peek_tag(instance, POSITION, 1);
end function peek_tag;
impure function peek_tag(
constant void : t_void
) return string is
begin
return peek_tag(1, POSITION, 1);
end function peek_tag;
----------------------------------------------------------------------------------------------------
-- Non public fetch_entry
-- Used by all fetch functions
----------------------------------------------------------------------------------------------------
impure function fetch_entry(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive
) return t_sb_entry is
variable v_sb_entry : t_sb_entry;
begin
-- Sanity check
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
v_sb_entry := vr_sb_queue.fetch(instance, identifier_option, identifier);
vr_delete_cnt(instance) := vr_delete_cnt(instance) + 1;
return v_sb_entry;
end function fetch_entry;
----------------------------------------------------------------------------------------------------
--
-- fetch_expected
--
-- Returns expected element from queue entry based on position or entry number and deleting entry
--
----------------------------------------------------------------------------------------------------
impure function fetch_expected(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "";
constant ext_proc_call : string := ""
) return t_element is
constant proc_name : string := "fetch_expected";
begin
-- Sanity checks in fetch entry
-- Logging
if ext_proc_call = "" then
log(instance, ID_DATA, proc_name & ": instance " & to_string(instance) & ", fetching expected by " & to_string(identifier_option) & " " &
to_string(identifier) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
return fetch_entry(instance, identifier_option, identifier).expected_element;
end function fetch_expected;
impure function fetch_expected(
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := ""
) return t_element is
begin
return fetch_expected(1, identifier_option, identifier, msg, "fetch_expected: fetching expected by " &
to_string(identifier_option) & " " & to_string(identifier) & ". ");
end function fetch_expected;
impure function fetch_expected(
constant instance : integer;
constant msg : string := ""
) return t_element is
begin
return fetch_expected(instance, POSITION, 1, msg);
end function fetch_expected;
impure function fetch_expected(
constant msg : string
) return t_element is
begin
return fetch_expected(POSITION, 1, msg);
end function fetch_expected;
impure function fetch_expected(
constant void : t_void
) return t_element is
begin
return fetch_expected(POSITION, 1);
end function fetch_expected;
----------------------------------------------------------------------------------------------------
--
-- fetch_source
--
-- Returns source element from queue entry based on position or entry number and deleting entry
--
----------------------------------------------------------------------------------------------------
impure function fetch_source(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "";
constant ext_proc_call : string := ""
) return string is
constant proc_name : string := "fetch_source";
begin
-- Sanity checks in fetch entry
-- Logging
if ext_proc_call = "" then
log(instance, ID_DATA, proc_name & ": instance " & to_string(instance) & ", fetching source by " & to_string(identifier_option) & " " &
to_string(identifier) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
return to_string(fetch_entry(instance, identifier_option, identifier).source);
end function fetch_source;
impure function fetch_source(
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := ""
) return string is
begin
return fetch_source(1, identifier_option, identifier, msg, "fetch_source: fetching source by " &
to_string(identifier_option) & " " & to_string(identifier) & ". ");
end function fetch_source;
impure function fetch_source(
constant instance : integer;
constant msg : string := ""
) return string is
begin
return fetch_source(instance, POSITION, 1, msg);
end function fetch_source;
impure function fetch_source(
constant msg : string
) return string is
begin
return fetch_source(POSITION, 1, msg);
end function fetch_source;
impure function fetch_source(
constant void : t_void
) return string is
begin
return fetch_source(POSITION, 1);
end function fetch_source;
----------------------------------------------------------------------------------------------------
--
-- fetch_tag
--
-- Returns tag from queue entry based on position or entry number and deleting entry
--
----------------------------------------------------------------------------------------------------
impure function fetch_tag(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "";
constant ext_proc_call : string := ""
) return string is
constant proc_name : string := "fetch_tag";
begin
-- Sanity checks in fetch entry
-- Logging
if ext_proc_call = "" then
log(instance, ID_DATA, proc_name & ": instance " & to_string(instance) & ", fetching tag by " & to_string(identifier_option) & " " &
to_string(identifier) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
return to_string(fetch_entry(instance, identifier_option, identifier).tag);
end function fetch_tag;
impure function fetch_tag(
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := ""
) return string is
begin
return fetch_tag(1, identifier_option, identifier, msg, "fetch_tag: fetching tag by " &
to_string(identifier_option) & " " & to_string(identifier) & ". ");
end function fetch_tag;
impure function fetch_tag(
constant instance : integer;
constant msg : string := ""
) return string is
begin
return fetch_tag(instance, POSITION, 1, msg);
end function fetch_tag;
impure function fetch_tag(
constant msg : string
) return string is
begin
return fetch_tag(POSITION, 1, msg);
end function fetch_tag;
impure function fetch_tag(
constant void : t_void
) return string is
begin
return fetch_tag(POSITION, 1);
end function fetch_tag;
----------------------------------------------------------------------------------------------------
--
-- exists
--
-- Returns true if entry exists, false if not.
--
----------------------------------------------------------------------------------------------------
impure function exists(
constant instance : integer;
constant expected_element : t_element;
constant tag_usage : t_tag_usage := NO_TAG;
constant tag : string := ""
) return boolean is
begin
return (find_expected_position(instance, expected_element, tag_usage, tag) /= C_NO_MATCH);
end function exists;
impure function exists(
constant expected_element : t_element;
constant tag_usage : t_tag_usage := NO_TAG;
constant tag : string := ""
) return boolean is
begin
return exists(1, expected_element, tag_usage, tag);
end function exists;
impure function exists(
constant instance : integer;
constant tag_usage : t_tag_usage;
constant tag : string
) return boolean is
begin
return (find_expected_position(instance, tag_usage, tag) /= C_NO_MATCH);
end function exists;
impure function exists(
constant tag_usage : t_tag_usage;
constant tag : string
) return boolean is
begin
return exists(1, tag_usage, tag);
end function exists;
end protected body;
end package body generic_sb_pkg;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Generated from core with identifier: xilinx.com:ip:fifo_generator:9.2 --
-- --
-- The FIFO Generator is a parameterizable first-in/first-out memory --
-- queue generator. Use it to generate resource and performance --
-- optimized FIFOs with common or independent read/write clock domains, --
-- and optional fixed or programmable full and empty flags and --
-- handshaking signals. Choose from a selection of memory resource --
-- types for implementation. Optional Hamming code based error --
-- detection and correction as well as error injection capability for --
-- system test help to insure data integrity. FIFO width and depth are --
-- parameterizable, and for native interface FIFOs, asymmetric read and --
-- write port widths are also supported. --
--------------------------------------------------------------------------------
-- Synthesized Netlist Wrapper
-- This file is provided to wrap around the synthesized netlist (if appropriate)
-- Interfaces:
-- AXI4Stream_MASTER_M_AXIS
-- AXI4Stream_SLAVE_S_AXIS
-- AXI4_MASTER_M_AXI
-- AXI4_SLAVE_S_AXI
-- AXI4Lite_MASTER_M_AXI
-- AXI4Lite_SLAVE_S_AXI
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY image_selector_fifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END image_selector_fifo;
ARCHITECTURE spartan6 OF image_selector_fifo IS
BEGIN
-- WARNING: This file provides an entity declaration with empty architecture, it
-- does not support direct instantiation. Please use an instantiation
-- template (VHO) to instantiate the IP within a design.
END spartan6;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Generated from core with identifier: xilinx.com:ip:fifo_generator:9.2 --
-- --
-- The FIFO Generator is a parameterizable first-in/first-out memory --
-- queue generator. Use it to generate resource and performance --
-- optimized FIFOs with common or independent read/write clock domains, --
-- and optional fixed or programmable full and empty flags and --
-- handshaking signals. Choose from a selection of memory resource --
-- types for implementation. Optional Hamming code based error --
-- detection and correction as well as error injection capability for --
-- system test help to insure data integrity. FIFO width and depth are --
-- parameterizable, and for native interface FIFOs, asymmetric read and --
-- write port widths are also supported. --
--------------------------------------------------------------------------------
-- Synthesized Netlist Wrapper
-- This file is provided to wrap around the synthesized netlist (if appropriate)
-- Interfaces:
-- AXI4Stream_MASTER_M_AXIS
-- AXI4Stream_SLAVE_S_AXIS
-- AXI4_MASTER_M_AXI
-- AXI4_SLAVE_S_AXI
-- AXI4Lite_MASTER_M_AXI
-- AXI4Lite_SLAVE_S_AXI
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY image_selector_fifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END image_selector_fifo;
ARCHITECTURE spartan6 OF image_selector_fifo IS
BEGIN
-- WARNING: This file provides an entity declaration with empty architecture, it
-- does not support direct instantiation. Please use an instantiation
-- template (VHO) to instantiate the IP within a design.
END spartan6;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Generated from core with identifier: xilinx.com:ip:fifo_generator:9.2 --
-- --
-- The FIFO Generator is a parameterizable first-in/first-out memory --
-- queue generator. Use it to generate resource and performance --
-- optimized FIFOs with common or independent read/write clock domains, --
-- and optional fixed or programmable full and empty flags and --
-- handshaking signals. Choose from a selection of memory resource --
-- types for implementation. Optional Hamming code based error --
-- detection and correction as well as error injection capability for --
-- system test help to insure data integrity. FIFO width and depth are --
-- parameterizable, and for native interface FIFOs, asymmetric read and --
-- write port widths are also supported. --
--------------------------------------------------------------------------------
-- Synthesized Netlist Wrapper
-- This file is provided to wrap around the synthesized netlist (if appropriate)
-- Interfaces:
-- AXI4Stream_MASTER_M_AXIS
-- AXI4Stream_SLAVE_S_AXIS
-- AXI4_MASTER_M_AXI
-- AXI4_SLAVE_S_AXI
-- AXI4Lite_MASTER_M_AXI
-- AXI4Lite_SLAVE_S_AXI
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY image_selector_fifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END image_selector_fifo;
ARCHITECTURE spartan6 OF image_selector_fifo IS
BEGIN
-- WARNING: This file provides an entity declaration with empty architecture, it
-- does not support direct instantiation. Please use an instantiation
-- template (VHO) to instantiate the IP within a design.
END spartan6;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use std.textio.all;
package SIMIO_PACKAGE is
component dspemulator
generic ( DSP_INC_FILE : string := "UNUSED";
ABUS_WIDTH : integer := 16;
DBUS_WIDTH : integer := 16 );
port (
clk : in std_logic;
dspce : out std_logic;
dspa : out std_logic_vector( ABUS_WIDTH-1 downto 0);
data : out std_logic_vector( DBUS_WIDTH-1 downto 0);
wr : out std_logic;
IOstb : out std_logic);
end component ;
component probe
generic ( PROBE_FILE : string := "UNUSED";
SIGNAL1_WIDTH : NATURAL:=6;
SIGNAL1_MASK : integer:=0;
SIGNAL1_TRG : integer:=0;
SIGNAL2_WIDTH : NATURAL:=6;
SIGNAL2_MASK : integer:=0;
SIGNAL2_TRG : integer:=0;
SIGNAL3_WIDTH : NATURAL:=6;
SIGNAL3_MASK : integer:=0;
SIGNAL3_TRG : integer:=0;
SIGNAL4_WIDTH : NATURAL:=6;
SIGNAL4_MASK : integer:=0;
SIGNAL4_TRG : integer:=0);
port (
clk : in std_logic;
signal1 : in std_logic_vector(SIGNAL1_WIDTH-1 downto 0);
signal2 : in std_logic_vector(SIGNAL2_WIDTH-1 downto 0);
signal3 : in std_logic_vector(SIGNAL3_WIDTH-1 downto 0);
signal4 : in std_logic_vector(SIGNAL4_WIDTH-1 downto 0));
end component;
component ADemulator
generic ( AD_FILE : string := "UNUSED";
DATA_WIDTH : integer := 6 );
port (
clk : in std_logic;
ce : in std_logic;
data : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component ;
component DAemulator
generic ( DA_FILE : string := "UNUSED";
DATA_WIDTH : integer := 6 );
port (
clk : in std_logic;
ce : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0));
end component ;
component IQADemulator
generic ( AD_FILE : string := "UNUSED";
DATA_WIDTH : integer := 6 );
port (
clk : in std_logic;
ce : in std_logic;
Iout : out std_logic_vector(DATA_WIDTH-1 downto 0);
Qout : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component ;
component IQDAemulator
generic ( DA_FILE : string := "UNUSED";
DATA_WIDTH : integer := 6 );
port (
clk : in std_logic;
ce : in std_logic;
Iin : in std_logic_vector(DATA_WIDTH-1 downto 0);
Qin : in std_logic_vector(DATA_WIDTH-1 downto 0));
end component ;
function int_to_str( value : integer ) return string;
function hex_str_to_int( str : string ) return integer;
function hex_to_str( value : integer ) return string;
procedure Shrink_line(L : inout LINE; pos : in integer);
end SIMIO_PACKAGE;
package body SIMIO_PACKAGE is
function int_to_str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
while (ivalue > 0 ) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 => line_no(index) := '0';
when 1 => line_no(index) := '1';
when 2 => line_no(index) := '2';
when 3 => line_no(index) := '3';
when 4 => line_no(index) := '4';
when 5 => line_no(index) := '5';
when 6 => line_no(index) := '6';
when 7 => line_no(index) := '7';
when 8 => line_no(index) := '8';
when 9 => line_no(index) := '9';
when others => ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function hex_str_to_int( str : string ) return integer is
variable len : integer := str'length;
variable ivalue : integer := 0;
variable digit : integer;
begin
for i in len downto 1 loop
case str(i) is
when '0' => digit := 0;
when '1' => digit := 1;
when '2' => digit := 2;
when '3' => digit := 3;
when '4' => digit := 4;
when '5' => digit := 5;
when '6' => digit := 6;
when '7' => digit := 7;
when '8' => digit := 8;
when '9' => digit := 9;
when 'A' => digit := 10;
when 'a' => digit := 10;
when 'B' => digit := 11;
when 'b' => digit := 11;
when 'C' => digit := 12;
when 'c' => digit := 12;
when 'D' => digit := 13;
when 'd' => digit := 13;
when 'E' => digit := 14;
when 'e' => digit := 14;
when 'F' => digit := 15;
when 'f' => digit := 15;
when others=>
ASSERT FALSE
REPORT "Illegal character "& str(i) & "in Intel Hex File! "
SEVERITY ERROR;
end case;
ivalue := ivalue * 16 + digit;
end loop;
return ivalue;
end;
function hex_to_str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
while ( index<=8 ) loop
digit := ivalue MOD 16;
ivalue := ivalue/16;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when 10 =>
line_no(index) := 'A';
when 11 =>
line_no(index) := 'B';
when 12 =>
line_no(index) := 'C';
when 13 =>
line_no(index) := 'D';
when 14 =>
line_no(index) := 'E';
when 15 =>
line_no(index) := 'F';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
procedure Shrink_line(L : inout LINE; pos : in integer) is
subtype nstring is string(1 to pos);
variable stmp : nstring;
begin
if pos >= 1 then
read(l,stmp);
end if;
end;
end SIMIO_PACKAGE;
|
-------------------------------------------------------------------------------
-- File Name : ZZ_TOP.vhd
--
-- Project : JPEG_ENC
--
-- Module : ZZ_TOP
--
-- Content : ZigZag Top level
--
-- Description : Zig Zag scan
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity ZZ_TOP is
port
(
CLK : in std_logic;
RST : in std_logic;
-- CTRL
start_pb : in std_logic;
ready_pb : out std_logic;
zig_sm_settings : in T_SM_SETTINGS;
-- Quantizer
qua_buf_sel : in std_logic;
qua_rdaddr : in std_logic_vector(5 downto 0);
qua_data : out std_logic_vector(11 downto 0);
-- FDCT
fdct_buf_sel : out std_logic;
fdct_rd_addr : out std_logic_vector(5 downto 0);
fdct_data : in std_logic_vector(11 downto 0);
fdct_rden : out std_logic
);
end entity ZZ_TOP;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of ZZ_TOP is
signal dbuf_data : std_logic_vector(11 downto 0);
signal dbuf_q : std_logic_vector(11 downto 0);
signal dbuf_we : std_logic;
signal dbuf_waddr : std_logic_vector(6 downto 0);
signal dbuf_raddr : std_logic_vector(6 downto 0);
signal zigzag_di : std_logic_vector(11 downto 0);
signal zigzag_divalid : std_logic;
signal zigzag_dout : std_logic_vector(11 downto 0);
signal zigzag_dovalid : std_logic;
signal wr_cnt : unsigned(5 downto 0):= (others => '0');
signal rd_cnt : unsigned(5 downto 0):= (others => '0');
signal rd_en_d : std_logic_vector(5 downto 0);
signal rd_en : std_logic;
signal fdct_buf_sel_s : std_logic;
signal zz_rd_addr : std_logic_vector(5 downto 0);
signal fifo_empty : std_logic;
signal fifo_rden : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
fdct_rd_addr <= std_logic_vector(zz_rd_addr);
qua_data <= dbuf_q;
fdct_buf_sel <= fdct_buf_sel_s;
fdct_rden <= rd_en;
-------------------------------------------------------------------
-- ZigZag Core
-------------------------------------------------------------------
U_zigzag : entity work.zigzag
generic map
(
RAMADDR_W => 6,
RAMDATA_W => 12
)
port map
(
rst => RST,
clk => CLK,
di => zigzag_di,
divalid => zigzag_divalid,
rd_addr => rd_cnt,
fifo_rden => fifo_rden,
fifo_empty => fifo_empty,
dout => zigzag_dout,
dovalid => zigzag_dovalid,
zz_rd_addr => zz_rd_addr
);
zigzag_di <= fdct_data;
zigzag_divalid <= rd_en_d(1);
-------------------------------------------------------------------
-- DBUF
-------------------------------------------------------------------
U_RAMZ : entity work.RAMZ
generic map
(
RAMADDR_W => 7,
RAMDATA_W => 12
)
port map
(
d => dbuf_data,
waddr => dbuf_waddr,
raddr => dbuf_raddr,
we => dbuf_we,
clk => CLK,
q => dbuf_q
);
dbuf_data <= zigzag_dout;
dbuf_waddr <= (not qua_buf_sel) & std_logic_vector(wr_cnt);
dbuf_we <= zigzag_dovalid;
dbuf_raddr <= qua_buf_sel & qua_rdaddr;
-------------------------------------------------------------------
-- FIFO Ctrl
-------------------------------------------------------------------
p_fifo_ctrl : process(CLK, RST)
begin
if RST = '1' then
fifo_rden <= '0';
elsif CLK'event and CLK = '1' then
if fifo_empty = '0' then
fifo_rden <= '1';
else
fifo_rden <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------
-- Counter1
-------------------------------------------------------------------
p_counter1 : process(CLK, RST)
begin
if RST = '1' then
rd_en <= '0';
rd_en_d <= (others => '0');
rd_cnt <= (others => '0');
elsif CLK'event and CLK = '1' then
rd_en_d <= rd_en_d(rd_en_d'length-2 downto 0) & rd_en;
if start_pb = '1' then
rd_cnt <= (others => '0');
rd_en <= '1';
end if;
if rd_en = '1' then
if rd_cnt = 64-1 then
rd_cnt <= (others => '0');
rd_en <= '0';
else
rd_cnt <= rd_cnt + 1;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- wr_cnt
-------------------------------------------------------------------
p_wr_cnt : process(CLK, RST)
begin
if RST = '1' then
wr_cnt <= (others => '0');
ready_pb <= '0';
elsif CLK'event and CLK = '1' then
ready_pb <= '0';
if start_pb = '1' then
wr_cnt <= (others => '0');
end if;
if zigzag_dovalid = '1' then
if wr_cnt = 64-1 then
wr_cnt <= (others => '0');
else
wr_cnt <=wr_cnt + 1;
end if;
-- give ready ahead to save cycles!
if wr_cnt = 64-1-3 then
ready_pb <= '1';
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- fdct_buf_sel
-------------------------------------------------------------------
p_buf_sel : process(CLK, RST)
begin
if RST = '1' then
fdct_buf_sel_s <= '0';
elsif CLK'event and CLK = '1' then
if start_pb = '1' then
fdct_buf_sel_s <= not fdct_buf_sel_s;
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
-------------------------------------------------------------------------------
-- File Name : ZZ_TOP.vhd
--
-- Project : JPEG_ENC
--
-- Module : ZZ_TOP
--
-- Content : ZigZag Top level
--
-- Description : Zig Zag scan
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity ZZ_TOP is
port
(
CLK : in std_logic;
RST : in std_logic;
-- CTRL
start_pb : in std_logic;
ready_pb : out std_logic;
zig_sm_settings : in T_SM_SETTINGS;
-- Quantizer
qua_buf_sel : in std_logic;
qua_rdaddr : in std_logic_vector(5 downto 0);
qua_data : out std_logic_vector(11 downto 0);
-- FDCT
fdct_buf_sel : out std_logic;
fdct_rd_addr : out std_logic_vector(5 downto 0);
fdct_data : in std_logic_vector(11 downto 0);
fdct_rden : out std_logic
);
end entity ZZ_TOP;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of ZZ_TOP is
signal dbuf_data : std_logic_vector(11 downto 0);
signal dbuf_q : std_logic_vector(11 downto 0);
signal dbuf_we : std_logic;
signal dbuf_waddr : std_logic_vector(6 downto 0);
signal dbuf_raddr : std_logic_vector(6 downto 0);
signal zigzag_di : std_logic_vector(11 downto 0);
signal zigzag_divalid : std_logic;
signal zigzag_dout : std_logic_vector(11 downto 0);
signal zigzag_dovalid : std_logic;
signal wr_cnt : unsigned(5 downto 0):= (others => '0');
signal rd_cnt : unsigned(5 downto 0):= (others => '0');
signal rd_en_d : std_logic_vector(5 downto 0);
signal rd_en : std_logic;
signal fdct_buf_sel_s : std_logic;
signal zz_rd_addr : std_logic_vector(5 downto 0);
signal fifo_empty : std_logic;
signal fifo_rden : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
fdct_rd_addr <= std_logic_vector(zz_rd_addr);
qua_data <= dbuf_q;
fdct_buf_sel <= fdct_buf_sel_s;
fdct_rden <= rd_en;
-------------------------------------------------------------------
-- ZigZag Core
-------------------------------------------------------------------
U_zigzag : entity work.zigzag
generic map
(
RAMADDR_W => 6,
RAMDATA_W => 12
)
port map
(
rst => RST,
clk => CLK,
di => zigzag_di,
divalid => zigzag_divalid,
rd_addr => rd_cnt,
fifo_rden => fifo_rden,
fifo_empty => fifo_empty,
dout => zigzag_dout,
dovalid => zigzag_dovalid,
zz_rd_addr => zz_rd_addr
);
zigzag_di <= fdct_data;
zigzag_divalid <= rd_en_d(1);
-------------------------------------------------------------------
-- DBUF
-------------------------------------------------------------------
U_RAMZ : entity work.RAMZ
generic map
(
RAMADDR_W => 7,
RAMDATA_W => 12
)
port map
(
d => dbuf_data,
waddr => dbuf_waddr,
raddr => dbuf_raddr,
we => dbuf_we,
clk => CLK,
q => dbuf_q
);
dbuf_data <= zigzag_dout;
dbuf_waddr <= (not qua_buf_sel) & std_logic_vector(wr_cnt);
dbuf_we <= zigzag_dovalid;
dbuf_raddr <= qua_buf_sel & qua_rdaddr;
-------------------------------------------------------------------
-- FIFO Ctrl
-------------------------------------------------------------------
p_fifo_ctrl : process(CLK, RST)
begin
if RST = '1' then
fifo_rden <= '0';
elsif CLK'event and CLK = '1' then
if fifo_empty = '0' then
fifo_rden <= '1';
else
fifo_rden <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------
-- Counter1
-------------------------------------------------------------------
p_counter1 : process(CLK, RST)
begin
if RST = '1' then
rd_en <= '0';
rd_en_d <= (others => '0');
rd_cnt <= (others => '0');
elsif CLK'event and CLK = '1' then
rd_en_d <= rd_en_d(rd_en_d'length-2 downto 0) & rd_en;
if start_pb = '1' then
rd_cnt <= (others => '0');
rd_en <= '1';
end if;
if rd_en = '1' then
if rd_cnt = 64-1 then
rd_cnt <= (others => '0');
rd_en <= '0';
else
rd_cnt <= rd_cnt + 1;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- wr_cnt
-------------------------------------------------------------------
p_wr_cnt : process(CLK, RST)
begin
if RST = '1' then
wr_cnt <= (others => '0');
ready_pb <= '0';
elsif CLK'event and CLK = '1' then
ready_pb <= '0';
if start_pb = '1' then
wr_cnt <= (others => '0');
end if;
if zigzag_dovalid = '1' then
if wr_cnt = 64-1 then
wr_cnt <= (others => '0');
else
wr_cnt <=wr_cnt + 1;
end if;
-- give ready ahead to save cycles!
if wr_cnt = 64-1-3 then
ready_pb <= '1';
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- fdct_buf_sel
-------------------------------------------------------------------
p_buf_sel : process(CLK, RST)
begin
if RST = '1' then
fdct_buf_sel_s <= '0';
elsif CLK'event and CLK = '1' then
if start_pb = '1' then
fdct_buf_sel_s <= not fdct_buf_sel_s;
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
-------------------------------------------------------------------------------
-- File Name : ZZ_TOP.vhd
--
-- Project : JPEG_ENC
--
-- Module : ZZ_TOP
--
-- Content : ZigZag Top level
--
-- Description : Zig Zag scan
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity ZZ_TOP is
port
(
CLK : in std_logic;
RST : in std_logic;
-- CTRL
start_pb : in std_logic;
ready_pb : out std_logic;
zig_sm_settings : in T_SM_SETTINGS;
-- Quantizer
qua_buf_sel : in std_logic;
qua_rdaddr : in std_logic_vector(5 downto 0);
qua_data : out std_logic_vector(11 downto 0);
-- FDCT
fdct_buf_sel : out std_logic;
fdct_rd_addr : out std_logic_vector(5 downto 0);
fdct_data : in std_logic_vector(11 downto 0);
fdct_rden : out std_logic
);
end entity ZZ_TOP;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of ZZ_TOP is
signal dbuf_data : std_logic_vector(11 downto 0);
signal dbuf_q : std_logic_vector(11 downto 0);
signal dbuf_we : std_logic;
signal dbuf_waddr : std_logic_vector(6 downto 0);
signal dbuf_raddr : std_logic_vector(6 downto 0);
signal zigzag_di : std_logic_vector(11 downto 0);
signal zigzag_divalid : std_logic;
signal zigzag_dout : std_logic_vector(11 downto 0);
signal zigzag_dovalid : std_logic;
signal wr_cnt : unsigned(5 downto 0):= (others => '0');
signal rd_cnt : unsigned(5 downto 0):= (others => '0');
signal rd_en_d : std_logic_vector(5 downto 0);
signal rd_en : std_logic;
signal fdct_buf_sel_s : std_logic;
signal zz_rd_addr : std_logic_vector(5 downto 0);
signal fifo_empty : std_logic;
signal fifo_rden : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
fdct_rd_addr <= std_logic_vector(zz_rd_addr);
qua_data <= dbuf_q;
fdct_buf_sel <= fdct_buf_sel_s;
fdct_rden <= rd_en;
-------------------------------------------------------------------
-- ZigZag Core
-------------------------------------------------------------------
U_zigzag : entity work.zigzag
generic map
(
RAMADDR_W => 6,
RAMDATA_W => 12
)
port map
(
rst => RST,
clk => CLK,
di => zigzag_di,
divalid => zigzag_divalid,
rd_addr => rd_cnt,
fifo_rden => fifo_rden,
fifo_empty => fifo_empty,
dout => zigzag_dout,
dovalid => zigzag_dovalid,
zz_rd_addr => zz_rd_addr
);
zigzag_di <= fdct_data;
zigzag_divalid <= rd_en_d(1);
-------------------------------------------------------------------
-- DBUF
-------------------------------------------------------------------
U_RAMZ : entity work.RAMZ
generic map
(
RAMADDR_W => 7,
RAMDATA_W => 12
)
port map
(
d => dbuf_data,
waddr => dbuf_waddr,
raddr => dbuf_raddr,
we => dbuf_we,
clk => CLK,
q => dbuf_q
);
dbuf_data <= zigzag_dout;
dbuf_waddr <= (not qua_buf_sel) & std_logic_vector(wr_cnt);
dbuf_we <= zigzag_dovalid;
dbuf_raddr <= qua_buf_sel & qua_rdaddr;
-------------------------------------------------------------------
-- FIFO Ctrl
-------------------------------------------------------------------
p_fifo_ctrl : process(CLK, RST)
begin
if RST = '1' then
fifo_rden <= '0';
elsif CLK'event and CLK = '1' then
if fifo_empty = '0' then
fifo_rden <= '1';
else
fifo_rden <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------
-- Counter1
-------------------------------------------------------------------
p_counter1 : process(CLK, RST)
begin
if RST = '1' then
rd_en <= '0';
rd_en_d <= (others => '0');
rd_cnt <= (others => '0');
elsif CLK'event and CLK = '1' then
rd_en_d <= rd_en_d(rd_en_d'length-2 downto 0) & rd_en;
if start_pb = '1' then
rd_cnt <= (others => '0');
rd_en <= '1';
end if;
if rd_en = '1' then
if rd_cnt = 64-1 then
rd_cnt <= (others => '0');
rd_en <= '0';
else
rd_cnt <= rd_cnt + 1;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- wr_cnt
-------------------------------------------------------------------
p_wr_cnt : process(CLK, RST)
begin
if RST = '1' then
wr_cnt <= (others => '0');
ready_pb <= '0';
elsif CLK'event and CLK = '1' then
ready_pb <= '0';
if start_pb = '1' then
wr_cnt <= (others => '0');
end if;
if zigzag_dovalid = '1' then
if wr_cnt = 64-1 then
wr_cnt <= (others => '0');
else
wr_cnt <=wr_cnt + 1;
end if;
-- give ready ahead to save cycles!
if wr_cnt = 64-1-3 then
ready_pb <= '1';
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- fdct_buf_sel
-------------------------------------------------------------------
p_buf_sel : process(CLK, RST)
begin
if RST = '1' then
fdct_buf_sel_s <= '0';
elsif CLK'event and CLK = '1' then
if start_pb = '1' then
fdct_buf_sel_s <= not fdct_buf_sel_s;
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
-------------------------------------------------------------------------------
-- File Name : ZZ_TOP.vhd
--
-- Project : JPEG_ENC
--
-- Module : ZZ_TOP
--
-- Content : ZigZag Top level
--
-- Description : Zig Zag scan
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity ZZ_TOP is
port
(
CLK : in std_logic;
RST : in std_logic;
-- CTRL
start_pb : in std_logic;
ready_pb : out std_logic;
zig_sm_settings : in T_SM_SETTINGS;
-- Quantizer
qua_buf_sel : in std_logic;
qua_rdaddr : in std_logic_vector(5 downto 0);
qua_data : out std_logic_vector(11 downto 0);
-- FDCT
fdct_buf_sel : out std_logic;
fdct_rd_addr : out std_logic_vector(5 downto 0);
fdct_data : in std_logic_vector(11 downto 0);
fdct_rden : out std_logic
);
end entity ZZ_TOP;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of ZZ_TOP is
signal dbuf_data : std_logic_vector(11 downto 0);
signal dbuf_q : std_logic_vector(11 downto 0);
signal dbuf_we : std_logic;
signal dbuf_waddr : std_logic_vector(6 downto 0);
signal dbuf_raddr : std_logic_vector(6 downto 0);
signal zigzag_di : std_logic_vector(11 downto 0);
signal zigzag_divalid : std_logic;
signal zigzag_dout : std_logic_vector(11 downto 0);
signal zigzag_dovalid : std_logic;
signal wr_cnt : unsigned(5 downto 0):= (others => '0');
signal rd_cnt : unsigned(5 downto 0):= (others => '0');
signal rd_en_d : std_logic_vector(5 downto 0);
signal rd_en : std_logic;
signal fdct_buf_sel_s : std_logic;
signal zz_rd_addr : std_logic_vector(5 downto 0);
signal fifo_empty : std_logic;
signal fifo_rden : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
fdct_rd_addr <= std_logic_vector(zz_rd_addr);
qua_data <= dbuf_q;
fdct_buf_sel <= fdct_buf_sel_s;
fdct_rden <= rd_en;
-------------------------------------------------------------------
-- ZigZag Core
-------------------------------------------------------------------
U_zigzag : entity work.zigzag
generic map
(
RAMADDR_W => 6,
RAMDATA_W => 12
)
port map
(
rst => RST,
clk => CLK,
di => zigzag_di,
divalid => zigzag_divalid,
rd_addr => rd_cnt,
fifo_rden => fifo_rden,
fifo_empty => fifo_empty,
dout => zigzag_dout,
dovalid => zigzag_dovalid,
zz_rd_addr => zz_rd_addr
);
zigzag_di <= fdct_data;
zigzag_divalid <= rd_en_d(1);
-------------------------------------------------------------------
-- DBUF
-------------------------------------------------------------------
U_RAMZ : entity work.RAMZ
generic map
(
RAMADDR_W => 7,
RAMDATA_W => 12
)
port map
(
d => dbuf_data,
waddr => dbuf_waddr,
raddr => dbuf_raddr,
we => dbuf_we,
clk => CLK,
q => dbuf_q
);
dbuf_data <= zigzag_dout;
dbuf_waddr <= (not qua_buf_sel) & std_logic_vector(wr_cnt);
dbuf_we <= zigzag_dovalid;
dbuf_raddr <= qua_buf_sel & qua_rdaddr;
-------------------------------------------------------------------
-- FIFO Ctrl
-------------------------------------------------------------------
p_fifo_ctrl : process(CLK, RST)
begin
if RST = '1' then
fifo_rden <= '0';
elsif CLK'event and CLK = '1' then
if fifo_empty = '0' then
fifo_rden <= '1';
else
fifo_rden <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------
-- Counter1
-------------------------------------------------------------------
p_counter1 : process(CLK, RST)
begin
if RST = '1' then
rd_en <= '0';
rd_en_d <= (others => '0');
rd_cnt <= (others => '0');
elsif CLK'event and CLK = '1' then
rd_en_d <= rd_en_d(rd_en_d'length-2 downto 0) & rd_en;
if start_pb = '1' then
rd_cnt <= (others => '0');
rd_en <= '1';
end if;
if rd_en = '1' then
if rd_cnt = 64-1 then
rd_cnt <= (others => '0');
rd_en <= '0';
else
rd_cnt <= rd_cnt + 1;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- wr_cnt
-------------------------------------------------------------------
p_wr_cnt : process(CLK, RST)
begin
if RST = '1' then
wr_cnt <= (others => '0');
ready_pb <= '0';
elsif CLK'event and CLK = '1' then
ready_pb <= '0';
if start_pb = '1' then
wr_cnt <= (others => '0');
end if;
if zigzag_dovalid = '1' then
if wr_cnt = 64-1 then
wr_cnt <= (others => '0');
else
wr_cnt <=wr_cnt + 1;
end if;
-- give ready ahead to save cycles!
if wr_cnt = 64-1-3 then
ready_pb <= '1';
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- fdct_buf_sel
-------------------------------------------------------------------
p_buf_sel : process(CLK, RST)
begin
if RST = '1' then
fdct_buf_sel_s <= '0';
elsif CLK'event and CLK = '1' then
if start_pb = '1' then
fdct_buf_sel_s <= not fdct_buf_sel_s;
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
-------------------------------------------------------------------------------
-- File Name : ZZ_TOP.vhd
--
-- Project : JPEG_ENC
--
-- Module : ZZ_TOP
--
-- Content : ZigZag Top level
--
-- Description : Zig Zag scan
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity ZZ_TOP is
port
(
CLK : in std_logic;
RST : in std_logic;
-- CTRL
start_pb : in std_logic;
ready_pb : out std_logic;
zig_sm_settings : in T_SM_SETTINGS;
-- Quantizer
qua_buf_sel : in std_logic;
qua_rdaddr : in std_logic_vector(5 downto 0);
qua_data : out std_logic_vector(11 downto 0);
-- FDCT
fdct_buf_sel : out std_logic;
fdct_rd_addr : out std_logic_vector(5 downto 0);
fdct_data : in std_logic_vector(11 downto 0);
fdct_rden : out std_logic
);
end entity ZZ_TOP;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of ZZ_TOP is
signal dbuf_data : std_logic_vector(11 downto 0);
signal dbuf_q : std_logic_vector(11 downto 0);
signal dbuf_we : std_logic;
signal dbuf_waddr : std_logic_vector(6 downto 0);
signal dbuf_raddr : std_logic_vector(6 downto 0);
signal zigzag_di : std_logic_vector(11 downto 0);
signal zigzag_divalid : std_logic;
signal zigzag_dout : std_logic_vector(11 downto 0);
signal zigzag_dovalid : std_logic;
signal wr_cnt : unsigned(5 downto 0):= (others => '0');
signal rd_cnt : unsigned(5 downto 0):= (others => '0');
signal rd_en_d : std_logic_vector(5 downto 0);
signal rd_en : std_logic;
signal fdct_buf_sel_s : std_logic;
signal zz_rd_addr : std_logic_vector(5 downto 0);
signal fifo_empty : std_logic;
signal fifo_rden : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
fdct_rd_addr <= std_logic_vector(zz_rd_addr);
qua_data <= dbuf_q;
fdct_buf_sel <= fdct_buf_sel_s;
fdct_rden <= rd_en;
-------------------------------------------------------------------
-- ZigZag Core
-------------------------------------------------------------------
U_zigzag : entity work.zigzag
generic map
(
RAMADDR_W => 6,
RAMDATA_W => 12
)
port map
(
rst => RST,
clk => CLK,
di => zigzag_di,
divalid => zigzag_divalid,
rd_addr => rd_cnt,
fifo_rden => fifo_rden,
fifo_empty => fifo_empty,
dout => zigzag_dout,
dovalid => zigzag_dovalid,
zz_rd_addr => zz_rd_addr
);
zigzag_di <= fdct_data;
zigzag_divalid <= rd_en_d(1);
-------------------------------------------------------------------
-- DBUF
-------------------------------------------------------------------
U_RAMZ : entity work.RAMZ
generic map
(
RAMADDR_W => 7,
RAMDATA_W => 12
)
port map
(
d => dbuf_data,
waddr => dbuf_waddr,
raddr => dbuf_raddr,
we => dbuf_we,
clk => CLK,
q => dbuf_q
);
dbuf_data <= zigzag_dout;
dbuf_waddr <= (not qua_buf_sel) & std_logic_vector(wr_cnt);
dbuf_we <= zigzag_dovalid;
dbuf_raddr <= qua_buf_sel & qua_rdaddr;
-------------------------------------------------------------------
-- FIFO Ctrl
-------------------------------------------------------------------
p_fifo_ctrl : process(CLK, RST)
begin
if RST = '1' then
fifo_rden <= '0';
elsif CLK'event and CLK = '1' then
if fifo_empty = '0' then
fifo_rden <= '1';
else
fifo_rden <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------
-- Counter1
-------------------------------------------------------------------
p_counter1 : process(CLK, RST)
begin
if RST = '1' then
rd_en <= '0';
rd_en_d <= (others => '0');
rd_cnt <= (others => '0');
elsif CLK'event and CLK = '1' then
rd_en_d <= rd_en_d(rd_en_d'length-2 downto 0) & rd_en;
if start_pb = '1' then
rd_cnt <= (others => '0');
rd_en <= '1';
end if;
if rd_en = '1' then
if rd_cnt = 64-1 then
rd_cnt <= (others => '0');
rd_en <= '0';
else
rd_cnt <= rd_cnt + 1;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- wr_cnt
-------------------------------------------------------------------
p_wr_cnt : process(CLK, RST)
begin
if RST = '1' then
wr_cnt <= (others => '0');
ready_pb <= '0';
elsif CLK'event and CLK = '1' then
ready_pb <= '0';
if start_pb = '1' then
wr_cnt <= (others => '0');
end if;
if zigzag_dovalid = '1' then
if wr_cnt = 64-1 then
wr_cnt <= (others => '0');
else
wr_cnt <=wr_cnt + 1;
end if;
-- give ready ahead to save cycles!
if wr_cnt = 64-1-3 then
ready_pb <= '1';
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- fdct_buf_sel
-------------------------------------------------------------------
p_buf_sel : process(CLK, RST)
begin
if RST = '1' then
fdct_buf_sel_s <= '0';
elsif CLK'event and CLK = '1' then
if start_pb = '1' then
fdct_buf_sel_s <= not fdct_buf_sel_s;
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
-- $Id: tbd_serport_autobaud.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbd_serport_autobaud - syn
-- Description: Wrapper for serport_uart_autobaud and serport_uart_rxtx to
-- avoid records. It has a port interface which will not be
-- modified by xst synthesis (no records, no generic port).
--
-- Dependencies: clkdivce
-- serport_uart_autobaud
-- serport_uart_rxtx
-- serport_uart_rx
--
-- To test: serport_uart_autobaud
-- serport_uart_rxtx
--
-- Target Devices: generic
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 151 291 0 - t 9.23
-- 2007-10-27 92 9.1 J30 xc3s1000-4 151 291 0 - t 9.23
-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 153 338 0 178 s 9.45
-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 152 293 0 - s 9.40
--
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2008-01-20 112 1.0.1 rename clkgen->clkdivce
-- 2007-06-24 60 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.serportlib.all;
entity tbd_serport_autobaud is -- serial port autobaud [tb design]
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RXSD : in slbit; -- receive serial data (uart view)
CE_USEC : out slbit; -- usec pulse (here every 4 clocks)
CE_MSEC : out slbit; -- msec pulse (here every 20 clocks)
CLKDIV : out slv13; -- clock divider setting
ABACT : out slbit; -- autobaud active
ABDONE : out slbit; -- autobaud done
RXDATA : out slv8; -- receiver data out (1st rx)
RXVAL : out slbit; -- receiver data valid (1st rx)
RXERR : out slbit; -- receiver data error (1st rx)
RXACT : out slbit; -- receiver active (1st rx)
TXSD2 : out slbit; -- transmit serial data (2nd tx)
RXDATA3 : out slv8; -- receiver data out (3rd rx)
RXVAL3 : out slbit; -- receiver data valid (3rd rx)
RXERR3 : out slbit; -- receiver data error (3rd rx)
RXACT3 : out slbit -- receiver active (3rd rx)
);
end tbd_serport_autobaud;
architecture syn of tbd_serport_autobaud is
constant cdwidth : positive := 13;
signal LCE_MSEC : slbit := '0';
signal LCLKDIV : slv13 := (others=>'0');
signal LRXDATA : slv8 := (others=>'0');
signal LRXVAL : slbit := '0';
signal LTXSD2 : slbit := '0';
signal LABACT : slbit := '0';
begin
CKLDIV : clkdivce
generic map (
CDUWIDTH => 6,
USECDIV => 4,
MSECDIV => 5)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => LCE_MSEC
);
AUTOBAUD : serport_uart_autobaud
generic map (
CDWIDTH => cdwidth,
CDINIT => 15)
port map (
CLK => CLK,
CE_MSEC => LCE_MSEC,
RESET => RESET,
RXSD => RXSD,
CLKDIV => LCLKDIV,
ACT => LABACT,
DONE => ABDONE
);
UART1 : serport_uart_rxtx
generic map (
CDWIDTH => cdwidth)
port map (
CLK => CLK,
RESET => LABACT,
CLKDIV => LCLKDIV,
RXSD => RXSD,
RXDATA => LRXDATA,
RXVAL => LRXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => LTXSD2,
TXDATA => LRXDATA,
TXENA => LRXVAL,
TXBUSY => open
);
UART2 : serport_uart_rx
generic map (
CDWIDTH => cdwidth)
port map (
CLK => CLK,
RESET => LABACT,
CLKDIV => LCLKDIV,
RXSD => LTXSD2,
RXDATA => RXDATA3,
RXVAL => RXVAL3,
RXERR => RXERR3,
RXACT => RXACT3
);
CE_MSEC <= LCE_MSEC;
CLKDIV <= LCLKDIV;
ABACT <= LABACT;
RXDATA <= LRXDATA;
RXVAL <= LRXVAL;
TXSD2 <= LTXSD2;
end syn;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_cmd_pkg is
--===============================================================================================
-- t_operation
-- - Bitvis defined BFM operations
--===============================================================================================
type t_operation is (
-- UVVM common
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
-- VVC local
MASTER_TRANSMIT_AND_RECEIVE, MASTER_TRANSMIT_AND_CHECK, MASTER_TRANSMIT_ONLY, MASTER_RECEIVE_ONLY, MASTER_CHECK_ONLY,
SLAVE_TRANSMIT_AND_RECEIVE, SLAVE_TRANSMIT_AND_CHECK, SLAVE_TRANSMIT_ONLY, SLAVE_RECEIVE_ONLY, SLAVE_CHECK_ONLY);
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
constant C_VVC_CMD_DATA_MAX_LENGTH : natural := 32;
constant C_VVC_CMD_MAX_WORDS : natural := 8;
--===============================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--===============================================================================================
type t_vvc_cmd_record is record
-- VVC dedicated fields
data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
num_words : natural;
word_length : natural;
when_to_start_transfer : t_when_to_start_transfer;
action_when_transfer_is_done : t_action_when_transfer_is_done;
action_between_words : t_action_between_words;
-- Common VVC fields (Used by td_vvc_framework_common_methods_pkg procedures, and thus mandatory)
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : natural;
command_type : t_immediate_or_queued; -- QUEUED/IMMEDIATE
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
data => (others => (others => '0')),
data_exp => (others => (others => '0')),
num_words => 0,
word_length => 0,
when_to_start_transfer => START_TRANSFER_IMMEDIATE,
action_when_transfer_is_done => RELEASE_LINE_AFTER_TRANSFER,
action_between_words => HOLD_LINE_BETWEEN_WORDS,
-- Common VVC fields
operation => NO_OPERATION,
proc_call => (others => NUL),
msg => (others => NUL),
cmd_idx => 0,
command_type => NO_COMMAND_TYPE,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
alert_level => failure,
delay => 0 ns,
quietness => NON_QUIET
);
--===============================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--===============================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--===============================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - Used for storing the result of a BFM procedure called by the VVC,
-- so that the result can be transported from the VVC to for example a sequencer via
-- fetch_result() as described in VVC_Framework_common_methods_QuickRef
--
-- - t_vvc_result includes the return value of the procedure in the BFM.
-- It can also be defined as a record if multiple values shall be transported from the BFM
--===============================================================================================
subtype t_vvc_result is std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--===============================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in vvc interpreter.
--===============================================================================================
type t_last_received_cmd_idx is array (t_channel range <>, natural range <>) of integer;
--===============================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from vvc to sequencer
--===============================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM) := (others => (others => -1));
end package vvc_cmd_pkg;
--=================================================================================================
--=================================================================================================
package body vvc_cmd_pkg is
end package body vvc_cmd_pkg;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_cmd_pkg is
--===============================================================================================
-- t_operation
-- - Bitvis defined BFM operations
--===============================================================================================
type t_operation is (
-- UVVM common
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
-- VVC local
MASTER_TRANSMIT_AND_RECEIVE, MASTER_TRANSMIT_AND_CHECK, MASTER_TRANSMIT_ONLY, MASTER_RECEIVE_ONLY, MASTER_CHECK_ONLY,
SLAVE_TRANSMIT_AND_RECEIVE, SLAVE_TRANSMIT_AND_CHECK, SLAVE_TRANSMIT_ONLY, SLAVE_RECEIVE_ONLY, SLAVE_CHECK_ONLY);
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
constant C_VVC_CMD_DATA_MAX_LENGTH : natural := 32;
constant C_VVC_CMD_MAX_WORDS : natural := 8;
--===============================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--===============================================================================================
type t_vvc_cmd_record is record
-- VVC dedicated fields
data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
num_words : natural;
word_length : natural;
when_to_start_transfer : t_when_to_start_transfer;
action_when_transfer_is_done : t_action_when_transfer_is_done;
action_between_words : t_action_between_words;
-- Common VVC fields (Used by td_vvc_framework_common_methods_pkg procedures, and thus mandatory)
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : natural;
command_type : t_immediate_or_queued; -- QUEUED/IMMEDIATE
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
data => (others => (others => '0')),
data_exp => (others => (others => '0')),
num_words => 0,
word_length => 0,
when_to_start_transfer => START_TRANSFER_IMMEDIATE,
action_when_transfer_is_done => RELEASE_LINE_AFTER_TRANSFER,
action_between_words => HOLD_LINE_BETWEEN_WORDS,
-- Common VVC fields
operation => NO_OPERATION,
proc_call => (others => NUL),
msg => (others => NUL),
cmd_idx => 0,
command_type => NO_COMMAND_TYPE,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
alert_level => failure,
delay => 0 ns,
quietness => NON_QUIET
);
--===============================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--===============================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--===============================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - Used for storing the result of a BFM procedure called by the VVC,
-- so that the result can be transported from the VVC to for example a sequencer via
-- fetch_result() as described in VVC_Framework_common_methods_QuickRef
--
-- - t_vvc_result includes the return value of the procedure in the BFM.
-- It can also be defined as a record if multiple values shall be transported from the BFM
--===============================================================================================
subtype t_vvc_result is std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--===============================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in vvc interpreter.
--===============================================================================================
type t_last_received_cmd_idx is array (t_channel range <>, natural range <>) of integer;
--===============================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from vvc to sequencer
--===============================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM) := (others => (others => -1));
end package vvc_cmd_pkg;
--=================================================================================================
--=================================================================================================
package body vvc_cmd_pkg is
end package body vvc_cmd_pkg;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNRND.VHD ***
--*** ***
--*** Function: DP LOG Output Block - Rounded ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END dp_lnrnd;
ARCHITECTURE rtl OF dp_lnrnd IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when condition true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNRND.VHD ***
--*** ***
--*** Function: DP LOG Output Block - Rounded ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END dp_lnrnd;
ARCHITECTURE rtl OF dp_lnrnd IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when condition true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNRND.VHD ***
--*** ***
--*** Function: DP LOG Output Block - Rounded ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END dp_lnrnd;
ARCHITECTURE rtl OF dp_lnrnd IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when condition true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNRND.VHD ***
--*** ***
--*** Function: DP LOG Output Block - Rounded ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END dp_lnrnd;
ARCHITECTURE rtl OF dp_lnrnd IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when condition true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNRND.VHD ***
--*** ***
--*** Function: DP LOG Output Block - Rounded ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END dp_lnrnd;
ARCHITECTURE rtl OF dp_lnrnd IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when condition true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNRND.VHD ***
--*** ***
--*** Function: DP LOG Output Block - Rounded ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END dp_lnrnd;
ARCHITECTURE rtl OF dp_lnrnd IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when condition true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNRND.VHD ***
--*** ***
--*** Function: DP LOG Output Block - Rounded ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END dp_lnrnd;
ARCHITECTURE rtl OF dp_lnrnd IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when condition true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNRND.VHD ***
--*** ***
--*** Function: DP LOG Output Block - Rounded ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END dp_lnrnd;
ARCHITECTURE rtl OF dp_lnrnd IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when condition true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNRND.VHD ***
--*** ***
--*** Function: DP LOG Output Block - Rounded ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END dp_lnrnd;
ARCHITECTURE rtl OF dp_lnrnd IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when condition true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNRND.VHD ***
--*** ***
--*** Function: DP LOG Output Block - Rounded ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END dp_lnrnd;
ARCHITECTURE rtl OF dp_lnrnd IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when condition true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc504.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p03n01i00504ent IS
END c03s02b02x00p03n01i00504ent;
ARCHITECTURE c03s02b02x00p03n01i00504arch OF c03s02b02x00p03n01i00504ent IS
type DATE is
record
DAY : Integer range 1 to 31;
MONTH : Integer range 1 to 12;
YEAR : Integer range 0 to 1000;
end record --- Failure_here ; Missing semicolon
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b02x00p03n01i00504 -Missing semicolon"
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p03n01i00504arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc504.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p03n01i00504ent IS
END c03s02b02x00p03n01i00504ent;
ARCHITECTURE c03s02b02x00p03n01i00504arch OF c03s02b02x00p03n01i00504ent IS
type DATE is
record
DAY : Integer range 1 to 31;
MONTH : Integer range 1 to 12;
YEAR : Integer range 0 to 1000;
end record --- Failure_here ; Missing semicolon
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b02x00p03n01i00504 -Missing semicolon"
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p03n01i00504arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc504.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p03n01i00504ent IS
END c03s02b02x00p03n01i00504ent;
ARCHITECTURE c03s02b02x00p03n01i00504arch OF c03s02b02x00p03n01i00504ent IS
type DATE is
record
DAY : Integer range 1 to 31;
MONTH : Integer range 1 to 12;
YEAR : Integer range 0 to 1000;
end record --- Failure_here ; Missing semicolon
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b02x00p03n01i00504 -Missing semicolon"
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p03n01i00504arch;
|
--------------------------------------------------------------------------------
-- Company: University of Genoa
-- Engineer: Alessio Leoncini, Alberto Oliveri
--
-- Create Date: 16:27:59 10/06/2011
-- Design Name:
-- Module Name: testCaosAlAl.vhd
-- Project Name: Caos
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: CaosAlAl
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_textio.all;
LIBRARY std;
use STD.textio.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testCaosAlAl IS
END testCaosAlAl;
ARCHITECTURE behavior OF testCaosAlAl IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CaosAlAl
PORT(
ck : IN std_logic;
res : IN std_logic;
out0 : OUT std_logic
);
END COMPONENT;
--Inputs
signal ck : std_logic := '0';
signal res : std_logic := '0';
--Outputs
signal out0 : std_logic;
-- No clocks detected in port list. Replace ck below with
-- appropriate port name
constant ck_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CaosAlAl PORT MAP (
ck => ck,
res => res,
out0 => out0
);
-- Clock process definitions
ck_process :process
begin
ck <= '0';
wait for ck_period/2;
ck <= '1';
wait for ck_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
res <= '1';
wait for 100 ns;
res<='0';
-- write a single line
wait;
end process;
-- Write bigregister process
write_file: process (ck) is
file my_output : TEXT open WRITE_MODE is "Test.out";
variable my_output_line : LINE;
begin
if rising_edge(ck) then
write(my_output_line,out0);
writeline(my_output, my_output_line);
end if;
end process write_file;
END;
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_with_checkers_top is
port ( Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
RTS_FF: in std_logic;
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
-- Arbiter outputs
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR
RTS_FF_in: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
state_in: out std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
next_state_out: out std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
err_East_Req_E,
err_West_Req_W,
err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
err_North_Req_E,
err_East_Req_W,
err_West_Req_S,
err_South_Req_L,
err_IDLE_Req_E,
err_Local_Req_E,
err_North_Req_W,
err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
err_IDLE_Req_W,
err_Local_Req_W,
err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
err_South_Req_E,
err_IDLE_Req_S,
err_Local_Req_S,
err_North_Req_L,
err_East_Req_N,
err_West_Req_E,
err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel,
err_state_local_xbar_sel : out std_logic
);
end Arbiter_with_checkers_top;
architecture behavior of Arbiter_with_checkers_top is
component Arbiter_pseudo is
port (
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
RTS_FF: in std_logic;
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector (4 downto 0); -- select lines for XBAR
RTS_FF_in: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
state_in: out std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
next_state_out: out std_logic_vector (5 downto 0) -- 6 states for Arbiter's FSM
);
end component;
component Arbiter_checkers is
port (
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic;
DCTS: in std_logic;
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L: in std_logic;
Xbar_sel : in std_logic_vector(4 downto 0);
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
next_state_out: in std_logic_vector (5 downto 0);
RTS_FF: in std_logic;
RTS_FF_in: in std_logic;
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
err_East_Req_E,
err_West_Req_W,
err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
err_North_Req_E,
err_East_Req_W,
err_West_Req_S,
err_South_Req_L,
err_IDLE_Req_E,
err_Local_Req_E,
err_North_Req_W,
err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
err_IDLE_Req_W,
err_Local_Req_W,
err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
err_South_Req_E,
err_IDLE_Req_S,
err_Local_Req_S,
err_North_Req_L,
err_East_Req_N,
err_West_Req_E,
err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel,
err_state_local_xbar_sel : out std_logic
);
end component;
signal Grant_N_sig, Grant_E_sig, Grant_W_sig, Grant_S_sig, Grant_L_sig: std_logic;
signal Xbar_sel_sig: std_logic_vector(4 downto 0);
signal state_in_sig: std_logic_vector (5 downto 0);
signal next_state_out_sig: std_logic_vector (5 downto 0);
signal RTS_FF_in_sig: std_logic;
begin
Grant_N <= Grant_N_sig;
Grant_E <= Grant_E_sig;
Grant_W <= Grant_W_sig;
Grant_S <= Grant_S_sig;
Grant_L <= Grant_L_sig;
Xbar_sel <= Xbar_sel_sig;
state_in <= state_in_sig;
RTS_FF_in <= RTS_FF_in_sig;
next_state_out <= next_state_out_sig;
-- Arbiter instantiation
ARBITER: Arbiter_pseudo port map (
Req_N=>Req_N,
Req_E=>Req_E,
Req_W=>Req_W,
Req_S=>Req_S,
Req_L=>Req_L,
DCTS => DCTS,
RTS_FF => RTS_FF,
state=>state,
Grant_N => Grant_N_sig,
Grant_E => Grant_E_sig,
Grant_W => Grant_W_sig,
Grant_S => Grant_S_sig,
Grant_L => Grant_L_sig,
Xbar_sel => Xbar_sel_sig,
RTS_FF_in => RTS_FF_in,
state_in => state_in_sig,
next_state_out => next_state_out_sig
);
-- Checkers instantiation
CHECKERS: Arbiter_checkers port map (
Req_N => Req_N,
Req_E => Req_E,
Req_W => Req_W,
Req_S => Req_S,
Req_L => Req_L,
DCTS => DCTS,
RTS_FF => RTS_FF,
state => state,
Grant_N => Grant_N_sig,
Grant_E => Grant_E_sig,
Grant_W => Grant_W_sig,
Grant_S => Grant_S_sig,
Grant_L => Grant_L_sig,
Xbar_sel=>Xbar_sel_sig,
state_in => state_in_sig,
next_state_out => next_state_out_sig,
RTS_FF_in => RTS_FF_in_sig,
err_state_IDLE_xbar => err_state_IDLE_xbar,
err_state_not_IDLE_xbar => err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in => err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in => err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in => err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state => err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state => err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants => err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants => err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants => err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE => err_Requests_next_state_IDLE,
err_IDLE_Req_L => err_IDLE_Req_L,
err_Local_Req_L => err_Local_Req_L,
err_North_Req_N => err_North_Req_N,
err_East_Req_E => err_East_Req_E,
err_West_Req_W => err_West_Req_W,
err_South_Req_S => err_South_Req_S,
err_IDLE_Req_N => err_IDLE_Req_N,
err_Local_Req_N => err_Local_Req_N,
err_North_Req_E => err_North_Req_E,
err_East_Req_W => err_East_Req_W,
err_West_Req_S => err_West_Req_S,
err_South_Req_L => err_South_Req_L,
err_IDLE_Req_E => err_IDLE_Req_E,
err_Local_Req_E => err_Local_Req_E,
err_North_Req_W => err_North_Req_W,
err_East_Req_S => err_East_Req_S,
err_West_Req_L => err_West_Req_L,
err_South_Req_N => err_South_Req_N,
err_IDLE_Req_W => err_IDLE_Req_W,
err_Local_Req_W => err_Local_Req_W,
err_North_Req_S => err_North_Req_S,
err_East_Req_L => err_East_Req_L,
err_West_Req_N => err_West_Req_N,
err_South_Req_E => err_South_Req_E,
err_IDLE_Req_S => err_IDLE_Req_S,
err_Local_Req_S => err_Local_Req_S,
err_North_Req_L => err_North_Req_L,
err_East_Req_N => err_East_Req_N,
err_West_Req_E => err_West_Req_E,
err_South_Req_W => err_South_Req_W,
err_next_state_onehot => err_next_state_onehot,
err_state_in_onehot => err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L => err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N => err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E => err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W => err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S => err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel => err_state_north_xbar_sel,
err_state_east_xbar_sel => err_state_east_xbar_sel,
err_state_west_xbar_sel => err_state_west_xbar_sel,
err_state_south_xbar_sel => err_state_south_xbar_sel,
err_state_local_xbar_sel => err_state_local_xbar_sel
);
end behavior; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
library work;
use work.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitIncIO-1;
constant ioBit : integer := maxAddrBit+1;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
component dualport_ram is
port (clk : in std_logic;
memAWriteEnable : in std_logic;
memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
memAWrite : in std_logic_vector(wordSize-1 downto 0);
memARead : out std_logic_vector(wordSize-1 downto 0);
memBWriteEnable : in std_logic;
memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
memBWrite : in std_logic_vector(wordSize-1 downto 0);
memBRead : out std_logic_vector(wordSize-1 downto 0));
end component;
component dram is
port (clk : in std_logic;
areset : in std_logic;
mem_writeEnable : in std_logic;
mem_readEnable : in std_logic;
mem_addr : in std_logic_vector(maxAddrBit downto 0);
mem_write : in std_logic_vector(wordSize-1 downto 0);
mem_read : out std_logic_vector(wordSize-1 downto 0);
mem_busy : out std_logic;
mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));
end component;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core is
port ( clk : in std_logic;
areset : in std_logic;
enable : in std_logic;
mem_req : out std_logic;
mem_we : out std_logic;
mem_ack : in std_logic;
mem_read : in std_logic_vector(wordSize-1 downto 0);
mem_write : out std_logic_vector(wordSize-1 downto 0);
out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);
interrupt : in std_logic;
break : out std_logic;
zpu_status : out std_logic_vector(63 downto 0));
end component;
component timer is
port(
clk : in std_logic;
areset : in std_logic;
sample : in std_logic;
reset : in std_logic;
counter : out std_logic_vector(63 downto 0));
end component;
component zpuio is
port ( areset : in std_logic;
cpu_clk : in std_logic;
clk_status : in std_logic_vector(2 downto 0);
cpu_din : in std_logic_vector(15 downto 0);
cpu_a : in std_logic_vector(20 downto 0);
cpu_we : in std_logic_vector(1 downto 0);
cpu_re : in std_logic;
cpu_dout : inout std_logic_vector(15 downto 0));
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_PushInt : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_Compare : std_logic_vector(3 downto 0) := "1110";
constant OpCode_PopInt : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(36, 6);
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(37, 6);
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(38, 6);
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(39, 6);
constant OpCode_Swap : std_logic_vector(5 downto 0) := conv_std_logic_vector(40, 6);
constant OpCode_Mult : std_logic_vector(5 downto 0) := conv_std_logic_vector(41, 6);
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(42, 6);
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := conv_std_logic_vector(43, 6);
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(44, 6);
constant OpCode_Call : std_logic_vector(5 downto 0) := conv_std_logic_vector(45, 6);
constant OpCode_Eq : std_logic_vector(5 downto 0) := conv_std_logic_vector(46, 6);
constant OpCode_Neq : std_logic_vector(5 downto 0) := conv_std_logic_vector(47, 6);
constant OpCode_Sub : std_logic_vector(5 downto 0) := conv_std_logic_vector(49, 6);
constant OpCode_Loadb : std_logic_vector(5 downto 0) := conv_std_logic_vector(51, 6);
constant OpCode_Storeb : std_logic_vector(5 downto 0) := conv_std_logic_vector(52, 6);
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(55, 6);
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(56, 6);
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(57, 6);
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := conv_std_logic_vector(61, 6);
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := conv_std_logic_vector(62, 6);
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(63, 6);
constant OpCode_Size : integer := 8;
end zpupkg;
|
entity forty_two is
port (
bv_out : out bit_vector );
end forty_two;
architecture only of forty_two is
begin -- only
process
begin -- process
bv_out <= "0110";
wait;
end process;
end only;
entity test_bench is
end test_bench;
architecture only of test_bench is
component forty_two_component
port (
c_bv_out : out bit_vector );
end component;
for ft0 : forty_two_component
use entity work.forty_two(only)
port map (
bv_out => c_bv_out );
signal bv_signal : bit_vector( 3 downto 0 );
begin -- only
ft0 : component forty_two_component
port map (
c_bv_out => bv_signal );
test: process
begin -- process test
wait for 1 ms;
assert bv_signal = "0110" report "TEST FAILED" severity ERROR;
assert not(bv_signal = "0110") report "TEST PASSED" severity NOTE;
wait;
end process test;
end only;
|
entity forty_two is
port (
bv_out : out bit_vector );
end forty_two;
architecture only of forty_two is
begin -- only
process
begin -- process
bv_out <= "0110";
wait;
end process;
end only;
entity test_bench is
end test_bench;
architecture only of test_bench is
component forty_two_component
port (
c_bv_out : out bit_vector );
end component;
for ft0 : forty_two_component
use entity work.forty_two(only)
port map (
bv_out => c_bv_out );
signal bv_signal : bit_vector( 3 downto 0 );
begin -- only
ft0 : component forty_two_component
port map (
c_bv_out => bv_signal );
test: process
begin -- process test
wait for 1 ms;
assert bv_signal = "0110" report "TEST FAILED" severity ERROR;
assert not(bv_signal = "0110") report "TEST PASSED" severity NOTE;
wait;
end process test;
end only;
|
entity forty_two is
port (
bv_out : out bit_vector );
end forty_two;
architecture only of forty_two is
begin -- only
process
begin -- process
bv_out <= "0110";
wait;
end process;
end only;
entity test_bench is
end test_bench;
architecture only of test_bench is
component forty_two_component
port (
c_bv_out : out bit_vector );
end component;
for ft0 : forty_two_component
use entity work.forty_two(only)
port map (
bv_out => c_bv_out );
signal bv_signal : bit_vector( 3 downto 0 );
begin -- only
ft0 : component forty_two_component
port map (
c_bv_out => bv_signal );
test: process
begin -- process test
wait for 1 ms;
assert bv_signal = "0110" report "TEST FAILED" severity ERROR;
assert not(bv_signal = "0110") report "TEST PASSED" severity NOTE;
wait;
end process test;
end only;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex7_nov is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex7_nov;
architecture behaviour of ex7_nov is
constant s1: std_logic_vector(3 downto 0) := "1100";
constant s2: std_logic_vector(3 downto 0) := "1101";
constant s3: std_logic_vector(3 downto 0) := "0111";
constant s4: std_logic_vector(3 downto 0) := "1010";
constant s5: std_logic_vector(3 downto 0) := "1000";
constant s6: std_logic_vector(3 downto 0) := "1011";
constant s7: std_logic_vector(3 downto 0) := "1001";
constant s8: std_logic_vector(3 downto 0) := "1111";
constant s9: std_logic_vector(3 downto 0) := "1110";
constant s0: std_logic_vector(3 downto 0) := "0000";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s7; output <= "11";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "00";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s2; output <= "--";
elsif std_match(input, "10") then next_state <= s5; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "11";
elsif std_match(input, "10") then next_state <= s8; output <= "--";
elsif std_match(input, "11") then next_state <= s5; output <= "--";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "00";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s1; output <= "11";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s7; output <= "00";
elsif std_match(input, "01") then next_state <= s5; output <= "--";
elsif std_match(input, "10") then next_state <= s2; output <= "11";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s9; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s2; output <= "00";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s4; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "00";
elsif std_match(input, "11") then next_state <= s5; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s3; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s4; output <= "11";
end if;
when s9 =>
if std_match(input, "00") then next_state <= s6; output <= "11";
elsif std_match(input, "01") then next_state <= s3; output <= "00";
elsif std_match(input, "10") then next_state <= s0; output <= "00";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "----"; output <= "--";
end case;
end process;
end behaviour;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_e_e
--
-- Generated
-- by: wig
-- on: Wed Nov 30 06:48:17 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_e_e-e.vhd,v 1.3 2005/11/30 14:04:03 wig Exp $
-- $Date: 2005/11/30 14:04:03 $
-- $Log: inst_e_e-e.vhd,v $
-- Revision 1.3 2005/11/30 14:04:03 wig
-- Updated testcase references
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.42 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_e_e
--
entity inst_e_e is
-- Generics:
-- No Generated Generics for Entity inst_e_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_e_e
end inst_e_e;
--
-- End of Generated Entity inst_e_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nano_cpu_pkg.all;
entity nano_cpu is
port (
clock : in std_logic;
reset : in std_logic;
-- instruction/data ram
ram_addr : out std_logic_vector(9 downto 0);
ram_en : out std_logic;
ram_we : out std_logic;
ram_wdata : out std_logic_vector(15 downto 0);
ram_rdata : in std_logic_vector(15 downto 0);
-- i/o interface
io_addr : out unsigned(7 downto 0);
io_write : out std_logic := '0';
io_read : out std_logic := '0';
io_wdata : out std_logic_vector(15 downto 0);
io_rdata : in std_logic_vector(15 downto 0);
stall : in std_logic );
end entity;
architecture gideon of nano_cpu is
signal i_addr : unsigned(9 downto 0);
signal inst : std_logic_vector(15 downto 11) := (others => '0');
signal accu : unsigned(15 downto 0);
signal branch_taken : boolean;
signal n, z : boolean;
signal stack_top : std_logic_vector(i_addr'range);
signal push : std_logic;
signal pop : std_logic;
signal update_accu : std_logic;
signal update_flag : std_logic;
signal long_inst : std_logic;
type t_state is (fetch_inst, decode_inst, data_state, external_data);
signal state : t_state;
begin
with ram_rdata(c_br_eq'range) select branch_taken <=
z when c_br_eq,
not z when c_br_neq,
n when c_br_mi,
not n when c_br_pl,
true when c_br_always,
true when c_br_call,
false when others;
with state select ram_addr <=
std_logic_vector(i_addr) when fetch_inst,
ram_rdata(ram_addr'range) when others;
io_wdata <= std_logic_vector(accu);
ram_wdata <= std_logic_vector(accu);
ram_en <= '0' when (state = decode_inst) and (ram_rdata(c_store'range) = c_store) else not stall;
push <= '1' when (state = decode_inst) and (ram_rdata(c_br_call'range) = c_br_call) and (ram_rdata(c_branch'range) = c_branch) else '0';
pop <= '1' when (state = decode_inst) and (ram_rdata(c_return'range) = c_return) else '0';
with ram_rdata(inst'range) select long_inst <=
'1' when c_store,
'1' when c_load_ind,
'1' when c_store_ind,
'0' when others;
process(clock)
begin
if rising_edge(clock) then
if stall='0' then
io_addr <= unsigned(ram_rdata(io_addr'range));
update_accu <= '0';
update_flag <= '0';
end if;
io_write <= '0';
io_read <= '0';
ram_we <= '0';
case state is
when fetch_inst =>
i_addr <= i_addr + 1;
state <= decode_inst;
when decode_inst =>
state <= fetch_inst;
inst <= ram_rdata(inst'range);
update_accu <= ram_rdata(11);
update_flag <= not ram_rdata(15);
-- special instructions
if ram_rdata(c_in'range) = c_in then
io_read <= '1';
state <= external_data;
elsif ram_rdata(c_branch'range) = c_branch then
update_accu <= '0';
update_flag <= '0';
if branch_taken then
i_addr <= unsigned(ram_rdata(i_addr'range));
end if;
elsif ram_rdata(c_return'range) = c_return then
i_addr <= unsigned(stack_top);
update_accu <= '0';
update_flag <= '0';
elsif ram_rdata(c_out'range) = c_out then
io_write <= '1';
if ram_rdata(7) = '1' then -- optimization: for ulpi access only
state <= external_data;
end if;
-- not so special instructions: alu instructions!
else
if long_inst='1' then
state <= data_state;
end if;
if ram_rdata(c_store'range) = c_store then
ram_we <= '1';
end if;
if ram_rdata(c_store_ind'range) = c_store_ind then
ram_we <= '1';
end if;
end if;
when external_data =>
if stall = '0' then
update_accu <= '0';
update_flag <= '0';
state <= fetch_inst;
end if;
when data_state =>
if inst = c_load_ind then
update_accu <= '1';
update_flag <= '1';
end if;
state <= fetch_inst;
when others =>
state <= fetch_inst;
end case;
if reset='1' then
state <= fetch_inst;
i_addr <= (others => '0');
end if;
end if;
end process;
i_alu: entity work.nano_alu
port map (
clock => clock,
reset => reset,
value_in => unsigned(ram_rdata),
ext_in => unsigned(io_rdata),
alu_oper => inst(14 downto 12),
update_accu => update_accu,
update_flag => update_flag,
accu => accu,
z => z,
n => n );
i_stack : entity work.distributed_stack
generic map (
width => i_addr'length,
simultaneous_pushpop => false )
port map (
clock => clock,
reset => reset,
pop => pop,
push => push,
flush => '0',
data_in => std_logic_vector(i_addr),
data_out => stack_top,
full => open,
data_valid => open );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nano_cpu_pkg.all;
entity nano_cpu is
port (
clock : in std_logic;
reset : in std_logic;
-- instruction/data ram
ram_addr : out std_logic_vector(9 downto 0);
ram_en : out std_logic;
ram_we : out std_logic;
ram_wdata : out std_logic_vector(15 downto 0);
ram_rdata : in std_logic_vector(15 downto 0);
-- i/o interface
io_addr : out unsigned(7 downto 0);
io_write : out std_logic := '0';
io_read : out std_logic := '0';
io_wdata : out std_logic_vector(15 downto 0);
io_rdata : in std_logic_vector(15 downto 0);
stall : in std_logic );
end entity;
architecture gideon of nano_cpu is
signal i_addr : unsigned(9 downto 0);
signal inst : std_logic_vector(15 downto 11) := (others => '0');
signal accu : unsigned(15 downto 0);
signal branch_taken : boolean;
signal n, z : boolean;
signal stack_top : std_logic_vector(i_addr'range);
signal push : std_logic;
signal pop : std_logic;
signal update_accu : std_logic;
signal update_flag : std_logic;
signal long_inst : std_logic;
type t_state is (fetch_inst, decode_inst, data_state, external_data);
signal state : t_state;
begin
with ram_rdata(c_br_eq'range) select branch_taken <=
z when c_br_eq,
not z when c_br_neq,
n when c_br_mi,
not n when c_br_pl,
true when c_br_always,
true when c_br_call,
false when others;
with state select ram_addr <=
std_logic_vector(i_addr) when fetch_inst,
ram_rdata(ram_addr'range) when others;
io_wdata <= std_logic_vector(accu);
ram_wdata <= std_logic_vector(accu);
ram_en <= '0' when (state = decode_inst) and (ram_rdata(c_store'range) = c_store) else not stall;
push <= '1' when (state = decode_inst) and (ram_rdata(c_br_call'range) = c_br_call) and (ram_rdata(c_branch'range) = c_branch) else '0';
pop <= '1' when (state = decode_inst) and (ram_rdata(c_return'range) = c_return) else '0';
with ram_rdata(inst'range) select long_inst <=
'1' when c_store,
'1' when c_load_ind,
'1' when c_store_ind,
'0' when others;
process(clock)
begin
if rising_edge(clock) then
if stall='0' then
io_addr <= unsigned(ram_rdata(io_addr'range));
update_accu <= '0';
update_flag <= '0';
end if;
io_write <= '0';
io_read <= '0';
ram_we <= '0';
case state is
when fetch_inst =>
i_addr <= i_addr + 1;
state <= decode_inst;
when decode_inst =>
state <= fetch_inst;
inst <= ram_rdata(inst'range);
update_accu <= ram_rdata(11);
update_flag <= not ram_rdata(15);
-- special instructions
if ram_rdata(c_in'range) = c_in then
io_read <= '1';
state <= external_data;
elsif ram_rdata(c_branch'range) = c_branch then
update_accu <= '0';
update_flag <= '0';
if branch_taken then
i_addr <= unsigned(ram_rdata(i_addr'range));
end if;
elsif ram_rdata(c_return'range) = c_return then
i_addr <= unsigned(stack_top);
update_accu <= '0';
update_flag <= '0';
elsif ram_rdata(c_out'range) = c_out then
io_write <= '1';
if ram_rdata(7) = '1' then -- optimization: for ulpi access only
state <= external_data;
end if;
-- not so special instructions: alu instructions!
else
if long_inst='1' then
state <= data_state;
end if;
if ram_rdata(c_store'range) = c_store then
ram_we <= '1';
end if;
if ram_rdata(c_store_ind'range) = c_store_ind then
ram_we <= '1';
end if;
end if;
when external_data =>
if stall = '0' then
update_accu <= '0';
update_flag <= '0';
state <= fetch_inst;
end if;
when data_state =>
if inst = c_load_ind then
update_accu <= '1';
update_flag <= '1';
end if;
state <= fetch_inst;
when others =>
state <= fetch_inst;
end case;
if reset='1' then
state <= fetch_inst;
i_addr <= (others => '0');
end if;
end if;
end process;
i_alu: entity work.nano_alu
port map (
clock => clock,
reset => reset,
value_in => unsigned(ram_rdata),
ext_in => unsigned(io_rdata),
alu_oper => inst(14 downto 12),
update_accu => update_accu,
update_flag => update_flag,
accu => accu,
z => z,
n => n );
i_stack : entity work.distributed_stack
generic map (
width => i_addr'length,
simultaneous_pushpop => false )
port map (
clock => clock,
reset => reset,
pop => pop,
push => push,
flush => '0',
data_in => std_logic_vector(i_addr),
data_out => stack_top,
full => open,
data_valid => open );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nano_cpu_pkg.all;
entity nano_cpu is
port (
clock : in std_logic;
reset : in std_logic;
-- instruction/data ram
ram_addr : out std_logic_vector(9 downto 0);
ram_en : out std_logic;
ram_we : out std_logic;
ram_wdata : out std_logic_vector(15 downto 0);
ram_rdata : in std_logic_vector(15 downto 0);
-- i/o interface
io_addr : out unsigned(7 downto 0);
io_write : out std_logic := '0';
io_read : out std_logic := '0';
io_wdata : out std_logic_vector(15 downto 0);
io_rdata : in std_logic_vector(15 downto 0);
stall : in std_logic );
end entity;
architecture gideon of nano_cpu is
signal i_addr : unsigned(9 downto 0);
signal inst : std_logic_vector(15 downto 11) := (others => '0');
signal accu : unsigned(15 downto 0);
signal branch_taken : boolean;
signal n, z : boolean;
signal stack_top : std_logic_vector(i_addr'range);
signal push : std_logic;
signal pop : std_logic;
signal update_accu : std_logic;
signal update_flag : std_logic;
signal long_inst : std_logic;
type t_state is (fetch_inst, decode_inst, data_state, external_data);
signal state : t_state;
begin
with ram_rdata(c_br_eq'range) select branch_taken <=
z when c_br_eq,
not z when c_br_neq,
n when c_br_mi,
not n when c_br_pl,
true when c_br_always,
true when c_br_call,
false when others;
with state select ram_addr <=
std_logic_vector(i_addr) when fetch_inst,
ram_rdata(ram_addr'range) when others;
io_wdata <= std_logic_vector(accu);
ram_wdata <= std_logic_vector(accu);
ram_en <= '0' when (state = decode_inst) and (ram_rdata(c_store'range) = c_store) else not stall;
push <= '1' when (state = decode_inst) and (ram_rdata(c_br_call'range) = c_br_call) and (ram_rdata(c_branch'range) = c_branch) else '0';
pop <= '1' when (state = decode_inst) and (ram_rdata(c_return'range) = c_return) else '0';
with ram_rdata(inst'range) select long_inst <=
'1' when c_store,
'1' when c_load_ind,
'1' when c_store_ind,
'0' when others;
process(clock)
begin
if rising_edge(clock) then
if stall='0' then
io_addr <= unsigned(ram_rdata(io_addr'range));
update_accu <= '0';
update_flag <= '0';
end if;
io_write <= '0';
io_read <= '0';
ram_we <= '0';
case state is
when fetch_inst =>
i_addr <= i_addr + 1;
state <= decode_inst;
when decode_inst =>
state <= fetch_inst;
inst <= ram_rdata(inst'range);
update_accu <= ram_rdata(11);
update_flag <= not ram_rdata(15);
-- special instructions
if ram_rdata(c_in'range) = c_in then
io_read <= '1';
state <= external_data;
elsif ram_rdata(c_branch'range) = c_branch then
update_accu <= '0';
update_flag <= '0';
if branch_taken then
i_addr <= unsigned(ram_rdata(i_addr'range));
end if;
elsif ram_rdata(c_return'range) = c_return then
i_addr <= unsigned(stack_top);
update_accu <= '0';
update_flag <= '0';
elsif ram_rdata(c_out'range) = c_out then
io_write <= '1';
if ram_rdata(7) = '1' then -- optimization: for ulpi access only
state <= external_data;
end if;
-- not so special instructions: alu instructions!
else
if long_inst='1' then
state <= data_state;
end if;
if ram_rdata(c_store'range) = c_store then
ram_we <= '1';
end if;
if ram_rdata(c_store_ind'range) = c_store_ind then
ram_we <= '1';
end if;
end if;
when external_data =>
if stall = '0' then
update_accu <= '0';
update_flag <= '0';
state <= fetch_inst;
end if;
when data_state =>
if inst = c_load_ind then
update_accu <= '1';
update_flag <= '1';
end if;
state <= fetch_inst;
when others =>
state <= fetch_inst;
end case;
if reset='1' then
state <= fetch_inst;
i_addr <= (others => '0');
end if;
end if;
end process;
i_alu: entity work.nano_alu
port map (
clock => clock,
reset => reset,
value_in => unsigned(ram_rdata),
ext_in => unsigned(io_rdata),
alu_oper => inst(14 downto 12),
update_accu => update_accu,
update_flag => update_flag,
accu => accu,
z => z,
n => n );
i_stack : entity work.distributed_stack
generic map (
width => i_addr'length,
simultaneous_pushpop => false )
port map (
clock => clock,
reset => reset,
pop => pop,
push => push,
flush => '0',
data_in => std_logic_vector(i_addr),
data_out => stack_top,
full => open,
data_valid => open );
end architecture;
|
---------------------------------------------------------------------
--
-- Registers:
-- REG00 (i, t0)
-- REG01 (t1, t5)
-- REG02 (e, t4)
-- REG03 (a, t3)
-- REG04 (b, t2)
-- REG05 (h)
-- REG06 (g)
-- REG07 (f)
-- REG08 (d)
-- REG09 (c)
-- Functional Units:
-- MULT00 (op1, op3, op5)
-- MULT01 (op2, op4)
-- SUB00 (op6, op7)
-- Multiplexers:
-- MX_MULT00 (op1, op3, op5)
-- MX_MULT01 (op2, op4)
-- MX_SUB00 (op6, op7)
-- MX_REG00 (i, t0)
-- MX_REG01 (t1, t5)
-- MX_REG02 (e, t4)
-- MX_REG03 (a, t3)
-- MX_REG04 (b, t2)
-- Expressions:
-- i = f(a, b, c, d, e, f, g, h) = (a * b * c * d) - h - (g * e * f)
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity input_dp is
port
(
a, b, c, d, e, f, g, h : IN std_logic_vector(3 downto 0);
i : OUT std_logic_vector(3 downto 0);
ctrl : IN std_logic_vector(0 to 18);
clear, clock : IN std_logic
);
end input_dp;
architecture rtl1 of input_dp is
component c_multiplexer
generic
(
width : integer := 4;
no_of_inputs : integer := 2;
select_size : integer := 1
);
port
(
input : in std_logic_vector(((width * no_of_inputs) - 1) downto 0);
mux_select : in std_logic_vector ((select_size - 1) downto 0);
output : out std_logic_vector ((width - 1) downto 0)
);
end component;
for all : c_multiplexer use entity work.c_multiplexer(behavior);
component c_register
generic
(
width : integer := 4
);
port
(
input : in std_logic_vector((width - 1) downto 0);
WR : in std_logic;
clear : in std_logic;
clock : in std_logic;
output : out std_logic_vector((width - 1) downto 0)
);
end component;
for all : c_register use entity work.c_register(behavior);
component c_multiplier
generic
(
width : integer := 4
);
port
(
input1 : std_logic_vector((width - 1) downto 0);
input2 : std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end component;
for all : c_multiplier use entity work.c_multiplier(behavior);
component c_subtractor
generic
(
width : integer := 4
);
port
(
input1, input2 : in std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end component;
for all : c_subtractor use entity work.c_subtractor(behavior);
-- Outputs of registers
signal REG00_out, REG01_out, REG02_out, REG03_out, REG04_out, REG05_out, REG06_out, REG07_out, REG08_out, REG09_out : std_logic_vector(3 downto 0);
-- Outputs of FUs
signal MULT00_out, MULT01_out, SUB00_out : std_logic_vector(3 downto 0);
-- Outputs of Interconnect Units
signal MX_MULT00_out, MX_MULT01_out, MX_SUB00_out : std_logic_vector(7 downto 0);
signal MX_REG00_out, MX_REG01_out, MX_REG02_out, MX_REG03_out, MX_REG04_out : std_logic_vector(3 downto 0);
begin
-- Registers
-- REG00 (i, t0)
REG00 : c_register
generic map(4)
port map
(
input(3 downto 0) => MX_REG00_out(3 downto 0), -- Items: i, t0
wr => ctrl(0),
clear => clear,
clock => clock,
output => REG00_out
);
-- REG01 (t1, t5)
REG01 : c_register
generic map(4)
port map
(
input(3 downto 0) => MX_REG01_out(3 downto 0), -- Items: t1, t5
wr => ctrl(1),
clear => clear,
clock => clock,
output => REG01_out
);
-- REG02 (e, t4)
REG02 : c_register
generic map(4)
port map
(
input(3 downto 0) => MX_REG02_out(3 downto 0), -- Items: e, t4
wr => ctrl(2),
clear => clear,
clock => clock,
output => REG02_out
);
-- REG03 (a, t3)
REG03 : c_register
generic map(4)
port map
(
input(3 downto 0) => MX_REG03_out(3 downto 0), -- Items: a, t3
wr => ctrl(3),
clear => clear,
clock => clock,
output => REG03_out
);
-- REG04 (b, t2)
REG04 : c_register
generic map(4)
port map
(
input(3 downto 0) => MX_REG04_out(3 downto 0), -- Items: b, t2
wr => ctrl(4),
clear => clear,
clock => clock,
output => REG04_out
);
-- REG05 (h)
REG05 : c_register
generic map(4)
port map
(
input(3 downto 0) => h(3 downto 0),
wr => ctrl(5),
clear => clear,
clock => clock,
output => REG05_out
);
-- REG06 (g)
REG06 : c_register
generic map(4)
port map
(
input(3 downto 0) => g(3 downto 0),
wr => ctrl(6),
clear => clear,
clock => clock,
output => REG06_out
);
-- REG07 (f)
REG07 : c_register
generic map(4)
port map
(
input(3 downto 0) => f(3 downto 0),
wr => ctrl(7),
clear => clear,
clock => clock,
output => REG07_out
);
-- REG08 (d)
REG08 : c_register
generic map(4)
port map
(
input(3 downto 0) => d(3 downto 0),
wr => ctrl(8),
clear => clear,
clock => clock,
output => REG08_out
);
-- REG09 (c)
REG09 : c_register
generic map(4)
port map
(
input(3 downto 0) => c(3 downto 0),
wr => ctrl(9),
clear => clear,
clock => clock,
output => REG09_out
);
-- Functional Units
-- MULT00 MULT(op1, op3, op5)
MULT00 : c_multiplier
generic map(4)
port map
(
input1(3 downto 0) => MX_MULT00_out(3 downto 0), -- a, e, g
input2(3 downto 0) => MX_MULT00_out(7 downto 4), -- b, f, t2
output(3 downto 0) => MULT00_out(3 downto 0)
);
-- MULT01 MULT(op2, op4)
MULT01 : c_multiplier
generic map(4)
port map
(
input1(3 downto 0) => MX_MULT01_out(3 downto 0), -- c, t0
input2(3 downto 0) => MX_MULT01_out(7 downto 4), -- d, t1
output(3 downto 0) => MULT01_out(3 downto 0)
);
-- SUB00 SUB(op6, op7)
SUB00 : c_subtractor
generic map(4)
port map
(
input1(3 downto 0) => MX_SUB00_out(3 downto 0), -- t3, t5
input2(3 downto 0) => MX_SUB00_out(7 downto 4), -- h, t4
output(3 downto 0) => SUB00_out(3 downto 0)
);
-- Multiplexers
-- MX_MULT00: op1, op3, op5
MX_MULT00 : c_multiplexer
generic map(8, 3, 2)
port map
(
-- Operation op1: MULT(a, b)
input(3 downto 0) => REG03_out(3 downto 0), -- a
input(7 downto 4) => REG04_out(3 downto 0), -- b
-- Operation op3: MULT(e, f)
input(11 downto 8) => REG02_out(3 downto 0), -- e
input(15 downto 12) => REG07_out(3 downto 0), -- f
-- Operation op5: MULT(g, t2)
input(19 downto 16) => REG06_out(3 downto 0), -- g
input(23 downto 20) => REG04_out(3 downto 0), -- t2
mux_select(1 downto 0) => ctrl(10 to 11),
output => MX_MULT00_out
);
-- MX_MULT01: op2, op4
MX_MULT01 : c_multiplexer
generic map(8, 2, 1)
port map
(
-- Operation op2: MULT(c, d)
input(3 downto 0) => REG09_out(3 downto 0), -- c
input(7 downto 4) => REG08_out(3 downto 0), -- d
-- Operation op4: MULT(t0, t1)
input(11 downto 8) => REG00_out(3 downto 0), -- t0
input(15 downto 12) => REG01_out(3 downto 0), -- t1
mux_select(0) => ctrl(12),
output => MX_MULT01_out
);
-- MX_SUB00: op6, op7
MX_SUB00 : c_multiplexer
generic map(8, 2, 1)
port map
(
-- Operation op6: SUB(t3, h)
input(3 downto 0) => REG03_out(3 downto 0), -- t3
input(7 downto 4) => REG05_out(3 downto 0), -- h
-- Operation op7: SUB(t5, t4)
input(11 downto 8) => REG01_out(3 downto 0), -- t5
input(15 downto 12) => REG02_out(3 downto 0), -- t4
mux_select(0) => ctrl(13),
output => MX_SUB00_out
);
-- MX_REG00: i, t0
MX_REG00 : c_multiplexer
generic map(4, 2, 1)
port map
(
input(3 downto 0) => SUB00_out(3 downto 0), -- i
input(7 downto 4) => MULT00_out(3 downto 0), -- t0
mux_select(0) => ctrl(14),
output => MX_REG00_out
);
-- MX_REG01: t1, t5
MX_REG01 : c_multiplexer
generic map(4, 2, 1)
port map
(
input(3 downto 0) => MULT01_out(3 downto 0), -- t1
input(7 downto 4) => SUB00_out(3 downto 0), -- t5
mux_select(0) => ctrl(15),
output => MX_REG01_out
);
-- MX_REG02: e, t4
MX_REG02 : c_multiplexer
generic map(4, 2, 1)
port map
(
input(3 downto 0) => e(3 downto 0), -- e
input(7 downto 4) => MULT00_out(3 downto 0), -- t4
mux_select(0) => ctrl(16),
output => MX_REG02_out
);
-- MX_REG03: a, t3
MX_REG03 : c_multiplexer
generic map(4, 2, 1)
port map
(
input(3 downto 0) => a(3 downto 0), -- a
input(7 downto 4) => MULT01_out(3 downto 0), -- t3
mux_select(0) => ctrl(17),
output => MX_REG03_out
);
-- MX_REG04: b, t2
MX_REG04 : c_multiplexer
generic map(4, 2, 1)
port map
(
input(3 downto 0) => b(3 downto 0), -- b
input(7 downto 4) => MULT00_out(3 downto 0), -- t2
mux_select(0) => ctrl(18),
output => MX_REG04_out
);
-- Primary outputs
i(3 downto 0) <= REG00_out(3 downto 0);
end rtl1;
|
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`protect end_protected
|
----------------------------------------------------------------------------
-- axi_datamover_addr_cntl.vhd
----------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_addr_cntl.vhd
--
-- Description:
-- This file implements the axi_datamover Master Address Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_datamover_addr_cntl.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
--
-- History:
-- DET 04/19/2011 Initial Version for EDK 13.3
--
--
-- DET 9/1/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Fixed Lint reported excesive line length for line 196.
-- ^^^^^^
--
-- DET 9/1/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Fixed a Lint reported issue with the vector widths of the addr2axi_aprot
-- assignment to the constant APROT_VALUE. The code was ok but Spyglass
-- was not interpreting the vector MS Index correctly, I changed the HDL
-- anyway.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
Use axi_datamover_v5_1.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_addr_cntl is
generic (
C_ADDR_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- sets the depth of the Command Queue FIFO
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the address bus width
C_ADDR_ID : Integer range 0 to 255 := 0;
-- Sets the value to be on the AxID output
C_ADDR_ID_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the AxID output
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Command Tag field width
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family
);
port (
-- Clock input ---------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------
-- AXI Address Channel I/O --------------------------------------------
addr2axi_aid : out std_logic_vector(C_ADDR_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
addr2axi_aaddr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
addr2axi_alen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
addr2axi_asize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
addr2axi_aburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_acache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_auser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_aprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
addr2axi_avalid : out std_logic; --
-- AXI Address Channel VALID output --
--
axi2addr_aready : in std_logic; --
-- AXI Address Channel READY input --
------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- Command Calculation Interface -----------------------------------------
mstr2addr_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : In std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : In std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
-- Sized to support 256 data beat bursts --
--
mstr2addr_size : In std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : In std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : In std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2addr_cmd_valid : in std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : out std_logic; --
-- Indication to the Command Calculator that the --
-- command is being accepted --
--------------------------------------------------------------------------
-- Halted Indication to Reset Module ------------------------------
addr2rst_stop_cmplt : out std_logic; --
-- Output flag indicating the address controller has stopped --
-- posting commands to the Address Channel due to a stop --
-- request vai the data2addr_stop_req input port --
------------------------------------------------------------------
-- Address Generation Control ---------------------------------------
allow_addr_req : in std_logic; --
-- Input used to enable/stall the posting of address requests. --
-- 0 = stall address request generation. --
-- 1 = Enable Address request geneartion --
--
addr_req_posted : out std_logic; --
-- Indication from the Address Channel Controller to external --
-- User logic that an address has been posted to the --
-- AXI Address Channel. --
---------------------------------------------------------------------
-- Data Channel Interface ---------------------------------------------
addr2data_addr_posted : Out std_logic; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel. --
--
data2addr_data_rdy : In std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer requset until the --
-- corresponding data is ready. This is expected to be held in --
-- the asserted state until the addr2data_addr_posted signal is --
-- asserted. --
--
data2addr_stop_req : In std_logic; --
-- Indication that the Data Channel has encountered an error --
-- or a soft shutdown request and needs the Address Controller --
-- to stop posting commands to the AXI Address channel --
-----------------------------------------------------------------------
-- Status Module Interface ---------------------------------------
addr2stat_calc_error : out std_logic; --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is loaded with a Calc error --
--
addr2stat_cmd_fifo_empty : out std_logic --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is empty --
------------------------------------------------------------------
);
end entity axi_datamover_addr_cntl;
architecture implementation of axi_datamover_addr_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Constant Declarations --------------------------------------------
Constant APROT_VALUE : std_logic_vector(2 downto 0) := (others => '0');
--'0' & -- bit 2, Normal Access
--'0' & -- bit 1, Nonsecure Access
--'0'; -- bit 0, Data Access
Constant LEN_WIDTH : integer := 8;
Constant SIZE_WIDTH : integer := 3;
Constant BURST_WIDTH : integer := 2;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant CALC_ERROR_WIDTH : integer := 1;
Constant ADDR_QUAL_WIDTH : integer := C_TAG_WIDTH + -- Cmd Tag field width
C_ADDR_WIDTH + -- Cmd Address field width
LEN_WIDTH + -- Cmd Len field width
SIZE_WIDTH + -- Cmd Size field width
BURST_WIDTH + -- Cmd Burst field width
CMD_CMPLT_WIDTH + -- Cmd Cmplt filed width
CALC_ERROR_WIDTH + -- Cmd Calc Error flag
8; -- Cmd Cache, user fields
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
-- Signal Declarations --------------------------------------------
signal sig_axi_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_axi_alen : std_logic_vector(7 downto 0) := (others => '0');
signal sig_axi_asize : std_logic_vector(2 downto 0) := (others => '0');
signal sig_axi_aburst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_axi_acache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_auser : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_avalid : std_logic := '0';
signal sig_axi_aready : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
Signal sig_aq_fifo_data_in : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
Signal sig_aq_fifo_data_out : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_fifo_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_fifo_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_calc_error : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len_reg : std_logic_vector(7 downto 0) := (others => '0');
signal sig_next_size_reg : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_addr_valid_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_pop_addr_reg : std_logic := '0';
signal sig_push_addr_reg : std_logic := '0';
signal sig_addr_reg_empty : std_logic := '0';
signal sig_addr_reg_full : std_logic := '0';
signal sig_posted_to_axi : std_logic := '0';
-- obsoleted signal sig_set_wfd_flop : std_logic := '0';
-- obsoleted signal sig_clr_wfd_flop : std_logic := '0';
-- obsoleted signal sig_wait_for_data : std_logic := '0';
-- obsoleted signal sig_data2addr_data_rdy_reg : std_logic := '0';
signal sig_allow_addr_req : std_logic := '0';
signal sig_posted_to_axi_2 : std_logic := '0';
signal new_cmd_in : std_logic;
signal first_addr_valid : std_logic;
signal first_addr_valid_del : std_logic;
signal first_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal last_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal addr2axi_cache_int : std_logic_vector (7 downto 0);
signal addr2axi_cache_int1 : std_logic_vector (7 downto 0);
signal last_one : std_logic;
signal latch : std_logic;
signal first_one : std_logic;
signal latch_n : std_logic;
signal latch_n_del : std_logic;
signal mstr2addr_cache_info_int : std_logic_vector (7 downto 0);
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_posted_to_axi : signal is "TRUE"; -- definition
Attribute KEEP of sig_posted_to_axi_2 : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi_2 : signal is "no";
begin --(architecture implementation)
-- AXI I/O Port assignments
addr2axi_aid <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_ADDR_ID, C_ADDR_ID_WIDTH));
addr2axi_aaddr <= sig_axi_addr ;
addr2axi_alen <= sig_axi_alen ;
addr2axi_asize <= sig_axi_asize ;
addr2axi_aburst <= sig_axi_aburst;
addr2axi_acache <= sig_axi_acache;
addr2axi_auser <= sig_axi_auser;
addr2axi_aprot <= APROT_VALUE ;
addr2axi_avalid <= sig_axi_avalid;
sig_axi_aready <= axi2addr_aready;
-- Command Calculator Handshake output
sig_fifo_wr_cmd_valid <= mstr2addr_cmd_valid ;
addr2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Data Channel Controller synchro pulse output
addr2data_addr_posted <= sig_addr_posted;
-- Status Module Interface outputs
addr2stat_calc_error <= sig_calc_error ;
addr2stat_cmd_fifo_empty <= sig_addr_reg_empty and
sig_cmd_fifo_empty;
-- Flag Indicating the Address Controller has completed a Stop
addr2rst_stop_cmplt <= (data2addr_stop_req and -- normal shutdown case
sig_addr_reg_empty) or
(data2addr_stop_req and -- shutdown after error trap
sig_calc_error);
-- Assign the address posting control and status
sig_allow_addr_req <= allow_addr_req ;
addr_req_posted <= sig_posted_to_axi_2 ;
-- Internal logic ------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where the cmd qualifier depth is
-- greater than 1.
--
------------------------------------------------------------
GEN_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH > 1) generate
begin
-- Format the input FIFO data word
sig_aq_fifo_data_in <= mstr2addr_cache &
mstr2addr_user &
mstr2addr_calc_error &
mstr2addr_cmd_cmplt &
mstr2addr_burst &
mstr2addr_size &
mstr2addr_len &
mstr2addr_addr &
mstr2addr_tag ;
-- Rip fields from FIFO output data word
sig_fifo_next_cache <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH + 7)
downto
(C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH + 4)
);
sig_fifo_next_user <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH + 3)
downto
(C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH)
);
sig_fifo_calc_error <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH)-1);
sig_fifo_next_cmd_cmplt <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH)-1);
sig_fifo_next_burst <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH)-1
downto
C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH) ;
sig_fifo_next_size <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH)-1
downto
C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH) ;
sig_fifo_next_len <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH)-1
downto
C_ADDR_WIDTH +
C_TAG_WIDTH) ;
sig_fifo_next_addr <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH)-1
downto
C_TAG_WIDTH) ;
sig_fifo_next_tag <= sig_aq_fifo_data_out(C_TAG_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_ADDR_QUAL_FIFO
--
-- Description:
-- Instance for the Address/Qualifier FIFO
--
------------------------------------------------------------
I_ADDR_QUAL_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => ADDR_QUAL_WIDTH ,
C_DEPTH => C_ADDR_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_aq_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_aq_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_ADDR_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where no additional FIFOing is needed
-- on the input command address/qualifiers.
--
------------------------------------------------------------
GEN_NO_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH = 1) generate
begin
-- Bypass FIFO
sig_fifo_next_tag <= mstr2addr_tag ;
sig_fifo_next_addr <= mstr2addr_addr ;
sig_fifo_next_len <= mstr2addr_len ;
sig_fifo_next_size <= mstr2addr_size ;
sig_fifo_next_burst <= mstr2addr_burst ;
sig_fifo_next_cache <= mstr2addr_cache ;
sig_fifo_next_user <= mstr2addr_user ;
sig_fifo_next_cmd_cmplt <= mstr2addr_cmd_cmplt ;
sig_fifo_calc_error <= mstr2addr_calc_error ;
sig_cmd_fifo_empty <= sig_addr_reg_empty ;
sig_fifo_wr_cmd_ready <= sig_fifo_rd_cmd_ready ;
sig_fifo_rd_cmd_valid <= sig_fifo_wr_cmd_valid ;
end generate GEN_NO_ADDR_FIFO;
-- Output Register Logic -------------------------------------------
sig_axi_addr <= sig_next_addr_reg ;
sig_axi_alen <= sig_next_len_reg ;
sig_axi_asize <= sig_next_size_reg ;
sig_axi_aburst <= sig_next_burst_reg ;
sig_axi_acache <= sig_next_cache_reg ;
sig_axi_auser <= sig_next_user_reg ;
sig_axi_avalid <= sig_addr_valid_reg ;
sig_calc_error <= sig_calc_error_reg ;
sig_fifo_rd_cmd_ready <= sig_addr_reg_empty and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_addr_posted <= sig_posted_to_axi ;
-- Internal signals
sig_push_addr_reg <= sig_addr_reg_empty and
sig_fifo_rd_cmd_valid and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_pop_addr_reg <= not(sig_calc_error_reg) and
sig_axi_aready and
sig_addr_reg_full;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_FIFO_REG
--
-- Process Description:
-- This process implements a register for the Address
-- Control FIFO that operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_ADDR_FIFO_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_addr_reg = '1') then
sig_next_tag_reg <= (others => '0') ;
sig_next_addr_reg <= (others => '0') ;
sig_next_len_reg <= (others => '0') ;
sig_next_size_reg <= (others => '0') ;
sig_next_burst_reg <= (others => '0') ;
sig_next_cache_reg <= (others => '0') ;
sig_next_user_reg <= (others => '0') ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_addr_valid_reg <= '0' ;
sig_calc_error_reg <= '0' ;
sig_addr_reg_empty <= '1' ;
sig_addr_reg_full <= '0' ;
elsif (sig_push_addr_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_addr_reg <= sig_fifo_next_addr ;
sig_next_len_reg <= sig_fifo_next_len ;
sig_next_size_reg <= sig_fifo_next_size ;
sig_next_burst_reg <= sig_fifo_next_burst ;
sig_next_cache_reg <= sig_fifo_next_cache ;
sig_next_user_reg <= sig_fifo_next_user ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_addr_valid_reg <= not(sig_fifo_calc_error);
sig_calc_error_reg <= sig_fifo_calc_error ;
sig_addr_reg_empty <= '0' ;
sig_addr_reg_full <= '1' ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_FIFO_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_POSTED_FLAG
--
-- Process Description:
-- This implements a FLOP that creates a 1 clock wide pulse
-- indicating a new address/qualifier set has been posted to
-- the AXI Addres Channel outputs. This is used to synchronize
-- the Data Channel Controller.
--
-------------------------------------------------------------
IMP_POSTED_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
elsif (sig_push_addr_reg = '1') then
sig_posted_to_axi <= '1';
sig_posted_to_axi_2 <= '1';
else
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
end if;
end if;
end process IMP_POSTED_FLAG;
-- PROC_CMD_DETECT : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_addr_valid_del <= first_addr_valid;
-- end if;
-- end process PROC_CMD_DETECT;
--
-- PROC_ADDR_DET : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= (others => '0');
-- last_addr_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (mstr2addr_cmd_valid = '1' and first_addr_valid = '0') then
-- first_addr_valid <= '1';
-- first_addr_int <= mstr2addr_addr;
-- last_addr_int <= last_addr_int;
-- elsif (mstr2addr_cmd_cmplt = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= first_addr_int;
-- last_addr_int <= mstr2addr_addr;
-- end if;
-- end if;
-- end process PROC_ADDR_DET;
--
-- latch <= first_addr_valid and (not first_addr_valid_del);
-- latch_n <= (not first_addr_valid) and first_addr_valid_del;
--
-- PROC_CACHE1 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- mstr2addr_cache_info_int <= (others => '0');
-- latch_n_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (latch_n = '1') then
-- mstr2addr_cache_info_int <= mstr2addr_cache_info;
-- end if;
-- latch_n_del <= latch_n;
-- end if;
-- end process PROC_CACHE1;
--
--
-- PROC_CACHE : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int1 <= (others => '0');
-- first_one <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_one <= '0';
---- if (latch = '1' and first_one = '0') then -- first one
-- if (sig_addr_valid_reg = '0' and first_addr_valid = '0') then
-- addr2axi_cache_int1 <= mstr2addr_cache_info;
---- first_one <= '1';
---- elsif (latch_n_del = '1') then
---- addr2axi_cache_int <= mstr2addr_cache_info_int;
-- elsif ((first_addr_int = sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- elsif ((last_addr_int >= sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- end if;
-- end if;
-- end process PROC_CACHE;
--
--
-- PROC_CACHE2 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- addr2axi_cache_int <= addr2axi_cache_int1;
-- end if;
-- end process PROC_CACHE2;
--
--addr2axi_cache <= addr2axi_cache_int (3 downto 0);
--addr2axi_user <= addr2axi_cache_int (7 downto 4);
--
end implementation;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 32) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 32) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 32) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 32) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 32) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 32) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 32) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 32) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 32) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 32) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 32) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
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