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-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Simulation constants, functions and utilities.
--
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.physical.all;
package simulation is
-- predefined constants to ease testvector concatenation
constant U8 : T_SLV_8 := (others => 'U');
constant U16 : T_SLV_16 := (others => 'U');
constant U24 : T_SLV_24 := (others => 'U');
constant U32 : T_SLV_32 := (others => 'U');
constant D8 : T_SLV_8 := (others => '-');
constant D16 : T_SLV_16 := (others => '-');
constant D24 : T_SLV_24 := (others => '-');
constant D32 : T_SLV_32 := (others => '-');
-- Testbench Status Management
-- ===========================================================================
-- The testbench is marked as failed. If a message is provided, it is
-- reported as an error.
procedure tbFail(msg : in string := "");
-- If the passed condition has evaluated false, the testbench is marked
-- as failed. In this case, the optional message will be reported as an
-- error if one was provided.
procedure tbAssert(cond : in boolean; msg : in string := "");
-- Prints out the overall testbench result as defined by the automated
-- testbench process. Unless tbFail() or tbAssert() with a false condition
-- have been called before, a successful completion will be reported, a
-- failure otherwise.
procedure tbPrintResult;
-- clock generation
-- ===========================================================================
subtype T_DutyCycle is REAL range 0.0 to 1.0;
procedure simStop;
impure function simIsStopped return BOOLEAN;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5);
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5);
-- waveform generation
-- ===========================================================================
type T_SIM_WAVEFORM_TUPLE_SL is record
Delay : TIME;
Value : STD_LOGIC;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_8 is record
Delay : TIME;
Value : T_SLV_8;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_16 is record
Delay : TIME;
Value : T_SLV_16;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_24 is record
Delay : TIME;
Value : T_SLV_24;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_32 is record
Delay : TIME;
Value : T_SLV_32;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_48 is record
Delay : TIME;
Value : T_SLV_48;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_64 is record
Delay : TIME;
Value : T_SLV_64;
end record;
type T_SIM_WAVEFORM_SL is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SL;
type T_SIM_WAVEFORM_SLV_8 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8;
type T_SIM_WAVEFORM_SLV_16 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16;
type T_SIM_WAVEFORM_SLV_24 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24;
type T_SIM_WAVEFORM_SLV_32 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32;
type T_SIM_WAVEFORM_SLV_48 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48;
type T_SIM_WAVEFORM_SLV_64 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64;
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform: T_TIMEVEC; InitialValue : BOOLEAN);
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8);
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16);
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24);
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32);
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48);
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64);
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC;
-- TODO: integrate VCD simulation functions and procedures from sim_value_change_dump.vhdl here
-- checksum functions
-- ===========================================================================
-- TODO: move checksum functions here
end;
use std.TextIO.all;
package body simulation is
-- Testbench Status Management
-- ===========================================================================
-- Internal state variable to log a failure condition for final reporting.
-- Once de-asserted, this variable will never return to a value of true.
shared variable pass : boolean := true;
shared variable simStopped : BOOLEAN := FALSE;
procedure tbFail(msg : in string := "") is
begin
if (str_length(msg) > 0) then
report str_trim(msg) severity error;
end if;
pass := false;
end;
procedure tbAssert(cond : in boolean; msg : in string := "") is
begin
if not cond then
tbFail(msg);
end if;
end;
procedure tbPrintResult is
variable l : line;
begin
write(l, string'("SIMULATION RESULT = "));
if pass then
write(l, string'("PASSED"));
else
write(l, string'("FAILED"));
end if;
writeline(output, l);
end procedure;
-- clock generation
procedure simStop is
begin
simStopped := TRUE;
end procedure;
impure function simIsStopped return BOOLEAN is
begin
return simStopped;
end function;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5) is
constant Period : TIME := to_time(Frequency);
begin
simGenerateClock(Clock, Period, DutyCycle);
end procedure;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5) is
constant TIME_HIGH : TIME := Period * DutyCycle;
constant TIME_LOW : TIME := Period - TIME_HIGH;
begin
Clock <= '0';
while (not simStopped) loop
wait for TIME_LOW;
Clock <= '1';
wait for TIME_HIGH;
Clock <= '0';
end loop;
end procedure;
-- waveform generation
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform : T_TIMEVEC; InitialValue : BOOLEAN) is
variable State : BOOLEAN := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0') is
variable State : STD_LOGIC := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0') is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC is
begin
return (0 => Pause, 1 => ResetPulse);
end function;
-- checksum functions
-- ===========================================================================
-- TODO: move checksum functions here
end package body;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Simulation constants, functions and utilities.
--
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.physical.all;
package simulation is
-- predefined constants to ease testvector concatenation
constant U8 : T_SLV_8 := (others => 'U');
constant U16 : T_SLV_16 := (others => 'U');
constant U24 : T_SLV_24 := (others => 'U');
constant U32 : T_SLV_32 := (others => 'U');
constant D8 : T_SLV_8 := (others => '-');
constant D16 : T_SLV_16 := (others => '-');
constant D24 : T_SLV_24 := (others => '-');
constant D32 : T_SLV_32 := (others => '-');
-- Testbench Status Management
-- ===========================================================================
-- The testbench is marked as failed. If a message is provided, it is
-- reported as an error.
procedure tbFail(msg : in string := "");
-- If the passed condition has evaluated false, the testbench is marked
-- as failed. In this case, the optional message will be reported as an
-- error if one was provided.
procedure tbAssert(cond : in boolean; msg : in string := "");
-- Prints out the overall testbench result as defined by the automated
-- testbench process. Unless tbFail() or tbAssert() with a false condition
-- have been called before, a successful completion will be reported, a
-- failure otherwise.
procedure tbPrintResult;
-- clock generation
-- ===========================================================================
subtype T_DutyCycle is REAL range 0.0 to 1.0;
procedure simStop;
impure function simIsStopped return BOOLEAN;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5);
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5);
-- waveform generation
-- ===========================================================================
type T_SIM_WAVEFORM_TUPLE_SL is record
Delay : TIME;
Value : STD_LOGIC;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_8 is record
Delay : TIME;
Value : T_SLV_8;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_16 is record
Delay : TIME;
Value : T_SLV_16;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_24 is record
Delay : TIME;
Value : T_SLV_24;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_32 is record
Delay : TIME;
Value : T_SLV_32;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_48 is record
Delay : TIME;
Value : T_SLV_48;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_64 is record
Delay : TIME;
Value : T_SLV_64;
end record;
type T_SIM_WAVEFORM_SL is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SL;
type T_SIM_WAVEFORM_SLV_8 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8;
type T_SIM_WAVEFORM_SLV_16 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16;
type T_SIM_WAVEFORM_SLV_24 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24;
type T_SIM_WAVEFORM_SLV_32 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32;
type T_SIM_WAVEFORM_SLV_48 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48;
type T_SIM_WAVEFORM_SLV_64 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64;
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform: T_TIMEVEC; InitialValue : BOOLEAN);
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8);
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16);
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24);
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32);
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48);
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64);
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC;
-- TODO: integrate VCD simulation functions and procedures from sim_value_change_dump.vhdl here
-- checksum functions
-- ===========================================================================
-- TODO: move checksum functions here
end;
use std.TextIO.all;
package body simulation is
-- Testbench Status Management
-- ===========================================================================
-- Internal state variable to log a failure condition for final reporting.
-- Once de-asserted, this variable will never return to a value of true.
shared variable pass : boolean := true;
shared variable simStopped : BOOLEAN := FALSE;
procedure tbFail(msg : in string := "") is
begin
if (str_length(msg) > 0) then
report str_trim(msg) severity error;
end if;
pass := false;
end;
procedure tbAssert(cond : in boolean; msg : in string := "") is
begin
if not cond then
tbFail(msg);
end if;
end;
procedure tbPrintResult is
variable l : line;
begin
write(l, string'("SIMULATION RESULT = "));
if pass then
write(l, string'("PASSED"));
else
write(l, string'("FAILED"));
end if;
writeline(output, l);
end procedure;
-- clock generation
procedure simStop is
begin
simStopped := TRUE;
end procedure;
impure function simIsStopped return BOOLEAN is
begin
return simStopped;
end function;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5) is
constant Period : TIME := to_time(Frequency);
begin
simGenerateClock(Clock, Period, DutyCycle);
end procedure;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5) is
constant TIME_HIGH : TIME := Period * DutyCycle;
constant TIME_LOW : TIME := Period - TIME_HIGH;
begin
Clock <= '0';
while (not simStopped) loop
wait for TIME_LOW;
Clock <= '1';
wait for TIME_HIGH;
Clock <= '0';
end loop;
end procedure;
-- waveform generation
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform : T_TIMEVEC; InitialValue : BOOLEAN) is
variable State : BOOLEAN := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0') is
variable State : STD_LOGIC := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0') is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC is
begin
return (0 => Pause, 1 => ResetPulse);
end function;
-- checksum functions
-- ===========================================================================
-- TODO: move checksum functions here
end package body;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Simulation constants, functions and utilities.
--
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.physical.all;
package simulation is
-- predefined constants to ease testvector concatenation
constant U8 : T_SLV_8 := (others => 'U');
constant U16 : T_SLV_16 := (others => 'U');
constant U24 : T_SLV_24 := (others => 'U');
constant U32 : T_SLV_32 := (others => 'U');
constant D8 : T_SLV_8 := (others => '-');
constant D16 : T_SLV_16 := (others => '-');
constant D24 : T_SLV_24 := (others => '-');
constant D32 : T_SLV_32 := (others => '-');
-- Testbench Status Management
-- ===========================================================================
-- The testbench is marked as failed. If a message is provided, it is
-- reported as an error.
procedure tbFail(msg : in string := "");
-- If the passed condition has evaluated false, the testbench is marked
-- as failed. In this case, the optional message will be reported as an
-- error if one was provided.
procedure tbAssert(cond : in boolean; msg : in string := "");
-- Prints out the overall testbench result as defined by the automated
-- testbench process. Unless tbFail() or tbAssert() with a false condition
-- have been called before, a successful completion will be reported, a
-- failure otherwise.
procedure tbPrintResult;
-- clock generation
-- ===========================================================================
subtype T_DutyCycle is REAL range 0.0 to 1.0;
procedure simStop;
impure function simIsStopped return BOOLEAN;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5);
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5);
-- waveform generation
-- ===========================================================================
type T_SIM_WAVEFORM_TUPLE_SL is record
Delay : TIME;
Value : STD_LOGIC;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_8 is record
Delay : TIME;
Value : T_SLV_8;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_16 is record
Delay : TIME;
Value : T_SLV_16;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_24 is record
Delay : TIME;
Value : T_SLV_24;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_32 is record
Delay : TIME;
Value : T_SLV_32;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_48 is record
Delay : TIME;
Value : T_SLV_48;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_64 is record
Delay : TIME;
Value : T_SLV_64;
end record;
type T_SIM_WAVEFORM_SL is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SL;
type T_SIM_WAVEFORM_SLV_8 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8;
type T_SIM_WAVEFORM_SLV_16 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16;
type T_SIM_WAVEFORM_SLV_24 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24;
type T_SIM_WAVEFORM_SLV_32 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32;
type T_SIM_WAVEFORM_SLV_48 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48;
type T_SIM_WAVEFORM_SLV_64 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64;
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform: T_TIMEVEC; InitialValue : BOOLEAN);
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8);
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16);
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24);
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32);
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48);
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64);
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC;
-- TODO: integrate VCD simulation functions and procedures from sim_value_change_dump.vhdl here
-- checksum functions
-- ===========================================================================
-- TODO: move checksum functions here
end;
use std.TextIO.all;
package body simulation is
-- Testbench Status Management
-- ===========================================================================
-- Internal state variable to log a failure condition for final reporting.
-- Once de-asserted, this variable will never return to a value of true.
shared variable pass : boolean := true;
shared variable simStopped : BOOLEAN := FALSE;
procedure tbFail(msg : in string := "") is
begin
if (str_length(msg) > 0) then
report str_trim(msg) severity error;
end if;
pass := false;
end;
procedure tbAssert(cond : in boolean; msg : in string := "") is
begin
if not cond then
tbFail(msg);
end if;
end;
procedure tbPrintResult is
variable l : line;
begin
write(l, string'("SIMULATION RESULT = "));
if pass then
write(l, string'("PASSED"));
else
write(l, string'("FAILED"));
end if;
writeline(output, l);
end procedure;
-- clock generation
procedure simStop is
begin
simStopped := TRUE;
end procedure;
impure function simIsStopped return BOOLEAN is
begin
return simStopped;
end function;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5) is
constant Period : TIME := to_time(Frequency);
begin
simGenerateClock(Clock, Period, DutyCycle);
end procedure;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5) is
constant TIME_HIGH : TIME := Period * DutyCycle;
constant TIME_LOW : TIME := Period - TIME_HIGH;
begin
Clock <= '0';
while (not simStopped) loop
wait for TIME_LOW;
Clock <= '1';
wait for TIME_HIGH;
Clock <= '0';
end loop;
end procedure;
-- waveform generation
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform : T_TIMEVEC; InitialValue : BOOLEAN) is
variable State : BOOLEAN := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0') is
variable State : STD_LOGIC := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0') is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC is
begin
return (0 => Pause, 1 => ResetPulse);
end function;
-- checksum functions
-- ===========================================================================
-- TODO: move checksum functions here
end package body;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Simulation constants, functions and utilities.
--
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.physical.all;
package simulation is
-- predefined constants to ease testvector concatenation
constant U8 : T_SLV_8 := (others => 'U');
constant U16 : T_SLV_16 := (others => 'U');
constant U24 : T_SLV_24 := (others => 'U');
constant U32 : T_SLV_32 := (others => 'U');
constant D8 : T_SLV_8 := (others => '-');
constant D16 : T_SLV_16 := (others => '-');
constant D24 : T_SLV_24 := (others => '-');
constant D32 : T_SLV_32 := (others => '-');
-- Testbench Status Management
-- ===========================================================================
-- The testbench is marked as failed. If a message is provided, it is
-- reported as an error.
procedure tbFail(msg : in string := "");
-- If the passed condition has evaluated false, the testbench is marked
-- as failed. In this case, the optional message will be reported as an
-- error if one was provided.
procedure tbAssert(cond : in boolean; msg : in string := "");
-- Prints out the overall testbench result as defined by the automated
-- testbench process. Unless tbFail() or tbAssert() with a false condition
-- have been called before, a successful completion will be reported, a
-- failure otherwise.
procedure tbPrintResult;
-- clock generation
-- ===========================================================================
subtype T_DutyCycle is REAL range 0.0 to 1.0;
procedure simStop;
impure function simIsStopped return BOOLEAN;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5);
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5);
-- waveform generation
-- ===========================================================================
type T_SIM_WAVEFORM_TUPLE_SL is record
Delay : TIME;
Value : STD_LOGIC;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_8 is record
Delay : TIME;
Value : T_SLV_8;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_16 is record
Delay : TIME;
Value : T_SLV_16;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_24 is record
Delay : TIME;
Value : T_SLV_24;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_32 is record
Delay : TIME;
Value : T_SLV_32;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_48 is record
Delay : TIME;
Value : T_SLV_48;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_64 is record
Delay : TIME;
Value : T_SLV_64;
end record;
type T_SIM_WAVEFORM_SL is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SL;
type T_SIM_WAVEFORM_SLV_8 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8;
type T_SIM_WAVEFORM_SLV_16 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16;
type T_SIM_WAVEFORM_SLV_24 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24;
type T_SIM_WAVEFORM_SLV_32 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32;
type T_SIM_WAVEFORM_SLV_48 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48;
type T_SIM_WAVEFORM_SLV_64 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64;
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform: T_TIMEVEC; InitialValue : BOOLEAN);
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8);
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16);
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24);
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32);
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48);
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64);
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC;
-- TODO: integrate VCD simulation functions and procedures from sim_value_change_dump.vhdl here
-- checksum functions
-- ===========================================================================
-- TODO: move checksum functions here
end;
use std.TextIO.all;
package body simulation is
-- Testbench Status Management
-- ===========================================================================
-- Internal state variable to log a failure condition for final reporting.
-- Once de-asserted, this variable will never return to a value of true.
shared variable pass : boolean := true;
shared variable simStopped : BOOLEAN := FALSE;
procedure tbFail(msg : in string := "") is
begin
if (str_length(msg) > 0) then
report str_trim(msg) severity error;
end if;
pass := false;
end;
procedure tbAssert(cond : in boolean; msg : in string := "") is
begin
if not cond then
tbFail(msg);
end if;
end;
procedure tbPrintResult is
variable l : line;
begin
write(l, string'("SIMULATION RESULT = "));
if pass then
write(l, string'("PASSED"));
else
write(l, string'("FAILED"));
end if;
writeline(output, l);
end procedure;
-- clock generation
procedure simStop is
begin
simStopped := TRUE;
end procedure;
impure function simIsStopped return BOOLEAN is
begin
return simStopped;
end function;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5) is
constant Period : TIME := to_time(Frequency);
begin
simGenerateClock(Clock, Period, DutyCycle);
end procedure;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5) is
constant TIME_HIGH : TIME := Period * DutyCycle;
constant TIME_LOW : TIME := Period - TIME_HIGH;
begin
Clock <= '0';
while (not simStopped) loop
wait for TIME_LOW;
Clock <= '1';
wait for TIME_HIGH;
Clock <= '0';
end loop;
end procedure;
-- waveform generation
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform : T_TIMEVEC; InitialValue : BOOLEAN) is
variable State : BOOLEAN := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0') is
variable State : STD_LOGIC := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0') is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC is
begin
return (0 => Pause, 1 => ResetPulse);
end function;
-- checksum functions
-- ===========================================================================
-- TODO: move checksum functions here
end package body;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Simulation constants, functions and utilities.
--
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.physical.all;
package simulation is
-- predefined constants to ease testvector concatenation
constant U8 : T_SLV_8 := (others => 'U');
constant U16 : T_SLV_16 := (others => 'U');
constant U24 : T_SLV_24 := (others => 'U');
constant U32 : T_SLV_32 := (others => 'U');
constant D8 : T_SLV_8 := (others => '-');
constant D16 : T_SLV_16 := (others => '-');
constant D24 : T_SLV_24 := (others => '-');
constant D32 : T_SLV_32 := (others => '-');
-- Testbench Status Management
-- ===========================================================================
-- The testbench is marked as failed. If a message is provided, it is
-- reported as an error.
procedure tbFail(msg : in string := "");
-- If the passed condition has evaluated false, the testbench is marked
-- as failed. In this case, the optional message will be reported as an
-- error if one was provided.
procedure tbAssert(cond : in boolean; msg : in string := "");
-- Prints out the overall testbench result as defined by the automated
-- testbench process. Unless tbFail() or tbAssert() with a false condition
-- have been called before, a successful completion will be reported, a
-- failure otherwise.
procedure tbPrintResult;
-- clock generation
-- ===========================================================================
subtype T_DutyCycle is REAL range 0.0 to 1.0;
procedure simStop;
impure function simIsStopped return BOOLEAN;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5);
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5);
-- waveform generation
-- ===========================================================================
type T_SIM_WAVEFORM_TUPLE_SL is record
Delay : TIME;
Value : STD_LOGIC;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_8 is record
Delay : TIME;
Value : T_SLV_8;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_16 is record
Delay : TIME;
Value : T_SLV_16;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_24 is record
Delay : TIME;
Value : T_SLV_24;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_32 is record
Delay : TIME;
Value : T_SLV_32;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_48 is record
Delay : TIME;
Value : T_SLV_48;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_64 is record
Delay : TIME;
Value : T_SLV_64;
end record;
type T_SIM_WAVEFORM_SL is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SL;
type T_SIM_WAVEFORM_SLV_8 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8;
type T_SIM_WAVEFORM_SLV_16 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16;
type T_SIM_WAVEFORM_SLV_24 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24;
type T_SIM_WAVEFORM_SLV_32 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32;
type T_SIM_WAVEFORM_SLV_48 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48;
type T_SIM_WAVEFORM_SLV_64 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64;
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform: T_TIMEVEC; InitialValue : BOOLEAN);
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8);
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16);
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24);
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32);
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48);
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64);
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC;
-- TODO: integrate VCD simulation functions and procedures from sim_value_change_dump.vhdl here
-- checksum functions
-- ===========================================================================
-- TODO: move checksum functions here
end;
use std.TextIO.all;
package body simulation is
-- Testbench Status Management
-- ===========================================================================
-- Internal state variable to log a failure condition for final reporting.
-- Once de-asserted, this variable will never return to a value of true.
shared variable pass : boolean := true;
shared variable simStopped : BOOLEAN := FALSE;
procedure tbFail(msg : in string := "") is
begin
if (str_length(msg) > 0) then
report str_trim(msg) severity error;
end if;
pass := false;
end;
procedure tbAssert(cond : in boolean; msg : in string := "") is
begin
if not cond then
tbFail(msg);
end if;
end;
procedure tbPrintResult is
variable l : line;
begin
write(l, string'("SIMULATION RESULT = "));
if pass then
write(l, string'("PASSED"));
else
write(l, string'("FAILED"));
end if;
writeline(output, l);
end procedure;
-- clock generation
procedure simStop is
begin
simStopped := TRUE;
end procedure;
impure function simIsStopped return BOOLEAN is
begin
return simStopped;
end function;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5) is
constant Period : TIME := to_time(Frequency);
begin
simGenerateClock(Clock, Period, DutyCycle);
end procedure;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5) is
constant TIME_HIGH : TIME := Period * DutyCycle;
constant TIME_LOW : TIME := Period - TIME_HIGH;
begin
Clock <= '0';
while (not simStopped) loop
wait for TIME_LOW;
Clock <= '1';
wait for TIME_HIGH;
Clock <= '0';
end loop;
end procedure;
-- waveform generation
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform : T_TIMEVEC; InitialValue : BOOLEAN) is
variable State : BOOLEAN := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0') is
variable State : STD_LOGIC := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0') is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC is
begin
return (0 => Pause, 1 => ResetPulse);
end function;
-- checksum functions
-- ===========================================================================
-- TODO: move checksum functions here
end package body;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_misc.all;
entity flit_tracker is
generic (
DATA_WIDTH: integer := 32;
tracker_file: string :="track.txt"
);
port (
clk: in std_logic;
RX: in std_logic_vector (DATA_WIDTH-1 downto 0);
valid_in : in std_logic
);
end;
architecture behavior of flit_tracker is
begin
process(clk)
variable source_id, destination_id, Packet_length, packet_id: integer;
variable LINEVARIABLE : line;
variable xor_check : std_logic;
file trace_file : text is out tracker_file;
begin
Packet_length := 0;
destination_id := 0;
source_id := 0;
packet_id := 0;
if clk'event and clk = '1' then
if unsigned(RX) /= to_unsigned(0, RX'length) and valid_in = '1' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" then
Packet_length := to_integer(unsigned(RX(28 downto 17)));
destination_id := to_integer(unsigned(RX(16 downto 13)));
source_id := to_integer(unsigned(RX(12 downto 9)));
packet_id := to_integer(unsigned(RX(8 downto 1)));
xor_check := XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
if xor_check = RX(0) then
write(LINEVARIABLE, "H flit at " & time'image(now) & " From " & integer'image(source_id) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(packet_id));
else
write(LINEVARIABLE, "H flit at " & time'image(now) & " From " & integer'image(source_id) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(packet_id) & " FAULTY ");
end if;
writeline(trace_file, LINEVARIABLE);
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
xor_check := XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
if xor_check = RX(0) then
write(LINEVARIABLE, "B flit at " & time'image(now));
else
write(LINEVARIABLE, "B flit at " & time'image(now) & " FAULTY ");
end if;
writeline(trace_file, LINEVARIABLE);
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
xor_check := XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
if xor_check = RX(0) then
write(LINEVARIABLE, "T flit at " & time'image(now));
else
write(LINEVARIABLE, "T flit at " & time'image(now) & " FAULTY ");
end if;
writeline(trace_file, LINEVARIABLE);
end if;
end if;
end if;
end process;
end; |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_misc.all;
entity flit_tracker is
generic (
DATA_WIDTH: integer := 32;
tracker_file: string :="track.txt"
);
port (
clk: in std_logic;
RX: in std_logic_vector (DATA_WIDTH-1 downto 0);
valid_in : in std_logic
);
end;
architecture behavior of flit_tracker is
begin
process(clk)
variable source_id, destination_id, Packet_length, packet_id: integer;
variable LINEVARIABLE : line;
variable xor_check : std_logic;
file trace_file : text is out tracker_file;
begin
Packet_length := 0;
destination_id := 0;
source_id := 0;
packet_id := 0;
if clk'event and clk = '1' then
if unsigned(RX) /= to_unsigned(0, RX'length) and valid_in = '1' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" then
Packet_length := to_integer(unsigned(RX(28 downto 17)));
destination_id := to_integer(unsigned(RX(16 downto 13)));
source_id := to_integer(unsigned(RX(12 downto 9)));
packet_id := to_integer(unsigned(RX(8 downto 1)));
xor_check := XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
if xor_check = RX(0) then
write(LINEVARIABLE, "H flit at " & time'image(now) & " From " & integer'image(source_id) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(packet_id));
else
write(LINEVARIABLE, "H flit at " & time'image(now) & " From " & integer'image(source_id) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(packet_id) & " FAULTY ");
end if;
writeline(trace_file, LINEVARIABLE);
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
xor_check := XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
if xor_check = RX(0) then
write(LINEVARIABLE, "B flit at " & time'image(now));
else
write(LINEVARIABLE, "B flit at " & time'image(now) & " FAULTY ");
end if;
writeline(trace_file, LINEVARIABLE);
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
xor_check := XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
if xor_check = RX(0) then
write(LINEVARIABLE, "T flit at " & time'image(now));
else
write(LINEVARIABLE, "T flit at " & time'image(now) & " FAULTY ");
end if;
writeline(trace_file, LINEVARIABLE);
end if;
end if;
end if;
end process;
end; |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_misc.all;
entity flit_tracker is
generic (
DATA_WIDTH: integer := 32;
tracker_file: string :="track.txt"
);
port (
clk: in std_logic;
RX: in std_logic_vector (DATA_WIDTH-1 downto 0);
valid_in : in std_logic
);
end;
architecture behavior of flit_tracker is
begin
process(clk)
variable source_id, destination_id, Packet_length, packet_id: integer;
variable LINEVARIABLE : line;
variable xor_check : std_logic;
file trace_file : text is out tracker_file;
begin
Packet_length := 0;
destination_id := 0;
source_id := 0;
packet_id := 0;
if clk'event and clk = '1' then
if unsigned(RX) /= to_unsigned(0, RX'length) and valid_in = '1' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" then
Packet_length := to_integer(unsigned(RX(28 downto 17)));
destination_id := to_integer(unsigned(RX(16 downto 13)));
source_id := to_integer(unsigned(RX(12 downto 9)));
packet_id := to_integer(unsigned(RX(8 downto 1)));
xor_check := XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
if xor_check = RX(0) then
write(LINEVARIABLE, "H flit at " & time'image(now) & " From " & integer'image(source_id) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(packet_id));
else
write(LINEVARIABLE, "H flit at " & time'image(now) & " From " & integer'image(source_id) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(packet_id) & " FAULTY ");
end if;
writeline(trace_file, LINEVARIABLE);
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
xor_check := XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
if xor_check = RX(0) then
write(LINEVARIABLE, "B flit at " & time'image(now));
else
write(LINEVARIABLE, "B flit at " & time'image(now) & " FAULTY ");
end if;
writeline(trace_file, LINEVARIABLE);
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
xor_check := XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
if xor_check = RX(0) then
write(LINEVARIABLE, "T flit at " & time'image(now));
else
write(LINEVARIABLE, "T flit at " & time'image(now) & " FAULTY ");
end if;
writeline(trace_file, LINEVARIABLE);
end if;
end if;
end if;
end process;
end; |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:32:48 11/24/2011
-- Design Name:
-- Module Name: C:/Users/Digitales/Desktop/roadWarriorV2/roadWarrior/testRoadWarrior.vhd
-- Project Name: roadWarrior
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: roadWarrior
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testRoadWarrior IS
END testRoadWarrior;
ARCHITECTURE behavior OF testRoadWarrior IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT roadWarrior
PORT(
clk : IN std_logic;
avance : IN std_logic;
reset : IN std_logic;
memoria : OUT std_logic_vector(6 downto 0);
registro : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal avance : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal memoria : std_logic_vector(6 downto 0);
signal registro : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
constant avance_period : time := 200 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: roadWarrior PORT MAP (
clk => clk,
avance => avance,
reset => reset,
memoria => memoria,
registro => registro
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
avance_process :process
begin
avance <= '0';
wait for avance_period;
avance <= '1';
wait for clk_period;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 10 ns;
reset <= '1';
wait for clk_period*3;
reset <= '0';
wait for clk_period*3;
-- insert stimulus here
wait;
end process;
END;
|
--
-- File Name: SortListPkg_int.vhd
-- Design Unit Name: SortListPkg_int
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis [email protected]
--
-- Description:
-- Sorting utility for array of scalars
-- Uses protected type so as to shrink and expand the data structure
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 06/2008: 0.1 Initial revision
-- Numerous revisions for VHDL Testbenches and Verification
-- 02/2009: 1.0 First Public Released Version
-- 02/25/2009 1.1 Replaced reference to std_2008 with a reference to
-- ieee_proposed.standard_additions.all ;
-- 06/16/2010 1.2 Added EraseList parameter to to_array
-- 3/2011 2.0 added inside as non protected type
-- 6/2011 2.1 added sort as non protected type
-- 4/2013 2013.04 No Changes
-- 5/2013 2013.05 No changes of substance.
-- Deleted extra variable declaration in procedure remove
-- 1/2014 2014.01 Added RevSort. Added AllowDuplicate paramter to Add procedure
-- 1/2015 2015.01 Changed Assert/Report to Alert
-- 11/2016 2016.11 Revised Add. When AllowDuplicate, add a matching value last.
-- 01/2020 2020.01 Updated Licenses to Apache
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2008 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use work.OsvvmGlobalPkg.all ;
use work.AlertLogPkg.all ;
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.std_logic_textio.all ;
-- comment out following 2 lines with VHDL-2008. Leave in for VHDL-2002
-- library ieee_proposed ; -- remove with VHDL-2008
-- use ieee_proposed.standard_additions.all ; -- remove with VHDL-2008
package SortListPkg_int is
-- with VHDL-2008, convert package to generic package
-- convert subtypes ElementType and ArrayofElementType to generics
-- package SortListGenericPkg is
subtype ElementType is integer ;
subtype ArrayofElementType is integer_vector ;
impure function inside (constant E : ElementType; constant A : in ArrayofElementType) return boolean ;
impure function sort (constant A : in ArrayofElementType) return ArrayofElementType ;
impure function revsort (constant A : in ArrayofElementType) return ArrayofElementType ;
type SortListPType is protected
procedure add ( constant A : in ElementType ; constant AllowDuplicate : Boolean := FALSE ) ;
procedure add ( constant A : in ArrayofElementType ) ;
procedure add ( constant A : in ArrayofElementType ; Min, Max : ElementType ) ;
procedure add ( variable A : inout SortListPType ) ;
-- Count items in list
impure function count return integer ;
impure function find_index ( constant A : ElementType) return integer ;
impure function inside (constant A : ElementType) return boolean ;
procedure insert ( constant A : in ElementType; constant index : in integer := 1 ) ;
impure function get ( constant index : in integer := 1 ) return ElementType ;
procedure erase ;
impure function Empty return boolean ;
procedure print ;
procedure remove ( constant A : in ElementType ) ;
procedure remove ( constant A : in ArrayofElementType ) ;
procedure remove ( variable A : inout SortListPType ) ;
impure function to_array (constant EraseList : boolean := FALSE) return ArrayofElementType ;
impure function to_rev_array (constant EraseList : boolean := FALSE) return ArrayofElementType ;
end protected SortListPType ;
end SortListPkg_int ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body SortListPkg_int is
impure function inside (constant E : ElementType; constant A : in ArrayofElementType) return boolean is
begin
for i in A'range loop
if E = A(i) then
return TRUE ;
end if ;
end loop ;
return FALSE ;
end function inside ;
type SortListPType is protected body
type ListType ;
type ListPointerType is access ListType ;
type ListType is record
A : ElementType ;
-- item_num : integer ;
NextPtr : ListPointerType ;
-- PrevPtr : ListPointerType ;
end record ;
variable HeadPointer : ListPointerType := NULL ;
-- variable TailPointer : ListPointerType := NULL ;
procedure add ( constant A : in ElementType ; constant AllowDuplicate : Boolean := FALSE ) is
variable CurPtr, tempPtr : ListPointerType ;
begin
if HeadPointer = NULL then
HeadPointer := new ListType'(A, NULL) ;
elsif A = HeadPointer.A then -- ignore duplicates
if AllowDuplicate then
tempPtr := HeadPointer ;
HeadPointer := new ListType'(A, tempPtr) ;
end if ;
elsif A < HeadPointer.A then
tempPtr := HeadPointer ;
HeadPointer := new ListType'(A, tempPtr) ;
else
CurPtr := HeadPointer ;
AddLoop : loop
exit AddLoop when CurPtr.NextPtr = NULL ;
exit AddLoop when A < CurPtr.NextPtr.A ;
if A = CurPtr.NextPtr.A then
-- if AllowDuplicate then -- changed s.t. insert at after match rather than before
-- exit AddLoop ; -- insert
-- else
if not AllowDuplicate then
return ; -- return without insert
end if;
end if ;
CurPtr := CurPtr.NextPtr ;
end loop AddLoop ;
tempPtr := CurPtr.NextPtr ;
CurPtr.NextPtr := new ListType'(A, tempPtr) ;
end if ;
end procedure add ;
procedure add ( constant A : in ArrayofElementType ) is
begin
for i in A'range loop
add(A(i)) ;
end loop ;
end procedure add ;
procedure add ( constant A : in ArrayofElementType ; Min, Max : ElementType ) is
begin
for i in A'range loop
if A(i) >= Min and A(i) <= Max then
add(A(i)) ;
end if ;
end loop ;
end procedure add ;
procedure add ( variable A : inout SortListPType ) is
begin
for i in 1 to A.Count loop
add(A.Get(i)) ;
end loop ;
end procedure add ;
-- Count items in list
impure function count return integer is
variable result : positive := 1 ;
variable CurPtr : ListPointerType ;
begin
if HeadPointer = NULL then
return 0 ;
else
CurPtr := HeadPointer ;
loop
exit when CurPtr.NextPtr = NULL ;
result := result + 1 ;
CurPtr := CurPtr.NextPtr ;
end loop ;
return result ;
end if ;
end function count ;
impure function find_index (constant A : ElementType) return integer is
variable result : positive := 2 ;
variable CurPtr : ListPointerType ;
begin
if HeadPointer = NULL then
return 0 ;
elsif A <= HeadPointer.A then
return 1 ;
else
CurPtr := HeadPointer ;
loop
exit when CurPtr.NextPtr = NULL ;
exit when A <= CurPtr.NextPtr.A ;
result := result + 1 ;
CurPtr := CurPtr.NextPtr ;
end loop ;
return result ;
end if ;
end function find_index ;
impure function inside (constant A : ElementType) return boolean is
variable CurPtr : ListPointerType ;
begin
if HeadPointer = NULL then
return FALSE ;
end if ;
if A = HeadPointer.A then
return TRUE ;
else
CurPtr := HeadPointer ;
loop
exit when CurPtr.NextPtr = NULL ;
exit when A < CurPtr.NextPtr.A ;
if A = CurPtr.NextPtr.A then
return TRUE ; -- exit
end if;
CurPtr := CurPtr.NextPtr ;
end loop ;
end if ;
return FALSE ;
end function inside ;
procedure insert( constant A : in ElementType; constant index : in integer := 1 ) is
variable CurPtr, tempPtr : ListPointerType ;
begin
if index <= 1 then
tempPtr := HeadPointer ;
HeadPointer := new ListType'(A, tempPtr) ;
else
CurPtr := HeadPointer ;
for i in 3 to index loop
exit when CurPtr.NextPtr = NULL ; -- end of list
CurPtr := CurPtr.NextPtr ;
end loop ;
tempPtr := CurPtr.NextPtr ;
CurPtr.NextPtr := new ListType'(A, tempPtr) ;
end if;
end procedure insert ;
impure function get ( constant index : in integer := 1 ) return ElementType is
variable CurPtr : ListPointerType ;
begin
if index > Count then
Alert(OSVVM_ALERTLOG_ID, "SortLIstPkg_int.get index out of range", FAILURE) ;
return ElementType'left ;
elsif HeadPointer = NULL then
return ElementType'left ;
elsif index <= 1 then
return HeadPointer.A ;
else
CurPtr := HeadPointer ;
for i in 2 to index loop
CurPtr := CurPtr.NextPtr ;
end loop ;
return CurPtr.A ;
end if;
end function get ;
procedure erase (variable CurPtr : inout ListPointerType ) is
begin
if CurPtr.NextPtr /= NULL then
erase (CurPtr.NextPtr) ;
end if ;
deallocate (CurPtr) ;
end procedure erase ;
procedure erase is
begin
if HeadPointer /= NULL then
erase(HeadPointer) ;
-- deallocate (HeadPointer) ;
HeadPointer := NULL ;
end if;
end procedure erase ;
impure function Empty return boolean is
begin
return HeadPointer = NULL ;
end Empty ;
procedure print is
variable buf : line ;
variable CurPtr : ListPointerType ;
begin
if HeadPointer = NULL then
write (buf, string'("( )")) ;
else
CurPtr := HeadPointer ;
write (buf, string'("(")) ;
loop
write (buf, CurPtr.A) ;
exit when CurPtr.NextPtr = NULL ;
write (buf, string'(", ")) ;
CurPtr := CurPtr.NextPtr ;
end loop ;
write (buf, string'(")")) ;
end if ;
writeline(OUTPUT, buf) ;
end procedure print ;
procedure remove ( constant A : in ElementType ) is
variable CurPtr, tempPtr : ListPointerType ;
begin
if HeadPointer = NULL then
return ;
elsif A = HeadPointer.A then
tempPtr := HeadPointer ;
HeadPointer := HeadPointer.NextPtr ;
deallocate (tempPtr) ;
else
CurPtr := HeadPointer ;
loop
exit when CurPtr.NextPtr = NULL ;
if A = CurPtr.NextPtr.A then
tempPtr := CurPtr.NextPtr ;
CurPtr.NextPtr := CurPtr.NextPtr.NextPtr ;
deallocate (tempPtr) ;
exit ;
end if ;
exit when A < CurPtr.NextPtr.A ;
CurPtr := CurPtr.NextPtr ;
end loop ;
end if ;
end procedure remove ;
procedure remove ( constant A : in ArrayofElementType ) is
begin
for i in A'range loop
remove(A(i)) ;
end loop ;
end procedure remove ;
procedure remove ( variable A : inout SortListPType ) is
begin
for i in 1 to A.Count loop
remove(A.Get(i)) ;
end loop ;
end procedure remove ;
impure function to_array (constant EraseList : boolean := FALSE) return ArrayofElementType is
variable result : ArrayofElementType(1 to Count) ;
begin
for i in 1 to Count loop
result(i) := Get(i) ;
end loop ;
if EraseList then
erase ;
end if ;
return result ;
end function to_array ;
impure function to_rev_array (constant EraseList : boolean := FALSE) return ArrayofElementType is
variable result : ArrayofElementType(Count downto 1) ;
begin
for i in 1 to Count loop
result(i) := Get(i) ;
end loop ;
if EraseList then
erase ;
end if ;
return result ;
end function to_rev_array ;
end protected body SortListPType ;
impure function sort (constant A : in ArrayofElementType) return ArrayofElementType is
variable Result : SortListPType ;
begin
for i in A'range loop
Result.Add(A(i), TRUE) ;
end loop ;
return Result.to_array(EraseList => TRUE) ;
end function sort ;
impure function revsort (constant A : in ArrayofElementType) return ArrayofElementType is
variable Result : SortListPType ;
begin
for i in A'range loop
Result.Add(A(i), TRUE) ;
end loop ;
return Result.to_rev_array(EraseList => TRUE) ;
end function revsort ;
end SortListPkg_int ;
|
--
-- File Name: SortListPkg_int.vhd
-- Design Unit Name: SortListPkg_int
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis [email protected]
--
-- Description:
-- Sorting utility for array of scalars
-- Uses protected type so as to shrink and expand the data structure
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 06/2008: 0.1 Initial revision
-- Numerous revisions for VHDL Testbenches and Verification
-- 02/2009: 1.0 First Public Released Version
-- 02/25/2009 1.1 Replaced reference to std_2008 with a reference to
-- ieee_proposed.standard_additions.all ;
-- 06/16/2010 1.2 Added EraseList parameter to to_array
-- 3/2011 2.0 added inside as non protected type
-- 6/2011 2.1 added sort as non protected type
-- 4/2013 2013.04 No Changes
-- 5/2013 2013.05 No changes of substance.
-- Deleted extra variable declaration in procedure remove
-- 1/2014 2014.01 Added RevSort. Added AllowDuplicate paramter to Add procedure
-- 1/2015 2015.01 Changed Assert/Report to Alert
-- 11/2016 2016.11 Revised Add. When AllowDuplicate, add a matching value last.
-- 01/2020 2020.01 Updated Licenses to Apache
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2008 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use work.OsvvmGlobalPkg.all ;
use work.AlertLogPkg.all ;
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.std_logic_textio.all ;
-- comment out following 2 lines with VHDL-2008. Leave in for VHDL-2002
-- library ieee_proposed ; -- remove with VHDL-2008
-- use ieee_proposed.standard_additions.all ; -- remove with VHDL-2008
package SortListPkg_int is
-- with VHDL-2008, convert package to generic package
-- convert subtypes ElementType and ArrayofElementType to generics
-- package SortListGenericPkg is
subtype ElementType is integer ;
subtype ArrayofElementType is integer_vector ;
impure function inside (constant E : ElementType; constant A : in ArrayofElementType) return boolean ;
impure function sort (constant A : in ArrayofElementType) return ArrayofElementType ;
impure function revsort (constant A : in ArrayofElementType) return ArrayofElementType ;
type SortListPType is protected
procedure add ( constant A : in ElementType ; constant AllowDuplicate : Boolean := FALSE ) ;
procedure add ( constant A : in ArrayofElementType ) ;
procedure add ( constant A : in ArrayofElementType ; Min, Max : ElementType ) ;
procedure add ( variable A : inout SortListPType ) ;
-- Count items in list
impure function count return integer ;
impure function find_index ( constant A : ElementType) return integer ;
impure function inside (constant A : ElementType) return boolean ;
procedure insert ( constant A : in ElementType; constant index : in integer := 1 ) ;
impure function get ( constant index : in integer := 1 ) return ElementType ;
procedure erase ;
impure function Empty return boolean ;
procedure print ;
procedure remove ( constant A : in ElementType ) ;
procedure remove ( constant A : in ArrayofElementType ) ;
procedure remove ( variable A : inout SortListPType ) ;
impure function to_array (constant EraseList : boolean := FALSE) return ArrayofElementType ;
impure function to_rev_array (constant EraseList : boolean := FALSE) return ArrayofElementType ;
end protected SortListPType ;
end SortListPkg_int ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body SortListPkg_int is
impure function inside (constant E : ElementType; constant A : in ArrayofElementType) return boolean is
begin
for i in A'range loop
if E = A(i) then
return TRUE ;
end if ;
end loop ;
return FALSE ;
end function inside ;
type SortListPType is protected body
type ListType ;
type ListPointerType is access ListType ;
type ListType is record
A : ElementType ;
-- item_num : integer ;
NextPtr : ListPointerType ;
-- PrevPtr : ListPointerType ;
end record ;
variable HeadPointer : ListPointerType := NULL ;
-- variable TailPointer : ListPointerType := NULL ;
procedure add ( constant A : in ElementType ; constant AllowDuplicate : Boolean := FALSE ) is
variable CurPtr, tempPtr : ListPointerType ;
begin
if HeadPointer = NULL then
HeadPointer := new ListType'(A, NULL) ;
elsif A = HeadPointer.A then -- ignore duplicates
if AllowDuplicate then
tempPtr := HeadPointer ;
HeadPointer := new ListType'(A, tempPtr) ;
end if ;
elsif A < HeadPointer.A then
tempPtr := HeadPointer ;
HeadPointer := new ListType'(A, tempPtr) ;
else
CurPtr := HeadPointer ;
AddLoop : loop
exit AddLoop when CurPtr.NextPtr = NULL ;
exit AddLoop when A < CurPtr.NextPtr.A ;
if A = CurPtr.NextPtr.A then
-- if AllowDuplicate then -- changed s.t. insert at after match rather than before
-- exit AddLoop ; -- insert
-- else
if not AllowDuplicate then
return ; -- return without insert
end if;
end if ;
CurPtr := CurPtr.NextPtr ;
end loop AddLoop ;
tempPtr := CurPtr.NextPtr ;
CurPtr.NextPtr := new ListType'(A, tempPtr) ;
end if ;
end procedure add ;
procedure add ( constant A : in ArrayofElementType ) is
begin
for i in A'range loop
add(A(i)) ;
end loop ;
end procedure add ;
procedure add ( constant A : in ArrayofElementType ; Min, Max : ElementType ) is
begin
for i in A'range loop
if A(i) >= Min and A(i) <= Max then
add(A(i)) ;
end if ;
end loop ;
end procedure add ;
procedure add ( variable A : inout SortListPType ) is
begin
for i in 1 to A.Count loop
add(A.Get(i)) ;
end loop ;
end procedure add ;
-- Count items in list
impure function count return integer is
variable result : positive := 1 ;
variable CurPtr : ListPointerType ;
begin
if HeadPointer = NULL then
return 0 ;
else
CurPtr := HeadPointer ;
loop
exit when CurPtr.NextPtr = NULL ;
result := result + 1 ;
CurPtr := CurPtr.NextPtr ;
end loop ;
return result ;
end if ;
end function count ;
impure function find_index (constant A : ElementType) return integer is
variable result : positive := 2 ;
variable CurPtr : ListPointerType ;
begin
if HeadPointer = NULL then
return 0 ;
elsif A <= HeadPointer.A then
return 1 ;
else
CurPtr := HeadPointer ;
loop
exit when CurPtr.NextPtr = NULL ;
exit when A <= CurPtr.NextPtr.A ;
result := result + 1 ;
CurPtr := CurPtr.NextPtr ;
end loop ;
return result ;
end if ;
end function find_index ;
impure function inside (constant A : ElementType) return boolean is
variable CurPtr : ListPointerType ;
begin
if HeadPointer = NULL then
return FALSE ;
end if ;
if A = HeadPointer.A then
return TRUE ;
else
CurPtr := HeadPointer ;
loop
exit when CurPtr.NextPtr = NULL ;
exit when A < CurPtr.NextPtr.A ;
if A = CurPtr.NextPtr.A then
return TRUE ; -- exit
end if;
CurPtr := CurPtr.NextPtr ;
end loop ;
end if ;
return FALSE ;
end function inside ;
procedure insert( constant A : in ElementType; constant index : in integer := 1 ) is
variable CurPtr, tempPtr : ListPointerType ;
begin
if index <= 1 then
tempPtr := HeadPointer ;
HeadPointer := new ListType'(A, tempPtr) ;
else
CurPtr := HeadPointer ;
for i in 3 to index loop
exit when CurPtr.NextPtr = NULL ; -- end of list
CurPtr := CurPtr.NextPtr ;
end loop ;
tempPtr := CurPtr.NextPtr ;
CurPtr.NextPtr := new ListType'(A, tempPtr) ;
end if;
end procedure insert ;
impure function get ( constant index : in integer := 1 ) return ElementType is
variable CurPtr : ListPointerType ;
begin
if index > Count then
Alert(OSVVM_ALERTLOG_ID, "SortLIstPkg_int.get index out of range", FAILURE) ;
return ElementType'left ;
elsif HeadPointer = NULL then
return ElementType'left ;
elsif index <= 1 then
return HeadPointer.A ;
else
CurPtr := HeadPointer ;
for i in 2 to index loop
CurPtr := CurPtr.NextPtr ;
end loop ;
return CurPtr.A ;
end if;
end function get ;
procedure erase (variable CurPtr : inout ListPointerType ) is
begin
if CurPtr.NextPtr /= NULL then
erase (CurPtr.NextPtr) ;
end if ;
deallocate (CurPtr) ;
end procedure erase ;
procedure erase is
begin
if HeadPointer /= NULL then
erase(HeadPointer) ;
-- deallocate (HeadPointer) ;
HeadPointer := NULL ;
end if;
end procedure erase ;
impure function Empty return boolean is
begin
return HeadPointer = NULL ;
end Empty ;
procedure print is
variable buf : line ;
variable CurPtr : ListPointerType ;
begin
if HeadPointer = NULL then
write (buf, string'("( )")) ;
else
CurPtr := HeadPointer ;
write (buf, string'("(")) ;
loop
write (buf, CurPtr.A) ;
exit when CurPtr.NextPtr = NULL ;
write (buf, string'(", ")) ;
CurPtr := CurPtr.NextPtr ;
end loop ;
write (buf, string'(")")) ;
end if ;
writeline(OUTPUT, buf) ;
end procedure print ;
procedure remove ( constant A : in ElementType ) is
variable CurPtr, tempPtr : ListPointerType ;
begin
if HeadPointer = NULL then
return ;
elsif A = HeadPointer.A then
tempPtr := HeadPointer ;
HeadPointer := HeadPointer.NextPtr ;
deallocate (tempPtr) ;
else
CurPtr := HeadPointer ;
loop
exit when CurPtr.NextPtr = NULL ;
if A = CurPtr.NextPtr.A then
tempPtr := CurPtr.NextPtr ;
CurPtr.NextPtr := CurPtr.NextPtr.NextPtr ;
deallocate (tempPtr) ;
exit ;
end if ;
exit when A < CurPtr.NextPtr.A ;
CurPtr := CurPtr.NextPtr ;
end loop ;
end if ;
end procedure remove ;
procedure remove ( constant A : in ArrayofElementType ) is
begin
for i in A'range loop
remove(A(i)) ;
end loop ;
end procedure remove ;
procedure remove ( variable A : inout SortListPType ) is
begin
for i in 1 to A.Count loop
remove(A.Get(i)) ;
end loop ;
end procedure remove ;
impure function to_array (constant EraseList : boolean := FALSE) return ArrayofElementType is
variable result : ArrayofElementType(1 to Count) ;
begin
for i in 1 to Count loop
result(i) := Get(i) ;
end loop ;
if EraseList then
erase ;
end if ;
return result ;
end function to_array ;
impure function to_rev_array (constant EraseList : boolean := FALSE) return ArrayofElementType is
variable result : ArrayofElementType(Count downto 1) ;
begin
for i in 1 to Count loop
result(i) := Get(i) ;
end loop ;
if EraseList then
erase ;
end if ;
return result ;
end function to_rev_array ;
end protected body SortListPType ;
impure function sort (constant A : in ArrayofElementType) return ArrayofElementType is
variable Result : SortListPType ;
begin
for i in A'range loop
Result.Add(A(i), TRUE) ;
end loop ;
return Result.to_array(EraseList => TRUE) ;
end function sort ;
impure function revsort (constant A : in ArrayofElementType) return ArrayofElementType is
variable Result : SortListPType ;
begin
for i in A'range loop
Result.Add(A(i), TRUE) ;
end loop ;
return Result.to_rev_array(EraseList => TRUE) ;
end function revsort ;
end SortListPkg_int ;
|
-- https://www.ics.uci.edu/~jmoorkan/vhdlref/Synario%20VHDL%20Manual.pdf
entity logical_ops_1 is
port (a, b, c, d: in bit;
m: out bit);
end logical_ops_1;
|
-- https://www.ics.uci.edu/~jmoorkan/vhdlref/Synario%20VHDL%20Manual.pdf
entity logical_ops_1 is
port (a, b, c, d: in bit;
m: out bit);
end logical_ops_1;
|
-- https://www.ics.uci.edu/~jmoorkan/vhdlref/Synario%20VHDL%20Manual.pdf
entity logical_ops_1 is
port (a, b, c, d: in bit;
m: out bit);
end logical_ops_1;
|
-- https://www.ics.uci.edu/~jmoorkan/vhdlref/Synario%20VHDL%20Manual.pdf
entity logical_ops_1 is
port (a, b, c, d: in bit;
m: out bit);
end logical_ops_1;
|
-- https://www.ics.uci.edu/~jmoorkan/vhdlref/Synario%20VHDL%20Manual.pdf
entity logical_ops_1 is
port (a, b, c, d: in bit;
m: out bit);
end logical_ops_1;
|
-- https://www.ics.uci.edu/~jmoorkan/vhdlref/Synario%20VHDL%20Manual.pdf
entity logical_ops_1 is
port (a, b, c, d: in bit;
m: out bit);
end logical_ops_1;
|
-- https://www.ics.uci.edu/~jmoorkan/vhdlref/Synario%20VHDL%20Manual.pdf
entity logical_ops_1 is
port (a, b, c, d: in bit;
m: out bit);
end logical_ops_1;
|
---------------------------------------------------------------------------------
--Project Test Bench------------------------------------------------------------
--By Kyle Williams, 04/07/2011--------------------------------------------------
--PROJECT DESCRIPTION------------------------------------------------------------
--1--Input Serial data stream----------------------------------------------------
--2--Detect a start of Frame whose pattern is 10101011----------------------------
--3--After frame detect take every 8 bits and store them in a ram----------------
--4--After 8 bytes have been written in the ram start reading the data from the ram
--5--check that data read from ram matches what was written in the ram-----------
---------------------------------------------------------------------------------
----------------Define Libraries to be used--------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
-----------------ENTITY FOR TEST BENCH------------------------------------------
ENTITY tb_ramIntro IS
GENERIC ( bits : INTEGER := 8); -- # of bits per word
END tb_ramIntro;
-----------------BEHAVIOR OF TEST BENCH-----------------------------------------
ARCHITECTURE tb_ramIntro of tb_ramIntro IS
-----------------COMPONENT INITIALIZATIONS--------------------------------------
COMPONENT generator
Generic(N : Integer := 8);
PORT(
clock, reset, load: OUT std_logic;
D : OUT std_logic_vector(n-1 downto 0);
vec : OUT std_logic_vector(N-1 downto 0);
sin : OUT STD_Logic
);
END COMPONENT;
COMPONENT receiver
PORT ( reset : IN STD_Logic;
clock : IN STD_LOGIC;
rec_in : IN STD_LOGIC;
enable : OUT STD_LOGIC;
rec_out : OUT STD_LOGIC_VECTOR (bits -1 DOWNTO 0)
);
End COMPONENT;
COMPONENT ramController
PORT ( reset : IN STD_Logic;
clock : IN STD_LOGIC;
enable : IN STD_LOGIC;
ctrl_in : IN STD_LOGIC_VECTOR (bits - 1 DOWNTO 0);
addr : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
wr_ena : OUT STD_LOGIC; -- write enable
ctrl_out : OUT STD_LOGIC_VECTOR (bits -1 DOWNTO 0)
);
End COMPONENT;
COMPONENT ram
PORT ( wr_ena : IN STD_LOGIC; -- write enable
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
addr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
ram_in : IN STD_LOGIC_VECTOR (bits - 1 DOWNTO 0);
ram_out : OUT STD_LOGIC_VECTOR (bits -1 DOWNTO 0)
);
End COMPONENT;
COMPONENT dataValidation
PORT ( reset : IN STD_Logic;
clock : IN STD_LOGIC;
wr_ena : IN STD_LOGIC; -- write enable
enable : IN STD_LOGIC;
ctrl_out : IN STD_LOGIC_VECTOR (bits -1 DOWNTO 0);
ram_out : IN STD_LOGIC_VECTOR (bits -1 DOWNTO 0);
data_Valid : OUT STD_LOGIC;
validOffset : OUT Integer
);
End COMPONENT;
-------------------VARIABLE DECLARATION----------------------------------------
Signal clock : STD_LOGIC;
Signal reset : STD_LOGIC;
Signal load : STD_LOGIC;
Signal sin : STD_LOGIC;
Signal wr_enable : STD_LOGIC;
Signal enable : STD_LOGIC;
Signal data_Valid : STD_LOGIC;
Signal address : STD_LOGIC_VECTOR(5 DOWNTO 0);--2^6 bit address 64 possible locations
Signal D : STD_LOGIC_VECTOR(bits-1 Downto 0);
Signal rec_out : STD_LOGIC_VECTOR(bits-1 DOWNTO 0);
Signal ctrl_out : STD_LOGIC_VECTOR(bits-1 DOWNTO 0);
Signal ram_out : STD_LOGIC_VECTOR(bits-1 DOWNTO 0);
Signal validOffset : Integer;
-------------------BEGINING OF INSTRUCTIONS-----------------------------------
BEGIN
-------------------VARIABLE DECLARATIONS--------------------------------------
Gen: generator
PORT Map (sin=>sin, clock => clock, reset => reset, load => load);
recMod:receiver
PORT MAP( reset => reset, clock => clock, enable=>enable,rec_in => sin, rec_out => rec_out);
ctrlMod:ramController
PORT MAP( reset=> reset,clock => clock,enable=>enable,ctrl_in => rec_out,addr=> address,wr_ena=>wr_enable,ctrl_out => ctrl_out);
SRAM:ram
PORT MAP( wr_ena=>wr_enable,clock=>clock,reset=>reset,addr=>address,ram_in=>ctrl_out,ram_out=>ram_out);
valid:dataValidation
PORT MAP(reset=>reset,clock=>clock,wr_ena=>wr_enable,enable=>enable,ctrl_out=>ctrl_out,
ram_out=>ram_out,data_Valid=>data_Valid,validOffset=>validOffset);
-------------------ADDITIONAL INSTRUCTIONS--------------------------------------
--look into tb_ram_demo so you can add a check
END tb_ramIntro;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: axi_master_burst_rd_wr_cntlr.vhd
--
-- Description:
-- This file implements the DataMover MM2S Full Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_master_burst.vhd
-- |
-- |-- proc_common_v4_0 (helper library)
-- |
-- |-- axi_master_burst_reset.vhd
-- |
-- |-- axi_master_rd_llink.vhd
-- |
-- |-- axi_master_wr_llink.vhd
-- |
-- |
-- |-- axi_master_burst_cmd_status.vhd
-- | |-- axi_master_burst_first_stb_offset.vhd
-- | |-- axi_master_burst_stbs_set.vhd
-- |
-- |-- axi_master_burst_rd_wr_cntlr.vhd
-- |-- axi_master_burst_pcc.vhd
-- | |-- axi_master_burst_strb_gen.vhd
-- |-- axi_master_burst_addr_cntl.vhd
-- |-- axi_master_burst_rddata_cntl.vhd
-- |-- axi_master_burst_wrdata_cntl.vhd
-- |-- axi_master_burst_rd_status_cntl.vhd
-- |-- axi_master_burst_wr_status_cntl.vhd
-- |-- axi_master_burst_skid_buf.vhd
-- |-- axi_master_burst_skid2mm_buf.vhd
--
--
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.0 $
-- Date: $01/18/2011$
--
-- History:
-- DET 01/18/2011 Initial Version
--
-- DET 2/10/2011 Initial for EDk 13.2
-- ~~~~~~
-- -- Per CR593239
-- - Added Min BTT width correction logic (adapted from Datamover)
-- ^^^^^^
-- DET 2/10/2011 Initial for EDK 13.2
-- ~~~~~~
-- - Updated the Addr Cntlr Instance with new ports for avalid
-- registering. Cleaned up a*valid signal generation.
-- - Added missing port mstr2dre_cmd_cmplt to the PCC instance
-- ^^^^^^
--
-- DET 2/15/2011 Initial for EDk 13.2
-- ~~~~~~
-- -- Per CR593812
-- - Modifications to remove unused features to improve Code coverage.
-- Used "-- coverage off" and "-- coverage on" strings.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI MASTER BURST to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_master_burst Library Modules
library axi_master_burst_v2_0 ;
use axi_master_burst_v2_0.axi_master_burst_pcc ;
use axi_master_burst_v2_0.axi_master_burst_addr_cntl ;
use axi_master_burst_v2_0.axi_master_burst_rddata_cntl ;
use axi_master_burst_v2_0.axi_master_burst_wrdata_cntl ;
use axi_master_burst_v2_0.axi_master_burst_rd_status_cntl;
use axi_master_burst_v2_0.axi_master_burst_wr_status_cntl;
use axi_master_burst_v2_0.axi_master_burst_skid_buf ;
use axi_master_burst_v2_0.axi_master_burst_skid2mm_buf ;
-------------------------------------------------------------------------------
entity axi_master_burst_rd_wr_cntlr is
generic (
C_RDWR_ARID : Integer range 0 to 255 := 0;
-- Specifies the constant value to output on
-- the ARID output port
C_RDWR_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_RDWR_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_RDWR_MDATA_WIDTH : Integer range 32 to 256 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_RDWR_SDATA_WIDTH : Integer range 8 to 256 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_RDWR_MAX_BURST_LEN : Integer range 16 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_RDWR_BTT_USED : Integer range 8 to 23 := 12;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_RDWR_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 2;
-- This parameter specifies the depth of the RDWR internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_RDWR_PCC_CMD_WIDTH : Integer range 68 to 68 := 68;
-- Specifies the width of the PCC Command input
C_RDWR_STATUS_WIDTH : Integer range 8 to 8 := 8;
-- Specifies the width of the Status Output bus
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-------------------------------------------------------------------------
-- RDWR Primary Clock input
-------------------------------------------------------------------------
rdwr_aclk : in std_logic;
-- Primary synchronization clock for the Master side
-- interface and internal logic. It is also used
-- for the User interface synchronization when
-- C_STSCMD_IS_ASYNC = 0.
-------------------------------------------------------------------------
-- RDWR Primary Reset input
-------------------------------------------------------------------------
rdwr_areset : in std_logic;
-- Reset used for the internal master logic
-------------------------------------------------------------------------
-- RDWR Master detected Error Output Discrete
-------------------------------------------------------------------------
rdwr_md_error : out std_logic;
-- Master detected error output (acive high)
-------------------------------------------------------------------------
-- Command/Status Module PCC Command Interface (AXI Stream Like)
-------------------------------------------------------------------------
cmd2rdwr_cmd_valid : in std_logic; -- Command IF
rdwr2cmd_cmd_ready : out std_logic; -- Command IF
cmd2rdwr_cmd_data : in std_logic_vector(C_RDWR_PCC_CMD_WIDTH-1 downto 0); -- Command IF
-------------------------------------------------------------------------
-- Command/Status Module Type Interface
-------------------------------------------------------------------------
cmd2rdwr_doing_read : in std_logic; -- Read Active Discrete
cmd2rdwr_doing_write : in std_logic; -- Write Active Discrete
-------------------------------------------------------------------------
-- Command/Status Module Read Status Ports (AXI Stream Like)
-------------------------------------------------------------------------
stat2rsc_status_ready : in std_logic; -- Read Status
rsc2stat_status_valid : out std_logic; -- Read Status
rsc2stat_status : out std_logic_vector(C_RDWR_STATUS_WIDTH-1 downto 0); -- Read Status
-------------------------------------------------------------------------
-- Command/Status Module Write Status Ports (AXI Stream Like)
-------------------------------------------------------------------------
stat2wsc_status_ready : in std_logic; -- Write Status
wsc2stat_status_valid : out std_logic; -- Write Status
wsc2stat_status : out std_logic_vector(C_RDWR_STATUS_WIDTH-1 downto 0); -- Write Status
-------------------------------------------------------------------------
-- LocalLink Enable Outputs (1 clock pulse)
-------------------------------------------------------------------------
rd_llink_enable : out std_logic; -- Read LLink Enable
wr_llink_enable : out std_logic; -- Write LLink Enable
-------------------------------------------------------------------------
-- Read Address Posting Contols/Status
-------------------------------------------------------------------------
rd_allow_addr_req : in std_logic; -- Read Address Posting
rd_addr_req_posted : out std_logic; -- Read Address Posting
rd_xfer_cmplt : out std_logic; -- Read Address Posting
-------------------------------------------------------------------------
-- Write Address Posting Contols/Status
-------------------------------------------------------------------------
wr_allow_addr_req : in std_logic; -- Write Address Posting
wr_addr_req_posted : out std_logic; -- Write Address Posting
wr_xfer_cmplt : out std_logic; -- Write Address Posting
-------------------------------------------------------------------------
-- AXI Read Address Channel I/O
-------------------------------------------------------------------------
rd_arid : out std_logic_vector(C_RDWR_ID_WIDTH-1 downto 0); -- AXI4
rd_araddr : out std_logic_vector(C_RDWR_ADDR_WIDTH-1 downto 0); -- AXI4
rd_arlen : out std_logic_vector(7 downto 0); -- AXI4
rd_arsize : out std_logic_vector(2 downto 0); -- AXI4
rd_arburst : out std_logic_vector(1 downto 0); -- AXI4
rd_arprot : out std_logic_vector(2 downto 0); -- AXI4
rd_arcache : out std_logic_vector(3 downto 0); -- AXI4
rd_arvalid : out std_logic; -- AXI4
rd_arready : in std_logic; -- AXI4
-------------------------------------------------------------------------
-- AXI Read Data Channel I/O
-------------------------------------------------------------------------
rd_rdata : In std_logic_vector(C_RDWR_MDATA_WIDTH-1 downto 0); -- AXI4
rd_rresp : In std_logic_vector(1 downto 0); -- AXI4
rd_rlast : In std_logic; -- AXI4
rd_rvalid : In std_logic; -- AXI4
rd_rready : Out std_logic; -- AXI4
-------------------------------------------------------------------------
-- AXI Read Master Stream Channel I/O
------------------------------------------------------------------------- -- AXI4 Stream
rd_strm_tdata : Out std_logic_vector(C_RDWR_SDATA_WIDTH-1 downto 0); -- AXI4 Stream
rd_strm_tstrb : Out std_logic_vector((C_RDWR_SDATA_WIDTH/8)-1 downto 0);-- AXI4 Stream
rd_strm_tlast : Out std_logic; -- AXI4 Stream
rd_strm_tvalid : Out std_logic; -- AXI4 Stream
rd_strm_tready : In std_logic; -- AXI4 Stream
-------------------------------------------------------------------------
-- AXI Write Address Channel I/O
-------------------------------------------------------------------------
wr_awid : out std_logic_vector(C_RDWR_ID_WIDTH-1 downto 0); -- AXI4
wr_awaddr : out std_logic_vector(C_RDWR_ADDR_WIDTH-1 downto 0); -- AXI4
wr_awlen : out std_logic_vector(7 downto 0); -- AXI4
wr_awsize : out std_logic_vector(2 downto 0); -- AXI4
wr_awburst : out std_logic_vector(1 downto 0); -- AXI4
wr_awprot : out std_logic_vector(2 downto 0); -- AXI4
wr_awcache : out std_logic_vector(3 downto 0); -- AXI4
wr_awvalid : out std_logic; -- AXI4
wr_awready : in std_logic; -- AXI4
-------------------------------------------------------------------------
-- RDWR AXI Write Data Channel I/O
-------------------------------------------------------------------------
wr_wdata : Out std_logic_vector(C_RDWR_MDATA_WIDTH-1 downto 0); -- AXI4
wr_wstrb : Out std_logic_vector((C_RDWR_MDATA_WIDTH/8)-1 downto 0); -- AXI4
wr_wlast : Out std_logic; -- AXI4
wr_wvalid : Out std_logic; -- AXI4
wr_wready : In std_logic; -- AXI4
-------------------------------------------------------------------------
-- RDWR AXI Write response Channel I/O
-------------------------------------------------------------------------
wr_bresp : In std_logic_vector(1 downto 0); -- AXI4
wr_bvalid : In std_logic; -- AXI4
wr_bready : Out std_logic; -- AXI4
-------------------------------------------------------------------------
-- RDWR AXI Slave Stream Channel I/O
-------------------------------------------------------------------------
wr_strm_tdata : In std_logic_vector(C_RDWR_SDATA_WIDTH-1 downto 0); -- AXI4 Stream
wr_strm_tstrb : In std_logic_vector((C_RDWR_SDATA_WIDTH/8)-1 downto 0); -- AXI4 Stream
wr_strm_tlast : In std_logic; -- AXI4 Stream
wr_strm_tvalid : In std_logic; -- AXI4 Stream
wr_strm_tready : Out std_logic -- AXI4 Stream
);
end entity axi_master_burst_rd_wr_cntlr;
architecture implementation of axi_master_burst_rd_wr_cntlr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_min_btt_width
--
-- Function Description:
-- This function calculates the minimum required value
-- for the used width of the command BTT field.
--
-------------------------------------------------------------------
function funct_get_min_btt_width (max_burst_beats : integer;
bytes_per_beat : integer ) return integer is
Variable var_min_btt_needed : Integer;
Variable var_max_bytes_per_burst : Integer;
begin
var_max_bytes_per_burst := max_burst_beats*bytes_per_beat;
-- coverage off
if (var_max_bytes_per_burst <= 16) then
var_min_btt_needed := 5;
elsif (var_max_bytes_per_burst <= 32) then
var_min_btt_needed := 6;
-- coverage on
elsif (var_max_bytes_per_burst <= 64) then
var_min_btt_needed := 7;
elsif (var_max_bytes_per_burst <= 128) then
var_min_btt_needed := 8;
elsif (var_max_bytes_per_burst <= 256) then
var_min_btt_needed := 9;
elsif (var_max_bytes_per_burst <= 512) then
var_min_btt_needed := 10;
elsif (var_max_bytes_per_burst <= 1024) then
var_min_btt_needed := 11;
elsif (var_max_bytes_per_burst <= 2048) then
var_min_btt_needed := 12;
elsif (var_max_bytes_per_burst <= 4096) then
var_min_btt_needed := 13;
-- coverage off
else -- 8K byte range
var_min_btt_needed := 14;
-- coverage on
end if;
Return (var_min_btt_needed);
end function funct_get_min_btt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_btt_used
--
-- Function Description:
-- THis function makes sure the BTT width used is at least the
-- minimum needed.
--
-------------------------------------------------------------------
function funct_fix_btt_used (requested_btt_width : integer;
min_btt_width : integer) return integer is
Variable var_corrected_btt_width : Integer;
begin
If (requested_btt_width < min_btt_width) Then
var_corrected_btt_width := min_btt_width;
else
var_corrected_btt_width := requested_btt_width;
End if;
Return (var_corrected_btt_width);
end function funct_fix_btt_used;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant RDWR_ARID_VALUE : integer range 0 to 255 := C_RDWR_ARID;
Constant RDWR_ARID_WIDTH : integer range 1 to 8 := C_RDWR_ID_WIDTH;
Constant RDWR_ADDR_WIDTH : integer range 32 to 64 := C_RDWR_ADDR_WIDTH;
Constant RDWR_MDATA_WIDTH : integer range 32 to 256 := C_RDWR_MDATA_WIDTH;
Constant RDWR_SDATA_WIDTH : integer range 8 to 256 := C_RDWR_SDATA_WIDTH;
Constant BASE_PCC_CMD_WIDTH : integer := 64;
Constant RDWR_TAG_WIDTH : integer range 1 to 8 := C_RDWR_PCC_CMD_WIDTH-BASE_PCC_CMD_WIDTH;
Constant RDWR_CMD_WIDTH : integer := C_RDWR_PCC_CMD_WIDTH;
Constant RDWR_STS_WIDTH : integer := C_RDWR_STATUS_WIDTH;
Constant INCLUDE_RDWR_STSFIFO : integer range 0 to 1 := 1;
Constant RDWR_STSCMD_FIFO_DEPTH : integer range 1 to 16 := 1;
Constant RDWR_STSCMD_IS_ASYNC : integer range 0 to 1 := 0;
Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_RDWR_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_RDWR_ADDR_PIPE_DEPTH;
Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_RDWR_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer range 2 to 5 := func_calc_rdmux_sel_bits(RDWR_MDATA_WIDTH);
Constant RDWR_BTT_USED : integer range 8 to 23 := C_RDWR_BTT_USED;
Constant RDWR_MAX_BURST_LEN : integer range 16 to 256 := C_RDWR_MAX_BURST_LEN;
Constant RDWR_BYTES_PER_BEAT : integer range 4 to 16 := RDWR_SDATA_WIDTH/8;
Constant RDWR_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(RDWR_MAX_BURST_LEN,
RDWR_BYTES_PER_BEAT);
Constant RDWR_CORRECTED_BTT_USED : integer := funct_fix_btt_used(RDWR_BTT_USED,
RDWR_MIN_BTT_NEEDED);
Constant OMIT_INDET_BTT : integer range 0 to 1 := 0;
Constant OMIT_DRE : integer range 0 to 1 := 0;
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 1;
Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2; -- 2 added for going
-- full thresholding
-- in WSC
Constant WSC_BYTES_RCVD_WIDTH : integer range 8 to 32 := RDWR_CORRECTED_BTT_USED;
Constant OMIT_STORE_FORWARD : integer range 0 to 1 := 0;
-- Signal Declarations ------------------------------------------
signal sig_md_error_reg : std_logic := '0';
signal sig_doing_read : std_logic := '0';
signal sig_doing_write : std_logic := '0';
signal sig_axi2addr_aready : std_logic := '0';
signal sig_addr2axi_arvalid : std_logic := '0';
signal sig_addr2axi_awvalid : std_logic := '0';
signal sig_addr2axi_aid : std_logic_vector(RDWR_ARID_WIDTH-1 downto 0) := (others => '0');
signal sig_addr2axi_aaddr : std_logic_vector(RDWR_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr2axi_alen : std_logic_vector(7 downto 0) := (others => '0');
signal sig_addr2axi_asize : std_logic_vector(2 downto 0) := (others => '0');
signal sig_addr2axi_aburst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_addr2axi_aprot : std_logic_vector(2 downto 0) := (others => '0');
signal sig_rdc2axi_rready : std_logic := '0';
signal sig_axi2rdc_rvalid : std_logic := '0';
signal sig_axi2rdc_rdata : std_logic_vector(RDWR_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_axi2rdc_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sig_axi2rdc_rlast : std_logic := '0';
signal sig_wdc2wrskid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_wrskid2wdc_wready : std_logic := '0';
signal sig_wdc2wrskid_wvalid : std_logic := '0';
signal sig_wdc2wrskid_wdata : std_logic_vector(RDWR_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_wdc2wrskid_wstrb : std_logic_vector((RDWR_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_wdc2wrskid_wlast : std_logic := '0';
signal sig_axi2wrskid_wready : std_logic := '0';
signal sig_wrskid2axi_wvalid : std_logic := '0';
signal sig_wrskid2axi_wdata : std_logic_vector(RDWR_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_wrskid2axi_wstrb : std_logic_vector((RDWR_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_wrskid2axi_wlast : std_logic := '0';
signal sig_wsc2axi_bready : std_logic := '0';
signal sig_axi2wsc_bvalid : std_logic := '0';
signal sig_axi2wsc_bresp : std_logic_vector(1 downto 0) := (others => '0');
signal sig_rdskid2rdc_tready : std_logic := '0';
signal sig_rdc2rdskid_tvalid : std_logic := '0';
signal sig_rdc2rdskid_tdata : std_logic_vector(RDWR_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2rdskid_tstrb : std_logic_vector((RDWR_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_rdc2rdskid_tlast : std_logic := '0';
signal sig_strm2rdskid_tready : std_logic := '0';
signal sig_rdskid2strm_tvalid : std_logic := '0';
signal sig_rdskid2strm_tdata : std_logic_vector(RDWR_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_rdskid2strm_tstrb : std_logic_vector((RDWR_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_rdskid2strm_tlast : std_logic := '0';
signal sig_wrskid2strm_tready : std_logic := '0';
signal sig_strm2wrskid_tvalid : std_logic := '0';
signal sig_strm2wrskid_tdata : std_logic_vector(RDWR_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strm2wrskid_tstrb : std_logic_vector((RDWR_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_strm2wrskid_tlast : std_logic := '0';
signal sig_wdc2wrskid_tready : std_logic := '0';
signal sig_wrskid2wdc_tvalid : std_logic := '0';
signal sig_wrskid2wdc_tdata : std_logic_vector(RDWR_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_wrskid2wdc_tstrb : std_logic_vector((RDWR_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_wrskid2wdc_tlast : std_logic := '0';
signal sig_cmd2pcc_command : std_logic_vector(RDWR_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2pcc_cmd_valid : std_logic := '0';
signal sig_pcc2cmd_cmd_ready : std_logic := '0';
signal sig_pcc2addr_tag : std_logic_vector(RDWR_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pcc2addr_addr : std_logic_vector(RDWR_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_pcc2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_pcc2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_pcc2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_pcc2addr_cmd_cmplt : std_logic := '0';
signal sig_pcc2addr_calc_error : std_logic := '0';
signal sig_pcc2addr_cmd_valid : std_logic := '0';
signal sig_addr2pcc_cmd_ready : std_logic := '0';
signal sig_pcc2data_tag : std_logic_vector(RDWR_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pcc2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_pcc2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_pcc2data_strt_strb : std_logic_vector((RDWR_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_pcc2data_last_strb : std_logic_vector((RDWR_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_pcc2data_drr : std_logic := '0';
signal sig_pcc2data_eof : std_logic := '0';
signal sig_pcc2data_sequential : std_logic := '0';
signal sig_pcc2data_calc_error : std_logic := '0';
signal sig_pcc2data_cmd_cmplt : std_logic := '0';
signal sig_pcc2data_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_pcc2data_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_pcc2all_calc_err : std_logic := '0';
signal sig_pcc2data_cmd_valid : std_logic := '0';
signal sig_pcc2rdc_cmd_valid : std_logic := '0';
signal sig_pcc2wdc_cmd_valid : std_logic := '0';
signal sig_data2pcc_cmd_ready : std_logic := '0';
signal sig_rdc2pcc_cmd_ready : std_logic := '0';
signal sig_wdc2pcc_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_addr2wdc_addr_posted : std_logic := '0';
signal sig_addr2rdc_addr_posted : std_logic := '0';
signal sig_rdc2skid_halt : std_logic := '0';
signal sig_wdc2skid_halt : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_rdc2addr_stop_req : std_logic := '0';
signal sig_wdc2addr_stop_req : std_logic := '0';
signal sig_wsc2wdc_halt_pipe : std_logic := '0';
signal sig_addr2stat_calc_error : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2wsc_calc_error : std_logic := '0';
signal sig_addr2stat_cmd_fifo_empty : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0';
signal sig_rdc2rsc_tag : std_logic_vector(RDWR_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2rsc_calc_err : std_logic := '0';
signal sig_rdc2rsc_okay : std_logic := '0';
signal sig_rdc2rsc_decerr : std_logic := '0';
signal sig_rdc2rsc_slverr : std_logic := '0';
signal sig_rdc2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2rdc_ready : std_logic := '0';
signal sig_rdc2rsc_valid : std_logic := '0';
signal sig_rsc2rdc_halt_pipe : std_logic := '0';
signal sig_allow_addr_req : std_logic := '0';
signal sig_addr_req_posted : std_logic := '0';
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(RDWR_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2wsc_status_ready : std_logic := '0';
signal sig_wsc2stat_status_valid : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(RDWR_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_wdc_stbs_asserted : std_logic_vector(7 downto 0) := (others => '0');
signal sig_wdc2wsc_tag : std_logic_vector(RDWR_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_wdc2wsc_calc_err : std_logic := '0';
signal sig_wdc2wsc_last_err : std_logic := '0';
signal sig_wdc2wsc_cmd_cmplt : std_logic := '0';
signal sig_wsc2wdc_ready : std_logic := '0';
signal sig_wdc2wsc_valid : std_logic := '0';
signal sig_wdc2wsc_eop : std_logic := '0';
signal sig_wdc2wsc_bytes_rcvd : std_logic_vector(WSC_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_enable_rd_llink : std_logic := '0';
signal sig_enable_wr_llink : std_logic := '0';
signal sig_doing_read_reg : std_logic := '0';
signal sig_doing_write_reg : std_logic := '0';
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_realign2wdc_eop_error : std_logic := '0';
begin --(architecture implementation)
---------------------------------------------------------------
-- Command Type Discrete Assignements
---------------------------------------------------------------
sig_doing_read <= cmd2rdwr_doing_read;
sig_doing_write <= cmd2rdwr_doing_write;
---------------------------------------------------------------
-- Read Address Pipelining Assignements
---------------------------------------------------------------
rd_addr_req_posted <= sig_addr_req_posted
When (sig_doing_read = '1')
Else '0';
rd_xfer_cmplt <= sig_rd_xfer_cmplt ;
---------------------------------------------------------------
-- Write Address Pipelining Assignements
---------------------------------------------------------------
wr_addr_req_posted <= sig_addr_req_posted
When (sig_doing_write = '1')
Else '0';
wr_xfer_cmplt <= sig_wr_xfer_cmplt;
---------------------------------------------------------------
-- AXI Read Addess Channel AREADY Port Assignments
-- This is a composite of the Read and Write Address ready
-- inputs.
---------------------------------------------------------------
sig_axi2addr_aready <= rd_arready
when (sig_doing_read = '1')
Else wr_awready
when (sig_doing_write = '1')
else '0' ;
---------------------------------------------------------------
-- AXI Read Addess Channel Port Assignments
---------------------------------------------------------------
rd_arvalid <= sig_addr2axi_arvalid;
rd_arid <= sig_addr2axi_aid ;
rd_araddr <= sig_addr2axi_aaddr ;
rd_arlen <= sig_addr2axi_alen ;
rd_arsize <= sig_addr2axi_asize ;
rd_arburst <= sig_addr2axi_aburst ;
rd_arprot <= sig_addr2axi_aprot ;
rd_arcache <= "0011" ; -- Per Interface-X guidelines for Masters ;
---------------------------------------------------------------
-- AXI Read Data Channel Port Assignments
---------------------------------------------------------------
rd_rready <= sig_rdc2axi_rready ;
sig_axi2rdc_rvalid <= rd_rvalid ;
sig_axi2rdc_rdata <= rd_rdata ;
sig_axi2rdc_rresp <= rd_rresp ;
sig_axi2rdc_rlast <= rd_rlast ;
---------------------------------------------------------------
-- AXI Write Addess Channel Port Assignments
---------------------------------------------------------------
wr_awvalid <= sig_addr2axi_awvalid;
wr_awid <= sig_addr2axi_aid ;
wr_awaddr <= sig_addr2axi_aaddr ;
wr_awlen <= sig_addr2axi_alen ;
wr_awsize <= sig_addr2axi_asize ;
wr_awburst <= sig_addr2axi_aburst ;
wr_awprot <= sig_addr2axi_aprot ;
wr_awcache <= "0011" ; -- Per Interface-X guidelines for Masters ;
-------------------------------------------------------------------------
-- AXI Write Data Channel Port Assignments
-------------------------------------------------------------------------
sig_axi2wrskid_wready <= wr_wready ;
wr_wvalid <= sig_wrskid2axi_wvalid ;
wr_wdata <= sig_wrskid2axi_wdata ;
wr_wstrb <= sig_wrskid2axi_wstrb ;
wr_wlast <= sig_wrskid2axi_wlast ;
-------------------------------------------------------------------------
-- AXI Write Response Channel Port Assignments
-------------------------------------------------------------------------
wr_bready <= sig_wsc2axi_bready ;
sig_axi2wsc_bvalid <= wr_bvalid ;
sig_axi2wsc_bresp <= wr_bresp ;
-------------------------------------------------------------------------
-- AXI Read Master Stream Channel Port Assignments
-------------------------------------------------------------------------
sig_strm2rdskid_tready <= rd_strm_tready ;
rd_strm_tvalid <= sig_rdskid2strm_tvalid ;
rd_strm_tdata <= sig_rdskid2strm_tdata ;
rd_strm_tstrb <= sig_rdskid2strm_tstrb ;
rd_strm_tlast <= sig_rdskid2strm_tlast ;
-------------------------------------------------------------------------
-- AXI Write Stream Channel Port Assignments
-------------------------------------------------------------------------
wr_strm_tready <= sig_wrskid2strm_tready ;
sig_strm2wrskid_tvalid <= wr_strm_tvalid ;
sig_strm2wrskid_tdata <= wr_strm_tdata ;
sig_strm2wrskid_tstrb <= wr_strm_tstrb ;
sig_strm2wrskid_tlast <= wr_strm_tlast ;
-------------------------------------------------------------------------
-- Read Status I/O Port Assignments
-------------------------------------------------------------------------
sig_stat2rsc_status_ready <= stat2rsc_status_ready ;
rsc2stat_status_valid <= sig_rsc2stat_status_valid ;
rsc2stat_status <= sig_rsc2stat_status ;
-------------------------------------------------------------------------
-- Write Status I/O Port Assignments
-------------------------------------------------------------------------
sig_stat2wsc_status_ready <= stat2wsc_status_ready ;
wsc2stat_status_valid <= sig_wsc2stat_status_valid ;
wsc2stat_status <= sig_wsc2stat_status ;
-------------------------------------------------------------------------
-- Internal error output discrete
-------------------------------------------------------------------------
rdwr_md_error <= sig_md_error_reg;
-------------------------------------------------------------------------
-- Assign the PCC Command Interface Ports
-------------------------------------------------------------------------
sig_cmd2pcc_command <= cmd2rdwr_cmd_data ;
sig_cmd2pcc_cmd_valid <= cmd2rdwr_cmd_valid ;
rdwr2cmd_cmd_ready <= sig_pcc2cmd_cmd_ready ;
-------------------------------------------------------------------------
-- Misc. Logic
-------------------------------------------------------------------------
sig_rst2all_stop_request <= '0';
-------------------------------------------------------------------------
-- LocalLink Enables Logic
-------------------------------------------------------------------------
rd_llink_enable <= sig_enable_rd_llink;
wr_llink_enable <= sig_enable_wr_llink;
-- create a 1 clock pulse for enabling the Read LocalLink on
-- the rising edge of the sig_doing_read signal.
sig_enable_rd_llink <= not(sig_doing_read_reg) and
sig_doing_read ;
-- create a 1 clock pulse for enabling the write LocalLink on
-- the rising edge of the sig_doing_write signal.
sig_enable_wr_llink <= not(sig_doing_write_reg) and
sig_doing_write ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DOING_RD_FLOP
--
-- Process Description:
-- Registers the Doing Read input signal
--
-------------------------------------------------------------
IMP_DOING_RD_FLOP : process (rdwr_aclk)
begin
if (rdwr_aclk'event and rdwr_aclk = '1') then
if (rdwr_areset = '1') then
sig_doing_read_reg <= '0';
else
sig_doing_read_reg <= sig_doing_read;
end if;
end if;
end process IMP_DOING_RD_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DOING_WR_FLOP
--
-- Process Description:
-- Registers the Doing Write input signal
--
-------------------------------------------------------------
IMP_DOING_WR_FLOP : process (rdwr_aclk)
begin
if (rdwr_aclk'event and rdwr_aclk = '1') then
if (rdwr_areset = '1') then
sig_doing_write_reg <= '0';
else
sig_doing_write_reg <= sig_doing_write;
end if;
end if;
end process IMP_DOING_WR_FLOP;
-------------------------------------------------------------------------
-- Predictive Command Calculator Logic
-------------------------------------------------------------------------
sig_data2pcc_cmd_ready <= sig_rdc2pcc_cmd_ready
When (sig_doing_read = '1')
Else sig_wdc2pcc_cmd_ready
When (sig_doing_write = '1')
Else '0';
sig_pcc2rdc_cmd_valid <= sig_pcc2data_cmd_valid
when (sig_doing_read = '1')
Else '0';
sig_pcc2wdc_cmd_valid <= sig_pcc2data_cmd_valid
when (sig_doing_write = '1')
Else '0';
------------------------------------------------------------
-- Instance: I_MSTR_PCC
--
-- Description:
-- Predictive Command Calculator Block
--
------------------------------------------------------------
I_MSTR_PCC : entity axi_master_burst_v2_0.axi_master_burst_pcc
generic map (
C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => RDWR_ADDR_WIDTH ,
C_STREAM_DWIDTH => RDWR_SDATA_WIDTH ,
C_MAX_BURST_LEN => RDWR_MAX_BURST_LEN ,
C_CMD_WIDTH => RDWR_CMD_WIDTH ,
C_TAG_WIDTH => RDWR_TAG_WIDTH ,
C_BTT_USED => RDWR_CORRECTED_BTT_USED ,
C_SUPPORT_INDET_BTT => OMIT_INDET_BTT
)
port map (
-- Clock input
primary_aclk => rdwr_aclk ,
mmap_reset => rdwr_areset ,
cmd2mstr_command => sig_cmd2pcc_command ,
cmd2mstr_cmd_valid => sig_cmd2pcc_cmd_valid ,
mst2cmd_cmd_ready => sig_pcc2cmd_cmd_ready ,
mstr2addr_tag => sig_pcc2addr_tag ,
mstr2addr_addr => sig_pcc2addr_addr ,
mstr2addr_len => sig_pcc2addr_len ,
mstr2addr_size => sig_pcc2addr_size ,
mstr2addr_burst => sig_pcc2addr_burst ,
mstr2addr_cmd_cmplt => sig_pcc2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_pcc2addr_calc_error ,
mstr2addr_cmd_valid => sig_pcc2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2pcc_cmd_ready ,
mstr2data_tag => sig_pcc2data_tag ,
mstr2data_saddr_lsb => sig_pcc2data_saddr_lsb ,
mstr2data_len => sig_pcc2data_len ,
mstr2data_strt_strb => sig_pcc2data_strt_strb ,
mstr2data_last_strb => sig_pcc2data_last_strb ,
mstr2data_drr => sig_pcc2data_drr ,
mstr2data_eof => sig_pcc2data_eof ,
mstr2data_sequential => sig_pcc2data_sequential ,
mstr2data_calc_error => sig_pcc2data_calc_error ,
mstr2data_cmd_cmplt => sig_pcc2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_pcc2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2pcc_cmd_ready ,
mstr2data_dre_src_align => sig_pcc2data_dre_src_align ,
mstr2data_dre_dest_align => sig_pcc2data_dre_dest_align ,
calc_error => sig_pcc2all_calc_err ,
dre2mstr_cmd_ready => LOGIC_HIGH ,
mstr2dre_cmd_valid => open ,
mstr2dre_tag => open ,
mstr2dre_dre_src_align => open ,
mstr2dre_dre_dest_align => open ,
mstr2dre_btt => open ,
mstr2dre_drr => open ,
mstr2dre_eof => open ,
mstr2dre_cmd_cmplt => open ,
mstr2dre_calc_error => open
);
-------------------------------------------------------------------------
-- Address Controller Logic
-------------------------------------------------------------------------
sig_allow_addr_req <= rd_allow_addr_req
when (sig_doing_read = '1')
Else wr_allow_addr_req
When (sig_doing_write = '1')
Else '0';
sig_addr2rdc_addr_posted <= sig_addr2data_addr_posted
When (sig_doing_read = '1')
Else '0';
sig_addr2wdc_addr_posted <= sig_addr2data_addr_posted
When (sig_doing_write = '1')
Else '0';
sig_data2addr_stop_req <= sig_rdc2addr_stop_req or
sig_wdc2addr_stop_req ;
sig_addr2rsc_calc_error <= sig_addr2stat_calc_error
when (sig_doing_read = '1')
Else '0';
sig_addr2wsc_calc_error <= sig_addr2stat_calc_error
when (sig_doing_write = '1')
Else '0';
sig_addr2rsc_cmd_fifo_empty <= sig_addr2stat_cmd_fifo_empty
when (sig_doing_read = '1')
Else '0';
sig_addr2wsc_cmd_fifo_empty <= sig_addr2stat_cmd_fifo_empty
when (sig_doing_write = '1')
Else '0';
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_master_burst_v2_0.axi_master_burst_addr_cntl
generic map (
C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => RDWR_ADDR_WIDTH ,
C_ADDR_ID => RDWR_ARID_VALUE ,
C_ADDR_ID_WIDTH => RDWR_ARID_WIDTH ,
C_TAG_WIDTH => RDWR_TAG_WIDTH
)
port map (
primary_aclk => rdwr_aclk ,
mmap_reset => rdwr_areset ,
doing_read => sig_doing_read ,
doing_write => sig_doing_write ,
addr2axi_aid => sig_addr2axi_aid ,
addr2axi_aaddr => sig_addr2axi_aaddr ,
addr2axi_alen => sig_addr2axi_alen ,
addr2axi_asize => sig_addr2axi_asize ,
addr2axi_aburst => sig_addr2axi_aburst ,
addr2axi_aprot => sig_addr2axi_aprot ,
addr2axi_arvalid => sig_addr2axi_arvalid ,
addr2axi_awvalid => sig_addr2axi_awvalid ,
axi2addr_aready => sig_axi2addr_aready ,
mstr2addr_tag => sig_pcc2addr_tag ,
mstr2addr_addr => sig_pcc2addr_addr ,
mstr2addr_len => sig_pcc2addr_len ,
mstr2addr_size => sig_pcc2addr_size ,
mstr2addr_burst => sig_pcc2addr_burst ,
mstr2addr_cmd_cmplt => sig_pcc2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_pcc2addr_calc_error ,
mstr2addr_cmd_valid => sig_pcc2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2pcc_cmd_ready ,
addr2rst_stop_cmplt => open ,
allow_addr_req => sig_allow_addr_req ,
addr_req_posted => sig_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2stat_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2stat_cmd_fifo_empty
);
-------------------------------------------------------------------------
-- Read Data Controller Logic
-------------------------------------------------------------------------
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_master_burst_v2_0.axi_master_burst_rddata_cntl
generic map (
C_INCLUDE_DRE => OMIT_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => RDWR_MDATA_WIDTH ,
C_STREAM_DWIDTH => RDWR_SDATA_WIDTH ,
C_TAG_WIDTH => RDWR_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => rdwr_aclk ,
mmap_reset => rdwr_areset ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_rdc2addr_stop_req ,
data2rst_stop_cmplt => open ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => sig_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => sig_axi2rdc_rdata ,
mm2s_rresp => sig_axi2rdc_rresp ,
mm2s_rlast => sig_axi2rdc_rlast ,
mm2s_rvalid => sig_axi2rdc_rvalid ,
mm2s_rready => sig_rdc2axi_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => open ,
mm2s_dre_use_autodest => open ,
mm2s_dre_src_align => open ,
mm2s_dre_dest_align => open ,
mm2s_dre_flush => open ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => sig_rdc2rdskid_tvalid ,
mm2s_strm_wready => sig_rdskid2rdc_tready ,
mm2s_strm_wdata => sig_rdc2rdskid_tdata ,
mm2s_strm_wstrb => sig_rdc2rdskid_tstrb ,
mm2s_strm_wlast => sig_rdc2rdskid_tlast ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_pcc2data_tag ,
mstr2data_saddr_lsb => sig_pcc2data_saddr_lsb ,
mstr2data_len => sig_pcc2data_len ,
mstr2data_strt_strb => sig_pcc2data_strt_strb ,
mstr2data_last_strb => sig_pcc2data_last_strb ,
mstr2data_drr => sig_pcc2data_drr ,
mstr2data_eof => sig_pcc2data_eof ,
mstr2data_sequential => sig_pcc2data_sequential ,
mstr2data_calc_error => sig_pcc2data_calc_error ,
mstr2data_cmd_cmplt => sig_pcc2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_pcc2rdc_cmd_valid ,
data2mstr_cmd_ready => sig_rdc2pcc_cmd_ready ,
mstr2data_dre_src_align => sig_pcc2data_dre_src_align ,
mstr2data_dre_dest_align => sig_pcc2data_dre_dest_align ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2rdc_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => open ,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_rdc2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_rdc2rsc_tag ,
data2rsc_calc_err => sig_rdc2rsc_calc_err ,
data2rsc_okay => sig_rdc2rsc_okay ,
data2rsc_decerr => sig_rdc2rsc_decerr ,
data2rsc_slverr => sig_rdc2rsc_slverr ,
data2rsc_cmd_cmplt => sig_rdc2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2rdc_ready ,
data2rsc_valid => sig_rdc2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2rdc_halt_pipe
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_master_burst_v2_0.axi_master_burst_rd_status_cntl
generic map (
C_STS_WIDTH => RDWR_STS_WIDTH ,
C_TAG_WIDTH => RDWR_TAG_WIDTH
)
port map (
primary_aclk => rdwr_aclk ,
mmap_reset => rdwr_areset ,
calc2rsc_calc_error => sig_pcc2all_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_rdc2rsc_tag ,
data2rsc_calc_error => sig_rdc2rsc_calc_err ,
data2rsc_okay => sig_rdc2rsc_okay ,
data2rsc_decerr => sig_rdc2rsc_decerr ,
data2rsc_slverr => sig_rdc2rsc_slverr ,
data2rsc_cmd_cmplt => sig_rdc2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2rdc_ready ,
data2rsc_valid => sig_rdc2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2rdc_halt_pipe
);
------------------------------------------------------------
-- Instance: I_READ_STREAM_SKID_BUF
--
-- Description:
-- Instance for the Read side Skid Buffer which provides
-- for registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_READ_STREAM_SKID_BUF : entity axi_master_burst_v2_0.axi_master_burst_skid_buf
generic map (
C_WDATA_WIDTH => RDWR_SDATA_WIDTH
)
port map (
-- System Ports
aclk => rdwr_aclk ,
arst => rdwr_areset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_rdc2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => sig_rdc2rdskid_tvalid ,
s_ready => sig_rdskid2rdc_tready ,
s_data => sig_rdc2rdskid_tdata ,
s_strb => sig_rdc2rdskid_tstrb ,
s_last => sig_rdc2rdskid_tlast ,
-- Master Side (Stream Data Output
m_valid => sig_rdskid2strm_tvalid ,
m_ready => sig_strm2rdskid_tready ,
m_data => sig_rdskid2strm_tdata ,
m_strb => sig_rdskid2strm_tstrb ,
m_last => sig_rdskid2strm_tlast
);
-------------------------------------------------------------------------
-- Write Data Controller Logic
-------------------------------------------------------------------------
sig_wdc_stbs_asserted <= (others => '0');
sig_realign2wdc_eop_error <= '0';
------------------------------------------------------------
-- Instance: I_WR_DATA_CNTL
--
-- Description:
-- Write Data Controller Block
--
------------------------------------------------------------
I_WR_DATA_CNTL : entity axi_master_burst_v2_0.axi_master_burst_wrdata_cntl
generic map (
C_REALIGNER_INCLUDED => OMIT_DRE ,
C_ENABLE_STORE_FORWARD => OMIT_STORE_FORWARD ,
C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => RDWR_MDATA_WIDTH ,
C_STREAM_DWIDTH => RDWR_SDATA_WIDTH ,
C_TAG_WIDTH => RDWR_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => rdwr_aclk ,
mmap_reset => rdwr_areset ,
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_wdc2addr_stop_req ,
data2rst_stop_cmplt => open ,
wr_xfer_cmplt => sig_wr_xfer_cmplt ,
s2mm_ld_nxt_len => open ,
s2mm_wr_len => open ,
data2skid_saddr_lsb => sig_wdc2wrskid_addr_lsb ,
data2skid_wdata => sig_wdc2wrskid_wdata ,
data2skid_wstrb => sig_wdc2wrskid_wstrb ,
data2skid_wlast => sig_wdc2wrskid_wlast ,
data2skid_wvalid => sig_wdc2wrskid_wvalid ,
skid2data_wready => sig_wrskid2wdc_wready ,
s2mm_strm_wvalid => sig_wrskid2wdc_tvalid ,
s2mm_strm_wready => sig_wdc2wrskid_tready ,
s2mm_strm_wdata => sig_wrskid2wdc_tdata ,
s2mm_strm_wstrb => sig_wrskid2wdc_tstrb ,
s2mm_strm_wlast => sig_wrskid2wdc_tlast ,
s2mm_strm_eop => sig_wrskid2wdc_tlast ,
s2mm_stbs_asserted => sig_wdc_stbs_asserted ,
realign2wdc_eop_error => sig_realign2wdc_eop_error ,
mstr2data_tag => sig_pcc2data_tag ,
mstr2data_saddr_lsb => sig_pcc2data_saddr_lsb ,
mstr2data_len => sig_pcc2data_len ,
mstr2data_strt_strb => sig_pcc2data_strt_strb ,
mstr2data_last_strb => sig_pcc2data_last_strb ,
mstr2data_drr => sig_pcc2data_drr ,
mstr2data_eof => sig_pcc2data_eof ,
mstr2data_sequential => sig_pcc2data_sequential ,
mstr2data_calc_error => sig_pcc2data_calc_error ,
mstr2data_cmd_cmplt => sig_pcc2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_pcc2wdc_cmd_valid ,
data2mstr_cmd_ready => sig_wdc2pcc_cmd_ready ,
addr2data_addr_posted => sig_addr2wdc_addr_posted ,
data2addr_data_rdy => open ,
data2all_tlast_error => open ,
data2all_dcntlr_halted => open ,
data2skid_halt => sig_wdc2skid_halt ,
data2wsc_tag => sig_wdc2wsc_tag ,
data2wsc_calc_err => sig_wdc2wsc_calc_err ,
data2wsc_last_err => sig_wdc2wsc_last_err ,
data2wsc_cmd_cmplt => sig_wdc2wsc_cmd_cmplt ,
wsc2data_ready => sig_wsc2wdc_ready ,
data2wsc_valid => sig_wdc2wsc_valid ,
data2wsc_eop => sig_wdc2wsc_eop ,
data2wsc_bytes_rcvd => sig_wdc2wsc_bytes_rcvd ,
wsc2mstr_halt_pipe => sig_wsc2wdc_halt_pipe
);
------------------------------------------------------------
-- Instance: I_WR_STATUS_CNTLR
--
-- Description:
-- Write Status Controller Block
--
------------------------------------------------------------
I_WR_STATUS_CNTLR : entity axi_master_burst_v2_0.axi_master_burst_wr_status_cntl
generic map (
C_ENABLE_STORE_FORWARD => OMIT_STORE_FORWARD ,
C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH ,
C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH ,
C_STS_WIDTH => RDWR_STS_WIDTH ,
C_TAG_WIDTH => RDWR_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => rdwr_aclk ,
mmap_reset => rdwr_areset ,
rst2wsc_stop_request => sig_rst2all_stop_request ,
wsc2rst_stop_cmplt => open ,
addr2wsc_addr_posted => sig_addr2wdc_addr_posted,
s2mm_bresp => sig_axi2wsc_bresp ,
s2mm_bvalid => sig_axi2wsc_bvalid ,
s2mm_bready => sig_wsc2axi_bready ,
calc2wsc_calc_error => sig_pcc2all_calc_err ,
addr2wsc_calc_error => sig_addr2wsc_calc_error ,
addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty ,
data2wsc_tag => sig_wdc2wsc_tag ,
data2wsc_calc_error => sig_wdc2wsc_calc_err ,
data2wsc_last_error => sig_wdc2wsc_last_err ,
data2wsc_cmd_cmplt => sig_wdc2wsc_cmd_cmplt ,
data2wsc_valid => sig_wdc2wsc_valid ,
wsc2data_ready => sig_wsc2wdc_ready ,
data2wsc_eop => sig_wdc2wsc_eop ,
data2wsc_bytes_rcvd => sig_wdc2wsc_bytes_rcvd ,
wsc2stat_status => sig_wsc2stat_status ,
stat2wsc_status_ready => sig_stat2wsc_status_ready ,
wsc2stat_status_valid => sig_wsc2stat_status_valid ,
wsc2mstr_halt_pipe => sig_wsc2wdc_halt_pipe
);
------------------------------------------------------------
-- Instance: I_WRITE_MMAP_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registered outputs and supports bi-dir throttling.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
------------------------------------------------------------
I_WRITE_MMAP_SKID_BUF : entity axi_master_burst_v2_0.axi_master_burst_skid2mm_buf
generic map (
C_MDATA_WIDTH => RDWR_MDATA_WIDTH ,
C_SDATA_WIDTH => RDWR_SDATA_WIDTH ,
C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH
)
port map (
-- System Ports
ACLK => rdwr_aclk ,
ARST => rdwr_areset ,
-- Slave Side (Wr Data Controller Input Side )
S_ADDR_LSB => sig_wdc2wrskid_addr_lsb,
S_VALID => sig_wdc2wrskid_wvalid ,
S_READY => sig_wrskid2wdc_wready ,
S_Data => sig_wdc2wrskid_wdata ,
S_STRB => sig_wdc2wrskid_wstrb ,
S_Last => sig_wdc2wrskid_wlast ,
-- Master Side (MMap Write Data Output Side)
M_VALID => sig_wrskid2axi_wvalid ,
M_READY => sig_axi2wrskid_wready ,
M_Data => sig_wrskid2axi_wdata ,
M_STRB => sig_wrskid2axi_wstrb ,
M_Last => sig_wrskid2axi_wlast
);
------------------------------------------------------------
-- Instance: I_WRITE_STRM_SKID_BUF
--
-- Description:
-- Instance for the Write Stream Input Skid Buffer which
-- provides for registerd Slave Stream inputs and supports
-- bi-dir throttling.
--
------------------------------------------------------------
I_WRITE_STRM_SKID_BUF : entity axi_master_burst_v2_0.axi_master_burst_skid_buf
generic map (
C_WDATA_WIDTH => RDWR_SDATA_WIDTH
)
port map (
-- System Ports
aclk => rdwr_aclk ,
arst => rdwr_areset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_wdc2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => sig_strm2wrskid_tvalid ,
s_ready => sig_wrskid2strm_tready ,
s_data => sig_strm2wrskid_tdata ,
s_strb => sig_strm2wrskid_tstrb ,
s_last => sig_strm2wrskid_tlast ,
-- Master Side (Stream Data Output)
m_valid => sig_wrskid2wdc_tvalid ,
m_ready => sig_wdc2wrskid_tready ,
m_data => sig_wrskid2wdc_tdata ,
m_strb => sig_wrskid2wdc_tstrb ,
m_last => sig_wrskid2wdc_tlast
);
end implementation;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
entity softcore is port (
clk, RX : in STD_LOGIC;
TX : out STD_LOGIC;
SW : in std_logic_vector(7 downto 0);
LED : out STD_LOGIC_VECTOR (7 downto 0));
end softcore;
architecture Behavioral of softcore is
component microblaze port(
Clk, Reset, UART_Rx : IN STD_LOGIC;
UART_Tx : OUT STD_LOGIC;
GPO1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
GPI1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
GPI1_Interrupt : OUT STD_LOGIC);
end component;
begin
core0 : microblaze port map(
Clk => Clk, Reset => '0',
UART_Rx => RX, UART_Tx => TX,
GPO1 => LED,
GPI1 => SW,
GPI1_Interrupt => open
);
end Behavioral;
|
component system is
port (
clk_50_clk : in std_logic := 'X'; -- clk
kernel_clk_clk : out std_logic; -- clk
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
peripheral_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
peripheral_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
peripheral_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
peripheral_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
peripheral_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
peripheral_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
peripheral_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
peripheral_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
peripheral_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
peripheral_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
peripheral_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
peripheral_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
peripheral_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
peripheral_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
peripheral_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
peripheral_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
peripheral_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
peripheral_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
peripheral_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
peripheral_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
peripheral_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
peripheral_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
peripheral_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
peripheral_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
peripheral_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
peripheral_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
peripheral_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
peripheral_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
peripheral_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
peripheral_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
peripheral_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
peripheral_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
peripheral_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
peripheral_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
peripheral_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA
peripheral_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL
peripheral_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53
reset_50_reset_n : in std_logic := 'X'; -- reset_n
acl_iface_alt_vip_itc_0_clocked_video_vid_clk : in std_logic := 'X'; -- vid_clk
acl_iface_alt_vip_itc_0_clocked_video_vid_data : out std_logic_vector(31 downto 0); -- vid_data
acl_iface_alt_vip_itc_0_clocked_video_underflow : out std_logic; -- underflow
acl_iface_alt_vip_itc_0_clocked_video_vid_datavalid : out std_logic; -- vid_datavalid
acl_iface_alt_vip_itc_0_clocked_video_vid_v_sync : out std_logic; -- vid_v_sync
acl_iface_alt_vip_itc_0_clocked_video_vid_h_sync : out std_logic; -- vid_h_sync
acl_iface_alt_vip_itc_0_clocked_video_vid_f : out std_logic; -- vid_f
acl_iface_alt_vip_itc_0_clocked_video_vid_h : out std_logic; -- vid_h
acl_iface_alt_vip_itc_0_clocked_video_vid_v : out std_logic; -- vid_v
acl_iface_clock_130_clk : in std_logic := 'X' -- clk
);
end component system;
u0 : component system
port map (
clk_50_clk => CONNECTED_TO_clk_50_clk, -- clk_50.clk
kernel_clk_clk => CONNECTED_TO_kernel_clk_clk, -- kernel_clk.clk
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
peripheral_hps_io_emac1_inst_TX_CLK => CONNECTED_TO_peripheral_hps_io_emac1_inst_TX_CLK, -- peripheral.hps_io_emac1_inst_TX_CLK
peripheral_hps_io_emac1_inst_TXD0 => CONNECTED_TO_peripheral_hps_io_emac1_inst_TXD0, -- .hps_io_emac1_inst_TXD0
peripheral_hps_io_emac1_inst_TXD1 => CONNECTED_TO_peripheral_hps_io_emac1_inst_TXD1, -- .hps_io_emac1_inst_TXD1
peripheral_hps_io_emac1_inst_TXD2 => CONNECTED_TO_peripheral_hps_io_emac1_inst_TXD2, -- .hps_io_emac1_inst_TXD2
peripheral_hps_io_emac1_inst_TXD3 => CONNECTED_TO_peripheral_hps_io_emac1_inst_TXD3, -- .hps_io_emac1_inst_TXD3
peripheral_hps_io_emac1_inst_RXD0 => CONNECTED_TO_peripheral_hps_io_emac1_inst_RXD0, -- .hps_io_emac1_inst_RXD0
peripheral_hps_io_emac1_inst_MDIO => CONNECTED_TO_peripheral_hps_io_emac1_inst_MDIO, -- .hps_io_emac1_inst_MDIO
peripheral_hps_io_emac1_inst_MDC => CONNECTED_TO_peripheral_hps_io_emac1_inst_MDC, -- .hps_io_emac1_inst_MDC
peripheral_hps_io_emac1_inst_RX_CTL => CONNECTED_TO_peripheral_hps_io_emac1_inst_RX_CTL, -- .hps_io_emac1_inst_RX_CTL
peripheral_hps_io_emac1_inst_TX_CTL => CONNECTED_TO_peripheral_hps_io_emac1_inst_TX_CTL, -- .hps_io_emac1_inst_TX_CTL
peripheral_hps_io_emac1_inst_RX_CLK => CONNECTED_TO_peripheral_hps_io_emac1_inst_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
peripheral_hps_io_emac1_inst_RXD1 => CONNECTED_TO_peripheral_hps_io_emac1_inst_RXD1, -- .hps_io_emac1_inst_RXD1
peripheral_hps_io_emac1_inst_RXD2 => CONNECTED_TO_peripheral_hps_io_emac1_inst_RXD2, -- .hps_io_emac1_inst_RXD2
peripheral_hps_io_emac1_inst_RXD3 => CONNECTED_TO_peripheral_hps_io_emac1_inst_RXD3, -- .hps_io_emac1_inst_RXD3
peripheral_hps_io_sdio_inst_CMD => CONNECTED_TO_peripheral_hps_io_sdio_inst_CMD, -- .hps_io_sdio_inst_CMD
peripheral_hps_io_sdio_inst_D0 => CONNECTED_TO_peripheral_hps_io_sdio_inst_D0, -- .hps_io_sdio_inst_D0
peripheral_hps_io_sdio_inst_D1 => CONNECTED_TO_peripheral_hps_io_sdio_inst_D1, -- .hps_io_sdio_inst_D1
peripheral_hps_io_sdio_inst_CLK => CONNECTED_TO_peripheral_hps_io_sdio_inst_CLK, -- .hps_io_sdio_inst_CLK
peripheral_hps_io_sdio_inst_D2 => CONNECTED_TO_peripheral_hps_io_sdio_inst_D2, -- .hps_io_sdio_inst_D2
peripheral_hps_io_sdio_inst_D3 => CONNECTED_TO_peripheral_hps_io_sdio_inst_D3, -- .hps_io_sdio_inst_D3
peripheral_hps_io_usb1_inst_D0 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D0, -- .hps_io_usb1_inst_D0
peripheral_hps_io_usb1_inst_D1 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D1, -- .hps_io_usb1_inst_D1
peripheral_hps_io_usb1_inst_D2 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D2, -- .hps_io_usb1_inst_D2
peripheral_hps_io_usb1_inst_D3 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D3, -- .hps_io_usb1_inst_D3
peripheral_hps_io_usb1_inst_D4 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D4, -- .hps_io_usb1_inst_D4
peripheral_hps_io_usb1_inst_D5 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D5, -- .hps_io_usb1_inst_D5
peripheral_hps_io_usb1_inst_D6 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D6, -- .hps_io_usb1_inst_D6
peripheral_hps_io_usb1_inst_D7 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D7, -- .hps_io_usb1_inst_D7
peripheral_hps_io_usb1_inst_CLK => CONNECTED_TO_peripheral_hps_io_usb1_inst_CLK, -- .hps_io_usb1_inst_CLK
peripheral_hps_io_usb1_inst_STP => CONNECTED_TO_peripheral_hps_io_usb1_inst_STP, -- .hps_io_usb1_inst_STP
peripheral_hps_io_usb1_inst_DIR => CONNECTED_TO_peripheral_hps_io_usb1_inst_DIR, -- .hps_io_usb1_inst_DIR
peripheral_hps_io_usb1_inst_NXT => CONNECTED_TO_peripheral_hps_io_usb1_inst_NXT, -- .hps_io_usb1_inst_NXT
peripheral_hps_io_uart0_inst_RX => CONNECTED_TO_peripheral_hps_io_uart0_inst_RX, -- .hps_io_uart0_inst_RX
peripheral_hps_io_uart0_inst_TX => CONNECTED_TO_peripheral_hps_io_uart0_inst_TX, -- .hps_io_uart0_inst_TX
peripheral_hps_io_i2c1_inst_SDA => CONNECTED_TO_peripheral_hps_io_i2c1_inst_SDA, -- .hps_io_i2c1_inst_SDA
peripheral_hps_io_i2c1_inst_SCL => CONNECTED_TO_peripheral_hps_io_i2c1_inst_SCL, -- .hps_io_i2c1_inst_SCL
peripheral_hps_io_gpio_inst_GPIO53 => CONNECTED_TO_peripheral_hps_io_gpio_inst_GPIO53, -- .hps_io_gpio_inst_GPIO53
reset_50_reset_n => CONNECTED_TO_reset_50_reset_n, -- reset_50.reset_n
acl_iface_alt_vip_itc_0_clocked_video_vid_clk => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_clk, -- acl_iface_alt_vip_itc_0_clocked_video.vid_clk
acl_iface_alt_vip_itc_0_clocked_video_vid_data => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_data, -- .vid_data
acl_iface_alt_vip_itc_0_clocked_video_underflow => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_underflow, -- .underflow
acl_iface_alt_vip_itc_0_clocked_video_vid_datavalid => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_datavalid, -- .vid_datavalid
acl_iface_alt_vip_itc_0_clocked_video_vid_v_sync => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_v_sync, -- .vid_v_sync
acl_iface_alt_vip_itc_0_clocked_video_vid_h_sync => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_h_sync, -- .vid_h_sync
acl_iface_alt_vip_itc_0_clocked_video_vid_f => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_f, -- .vid_f
acl_iface_alt_vip_itc_0_clocked_video_vid_h => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_h, -- .vid_h
acl_iface_alt_vip_itc_0_clocked_video_vid_v => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_v, -- .vid_v
acl_iface_clock_130_clk => CONNECTED_TO_acl_iface_clock_130_clk -- acl_iface_clock_130.clk
);
|
------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice, this
-- list of conditions and the following disclaimer in the documentation and/or other
-- materials provided with the distribution.
--
-- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-- Entity: d2prc
-- File: d2prc.vhd
-- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino)
-- Contacts: [email protected] www.testgroup.polito.it
-- Description: dprc dependable mode (see the DPR IP-core user manual for operations details).
-- Last revision: 08/10/2014
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.DMA2AHB_Package.all;
library testgrouppolito;
use testgrouppolito.dprc_pkg.all;
library techmap;
use techmap.gencomp.all;
entity d2prc is
generic (
technology : integer := virtex4; -- Target technology
fifo_depth : integer := 9; -- true FIFO depth = 2**fifo_depth
crc_block : integer := 10); -- Number of 32-bit words in a CRC-block
port (
rstn : in std_ulogic; -- Asynchronous Reset input (active low)
clkm : in std_ulogic; -- Clock input
clk100 : in std_ulogic; -- 100 MHz Clock input
dmai : out DMA_In_Type; -- dma signals input
dmao : in DMA_Out_Type; -- dma signals output
icapi : out icap_in_type; -- icap input signals
icapo : in icap_out_type; -- icap output signals
apbregi : in dprc_apbregin_type; -- values from apb registers (control, address, rm_reset)
apbcontrol : out dprc_apbcontrol_type; -- control signals for apb register
rm_reset : out std_logic_vector(31 downto 0)); -- Reconfigurable modules reset (1 bit for each different reconfigurable partition);
end d2prc;
architecture d2prc_rtl of d2prc is
type icap_state is (IDLE, START, READ_LENGTH, WAIT_AB, WRITE_ICAP, WRITE_ICAP_VERIFY, END_CONFIG, ABORT, ICAP_ERROR_LATENCY);
signal pstate, nstate : icap_state;
type ahb_state is (IDLE_AHB, START_AHB, GRANTED, CHECK_CRC, WAIT_WRITE_END, CHECK_LAST_CRC, BUS_CNTL_ERROR, FIFO_FULL, ICAP_ERROR, CRC_ERROR);
signal present_state, next_state : ahb_state;
-- fifo types
type ififo_type is record
wen : std_ulogic;
waddress : std_logic_vector(fifo_depth downto 0);
waddress_gray : std_logic_vector(fifo_depth downto 0);
idata : std_logic_vector(31 downto 0);
full : std_ulogic;
end record;
type ofifo_type is record
ren : std_ulogic;
raddress : std_logic_vector(fifo_depth downto 0);
raddress_gray : std_logic_vector(fifo_depth downto 0);
odata : std_logic_vector(31 downto 0);
empty : std_ulogic;
end record;
-- cdc control signals for async_dprc
type cdc_async is record
start : std_ulogic;
stop : std_ulogic;
icap_errn : std_ulogic;
icap_end : std_ulogic;
end record;
-- dummy fifo types
type icfifo_type is record
wen : std_ulogic;
waddress : std_logic_vector(4 downto 0);
waddress_gray : std_logic_vector(4 downto 0);
idata : std_logic_vector(0 downto 0);
full : std_ulogic;
end record;
type ocfifo_type is record
ren : std_ulogic;
raddress : std_logic_vector(4 downto 0);
raddress_gray : std_logic_vector(4 downto 0);
odata : std_logic_vector(0 downto 0);
empty : std_ulogic;
end record;
signal fifo_in, regfifo_in : ififo_type;
signal cfifoi, regcfifoi : icfifo_type;
signal fifo_out, regfifo_out : ofifo_type;
signal cfifoo, regcfifoo : ocfifo_type;
signal raddr_sync, waddr_sync : std_logic_vector(fifo_depth downto 0);
signal craddr_sync, cwaddr_sync : std_logic_vector(4 downto 0);
signal cdc_ahb, rcdc_ahb, cdc_icap, rcdc_icap : cdc_async;
type regs_ahb is record
c_grant : std_logic_vector(19 downto 0);
c_ready : std_logic_vector(19 downto 0);
c_latency : std_logic_vector(2 downto 0);
rm_reset : std_logic_vector(31 downto 0);
rst_persist : std_ulogic;
address : std_logic_vector(31 downto 0);
crc_signature : std_logic_vector(31 downto 0);
c_block : std_logic_vector(integer(ceil(log2(real(crc_block))))-1 downto 0); -- size the counter depending on the actual crc block size
end record;
type regs_icap is record
c_bitstream : std_logic_vector(19 downto 0);
c_latency : std_logic_vector(2 downto 0);
c_block : std_Logic_vector(integer(ceil(log2(real(crc_block))))-1 downto 0); -- size the counter depending on the actual crc block size
end record;
signal reg, regin : regs_ahb;
signal regicap, reginicap :regs_icap;
signal rstact : std_ulogic;
begin
-- fixed signals
dmai.Data <= (others => '0');
dmai.Beat <= HINCR;
dmai.Size <= HSIZE32;
dmai.Store <= '0'; --Only read transfer requests
dmai.Reset <= not(rstn);
dmai.Address <= reg.address;
rm_reset <= reg.rm_reset;
icapi.idata <= fifo_out.odata;
fifo_in.idata <= dmao.Data;
cfifoi.idata(0) <= cfifoi.wen;
-------------------------------
-- ahb bus clock domain
-------------------------------
ahbcomb: process(raddr_sync, craddr_sync, regfifo_in, regcfifoi, rcdc_ahb, cdc_ahb, reg, present_state, rstn, rstact, apbregi, dmao)
variable vfifo_in : ififo_type;
variable vcfifoi : icfifo_type;
variable vcdc_ahb : cdc_async;
variable regv : regs_ahb;
variable raddr_sync_decoded : std_logic_vector(fifo_depth downto 0);
variable craddr_sync_decoded : std_logic_vector(4 downto 0);
begin
apbcontrol.timer_clear <= '0';
apbcontrol.status_clr <= '0';
dmai.Request <= '0';
dmai.Burst <= '0';
dmai.Lock <= '0';
apbcontrol.status_value <= (others=>'0');
apbcontrol.status_en <= '0';
apbcontrol.control_clr <= '0';
apbcontrol.timer_en <= '0';
rstact <= '0';
vfifo_in.wen := '0';
vcfifoi.wen := '0';
regv := reg;
vcdc_ahb := rcdc_ahb;
vcdc_ahb.start := '0';
vcdc_ahb.stop := '0';
-- initialize fifo signals
vfifo_in.waddress := regfifo_in.waddress;
vfifo_in.full := '0';
vcfifoi.waddress := regcfifoi.waddress;
vcfifoi.full := '0';
-- fifos full generation
gray_decoder(raddr_sync,fifo_depth,raddr_sync_decoded);
if (vfifo_in.waddress(fifo_depth)=raddr_sync_decoded(fifo_depth) and (vfifo_in.waddress(fifo_depth-1 downto 0)-raddr_sync_decoded(fifo_depth-1 downto 0))>(2**fifo_depth-16)) then
vfifo_in.full := '1';
elsif (vfifo_in.waddress(fifo_depth)/= raddr_sync_decoded(fifo_depth) and (raddr_sync_decoded(fifo_depth-1 downto 0)-vfifo_in.waddress(fifo_depth-1 downto 0))<16) then
vfifo_in.full := '1';
end if;
gray_decoder(craddr_sync,4,craddr_sync_decoded);
if (vcfifoi.waddress(4)=craddr_sync_decoded(4) and (vcfifoi.waddress(3 downto 0)-craddr_sync_decoded(3 downto 0))>10) then
vcfifoi.full := '1';
elsif (vcfifoi.waddress(4)/= craddr_sync(4) and (craddr_sync_decoded(3 downto 0)-vcfifoi.waddress(3 downto 0))<10) then
vcfifoi.full := '1';
end if;
case present_state is
when IDLE_AHB =>
if (apbregi.control(19 downto 0)/=X"00000") then
next_state <= START_AHB;
apbcontrol.timer_clear <= '1'; -- clear timer register
apbcontrol.status_clr <= '1'; -- clear status register
regv.c_grant := apbregi.control(19 downto 0);
regv.c_ready := apbregi.control(19 downto 0);
regv.c_block := std_logic_vector(to_unsigned(crc_block-1,regv.c_block'length)); -- initialize counter
regv.address := apbregi.address;
vcdc_ahb.start := '1'; -- start icap write controller
regv.crc_signature := (others=>'1'); --reset crc_signature
else
next_state <= IDLE_AHB;
end if;
vfifo_in.waddress := (others=>'0');
vcfifoi.waddress := (others=>'0');
when START_AHB =>
if (dmao.Grant and dmao.Ready)='1' then
if (regv.c_block=0) then
next_state <= CHECK_CRC;
else
next_state <= GRANTED;
end if;
else
next_state <= START_AHB;
end if;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
vcdc_ahb.start := '1'; -- start icap write controller
when GRANTED =>
if (regv.c_block=0) and (dmao.Ready='1') then
next_state <= CHECK_CRC;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
elsif (regv.c_grant=0) then -- if the number of granted requests is equal to the bitstream words, request last crc
next_state <= CHECK_LAST_CRC;
elsif ((vfifo_in.full='1') or (vcfifoi.full='1')) then
next_state<=FIFO_FULL;
else
next_state <= GRANTED;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
end if;
when CHECK_LAST_CRC =>
if (regv.c_ready=1) and (dmao.Ready='1') then -- if CRC word received, check CRC and start downloading another block
if (regv.crc_signature/=dmao.Data) then -- do not write signature in data FIFO
next_state <= CRC_ERROR;
vcdc_ahb.stop := '1';
else
next_state <= WAIT_WRITE_END;
vcfifoi.wen := '1'; -- validate block
end if;
else
next_state <= CHECK_LAST_CRC;
end if;
when CHECK_CRC =>
if (dmao.Ready='1') then -- if CRC word received, check CRC and start downloading another block
if (regv.crc_signature/=dmao.Data) then -- do not write signature in data FIFO
next_state <= CRC_ERROR;
vcdc_ahb.stop := '1';
else
if (regv.c_grant=0) then
next_state <= CHECK_LAST_CRC;
else
next_state <= GRANTED;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
end if;
vcfifoi.wen := '1'; -- validate block
end if;
regv.c_block := std_logic_vector(to_unsigned(crc_block-1,regv.c_block'length)); -- re-initialize counter
else
next_state <= CHECK_CRC;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
end if;
when FIFO_FULL =>
if (regv.c_block=0) and (dmao.Ready='1') then
next_state <= CHECK_CRC;
elsif ((regv.c_grant=regv.c_ready) and (vfifo_in.full='0') and (vcfifoi.full='0')) then
next_state <= GRANTED;
else
next_state <= FIFO_FULL;
end if;
when WAIT_WRITE_END =>
if (regv.c_block=0) and (dmao.Ready='1') then
next_state <= CHECK_CRC;
elsif (cdc_ahb.icap_end='1') then
next_state <= IDLE_AHB;
regv.rst_persist := '0';
apbcontrol.status_value(3 downto 0) <= "1111";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
else
next_state <= WAIT_WRITE_END;
end if;
when CRC_ERROR =>
next_state <= IDLE_AHB;
apbcontrol.status_value(3 downto 0) <= "0001";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
vfifo_in.waddress := (others=>'0');
vcfifoi.waddress := (others=>'0');
vcdc_ahb.stop := '1';
regv.rst_persist := '1';
when BUS_CNTL_ERROR =>
next_state <= IDLE_AHB;
apbcontrol.status_value(3 downto 0) <= "0100";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
vfifo_in.waddress := (others=>'0');
vcfifoi.waddress := (others=>'0');
vcdc_ahb.stop := '1';
regv.rst_persist := '1';
when ICAP_ERROR =>
next_state <= IDLE_AHB;
apbcontrol.status_value(3 downto 0) <= "1000";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
vfifo_in.waddress := (others=>'0');
vcfifoi.waddress := (others=>'0');
regv.rst_persist := '1';
end case;
-- CRC check and fifo write enables
if (dmao.Ready='1') then
if (present_state/=CHECK_CRC) or (present_state=CHECK_LAST_CRC and regv.c_ready>1) then
crc(dmao.Data,reg.crc_signature,regv.crc_signature);
vfifo_in.wen := '1';
end if;
end if;
if (present_state/=IDLE_AHB) then
apbcontrol.timer_en <= '1'; -- Enable timer
rstact <= '1';
if dmao.Ready='1' then
regv.c_ready:=regv.c_ready-1;
end if;
if dmao.Grant='1' then
regv.c_grant:=regv.c_grant-1;
regv.address:=regv.address+4;
end if;
end if;
if (present_state/=IDLE_AHB) and (present_state/=CHECK_CRC) and (dmao.Ready='1') then
regv.c_block := regv.c_block-1;
end if;
if (present_state/=IDLE_AHB) and (cdc_ahb.icap_errn='0') then
next_state <= ICAP_ERROR;
end if;
if (dmao.Fault or dmao.Retry)='1' then
next_state <= BUS_CNTL_ERROR;
vcdc_ahb.stop := '1';
end if;
-- write fifos
if vfifo_in.wen = '1' then
vfifo_in.waddress := vfifo_in.waddress +1;
end if;
if vcfifoi.wen = '1' then
vcfifoi.waddress := vcfifoi.waddress +1;
end if;
gray_encoder(vfifo_in.waddress,vfifo_in.waddress_gray);
gray_encoder(vcfifoi.waddress,vcfifoi.waddress_gray);
-- fifos write address to be latched and synchronized
fifo_in.waddress_gray <= vfifo_in.waddress_gray;
cfifoi.waddress_gray <= vcfifoi.waddress_gray;
fifo_in.waddress <= vfifo_in.waddress;
cfifoi.waddress <= vcfifoi.waddress;
fifo_in.wen <= vfifo_in.wen;
cfifoi.wen <= vcfifoi.wen;
-- update fifo full
fifo_in.full <= vfifo_in.full;
cfifoi.full <= vcfifoi.full;
-- reconfigurable modules synchrounous reset generation (active high)
for i in 0 to 31 loop
regv.rm_reset(i) := not(rstn) or (apbregi.rm_reset(i) and (rstact or regv.rst_persist));
end loop;
cdc_ahb.start <= vcdc_ahb.start;
cdc_ahb.stop <= vcdc_ahb.stop;
regin <= regv;
end process;
ahbreg: process(clkm,rstn)
begin
if rstn='0' then
regfifo_in.waddress <= (others =>'0');
regcfifoi.waddress <= (others =>'0');
regfifo_in.waddress_gray <= (others =>'0');
regcfifoi.waddress_gray <= (others =>'0');
rcdc_ahb.start <= '0';
rcdc_ahb.stop <= '0';
present_state <= IDLE_AHB;
reg.rm_reset <= (others=>'0');
reg.c_grant <= (others=>'0');
reg.c_ready <= (others=>'0');
reg.c_latency <= (others=>'0');
reg.address <= (others=>'0');
reg.crc_signature <= (others=>'1');
reg.c_block <= (others=>'0');
reg.rst_persist <= '0';
elsif rising_edge(clkm) then
regfifo_in <= fifo_in;
regcfifoi <= cfifoi;
rcdc_ahb <= cdc_ahb;
present_state <= next_state;
reg <= regin;
end if;
end process;
-------------------------------
-- synchronization registers
-------------------------------
-- input d is already registered in the source clock domain
syn_gen0: for i in 0 to fifo_depth generate -- data fifo addresses
syncreg_inst0: syncreg generic map (tech => technology, stages => 2)
port map(clk => clk100, d => regfifo_in.waddress_gray(i), q => waddr_sync(i));
syncreg_inst1: syncreg generic map (tech => technology, stages => 2)
port map(clk => clkm, d => regfifo_out.raddress_gray(i), q => raddr_sync(i));
end generate;
syn_gen01: for i in 0 to 4 generate -- dummy control fifo addresses
syncreg_inst01: syncreg generic map (tech => technology, stages => 2)
port map(clk => clk100, d => regcfifoi.waddress_gray(i), q => cwaddr_sync(i));
syncreg_inst11: syncreg generic map (tech => technology, stages => 2)
port map(clk => clkm, d => regcfifoo.raddress_gray(i), q => craddr_sync(i));
end generate;
-- CDC control signals
syncreg_inst2: syncreg generic map (tech => technology, stages => 2)
port map(clk => clkm, d => rcdc_icap.icap_errn, q => cdc_ahb.icap_errn);
syncreg_inst3: syncreg generic map (tech => technology, stages => 2)
port map(clk => clkm, d => rcdc_icap.icap_end, q => cdc_ahb.icap_end);
syncreg_inst4: syncreg generic map (tech => technology, stages => 2)
port map(clk => clk100, d => rcdc_ahb.start, q => cdc_icap.start);
syncreg_inst5: syncreg generic map (tech => technology, stages => 2)
port map(clk => clk100, d => rcdc_ahb.stop, q => cdc_icap.stop);
-------------------------------
-- icap clock domain
-------------------------------
icapcomb: process(waddr_sync, cwaddr_sync, regfifo_out, fifo_out, regcfifoo, cfifoo, cdc_icap, pstate, regicap, icapo)
variable vfifo_out : ofifo_type;
variable vcfifoo : ocfifo_type;
variable vcdc_icap : cdc_async;
variable vregicap : regs_icap;
begin
icapi.cen <= '1';
icapi.wen <= '1';
vcdc_icap.icap_end := '0';
vcdc_icap.icap_errn := '1';
vregicap := regicap;
-- initialize fifo signals
vfifo_out.raddress := regfifo_out.raddress;
vfifo_out.empty := '0';
vfifo_out.ren := '0';
vcfifoo.raddress := regcfifoo.raddress;
vcfifoo.empty := '0';
vcfifoo.ren := '0';
-- fifos empty generation
gray_encoder(vfifo_out.raddress,vfifo_out.raddress_gray);
if (vfifo_out.raddress_gray=waddr_sync) then
vfifo_out.empty := '1';
end if;
gray_encoder(vcfifoo.raddress,vcfifoo.raddress_gray);
if (vcfifoo.raddress_gray=cwaddr_sync) then
vcfifoo.empty := '1';
end if;
-- fsm
case pstate is
when IDLE =>
if (cdc_icap.start='1') then
nstate <= START;
else
nstate <= IDLE;
end if;
vregicap.c_block:=std_logic_vector(to_unsigned(crc_block-1,vregicap.c_block'length)); -- initialize counter
when START =>
if (cfifoo.empty='0') then -- read first word of the bitstream & first checked block
vfifo_out.ren := '1';
vcfifoo.ren := '1';
nstate <= READ_LENGTH;
else
nstate <= START;
end if;
icapi.wen <= '0';
when READ_LENGTH =>
if (vregicap.c_block=0) then
nstate <= WAIT_AB;
else
nstate <= WRITE_ICAP;
end if;
vregicap.c_bitstream := fifo_out.odata(19 downto 0);
vfifo_out.ren := '1';
icapi.wen <= '0';
when WAIT_AB =>
if (vregicap.c_bitstream=1) then
nstate <= ICAP_ERROR_LATENCY;
elsif (cfifoo.empty='0') then -- download another block
vfifo_out.ren := '1';
vcfifoo.ren := '1';
nstate <= WRITE_ICAP;
else
nstate <= WAIT_AB;
end if;
icapi.wen <= '0';
vregicap.c_block:=std_logic_vector(to_unsigned(crc_block-1,vregicap.c_block'length)); -- reinitialize counter
icapi.cen <= not(regfifo_out.ren); --1 cycle latency with respect to fifo_out.ren
when WRITE_ICAP =>
if (vregicap.c_bitstream=1) then
nstate <= ICAP_ERROR_LATENCY;
elsif (vregicap.c_block=0) then
nstate <= WAIT_AB; -- wait for another block
vfifo_out.ren := '1';
elsif (icapo.odata(7) = '1') then -- if the ICAP is correctly initialized, then monitor ICAP status
nstate <= WRITE_ICAP_VERIFY;
vfifo_out.ren := '1';
else
nstate <= WRITE_ICAP;
vfifo_out.ren := '1';
end if;
icapi.wen <= '0';
icapi.cen <= not(regfifo_out.ren); --1 cycle latency with respect to fifo_out.ren
when WRITE_ICAP_VERIFY =>
if (vregicap.c_bitstream=1) then
nstate <= ICAP_ERROR_LATENCY;
elsif (vregicap.c_block=0) then
nstate <= WAIT_AB; -- wait for another block
vfifo_out.ren := '1';
elsif (icapo.odata(7) = '0') then -- verify ICAP status for configuration errors
nstate <= ABORT;
vcdc_icap.icap_errn:='0'; -- signal icap error to the ahb clock domain
vfifo_out.ren := '1';
else
nstate <= WRITE_ICAP_VERIFY;
vfifo_out.ren := '1';
end if;
icapi.wen <= '0';
icapi.cen <= not(regfifo_out.ren); --1 cycle latency with respect to fifo_out.ren
when END_CONFIG =>
nstate <= IDLE;
vfifo_out.raddress := (others=>'0');
vcfifoo.raddress := (others=>'0');
vcdc_icap.icap_end := '1';
when ABORT =>
if (vregicap.c_latency=4) then
nstate <= IDLE;
vregicap.c_latency := (others=>'0');
else
nstate <= ABORT;
vregicap.c_latency := vregicap.c_latency+1;
end if;
icapi.cen <= '0'; -- continue abort sequence
vcdc_icap.icap_errn:='0'; -- signal icap error to the ahb clock domain
vfifo_out.raddress := (others=>'0'); -- reset fifo address
vcfifoo.raddress := (others=>'0');
when ICAP_ERROR_LATENCY =>
if (icapo.odata(7) = '0') then -- verify ICAP status for configuration errors
nstate <= ABORT;
vregicap.c_latency := (others=>'0');
vcdc_icap.icap_errn:='0'; -- signal icap error to the ahb clock domain
elsif (vregicap.c_latency=4) then
nstate <= END_CONFIG;
vregicap.c_latency := (others=>'0');
vcdc_icap.icap_end := '1';
else
nstate <= ICAP_ERROR_LATENCY;
vregicap.c_latency := vregicap.c_latency+1;
end if;
icapi.wen <= '0';
end case;
if (cdc_icap.stop='1') then
nstate <= ABORT;
vregicap.c_latency := (others=>'0');
vfifo_out.ren := '1';
end if;
-- read fifos
if vfifo_out.ren = '1' then
vfifo_out.raddress := vfifo_out.raddress +1;
end if;
if vcfifoo.ren = '1' then
vcfifoo.raddress := vcfifoo.raddress +1;
end if;
if vfifo_out.ren = '1' then
vregicap.c_bitstream := vregicap.c_bitstream -1; -- because fifo introduces 1-cycle latency on output data
vregicap.c_block := vregicap.c_block-1;
end if;
-- fifos read address to be latched and synchronized
fifo_out.raddress_gray <= vfifo_out.raddress_gray;
cfifoo.raddress_gray <= vcfifoo.raddress_gray;
fifo_out.raddress <= vfifo_out.raddress;
cfifoo.raddress <= vcfifoo.raddress;
-- update fifo empty
fifo_out.empty <= vfifo_out.empty;
cfifoo.empty <= vcfifoo.empty;
fifo_out.ren <= vfifo_out.ren;
cfifoo.ren <= vcfifoo.ren;
cdc_icap.icap_errn <= vcdc_icap.icap_errn;
cdc_icap.icap_end <= vcdc_icap.icap_end;
reginicap <= vregicap;
end process;
icapreg: process(clk100,rstn)
begin
if rstn='0' then
regfifo_out.raddress <= (others =>'0');
regfifo_out.raddress_gray <= (others =>'0');
regfifo_out.ren <= '0';
regcfifoo.raddress <= (others =>'0');
regcfifoo.raddress_gray <= (others =>'0');
regcfifoo.ren <= '0';
regicap.c_bitstream <= (others =>'0');
regicap.c_latency <= (others =>'0');
regicap.c_block <= (others=>'0');
rcdc_icap.start <= '0';
rcdc_icap.stop <= '0';
elsif rising_edge(clk100) then
regfifo_out.raddress <= fifo_out.raddress;
regfifo_out.raddress_gray <= fifo_out.raddress_gray;
regfifo_out.ren <= fifo_out.ren;
regcfifoo.raddress <= cfifoo.raddress;
regcfifoo.raddress_gray <= cfifoo.raddress_gray;
pstate <= nstate;
regicap <= reginicap;
rcdc_icap <= cdc_icap;
end if;
end process;
--Instantiate data buffer
ram0 : syncram_2p generic map ( tech => technology, abits => fifo_depth, dbits => 32, sepclk => 1) -- 2**fifo_depth 32-bit data RAM
port map (clk100, fifo_out.ren, fifo_out.raddress(fifo_depth-1 downto 0), fifo_out.odata, clkm, fifo_in.wen, fifo_in.waddress(fifo_depth-1 downto 0), fifo_in.idata);
end d2prc_rtl;
|
-- Btrace 448
-- Sphere Generator - Test Bench
--
-- Bradley Boccuzzi
-- 2016
library ieee;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.btrace_pack.all;
entity spheregen_TB is
end spheregen_TB;
architecture arch of spheregen_TB is
constant clkPd: time := 20 ns;
signal clk, rst: std_logic;
signal d_vect: vector := (x"00000000", x"00000000", x"03E80000");
signal origin_point: point := (x"00000000", x"00000000", x"00000000");
-- should be positioned at z = 16, x = 0, y = 0
-- size 2
signal myObject: object := ((x"00000000", x"00000000", x"01900000"), x"00500000", x"F00");
signal obj_hit: std_logic;
signal result: std_logic_vector(31 downto 0);
begin
uut: entity work.sphere_gen port map(clk, d_vect, origin_point, myObject, result, obj_hit);
clkProc: process
begin
clk <= '1';
wait for clkPd/2;
clk <= '0';
wait for clkPd/2;
end process clkProc;
mainProc: process
begin
rst <= '1';
wait for clkPd/3;
wait for clkPd;
rst <= '0';
wait;
end process mainProc;
end arch;
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
use work.cam_pkg.all;
entity coproc_2 is
port(
clock : in std_logic;
reset : in std_logic;
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_1_valid : in std_logic;
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of coproc_2 is
signal min_reg : unsigned(7 downto 0);
signal beta_reg : unsigned(15 downto 0);
signal beta_tmp : unsigned(15 downto 0);
signal min_tmp, max_tmp : unsigned(7 downto 0);
signal store_min_beta : std_logic;
signal a,b : unsigned(15 downto 0);
signal OUTPUT_1_tmp : std_logic_vector(31 downto 0);
begin
-------------------------------------------------------------------------
scaling_computation : process (INPUT_1, min_reg, beta_reg)
variable mini : UNSIGNED(7 downto 0);
variable data1, data2, data3, data4 : UNSIGNED(7 downto 0);
variable diff1, diff2, diff3, diff4 : UNSIGNED(7 downto 0);
variable mult1, mult2, mult3, mult4 : UNSIGNED(23 downto 0);
begin
-- data1 := UNSIGNED( INPUT_1(7 downto 0) );
-- data2 := UNSIGNED( INPUT_1(15 downto 8) );
-- data3 := UNSIGNED( INPUT_1(23 downto 16) );
-- data4 := UNSIGNED( INPUT_1(31 downto 24) );
-- diff1 := data1 - min_reg; -- 8
-- diff2 := data2 - min_reg; -- 8
-- diff3 := data3 - min_reg; -- 8
-- diff4 := data4 - min_reg; -- 8
-- mult1 := diff1 * beta_reg; -- 24
-- mult2 := diff2 * beta_reg; -- 24
-- mult3 := diff3 * beta_reg; -- 24
-- mult4 := diff4 * beta_reg; -- 24
-- OUTPUT_1_tmp(7 downto 0) <= std_logic_vector(mult1(15 downto 8));
-- OUTPUT_1_tmp(15 downto 8) <= std_logic_vector(mult2(15 downto 8));
-- OUTPUT_1_tmp(23 downto 16) <= std_logic_vector(mult3(15 downto 8));
-- OUTPUT_1_tmp(31 downto 24) <= std_logic_vector(mult4(15 downto 8));
end process;
-------------------------------------------------------------------------
max_tmp <= UNSIGNED(INPUT_1(7 downto 0));
min_tmp <= UNSIGNED(INPUT_1(15 downto 8));
b <= "00000000"&(max_tmp-min_tmp);
a <= TO_UNSIGNED( 255, 8)&"00000000";
--beta_tmp <= divide(TO_UNSIGNED( 255, 8), (max_tmp-min_tmp));
beta_tmp <= divide(a,b); --(8,8)
--beta_tmp <= "00000000"&max_tmp-min_tmp;
-------------------------------------------------------------------------
process (clock, reset)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
store_min_beta <= '1';
min_reg <= (others => '0');
beta_reg <= (others => '0');
OUTPUT_1 <= (others => '0');
ELSE
IF (INPUT_1_valid = '1' and store_min_beta ='1') THEN
store_min_beta <= '0';
min_reg <= UNSIGNED(INPUT_1(15 downto 8));
beta_reg <= beta_tmp;
OUTPUT_1 <= INPUT_1;
ELSIF (INPUT_1_valid = '1' and store_min_beta = '0') THEN
store_min_beta <= '0';
min_reg <= min_reg;
beta_reg <= beta_reg;
OUTPUT_1 <= OUTPUT_1_tmp;
--OUTPUT_1 <= "000000000000000000000000"&std_logic_vector(min_reg);
END IF;
END IF;
END IF;
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
use work.cam_pkg.all;
entity coproc_2 is
port(
clock : in std_logic;
reset : in std_logic;
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_1_valid : in std_logic;
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of coproc_2 is
signal min_reg : unsigned(7 downto 0);
signal beta_reg : unsigned(15 downto 0);
signal beta_tmp : unsigned(15 downto 0);
signal min_tmp, max_tmp : unsigned(7 downto 0);
signal store_min_beta : std_logic;
signal a,b : unsigned(15 downto 0);
signal OUTPUT_1_tmp : std_logic_vector(31 downto 0);
begin
-------------------------------------------------------------------------
scaling_computation : process (INPUT_1, min_reg, beta_reg)
variable mini : UNSIGNED(7 downto 0);
variable data1, data2, data3, data4 : UNSIGNED(7 downto 0);
variable diff1, diff2, diff3, diff4 : UNSIGNED(7 downto 0);
variable mult1, mult2, mult3, mult4 : UNSIGNED(23 downto 0);
begin
-- data1 := UNSIGNED( INPUT_1(7 downto 0) );
-- data2 := UNSIGNED( INPUT_1(15 downto 8) );
-- data3 := UNSIGNED( INPUT_1(23 downto 16) );
-- data4 := UNSIGNED( INPUT_1(31 downto 24) );
-- diff1 := data1 - min_reg; -- 8
-- diff2 := data2 - min_reg; -- 8
-- diff3 := data3 - min_reg; -- 8
-- diff4 := data4 - min_reg; -- 8
-- mult1 := diff1 * beta_reg; -- 24
-- mult2 := diff2 * beta_reg; -- 24
-- mult3 := diff3 * beta_reg; -- 24
-- mult4 := diff4 * beta_reg; -- 24
-- OUTPUT_1_tmp(7 downto 0) <= std_logic_vector(mult1(15 downto 8));
-- OUTPUT_1_tmp(15 downto 8) <= std_logic_vector(mult2(15 downto 8));
-- OUTPUT_1_tmp(23 downto 16) <= std_logic_vector(mult3(15 downto 8));
-- OUTPUT_1_tmp(31 downto 24) <= std_logic_vector(mult4(15 downto 8));
end process;
-------------------------------------------------------------------------
max_tmp <= UNSIGNED(INPUT_1(7 downto 0));
min_tmp <= UNSIGNED(INPUT_1(15 downto 8));
b <= "00000000"&(max_tmp-min_tmp);
a <= TO_UNSIGNED( 255, 8)&"00000000";
--beta_tmp <= divide(TO_UNSIGNED( 255, 8), (max_tmp-min_tmp));
beta_tmp <= divide(a,b); --(8,8)
--beta_tmp <= "00000000"&max_tmp-min_tmp;
-------------------------------------------------------------------------
process (clock, reset)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
store_min_beta <= '1';
min_reg <= (others => '0');
beta_reg <= (others => '0');
OUTPUT_1 <= (others => '0');
ELSE
IF (INPUT_1_valid = '1' and store_min_beta ='1') THEN
store_min_beta <= '0';
min_reg <= UNSIGNED(INPUT_1(15 downto 8));
beta_reg <= beta_tmp;
OUTPUT_1 <= INPUT_1;
ELSIF (INPUT_1_valid = '1' and store_min_beta = '0') THEN
store_min_beta <= '0';
min_reg <= min_reg;
beta_reg <= beta_reg;
OUTPUT_1 <= OUTPUT_1_tmp;
--OUTPUT_1 <= "000000000000000000000000"&std_logic_vector(min_reg);
END IF;
END IF;
END IF;
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
-- Ejercicio 3, contador Asíncrono
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.txt_util.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_Cont32bAsync IS
END tb_Cont32bAsync;
ARCHITECTURE behavior OF tb_Cont32bAsync IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Cont32bAsync
PORT(
CLK : IN std_logic;
RST : IN std_logic;
LOAD : IN std_logic;
CE : IN std_logic;
UND : IN std_logic;
DIN : IN std_logic_vector(31 downto 0);
Q : BUFFER std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
signal LOAD : std_logic := '0';
signal CE : std_logic := '0';
signal UND : std_logic := '0';
signal DIN : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal Q : std_logic_vector(31 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Cont32bAsync PORT MAP (
CLK => CLK,
RST => RST,
LOAD => LOAD,
CE => CE,
UND => UND,
DIN => DIN,
Q => Q
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- check initial states
wait for 6 ns;
DIN<=x"00000000";
RST<='1';
LOAD<='0';
UND<='0';
CE <= '0';
wait for 10 ns;
RST <= '0';
wait for 40 ns; -- debe mantenerse sin contar
DIN <= x"0000005A";
CE<='1';
wait for 20 ns;
LOAD <= '1';
wait for 10 ns;
LOAD <= '0';
wait for 100 ns;
UND <= '1';
wait;
end process;
corr_proc: process(CLK)
variable theTime : time;
begin
theTime := now;
if theTime=10000 ps then
assert (Q=x"00000000")
report "Resultado erroneo a los " & time'image(theTime) & " Q=" & str(Q)
severity ERROR;
end if;
if theTime=70000 ps then
assert (Q=x"ffffffff")
report "Resultado erroneo a los " & time'image(theTime) & " Q=" & str(Q)
severity ERROR;
end if;
if theTime=80000 ps then
assert (Q=x"fffffffe")
report "Resultado erroneo a los " & time'image(theTime) & " Q=" & str(Q)
severity ERROR;
end if;
if theTime=90000 ps then
assert (Q=x"0000005a")
report "Resultado erroneo a los " & time'image(theTime) & " Q=" & str(Q)
severity ERROR;
end if;
if theTime=120000 ps then
assert (Q=x"00000057")
report "Resultado erroneo a los " & time'image(theTime) & " Q=" & str(Q)
severity ERROR;
end if;
if theTime=210000 ps then
assert (Q=x"00000052")
report "Resultado erroneo a los " & time'image(theTime) & " Q=" & str(Q)
severity ERROR;
end if;
end process;
END;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
use IEEE.NUMERIC_STD.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
ENTITY amplifier_tb IS
END amplifier_tb;
ARCHITECTURE behavior OF amplifier_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT amplifier
PORT(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
wave : in signed(31 downto 0);
percentage: in signed(31 downto 0);
amp : out signed(31 downto 0)
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal ce : std_logic := '1';
signal incr : signed(31 downto 0) := to_signed(integer(real( 0.1 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal incr2 : signed(31 downto 0) := to_signed(integer(real( 0.2 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
--Outputs
signal rmp : signed(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: amplifier PORT MAP (
clk => clk,
rst => rst,
ce => ce,
incr => incr,
incr2 => incr2,
rmp => rmp
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
library verilog;
use verilog.vl_types.all;
entity IDctr is
port(
Op : in vl_logic_vector(5 downto 0);
Func : in vl_logic_vector(5 downto 0);
Condition : out vl_logic_vector(2 downto 0);
Branch : out vl_logic;
MemWrite : out vl_logic;
RegWrite : out vl_logic;
MemRead : out vl_logic;
Jump : out vl_logic_vector(1 downto 0);
ExResultSrc : out vl_logic_vector(1 downto 0);
ALUSrcA : out vl_logic;
ALUSrcB : out vl_logic;
ALUOp : out vl_logic_vector(3 downto 0);
RegDst : out vl_logic_vector(1 downto 0);
ShiftAmountSrc : out vl_logic;
ShiftOp : out vl_logic_vector(1 downto 0);
IF_ID_RtRead : out vl_logic;
ExtendI : out vl_logic_vector(1 downto 0)
);
end IDctr;
|
-------------------------------------------------------------------------------
--
-- File: SyncAsync.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module synchronizes the asynchronous signal (aIn) with the OutClk clock
-- domain and provides it on oOut. The number of FFs in the synchronizer chain
-- can be configured with kStages. The reset value for oOut can be configured
-- with kResetTo. The asynchronous reset (aReset) is always active-high.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SyncAsync is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2; --double sync by default
kResetPolarity : std_logic := '1'); --aReset active-high by default
Port (
aReset : in STD_LOGIC; -- active-high/active-low asynchronous reset
aIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end SyncAsync;
architecture Behavioral of SyncAsync is
signal oSyncStages : std_logic_vector(kStages-1 downto 0) := (others => kResetTo);
attribute ASYNC_REG : string;
attribute ASYNC_REG of oSyncStages: signal is "TRUE";
begin
Sync: process (OutClk, aReset)
begin
if (aReset = kResetPolarity) then
oSyncStages <= (others => kResetTo);
elsif Rising_Edge(OutClk) then
oSyncStages <= oSyncStages(oSyncStages'high-1 downto 0) & aIn;
end if;
end process Sync;
oOut <= oSyncStages(oSyncStages'high);
end Behavioral;
|
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version:
-- \ \ Application: MIG
-- / / Filename: phy_rdlvl.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:13 $
-- \ \ / \ Date Created:
-- \___\/\___\
--
--Device: Virtex-6
--Design Name: DDR3 SDRAM
--Purpose:
-- Read leveling calibration logic
-- NOTES:
-- 1. DQ per-bit deskew is not yet supported
--Reference:
--Revision History:
--*****************************************************************************
--******************************************************************************
--**$Id: phy_rdlvl.vhd,v 1.1 2011/06/02 07:18:13 mishra Exp $
--**$Date: 2011/06/02 07:18:13 $
--**$Author: mishra $
--**$Revision: 1.1 $
--**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/vhdl/rtl/phy/phy_rdlvl.vhd,v $
--******************************************************************************
library unisim;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity phy_rdlvl is
generic (
TCQ : integer := 100; -- clk->out delay (sim only)
nCK_PER_CLK : integer := 2; -- # of memory clocks per CLK
CLK_PERIOD : integer := 3333; -- Internal clock period (in ps)
REFCLK_FREQ : integer := 300; -- IODELAY Reference Clock freq (MHz)
DQ_WIDTH : integer := 64; -- # of DQ (data)
DQS_CNT_WIDTH : integer := 3; -- = ceil(log2(DQS_WIDTH))
DQS_WIDTH : integer := 8; -- # of DQS (strobe)
DRAM_WIDTH : integer := 8; -- # of DQ per DQS
DRAM_TYPE : string := "DDR3"; -- Memory I/F type: "DDR3", "DDR2"
PD_TAP_REQ : integer := 10; -- # of IODELAY taps reserved for PD
nCL : integer := 5; -- Read CAS latency (in clk cyc)
SIM_CAL_OPTION : string := "NONE"; -- Skip various calibration steps
REG_CTRL : string := "ON"; -- "ON" for registered DIMM
DEBUG_PORT : string := "OFF" -- Enable debug port
);
port (
clk : in std_logic;
rst : in std_logic;
-- Calibration status, control signals
rdlvl_start : in std_logic_vector(1 downto 0);
rdlvl_clkdiv_start : in std_logic;
rdlvl_rd_active : in std_logic;
rdlvl_done : out std_logic_vector(1 downto 0);
rdlvl_clkdiv_done : out std_logic;
rdlvl_err : out std_logic_vector(1 downto 0);
rdlvl_prech_req : out std_logic;
prech_done : in std_logic;
-- Captured data in resync clock domain
rd_data_rise0 : in std_logic_vector(DQ_WIDTH - 1 downto 0);
rd_data_fall0 : in std_logic_vector(DQ_WIDTH - 1 downto 0);
rd_data_rise1 : in std_logic_vector(DQ_WIDTH - 1 downto 0);
rd_data_fall1 : in std_logic_vector(DQ_WIDTH - 1 downto 0);
-- Stage 1 calibration outputs
dlyce_cpt : out std_logic_vector(DQS_WIDTH - 1 downto 0);
dlyinc_cpt : out std_logic;
dlyce_rsync : out std_logic_vector(3 downto 0);
dlyinc_rsync : out std_logic;
dlyval_dq : out std_logic_vector(5*DQS_WIDTH - 1 downto 0);
dlyval_dqs : out std_logic_vector(5*DQS_WIDTH - 1 downto 0);
-- Stage 2 calibration inputs/outputs
rd_bitslip_cnt : out std_logic_vector(2*DQS_WIDTH - 1 downto 0);
rd_clkdly_cnt : out std_logic_vector(2*DQS_WIDTH - 1 downto 0);
rd_active_dly : out std_logic_vector(4 downto 0);
rdlvl_pat_resume : in std_logic; -- resume pattern cal
rdlvl_pat_err : out std_logic; -- error during pattern cal
rdlvl_pat_err_cnt : out std_logic_vector(DQS_CNT_WIDTH - 1 downto 0); -- erroring DQS group
-- Resynchronization clock (clkinv_inv) calibration outputs
rd_clkdiv_inv : out std_logic_vector(DQS_WIDTH - 1 downto 0);
-- Debug Port
dbg_cpt_first_edge_cnt : out std_logic_vector(5*DQS_WIDTH - 1 downto 0);
dbg_cpt_second_edge_cnt : out std_logic_vector(5*DQS_WIDTH - 1 downto 0);
dbg_rd_bitslip_cnt : out std_logic_vector(3*DQS_WIDTH - 1 downto 0);
dbg_rd_clkdiv_inv : out std_logic_vector(DQS_WIDTH - 1 downto 0);
dbg_rd_clkdly_cnt : out std_logic_vector(2*DQS_WIDTH - 1 downto 0);
dbg_rd_active_dly : out std_logic_vector(4 downto 0);
dbg_idel_up_all : in std_logic;
dbg_idel_down_all : in std_logic;
dbg_idel_up_cpt : in std_logic;
dbg_idel_down_cpt : in std_logic;
dbg_idel_up_rsync : in std_logic;
dbg_idel_down_rsync : in std_logic;
dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH - 1 downto 0);
dbg_sel_all_idel_cpt : in std_logic;
dbg_sel_idel_rsync : in std_logic_vector(DQS_CNT_WIDTH - 1 downto 0);
dbg_sel_all_idel_rsync : in std_logic;
dbg_phy_rdlvl : out std_logic_vector(255 downto 0)
);
end entity phy_rdlvl;
architecture arch of phy_rdlvl is
-- Function to 'and' all the bits of a signal
function AND_BR(inp_sig: std_logic_vector)
return std_logic is
variable return_var : std_logic := '1';
begin
for index in inp_sig'range loop
return_var := return_var and inp_sig(index);
end loop;
return return_var;
end function;
-- Function to 'OR' all the bits of a signal
function OR_BR(inp_sig: std_logic_vector(DQS_WIDTH-1 downto 0))
return std_logic is
variable return_var : std_logic := '0';
begin
for index in inp_sig'range loop
return_var := return_var or inp_sig(index);
end loop;
return return_var;
end function;
-- function calc_cnt_idel_dec_cpt (second_edge_taps_r, first_edge_taps_r: std_logic_vector) return std_logic_vector is
-- variable tmp : std_logic_vector (5 downto 0);
-- begin
-- tmp := std_logic_vector(unsigned(second_edge_taps_r - first_edge_taps_r) srl 1);
-- tmp := tmp + '1';
-- return tmp;
-- end function;
function calc_cnt_idel_dec_cpt (second_edge_taps_r, first_edge_taps_r: std_logic_vector) return std_logic_vector is
variable tmp : std_logic_vector (6 downto 0);
begin
tmp := std_logic_vector(to_unsigned(to_integer(signed('0' & second_edge_taps_r)) -
to_integer(signed('0' & first_edge_taps_r)), 7) srl 1) + '1';
return tmp(5 downto 0);
end function;
function add_vectors (opd1, opd2: std_logic_vector) return std_logic_vector is
variable tmp : std_logic_vector (5 downto 0);
begin
tmp := opd1 + ('0' & opd2);
return tmp(4 downto 0);
end function;
function subtract_vectors (opd1, opd2: std_logic_vector) return std_logic_vector is
variable tmp : std_logic_vector (5 downto 0);
begin
tmp := opd1 - ('0' & opd2);
return tmp(4 downto 0);
end function;
-- minimum time (in IDELAY taps) for which capture data must be stable for
-- algorithm to consider a valid data eye to be found. The read leveling
-- logic will ignore any window found smaller than this value. Limitations
-- on how small this number can be is determined by: (1) the algorithmic
-- limitation of how many taps wide the data eye can be (3 taps), and (2)
-- how wide regions of "instability" that occur around the edges of the
-- read valid window can be (i.e. need to be able to filter out "false"
-- windows that occur for a short # of taps around the edges of the true
-- data window, although with multi-sampling during read leveling, this is
-- not as much a concern) - the larger the value, the more protection
-- against "false" windows
function MIN_EYE_SIZE_CALC return integer is
begin
if (DRAM_TYPE = "DDR3") then
return 3;
else
return 6;
end if;
end function;
constant MIN_EYE_SIZE : integer := MIN_EYE_SIZE_CALC;
-- # of clock cycles to wait after changing IDELAY value or read data MUX
-- to allow both IDELAY chain to settle, and for delayed input to
-- propagate thru ISERDES
constant PIPE_WAIT_CNT : integer := 16;
-- Length of calibration sequence (in # of words)
constant CAL_PAT_LEN : integer := 8;
-- Read data shift register length
constant RD_SHIFT_LEN : integer := CAL_PAT_LEN / (2*nCK_PER_CLK);
-- Amount to shift by if one edge found (= 0.5*(bit_period)). Limit to 31
constant IODELAY_TAP_RES : integer := 1000000 / (REFCLK_FREQ * 64);
--Function to compare two vectors and return value if both vectors have true values (either 0s or 1s)
function ADVANCE_COMP(
input_a : std_logic_vector;
input_b : std_logic_vector
) return std_logic is
variable temp : std_logic_vector(RD_SHIFT_LEN-1 downto 0 ) := (others => '1');
begin
for i in input_a'range loop
if(((input_a(i) = '0') and (input_b(i) = '0')) or ((input_a(i) = '1') and (input_b(i) = '1'))) then
temp(i) := '1' ;
else
temp(i) := '0' ;
end if ;
end loop;
if((AND_BR(temp)) = '1' ) then
return '1' ;
else
return '0';
end if ;
end;
function CACL_TBY4_TAPS return integer is
begin
if ( ((CLK_PERIOD/nCK_PER_CLK/4) / IODELAY_TAP_RES) > 31) then
return (31);
else
return ((CLK_PERIOD/nCK_PER_CLK/4) / IODELAY_TAP_RES);
end if;
end function;
constant TBY4_TAPS : integer := CACL_TBY4_TAPS;
-- Maximum amount to wait after read issued until read data returned
constant MAX_RD_DLY_CNT : integer := 32;
-- # of cycles to wait after changing RDEN count value
constant RDEN_WAIT_CNT : integer := 8;
-- used during read enable calibration - difference between what the
-- calibration logic measured read enable delay to be, and what it needs
-- to set the value of the read active delay control to be
constant RDEN_DELAY_OFFSET : integer := 5;
-- # of read data samples to examine when detecting whether an edge has
-- occured during stage 1 calibration. Width of local param must be
-- changed as appropriate. Note that there are two counters used, each
-- counter can be changed independently of the other - they are used in
-- cascade to create a larger counter
constant DETECT_EDGE_SAMPLE_CNT0 : std_logic_vector(11 downto 0) := X"FFF";
constant DETECT_EDGE_SAMPLE_CNT1 : std_logic_vector(11 downto 0) := X"001";
-- # of taps in IDELAY chain. When the phase detector taps are reserved
-- before the start of calibration, reduce half that amount from the
-- total available taps.
constant IODELAY_TAP_LEN : integer := 32 - (PD_TAP_REQ/2);
-- Half the PD taps
constant PD_HALF_TAP : integer := (PD_TAP_REQ/2);
-- Type declarations for multi-dimensional arrays
type type_6 is array (0 to DQS_WIDTH-1) of std_logic_vector(4 downto 0);
type type_5 is array (3 downto 0) of std_logic_vector(RD_SHIFT_LEN - 1 downto 0);
type type_3 is array (DQS_WIDTH-1 downto 0) of std_logic_vector(4 downto 0);
type type_4 is array (DRAM_WIDTH-1 downto 0) of std_logic_vector(RD_SHIFT_LEN-1 downto 0);
constant CAL1_IDLE : std_logic_vector(4 downto 0) := "00000";
constant CAL1_NEW_DQS_WAIT : std_logic_vector(4 downto 0) := "00001";
constant CAL1_IDEL_STORE_FIRST : std_logic_vector(4 downto 0) := "00010";
constant CAL1_DETECT_EDGE : std_logic_vector(4 downto 0) := "00011";
constant CAL1_IDEL_STORE_OLD : std_logic_vector(4 downto 0) := "00100";
constant CAL1_IDEL_INC_CPT : std_logic_vector(4 downto 0) := "00101";
constant CAL1_IDEL_INC_CPT_WAIT : std_logic_vector(4 downto 0) := "00110";
constant CAL1_CALC_IDEL : std_logic_vector(4 downto 0) := "00111";
constant CAL1_IDEL_DEC_CPT : std_logic_vector(4 downto 0) := "01000";
constant CAL1_NEXT_DQS : std_logic_vector(4 downto 0) := "01001";
constant CAL1_DONE : std_logic_vector(4 downto 0) := "01010";
constant CAL1_RST_CPT : std_logic_vector(4 downto 0) := "01011";
constant CAL1_DETECT_EDGE_DQ : std_logic_vector(4 downto 0) := "01100";
constant CAL1_IDEL_INC_DQ : std_logic_vector(4 downto 0) := "01101";
constant CAL1_IDEL_INC_DQ_WAIT : std_logic_vector(4 downto 0) := "01110";
constant CAL1_CALC_IDEL_DQ : std_logic_vector(4 downto 0) := "01111";
constant CAL1_IDEL_INC_DQ_CPT : std_logic_vector(4 downto 0) := "10000";
constant CAL1_IDEL_INC_PD_CPT : std_logic_vector(4 downto 0) := "10001";
constant CAL1_IDEL_PD_ADJ : std_logic_vector(4 downto 0) := "10010";
constant CAL1_SKIP_RDLVL_INC_IDEL : std_logic_vector(4 downto 0) := "11111"; -- Only for simulation
constant CAL2_IDLE : std_logic_vector(2 downto 0) := "000";
constant CAL2_READ_WAIT : std_logic_vector(2 downto 0) := "001";
constant CAL2_DETECT_MATCH : std_logic_vector(2 downto 0) := "010";
constant CAL2_BITSLIP_WAIT : std_logic_vector(2 downto 0) := "011";
constant CAL2_NEXT_DQS : std_logic_vector(2 downto 0) := "100";
constant CAL2_DONE : std_logic_vector(2 downto 0) := "101";
constant CAL2_ERROR_TO : std_logic_vector(2 downto 0) := "110";
constant CAL_CLKDIV_IDLE : std_logic_vector(3 downto 0) := "0000";
constant CAL_CLKDIV_NEW_DQS_WAIT : std_logic_vector(3 downto 0) := "0001";
constant CAL_CLKDIV_IDEL_STORE_REF : std_logic_vector(3 downto 0) := "0010";
constant CAL_CLKDIV_DETECT_EDGE : std_logic_vector(3 downto 0) := "0011";
constant CAL_CLKDIV_IDEL_INCDEC_RSYNC : std_logic_vector(3 downto 0) := "0100";
constant CAL_CLKDIV_IDEL_INCDEC_RSYNC_WAIT : std_logic_vector(3 downto 0) := "0101";
constant CAL_CLKDIV_IDEL_SET_MIDPT_RSYNC : std_logic_vector(3 downto 0) := "0110";
constant CAL_CLKDIV_NEXT_CHECK : std_logic_vector(3 downto 0) := "0111";
constant CAL_CLKDIV_NEXT_DQS : std_logic_vector(3 downto 0) := "1000";
constant CAL_CLKDIV_DONE : std_logic_vector(3 downto 0) := "1001";
signal cal_clkdiv_clkdiv_inv_r : std_logic;
signal cal_clkdiv_cnt_clkdiv_r : std_logic_vector(DQS_CNT_WIDTH - 1 downto 0);
signal cal_clkdiv_dlyce_rsync_r : std_logic;
signal cal_clkdiv_dlyinc_rsync_r : std_logic;
signal cal_clkdiv_idel_rsync_inc_r : std_logic;
signal cal_clkdiv_prech_req_r : std_logic;
signal cal_clkdiv_store_sr_req_r : std_logic;
signal cal_clkdiv_state_r : std_logic_vector(3 downto 0);
signal cal1_cnt_cpt_r : std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
signal cal1_dlyce_cpt_r : std_logic;
signal cal1_dlyinc_cpt_r : std_logic;
signal cal1_dq_tap_cnt_r : std_logic_vector(4 downto 0);
signal cal1_dq_taps_inc_r : std_logic;
signal cal1_prech_req_r : std_logic;
signal cal1_found_edge : std_logic;
signal cal1_state_r : std_logic_vector(4 downto 0);
signal cal1_store_sr_req_r : std_logic;
signal cal2_clkdly_cnt_r : std_logic_vector(2*DQS_WIDTH - 1 downto 0);
signal cal2_cnt_bitslip_r : std_logic_vector(1 downto 0);
signal cal2_cnt_rd_dly_r : std_logic_vector(4 downto 0);
signal cal2_cnt_rden_r : std_logic_vector(DQS_CNT_WIDTH - 1 downto 0);
signal cal2_deskew_err_r : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal cal2_dly_cnt_delta_r : type_3;
signal cal2_done_r : std_logic;
signal cal2_done_r1 : std_logic;
signal cal2_done_r2 : std_logic;
signal cal2_done_r3 : std_logic;
signal cal2_dly_cnt_r : std_logic_vector(5*DQS_WIDTH - 1 downto 0);
signal cal2_en_dqs_skew_r : std_logic;
signal cal2_max_cnt_rd_dly_r : std_logic_vector(4 downto 0);
signal cal2_prech_req_r : std_logic;
signal cal2_rd_active_dly_r : std_logic_vector(4 downto 0);
signal cal2_rd_bitslip_cnt_r : std_logic_vector(2*DQS_WIDTH - 1 downto 0);
signal cal2_state_r : std_logic_vector(2 downto 0);
signal clkdiv_inv_r : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal cnt_eye_size_r : std_logic_vector(2 downto 0);
signal cnt_idel_dec_cpt_r : std_logic_vector(5 downto 0);
signal cnt_idel_inc_cpt_r : std_logic_vector(4 downto 0);
signal cnt_idel_skip_idel_r : std_logic_vector(4 downto 0);
signal cnt_pipe_wait_r : std_logic_vector(3 downto 0);
signal cnt_rden_wait_r : std_logic_vector(2 downto 0);
signal cnt_shift_r : std_logic_vector(3 downto 0);
signal detect_edge_cnt0_r : std_logic_vector(11 downto 0);
signal detect_edge_cnt1_en_r : std_logic;
signal detect_edge_cnt1_r : std_logic_vector(11 downto 0);
signal detect_edge_done_r : std_logic;
signal detect_edge_start_r : std_logic;
signal dlyce_or : std_logic;
signal dlyval_dq_reg_r : std_logic_vector(5*DQS_WIDTH - 1 downto 0);
signal first_edge_taps_r : std_logic_vector(4 downto 0);
signal found_edge_r : std_logic;
signal found_edge_latched_r : std_logic;
signal found_edge_valid_r : std_logic;
signal found_dq_edge_r : std_logic;
signal found_first_edge_r : std_logic;
signal found_jitter_latched_r : std_logic;
signal found_second_edge_r : std_logic;
signal found_stable_eye_r : std_logic;
signal found_two_edge_r : std_logic;
signal idel_tap_cnt_cpt_r : std_logic_vector(4 downto 0);
signal idel_tap_delta_rsync_r : std_logic_vector(4 downto 0);
signal idel_tap_limit_cpt_r : std_logic;
signal idel_tap_limit_dq_r : std_logic;
signal last_tap_jitter_r : std_logic;
signal min_rsync_marg_r : std_logic_vector(4 downto 0);
signal mux_rd_fall0_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal mux_rd_fall1_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal mux_rd_rise0_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal mux_rd_rise1_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal new_cnt_clkdiv_r : std_logic;
signal new_cnt_cpt_r : std_logic;
signal old_sr_fall0_r : type_4;
signal old_sr_fall1_r : type_4;
signal old_sr_rise0_r : type_4;
signal old_sr_rise1_r : type_4;
signal old_sr_valid_r : std_logic;
signal pat_data_match_r : std_logic;
signal pat_fall0 : type_5;
signal pat_fall1 : type_5;
signal pat_match_fall0_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal pat_match_fall0_and_r : std_logic;
signal pat_match_fall1_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal pat_match_fall1_and_r : std_logic;
signal pat_match_rise0_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal pat_match_rise0_and_r : std_logic;
signal pat_match_rise1_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal pat_match_rise1_and_r : std_logic;
signal pat_rise0 : type_5;
signal pat_rise1 : type_5;
signal pipe_wait : std_logic;
signal pol_min_rsync_marg_r : std_logic;
signal prev_found_edge_r : std_logic;
signal prev_found_edge_valid_r : std_logic;
signal prev_match_fall0_and_r : std_logic;
signal prev_match_fall0_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal prev_match_fall1_and_r : std_logic;
signal prev_match_fall1_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal prev_match_rise0_and_r : std_logic;
signal prev_match_rise0_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal prev_match_rise1_and_r : std_logic;
signal prev_match_rise1_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal prev_match_valid_r : std_logic;
signal prev_match_valid_r1 : std_logic;
signal prev_sr_fall0_r : type_4;
signal prev_sr_fall1_r : type_4;
signal prev_sr_rise0_r : type_4;
signal prev_sr_rise1_r : type_4;
signal rd_mux_sel_r : std_logic_vector(DQS_CNT_WIDTH - 1 downto 0);
signal rd_active_posedge_r : std_logic;
signal rd_active_r : std_logic;
signal rden_wait_r : std_logic;
signal right_edge_taps_r : std_logic_vector(4 downto 0);
signal second_edge_taps_r : std_logic_vector(4 downto 0);
signal second_edge_dq_taps_r : std_logic_vector(4 downto 0);
signal sr_fall0_r : type_4;
signal sr_fall1_r : type_4;
signal sr_rise0_r : type_4;
signal sr_rise1_r : type_4;
signal sr_match_fall0_and_r : std_logic;
signal sr_match_fall0_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal sr_match_fall1_and_r : std_logic;
signal sr_match_fall1_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal sr_match_valid_r : std_logic;
signal sr_match_valid_r1 : std_logic;
signal sr_match_rise0_and_r : std_logic;
signal sr_match_rise0_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal sr_match_rise1_and_r : std_logic;
signal sr_match_rise1_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal store_sr_done_r : std_logic;
signal store_sr_r : std_logic;
signal store_sr_req : std_logic;
signal sr_valid_r : std_logic;
signal tby4_r : std_logic_vector(5 downto 0);
signal dbg_phy_clk : std_logic;
-- Debug
signal dbg_cpt_first_edge_taps : type_6;
signal dbg_cpt_second_edge_taps : type_6;
-- Declare intermediate signals for referenced outputs
signal rdlvl_clkdiv_done_1 : std_logic;
signal rdlvl_done_1 : std_logic_vector(1 downto 0);
signal rdlvl_err_2 : std_logic_vector(1 downto 0);
-- Declare intermediate signals for referenced outputs
signal rd_mux_sel_r_index : std_logic_vector(1 downto 0);
begin
-- Drive referenced outputs
rdlvl_done <= rdlvl_done_1;
rdlvl_err <= rdlvl_err_2;
rdlvl_clkdiv_done <= rdlvl_clkdiv_done_1;
--***************************************************************************
-- Debug
--***************************************************************************
dbg_phy_rdlvl(1 downto 0) <= rdlvl_start(1 downto 0);
dbg_phy_rdlvl(2) <= found_edge_r;
dbg_phy_rdlvl(3) <= pat_data_match_r;
dbg_phy_rdlvl(6 downto 4) <= cal2_state_r(2 downto 0);
dbg_phy_rdlvl(8 downto 7) <= cal2_cnt_bitslip_r(1 downto 0);
dbg_phy_rdlvl(13 downto 9) <= cal1_state_r(4 downto 0);
dbg_phy_rdlvl(20 downto 14) <= ('0' & cnt_idel_dec_cpt_r);
dbg_phy_rdlvl(21) <= found_first_edge_r;
dbg_phy_rdlvl(22) <= found_second_edge_r;
dbg_phy_rdlvl(23) <= old_sr_valid_r;
dbg_phy_rdlvl(24) <= store_sr_r;
dbg_phy_rdlvl(32 downto 25) <= (sr_fall1_r(0)(1 downto 0) & sr_rise1_r(0)(1 downto 0) &
sr_fall0_r(0)(1 downto 0) & sr_rise0_r(0)(1 downto 0));
dbg_phy_rdlvl(40 downto 33) <= (old_sr_fall1_r(0)(1 downto 0) & old_sr_rise1_r(0)(1 downto 0) &
old_sr_fall0_r(0)(1 downto 0) & old_sr_rise0_r(0)(1 downto 0));
dbg_phy_rdlvl(41) <= sr_valid_r;
dbg_phy_rdlvl(42) <= found_stable_eye_r;
dbg_phy_rdlvl(47 downto 43) <= idel_tap_cnt_cpt_r;
dbg_phy_rdlvl(48) <= idel_tap_limit_cpt_r;
dbg_phy_rdlvl(53 downto 49) <= first_edge_taps_r;
dbg_phy_rdlvl(58 downto 54) <= second_edge_taps_r;
dbg_phy_rdlvl(64 downto 59) <= tby4_r;
dbg_phy_rdlvl(67 downto 65) <= cnt_eye_size_r;
dbg_phy_rdlvl(72 downto 68) <= cal1_dq_tap_cnt_r;
dbg_phy_rdlvl(73) <= found_dq_edge_r;
dbg_phy_rdlvl(74) <= found_edge_valid_r;
gen_72width: if (DQS_CNT_WIDTH < 5) generate
dbg_phy_rdlvl(75+DQS_CNT_WIDTH-1 downto 75) <= cal1_cnt_cpt_r;
dbg_phy_rdlvl(78 downto 75+DQS_CNT_WIDTH) <= (others => '0');
dbg_phy_rdlvl(79+DQS_CNT_WIDTH-1 downto 79) <= cal2_cnt_rden_r;
dbg_phy_rdlvl(82 downto 79+DQS_CNT_WIDTH) <= (others => '0');
end generate;
gen_144width: if (DQS_CNT_WIDTH = 5) generate
dbg_phy_rdlvl(78 downto 75) <= cal1_cnt_cpt_r(DQS_CNT_WIDTH-2 downto 0);
dbg_phy_rdlvl(82 downto 79) <= cal2_cnt_rden_r(DQS_CNT_WIDTH-2 downto 0);
end generate;
dbg_phy_rdlvl(83) <= cal1_dlyce_cpt_r;
dbg_phy_rdlvl(84) <= cal1_dlyinc_cpt_r;
dbg_phy_rdlvl(85) <= found_edge_r;
dbg_phy_rdlvl(86) <= found_first_edge_r;
dbg_phy_rdlvl(91 downto 87) <= right_edge_taps_r;
dbg_phy_rdlvl(96 downto 92) <= second_edge_dq_taps_r;
dbg_phy_rdlvl(102 downto 97) <= tby4_r;
dbg_phy_rdlvl(103) <= cal_clkdiv_clkdiv_inv_r;
dbg_phy_rdlvl(104) <= cal_clkdiv_dlyce_rsync_r;
dbg_phy_rdlvl(105) <= cal_clkdiv_dlyinc_rsync_r;
dbg_phy_rdlvl(106) <= cal_clkdiv_idel_rsync_inc_r;
dbg_phy_rdlvl(107) <= pol_min_rsync_marg_r;
dbg_phy_rdlvl(111 downto 108) <= cal_clkdiv_state_r;
gen_dbg_cal_clkdiv_cnt_clkdiv_r_lt4: if (DQS_CNT_WIDTH < 4) generate
dbg_phy_rdlvl(112+DQS_CNT_WIDTH-1 downto 112) <= cal_clkdiv_cnt_clkdiv_r;
dbg_phy_rdlvl(115 downto 112+DQS_CNT_WIDTH) <= (others => '0');
end generate;
gen_dbg_cal_clkdiv_cnt_clkdiv_r_ge4: if (DQS_CNT_WIDTH >= 4) generate
dbg_phy_rdlvl(115 downto 112) <= cal_clkdiv_cnt_clkdiv_r(3 downto 0);
end generate;
dbg_phy_rdlvl(120 downto 116) <= idel_tap_delta_rsync_r;
dbg_phy_rdlvl(125 downto 121) <= min_rsync_marg_r;
gen_dbg_clkdiv_inv_r_lt9: if (DQS_WIDTH < 9) generate
dbg_phy_rdlvl(126+DQS_WIDTH-1 downto 126) <= clkdiv_inv_r;
dbg_phy_rdlvl(134 downto 126+DQS_WIDTH) <= (others => '0');
end generate;
gen_dbg_clkdiv_inv_r_ge9: if (DQS_WIDTH >= 9) generate
dbg_phy_rdlvl(134 downto 126) <= clkdiv_inv_r(8 downto 0);
end generate;
dbg_phy_rdlvl(135) <= rdlvl_clkdiv_start;
dbg_phy_rdlvl(136) <= rdlvl_clkdiv_done_1;
dbg_phy_rdlvl(255 downto 137) <= (others => '0');
--***************************************************************************
-- Debug output
--***************************************************************************
-- Record first and second edges found during CPT calibration
gen_dbg_cpt_edge : for ce_i in 0 to (DQS_WIDTH-1) generate
dbg_cpt_first_edge_cnt((5*ce_i)+4 downto (5*ce_i)) <= dbg_cpt_first_edge_taps(ce_i);
dbg_cpt_second_edge_cnt((5*ce_i)+4 downto (5*ce_i)) <= dbg_cpt_second_edge_taps(ce_i);
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
dbg_cpt_first_edge_taps(ce_i) <= (others => '0') after (TCQ)*1 ps;
dbg_cpt_second_edge_taps(ce_i) <= (others => '0') after (TCQ)*1 ps;
else
-- Record tap counts of first and second edge edges during
-- CPT calibration for each DQS group. If neither edge has
-- been found, then those taps will remain 0
if ((cal1_state_r = CAL1_CALC_IDEL) or (cal1_state_r = CAL1_RST_CPT)) then
if (found_first_edge_r = '1' and (TO_INTEGER(unsigned(cal1_cnt_cpt_r)) = ce_i)) then
dbg_cpt_first_edge_taps(ce_i) <= first_edge_taps_r after (TCQ)*1 ps;
end if;
if (found_second_edge_r = '1' and (TO_INTEGER(unsigned(cal1_cnt_cpt_r)) = ce_i)) then
dbg_cpt_second_edge_taps(ce_i) <= second_edge_taps_r after (TCQ)*1 ps;
end if;
end if;
end if;
end if;
end process;
end generate;
process (clk)
begin
if (clk'event and clk = '1') then
dbg_rd_active_dly <= cal2_rd_active_dly_r after (TCQ)*1 ps;
dbg_rd_clkdly_cnt <= cal2_clkdly_cnt_r after (TCQ)*1 ps;
end if;
end process;
-- cal2_rd_bitslip_cnt_r is only 2*DQS_WIDTH (2 bits per DQS group), but
-- is expanded to 3 bits per DQS group to maintain width compatibility with
-- previous definition of dbg_rd_bitslip_cnt (not a huge issue, should
-- align these eventually - minimize impact on debug designs)
gen_dbg_rd_bitslip : for d_i in 0 to DQS_WIDTH-1 generate
process (clk)
begin
if (clk'event and clk = '1') then
dbg_rd_bitslip_cnt(3*d_i+1 downto 3*d_i) <= cal2_rd_bitslip_cnt_r(2*d_i+1 downto 2*d_i) after (TCQ)*1 ps;
dbg_rd_bitslip_cnt(3*d_i+2) <= '0' after (TCQ)*1 ps;
end if;
end process;
end generate;
--***************************************************************************
-- Data mux to route appropriate bit to calibration logic - i.e. calibration
-- is done sequentially, one bit (or DQS group) at a time
--***************************************************************************
rd_mux_sel_r_index <= rdlvl_clkdiv_done_1 & rdlvl_done_1(0);
process (clk)
begin
if (clk'event and clk = '1') then
--(* full_case, parallel_case *)
case (rd_mux_sel_r_index) is
when "00" =>
rd_mux_sel_r <= cal1_cnt_cpt_r after (TCQ)*1 ps;
when "01" =>
rd_mux_sel_r <= cal_clkdiv_cnt_clkdiv_r after (TCQ)*1 ps;
when "10" =>
rd_mux_sel_r <= cal2_cnt_rden_r after (TCQ)*1 ps; -- don't care
when "11" =>
rd_mux_sel_r <= cal2_cnt_rden_r after (TCQ)*1 ps;
when others =>
null;
end case;
end if;
end process;
-- Register outputs for improved timing.
-- NOTE: Will need to change when per-bit DQ deskew is supported.
-- Currenly all bits in DQS group are checked in aggregate
gen_mux_rd : for mux_i in 0 to DRAM_WIDTH-1 generate
process (clk)
begin
if (clk'event and clk = '1') then
mux_rd_rise0_r(mux_i) <= rd_data_rise0(DRAM_WIDTH*to_integer(unsigned(rd_mux_sel_r)) + mux_i) after (TCQ)*1 ps;
mux_rd_fall0_r(mux_i) <= rd_data_fall0(DRAM_WIDTH*to_integer(unsigned(rd_mux_sel_r)) + mux_i) after (TCQ)*1 ps;
mux_rd_rise1_r(mux_i) <= rd_data_rise1(DRAM_WIDTH*to_integer(unsigned(rd_mux_sel_r)) + mux_i) after (TCQ)*1 ps;
mux_rd_fall1_r(mux_i) <= rd_data_fall1(DRAM_WIDTH*to_integer(unsigned(rd_mux_sel_r)) + mux_i) after (TCQ)*1 ps;
end if;
end process;
end generate;
--***************************************************************************
-- Demultiplexor to control IODELAY tap values
--***************************************************************************
-- Capture clock
process (clk)
begin
if (clk'event and clk = '1') then
dlyce_cpt <= (others => '0') after (TCQ)*1 ps;
dlyinc_cpt <= '0' after (TCQ)*1 ps;
if (cal1_dlyce_cpt_r = '1') then
if ((SIM_CAL_OPTION = "NONE") or (SIM_CAL_OPTION = "FAST_WIN_DETECT")) then
-- Change only specified DQS group's capture clock
dlyce_cpt(to_integer(unsigned(rd_mux_sel_r))) <= '1' after (TCQ)*1 ps;
dlyinc_cpt <= cal1_dlyinc_cpt_r after (TCQ)*1 ps;
elsif ((SIM_CAL_OPTION = "FAST_CAL") or (SIM_CAL_OPTION = "SKIP_CAL")) then
-- if simulating, and "shortcuts" for calibration enabled, apply
-- results to all other elements (i.e. assume delay on all
-- bits/bytes is same). Also do the same if skipping calibration
-- (the logic will still increment IODELAY to the "hardcoded" value)
dlyce_cpt <= (others => '1') after (TCQ)*1 ps;
dlyinc_cpt <= cal1_dlyinc_cpt_r after (TCQ)*1 ps;
end if;
elsif (DEBUG_PORT = "ON") then
-- simultaneously inc/dec all CPT idelays
if ((dbg_idel_up_all or dbg_idel_down_all or dbg_sel_all_idel_cpt) = '1') then
dlyce_cpt <= (others => (dbg_idel_up_all or dbg_idel_down_all or dbg_idel_up_cpt or dbg_idel_down_cpt)) after (TCQ)*1 ps;
dlyinc_cpt <= dbg_idel_up_all or dbg_idel_up_cpt after (TCQ)*1 ps;
else
-- select specific cpt clock for adjustment
if (to_integer(unsigned(dbg_sel_idel_cpt)) < DQS_WIDTH) then
dlyce_cpt(to_integer(unsigned(dbg_sel_idel_cpt))) <= dbg_idel_up_cpt or dbg_idel_down_cpt after (TCQ)*1 ps;
end if;
dlyinc_cpt <= dbg_idel_up_cpt after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
-- Resync clock
process (clk)
begin
if (clk'event and clk = '1') then
dlyce_rsync <= (others => '0') after (TCQ)*1 ps;
dlyinc_rsync <= '0' after (TCQ)*1 ps;
if (cal_clkdiv_dlyce_rsync_r = '1') then
-- When shifting RSYNC, shift all BUFR IODELAYs. This is allowed
-- because only one DQS-group's data is being checked at any one
-- time, and at the end of calibration, all of the BUFR IODELAYs
-- will be reset to the starting tap value
dlyce_rsync <= (others => '1') after (TCQ)*1 ps;
dlyinc_rsync <= cal_clkdiv_dlyinc_rsync_r after (TCQ)*1 ps;
elsif (DEBUG_PORT = "ON") then
-- simultaneously inc/dec all RSYNC idelays
if ((dbg_idel_up_all or dbg_idel_down_all or dbg_sel_all_idel_rsync) = '1') then
dlyce_rsync <= (others => (dbg_idel_up_all or dbg_idel_down_all or dbg_idel_up_rsync or dbg_idel_down_rsync)) after (TCQ)*1 ps;
dlyinc_rsync <= dbg_idel_up_all or dbg_idel_up_rsync after (TCQ)*1 ps;
else
-- select specific rsync clock for adjustment
if (to_integer(unsigned(dbg_sel_idel_rsync)) < 4) then
dlyce_rsync(to_integer(unsigned(dbg_sel_idel_rsync))) <= (dbg_idel_up_rsync or dbg_idel_down_rsync) after (TCQ)*1 ps;
end if;
dlyinc_rsync <= dbg_idel_up_rsync after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
-- DQ parallel load tap values
-- Currently no debug port option to change DQ taps
-- NOTE: This values are not initially assigned after reset - until
-- a particular byte is being calibrated, the IDELAY dlyval values from
-- this module will be X's in simulation - this will be okay - those
-- IDELAYs won't be used until the byte is calibrated
process (clk)
begin
if (clk'event and clk = '1') then
-- If read leveling is not complete, calibration logic has complete
-- control of loading of DQ IDELAY taps
if ((SIM_CAL_OPTION = "NONE") or (SIM_CAL_OPTION = "FAST_WIN_DETECT")) then
-- Load all IDELAY value for all bits in that byte with the same
-- value. Eventually this will be changed to accomodate different
-- tap counts across the bits in a DQS group (i.e. "per-bit" cal)
for i in 0 to 4 loop
dlyval_dq_reg_r(5*to_integer(unsigned(cal1_cnt_cpt_r))+ i) <= cal1_dq_tap_cnt_r(i) after (TCQ)*1 ps;
end loop;
elsif (SIM_CAL_OPTION = "FAST_CAL") then
-- For simulation purposes, to reduce time associated with
-- calibration, calibrate only one DQS group, and load all IODELAY
-- values for all DQS groups with same value
for idx in 0 to (DQS_WIDTH-1) loop
dlyval_dq_reg_r(5*idx+4 downto 5*idx) <= cal1_dq_tap_cnt_r after (TCQ)*1 ps;
end loop;
elsif (SIM_CAL_OPTION = "SKIP_CAL") then
-- If skipping calibration altogether (only for simulation), set
-- all the DQ IDELAY delay values to 0
dlyval_dq_reg_r <= (others => '0') after (TCQ)*1 ps;
end if;
end if;
end process;
-- Register for timing (help with logic placement) - we're gonna need
-- all the help we can get
-- dlyval_dqs is assigned the value of dq taps. It is used in the PD module.
-- Changes will be made to this assignment when perbit deskew is done.
process (clk)
begin
if (clk'event and clk = '1') then
dlyval_dq <= dlyval_dq_reg_r after (TCQ)*1 ps;
dlyval_dqs <= dlyval_dq_reg_r after (TCQ)*1 ps;
end if;
end process;
--***************************************************************************
-- Generate signal used to delay calibration state machine - used when:
-- (1) IDELAY value changed
-- (2) RD_MUX_SEL value changed
-- Use when a delay is necessary to give the change time to propagate
-- through the data pipeline (through IDELAY and ISERDES, and fabric
-- pipeline stages)
--***************************************************************************
-- combine requests to modify any of the IDELAYs into one
dlyce_or <= '1' when (cal1_state_r = CAL1_IDEL_INC_DQ) else
(cal1_dlyce_cpt_r or new_cnt_cpt_r or
cal_clkdiv_dlyce_rsync_r or new_cnt_clkdiv_r);
-- NOTE: Can later recode to avoid combinational path, but be careful about
-- timing effect on main state logic
pipe_wait <= '1' when (to_integer(unsigned(cnt_pipe_wait_r)) /= (PIPE_WAIT_CNT-1)) else dlyce_or;
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
cnt_pipe_wait_r <= "0000" after (TCQ)*1 ps;
elsif (dlyce_or = '1') then
cnt_pipe_wait_r <= "0000" after (TCQ)*1 ps;
elsif (to_integer(unsigned(cnt_pipe_wait_r)) /= (PIPE_WAIT_CNT-1)) then
cnt_pipe_wait_r <= cnt_pipe_wait_r + "0001" after (TCQ)*1 ps;
end if;
end if;
end process;
--***************************************************************************
-- generate request to PHY_INIT logic to issue precharged. Required when
-- calibration can take a long time (during which there are only constant
-- reads present on this bus). In this case need to issue perioidic
-- precharges to avoid tRAS violation. This signal must meet the following
-- requirements: (1) only transition from 0->1 when prech is first needed,
-- (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted
--***************************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
rdlvl_prech_req <= '0' after (TCQ)*1 ps;
else
-- Combine requests from all stages here
rdlvl_prech_req <= cal1_prech_req_r or cal2_prech_req_r or
cal_clkdiv_prech_req_r after (TCQ)*1 ps;
end if;
end if;
end process;
--***************************************************************************
-- Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES
-- NOTE: Written using discrete flops, but SRL can be used if the matching
-- logic does the comparison sequentially, rather than parallel
--***************************************************************************
gen_sr : for rd_i in 0 to DRAM_WIDTH-1 generate
process (clk)
begin
if (clk'event and clk = '1') then
sr_rise0_r(rd_i) <= sr_rise0_r(rd_i)(RD_SHIFT_LEN - 2 downto 0) & mux_rd_rise0_r(rd_i) after (TCQ)*1 ps;
sr_fall0_r(rd_i) <= sr_fall0_r(rd_i)(RD_SHIFT_LEN - 2 downto 0) & mux_rd_fall0_r(rd_i) after (TCQ)*1 ps;
sr_rise1_r(rd_i) <= sr_rise1_r(rd_i)(RD_SHIFT_LEN - 2 downto 0) & mux_rd_rise1_r(rd_i) after (TCQ)*1 ps;
sr_fall1_r(rd_i) <= sr_fall1_r(rd_i)(RD_SHIFT_LEN - 2 downto 0) & mux_rd_fall1_r(rd_i) after (TCQ)*1 ps;
end if;
end process;
end generate;
--***************************************************************************
-- First stage calibration: Capture clock
--***************************************************************************
--*****************************************************************
-- Free-running counter to keep track of when to do parallel load of
-- data from memory
--*****************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
cnt_shift_r <= (others => '0') after (TCQ)*1 ps;
sr_valid_r <= '0' after (TCQ)*1 ps;
else
if (to_integer(unsigned(cnt_shift_r)) = (RD_SHIFT_LEN-1)) then
sr_valid_r <= '1' after (TCQ)*1 ps;
cnt_shift_r <= (others => '0') after (TCQ)*1 ps;
else
sr_valid_r <= '0' after (TCQ)*1 ps;
cnt_shift_r <= cnt_shift_r + "0001" after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
--*****************************************************************
-- Logic to determine when either edge of the data eye encountered
-- Pre- and post-IDELAY update data pattern is compared, if they
-- differ, than an edge has been encountered. Currently no attempt
-- made to determine if the data pattern itself is "correct", only
-- whether it changes after incrementing the IDELAY (possible
-- future enhancement)
--*****************************************************************
store_sr_req <= cal1_store_sr_req_r or cal_clkdiv_store_sr_req_r;
-- Simple handshaking - when calib state machines want the OLD SR
-- value to get loaded, it requests for it to be loaded. One the
-- next sr_valid_r pulse, it does get loaded, and store_sr_done_r
-- is then pulsed asserted to indicate this, and we all go on our
-- merry way
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
store_sr_done_r <= '0' after (TCQ)*1 ps;
store_sr_r <= '0' after (TCQ)*1 ps;
else
store_sr_done_r <= sr_valid_r and store_sr_r;
if (store_sr_req = '1') then
store_sr_r <= '1' after (TCQ)*1 ps;
elsif ((sr_valid_r and store_sr_r) = '1') then
store_sr_r <= '0' after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
-- Determine if the comparison logic is putting out a valid
-- output - as soon as a request is made to load in a new value
-- for the OLD_SR shift register, the valid pipe is cleared. It
-- then gets asserted once the new value gets loaded into the
-- OLD_SR register
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
sr_match_valid_r <= '0' after (TCQ)*1 ps;
sr_match_valid_r1 <= '0' after (TCQ)*1 ps;
old_sr_valid_r <= '0' after (TCQ)*1 ps;
else
-- Flag to indicate whether data in OLD_SR register is valid
if (store_sr_req = '1') then
old_sr_valid_r <= '0' after (TCQ)*1 ps;
elsif (store_sr_done_r = '1') then
-- Immediately flush valid pipe to prevent any logic from
-- acting on compare results using previous OLD_SR data
old_sr_valid_r <= '1' after (TCQ)*1 ps;
end if;
if (store_sr_req = '1') then
sr_match_valid_r <= '0' after (TCQ)*1 ps;
sr_match_valid_r1 <= '0' after (TCQ)*1 ps;
else
sr_match_valid_r <= old_sr_valid_r and sr_valid_r after (TCQ)*1 ps;
sr_match_valid_r1 <= sr_match_valid_r after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
-- Create valid qualifier for previous sample compare - might not
-- be needed - check previous sample compare timing
process(clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
prev_match_valid_r <= '0' after (TCQ)*1 ps;
prev_match_valid_r1 <= '0' after (TCQ)*1 ps;
else
prev_match_valid_r <= sr_valid_r after (TCQ)*1 ps;
prev_match_valid_r1 <= prev_match_valid_r after (TCQ)*1 ps;
end if;
end if;
end process;
-- Transfer current data to old data, prior to incrementing IDELAY
gen_old_sr : for z in 0 to DRAM_WIDTH-1 generate
process (clk)
begin
if (clk'event and clk = '1') then
if (sr_valid_r = '1') then
-- Load last sample (i.e. from current sampling interval)
prev_sr_rise0_r(z) <= sr_rise0_r(z) after (TCQ)*1 ps;
prev_sr_fall0_r(z) <= sr_fall0_r(z) after (TCQ)*1 ps;
prev_sr_rise1_r(z) <= sr_rise1_r(z) after (TCQ)*1 ps;
prev_sr_fall1_r(z) <= sr_fall1_r(z) after (TCQ)*1 ps;
end if;
if ((sr_valid_r and store_sr_r) = '1') then
old_sr_rise0_r(z) <= sr_rise0_r(z) after (TCQ)*1 ps;
old_sr_fall0_r(z) <= sr_fall0_r(z) after (TCQ)*1 ps;
old_sr_rise1_r(z) <= sr_rise1_r(z) after (TCQ)*1 ps;
old_sr_fall1_r(z) <= sr_fall1_r(z) after (TCQ)*1 ps;
end if;
end if;
end process;
end generate;
--*******************************************************
-- Match determination occurs over 3 cycles - pipelined for better timing
--*******************************************************
-- CYCLE1: Compare all bits in DQS grp, generate separate term for each
-- bit for each cycle of training seq. For example, if training seq = 4
-- words, and there are 8-bits per DQS group, then there is total of
-- 8*4 = 32 terms generated in this cycle
gen_sr_match : for sh_i in 0 to DRAM_WIDTH-1 generate
process (clk)
begin
if (clk'event and clk = '1') then
if (sr_valid_r = '1') then
-- Structure HDL such that X on data bus will result in a mismatch
-- This is required for memory models that can drive the bus with
-- X's to model uncertainty regions (e.g. Denali)
-- Check current sample vs. sample from last IODELAY tap
--if (sr_rise0_r(sh_i) = old_sr_rise0_r(sh_i)) then
if (ADVANCE_COMP(sr_rise0_r(sh_i),old_sr_rise0_r(sh_i)) = '1') then
sr_match_rise0_r(sh_i) <= '1' after (TCQ)*1 ps;
else
sr_match_rise0_r(sh_i) <= '0' after (TCQ)*1 ps;
end if;
--if (sr_fall0_r(sh_i) = old_sr_fall0_r(sh_i)) then
if (ADVANCE_COMP(sr_fall0_r(sh_i),old_sr_fall0_r(sh_i)) = '1') then
sr_match_fall0_r(sh_i) <= '1' after (TCQ)*1 ps;
else
sr_match_fall0_r(sh_i) <= '0' after (TCQ)*1 ps;
end if;
--if (sr_rise1_r(sh_i) = old_sr_rise1_r(sh_i)) then
if (ADVANCE_COMP(sr_rise1_r(sh_i),old_sr_rise1_r(sh_i)) = '1') then
sr_match_rise1_r(sh_i) <= '1' after (TCQ)*1 ps;
else
sr_match_rise1_r(sh_i) <= '0' after (TCQ)*1 ps;
end if;
--if (sr_fall1_r(sh_i) = old_sr_fall1_r(sh_i)) then
if (ADVANCE_COMP(sr_fall1_r(sh_i),old_sr_fall1_r(sh_i)) = '1') then
sr_match_fall1_r(sh_i) <= '1' after (TCQ)*1 ps;
else
sr_match_fall1_r(sh_i) <= '0' after (TCQ)*1 ps;
end if;
-- Check current sample vs. sample from current IODELAY tap
--if (sr_rise0_r(sh_i) = prev_sr_rise0_r(sh_i)) then
if (ADVANCE_COMP(sr_rise0_r(sh_i),prev_sr_rise0_r(sh_i)) = '1') then
prev_match_rise0_r(sh_i) <= '1' after (TCQ)*1 ps;
else
prev_match_rise0_r(sh_i) <= '0' after (TCQ)*1 ps;
end if;
--if (sr_fall0_r(sh_i) = prev_sr_fall0_r(sh_i)) then
if (ADVANCE_COMP(sr_fall0_r(sh_i),prev_sr_fall0_r(sh_i)) = '1') then
prev_match_fall0_r(sh_i) <= '1' after (TCQ)*1 ps;
else
prev_match_fall0_r(sh_i) <= '0' after (TCQ)*1 ps;
end if;
--if (sr_rise1_r(sh_i) = prev_sr_rise1_r(sh_i)) then
if (ADVANCE_COMP(sr_rise1_r(sh_i),prev_sr_rise1_r(sh_i)) = '1') then
prev_match_rise1_r(sh_i) <= '1' after (TCQ)*1 ps;
else
prev_match_rise1_r(sh_i) <= '0' after (TCQ)*1 ps;
end if;
--if (sr_fall1_r(sh_i) = prev_sr_fall1_r(sh_i)) then
if (ADVANCE_COMP(sr_fall1_r(sh_i),prev_sr_fall1_r(sh_i)) = '1') then
prev_match_fall1_r(sh_i) <= '1' after (TCQ)*1 ps;
else
prev_match_fall1_r(sh_i) <= '0' after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
end generate;
-- CYCLE 2: Logical AND match terms from all bits in DQS group together
process (clk)
begin
if (clk'event and clk = '1') then
-- Check current sample vs. sample from last IODELAY tap
sr_match_rise0_and_r <= AND_BR(sr_match_rise0_r) after (TCQ)*1 ps;
sr_match_fall0_and_r <= AND_BR(sr_match_fall0_r) after (TCQ)*1 ps;
sr_match_rise1_and_r <= AND_BR(sr_match_rise1_r) after (TCQ)*1 ps;
sr_match_fall1_and_r <= AND_BR(sr_match_fall1_r) after (TCQ)*1 ps;
-- Check current sample vs. sample from current IODELAY tap
prev_match_rise0_and_r <= AND_BR(prev_match_rise0_r) after (TCQ)*1 ps;
prev_match_fall0_and_r <= AND_BR(prev_match_fall0_r) after (TCQ)*1 ps;
prev_match_rise1_and_r <= AND_BR(prev_match_rise1_r) after (TCQ)*1 ps;
prev_match_fall1_and_r <= AND_BR(prev_match_fall1_r) after (TCQ)*1 ps;
end if;
end process;
-- CYCLE 3: During the third cycle of compare, the comparison output
-- over all the cycles of the training sequence is output
process (clk)
begin
if (clk'event and clk = '1') then
-- Found edge only asserted if OLD_SR shift register contents are valid
-- and a match has not occurred - since we're using this shift register
-- scheme, we need to qualify the match with the valid signals because
-- the "old" and "current" shift register contents can't be compared on
-- every clock cycle, only when the shift register is "fully loaded"
found_edge_r <= ((not(sr_match_rise0_and_r) or not(sr_match_fall0_and_r) or
not(sr_match_rise1_and_r) or not(sr_match_fall1_and_r)) and
(sr_match_valid_r1)) after (TCQ)*1 ps;
found_edge_valid_r <= sr_match_valid_r1 after (TCQ)*1 ps;
prev_found_edge_r <= ((not(prev_match_rise0_and_r) or not(prev_match_fall0_and_r) or
not(prev_match_rise1_and_r) or not(prev_match_fall1_and_r)) and
(prev_match_valid_r1)) after (TCQ)*1 ps;
prev_found_edge_valid_r <= prev_match_valid_r1 after (TCQ)*1 ps;
end if;
end process;
--*******************************************************
-- Counters for tracking # of samples compared
-- For each comparision point (i.e. to determine if an edge has
-- occurred after each IODELAY increment when read leveling),
-- multiple samples are compared in order to average out the effects
-- of jitter. If any one of these samples is different than the "old"
-- sample corresponding to the previous IODELAY value, then an edge
-- is declared to be detected.
--*******************************************************
-- Two counters are used to keep track of # of samples compared, in
-- order to make it easier to meeting timing on these paths
-- First counter counts the number of samples directly
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
detect_edge_cnt0_r <= (others => '0') after (TCQ)*1 ps;
else
if (detect_edge_start_r = '1') then
detect_edge_cnt0_r <= (others => '0') after (TCQ)*1 ps;
elsif (found_edge_valid_r = '1') then
detect_edge_cnt0_r <= detect_edge_cnt0_r + '1' after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
detect_edge_cnt1_en_r <= '0' after (TCQ)*1 ps;
else
if (((SIM_CAL_OPTION = "FAST_CAL") or (SIM_CAL_OPTION = "FAST_WIN_DETECT")) and (detect_edge_cnt0_r = X"001")) then
-- Bypass multi-sampling for stage 1 when simulating with
-- either fast calibration option, or with multi-sampling
-- disabled
detect_edge_cnt1_en_r <= '1' after (TCQ)*1 ps;
elsif (detect_edge_cnt0_r = DETECT_EDGE_SAMPLE_CNT0) then
detect_edge_cnt1_en_r <= '1' after (TCQ)*1 ps;
else
detect_edge_cnt1_en_r <= '0' after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
-- Counter #2
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
detect_edge_cnt1_r <= (others => '0') after (TCQ)*1 ps;
else
if (detect_edge_start_r = '1') then
detect_edge_cnt1_r <= (others => '0') after (TCQ)*1 ps;
elsif (detect_edge_cnt1_en_r = '1') then
detect_edge_cnt1_r <= detect_edge_cnt1_r + '1' after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
detect_edge_done_r <= '0' after (TCQ)*1 ps;
else
if (detect_edge_start_r = '1') then
detect_edge_done_r <= '0' after (TCQ)*1 ps;
elsif (((SIM_CAL_OPTION = "FAST_CAL") or (SIM_CAL_OPTION = "FAST_WIN_DETECT")) and (detect_edge_cnt1_r = X"001")) then
-- Bypass multi-sampling for stage 1 when simulating with
-- either fast calibration option, or with multi-sampling
-- disabled
detect_edge_done_r <= '1' after (TCQ)*1 ps;
elsif (detect_edge_cnt1_r = DETECT_EDGE_SAMPLE_CNT1) then
detect_edge_done_r <= '1' after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
--*****************************************************************
-- Keep track of how long we've been in the same data eye
-- (i.e. over how many taps we have not yet found an eye)
--*****************************************************************
-- An actual edge occurs when either: (1) difference in read data between
-- current IODELAY tap and previous IODELAY tap (yes, this is confusing,
-- since this condition is represented by found_edge_latched_r), (2) if
-- the previous IODELAY tap read data was jittering (in which case it
-- doesn't matter what the current IODELAY tap sample looks like)
cal1_found_edge <= found_edge_latched_r or last_tap_jitter_r;
process (clk)
begin
if (clk'event and clk = '1') then
-- Reset to 0 every time we begin processing a new DQS group
if ((cal1_state_r = CAL1_IDLE) or (cal1_state_r = CAL1_NEXT_DQS)) then
cnt_eye_size_r <= "000" after (TCQ)*1 ps;
found_stable_eye_r <= '0' after (TCQ)*1 ps;
last_tap_jitter_r <= '0' after (TCQ)*1 ps;
found_edge_latched_r <= '0' after (TCQ)*1 ps;
found_jitter_latched_r <= '0' after (TCQ)*1 ps;
elsif (not(cal1_state_r = CAL1_DETECT_EDGE)) then
-- Reset "latched" signals before looking for an edge
found_edge_latched_r <= '0' after (TCQ)*1 ps;
found_jitter_latched_r <= '0' after (TCQ)*1 ps;
elsif (cal1_state_r = CAL1_DETECT_EDGE) then
if (not(detect_edge_done_r = '1')) then
-- While sampling:
-- Latch if we've found an edge (i.e. difference between current
-- and previous IODELAY tap), and/or jitter (difference between
-- current and previous sample - on the same IODELAY tap). It is
-- possible to find an edge, and not jitter, but not vice versa
if (found_edge_r = '1') then
found_edge_latched_r <= '1' after (TCQ)*1 ps;
end if;
if (prev_found_edge_r = '1') then
found_jitter_latched_r <= '1' after (TCQ)*1 ps;
end if;
else
-- Once the sample interval is over, it's time for housekeeping:
-- If jitter found during current tap, record for future compares
last_tap_jitter_r <= found_jitter_latched_r after (TCQ)*1 ps;
-- If we found an edge, or if the previous IODELAY tap had jitter
-- then reset stable window counter to 0 - obviously we're not in
-- the data valid window. Note that we care about whether jitter
-- occurred during the previous tap because it's possible to not
-- find an edge (in terms of how it's determined in found_edge_r)
-- even though jitter occured during the previous tap.
if (cal1_found_edge = '1') then
cnt_eye_size_r <= "000" after (TCQ)*1 ps;
found_stable_eye_r <= '0' after (TCQ)*1 ps;
else
-- Otherwise, everytime we look for an edge, and don't find
-- one, increment counter until minimum eye size encountered -
-- note this counter does not track the eye size, but only if
-- it exceeded minimum size
if (to_integer(unsigned(cnt_eye_size_r)) = (MIN_EYE_SIZE-1)) then
found_stable_eye_r <= '1' after (TCQ)*1 ps;
else
found_stable_eye_r <= '0' after (TCQ)*1 ps;
cnt_eye_size_r <= cnt_eye_size_r + '1' after (TCQ)*1 ps;
end if;
end if;
end if;
end if;
end if;
end process;
--*****************************************************************
-- keep track of edge tap counts found, and current capture clock
-- tap count
--*****************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
idel_tap_cnt_cpt_r <= (others => '0') after (TCQ)*1 ps;
idel_tap_limit_cpt_r <= '0' after (TCQ)*1 ps;
else
if (new_cnt_cpt_r = '1') then
idel_tap_cnt_cpt_r <= "00000" after (TCQ)*1 ps;
idel_tap_limit_cpt_r <= '0' after (TCQ)*1 ps;
elsif (cal1_dlyce_cpt_r = '1') then
if (cal1_dlyinc_cpt_r = '1') then
idel_tap_cnt_cpt_r <= idel_tap_cnt_cpt_r + '1' after (TCQ)*1 ps;
else
-- Assert if tap limit has been reached
idel_tap_cnt_cpt_r <= idel_tap_cnt_cpt_r - '1' after (TCQ)*1 ps;
end if;
if ((to_integer(unsigned(idel_tap_cnt_cpt_r)) = (IODELAY_TAP_LEN-2)) and (cal1_dlyinc_cpt_r = '1')) then
idel_tap_limit_cpt_r <= '1' after (TCQ)*1 ps;
else
idel_tap_limit_cpt_r <= '0' after (TCQ)*1 ps;
end if;
end if;
end if;
end if;
end process;
--*****************************************************************
-- keep track of when DQ tap limit is reached
--*****************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
idel_tap_limit_dq_r <= '0' after (TCQ)*1 ps;
else
if (new_cnt_cpt_r = '1') then
idel_tap_limit_dq_r <= '0' after (TCQ)*1 ps;
elsif (to_integer(unsigned(cal1_dq_tap_cnt_r)) = (IODELAY_TAP_LEN-1)) then
idel_tap_limit_dq_r <= '1' after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
--*****************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
cal1_cnt_cpt_r <= (others => '0') after (TCQ)*1 ps;
cal1_dlyce_cpt_r <= '0' after (TCQ)*1 ps;
cal1_dlyinc_cpt_r <= '0' after (TCQ)*1 ps;
cal1_dq_tap_cnt_r <= "00000" after (TCQ)*1 ps;
cal1_dq_taps_inc_r <= '0' after (TCQ)*1 ps;
cal1_prech_req_r <= '0' after (TCQ)*1 ps;
cal1_store_sr_req_r <= '0' after (TCQ)*1 ps;
cal1_state_r <= CAL1_IDLE after (TCQ)*1 ps;
cnt_idel_dec_cpt_r <= "XXXXXX" after (TCQ)*1 ps;
cnt_idel_inc_cpt_r <= "XXXXX" after (TCQ)*1 ps;
cnt_idel_skip_idel_r<= "XXXXX" after (TCQ)*1 ps;
detect_edge_start_r <= '0' after (TCQ)*1 ps;
found_dq_edge_r <= '0' after (TCQ)*1 ps;
found_two_edge_r <= '0' after (TCQ)*1 ps;
found_first_edge_r <= '0' after (TCQ)*1 ps;
found_second_edge_r <= '0' after (TCQ)*1 ps;
first_edge_taps_r <= "XXXXX" after (TCQ)*1 ps;
new_cnt_cpt_r <= '0' after (TCQ)*1 ps;
rdlvl_done_1(0) <= '0' after (TCQ)*1 ps;
rdlvl_err_2(0) <= '0' after (TCQ)*1 ps;
right_edge_taps_r <= "XXXXX" after (TCQ)*1 ps;
second_edge_taps_r <= "XXXXX" after (TCQ)*1 ps;
second_edge_dq_taps_r <= "XXXXX" after (TCQ)*1 ps;
else
-- default (inactive) states for all "pulse" outputs
cal1_prech_req_r <= '0' after (TCQ)*1 ps;
cal1_dlyce_cpt_r <= '0' after (TCQ)*1 ps;
cal1_dlyinc_cpt_r <= '0' after (TCQ)*1 ps;
cal1_store_sr_req_r <= '0' after (TCQ)*1 ps;
detect_edge_start_r <= '0' after (TCQ)*1 ps;
new_cnt_cpt_r <= '0' after (TCQ)*1 ps;
case (cal1_state_r) is
when CAL1_IDLE =>
if ((rdlvl_start(0)) = '1') then
if (SIM_CAL_OPTION = "SKIP_CAL") then
-- "Hardcoded" calibration option
cnt_idel_skip_idel_r <= std_logic_vector(to_unsigned(TBY4_TAPS, 5)) after (TCQ)*1 ps;
cal1_state_r <= CAL1_SKIP_RDLVL_INC_IDEL after (TCQ)*1 ps;
else
new_cnt_cpt_r <= '1' after (TCQ)*1 ps;
cal1_state_r <= CAL1_NEW_DQS_WAIT after (TCQ)*1 ps;
end if;
end if;
-- Wait for various MUXes associated with a new DQS group to
-- change - also gives time for the read data shift register
-- to load with the updated data for the new DQS group
when CAL1_NEW_DQS_WAIT =>
if (pipe_wait = '0') then
cal1_state_r <= CAL1_IDEL_STORE_FIRST after (TCQ)*1 ps;
end if;
-- When first starting calibration for a DQS group, save the
-- current value of the read data shift register, and use this
-- as a reference. Note that for the first iteration of the
-- edge detection loop, we will in effect be checking for an edge
-- at IODELAY taps = 0 - normally, we are comparing the read data
-- for IODELAY taps = N, with the read data for IODELAY taps = N-1
-- An edge can only be found at IODELAY taps = 0 if the read data
-- is changing during this time (possible due to jitter)
when CAL1_IDEL_STORE_FIRST =>
cal1_store_sr_req_r <= '1' after (TCQ)*1 ps;
detect_edge_start_r <= '1' after (TCQ)*1 ps;
if (store_sr_done_r = '1') then
if (cal1_dq_taps_inc_r = '1') then -- if using dq taps
cal1_state_r <= CAL1_DETECT_EDGE_DQ after (TCQ)*1 ps;
else
cal1_state_r <= CAL1_DETECT_EDGE after (TCQ)*1 ps;
end if;
end if;
-- Check for presence of data eye edge
when CAL1_DETECT_EDGE =>
if (detect_edge_done_r = '1') then
if (cal1_found_edge = '1') then
-- Sticky bit - asserted after we encounter an edge, although
-- the current edge may not be considered the "first edge" this
-- just means we found at least one edge
found_first_edge_r <= '1' after (TCQ)*1 ps;
-- For use during "low-frequency" edge detection:
-- Prevent underflow if we find an edge right away - at any
-- rate, if we do, and later we don't find a second edge by
-- using DQ taps, then we're running at a very low
-- frequency, and we really don't care about whether the
-- first edge found is a "left" or "right" edge - we have
-- more margin to absorb any inaccuracy
if (found_first_edge_r = '0') then
if (idel_tap_cnt_cpt_r = "00000") then
right_edge_taps_r <= "00000" after (TCQ)*1 ps;
else
right_edge_taps_r <= (idel_tap_cnt_cpt_r - '1') after (TCQ)*1 ps;
end if;
end if;
-- Both edges of data valid window found:
-- If we've found a second edge after a region of stability
-- then we must have just passed the second ("right" edge of
-- the window. Record this second_edge_taps = current tap-1,
-- because we're one past the actual second edge tap, where
-- the edge taps represent the extremes of the data valid
-- window (i.e. smallest & largest taps where data still valid
if ((found_first_edge_r and found_stable_eye_r) = '1') then
found_second_edge_r <= '1' after (TCQ)*1 ps;
second_edge_taps_r <= idel_tap_cnt_cpt_r - '1' after (TCQ)*1 ps;
cal1_state_r <= CAL1_CALC_IDEL after (TCQ)*1 ps;
else
-- Otherwise, an edge was found (just not the "second" edge)
-- then record current tap count - this may be the "left"
-- edge of the current data valid window
first_edge_taps_r <= idel_tap_cnt_cpt_r after (TCQ)*1 ps;
-- If we haven't run out of taps, then keep incrementing
if (idel_tap_limit_cpt_r = '0') then
cal1_state_r <= CAL1_IDEL_STORE_OLD after (TCQ)*1 ps;
else
-- If we ran out of taps moving the capture clock, and we
-- haven't found second edge, then try to find edges by
-- moving the DQ IODELAY taps
cal1_state_r <= CAL1_RST_CPT after (TCQ)*1 ps;
-- Using this counter to reset the CPT taps to zero
-- taps + any PD taps
cnt_idel_dec_cpt_r <= std_logic_vector(to_unsigned((IODELAY_TAP_LEN-1), 6)) after (TCQ)*1 ps;
end if;
end if;
else
-- Otherwise, if we haven't found an edge....
if (idel_tap_limit_cpt_r = '0') then
-- If we still have taps left to use, then keep incrementing
cal1_state_r <= CAL1_IDEL_STORE_OLD after (TCQ)*1 ps;
else
-- If we ran out of taps moving the capture clock, and we
-- haven't found even one or second edge, then try to find
-- edges by moving the DQ IODELAY taps
cal1_state_r <= CAL1_RST_CPT after (TCQ)*1 ps;
-- Using this counter to reset the CPT taps to zero
-- taps + any PD taps
cnt_idel_dec_cpt_r <= std_logic_vector(to_unsigned((IODELAY_TAP_LEN-1), 6)) after (TCQ)*1 ps;
end if;
end if;
end if;
-- Store the current read data into the read data shift register
-- before incrementing the tap count and doing this again
when CAL1_IDEL_STORE_OLD =>
cal1_store_sr_req_r <= '1' after (TCQ)*1 ps;
if (store_sr_done_r = '1') then
if (cal1_dq_taps_inc_r = '1') then -- if using dq taps
cal1_state_r <= CAL1_IDEL_INC_DQ after (TCQ)*1 ps;
else
cal1_state_r <= CAL1_IDEL_INC_CPT after (TCQ)*1 ps;
end if;
end if;
-- Increment IDELAY for both capture and resync clocks
when CAL1_IDEL_INC_CPT =>
cal1_dlyce_cpt_r <= '1' after (TCQ)*1 ps;
cal1_dlyinc_cpt_r <= '1' after (TCQ)*1 ps;
cal1_state_r <= CAL1_IDEL_INC_CPT_WAIT after (TCQ)*1 ps;
-- Wait for IDELAY for both capture and resync clocks, and internal
-- nodes within ISERDES to settle, before checking again for an edge
when CAL1_IDEL_INC_CPT_WAIT =>
detect_edge_start_r <= '1' after (TCQ)*1 ps;
if (pipe_wait = '0') then
cal1_state_r <= CAL1_DETECT_EDGE after (TCQ)*1 ps;
end if;
-- Calculate final value of IDELAY. At this point, one or both
-- edges of data eye have been found, and/or all taps have been
-- exhausted looking for the edges
-- NOTE: We're calculating the amount to decrement by, not the
-- absolute setting for DQ IDELAY
when CAL1_CALC_IDEL =>
--*******************************************************
-- Now take care of IDELAY for capture clock:
-- Explanation of calculations:
-- 1. If 2 edges found, final IDELAY value =
-- TAPS = FE_TAPS + ((SE_TAPS-FE_TAPS)/2)
-- 2. If 1 edge found, final IDELAY value is either:
-- TAPS = FE_TAPS - TBY4_TAPS, or
-- TAPS = FE_TAPS + TBY4_TAPS
-- Depending on which is achievable without overflow
-- (and with bias toward having fewer taps)
-- 3. If no edges found, then final IDELAY value is:
-- TAPS = 15
-- This is the best we can do with the information we
-- have it guarantees we have at least 15 taps of
-- margin on either side of calibration point
-- How the final IDELAY tap is reached:
-- 1. If 2 edges found, current tap count = SE_TAPS + 1
-- * Decrement by [(SE_TAPS-FE_TAPS)/2] + 1
-- 2. If 1 edge found, current tap count = 31
-- * Decrement by 31 - FE_TAPS - TBY4, or
-- * Decrement by 31 - FE_TAPS + TBY4
-- 3. If no edges found
-- * Decrement by 16
--*******************************************************
-- CASE1: If 2 edges found.
-- Only CASE1 will be true. Due to the low frequency fixes
-- the SM will not transition to this state when two edges are not
-- found.
if (found_second_edge_r = '1') then
-- SYNTHESIS_NOTE: May want to pipeline this operation
-- over multiple cycles for better timing. If so, need
-- to add delay state in CAL1 state machine
cnt_idel_dec_cpt_r <= calc_cnt_idel_dec_cpt(second_edge_taps_r,first_edge_taps_r) after (TCQ)*1 ps;
-- CASE 2: 1 edge found
-- NOTE: Need to later add logic to prevent decrementing below 0
elsif (found_first_edge_r = '1') then
if ( to_integer(unsigned(first_edge_taps_r)) >= (IODELAY_TAP_LEN/2) and
((to_integer(unsigned(first_edge_taps_r)) + TBY4_TAPS) < (IODELAY_TAP_LEN - 1)) ) then
-- final IDELAY value = [FIRST_EDGE_TAPS-CLK_MEM_PERIOD/2]
cnt_idel_dec_cpt_r <= std_logic_vector(to_unsigned(((IODELAY_TAP_LEN-1) -
to_integer(unsigned(first_edge_taps_r)) - TBY4_TAPS), 6)) after (TCQ)*1 ps;
else
-- final IDELAY value = [FIRST_EDGE_TAPS+CLK_MEM_PERIOD/2]
cnt_idel_dec_cpt_r <= std_logic_vector(to_unsigned(((IODELAY_TAP_LEN-1) -
to_integer(unsigned(first_edge_taps_r)) + TBY4_TAPS), 6)) after (TCQ)*1 ps;
end if;
else
-- CASE 3: No edges found, decrement by half tap length
cnt_idel_dec_cpt_r <= std_logic_vector(to_unsigned(IODELAY_TAP_LEN/2, 6)) after (TCQ)*1 ps;
end if;
-- Now use the value we just calculated to decrement CPT taps
-- to the desired calibration point
cal1_state_r <= CAL1_IDEL_DEC_CPT after (TCQ)*1 ps;
-- decrement capture clock IDELAY for final adjustment - center
-- capture clock in middle of data eye. This adjustment will occur
-- only when both the edges are found usign CPT taps. Must do this
-- incrementally to avoid clock glitching (since CPT drives clock
-- divider within each ISERDES)
when CAL1_IDEL_DEC_CPT =>
cal1_dlyce_cpt_r <= '1' after (TCQ)*1 ps;
cal1_dlyinc_cpt_r <= '0' after (TCQ)*1 ps;
-- once adjustment is complete, we're done with calibration for
-- this DQS, repeat for next DQS
cnt_idel_dec_cpt_r <= cnt_idel_dec_cpt_r - "000001" after (TCQ)*1 ps;
if ((cnt_idel_dec_cpt_r) = "1") then
cal1_state_r <= CAL1_IDEL_PD_ADJ after (TCQ)*1 ps;
end if;
-- Determine whether we're done, or have more DQS's to calibrate
-- Also request precharge after every byte, as appropriate
when CAL1_NEXT_DQS =>
cal1_prech_req_r <= '1' after (TCQ)*1 ps;
-- Prepare for another iteration with next DQS group
found_dq_edge_r <= '0' after (TCQ)*1 ps;
found_two_edge_r <= '0' after (TCQ)*1 ps;
found_first_edge_r <= '0' after (TCQ)*1 ps;
found_second_edge_r<= '0' after (TCQ)*1 ps;
cal1_dq_taps_inc_r <= '0' after (TCQ)*1 ps;
-- Wait until precharge that occurs in between calibration of
-- DQS groups is finished
if (prech_done = '1') then
if ((to_integer(unsigned(cal1_cnt_cpt_r)) >= (DQS_WIDTH-1)) or (SIM_CAL_OPTION = "FAST_CAL")) then
cal1_state_r <= CAL1_DONE after (TCQ)*1 ps;
else
-- Process next DQS group
new_cnt_cpt_r <= '1' after (TCQ)*1 ps;
cal1_dq_tap_cnt_r <= "00000" after (TCQ)*1 ps;
cal1_cnt_cpt_r <= cal1_cnt_cpt_r + '1' after (TCQ)*1 ps;
cal1_state_r <= CAL1_NEW_DQS_WAIT after (TCQ)*1 ps;
end if;
end if;
when CAL1_RST_CPT =>
cal1_dq_taps_inc_r <= '1' after (TCQ)*1 ps;
-- If we never found even one edge by varying CPT taps, then
-- as an approximation set first edge tap indicators to 31. This
-- will be used later in the low-frequency portion of calibration
if (found_first_edge_r = '0') then
first_edge_taps_r <= std_logic_vector(to_unsigned((IODELAY_TAP_LEN- 1), 5)) after (TCQ)*1 ps;
right_edge_taps_r <= std_logic_vector(to_unsigned((IODELAY_TAP_LEN- 1), 5)) after (TCQ)*1 ps;
end if;
if ((cnt_idel_dec_cpt_r) = "000000") then
-- once the decerement is done. Go back to the CAL1_NEW_DQS_WAIT
-- state to load the correct data for comparison and to start
-- with DQ taps.
cal1_state_r <= CAL1_NEW_DQS_WAIT after (TCQ)*1 ps;
-- Start with a DQ tap value of 0
cal1_dq_tap_cnt_r <= "00000" after (TCQ)*1 ps;
else
-- decrement both CPT taps to initial value.
-- DQ IODELAY taps will be used to find the edges
cal1_dlyce_cpt_r <= '1' after (TCQ)*1 ps;
cal1_dlyinc_cpt_r <= '0' after (TCQ)*1 ps;
cnt_idel_dec_cpt_r <= cnt_idel_dec_cpt_r - "000001" after (TCQ)*1 ps;
end if;
-- When two edges are not found using CPT taps, finding edges
-- using DQ taps.
when CAL1_DETECT_EDGE_DQ =>
if (detect_edge_done_r = '1') then
-- when using DQ taps make sure the window size is atleast 10.
-- DQ taps used only in low frequency designs.
if (((found_edge_r)) = '1' and ((found_first_edge_r = '0') or (tby4_r > "000101"))) then
-- Sticky bit - asserted after we encounter first edge
-- If we've found a second edge(using dq taps) after a region
-- of stability ( using tby4_r count) then this must be the
-- second ("using dq taps") edge of the window
found_dq_edge_r <= '1' after (TCQ)*1 ps;
found_two_edge_r <= found_first_edge_r after (TCQ)*1 ps;
cal1_state_r <= CAL1_CALC_IDEL_DQ after (TCQ)*1 ps;
-- Recording the dq taps when an edge is found. Account for
-- the case when an edge is found at DQ IODELAY = 0 taps -
-- possible because of jitter
if (not(cal1_dq_tap_cnt_r = "00000")) then
second_edge_dq_taps_r <= (cal1_dq_tap_cnt_r - '1') after (TCQ)*1 ps;
else
second_edge_dq_taps_r <= "00000" after (TCQ)*1 ps;
end if;
else
-- No more DQ taps to increment - set left edge tap distance
-- to 31 as an approximation, and move on to figuring out
-- what needs to be done to center (or approximately center)
-- sampling point in middle of read window
if (idel_tap_limit_dq_r = '1') then
cal1_state_r <= CAL1_CALC_IDEL_DQ after (TCQ)*1 ps;
second_edge_dq_taps_r <= std_logic_vector(to_unsigned((IODELAY_TAP_LEN- 1), 5)) after (TCQ)*1 ps;
else
cal1_state_r <= CAL1_IDEL_STORE_OLD after (TCQ)*1 ps;
end if;
end if;
end if;
when CAL1_IDEL_INC_DQ =>
cal1_dq_tap_cnt_r <= cal1_dq_tap_cnt_r + "00001" after (TCQ)*1 ps;
cal1_state_r <= CAL1_IDEL_INC_DQ_WAIT after (TCQ)*1 ps;
-- Wait for IDELAY for DQ, and internal nodes within ISERDES
-- to settle, before checking again for an edge
when CAL1_IDEL_INC_DQ_WAIT =>
detect_edge_start_r <= '1' after (TCQ)*1 ps;
if (pipe_wait = '0') then
cal1_state_r <= CAL1_DETECT_EDGE_DQ after (TCQ)*1 ps;
end if;
when CAL1_CALC_IDEL_DQ =>
cal1_state_r <= CAL1_IDEL_INC_DQ_CPT after (TCQ)*1 ps;
cal1_dq_tap_cnt_r <= "00000" after (TCQ)*1 ps;
cnt_idel_inc_cpt_r <= "00000" after (TCQ)*1 ps;
--------------------------------------------------------------
-- Determine whether to move DQ or CPT IODELAY taps to best
-- position sampling point in data valid window. In general,
-- we want to avoid setting DQ IODELAY taps to a nonzero value
-- in order to avoid adding IODELAY pattern-dependent jitter.
--------------------------------------------------------------
-- At this point, we have the following products of calibration:
-- 1. right_edge_taps_r: distance in IODELAY taps from start
-- position to right margin of current data valid window.
-- Measured using CPT IODELAY.
-- 2. first_edge_taps_r: distance in IODELAY taps from start
-- position to start of left edge of next data valid window.
-- Note that {first_edge_taps_r - right_edge_taps_r} = width
-- of the uncertainty or noise region between consecutive
-- data eyes. Measured using CPT IODELAY.
-- 3. second_edge_dq_taps_r: distance in IODELAY taps from left
-- edge of current data valid window. Measured using DQ
-- IODELAY.
-- 4. tby4_r: half the width of the eye as calculated by
-- {second_edge_dq_taps_r + first_edge_taps_r}
-- ------------------------------------------------------------
-- If two edges are found (one each from moving CPT, and DQ
-- IODELAYs), then the following cases are considered for setting
-- final DQ and CPT delays (in the following order):
-- 1. second_edge_dq_taps_r <= tby4_r:
-- * incr. CPT taps by {second_edge_dq_taps_r - tby4_r}
-- this means that there is more taps available to the right
-- of the starting position
-- 2. first_edge_taps_r + tby4_r <= 31 taps (IODELAY length)
-- * incr CPT taps by {tby4_r}
-- this means we have enough CPT taps available to us to
-- position the sampling point in the middle of the next
-- sampling window. Alternately, we could have instead
-- positioned ourselves in the middle of the current window
-- by using DQ taps, but if possible avoid using DQ taps
-- because of pattern-dependent jitter
-- 3. otherwise, our only recourse is to move DQ taps in order
-- to center the sampling point in the middle of the current
-- data valid window
-- * set DQ taps to {tby4_r - right_edge_taps_r}
-- ------------------------------------------------------------
-- Note that the case where only one edge is found, either using
-- CPT or DQ IODELAY taps is a subset of the above 3 cases, which
-- can be approximated by setting either right_edge_taps_r = 31,
-- or second_edge_dq_taps_r = 31. This doesn't result in an exact
-- centering, but this will only occur at an extremely low
-- frequency, and exact centering is not required
-- ------------------------------------------------------------
if (('0' & second_edge_dq_taps_r) <= tby4_r) then
cnt_idel_inc_cpt_r <= subtract_vectors(tby4_r, second_edge_dq_taps_r) after (TCQ)*1 ps;
elsif ((('0' & first_edge_taps_r) + tby4_r) <= std_logic_vector(to_unsigned(IODELAY_TAP_LEN - 1, 6))) then
cnt_idel_inc_cpt_r <= add_vectors(tby4_r, first_edge_taps_r) after (TCQ)*1 ps;
else
cal1_dq_tap_cnt_r <= subtract_vectors(tby4_r, right_edge_taps_r) after (TCQ)*1 ps;
end if;
-- increment capture clock IDELAY for final adjustment - center
-- capture clock in middle of data eye. This state transition will
-- occur when only one edge or no edge is found using CPT taps
when CAL1_IDEL_INC_DQ_CPT =>
if (cnt_idel_inc_cpt_r = "00000") then
-- once adjustment is complete, we're done with calibration for
-- this DQS, repeat for next DQS.
cal1_state_r <= CAL1_IDEL_PD_ADJ after (TCQ)*1 ps;
else
cal1_dlyce_cpt_r <= '1' after (TCQ)*1 ps;
cal1_dlyinc_cpt_r <= '1' after (TCQ)*1 ps;
cnt_idel_inc_cpt_r <= cnt_idel_inc_cpt_r - '1' after (TCQ)*1 ps;
end if;
when CAL1_IDEL_PD_ADJ =>
-- If CPT is < than half the required PD taps then move the
-- CPT taps the DQ taps togather
if (to_integer(unsigned(idel_tap_cnt_cpt_r)) < PD_HALF_TAP) then
cal1_dlyce_cpt_r <= '1' after (TCQ)*1 ps;
cal1_dlyinc_cpt_r <= '1' after (TCQ)*1 ps;
cal1_dq_tap_cnt_r <= cal1_dq_tap_cnt_r + "00001" after (TCQ)*1 ps;
else
cal1_state_r <= CAL1_NEXT_DQS after (TCQ)*1 ps;
end if;
-- Done with this stage of calibration
-- if used, allow DEBUG_PORT to control taps
when CAL1_DONE =>
rdlvl_done_1(0) <= '1' after (TCQ)*1 ps;
-- Used for simulation only - hardcode IDELAY values for all rdlvl
-- associated IODELAYs - kind of a cheesy way of providing for
-- simulation, but I don't feel like modifying PHY_DQ_IOB to add
-- extra parameters just for simulation. This part shouldn't get
-- synthesized.
when CAL1_SKIP_RDLVL_INC_IDEL =>
cal1_dlyce_cpt_r <= '1' after (TCQ)*1 ps;
cal1_dlyinc_cpt_r <= '1' after (TCQ)*1 ps;
cnt_idel_skip_idel_r <= cnt_idel_skip_idel_r - '1' after (TCQ)*1 ps;
if (cnt_idel_skip_idel_r = "00001") then
cal1_state_r <= CAL1_DONE after (TCQ)*1 ps;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
--***************************************************************************
-- Calculates the window size during calibration.
-- Value is used only when two edges are not found using the CPT taps.
-- cal1_dq_tap_cnt_r deceremented by 1 to account for the correct window.
--***************************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
if (cal1_dq_tap_cnt_r > "00000") then
tby4_r <= std_logic_vector(unsigned(('0' & cal1_dq_tap_cnt_r) + ('0' & right_edge_taps_r) - 1) srl 1) after (TCQ)*1 ps;
else
tby4_r <= std_logic_vector(unsigned(('0' & cal1_dq_tap_cnt_r) + ('0' & right_edge_taps_r)) srl 1) after (TCQ)*1 ps;
end if;
end if;
end process;
--***************************************************************************
-- Stage 2 calibration: Read Enable
-- Read enable calibration determines the "round-trip" time (in # of CLK
-- cycles) between when a read command is issued by the controller, and
-- when the corresponding read data is synchronized by into the CLK domain
--***************************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
rd_active_r <= rdlvl_rd_active after (TCQ)*1 ps;
rd_active_posedge_r <= rdlvl_rd_active and not(rd_active_r) after (TCQ)*1 ps;
end if;
end process;
--*****************************************************************
-- Expected data pattern when properly aligned through bitslip
-- Based on pattern of ({rise,fall}) =
-- 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6
-- Examining only the LSb of each DQS group, pattern is =
-- bit3: 1, 0, 1, 0, 0, 1, 1, 0
-- bit2: 1, 0, 0, 1, 1, 0, 0, 1
-- bit1: 1, 0, 1, 0, 0, 1, 0, 1
-- bit0: 1, 0, 0, 1, 1, 0, 1, 0
-- Change the hard-coded pattern below accordingly as RD_SHIFT_LEN
-- and the actual training pattern contents change
--*****************************************************************
pat_rise0(3) <= "10";
pat_fall0(3) <= "01";
pat_rise1(3) <= "11";
pat_fall1(3) <= "00";
pat_rise0(2) <= "11";
pat_fall0(2) <= "00";
pat_rise1(2) <= "00";
pat_fall1(2) <= "11";
pat_rise0(1) <= "10";
pat_fall0(1) <= "01";
pat_rise1(1) <= "10";
pat_fall1(1) <= "01";
pat_rise0(0) <= "11";
pat_fall0(0) <= "00";
pat_rise1(0) <= "01";
pat_fall1(0) <= "10";
--*****************************************************************
-- Do not need to look at sr_valid_r - the pattern can occur anywhere
-- during the shift of the data shift register - as long as the order
-- of the bits in the training sequence is correct. Each bit of each
-- byte is compared to expected pattern - this is not strictly required.
-- This was done to prevent (and "drastically decrease") the chance that
-- invalid data clocked in when the DQ bus is tri-state (along with a
-- combination of the correct data) will resemble the expected data
-- pattern. A better fix for this is to change the training pattern and/or
-- make the pattern longer.
--*****************************************************************
gen_pat_match : for pt_i in 0 to DRAM_WIDTH-1 generate
process (clk)
begin
if (clk'event and clk = '1') then
if (sr_rise0_r(pt_i) = pat_rise0(pt_i mod 4)) then
pat_match_rise0_r(pt_i) <= '1' after (TCQ)*1 ps;
else
pat_match_rise0_r(pt_i) <= '0' after (TCQ)*1 ps;
end if;
if (sr_fall0_r(pt_i) = pat_fall0(pt_i mod 4)) then
pat_match_fall0_r(pt_i) <= '1' after (TCQ)*1 ps;
else
pat_match_fall0_r(pt_i) <= '0' after (TCQ)*1 ps;
end if;
if (sr_rise1_r(pt_i) = pat_rise1(pt_i mod 4)) then
pat_match_rise1_r(pt_i) <= '1' after (TCQ)*1 ps;
else
pat_match_rise1_r(pt_i) <= '0' after (TCQ)*1 ps;
end if;
if (sr_fall1_r(pt_i) = pat_fall1(pt_i mod 4)) then
pat_match_fall1_r(pt_i) <= '1' after (TCQ)*1 ps;
else
pat_match_fall1_r(pt_i) <= '0' after (TCQ)*1 ps;
end if;
end if;
end process;
end generate;
process (clk)
begin
if (clk'event and clk = '1') then
pat_match_rise0_and_r <= AND_BR(pat_match_rise0_r) after (TCQ)*1 ps;
pat_match_fall0_and_r <= AND_BR(pat_match_fall0_r) after (TCQ)*1 ps;
pat_match_rise1_and_r <= AND_BR(pat_match_rise1_r) after (TCQ)*1 ps;
pat_match_fall1_and_r <= AND_BR(pat_match_fall1_r) after (TCQ)*1 ps;
pat_data_match_r <= (pat_match_rise0_and_r and pat_match_fall0_and_r and
pat_match_rise1_and_r and pat_match_fall1_and_r) after (TCQ)*1 ps;
end if;
end process;
-- Generic counter to force wait after either bitslip value or
-- CNT_RDEN is changed - allows time for old contents of read pipe
-- to flush out
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
rden_wait_r <= '0' after (TCQ)*1 ps;
cnt_rden_wait_r <= (others => '0') after (TCQ)*1 ps;
else
if (to_integer(unsigned(cal2_state_r)) /= CAL2_READ_WAIT) then
rden_wait_r <= '1' after (TCQ)*1 ps;
cnt_rden_wait_r <= (others => '0') after (TCQ)*1 ps;
else
cnt_rden_wait_r <= cnt_rden_wait_r + '1' after (TCQ)*1 ps;
if (cnt_rden_wait_r = std_logic_vector(to_unsigned(RDEN_WAIT_CNT - 1, 3))) then
rden_wait_r <= '0' after (TCQ)*1 ps;
end if;
end if;
end if;
end if;
end process;
-- Register output for timing purposes
process (clk)
begin
if (clk'event and clk = '1') then
rd_bitslip_cnt <= cal2_rd_bitslip_cnt_r after (TCQ)*1 ps;
rd_active_dly <= cal2_rd_active_dly_r after (TCQ)*1 ps;
end if;
end process;
--*****************************************************************
-- Calibration state machine for determining polarity of ISERDES
-- CLKDIV invert control on a per-DQS group basis
-- This stage is used to choose the best phase of the resync clock
-- (on a per-DQS group basis) - "best phase" meaning the phase that
-- results in the largest possible margin in the CLK-to-RSYNC clock
-- domain transfer within the ISERDES.
-- NOTE: This stage actually takes place after stage 1 calibration.
-- For the time being, the signal naming convention associated with
-- this stage will be known as "cal_clkdiv". However, it really is
-- another stage of calibration - should be stage 2, and what is
-- currently stage 2 (rd_active_dly calibration) should be changed
-- to stage 3.
--*****************************************************************
rd_clkdiv_inv <= clkdiv_inv_r;
dbg_rd_clkdiv_inv <= clkdiv_inv_r;
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
cal_clkdiv_clkdiv_inv_r <= '0' after (TCQ)*1 ps;
cal_clkdiv_cnt_clkdiv_r <= (others => '0') after (TCQ)*1 ps;
cal_clkdiv_dlyce_rsync_r <= '0' after (TCQ)*1 ps;
cal_clkdiv_dlyinc_rsync_r <= '0' after (TCQ)*1 ps;
cal_clkdiv_idel_rsync_inc_r <= '0' after (TCQ)*1 ps;
cal_clkdiv_prech_req_r <= '0' after (TCQ)*1 ps;
cal_clkdiv_state_r <= CAL_CLKDIV_IDLE after (TCQ)*1 ps;
cal_clkdiv_store_sr_req_r <= '0' after (TCQ)*1 ps;
clkdiv_inv_r <= (others => '0') after (TCQ)*1 ps;
idel_tap_delta_rsync_r <= "00000" after (TCQ)*1 ps;
min_rsync_marg_r <= "XXXXX" after (TCQ)*1 ps;
new_cnt_clkdiv_r <= '0' after (TCQ)*1 ps;
pol_min_rsync_marg_r <= '0' after (TCQ)*1 ps;
rdlvl_clkdiv_done_1 <= '0' after (TCQ)*1 ps;
else
-- default (inactive) states for all "pulse" outputs
cal_clkdiv_dlyce_rsync_r <= '0' after (TCQ)*1 ps;
cal_clkdiv_prech_req_r <= '0' after (TCQ)*1 ps;
cal_clkdiv_store_sr_req_r <= '0' after (TCQ)*1 ps;
new_cnt_clkdiv_r <= '0' after (TCQ)*1 ps;
case (cal_clkdiv_state_r) is
when CAL_CLKDIV_IDLE =>
if (rdlvl_clkdiv_start = '1') then
if (SIM_CAL_OPTION = "SKIP_CAL") then
-- "Hardcoded" calibration option - for all DQS groups
-- do not invert rsync clock
clkdiv_inv_r <= (others => '0') after (TCQ)*1 ps;
cal_clkdiv_state_r <= CAL_CLKDIV_DONE after (TCQ)*1 ps;
else
new_cnt_clkdiv_r <= '1' after (TCQ)*1 ps;
cal_clkdiv_state_r <= CAL_CLKDIV_NEW_DQS_WAIT after (TCQ)*1 ps;
end if;
end if;
-- Wait for various MUXes associated with a new DQS group to
-- change - also gives time for the read data shift register
-- to load with the updated data for the new DQS group
when CAL_CLKDIV_NEW_DQS_WAIT =>
-- Reset smallest recorded margin
min_rsync_marg_r <= "10000" after (TCQ)*1 ps;
pol_min_rsync_marg_r <= '0' after (TCQ)*1 ps;
if (pipe_wait = '0') then
cal_clkdiv_state_r <= CAL_CLKDIV_IDEL_STORE_REF after (TCQ)*1 ps;
end if;
-- For a given polarity of the rsync clock, save the initial data
-- value and use this as a reference to decide when an "edge" has
-- been encountered as the rsync clock is shifted
when CAL_CLKDIV_IDEL_STORE_REF =>
cal_clkdiv_store_sr_req_r <= '1' after (TCQ)*1 ps;
if (store_sr_done_r = '1') then
cal_clkdiv_state_r <= CAL_CLKDIV_DETECT_EDGE after (TCQ)*1 ps;
end if;
-- Check for presence of cpt-rsync clock synchronization "edge"
-- This occurs when the captured data sequence changes as the RSYNC
-- clock is shifted
when CAL_CLKDIV_DETECT_EDGE =>
if (found_edge_valid_r = '1') then
-- If an edge found, or we've run out of taps looking for an
-- edge, then:
-- (1) If the current margin found is the smallest, then
-- record it, as well as whether the CLKDIV was inverted
-- or not when this margin was measured
-- (2) Reverse the direction of IDEL_RSYNC_INC and/or invert
-- CLKDIV. We only invert CLKDIV if we just finished
-- incrementing the RSYNC IODELAY with CLKDIV not inverted
-- (3) Restore the original RSYNC clock delay in preparation
-- for either further measurements with the current DQS
-- group, or with the next DQS group
if ((idel_tap_delta_rsync_r = "01111") or (found_edge_r = '1')) then
-- record the margin if it's the smallest found so far
if (idel_tap_delta_rsync_r < min_rsync_marg_r) then
min_rsync_marg_r <= idel_tap_delta_rsync_r after (TCQ)*1 ps;
pol_min_rsync_marg_r <= cal_clkdiv_clkdiv_inv_r after (TCQ)*1 ps;
end if;
-- Reverse direction of RSYNC inc/dec
cal_clkdiv_idel_rsync_inc_r <= not(cal_clkdiv_idel_rsync_inc_r) after (TCQ)*1 ps;
-- Check whether to also invert CLKDIV (see above comments)
if (cal_clkdiv_idel_rsync_inc_r = '1') then
cal_clkdiv_clkdiv_inv_r <= not(cal_clkdiv_clkdiv_inv_r) after (TCQ)*1 ps;
clkdiv_inv_r(to_integer(unsigned(cal_clkdiv_cnt_clkdiv_r))) <= not(cal_clkdiv_clkdiv_inv_r) after (TCQ)*1 ps;
end if;
-- Proceed to restoring original RSYNC clock delay
cal_clkdiv_state_r <= CAL_CLKDIV_IDEL_SET_MIDPT_RSYNC after (TCQ)*1 ps;
else
-- Otherwise, increment or decrement RSYNC phase, keep
-- looking for an edge
cal_clkdiv_state_r <= CAL_CLKDIV_IDEL_INCDEC_RSYNC after (TCQ)*1 ps;
end if;
end if;
-- Increment or decrement RSYNC IODELAY by 1
when CAL_CLKDIV_IDEL_INCDEC_RSYNC =>
cal_clkdiv_dlyce_rsync_r <= '1' after (TCQ)*1 ps;
cal_clkdiv_dlyinc_rsync_r <= cal_clkdiv_idel_rsync_inc_r after (TCQ)*1 ps;
cal_clkdiv_state_r <= CAL_CLKDIV_IDEL_INCDEC_RSYNC_WAIT after (TCQ)*1 ps;
idel_tap_delta_rsync_r <= idel_tap_delta_rsync_r + '1' after (TCQ)*1 ps;
-- Wait for RSYNC IODELAY, internal nodes within ISERDES, and
-- comparison logic shift register to settle, before checking again
-- for an edge
when CAL_CLKDIV_IDEL_INCDEC_RSYNC_WAIT =>
if (pipe_wait = '0') then
cal_clkdiv_state_r <= CAL_CLKDIV_DETECT_EDGE after (TCQ)*1 ps;
end if;
-- Restore RSYNC IODELAY to starting value
when CAL_CLKDIV_IDEL_SET_MIDPT_RSYNC =>
-- Check case if we found an edge at starting tap (possible if
-- we start at or near (near enough for jitter to affect us)
-- the transfer point between the CLK and RSYNC clock domains
if (idel_tap_delta_rsync_r = "00000") then
cal_clkdiv_state_r <= CAL_CLKDIV_NEXT_CHECK after (TCQ)*1 ps;
else
cal_clkdiv_dlyce_rsync_r <= '1' after (TCQ)*1 ps;
-- inc/dec the RSYNC IODELAY in the opposite directionas
-- the just-finished search. This is a bit confusing, but note
-- that after finishing the search, we always invert
-- IDEL_RSYNC_INC prior to arriving at this state
cal_clkdiv_dlyinc_rsync_r <= cal_clkdiv_idel_rsync_inc_r after (TCQ)*1 ps;
idel_tap_delta_rsync_r <= idel_tap_delta_rsync_r - '1' after (TCQ)*1 ps;
if (idel_tap_delta_rsync_r = "00001") then
cal_clkdiv_state_r <= CAL_CLKDIV_NEXT_CHECK after (TCQ)*1 ps;
end if;
end if;
-- Determine where to go next:
-- (1) start looking for an edge in the other direction (CLKDIV
-- polarity unchanged)
-- (2) change CLKDIV polarity, resample and record a reference
-- data value, and start looking for an edge
-- (3) if we've searched all 4 possibilities (CLKDIV inverted,
-- not inverted, RSYNC shifted in left and right directions)
-- then decide which clock polarity is best to use for CLKDIV
-- and proceed to next DQS
-- NOTE: When we're comparing the current "state" (using both
-- IDEL_RSYNC_INC and CLKDIV_INV) we are comparing what the
-- next value of these signals will be, not what they were
-- for the phase of edge detection just finished. Therefore
-- IDEL_RSYNC_INC=0 and CLKDIV_INV=1 means we are about to
-- decrement RSYNC with CLKDIV inverted (or in other words,
-- we just searched with incrementing RSYNC, and CLKDIV not
-- inverted)
when CAL_CLKDIV_NEXT_CHECK =>
-- Wait for any residual change effects (CLKDIV inversion, RSYNC
-- IODELAY inc/dec) from previous state to finish
if (pipe_wait = '0') then
if ((cal_clkdiv_idel_rsync_inc_r = '0') and (cal_clkdiv_clkdiv_inv_r = '0')) then
-- If we've searched all 4 possibilities, then decide which
-- is the "best" clock polarity (which is to say, whichever
-- polarity which DID NOT result in the minimum margin found)
-- to use and proceed to next DQS
if (SIM_CAL_OPTION = "FAST_CAL") then
-- if simulating, and "shortcuts" for calibration enabled,
-- apply results to all other elements (i.e. assume delay
-- on all bits/bytes is same)
clkdiv_inv_r <= (others => not(pol_min_rsync_marg_r)) after (TCQ)*1 ps;
else
-- Otherwise, apply result only to current DQS group
clkdiv_inv_r(to_integer(unsigned(cal_clkdiv_cnt_clkdiv_r))) <= not(pol_min_rsync_marg_r) after (TCQ)*1 ps;
end if;
cal_clkdiv_state_r <= CAL_CLKDIV_NEXT_DQS after (TCQ)*1 ps;
elsif ((cal_clkdiv_idel_rsync_inc_r = '0') and (cal_clkdiv_clkdiv_inv_r = '1')) then
-- If we've finished searching with CLKDIV not inverted
-- Now store a new reference value for edge-detection
-- comparison purposes and begin looking for an edge
cal_clkdiv_state_r <= CAL_CLKDIV_IDEL_STORE_REF after (TCQ)*1 ps;
else
-- Otherwise, we've just finished checking by decrementing
-- RSYNC. Now look for an edge by incrementing RSYNC
-- (keep the CLKDIV polarity unchanged)
cal_clkdiv_state_r <= CAL_CLKDIV_DETECT_EDGE after (TCQ)*1 ps;
end if;
end if;
-- Determine whether we're done, or have more DQS's to calibrate
-- Also request precharge after every byte
when CAL_CLKDIV_NEXT_DQS =>
cal_clkdiv_prech_req_r <= '1' after (TCQ)*1 ps;
-- Wait until precharge that occurs in between calibration of
-- DQS groups is finished
if (prech_done = '1') then
if (((to_integer(unsigned(cal_clkdiv_cnt_clkdiv_r))) >= DQS_WIDTH-1) or (SIM_CAL_OPTION = "FAST_CAL")) then
-- If FAST_CAL enabled, only cal first DQS group - the results
-- (aka CLKDIV invert) have been applied to all DQS groups
cal_clkdiv_state_r <= CAL_CLKDIV_DONE after (TCQ)*1 ps;
else
-- Otherwise increment DQS group counter and keep going
new_cnt_clkdiv_r <= '1' after (TCQ)*1 ps;
cal_clkdiv_cnt_clkdiv_r <= cal_clkdiv_cnt_clkdiv_r + '1' after (TCQ)*1 ps;
cal_clkdiv_state_r <= CAL_CLKDIV_NEW_DQS_WAIT after (TCQ)*1 ps;
end if;
end if;
-- Done with this stage of calibration
when CAL_CLKDIV_DONE =>
rdlvl_clkdiv_done_1 <= '1' after (TCQ)*1 ps;
when others =>
null;
end case;
end if;
end if;
end process;
--*****************************************************************
-- Stage 2 state machine
--*****************************************************************
-- when calibrating, check to see which clock cycle (after the read is
-- issued) does the expected data pattern arrive. Record this result
-- NOTES:
-- 1. An error condition can occur due to two reasons:
-- a. If the matching logic waits a long enough amount of time
-- and the expected data pattern is not received (longer than
-- the theoretical maximum time that the data can take, factoring
-- in CAS latency, prop delays, etc.), then flag an error.
-- However, the error may be "recoverable" in that the write
-- logic is still calibrating itself (in this case part of the
-- write calibration is intertwined with the this stage of read
-- calibration - write logic writes a pattern to the memory, then
-- relies on rdlvl to find that pattern - if it doesn't, wrlvl
-- changes its timing and tries again. By design, if the write path
-- timing is incorrect, the rdlvl logic will never find the
-- pattern). Because of this, there is a mechanism to restart
-- this stage of rdlvl if an "error" is found.
-- b. If the delay between different DQS groups is too large.
-- There will be a maximum "skew" between different DQS groups
-- based on routing, clock skew, etc.
-- NOTE: Can add error checking here in case valid data not found on any
-- of the available pipeline stages
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
cal2_cnt_bitslip_r <= (others => '0') after (TCQ)*1 ps;
cal2_cnt_rd_dly_r <= (others => '0') after (TCQ)*1 ps;
cal2_cnt_rden_r <= (others => '0') after (TCQ)*1 ps;
cal2_done_r <= '0' after (TCQ)*1 ps;
cal2_en_dqs_skew_r <= '0' after (TCQ)*1 ps;
cal2_max_cnt_rd_dly_r <= (others => '0') after (TCQ)*1 ps;
cal2_prech_req_r <= '0' after (TCQ)*1 ps;
cal2_rd_bitslip_cnt_r <= (others => '0') after (TCQ)*1 ps;
cal2_state_r <= CAL2_IDLE after (TCQ)*1 ps;
rdlvl_pat_err <= '0' after (TCQ)*1 ps;
else
cal2_prech_req_r <= '0' after (TCQ)*1 ps;
case (cal2_state_r) is
when CAL2_IDLE =>
if ((rdlvl_start(1)) = '1') then
if ((SIM_CAL_OPTION = "SKIP_CAL") and (REG_CTRL = "ON")) then
-- If skip rdlvl, then proceed to end. Also hardcode bitslip
-- values based on CAS latency
cal2_state_r <= CAL2_DONE after (TCQ)*1 ps;
for idx in 0 to (DQS_WIDTH-1) loop
case nCL is
when 3 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "01" after (TCQ)*1 ps;
when 4 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "11" after (TCQ)*1 ps;
when 5 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "01" after (TCQ)*1 ps;
when 6 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "11" after (TCQ)*1 ps;
when 7 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "01" after (TCQ)*1 ps;
when 8 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "11" after (TCQ)*1 ps;
when 9 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "01" after (TCQ)*1 ps;
when 10 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "11" after (TCQ)*1 ps;
when 11 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "01" after (TCQ)*1 ps;
when others =>
null;
end case;
end loop;
elsif (SIM_CAL_OPTION = "SKIP_CAL") then
-- If skip rdlvl, then proceed to end. Also hardcode bitslip
-- values based on CAS latency
cal2_state_r <= CAL2_DONE after (TCQ)*1 ps;
for idx in 0 to (DQS_WIDTH-1) loop
case nCL is
when 3 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "11" after (TCQ)*1 ps;
when 4 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "01" after (TCQ)*1 ps;
when 5 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "11" after (TCQ)*1 ps;
when 6 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "01" after (TCQ)*1 ps;
when 7 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "11" after (TCQ)*1 ps;
when 8 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "01" after (TCQ)*1 ps;
when 9 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "11" after (TCQ)*1 ps;
when 10 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "01" after (TCQ)*1 ps;
when 11 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "11" after (TCQ)*1 ps;
when others =>
null;
end case;
end loop;
else
cal2_state_r <= CAL2_READ_WAIT after (TCQ)*1 ps;
end if;
end if;
-- General wait state to wait for read pipe contents to settle
-- either after bitslip is changed
when CAL2_READ_WAIT =>
-- Reset read delay counter after bitslip is changed - with every
-- new bitslip setting, we need to remeasure the read delay
cal2_cnt_rd_dly_r <= "00000" after (TCQ)*1 ps;
-- Wait for rising edge of synchronized rd_active signal from
-- controller, then starts counting clock cycles until the correct
-- pattern is returned from memory. Also make sure that we've
-- waited long enough after incrementing CNT_RDEN to allow data
-- to change, and ISERDES pipeline to flush out
if ((rd_active_posedge_r = '1') and (not(rden_wait_r)) = '1') then
cal2_state_r <= CAL2_DETECT_MATCH after (TCQ)*1 ps;
end if;
-- Wait until either a match is found, or until enough cycles
-- have passed that there could not possibly be a match
when CAL2_DETECT_MATCH =>
-- Increment delay counter for every cycle we're in this state
cal2_cnt_rd_dly_r <= cal2_cnt_rd_dly_r + '1' after (TCQ)*1 ps;
if (pat_data_match_r = '1') then
-- If found data match, then move on to next DQS group
cal2_state_r <= CAL2_NEXT_DQS after (TCQ)*1 ps;
elsif (to_integer(unsigned(cal2_cnt_rd_dly_r)) = MAX_RD_DLY_CNT-1) then
if (cal2_cnt_bitslip_r /= "11") then
-- If we've waited enough cycles for worst possible "round-trip"
-- delay, then try next bitslip setting, and repeat this process
cal2_state_r <= CAL2_READ_WAIT after (TCQ)*1 ps;
cal2_cnt_bitslip_r <= cal2_cnt_bitslip_r + "01" after (TCQ)*1 ps;
-- Update bitslip count for current DQS group
if (SIM_CAL_OPTION = "FAST_CAL") then
-- Increment bitslip count - for simulation, update bitslip
-- count for all DQS groups with same value
loop_sim_bitslip: for i in 0 to DQS_WIDTH-1 loop
cal2_rd_bitslip_cnt_r((2*i)+1 downto 2*i) <= cal2_rd_bitslip_cnt_r((2*i)+1 downto 2*i) + '1' after (TCQ)*1 ps;
end loop;
else
-- Otherwise, increment only for current DQS group
if ( cal2_rd_bitslip_cnt_r(2*to_integer(unsigned(cal2_cnt_rden_r))) = '1' ) then
cal2_rd_bitslip_cnt_r(2*to_integer(unsigned(cal2_cnt_rden_r))+0) <= '0' after (TCQ)*1 ps;
cal2_rd_bitslip_cnt_r(2*to_integer(unsigned(cal2_cnt_rden_r))+1) <=
cal2_rd_bitslip_cnt_r(2*to_integer(unsigned(cal2_cnt_rden_r))+1) xor '1' after (TCQ)*1 ps;
else
cal2_rd_bitslip_cnt_r(2*to_integer(unsigned(cal2_cnt_rden_r))+0) <= '1' after (TCQ)*1 ps;
end if;
end if;
else
-- Otherwise, if we've already exhausted all bitslip settings
-- and still haven't found a match, the boat has **possibly **
-- sunk (may be an error due to write calibration still
-- figuring out its own timing)
cal2_state_r <= CAL2_ERROR_TO after (TCQ)*1 ps;
end if;
end if;
-- Final processing for current DQS group. Move on to next group
-- Determine read enable delay between current DQS and DQS[0]
when CAL2_NEXT_DQS =>
-- At this point, we've just found the correct pattern for the
-- current DQS group. Now check to see how long it took for the
-- pattern to return. Record the current delay time, as well as
-- the maximum time required across all the bytes
if (cal2_cnt_rd_dly_r > cal2_max_cnt_rd_dly_r) then
cal2_max_cnt_rd_dly_r <= cal2_cnt_rd_dly_r after (TCQ)*1 ps;
end if;
if (SIM_CAL_OPTION = "FAST_CAL") then
-- For simulation, update count for all DQS groups
for j in 0 to DQS_WIDTH - 1 loop
cal2_dly_cnt_r(5*j+4 downto 5*j) <= cal2_cnt_rd_dly_r after (TCQ)*1 ps;
end loop;
else
for idx in 0 to 4 loop
cal2_dly_cnt_r(5*to_integer(unsigned(cal2_cnt_rden_r))+idx) <= cal2_cnt_rd_dly_r(idx) after (TCQ)*1 ps;
end loop;
end if;
-- Request bank/row precharge, and wait for its completion. Always
-- precharge after each DQS group to avoid tRAS(max) violation
cal2_prech_req_r <= '1' after (TCQ)*1 ps;
if (prech_done = '1') then
if (((DQS_WIDTH = 1) or (SIM_CAL_OPTION = "FAST_CAL")) or (to_integer(unsigned(cal2_cnt_rden_r)) >= (DQS_WIDTH-1))) then
-- If either FAST_CAL is enabled and first DQS group is
-- finished, or if the last DQS group was just finished,
-- then indicate that we can switch to final values for
-- byte skews, and signal end of stage 2 calibration
cal2_en_dqs_skew_r <= '1' after (TCQ)*1 ps;
cal2_state_r <= CAL2_DONE after (TCQ)*1 ps;
else
-- Continue to next DQS group
cal2_cnt_rden_r <= cal2_cnt_rden_r + '1' after (TCQ)*1 ps;
cal2_cnt_bitslip_r <= "00" after (TCQ)*1 ps;
cal2_state_r <= CAL2_READ_WAIT after (TCQ)*1 ps;
end if;
end if;
-- Finished with read enable calibration
when CAL2_DONE =>
cal2_done_r <= '1' after (TCQ)*1 ps;
-- Error detected due to timeout from waiting for expected data pat
-- Also assert error in this case, but also allow opportunity for
-- external control logic to resume the calibration at this point
when CAL2_ERROR_TO =>
-- Assert error even though error might be temporary (until write
-- calibration logic asserts RDLVL_PAT_RESUME
rdlvl_pat_err <= '1' after (TCQ)*1 ps;
-- Wait for resume signal from write calibration logic
if (rdlvl_pat_resume = '1') then
-- Similarly, reset bitslip control for current DQS group to 0
cal2_rd_bitslip_cnt_r(2*to_integer(unsigned(cal2_cnt_rden_r))+1) <= '0' after (TCQ)*1 ps;
cal2_rd_bitslip_cnt_r(2*to_integer(unsigned(cal2_cnt_rden_r))+0) <= '0' after (TCQ)*1 ps;
cal2_cnt_bitslip_r <= (others => '0') after (TCQ)*1 ps;
cal2_state_r <= CAL2_READ_WAIT after (TCQ)*1 ps;
rdlvl_pat_err <= '0' after (TCQ)*1 ps;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
-- Display which DQS group failed when timeout error occurs during pattern
-- calibration. NOTE: Only valid when rdlvl_pat_err = 1
rdlvl_pat_err_cnt <= cal2_cnt_rden_r;
-- Final output: determine amount to delay rd_active signal by
process (clk)
begin
if (clk'event and clk = '1') then
if (SIM_CAL_OPTION = "SKIP_CAL") then
-- Hardcoded option (for simulation only). The results are very
-- specific for a testbench w/o additional net delays using a Micron
-- memory model. Any other configuration may not work.
case nCL is
when 5 =>
cal2_rd_active_dly_r <= "01010" after (TCQ)*1 ps;
when 6 =>
cal2_rd_active_dly_r <= "01010" after (TCQ)*1 ps;
when 7 =>
cal2_rd_active_dly_r <= "01011" after (TCQ)*1 ps;
when 8 =>
cal2_rd_active_dly_r <= "01011" after (TCQ)*1 ps;
when 9 =>
cal2_rd_active_dly_r <= "01100" after (TCQ)*1 ps;
when 10 =>
cal2_rd_active_dly_r <= "01100" after (TCQ)*1 ps;
when 11 =>
cal2_rd_active_dly_r <= "01101" after (TCQ)*1 ps;
when others =>
null;
end case;
elsif (rdlvl_done_1(1) = '0') then
-- Before calibration is complete, set RD_ACTIVE to minimum delay
cal2_rd_active_dly_r <= (others => '0') after (TCQ)*1 ps;
else
-- Set RD_ACTIVE based on maximum DQS group delay
cal2_rd_active_dly_r <= cal2_max_cnt_rd_dly_r - std_logic_vector(to_unsigned(RDEN_DELAY_OFFSET, 5)) after (TCQ)*1 ps;
end if;
end if;
end process;
gen_dly : for dqs_i in 0 to DQS_WIDTH-1 generate
-- Determine difference between delay for each DQS group, and the
-- DQS group with the maximum delay
process (clk)
begin
if (clk'event and clk = '1') then
cal2_dly_cnt_delta_r(dqs_i) <= cal2_max_cnt_rd_dly_r - cal2_dly_cnt_r(5*dqs_i+4 downto 5*dqs_i) after (TCQ)*1 ps;
end if;
end process;
-- Delay those DQS groups with less than the maximum delay
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
cal2_clkdly_cnt_r(2*dqs_i+1 downto 2*dqs_i) <= "00" after (TCQ)*1 ps;
cal2_deskew_err_r(dqs_i) <= '0' after (TCQ)*1 ps;
elsif (cal2_en_dqs_skew_r = '0') then
-- While calibrating, do not skew individual bytes
cal2_clkdly_cnt_r(2*dqs_i+1 downto 2*dqs_i) <= "00" after (TCQ)*1 ps;
cal2_deskew_err_r(dqs_i) <= '0' after (TCQ)*1 ps;
else
-- Once done calibrating, go ahead and skew individual bytes
case cal2_dly_cnt_delta_r(dqs_i) is
when "00000" =>
cal2_clkdly_cnt_r(2*dqs_i+1 downto 2*dqs_i) <= "00" after (TCQ)*1 ps;
cal2_deskew_err_r(dqs_i) <= '0' after (TCQ)*1 ps;
when "00001" =>
cal2_clkdly_cnt_r(2*dqs_i+1 downto 2*dqs_i) <= "01" after (TCQ)*1 ps;
cal2_deskew_err_r(dqs_i) <= '0' after (TCQ)*1 ps;
when "00010" =>
cal2_clkdly_cnt_r(2*dqs_i+1 downto 2*dqs_i) <= "10" after (TCQ)*1 ps;
cal2_deskew_err_r(dqs_i) <= '0' after (TCQ)*1 ps;
when "00011" =>
cal2_clkdly_cnt_r(2*dqs_i+1 downto 2*dqs_i) <= "11" after (TCQ)*1 ps;
cal2_deskew_err_r(dqs_i) <= '0' after (TCQ)*1 ps;
-- If there's more than 3 cycles of skew between different
-- then flag error
when others =>
cal2_clkdly_cnt_r(2*dqs_i+1 downto 2*dqs_i) <= "XX" after (TCQ)*1 ps;
cal2_deskew_err_r(dqs_i) <= '1' after (TCQ)*1 ps;
end case;
end if;
end if;
end process;
end generate;
process (clk)
begin
if (clk'event and clk = '1') then
rd_clkdly_cnt <= cal2_clkdly_cnt_r after (TCQ)*1 ps;
end if;
end process;
-- Assert when non-recoverable error occurs during stage 2 cal
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
rdlvl_err_2(1) <= '0' after (TCQ)*1 ps;
else
-- Combine errors from each of the individual DQS group deskews
rdlvl_err_2(1) <= or_br(cal2_deskew_err_r) after (TCQ)*1 ps;
end if;
end if;
end process;
-- Delay assertion of RDLVL_DONE for stage 2 by a few cycles after
-- we've reached CAL2_DONE to account for fact that the proper deskew
-- delays still need to be calculated, and driven to the individual
-- DQ/DQS delay blocks. It's not an exact science, the # of delay cycles
-- is sufficient. Feel free to add more delay if the calculation or FSM
-- logic is later changed.
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
cal2_done_r1 <= '0' after (TCQ)*1 ps;
cal2_done_r2 <= '0' after (TCQ)*1 ps;
cal2_done_r3 <= '0' after (TCQ)*1 ps;
rdlvl_done_1(1) <= '0' after (TCQ)*1 ps;
else
cal2_done_r1 <= cal2_done_r after (TCQ)*1 ps;
cal2_done_r2 <= cal2_done_r1 after (TCQ)*1 ps;
cal2_done_r3 <= cal2_done_r2 after (TCQ)*1 ps;
rdlvl_done_1(1) <= cal2_done_r3 after (TCQ)*1 ps;
end if;
end if;
end process;
end architecture arch;
|
--
-- Automatically generated
-- with the command 'bin/ipxact2vhdl --srcFile example/input/test.xml --destDir example/output'
--
-- Do not manually edit!
--
-- VHDL 93
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package example_vhd_pkg is
constant addr_width : natural := 3;
constant data_width : natural := 32;
-- monkey
type monkey_enum is (chimp, -- a monkey
gorilla,
phb); -- and another monkey
function monkey_enum_to_sulv(v: monkey_enum ) return std_ulogic_vector;
function sulv_to_monkey_enum(v: std_ulogic_vector(2-1 downto 0)) return monkey_enum;
constant reg0_addr : natural := 0 ; -- 0x0
constant reg1_addr : natural := 1 ; -- 0x1
constant reg2_addr : natural := 2 ; -- 0x2
constant reg3_addr : natural := 3 ; -- 0x3
constant reg4_addr : natural := 4 ; -- 0x4
constant reg5_addr : natural := 5 ; -- 0x5
constant reg6_addr : natural := 6 ; -- 0x6
constant reg7_addr : natural := 7 ; -- 0x7
constant reg0_reset_value : std_ulogic_vector(data_width-1 downto 0) := std_ulogic_vector(to_unsigned(0, data_width)); -- 0x00000000
constant reg1_reset_value : std_ulogic_vector(data_width-1 downto 0) := std_ulogic_vector(to_unsigned(1, data_width)); -- 0x00000001
constant reg2_reset_value : std_ulogic_vector(data_width-1 downto 0) := std_ulogic_vector(to_unsigned(1, data_width)); -- 0x00000001
constant reg3_reset_value : std_ulogic_vector(data_width-1 downto 0) := std_ulogic_vector(to_unsigned(1, data_width)); -- 0x00000001
constant reg4_reset_value : std_ulogic_vector(data_width-1 downto 0) := std_ulogic_vector(to_unsigned(12, data_width)); -- 0x0000000c
constant reg7_reset_value : std_ulogic_vector(data_width-1 downto 0) := std_ulogic_vector(to_unsigned(0, data_width)); -- 0x00000000
type reg0_record_type is record
byte3 : std_ulogic_vector(7 downto 0); -- [31:24]
byte2 : std_ulogic_vector(7 downto 0); -- [23:16]
byte1 : std_ulogic_vector(7 downto 0); -- [15:8]
byte0 : std_ulogic_vector(7 downto 0); -- [7:0]
end record;
type reg1_record_type is record
field0 : std_ulogic_vector(31 downto 0); -- [31:0]
end record;
type reg2_record_type is record
monkey2 : monkey_enum; -- [5:4]
monkey : monkey_enum; -- [3:2]
power2 : std_ulogic; -- [1]
power : std_ulogic; -- [0]
end record;
type reg3_record_type is record
field0 : std_ulogic_vector(31 downto 0); -- [31:0]
end record;
type reg4_record_type is record
reg4 : std_ulogic_vector(31 downto 0); -- [31:0]
end record;
type reg5_record_type is record
reg5 : std_ulogic_vector(31 downto 0); -- [31:0]
end record;
type reg6_record_type is record
reg6 : std_ulogic_vector(31 downto 0); -- [31:0]
end record;
type reg7_record_type is record
nibble2 : std_ulogic_vector(3 downto 0); -- [19:16]
unused1 : std_ulogic_vector(3 downto 0); -- [15:12]
nibble1 : std_ulogic_vector(3 downto 0); -- [11:8]
unused0 : std_ulogic_vector(3 downto 0); -- [7:4]
nibble0 : std_ulogic_vector(3 downto 0); -- [3:0]
end record;
type example_in_record_type is record
reg6 : reg6_record_type; -- addr 0x6
end record;
type example_out_record_type is record
reg0 : reg0_record_type; -- addr 0x0
reg1 : reg1_record_type; -- addr 0x1
reg2 : reg2_record_type; -- addr 0x2
reg3 : reg3_record_type; -- addr 0x3
reg4 : reg4_record_type; -- addr 0x4
reg5 : reg5_record_type; -- addr 0x5
reg7 : reg7_record_type; -- addr 0x7
end record;
function read_example(registers_i : example_in_record_type;
registers_o : example_out_record_type;
address : std_ulogic_vector(addr_width-1 downto 0)
) return std_ulogic_vector;
function write_example(value : std_ulogic_vector(data_width-1 downto 0);
address : std_ulogic_vector(addr_width-1 downto 0);
registers_o : example_out_record_type
) return example_out_record_type;
function reset_example return example_out_record_type;
function reset_example(address: std_ulogic_vector(addr_width-1 downto 0);
registers_o : example_out_record_type
) return example_out_record_type;
end;
package body example_vhd_pkg is
-- monkey
function monkey_enum_to_sulv(v: monkey_enum ) return std_ulogic_vector is
variable r : std_ulogic_vector(2-1 downto 0);
begin
case v is
when chimp => r:="00"; -- 0
when gorilla => r:="01"; -- 1
when phb => r:="10"; -- 2
end case;
return r;
end function;
function sulv_to_monkey_enum(v: std_ulogic_vector(2-1 downto 0)) return monkey_enum is
variable r : monkey_enum;
begin
case v is
when "00" => r:=chimp;
when "01" => r:=gorilla;
when "10" => r:=phb;
when others => r:=chimp; -- error
end case;
return r;
end function;
function reg0_record_type_to_sulv(v : reg0_record_type) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
r := (others => '0');
r(31 downto 24) := v.byte3;
r(23 downto 16) := v.byte2;
r(15 downto 8) := v.byte1;
r(7 downto 0) := v.byte0;
return r;
end function;
function sulv_to_reg0_record_type(v : std_ulogic_vector) return reg0_record_type is
variable r : reg0_record_type;
begin
r.byte3 := v(31 downto 24);
r.byte2 := v(23 downto 16);
r.byte1 := v(15 downto 8);
r.byte0 := v(7 downto 0);
return r;
end function;
function reg1_record_type_to_sulv(v : reg1_record_type) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
r := (others => '0');
r(31 downto 0) := v.field0;
return r;
end function;
function sulv_to_reg1_record_type(v : std_ulogic_vector) return reg1_record_type is
variable r : reg1_record_type;
begin
r.field0 := v(31 downto 0);
return r;
end function;
function reg2_record_type_to_sulv(v : reg2_record_type) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
r := (others => '0');
r(5 downto 4) := monkey_enum_to_sulv(v.monkey2);
r(3 downto 2) := monkey_enum_to_sulv(v.monkey);
r(1) := v.power2;
r(0) := v.power;
return r;
end function;
function sulv_to_reg2_record_type(v : std_ulogic_vector) return reg2_record_type is
variable r : reg2_record_type;
begin
r.monkey2 := sulv_to_monkey_enum(v(5 downto 4));
r.monkey := sulv_to_monkey_enum(v(3 downto 2));
r.power2 := v(1);
r.power := v(0);
return r;
end function;
function reg3_record_type_to_sulv(v : reg3_record_type) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
r := (others => '0');
r(31 downto 0) := v.field0;
return r;
end function;
function sulv_to_reg3_record_type(v : std_ulogic_vector) return reg3_record_type is
variable r : reg3_record_type;
begin
r.field0 := v(31 downto 0);
return r;
end function;
function reg4_record_type_to_sulv(v : reg4_record_type) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
r := (others => '0');
r(31 downto 0) := v.reg4;
return r;
end function;
function sulv_to_reg4_record_type(v : std_ulogic_vector) return reg4_record_type is
variable r : reg4_record_type;
begin
r.reg4 := v(31 downto 0);
return r;
end function;
function reg5_record_type_to_sulv(v : reg5_record_type) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
r := (others => '0');
r(31 downto 0) := v.reg5;
return r;
end function;
function sulv_to_reg5_record_type(v : std_ulogic_vector) return reg5_record_type is
variable r : reg5_record_type;
begin
r.reg5 := v(31 downto 0);
return r;
end function;
function reg6_record_type_to_sulv(v : reg6_record_type) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
r := (others => '0');
r(31 downto 0) := v.reg6;
return r;
end function;
function sulv_to_reg6_record_type(v : std_ulogic_vector) return reg6_record_type is
variable r : reg6_record_type;
begin
r.reg6 := v(31 downto 0);
return r;
end function;
function reg7_record_type_to_sulv(v : reg7_record_type) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
r := (others => '0');
r(19 downto 16) := v.nibble2;
r(15 downto 12) := v.unused1;
r(11 downto 8) := v.nibble1;
r(7 downto 4) := v.unused0;
r(3 downto 0) := v.nibble0;
return r;
end function;
function sulv_to_reg7_record_type(v : std_ulogic_vector) return reg7_record_type is
variable r : reg7_record_type;
begin
r.nibble2 := v(19 downto 16);
r.unused1 := v(15 downto 12);
r.nibble1 := v(11 downto 8);
r.unused0 := v(7 downto 4);
r.nibble0 := v(3 downto 0);
return r;
end function;
function read_example(registers_i : example_in_record_type;
registers_o : example_out_record_type;
address : std_ulogic_vector(addr_width-1 downto 0)
) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
case to_integer(unsigned(address)) is
when reg0_addr => r:= reg0_record_type_to_sulv(registers_o.reg0);
when reg1_addr => r:= reg1_record_type_to_sulv(registers_o.reg1);
when reg2_addr => r:= reg2_record_type_to_sulv(registers_o.reg2);
when reg3_addr => r:= reg3_record_type_to_sulv(registers_o.reg3);
when reg4_addr => r:= reg4_record_type_to_sulv(registers_o.reg4);
when reg5_addr => r:= reg5_record_type_to_sulv(registers_o.reg5);
when reg6_addr => r:= reg6_record_type_to_sulv(registers_i.reg6);
when reg7_addr => r:= reg7_record_type_to_sulv(registers_o.reg7);
when others => r := (others => '0');
end case;
return r;
end function;
function write_example(value : std_ulogic_vector(data_width-1 downto 0);
address : std_ulogic_vector(addr_width-1 downto 0);
registers_o : example_out_record_type
) return example_out_record_type is
variable r : example_out_record_type;
begin
r := registers_o;
case to_integer(unsigned(address)) is
when reg0_addr => r.reg0 := sulv_to_reg0_record_type(value);
when reg1_addr => r.reg1 := sulv_to_reg1_record_type(value);
when reg2_addr => r.reg2 := sulv_to_reg2_record_type(value);
when reg3_addr => r.reg3 := sulv_to_reg3_record_type(value);
when reg4_addr => r.reg4 := sulv_to_reg4_record_type(value);
when reg5_addr => r.reg5 := sulv_to_reg5_record_type(value);
when reg7_addr => r.reg7 := sulv_to_reg7_record_type(value);
when others => null;
end case;
return r;
end function;
function reset_example return example_out_record_type is
variable r : example_out_record_type;
begin
r.reg0 := sulv_to_reg0_record_type(reg0_reset_value);
r.reg1 := sulv_to_reg1_record_type(reg1_reset_value);
r.reg2 := sulv_to_reg2_record_type(reg2_reset_value);
r.reg3 := sulv_to_reg3_record_type(reg3_reset_value);
r.reg4 := sulv_to_reg4_record_type(reg4_reset_value);
r.reg7 := sulv_to_reg7_record_type(reg7_reset_value);
return r;
end function;
function reset_example(address: std_ulogic_vector(addr_width-1 downto 0);
registers_o : example_out_record_type
) return example_out_record_type is
variable r : example_out_record_type;
begin
r := registers_o;
case to_integer(unsigned(address)) is
when reg0_addr => r.reg0 := sulv_to_reg0_record_type(reg0_reset_value);
when reg1_addr => r.reg1 := sulv_to_reg1_record_type(reg1_reset_value);
when reg2_addr => r.reg2 := sulv_to_reg2_record_type(reg2_reset_value);
when reg3_addr => r.reg3 := sulv_to_reg3_record_type(reg3_reset_value);
when reg4_addr => r.reg4 := sulv_to_reg4_record_type(reg4_reset_value);
when reg7_addr => r.reg7 := sulv_to_reg7_record_type(reg7_reset_value);
when others => null;
end case;
return r;
end function;
end package body;
|
--
-- Automatically generated
-- with the command 'bin/ipxact2vhdl --srcFile example/input/test.xml --destDir example/output'
--
-- Do not manually edit!
--
-- VHDL 93
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package example_vhd_pkg is
constant addr_width : natural := 3;
constant data_width : natural := 32;
-- monkey
type monkey_enum is (chimp, -- a monkey
gorilla,
phb); -- and another monkey
function monkey_enum_to_sulv(v: monkey_enum ) return std_ulogic_vector;
function sulv_to_monkey_enum(v: std_ulogic_vector(2-1 downto 0)) return monkey_enum;
constant reg0_addr : natural := 0 ; -- 0x0
constant reg1_addr : natural := 1 ; -- 0x1
constant reg2_addr : natural := 2 ; -- 0x2
constant reg3_addr : natural := 3 ; -- 0x3
constant reg4_addr : natural := 4 ; -- 0x4
constant reg5_addr : natural := 5 ; -- 0x5
constant reg6_addr : natural := 6 ; -- 0x6
constant reg7_addr : natural := 7 ; -- 0x7
constant reg0_reset_value : std_ulogic_vector(data_width-1 downto 0) := std_ulogic_vector(to_unsigned(0, data_width)); -- 0x00000000
constant reg1_reset_value : std_ulogic_vector(data_width-1 downto 0) := std_ulogic_vector(to_unsigned(1, data_width)); -- 0x00000001
constant reg2_reset_value : std_ulogic_vector(data_width-1 downto 0) := std_ulogic_vector(to_unsigned(1, data_width)); -- 0x00000001
constant reg3_reset_value : std_ulogic_vector(data_width-1 downto 0) := std_ulogic_vector(to_unsigned(1, data_width)); -- 0x00000001
constant reg4_reset_value : std_ulogic_vector(data_width-1 downto 0) := std_ulogic_vector(to_unsigned(12, data_width)); -- 0x0000000c
constant reg7_reset_value : std_ulogic_vector(data_width-1 downto 0) := std_ulogic_vector(to_unsigned(0, data_width)); -- 0x00000000
type reg0_record_type is record
byte3 : std_ulogic_vector(7 downto 0); -- [31:24]
byte2 : std_ulogic_vector(7 downto 0); -- [23:16]
byte1 : std_ulogic_vector(7 downto 0); -- [15:8]
byte0 : std_ulogic_vector(7 downto 0); -- [7:0]
end record;
type reg1_record_type is record
field0 : std_ulogic_vector(31 downto 0); -- [31:0]
end record;
type reg2_record_type is record
monkey2 : monkey_enum; -- [5:4]
monkey : monkey_enum; -- [3:2]
power2 : std_ulogic; -- [1]
power : std_ulogic; -- [0]
end record;
type reg3_record_type is record
field0 : std_ulogic_vector(31 downto 0); -- [31:0]
end record;
type reg4_record_type is record
reg4 : std_ulogic_vector(31 downto 0); -- [31:0]
end record;
type reg5_record_type is record
reg5 : std_ulogic_vector(31 downto 0); -- [31:0]
end record;
type reg6_record_type is record
reg6 : std_ulogic_vector(31 downto 0); -- [31:0]
end record;
type reg7_record_type is record
nibble2 : std_ulogic_vector(3 downto 0); -- [19:16]
unused1 : std_ulogic_vector(3 downto 0); -- [15:12]
nibble1 : std_ulogic_vector(3 downto 0); -- [11:8]
unused0 : std_ulogic_vector(3 downto 0); -- [7:4]
nibble0 : std_ulogic_vector(3 downto 0); -- [3:0]
end record;
type example_in_record_type is record
reg6 : reg6_record_type; -- addr 0x6
end record;
type example_out_record_type is record
reg0 : reg0_record_type; -- addr 0x0
reg1 : reg1_record_type; -- addr 0x1
reg2 : reg2_record_type; -- addr 0x2
reg3 : reg3_record_type; -- addr 0x3
reg4 : reg4_record_type; -- addr 0x4
reg5 : reg5_record_type; -- addr 0x5
reg7 : reg7_record_type; -- addr 0x7
end record;
function read_example(registers_i : example_in_record_type;
registers_o : example_out_record_type;
address : std_ulogic_vector(addr_width-1 downto 0)
) return std_ulogic_vector;
function write_example(value : std_ulogic_vector(data_width-1 downto 0);
address : std_ulogic_vector(addr_width-1 downto 0);
registers_o : example_out_record_type
) return example_out_record_type;
function reset_example return example_out_record_type;
function reset_example(address: std_ulogic_vector(addr_width-1 downto 0);
registers_o : example_out_record_type
) return example_out_record_type;
end;
package body example_vhd_pkg is
-- monkey
function monkey_enum_to_sulv(v: monkey_enum ) return std_ulogic_vector is
variable r : std_ulogic_vector(2-1 downto 0);
begin
case v is
when chimp => r:="00"; -- 0
when gorilla => r:="01"; -- 1
when phb => r:="10"; -- 2
end case;
return r;
end function;
function sulv_to_monkey_enum(v: std_ulogic_vector(2-1 downto 0)) return monkey_enum is
variable r : monkey_enum;
begin
case v is
when "00" => r:=chimp;
when "01" => r:=gorilla;
when "10" => r:=phb;
when others => r:=chimp; -- error
end case;
return r;
end function;
function reg0_record_type_to_sulv(v : reg0_record_type) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
r := (others => '0');
r(31 downto 24) := v.byte3;
r(23 downto 16) := v.byte2;
r(15 downto 8) := v.byte1;
r(7 downto 0) := v.byte0;
return r;
end function;
function sulv_to_reg0_record_type(v : std_ulogic_vector) return reg0_record_type is
variable r : reg0_record_type;
begin
r.byte3 := v(31 downto 24);
r.byte2 := v(23 downto 16);
r.byte1 := v(15 downto 8);
r.byte0 := v(7 downto 0);
return r;
end function;
function reg1_record_type_to_sulv(v : reg1_record_type) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
r := (others => '0');
r(31 downto 0) := v.field0;
return r;
end function;
function sulv_to_reg1_record_type(v : std_ulogic_vector) return reg1_record_type is
variable r : reg1_record_type;
begin
r.field0 := v(31 downto 0);
return r;
end function;
function reg2_record_type_to_sulv(v : reg2_record_type) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
r := (others => '0');
r(5 downto 4) := monkey_enum_to_sulv(v.monkey2);
r(3 downto 2) := monkey_enum_to_sulv(v.monkey);
r(1) := v.power2;
r(0) := v.power;
return r;
end function;
function sulv_to_reg2_record_type(v : std_ulogic_vector) return reg2_record_type is
variable r : reg2_record_type;
begin
r.monkey2 := sulv_to_monkey_enum(v(5 downto 4));
r.monkey := sulv_to_monkey_enum(v(3 downto 2));
r.power2 := v(1);
r.power := v(0);
return r;
end function;
function reg3_record_type_to_sulv(v : reg3_record_type) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
r := (others => '0');
r(31 downto 0) := v.field0;
return r;
end function;
function sulv_to_reg3_record_type(v : std_ulogic_vector) return reg3_record_type is
variable r : reg3_record_type;
begin
r.field0 := v(31 downto 0);
return r;
end function;
function reg4_record_type_to_sulv(v : reg4_record_type) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
r := (others => '0');
r(31 downto 0) := v.reg4;
return r;
end function;
function sulv_to_reg4_record_type(v : std_ulogic_vector) return reg4_record_type is
variable r : reg4_record_type;
begin
r.reg4 := v(31 downto 0);
return r;
end function;
function reg5_record_type_to_sulv(v : reg5_record_type) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
r := (others => '0');
r(31 downto 0) := v.reg5;
return r;
end function;
function sulv_to_reg5_record_type(v : std_ulogic_vector) return reg5_record_type is
variable r : reg5_record_type;
begin
r.reg5 := v(31 downto 0);
return r;
end function;
function reg6_record_type_to_sulv(v : reg6_record_type) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
r := (others => '0');
r(31 downto 0) := v.reg6;
return r;
end function;
function sulv_to_reg6_record_type(v : std_ulogic_vector) return reg6_record_type is
variable r : reg6_record_type;
begin
r.reg6 := v(31 downto 0);
return r;
end function;
function reg7_record_type_to_sulv(v : reg7_record_type) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
r := (others => '0');
r(19 downto 16) := v.nibble2;
r(15 downto 12) := v.unused1;
r(11 downto 8) := v.nibble1;
r(7 downto 4) := v.unused0;
r(3 downto 0) := v.nibble0;
return r;
end function;
function sulv_to_reg7_record_type(v : std_ulogic_vector) return reg7_record_type is
variable r : reg7_record_type;
begin
r.nibble2 := v(19 downto 16);
r.unused1 := v(15 downto 12);
r.nibble1 := v(11 downto 8);
r.unused0 := v(7 downto 4);
r.nibble0 := v(3 downto 0);
return r;
end function;
function read_example(registers_i : example_in_record_type;
registers_o : example_out_record_type;
address : std_ulogic_vector(addr_width-1 downto 0)
) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
case to_integer(unsigned(address)) is
when reg0_addr => r:= reg0_record_type_to_sulv(registers_o.reg0);
when reg1_addr => r:= reg1_record_type_to_sulv(registers_o.reg1);
when reg2_addr => r:= reg2_record_type_to_sulv(registers_o.reg2);
when reg3_addr => r:= reg3_record_type_to_sulv(registers_o.reg3);
when reg4_addr => r:= reg4_record_type_to_sulv(registers_o.reg4);
when reg5_addr => r:= reg5_record_type_to_sulv(registers_o.reg5);
when reg6_addr => r:= reg6_record_type_to_sulv(registers_i.reg6);
when reg7_addr => r:= reg7_record_type_to_sulv(registers_o.reg7);
when others => r := (others => '0');
end case;
return r;
end function;
function write_example(value : std_ulogic_vector(data_width-1 downto 0);
address : std_ulogic_vector(addr_width-1 downto 0);
registers_o : example_out_record_type
) return example_out_record_type is
variable r : example_out_record_type;
begin
r := registers_o;
case to_integer(unsigned(address)) is
when reg0_addr => r.reg0 := sulv_to_reg0_record_type(value);
when reg1_addr => r.reg1 := sulv_to_reg1_record_type(value);
when reg2_addr => r.reg2 := sulv_to_reg2_record_type(value);
when reg3_addr => r.reg3 := sulv_to_reg3_record_type(value);
when reg4_addr => r.reg4 := sulv_to_reg4_record_type(value);
when reg5_addr => r.reg5 := sulv_to_reg5_record_type(value);
when reg7_addr => r.reg7 := sulv_to_reg7_record_type(value);
when others => null;
end case;
return r;
end function;
function reset_example return example_out_record_type is
variable r : example_out_record_type;
begin
r.reg0 := sulv_to_reg0_record_type(reg0_reset_value);
r.reg1 := sulv_to_reg1_record_type(reg1_reset_value);
r.reg2 := sulv_to_reg2_record_type(reg2_reset_value);
r.reg3 := sulv_to_reg3_record_type(reg3_reset_value);
r.reg4 := sulv_to_reg4_record_type(reg4_reset_value);
r.reg7 := sulv_to_reg7_record_type(reg7_reset_value);
return r;
end function;
function reset_example(address: std_ulogic_vector(addr_width-1 downto 0);
registers_o : example_out_record_type
) return example_out_record_type is
variable r : example_out_record_type;
begin
r := registers_o;
case to_integer(unsigned(address)) is
when reg0_addr => r.reg0 := sulv_to_reg0_record_type(reg0_reset_value);
when reg1_addr => r.reg1 := sulv_to_reg1_record_type(reg1_reset_value);
when reg2_addr => r.reg2 := sulv_to_reg2_record_type(reg2_reset_value);
when reg3_addr => r.reg3 := sulv_to_reg3_record_type(reg3_reset_value);
when reg4_addr => r.reg4 := sulv_to_reg4_record_type(reg4_reset_value);
when reg7_addr => r.reg7 := sulv_to_reg7_record_type(reg7_reset_value);
when others => null;
end case;
return r;
end function;
end package body;
|
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity round_f is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic;
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end round_f;
architecture Behavioral of round_f is
signal a_0_in_s : std_logic_vector(31 downto 0);
signal theta_0_s : std_logic_vector(31 downto 0);
signal theta_1_s : std_logic_vector(31 downto 0);
signal theta_2_s : std_logic_vector(31 downto 0);
signal theta_3_s : std_logic_vector(31 downto 0);
signal pi_1_1_s : std_logic_vector(31 downto 0);
signal pi_1_2_s : std_logic_vector(31 downto 0);
signal pi_1_3_s : std_logic_vector(31 downto 0);
signal gamma_0_s : std_logic_vector(31 downto 0);
signal gamma_1_s : std_logic_vector(31 downto 0);
signal gamma_2_s : std_logic_vector(31 downto 0);
signal gamma_3_s : std_logic_vector(31 downto 0);
signal pi_2_1_s : std_logic_vector(31 downto 0);
signal pi_2_2_s : std_logic_vector(31 downto 0);
signal pi_2_3_s : std_logic_vector(31 downto 0);
component theta is
port(a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component pi_1 is
port(a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component gamma is
port(a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component pi_2 is
port(a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component reg_128 is
port(clk : in std_logic;
rst : in std_logic;
data_in_0 : in std_logic_vector(31 downto 0);
data_in_1 : in std_logic_vector(31 downto 0);
data_in_2 : in std_logic_vector(31 downto 0);
data_in_3 : in std_logic_vector(31 downto 0);
data_out_0 : out std_logic_vector(31 downto 0);
data_out_1 : out std_logic_vector(31 downto 0);
data_out_2 : out std_logic_vector(31 downto 0);
data_out_3 : out std_logic_vector(31 downto 0));
end component;
signal a_0_aux_s : std_logic_vector(31 downto 0);
signal stage_0_out_0_s : std_logic_vector(31 downto 0);
signal stage_0_out_1_s : std_logic_vector(31 downto 0);
signal stage_0_out_2_s : std_logic_vector(31 downto 0);
signal stage_0_out_3_s : std_logic_vector(31 downto 0);
signal stage_1_out_0_s : std_logic_vector(31 downto 0);
signal stage_1_out_1_s : std_logic_vector(31 downto 0);
signal stage_1_out_2_s : std_logic_vector(31 downto 0);
signal stage_1_out_3_s : std_logic_vector(31 downto 0);
signal rc_delay_s : std_logic_vector(31 downto 0);
begin
rc_delay_s <= rc_in;
a_0_in_s <= (a_0_in xor rc_delay_s) when enc = '0' else a_0_in;
THETA_0 : theta port map (a_0_in_s,
a_1_in,
a_2_in,
a_3_in,
k_0_in,
k_1_in,
k_2_in,
k_3_in,
theta_0_s,
theta_1_s,
theta_2_s,
theta_3_s);
REG_STAGE_0: reg_128 port map (clk,
rst,
theta_0_s,
theta_1_s,
theta_2_s,
theta_3_s,
stage_0_out_0_s,
stage_0_out_1_s,
stage_0_out_2_s,
stage_0_out_3_s);
PI_1_0 : pi_1 port map (stage_0_out_1_s,
stage_0_out_2_s,
stage_0_out_3_s,
pi_1_1_s,
pi_1_2_s,
pi_1_3_s);
a_0_aux_s <= (stage_0_out_0_s xor rc_delay_s) when enc = '1' else stage_0_out_0_s;
REG_STAGE_1: reg_128 port map (clk,
rst,
a_0_aux_s,
pi_1_1_s,
pi_1_2_s,
pi_1_3_s,
stage_1_out_0_s,
stage_1_out_1_s,
stage_1_out_2_s,
stage_1_out_3_s);
GAMMA_0 : gamma port map (stage_1_out_0_s,
stage_1_out_1_s,
stage_1_out_2_s,
stage_1_out_3_s,
gamma_0_s,
gamma_1_s,
gamma_2_s,
gamma_3_s);
PI_2_0 : pi_2 port map (gamma_1_s,
gamma_2_s,
gamma_3_s,
pi_2_1_s,
pi_2_2_s,
pi_2_3_s);
a_0_out <= gamma_0_s;
a_1_out <= pi_2_1_s;
a_2_out <= pi_2_2_s;
a_3_out <= pi_2_3_s;
end Behavioral;
|
-- Company: Fachhochschule Dortmund
-- Engineer: Mysara Ibrahim
--
-- Create Date: 27/06/2017 10:20:32 AM
-- Design Name: Comparator Unit for Convolutional Codes example project
-- Module Name: MyComparator - Behavioral
-- Project Name: Convolutional Codes example project
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.conf_pkg.all;
entity MyComparator_tb is
-- EMPTY
end;
architecture Behavioral of MyComparator_tb is
-- Signals declaration
signal IN1: integer;
signal IN2: integer;
signal Bigger: integer;
signal Comp_clk: std_logic;
signal selectionIndex: bit;
-- Components declaration
component MyComparator
port (IN1: in integer;
IN2 : in integer;
Bigger : out integer;
Comp_clk: in std_logic;
selectionIndex : out bit);
end component;
begin
uut: MyComparator port map ( IN1 => IN1,
IN2 => IN2,
Bigger => Bigger,
Comp_clk => Comp_clk,
selectionIndex => selectionIndex);
-- Clock generated
clk_process : process
begin
Comp_clk <= '0';
wait for clk_period/2;
Comp_clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus generated
stim_proc : process
begin
wait for clk_period/2;
IN1 <= 1;
IN2 <= 2;
wait for clk_period;
IN1 <= 2;
IN2 <= 1;
wait for clk_period;
IN1 <= 2;
IN2 <= 2;
wait for clk_period;
end process;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_shadow_6_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_6_e-e.vhd,v 1.2 2005/07/15 16:20:01 wig Exp $
-- $Date: 2005/07/15 16:20:01 $
-- $Log: inst_shadow_6_e-e.vhd,v $
-- Revision 1.2 2005/07/15 16:20:01 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_shadow_6_e
--
entity inst_shadow_6_e is
-- Generics:
-- No Generated Generics for Entity inst_shadow_6_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_shadow_6_e
end inst_shadow_6_e;
--
-- End of Generated Entity inst_shadow_6_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
entity guard is
end entity;
architecture test of guard is
signal value : natural := 0;
signal output : natural;
begin
b1: block (value < 10) is
begin
p1: output <= guarded value * 2;
p2: with output select value <= guarded output + 1 when others;
end block;
end architecture;
|
-- *** a.a-CU-HW.vhd *** --
-- this block is describes the control unit.
-- This is a Hardwired control unit
-- Microcode LUT is declared directly here
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.myTypes.all;
entity dlx_cu is
generic (
MICROCODE_MEM_SIZE : integer := 64; -- Microcode Memory Size
FUNC_SIZE : integer := 11; -- Func Field Size for R-Type Ops
OP_CODE_SIZE : integer := 6; -- Op Code Size
IR_SIZE : integer := 32; -- Instruction Register Size
CW_SIZE : integer := 13); -- Control Word Size
port (
Clk : in std_logic; -- Clock
Rst : in std_logic; -- Reset: Active-High
IR_IN : in std_logic_vector(IR_SIZE - 1 downto 0); -- Instruction Register
stall_exe_i : in std_logic; -- Stall signal coming from EXE stage
mispredict_i : in std_logic;
D1_i : in std_logic_vector(4 downto 0); -- Destination register of exe stage
D2_i : in std_logic_vector(4 downto 0); -- Destination register of mem stage
S1_LATCH_EN : out std_logic; -- Latch enable of Fetch stage
S2_LATCH_EN : out std_logic; -- Latch enable of Dec stage
S3_LATCH_EN : out std_logic; -- Latch enable of Exe stage
S_MUX_PC_BUS : out std_logic_vector(1 downto 0); -- Control of mux to PC
S_EXT : out std_logic; -- Control of extender
S_EXT_SIGN : out std_logic; -- Control of extender sign
S_EQ_NEQ : out std_logic; -- Control of Comparator
S_MUX_DEST : out std_logic_vector(1 downto 0); -- Control of Destination register
S_MUX_LINK : out std_logic; -- Control of link mux
S_MUX_MEM : out std_logic; -- Control of mux to memory address
S_MEM_W_R : out std_logic; -- Control of mem W/R
S_MEM_EN : out std_logic; -- Control mem enable
S_RF_W_wb : out std_logic; -- Control WB enable
S_RF_W_mem : out std_logic; -- Current op in mem is going to write on wb?
S_RF_W_exe : out std_logic; -- Current op in exe is going to write on wb?
S_MUX_ALUIN : out std_logic; -- Control ALU input ( IMM or B )
stall_exe_o : out std_logic; -- Stall exe stage
stall_dec_o : out std_logic; -- Stall dec stage
stall_fetch_o : out std_logic; -- Stall fetch stage
stall_btb_o : out std_logic; -- Stall btb
was_branch_o : out std_logic; -- Op in decode is a branch or not?
was_jmp_o : out std_logic;
ALU_WORD_o : out std_logic_vector(12 downto 0); -- Opcode to ALU
ALU_OPCODE : out aluOp -- Opcode to ALU
);
end dlx_cu;
architecture dlx_cu_hw of dlx_cu is
-- ***************************
-- *** SIGNAL DECLARATIONS ***
-- ***************************
-- this is the microcode memory, it works as a LUT -> to decode an instruction it's opcode indexes this memory
signal IR_opcode : std_logic_vector(OP_CODE_SIZE -1 downto 0); -- OpCode part of IR
signal IR_func : std_logic_vector(FUNC_SIZE -1 downto 0); -- Func part of IR when Rtype
signal cw_d : std_logic_vector(CW_SIZE - 1 downto 0);
signal cw_from_mem : std_logic_vector(CW_SIZE - 1 downto 0); -- full control word read from cw_mem
-- control word is shifted to the correct stage
signal cw_e : std_logic_vector(CW_SIZE - 1 - 6 downto 0); -- second stage
signal cw_m : std_logic_vector(CW_SIZE - 1 - 9 downto 0); -- third stage
signal cw_w : std_logic_vector(CW_SIZE - 1 - 12 downto 0); -- fourth stage
signal aluOpcode_d : aluOp := NOP; -- ALUOP defined in package -- ! MIGHT NOT BE SYNTHESIZABLE
signal aluOpcode_e : aluOp := NOP; -- shifted ALUOP to feed execute stage -- ! MIGHT NOT BE SYNTHESIZABLE
signal S_MEM_LOAD : std_logic; -- is current op in mem stage a LOAD?
signal S_EXE_LOAD : std_logic; -- is current op in exe stage a LOAD?
-- stall signals from stall unit
signal stall_exe_o_TEMP : std_logic;
signal stall_dec_o_TEMP : std_logic;
signal stall_btb_o_TEMP : std_logic;
signal stall_fetch_o_TEMP : std_logic;
signal bubble_dec : std_logic; -- transform next op in decode into a NOP
signal next_bubble_dec : std_logic;
signal bubble_exe : std_logic; -- transform next op in exe into a NOP
signal next_bubble_exe : std_logic;
-- ********************************
-- *** COMPONENTS DECLARATION ***
-- ********************************
component cw_mem is
generic (
MICROCODE_MEM_SIZE : integer; -- Microcode Memory Size
OP_CODE_SIZE : integer; -- Op Code Size
CW_SIZE : integer -- Control Word Size
);
port (
OPCODE_IN : in std_logic_vector(OP_CODE_SIZE - 1 downto 0); -- Instruction Register
CW_OUT : out std_logic_vector(CW_SIZE - 1 downto 0)
);
end component;
component alu_ctrl is
port (
OP : in AluOp;
BOOTH_STALL : in std_logic;
ALU_WORD : out std_logic_vector(12 downto 0)
);
end component;
-- instantiation of stall_logic block
component stall_logic is
generic (
FUNC_SIZE : integer; -- Func Field Size for R-Type Ops
OP_CODE_SIZE : integer -- Op Code Size
);
port (
-- Instruction Register
OPCODE_i : in std_logic_vector(OP_CODE_SIZE-1 downto 0);
FUNC_i : in std_logic_vector(FUNC_SIZE-1 downto 0);
rA_i : in std_logic_vector(4 downto 0);
rB_i : in std_logic_vector(4 downto 0);
D1_i : in std_logic_vector(4 downto 0); -- taken from output of destination mux in EXE stage
D2_i : in std_logic_vector(4 downto 0);
S_mem_LOAD_i : in std_logic;
S_exe_LOAD_i : in std_logic;
S_exe_WRITE_i : in std_logic;
S_MUX_PC_BUS_i : in std_logic_vector(1 downto 0);
mispredict_i : in std_logic;
bubble_dec_o : out std_logic;
bubble_exe_o : out std_logic;
stall_exe_o : out std_logic;
stall_dec_o : out std_logic;
stall_btb_o : out std_logic;
stall_fetch_o : out std_logic
);
end component;
begin
-- ********************************
-- *** COMPONENTS INSTANTIATION ***
-- ********************************
STALL_L : stall_logic
generic map (
FUNC_SIZE => 11,
OP_CODE_SIZE => 6
)
port map(
-- Instruction Register
OPCODE_i => IR_opcode,
FUNC_i => IR_func,
rA_i => IR_IN(25 downto 21),
rB_i => IR_IN(20 downto 16),
D1_i => D1_i,
D2_i => D2_i,
S_mem_LOAD_i => S_MEM_LOAD,
S_exe_LOAD_i => S_EXE_LOAD,
S_exe_WRITE_i => cw_e(CW_SIZE - 13),
S_MUX_PC_BUS_i => cw_d(CW_SIZE - 1 downto CW_SIZE - 2),
mispredict_i => mispredict_i,
bubble_dec_o => next_bubble_dec,
bubble_exe_o => next_bubble_exe,
stall_exe_o => stall_exe_o_TEMP,
stall_dec_o => stall_dec_o_TEMP,
stall_btb_o => stall_btb_o_TEMP,
stall_fetch_o => stall_fetch_o_TEMP
);
CWM : cw_mem
generic map(
MICROCODE_MEM_SIZE => MICROCODE_MEM_SIZE,
OP_CODE_SIZE => OP_CODE_SIZE,
CW_SIZE => CW_SIZE
)
port map(
OPCODE_IN => IR_opcode,
CW_OUT => cw_from_mem
);
ALU_C: alu_ctrl
port map(
OP => aluopcode_d,
BOOTH_STALL => stall_dec_o_TEMP,
ALU_WORD => ALU_WORD_o
);
-- stall signals for each individual stage of the pipeline
-- an OR is needed cause a stall might come from ALU too
stall_exe_o <= stall_exe_i or stall_exe_o_TEMP;
stall_dec_o <= stall_exe_i or stall_dec_o_TEMP;
stall_fetch_o <= stall_exe_i or stall_fetch_o_TEMP;
stall_btb_o <= stall_exe_i or stall_btb_o_TEMP;
-- split function in OPCODE and FUNC
IR_opcode(5 downto 0) <= IR_IN(31 downto 26);
IR_func(10 downto 0) <= IR_IN(FUNC_SIZE - 1 downto 0);
-- control work is assigned to the word looked up in microcode memory
-- in case of bubble_dec, a NOP cw is fed instead
cw_d <= cw_from_mem when bubble_dec = '0' else "0000000000000";
-- *** ATM THE LATCH ENABLES ARE DOING NOTHING! EVERYTHING IS CONTROLLED BY STALL ***
S1_LATCH_EN <= '1';
S2_LATCH_EN <= '1';
S3_LATCH_EN <= '1';
-- DEC stage control signals
S_MUX_PC_BUS <= cw_d(CW_SIZE - 1 downto CW_SIZE - 2);
S_EXT <= cw_d(CW_SIZE - 3);
S_EXT_SIGN <= cw_d(CW_SIZE - 4);
S_EQ_NEQ <= cw_d(CW_SIZE - 5);
S_MUX_LINK <= cw_d(CW_SIZE - 6);
-- EXE stage control signals
S_MUX_ALUIN <= cw_e(CW_SIZE - 7);
S_MUX_DEST <= cw_e(CW_SIZE - 8 downto CW_SIZE - 9);
-- MEM stage control signals
S_MEM_EN <= cw_m(CW_SIZE - 10);
S_MEM_W_R <= cw_m(CW_SIZE - 11);
S_MUX_MEM <= cw_m(CW_SIZE - 12);
-- WB stage control signals
S_RF_W_wb <= cw_w(CW_SIZE - 13);
-- RF write signal is sent to other stages to compute hazards/forwarding
S_RF_W_mem <= cw_m(CW_SIZE - 13);
S_RF_W_exe <= cw_e(CW_SIZE - 13);
-- is the current op in mem stage a LOAD?
S_MEM_LOAD <= cw_m(CW_SIZE - 10) and (not cw_m(CW_SIZE - 11));
-- is the current op in exe stage a LOAD?
S_EXE_LOAD <= cw_e(CW_SIZE - 10) and (not cw_e(CW_SIZE - 11));
-- is current op in DEC stage a branch?
was_branch_o <= cw_d(CW_SIZE - 1) and cw_d(CW_SIZE - 2);
-- is current op in DEC stage an inconditional jump?
was_jmp_o <= cw_d(CW_SIZE - 1) xor cw_d(CW_SIZE - 2);
ALU_OPCODE <= aluOpcode_e;
-- ********************************
-- *** PROCESSES ***
-- ********************************
-- sequential process to manage and pipeline control words
CW_PIPE: process (Clk, Rst)
begin -- process Clk
if Rst = '1' then -- asynchronous reset (active high)
cw_e <= (others => '0');
cw_m <= (others => '0');
cw_w <= (others => '0');
aluOpcode_e <= NOP;
elsif Clk'event and Clk = '1' then -- rising clock edge
-- update of the bubbe signal
-- bubble means: cancel next operation and make it a nop ( used in case of misprediction or inconditional jumps)
bubble_dec <= next_bubble_dec;
bubble_exe <= next_bubble_exe;
-- EXE stalled
if stall_exe_i = '1' or stall_exe_o_TEMP = '1' then
cw_m <= "0000"; -- NOP instertion
cw_e <= cw_e;
aluOpcode_e <= aluOpcode_e;
-- DEC stalled
elsif stall_dec_o_TEMP = '1' then
cw_e <= "0000000"; -- NOP instertion
cw_m <= cw_e(CW_SIZE - 1 - 9 downto 0);
-- no stall
else
cw_e <= cw_d(CW_SIZE - 1 - 6 downto 0);
cw_m <= cw_e(CW_SIZE - 1 - 9 downto 0);
aluOpcode_e <= aluOpcode_d;
end if;
-- WB cannot be stalled
cw_w <= cw_m(CW_SIZE - 1 - 12 downto 0);
end if;
end process CW_PIPE;
-- combinatorial process to generate ALU OP CODES
ALU_OP_CODE_P : process (IR_opcode, IR_func)
begin
case conv_integer(unsigned(IR_opcode)) is
-- case of R type requires analysis of FUNC
when 0 =>
case conv_integer(unsigned(IR_func)) is
when 4 => aluOpcode_d <= SLLS; -- sll according to instruction set coding
when 6 => aluOpcode_d <= SRLS;
when 7 => aluOpcode_d <= SRAS;
when 32 => aluOpcode_d <= ADDS;
when 33 => aluOpcode_d <= ADDUS;
when 34 => aluOpcode_d <= SUBS;
when 35 => aluOpcode_d <= SUBUS;
when 36 => aluOpcode_d <= ANDS;
when 37 => aluOpcode_d <= ORS;
when 38 => aluOpcode_d <= XORS;
when 40 => aluOpcode_d <= SEQS;
when 41 => aluOpcode_d <= SNES;
when 42 => aluOpcode_d <= SLTS;
when 43 => aluOpcode_d <= SGTS;
when 44 => aluOpcode_d <= SLES;
when 45 => aluOpcode_d <= SGES;
when 48 => aluOpcode_d <= MOVI2SS;
when 49 => aluOpcode_d <= MOVS2IS;
when 50 => aluOpcode_d <= MOVFS;
when 51 => aluOpcode_d <= MOVDS;
when 52 => aluOpcode_d <= MOVFP2IS;
when 53 => aluOpcode_d <= MOVI2FP;
when 54 => aluOpcode_d <= MOVI2TS;
when 55 => aluOpcode_d <= MOVT2IS;
when 58 => aluOpcode_d <= SLTUS;
when 59 => aluOpcode_d <= SGTUS;
when 60 => aluOpcode_d <= SLEUS;
when 61 => aluOpcode_d <= SGEUS;
when others => aluOpcode_d <= NOP; -- might not be synthesizable
end case;
-- type F instruction case -- MULT only at the moment
when 1 =>
case conv_integer(unsigned(IR_func)) is
when 22 => aluOpcode_d <= MULTU;
when 14 => aluOpcode_d <= MULTS;
when others => aluOpcode_d <= NOP; -- might not be synthesizable
end case;
-- I-TYPE instructions
when 2 => aluOpcode_d <= NOP; -- j
when 3 => aluOpcode_d <= NOP; -- jal
when 4 => aluOpcode_d <= NOP; -- beqz
when 5 => aluOpcode_d <= NOP; -- bnez
when 8 => aluOpcode_d <= ADDS; -- addi
when 9 => aluOpcode_d <= ADDUS; -- addui
when 10 => aluOpcode_d <= SUBS; -- subi
when 11 => aluOpcode_d <= SUBUS; -- subui
when 12 => aluOpcode_d <= ANDS; -- andi
when 13 => aluOpcode_d <= ORS; -- ori
when 14 => aluOpcode_d <= XORS; -- xori
when 18 => aluOpcode_d <= NOP; -- jr
when 19 => aluOpcode_d <= NOP; -- jalr
when 20 => aluOpcode_d <= SLLS; -- slli
when 21 => aluOpcode_d <= NOP; -- nop
when 22 => aluOpcode_d <= SRLS; -- srli
when 23 => aluOpcode_d <= SRAS; -- srai
when 24 => aluOpcode_d <= SEQS; -- seqi
when 25 => aluOpcode_d <= SNES; -- snei
when 26 => aluOpcode_d <= SLTS; -- slti
when 27 => aluOpcode_d <= SGTS; -- sgti
when 28 => aluOpcode_d <= SLES; -- slei
when 29 => aluOpcode_d <= SGES; -- sgei
when 35 => aluOpcode_d <= ADDS; -- lw
when 43 => aluOpcode_d <= ADDS; -- sw
when 58 => aluOpcode_d <= SLTUS; -- sltui
when 59 => aluOpcode_d <= SGTUS; -- sgtui
when 60 => aluOpcode_d <= SLEUS; -- sleui
when 61 => aluOpcode_d <= SGEUS; -- sgeui
when others => aluOpcode_d <= NOP; -- might not be synthesizable
end case;
end process ALU_OP_CODE_P;
end dlx_cu_hw;
|
library IEEE;
use IEEE.Std_Logic_1164.all;
entity myMux2 is
port(a: in std_logic; b: in std_logic; sel: in std_logic; s: out std_logic);
end myMux2;
architecture behavioral of myMux2 is
component myAnd2
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
component myOr2
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
component myNot
port(a: in std_logic; s: out std_logic);
end component;
signal selNot: std_logic;
signal aAndNotSelOut: std_logic;
signal bAndSelOut: std_logic;
begin
myNot_1: myNot port map(a => sel, s => selNot);
myAnd2_1: myAnd2 port map(a => a, b => selNot, s => aAndNotSelOut);
myAnd2_2: myAnd2 port map(a => b, b => sel, s => bAndSelOut);
myOr2_1: myOr2 port map(a => aAndNotSelOut, b => bAndSelOut, s => s);
end behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: charrom_package
-- File: charrom_package.vhd
-- Author: Marcus Hellqvist
-- Description: Charrom types and component
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
package charrom_package is
type rom_type is record
addr : std_logic_vector(11 downto 0);
data : std_logic_vector(7 downto 0);
end record;
component charrom
port(
clk : in std_ulogic;
addr : in std_logic_vector(11 downto 0);
data : out std_logic_vector(7 downto 0)
);
end component;
end package;
|
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: VHDL Package - ReconOS
--
-- project: ReconOS
-- author: Enno Lübbers, University of Paderborn
-- Andreas Agne, University of Paderborn
-- Christoph Rüthing, University of Paderborn
-- description: The entire ReconOS package with type definitions and
-- hardware OS services in VHDL
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
package reconos_pkg is
constant C_FIFO_WIDTH : integer := 32;
constant C_OSIF_WIDTH : integer := C_FIFO_WIDTH;
constant C_MEMIF_WIDTH : integer := C_FIFO_WIDTH;
-- any request will be split up in multiple requests of size C_CHUNK_SIZE (in words)
constant C_CHUNK_SIZE : integer := 64;
constant C_CHUNK_SIZE_BYTES : integer := C_CHUNK_SIZE * 4;
constant C_MEMIF_LENGTH_WIDTH : integer := 24;
constant C_MEMIF_CMD_WIDTH : integer := C_MEMIF_WIDTH - C_MEMIF_LENGTH_WIDTH;
-- common constants
constant C_RECONOS_FAILURE : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"00000000";
constant C_RECONOS_SUCCESS : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"00000001";
-- commands
constant OSIF_CMD_THREAD_GET_INIT_DATA : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000A0";
constant OSIF_CMD_THREAD_DELAY : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000A1"; -- ToDo
constant OSIF_CMD_THREAD_EXIT : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000A2";
constant OSIF_CMD_THREAD_YIELD : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000A3"; -- ToDo
constant OSIF_CMD_THREAD_RESUME : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000A4"; -- ToDo
constant OSIF_CMD_THREAD_LOAD_STATE : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000A5"; -- ToDo
constant OSIF_CMD_THREAD_STORE_STATE : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000A6"; -- ToDo
constant OSIF_CMD_SEM_POST : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000B0";
constant OSIF_CMD_SEM_WAIT : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000B1";
constant OSIF_CMD_MUTEX_LOCK : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000C0";
constant OSIF_CMD_MUTEX_UNLOCK : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000C1";
constant OSIF_CMD_MUTEX_TRYLOCK : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000C2"; -- Not tested, yet
constant OSIF_CMD_COND_WAIT : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000D0"; -- Not tested, yet
constant OSIF_CMD_COND_SIGNAL : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000D1"; -- Not tested, yet
constant OSIF_CMD_COND_BROADCAST : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000D2"; -- Not tested, yet
constant OSIF_CMD_RQ_RECEIVE : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000E0"; -- ToDo
constant OSIF_CMD_RQ_SEND : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000E1"; -- ToDo
constant OSIF_CMD_MBOX_GET : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000F0";
constant OSIF_CMD_MBOX_PUT : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000F1";
constant OSIF_CMD_MBOX_TRYGET : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000F2"; -- ToDo
constant OSIF_CMD_MBOX_TRYPUT : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000F3"; -- ToDo
constant OSIF_CMD_YIELD_MASK : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"80000000";
constant MEMIF_CMD_READ : std_logic_vector(C_MEMIF_CMD_WIDTH - 1 downto 0) := X"00";
constant MEMIF_CMD_WRITE : std_logic_vector(C_MEMIF_CMD_WIDTH - 1 downto 0) := X"F0";
-- type definitions for easier handling of signals
type i_fifo_t is record
s_data : std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
s_fill : std_logic_vector(15 downto 0);
s_empty : std_logic;
m_rem : std_logic_vector(15 downto 0);
m_full : std_logic;
s_re : std_logic;
m_we : std_logic;
step : integer range 0 to 15;
void : std_logic;
end record;
type o_fifo_t is record
s_re : std_logic;
m_data : std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
m_we : std_logic;
step : integer range 0 to 15;
void : std_logic;
end record;
alias i_osif_t is i_fifo_t;
alias o_osif_t is o_fifo_t;
alias i_memif_t is i_fifo_t;
alias o_memif_t is o_fifo_t;
type i_ram_t is record
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
count : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 3 downto 0);
remote_addr : std_logic_vector(31 downto 0);
remainder : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 3 downto 0);
step : integer range 0 to 15;
end record;
type o_ram_t is record
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
we : std_logic;
count : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 3 downto 0);
remote_addr : std_logic_vector(31 downto 0);
remainder : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 3 downto 0);
step : integer range 0 to 15;
end record;
-- setup functions
procedure fifo_setup (
signal i_fifo : out i_fifo_t;
signal o_fifo : in o_fifo_t;
signal s_data : in std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
signal s_fill : in std_logic_vector(15 downto 0);
signal s_empty : in std_logic;
signal m_rem : in std_logic_vector(15 downto 0);
signal m_full : in std_logic;
signal s_re : out std_logic;
signal m_data : out std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
signal m_we : out std_logic
);
procedure fifo_reset (
signal o_fifo : out o_fifo_t
);
procedure osif_setup (
signal i_osif : out i_osif_t;
signal o_osif : in o_osif_t;
signal sw2hw_data : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal sw2hw_fill : in std_logic_vector(15 downto 0);
signal sw2hw_empty : in std_logic;
signal hw2sw_rem : in std_logic_vector(15 downto 0);
signal hw2sw_full : in std_logic;
signal sw2hw_re : out std_logic;
signal hw2sw_data : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal hw2sw_we : out std_logic
);
procedure osif_reset (
signal o_osif : out o_osif_t
);
procedure memif_setup (
signal i_memif : out i_memif_t;
signal o_memif : in o_memif_t;
signal mem2hwt_data : in std_logic_vector(C_MEMIF_WIDTH - 1 downto 0);
signal mem2hwt_fill : in std_logic_vector(15 downto 0);
signal mem2hwt_empty : in std_logic;
signal hwt2mem_rem : in std_logic_vector(15 downto 0);
signal hwt2mem_full : in std_logic;
signal mem2hwt_re : out std_logic;
signal hwt2mem_data : out std_logic_vector(C_MEMIF_WIDTH - 1 downto 0);
signal hwt2mem_we : out std_logic
);
procedure memif_reset (
signal o_memif : out o_memif_t
);
procedure ram_setup (
signal i_ram : out i_ram_t;
signal o_ram : in o_ram_t;
signal addr : out std_logic_vector(C_MEMIF_WIDTH - 1 downto 0);
signal we : out std_logic;
signal o_data : out std_logic_vector(C_MEMIF_WIDTH - 1 downto 0);
signal i_data : in std_logic_vector(C_MEMIF_WIDTH - 1 downto 0)
);
procedure ram_reset (
signal o_ram : out o_ram_t
);
-- fifo access functions
procedure fifo_default (
signal o_fifo : out o_fifo_t
);
procedure fifo_pull_word (
signal i_fifo : in i_fifo_t;
signal o_fifo : out o_fifo_t;
signal result : out std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
next_step : integer;
continue : boolean
);
procedure fifo_push_word (
signal i_fifo : in i_fifo_t;
signal o_fifo : out o_fifo_t;
data : std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
next_step : integer
);
procedure fifo_pull (
signal i_fifo : in i_fifo_t;
signal o_fifo : out o_fifo_t;
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
count : in std_logic_vector(C_MEMIF_LENGTH_WIDTH - 3 downto 0);
next_step : integer
);
procedure fifo_push (
signal i_fifo : in i_fifo_t;
signal o_fifo : out o_fifo_t;
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
count : in std_logic_vector(C_MEMIF_LENGTH_WIDTH - 3 downto 0);
next_step : integer
);
-- functions to access osif directly
procedure osif_read (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_write (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
data : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
-- generic osif functions
procedure osif_call_0 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_call_1 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
arg0 : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_call_1_2 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
arg0 : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result1 : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result2 : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_call_2 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
arg0 : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
arg1 : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
-- osif functions
procedure osif_set_yield (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t
);
procedure osif_sem_post (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_sem_wait (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_mutex_lock (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_mutex_unlock (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_mutex_trylock (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_cond_wait (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
cond_handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
mutex_handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_cond_signal (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_cond_broadcast (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_mbox_put (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
word : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_mbox_get (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_mbox_tryput (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
word : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_mbox_tryget (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result1 : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result2 : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_rq_receive (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
size : in std_logic_vector(31 downto 0);
addr : in std_logic_vector(31 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_rq_send (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
size : in std_logic_vector(31 downto 0);
addr : in std_logic_vector(31 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_get_init_data (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_thread_exit (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t
);
-- memif functions
procedure memif_flush (
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
variable done : out boolean
);
procedure memif_write_word (
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
addr : in std_logic_vector(31 downto 0);
data : in std_logic_vector(31 downto 0);
variable done : out boolean
);
procedure memif_read_word (
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
addr : in std_logic_vector(31 downto 0);
signal data : out std_logic_vector(31 downto 0);
variable done : out boolean
);
procedure memif_write (
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
src_addr : in std_logic_vector(31 downto 0);
dst_addr : in std_logic_vector(31 downto 0);
len : in std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure memif_read (
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
src_addr : in std_logic_vector(31 downto 0);
dst_addr : in std_logic_vector(31 downto 0);
len : in std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
variable done : out boolean
);
end package reconos_pkg;
package body reconos_pkg is
procedure fifo_setup (
signal i_fifo : out i_fifo_t;
signal o_fifo : in o_fifo_t;
signal s_data : in std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
signal s_fill : in std_logic_vector(15 downto 0);
signal s_empty : in std_logic;
signal m_rem : in std_logic_vector(15 downto 0);
signal m_full : in std_logic;
signal s_re : out std_logic;
signal m_data : out std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
signal m_we : out std_logic
) is begin
i_fifo.step <= o_fifo.step;
i_fifo.s_data <= s_data;
i_fifo.s_fill <= s_fill;
i_fifo.s_empty <= s_empty;
i_fifo.m_rem <= m_rem;
i_fifo.m_full <= m_full;
s_re <= o_fifo.s_re;
m_data <= o_fifo.m_data;
m_we <= o_fifo.m_we;
i_fifo.s_re <= o_fifo.s_re;
i_fifo.m_we <= o_fifo.m_we;
i_fifo.void <= o_fifo.void;
end procedure fifo_setup;
procedure fifo_reset (
signal o_fifo : out o_fifo_t
) is begin
o_fifo.step <= 0;
o_fifo.m_we <= '0';
o_fifo.s_re <= '0';
o_fifo.m_data <= (others => '0');
o_fifo.void <= '0';
end procedure fifo_reset;
procedure osif_setup (
signal i_osif : out i_osif_t;
signal o_osif : in o_osif_t;
signal sw2hw_data : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal sw2hw_fill : in std_logic_vector(15 downto 0);
signal sw2hw_empty : in std_logic;
signal hw2sw_rem : in std_logic_vector(15 downto 0);
signal hw2sw_full : in std_logic;
signal sw2hw_re : out std_logic;
signal hw2sw_data : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal hw2sw_we : out std_logic
) is begin
fifo_setup(i_osif, o_osif, sw2hw_data, sw2hw_fill, sw2hw_empty,
hw2sw_rem, hw2sw_full, sw2hw_re, hw2sw_data, hw2sw_we);
end procedure osif_setup;
procedure osif_reset (
signal o_osif : out o_osif_t
) is begin
fifo_reset(o_osif);
end procedure osif_reset;
procedure memif_setup (
signal i_memif : out i_memif_t;
signal o_memif : in o_memif_t;
signal mem2hwt_data : in std_logic_vector(C_MEMIF_WIDTH - 1 downto 0);
signal mem2hwt_fill : in std_logic_vector(15 downto 0);
signal mem2hwt_empty : in std_logic;
signal hwt2mem_rem : in std_logic_vector(15 downto 0);
signal hwt2mem_full : in std_logic;
signal mem2hwt_re : out std_logic;
signal hwt2mem_data : out std_logic_vector(C_MEMIF_WIDTH - 1 downto 0);
signal hwt2mem_we : out std_logic
) is begin
fifo_setup(i_memif, o_memif, mem2hwt_data, mem2hwt_fill, mem2hwt_empty,
hwt2mem_rem, hwt2mem_full, mem2hwt_re, hwt2mem_data, hwt2mem_we);
end procedure memif_setup;
procedure memif_reset (
signal o_memif : out o_memif_t
) is begin
fifo_reset(o_memif);
end procedure memif_reset;
procedure ram_setup (
signal i_ram : out i_ram_t;
signal o_ram : in o_ram_t;
signal addr : out std_logic_vector(C_MEMIF_WIDTH - 1 downto 0);
signal we : out std_logic;
signal o_data : out std_logic_vector(C_MEMIF_WIDTH - 1 downto 0);
signal i_data : in std_logic_vector(C_MEMIF_WIDTH - 1 downto 0)
) is begin
i_ram.data <= i_data;
addr <= o_ram.addr;
we <= o_ram.we;
o_data <= o_ram.data;
i_ram.addr <= o_ram.addr;
i_ram.count <= o_ram.count;
i_ram.step <= o_ram.step;
i_ram.remote_addr <= o_ram.remote_addr;
i_ram.remainder <= o_ram.remainder;
end procedure ram_setup;
procedure ram_reset (
signal o_ram : out o_ram_t
) is begin
o_ram.we <= '0';
o_ram.addr <= (others => '0');
o_ram.data <= (others => '0');
o_ram.count <= (others => '0');
o_ram.step <= 0;
o_ram.remote_addr <= (others => '0');
o_ram.remainder <= (others => '0');
end procedure ram_reset;
-- fifo access functions
procedure fifo_default (
signal o_fifo : out o_fifo_t
) is begin
o_fifo.s_re <= '0';
o_fifo.m_we <= '0';
end procedure fifo_default;
procedure fifo_pull_word (
signal i_fifo : in i_fifo_t;
signal o_fifo : out o_fifo_t;
signal result : out std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
next_step : integer;
continue : boolean
) is begin
-- set re, if FIFO is empty this is no problem
--if i_fifo.s_empty = '0' then
o_fifo.s_re <= '1';
--end if;
-- read data one clock cycle after setting the re
-- and only if FIFO not empty
if i_fifo.s_empty = '0' and i_fifo.s_re = '1' then
result <= i_fifo.s_data;
o_fifo.step <= next_step;
-- stop reading if continue is false (last read)
if not continue then
o_fifo.s_re <= '0';
end if;
end if;
end procedure fifo_pull_word;
procedure fifo_push_word (
signal i_fifo : in i_fifo_t;
signal o_fifo : out o_fifo_t;
data : std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
next_step : integer
) is begin
o_fifo.m_data <= data;
if i_fifo.m_full = '0'
and (i_fifo.m_we = '0' or or_reduce(i_fifo.m_rem) = '1') then
-- write data into FIFO if
-- FIFO is not full
-- and no previous write or more than one word free
o_fifo.m_we <= '1';
o_fifo.step <= next_step;
end if;
end procedure fifo_push_word;
procedure fifo_pull (
signal i_fifo : in i_fifo_t;
signal o_fifo : out o_fifo_t;
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
count : in std_logic_vector(C_MEMIF_LENGTH_WIDTH - 3 downto 0);
next_step : integer
) is begin
case i_ram.step is
when 0 =>
-- because of the FIFO implementation used
-- we can keep the RE high and check the empty flag
o_fifo.s_re <= '1';
-- set address one word before actual address
--o_ram.addr <= i_ram.addr - 1;
o_ram.step <= 1;
o_ram.count <= (others => '0');
when 1 =>
o_fifo.s_re <= '1';
if i_fifo.s_empty = '0' then
o_ram.we <= '1';
o_ram.data <= i_fifo.s_data;
if or_reduce(i_ram.count) = '0' then
o_ram.addr <= i_ram.addr;
else
o_ram.addr <= i_ram.addr + 1;
end if;
o_ram.count <= i_ram.count + 1;
if i_ram.count = count - 1 then
o_ram.step <= 2;
end if;
end if;
when others =>
o_ram.we <= '0';
o_ram.step <= 0;
o_fifo.step <= next_step;
end case;
end procedure fifo_pull;
procedure fifo_push (
signal i_fifo : in i_fifo_t;
signal o_fifo : out o_fifo_t;
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
count : in std_logic_vector(C_MEMIF_LENGTH_WIDTH - 3 downto 0);
next_step : integer
) is begin
case i_ram.step is
when 0 =>
-- waiting for FIFO to become empty enough
-- this is not so nice, but should be now major drawback
-- since the FIFOs are empty most of the time
if i_fifo.m_full = '0' and i_fifo.m_rem >= count - 1 then
o_ram.count <= (others => '0');
o_ram.addr <= i_ram.addr + 1;
o_ram.step <= 1;
end if;
when 1 =>
o_fifo.m_we <= '1';
o_fifo.m_data <= i_ram.data;
o_ram.addr <= i_ram.addr + 1;
o_ram.count <= i_ram.count + 1;
if i_ram.count = count - 1 then
o_ram.step <= 2;
end if;
when others =>
o_ram.addr <= i_ram.addr - 2;
o_fifo.m_we <= '0';
o_ram.step <= 0;
o_fifo.step <= next_step;
end case;
end procedure fifo_push;
procedure osif_read (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_osif);
case i_osif.step is
when 0 =>
fifo_pull_word(i_osif, o_osif, result, 1, False);
when others =>
done := True;
o_osif.void <= '0';
o_osif.step <= 0;
end case;
end procedure osif_read;
procedure osif_write (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
data : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_osif);
case i_osif.step is
when 0 =>
fifo_push_word(i_osif, o_osif, data, 1);
when others =>
done := True;
o_osif.void <= '0';
o_osif.step <= 0;
end case;
end procedure osif_write;
procedure osif_call_0 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_osif);
case i_osif.step is
when 0 =>
-- wait for yield bit
o_osif.step <= 1;
when 1 =>
-- push call_id into FIFO
if i_osif.void = '1' then
fifo_push_word(i_osif, o_osif, call_id or OSIF_CMD_YIELD_MASK, 2);
else
fifo_push_word(i_osif, o_osif, call_id, 2);
end if;
when 2 =>
fifo_pull_word(i_osif, o_osif, result, 3, False);
when others =>
done := True;
o_osif.void <= '0';
o_osif.step <= 0;
end case;
end procedure osif_call_0;
procedure osif_call_1 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
arg0 : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_osif);
case i_osif.step is
when 0 =>
-- wait for yield bit
o_osif.step <= 1;
when 1 =>
-- push call_id into FIFO
if i_osif.void = '1' then
fifo_push_word(i_osif, o_osif, call_id or OSIF_CMD_YIELD_MASK, 2);
else
fifo_push_word(i_osif, o_osif, call_id, 2);
end if;
when 2 =>
-- push arg0 into FIFO
fifo_push_word(i_osif, o_osif, arg0, 3);
when 3 =>
fifo_pull_word(i_osif, o_osif, result, 4, False);
when others =>
done := True;
o_osif.void <= '0';
o_osif.step <= 0;
end case;
end procedure osif_call_1;
procedure osif_call_1_2 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
arg0 : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result1 : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result2 : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_osif);
case i_osif.step is
when 0 =>
-- wait for yield bit
o_osif.step <= 1;
when 1 =>
-- push call_id into FIFO
if i_osif.void = '1' then
fifo_push_word(i_osif, o_osif, call_id or OSIF_CMD_YIELD_MASK, 2);
else
fifo_push_word(i_osif, o_osif, call_id, 2);
end if;
when 2 =>
-- push arg0 into FIFO
fifo_push_word(i_osif, o_osif, arg0, 3);
when 3 =>
fifo_pull_word(i_osif, o_osif, result1, 4, True);
when 4 =>
fifo_pull_word(i_osif, o_osif, result2, 5, False);
when others =>
done := True;
o_osif.void <= '0';
o_osif.step <= 0;
end case;
end procedure osif_call_1_2;
procedure osif_call_2 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
arg0 : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
arg1 : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_osif);
case i_osif.step is
when 0 =>
-- wait for yield bit
o_osif.step <= 1;
when 1 =>
-- push call_id into FIFO
if i_osif.void = '1' then
fifo_push_word(i_osif, o_osif, call_id or OSIF_CMD_YIELD_MASK, 2);
else
fifo_push_word(i_osif, o_osif, call_id, 2);
end if;
when 2 =>
-- push arg0 into FIFO
fifo_push_word(i_osif, o_osif, arg0, 3);
when 3 =>
-- push arg1 into FIFO
fifo_push_word(i_osif, o_osif, arg1, 4);
when 4 =>
fifo_pull_word(i_osif, o_osif, result, 5, False);
when others =>
done := True;
o_osif.void <= '0';
o_osif.step <= 0;
end case;
end procedure osif_call_2;
-- osif functions
procedure osif_set_yield (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t
) is begin
o_osif.void <= '1';
end procedure osif_set_yield;
procedure osif_sem_post (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1(i_osif, o_osif, OSIF_CMD_SEM_POST, handle, result, done);
end procedure osif_sem_post;
procedure osif_sem_wait (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1(i_osif, o_osif, OSIF_CMD_SEM_WAIT, handle, result, done);
end procedure osif_sem_wait;
procedure osif_mutex_lock (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1(i_osif, o_osif, OSIF_CMD_MUTEX_LOCK, handle, result, done);
end procedure osif_mutex_lock;
procedure osif_mutex_unlock (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1(i_osif, o_osif, OSIF_CMD_MUTEX_UNLOCK, handle, result, done);
end procedure osif_mutex_unlock;
procedure osif_mutex_trylock (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1(i_osif, o_osif, OSIF_CMD_MUTEX_TRYLOCK, handle, result, done);
end procedure osif_mutex_trylock;
procedure osif_cond_wait (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
cond_handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
mutex_handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_2(i_osif, o_osif, OSIF_CMD_COND_WAIT, cond_handle, mutex_handle, result, done);
end procedure osif_cond_wait;
procedure osif_cond_signal (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1(i_osif, o_osif, OSIF_CMD_COND_SIGNAL, handle, result, done);
end procedure osif_cond_signal;
procedure osif_cond_broadcast (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1(i_osif, o_osif, OSIF_CMD_COND_BROADCAST, handle, result, done);
end procedure osif_cond_broadcast;
procedure osif_mbox_put (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
word : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_2(i_osif, o_osif, OSIF_CMD_MBOX_PUT, handle, word, result, done);
end procedure osif_mbox_put;
procedure osif_mbox_get (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1(i_osif, o_osif, OSIF_CMD_MBOX_GET, handle, result, done);
end procedure osif_mbox_get;
procedure osif_mbox_tryput (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
word : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_2(i_osif, o_osif, OSIF_CMD_MBOX_TRYPUT, handle, word, result, done);
end procedure osif_mbox_tryput;
procedure osif_mbox_tryget (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result1 : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result2 : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1_2(i_osif, o_osif, OSIF_CMD_MBOX_TRYGET, handle, result1, result2, done);
end procedure osif_mbox_tryget;
procedure osif_rq_receive (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
size : in std_logic_vector(31 downto 0);
addr : in std_logic_vector(31 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- not implemented yet
end procedure osif_rq_receive;
procedure osif_rq_send (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
size : in std_logic_vector(31 downto 0);
addr : in std_logic_vector(31 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- not implemented yet
end procedure osif_rq_send;
procedure osif_get_init_data (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_0(i_osif, o_osif, OSIF_CMD_THREAD_GET_INIT_DATA, result, done);
end procedure osif_get_init_data;
procedure osif_thread_exit (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t
) is begin
fifo_default(o_osif);
case i_osif.step is
when 0 =>
-- push THREAD_EXIT
fifo_push_word(i_osif, o_osif, OSIF_CMD_THREAD_EXIT, 1);
when others =>
-- never return from this loop
o_osif.step <= 2;
end case;
end procedure osif_thread_exit;
--memif functions
procedure memif_flush (
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
variable done : out boolean
) is begin
done := False;
if i_memif.m_rem = X"007F" and i_memif.m_full = '0' then
done := True;
end if;
end procedure memif_flush;
procedure memif_write_word (
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
addr : in std_logic_vector(31 downto 0);
data : in std_logic_vector(31 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_memif);
case i_memif.step is
when 0 =>
fifo_push_word(i_memif, o_memif, MEMIF_CMD_WRITE & X"000004", 1);
when 1 =>
fifo_push_word(i_memif, o_memif, addr, 2);
when 2 =>
fifo_push_word(i_memif, o_memif, data, 3);
when others =>
done := True;
o_memif.step <= 0;
end case;
end procedure memif_write_word;
procedure memif_read_word (
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
addr : in std_logic_vector(31 downto 0);
signal data : out std_logic_vector(31 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_memif);
case i_memif.step is
when 0 =>
fifo_push_word(i_memif, o_memif, MEMIF_CMD_READ & X"000004", 1);
when 1 =>
fifo_push_word(i_memif, o_memif, addr, 2);
when 2 =>
fifo_pull_word(i_memif, o_memif, data, 3, False);
when others =>
done := True;
o_memif.step <= 0;
end case;
end procedure memif_read_word;
procedure memif_write (
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
src_addr : in std_logic_vector(31 downto 0);
dst_addr : in std_logic_vector(31 downto 0);
len : in std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_memif);
case i_memif.step is
when 0 =>
o_ram.addr <= src_addr;
o_ram.remainder <= len(C_MEMIF_LENGTH_WIDTH - 1 downto 2);
o_ram.remote_addr <= dst_addr;
o_memif.step <= 1;
when 1 =>
if i_ram.remainder > C_CHUNK_SIZE then
fifo_push_word(i_memif, o_memif, MEMIF_CMD_WRITE & CONV_STD_LOGIC_VECTOR(C_CHUNK_SIZE_BYTES, C_MEMIF_LENGTH_WIDTH), 2);
else
fifo_push_word(i_memif, o_memif, MEMIF_CMD_WRITE & i_ram.remainder & "00", 2);
end if;
when 2 =>
fifo_push_word(i_memif, o_memif, i_ram.remote_addr, 3);
when 3 =>
if i_ram.remainder > C_CHUNK_SIZE then
fifo_push(i_memif, o_memif, i_ram, o_ram, CONV_STD_LOGIC_VECTOR(C_CHUNK_SIZE, C_MEMIF_LENGTH_WIDTH - 2), 4);
else
fifo_push(i_memif, o_memif, i_ram, o_ram, i_ram.remainder, 4);
end if;
when 4 =>
if i_ram.remainder > C_CHUNK_SIZE then
-- o_ram.addr is incremented by fifo_push
o_ram.remainder <= i_ram.remainder - C_CHUNK_SIZE;
o_ram.remote_addr <= i_ram.remote_addr + C_CHUNK_SIZE_BYTES;
o_ram.addr <= i_ram.addr + 1;
o_memif.step <= 1;
else
o_memif.step <= 5;
end if;
when others =>
done := True;
o_memif.step <= 0;
end case;
end procedure memif_write;
procedure memif_read (
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
src_addr : in std_logic_vector(31 downto 0);
dst_addr : in std_logic_vector(31 downto 0);
len : in std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_memif);
case i_memif.step is
when 0 =>
o_ram.addr <= dst_addr;
o_ram.remainder <= len(C_MEMIF_LENGTH_WIDTH - 1 downto 2);
o_ram.remote_addr <= src_addr;
o_memif.step <= 1;
when 1 =>
if i_ram.remainder > C_CHUNK_SIZE then
fifo_push_word(i_memif, o_memif, MEMIF_CMD_READ & CONV_STD_LOGIC_VECTOR(C_CHUNK_SIZE_BYTES, C_MEMIF_LENGTH_WIDTH), 2);
else
fifo_push_word(i_memif, o_memif, MEMIF_CMD_READ & i_ram.remainder & "00", 2);
end if;
when 2 =>
fifo_push_word(i_memif, o_memif, i_ram.remote_addr, 3);
when 3 =>
if i_ram.remainder > C_CHUNK_SIZE then
fifo_pull(i_memif, o_memif, i_ram, o_ram, CONV_STD_LOGIC_VECTOR(C_CHUNK_SIZE, C_MEMIF_LENGTH_WIDTH - 2), 4);
else
fifo_pull(i_memif, o_memif, i_ram, o_ram, i_ram.remainder, 4);
end if;
when 4 =>
if i_ram.remainder > C_CHUNK_SIZE then
-- o_ram.addr is incremented by fifo_push
o_ram.remainder <= i_ram.remainder - C_CHUNK_SIZE;
o_ram.remote_addr <= i_ram.remote_addr + C_CHUNK_SIZE_BYTES;
o_ram.addr <= i_ram.addr + 1;
o_memif.step <= 1;
else
o_memif.step <= 5;
end if;
when others =>
done := True;
o_memif.step <= 0;
end case;
end procedure memif_read;
end package body reconos_pkg;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity DS1722 is
Port( CLK_I: in std_logic;
T2: in std_logic;
RESET: in std_logic;
DATA_IN: in std_logic_vector(7 downto 0);
DATA_OUT: out std_logic_vector(7 downto 0);
ADDRESS: in std_logic_vector(7 downto 0);
START: in std_logic;
DONE: out std_logic;
TEMP_SPI: out STD_LOGIC; -- Physical interfaes
TEMP_SPO: in STD_LOGIC;
TEMP_CE: out STD_LOGIC;
TEMP_SCLK: out STD_LOGIC
);
end DS1722;
architecture DS1722_arch of DS1722 is
signal counter : std_logic_vector(7 downto 0);
signal data_latch : std_logic_vector(7 downto 0);
type BIG_STATE is ( SET_CE, LATCH_ADD, ADD_OUT_1, ADD_OUT_2,
DATA, WRITE_DATA_1, WRITE_DATA_2, READ_DATA_1, READ_DATA_2,
NEXT_TO_LAST_ONE, LAST_ONE);
signal state : BIG_STATE;
signal bit_count: INTEGER range 0 to 7;
signal Write: std_logic;
begin
-- Set up counter to sample digital themometer.
process (CLK_I, RESET)
begin
if (RESET = '1') then --asynchronous RESET active High
counter <= "00000000";
elsif (rising_edge(CLK_I)) then
if (T2 = '1') then
counter <= counter + "00000001";
end if;
end if;
end process;
DONE <= START when (state = LAST_ONE) else '0';
DATA_OUT <= data_latch;
Write <= ADDRESS(7);
-- process to convert byte commands to SPI and SPI to byte.
process (CLK_I, RESET)
begin
if (RESET='1') then --asynchronous RESET active High
state <= SET_CE;
TEMP_CE <= '0';
TEMP_SCLK <= '0';
bit_count <= 0;
elsif (rising_edge(CLK_I)) then
if (T2 = '1') then
if (counter = "11111111" and START = '1') then
case state is
when SET_CE =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
state <= LATCH_ADD;
bit_count <= 0;
when LATCH_ADD =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
state <= ADD_OUT_1;
data_latch <= ADDRESS;
when ADD_OUT_1 =>
TEMP_SCLK <= '1';
TEMP_CE <= '1';
state <= ADD_OUT_2;
TEMP_SPI <= data_latch(7);
when ADD_OUT_2 =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
data_latch <= data_latch(6 downto 0) & data_latch(7);
if bit_count < 7 then
state <= ADD_OUT_1;
bit_count <= bit_count + 1;
else
state <= DATA;
bit_count <= 0;
end if;
when DATA =>
data_latch <= DATA_IN;
TEMP_SCLK <= '0';
TEMP_CE <= '1';
if Write = '0' then
state <= READ_DATA_1;
else
state <= WRITE_DATA_1;
end if;
when WRITE_DATA_1 =>
TEMP_SCLK <= '1';
TEMP_CE <= '1';
state <= WRITE_DATA_2;
TEMP_SPI <= data_latch(7);
when WRITE_DATA_2 =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
data_latch <= data_latch(6 downto 0) & data_latch(7);
if bit_count < 7 then
state <= WRITE_DATA_1;
bit_count <= bit_count + 1;
else
state <= NEXT_TO_LAST_ONE;
bit_count <= 0;
end if;
when READ_DATA_1 =>
TEMP_SCLK <= '1';
TEMP_CE <= '1';
state <= READ_DATA_2;
when READ_DATA_2 =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
data_latch <= data_latch(6 downto 0) & TEMP_SPO;
if bit_count < 7 then
state <= READ_DATA_1;
bit_count <= bit_count + 1;
else
state <= NEXT_TO_LAST_ONE;
bit_count <= 0;
end if;
when NEXT_TO_LAST_ONE =>
TEMP_CE <= '0';
TEMP_SCLK <= '0';
state <= LAST_ONE;
when LAST_ONE =>
TEMP_CE <= '0';
TEMP_SCLK <= '0';
state <= SET_CE;
end case;
end if;
end if;
end if;
end process;
end DS1722_arch;
|
architecture RTL of ENT is begin end architecture RTL;
architecture RTL of ENT is
begin
end;
architecture RTL of ENT is
-- Some domment
begin
end;
architecture RTL of ENT is--some comment
begin
end;
|
-------------------------------------------------------------------------------
--! @file sbox.vhd
--! @brief AES S-box
--! @project VLSI Book - AES-128 Example
--! @author Michael Muehlberghuber ([email protected])
--! @company Integrated Systems Laboratory, ETH Zurich
--! @copyright Copyright (C) 2014 Integrated Systems Laboratory, ETH Zurich
--! @date 2014-06-05
--! @updated 2014-09-02
--! @platform Simulation: ModelSim; Synthesis: Synopsys
--! @standard VHDL'93/02
-------------------------------------------------------------------------------
-- Revision Control System Information:
-- File ID : $Id: sbox.vhd 10 2014-09-29 12:51:46Z u59323933 $
-- Revision : $Revision: 10 $
-- Local Date : $Date: 2014-09-29 14:51:46 +0200 (Mon, 29 Sep 2014) $
-- Modified By : $Author: u59323933 $
-------------------------------------------------------------------------------
-- Major Revisions:
-- Date Version Author Description
-- 2014-06-05 1.0 michmueh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.aes128Pkg.all;
-------------------------------------------------------------------------------
--! @brief AES S-box
--!
--! The present design implements the S-box of the Advanced Encryption Standard
--! (AES). Since the overall AES structure is based on a byte-oriented design,
--! also the S-box hast been implemented such that a single byte can be
--! substituted. This S-box was realized using a "straight-forward" approach
--! using a LUT based on an array of constants. Thereby shifting all the
--! "effort" of the actual architecture over to the synthesizer.
-------------------------------------------------------------------------------
entity sbox is
port (
--! @brief Input to the S-box.
In_DI : in Byte;
--! @brief Substituted output of the S-box.
Out_DO : out Byte);
end entity sbox;
-------------------------------------------------------------------------------
--! @brief AES S-box implementation based on a look-up table.
--!
--! AES S-box implementaion based on a look-up table (LUT), which has been
--! implemented "straight forward" by using an array of constants and thereby
--! shifting "all the work" of the actual S-box architecture over to the
--! synthesizer being used.
-------------------------------------------------------------------------------
architecture Lut of sbox is
-----------------------------------------------------------------------------
-- Type definitions
-----------------------------------------------------------------------------
subtype ByteInt is integer range 0 to 255;
type ByteArray is array (0 to 255) of ByteInt;
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant SBOX : ByteArray := (
99, 124, 119, 123, 242, 107, 111, 197, 48, 1, 103, 43, 254, 215, 171, 118,
202, 130, 201, 125, 250, 89, 71, 240, 173, 212, 162, 175, 156, 164, 114, 192,
183, 253, 147, 38, 54, 63, 247, 204, 52, 165, 229, 241, 113, 216, 49, 21,
4, 199, 35, 195, 24, 150, 5, 154, 7, 18, 128, 226, 235, 39, 178, 117,
9, 131, 44, 26, 27, 110, 90, 160, 82, 59, 214, 179, 41, 227, 47, 132,
83, 209, 0, 237, 32, 252, 177, 91, 106, 203, 190, 57, 74, 76, 88, 207,
208, 239, 170, 251, 67, 77, 51, 133, 69, 249, 2, 127, 80, 60, 159, 168,
81, 163, 64, 143, 146, 157, 56, 245, 188, 182, 218, 33, 16, 255, 243, 210,
205, 12, 19, 236, 95, 151, 68, 23, 196, 167, 126, 61, 100, 93, 25, 115,
96, 129, 79, 220, 34, 42, 144, 136, 70, 238, 184, 20, 222, 94, 11, 219,
224, 50, 58, 10, 73, 6, 36, 92, 194, 211, 172, 98, 145, 149, 228, 121,
231, 200, 55, 109, 141, 213, 78, 169, 108, 86, 244, 234, 101, 122, 174, 8,
186, 120, 37, 46, 28, 166, 180, 198, 232, 221, 116, 31, 75, 189, 139, 138,
112, 62, 181, 102, 72, 3, 246, 14, 97, 53, 87, 185, 134, 193, 29, 158,
225, 248, 152, 17, 105, 217, 142, 148, 155, 30, 135, 233, 206, 85, 40, 223,
140, 161, 137, 13, 191, 230, 66, 104, 65, 153, 45, 15, 176, 84, 187, 22);
begin -- architecture Lut
-----------------------------------------------------------------------------
-- Output assignments
-----------------------------------------------------------------------------
Out_DO <= std_logic_vector(to_unsigned(
SBOX(to_integer(unsigned(In_DI))), 8));
end architecture Lut;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
package common is
-- definition for a machine word
subtype word is std_logic_vector(31 downto 0);
subtype reg_addr_t is std_logic_vector(4 downto 0);
subtype alu_func_t is std_logic_vector(3 downto 0);
constant ALU_NONE : alu_func_t := "0000";
constant ALU_ADD : alu_func_t := "0001";
constant ALU_ADDU : alu_func_t := "0010";
constant ALU_SUB : alu_func_t := "0011";
constant ALU_SUBU : alu_func_t := "0100";
constant ALU_SLT : alu_func_t := "0101";
constant ALU_SLTU : alu_func_t := "0110";
constant ALU_AND : alu_func_t := "0111";
constant ALU_OR : alu_func_t := "1000";
constant ALU_XOR : alu_func_t := "1001";
constant ALU_SLL : alu_func_t := "1010";
constant ALU_SRA : alu_func_t := "1011";
constant ALU_SRL : alu_func_t := "1100";
subtype insn_type_t is std_logic_vector(3 downto 0);
constant OP_ILLEGAL : insn_type_t := "0000";
constant OP_LUI : insn_type_t := "0001";
constant OP_AUIPC : insn_type_t := "0010";
constant OP_JAL : insn_type_t := "0011";
constant OP_JALR : insn_type_t := "0100";
constant OP_BRANCH : insn_type_t := "0101";
constant OP_LOAD : insn_type_t := "0110";
constant OP_STORE : insn_type_t := "0111";
constant OP_ALU : insn_type_t := "1000";
constant OP_STALL : insn_type_t := "1001";
constant OP_SYSTEM : insn_type_t := "1010";
subtype branch_type_t is std_logic_vector(2 downto 0);
constant BRANCH_NONE : branch_type_t := "000";
constant BEQ : branch_type_t := "001";
constant BNE : branch_type_t := "010";
constant BLT : branch_type_t := "011";
constant BGE : branch_type_t := "100";
constant BLTU : branch_type_t := "101";
constant BGEU : branch_type_t := "110";
subtype load_type_t is std_logic_vector(2 downto 0);
constant LOAD_NONE : load_type_t := "000";
constant LB : load_type_t := "001";
constant LH : load_type_t := "010";
constant LW : load_type_t := "011";
constant LBU : load_type_t := "100";
constant LHU : load_type_t := "101";
subtype store_type_t is std_logic_vector(1 downto 0);
constant STORE_NONE : store_type_t := "00";
constant SB : store_type_t := "01";
constant SH : store_type_t := "10";
constant SW : store_type_t := "11";
subtype system_type_t is std_logic_vector(2 downto 0);
constant SYSTEM_ECALL : system_type_t := "000";
constant SYSTEM_EBREAK : system_type_t := "001";
constant SYSTEM_CSRRW : system_type_t := "010";
constant SYSTEM_CSRRS : system_type_t := "011";
constant SYSTEM_CSRRC : system_type_t := "100";
constant SYSTEM_CSRRWI : system_type_t := "101";
constant SYSTEM_CSRRSI : system_type_t := "110";
constant SYSTEM_CSRRCI : system_type_t := "111";
-- print a string with a newline
procedure println (str : in string);
procedure print (slv : in std_logic_vector);
procedure write(l : inout line; slv : in std_logic_vector);
function hstr(slv : std_logic_vector) return string;
-- instruction formats
type r_insn_t is (R_ADD, R_SLT, R_SLTU, R_AND, R_OR, R_XOR, R_SLL, R_SRL, R_SUB, R_SRA);
type i_insn_t is (I_JALR, I_LB, I_LH, I_LW, I_LBU, I_LHU, I_ADDI, I_SLTI, I_SLTIU, I_XORI, I_ORI, I_ANDI, I_SLLI, I_SRLI, I_SRAI);
type s_insn_t is (S_SB, S_SH, S_SW);
type sb_insn_t is (SB_BEQ, SB_BNE, SB_BLT, SB_BGE, SB_BLTU, SB_BGEU);
type u_insn_t is (U_LUI, U_AUIPC);
type uj_insn_t is (UJ_JAL);
-- ADDI r0, r0, r0
constant NOP : word := "00000000000000000000000000010011";
end package common;
package body common is
function hstr(slv : std_logic_vector) return string is
variable hexlen : integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- print a string with a newline
procedure println (str : in string) is
variable l : line;
begin -- procedure println
write(l, str);
writeline(output, l);
end procedure println;
procedure write(l : inout line; slv : in std_logic_vector) is
begin
for i in slv'range loop
if slv(i) = '0' then
write(l, string'("0"));
elsif slv(i) = '1' then
write(l, string'("1"));
elsif slv(i) = 'X' then
write(l, string'("X"));
elsif slv(i) = 'U' then
write(l, string'("U"));
end if;
end loop; -- i
end procedure write;
procedure print (slv : in std_logic_vector) is
variable l : line;
begin -- procedure print
write(l, slv);
writeline(output, l);
end procedure print;
end package body common;
|
library ieee;
use ieee.numeric_bit.all;
entity umul23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (45 downto 0)
);
end entity umul23;
architecture rtl of umul23 is
begin
c_o <= a_i * b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity umul23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (45 downto 0)
);
end entity umul23;
architecture rtl of umul23 is
begin
c_o <= a_i * b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity umul23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (45 downto 0)
);
end entity umul23;
architecture rtl of umul23 is
begin
c_o <= a_i * b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity umul23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (45 downto 0)
);
end entity umul23;
architecture rtl of umul23 is
begin
c_o <= a_i * b_i;
end architecture rtl;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for A_CLK_struct
--
-- Generated by wig
-- on Wed Jan 29 16:39:40 2003
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author$
-- $Id$
-- $Date$
-- $Log$
--
-- Based on Mix Architecture Template
--
-- Generator: mix_0.pl /mix/0.1, [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_arith.all;
--
--
-- Start of Generated Architecture A_CLK_struct
--
architecture A_CLK_struct of A_CLK is
--
-- Components
--
-- Generated Components
component PADS
port (
-- generated
-- NO IN PORTs : ;
-- NO OUT PORTs :
-- end of generated port
);
end component;
-- ---------
component a_fsm
port (
-- generated
alarm_button : in std_ulogic;
alarm_in_u : in std_ulogic;
clk : in std_ulogic;
key : in std_ulogic_vector(3 downto 0);
load_new_a : out std_ulogic;
load_new_c : out std_ulogic;
one_second : in std_ulogic;
reset : in std_ulogic;
shift : out std_ulogic;
show_a : out std_ulogic;
show_new_time : out std_ulogic;
time_button : in std_ulogic;
wire_high_bit : in __E_TYPE_MISMATCH(3 downto 0);
wire_high_bus : in __E_TYPE_MISMATCH(3 downto 0);
wire_low_bus : in __E_TYPE_MISMATCH(3 downto 0)
-- end of generated port
);
end component;
-- ---------
component alreg
port (
-- generated
alarm_time : out std_ulogic_vector(3 downto 0);
load_new_a : in std_ulogic;
new_alarm_time : in std_ulogic_vector(3 downto 0);
reset : in std_ulogic
-- end of generated port
);
end component;
-- ---------
component count4
port (
-- generated
clk : in std_ulogic;
current_time_ls_hr : out std_ulogic_vector(3 downto 0);
current_time_ls_min : out std_ulogic_vector(3 downto 0);
current_time_ms_hr : out std_ulogic_vector(3 downto 0);
current_time_ms_min : out std_ulogic_vector(3 downto 0);
load_new_c : in std_ulogic;
new_current_time_ls_hr : in std_ulogic_vector(3 downto 0);
new_current_time_ls_min : in std_ulogic_vector(3 downto 0);
new_current_time_ms_hr : in std_ulogic_vector(3 downto 0);
new_current_time_ms_min : in std_ulogic_vector(3 downto 0);
one_minute : in std_ulogic;
reset : in std_ulogic
-- end of generated port
);
end component;
-- ---------
component ddrv4
port (
-- generated
P_MIX_sound_alarm_test1_GI : in std_ulogic;
P_MIX_sound_alarm_test1_GO : out std_ulogic;
alarm_time_ls_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ls_min : in std_ulogic_vector(3 downto 0);
alarm_time_ms_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ms_min : in std_ulogic_vector(3 downto 0);
clk : in std_ulogic;
current_time_ls_hr : in std_ulogic_vector(3 downto 0);
current_time_ls_min : in std_ulogic_vector(3 downto 0);
current_time_ms_hr : in std_ulogic_vector(3 downto 0);
current_time_ms_min : in std_ulogic_vector(3 downto 0);
display_ls_hr : out std_ulogic_vector(6 downto 0);
display_ls_min : out std_ulogic_vector(6 downto 0);
display_ms_hr : out std_ulogic_vector(6 downto 0);
display_ms_min : out std_ulogic_vector(6 downto 0);
key_buffer_0 : in std_ulogic_vector(3 downto 0);
key_buffer_1 : in std_ulogic_vector(3 downto 0);
key_buffer_2 : in std_ulogic_vector(3 downto 0);
key_buffer_3 : in std_ulogic_vector(3 downto 0);
reset : in std_ulogic;
show_a : in std_ulogic;
show_new_time : in std_ulogic;
sound_alarm : out std_ulogic
-- end of generated port
);
end component;
-- ---------
component keypad
port (
-- generated
clk : in std_ulogic;
columns : in std_ulogic_vector(2 downto 0);
reset : in std_ulogic;
rows : out std_ulogic_vector(3 downto 0)
-- end of generated port
);
end component;
-- ---------
component keyscan
port (
-- generated
alarm_button : out std_ulogic;
clk : in std_ulogic;
columns : out std_ulogic_vector(2 downto 0);
key : out std_ulogic_vector(3 downto 0);
key_buffer_0 : out std_ulogic_vector(3 downto 0);
key_buffer_1 : out std_ulogic_vector(3 downto 0);
key_buffer_2 : out std_ulogic_vector(3 downto 0);
key_buffer_3 : out std_ulogic_vector(3 downto 0);
reset : in std_ulogic;
rows : in std_ulogic_vector(3 downto 0);
shift : in std_ulogic;
time_button : out std_ulogic
-- end of generated port
);
end component;
-- ---------
component timegen
port (
-- generated
clk : in std_ulogic;
one_minute : out std_ulogic;
one_second : out std_ulogic;
reset : in std_ulogic;
stopwatch : in std_ulogic
-- end of generated port
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signals
--
signal __LOGIC1__ : __E_TYPE_MISMATCH(3 downto 0);
signal __LOGIC0__ : __E_TYPE_MISMATCH(3 downto 0);
signal alarm_button : std_ulogic;
signal alarm_time_ls_hr : std_ulogic_vector(3 downto 0);
signal alarm_time_ls_min : std_ulogic_vector(3 downto 0);
signal alarm_time_ms_hr : std_ulogic_vector(3 downto 0);
signal alarm_time_ms_min : std_ulogic_vector(3 downto 0);
signal clk : std_ulogic;
signal columns : std_ulogic_vector(2 downto 0);
signal current_time_ls_hr : std_ulogic_vector(3 downto 0);
signal current_time_ls_min : std_ulogic_vector(3 downto 0);
signal current_time_ms_hr : std_ulogic_vector(3 downto 0);
signal current_time_ms_min : std_ulogic_vector(3 downto 0);
signal display_ls_hr : std_ulogic_vector(6 downto 0);
signal display_ls_min : std_ulogic_vector(6 downto 0);
signal display_ms_hr : std_ulogic_vector(6 downto 0);
signal display_ms_min : std_ulogic_vector(6 downto 0);
signal key : std_ulogic_vector(3 downto 0);
signal key_buffer_0 : std_ulogic_vector(3 downto 0);
signal key_buffer_1 : std_ulogic_vector(3 downto 0);
signal key_buffer_2 : std_ulogic_vector(3 downto 0);
signal key_buffer_3 : std_ulogic_vector(3 downto 0);
signal load_new_a : std_ulogic;
signal load_new_c : std_ulogic;
signal one_minute : std_ulogic;
signal one_sec_pulse : std_ulogic;
signal reset : std_ulogic;
signal rows : std_ulogic_vector(3 downto 0);
signal shift : std_ulogic;
signal show_a : std_ulogic;
signal show_new_time : std_ulogic;
signal sound_alarm : std_ulogic;
signal sound_alarm_test1 : std_ulogic;
signal stopwatch : std_ulogic;
signal time_button : std_ulogic;
--
-- End of Generated Signals
--
-- %CONSTANTS%
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
__LOGIC1__ <= '0';
__LOGIC0__ <= '0';
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for PADS
PADS: PADS PORT MAP(
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for control
control: a_fsm PORT MAP(
wire_high_bit => __LOGIC1__,
wire_high_bus => __LOGIC1__,
wire_low_bus => __LOGIC0__,
alarm_button => alarm_button,
clk => clk,
key => key,
one_second => one_sec_pulse,
reset => reset,
alarm_in_u => sound_alarm_test1,
time_button => time_button,
load_new_a => load_new_a,
load_new_c => load_new_c,
shift => shift,
show_a => show_a,
show_new_time => show_new_time
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for u0_alreg
u0_alreg: alreg PORT MAP(
new_alarm_time => key_buffer_0,
load_new_a => load_new_a,
reset => reset,
alarm_time => alarm_time_ls_min
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for u1_alreg
u1_alreg: alreg PORT MAP(
new_alarm_time => key_buffer_1,
load_new_a => load_new_a,
reset => reset,
alarm_time => alarm_time_ms_min
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for u2_alreg
u2_alreg: alreg PORT MAP(
new_alarm_time => key_buffer_2,
load_new_a => load_new_a,
reset => reset,
alarm_time => alarm_time_ls_hr
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for u3_alreg
u3_alreg: alreg PORT MAP(
new_alarm_time => key_buffer_3,
load_new_a => load_new_a,
reset => reset,
alarm_time => alarm_time_ms_hr
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for u_counter
u_counter: count4 PORT MAP(
clk => clk,
new_current_time_ls_min => key_buffer_0,
new_current_time_ms_min => key_buffer_1,
new_current_time_ls_hr => key_buffer_2,
new_current_time_ms_hr => key_buffer_3,
load_new_c => load_new_c,
one_minute => one_minute,
reset => reset,
current_time_ls_hr => current_time_ls_hr,
current_time_ls_min => current_time_ls_min,
current_time_ms_hr => current_time_ms_hr,
current_time_ms_min => current_time_ms_min
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for u_ddrv4
u_ddrv4: ddrv4 PORT MAP(
alarm_time_ls_hr => alarm_time_ls_hr,
alarm_time_ls_min => alarm_time_ls_min,
alarm_time_ms_hr => alarm_time_ms_hr,
alarm_time_ms_min => alarm_time_ms_min,
clk => clk,
current_time_ls_hr => current_time_ls_hr,
current_time_ls_min => current_time_ls_min,
current_time_ms_hr => current_time_ms_hr,
current_time_ms_min => current_time_ms_min,
key_buffer_0 => key_buffer_0,
key_buffer_1 => key_buffer_1,
key_buffer_2 => key_buffer_2,
key_buffer_3 => key_buffer_3,
reset => reset,
show_a => show_a,
show_new_time => show_new_time,
P_MIX_sound_alarm_test1_GI => sound_alarm_test1,
display_ls_hr => display_ls_hr,
display_ls_min => display_ls_min,
display_ms_hr => display_ms_hr,
display_ms_min => display_ms_min,
sound_alarm => sound_alarm,
P_MIX_sound_alarm_test1_GO => sound_alarm_test1
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for u_keypad
u_keypad: keypad PORT MAP(
clk => clk,
columns => columns,
reset => reset,
rows => rows
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for u_keyscan
u_keyscan: keyscan PORT MAP(
clk => clk,
reset => reset,
rows => rows,
shift => shift,
alarm_button => alarm_button,
columns => columns,
key => key,
key_buffer_0 => key_buffer_0,
key_buffer_1 => key_buffer_1,
key_buffer_2 => key_buffer_2,
key_buffer_3 => key_buffer_3,
time_button => time_button
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for u_timegen
u_timegen: timegen PORT MAP(
clk => clk,
reset => reset,
stopwatch => stopwatch,
one_minute => one_minute,
one_second => one_sec_pulse
);
-- End of Generated Instance Port Map
end A_CLK_struct;
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- Bibliotecas Utilizadas
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
--Declaracao da Entidade
ENTITY MaquinaDeEstadosPrincipal IS
--Generic();
PORT --Entradas e Saidas da entidade
(
CLK_50M : IN std_logic; --Clock dado pela Spartan3 em Hz
PS2_CLK1 : IN std_logic; --Sinal de clock interno do teclado
PS2_DATA1 : IN std_logic; --Sinal de dados interno do teclado
ENTRADAA : OUT std_logic_vector(19 DOWNTO 0);
ENTRADAB : OUT std_logic_vector(19 DOWNTO 0);
FINISH : OUT std_logic;
MDDRESET : OUT std_logic
);
END MaquinaDeEstadosPrincipal;
--Declaracao da arquitetura da entidade
ARCHITECTURE ArcMaquinaDeEstadosPrincipal OF MaquinaDeEstadosPrincipal IS
--Declaracao de tipos
TYPE recebeNumero IS
(
PrimeiroDigA, SegundoDigA, TerceiroDigA, QuartoDigA, QuintoDigA, EsperandoSinal,
PrimeiroDigB, SegundoDigB, TerceiroDigB, QuartoDigB, QuintoDigB, EsperandoEnter, Enviar
);
--Declaracao dos sinais utilizados
signal ascii_start, prev_ascii_start : std_logic ; --Sinal para mapeamento de componente
signal getting_number : recebeNumero := PrimeiroDigA;
signal internal_ascii_code : std_logic_vector(6 downto 0); --Sinal para mapeamento de componente
signal internal_number : integer; --Sinal para mapeamento de componente
signal operandoB : std_logic_vector(7 downto 0); --Operador
signal operandoA : std_logic_vector(7 downto 0); --Operador
--Componente que traduz de codigo entendido pelo teclado para codigo ascii
begin
--Mapeamento dos componentes
ps2_keyboard_to_ascii: entity work.ps2_keyboard_to_ascii port map
(CLK_50M, PS2_CLK1,PS2_DATA1, ascii_start, internal_ascii_code);
--Processo onde os operandos sao obtidos do teclado
Carregar_Dados: process(CLK_50M, ascii_start, internal_ascii_code)
variable entradaA_aux : std_logic_vector(7 downto 0) := (others => '0');
variable entradaA_obtida : std_logic_vector(19 downto 0) := (others => '0');
variable entradaB_aux : std_logic_vector(7 downto 0) := (others => '0');
variable entradaB_obtida : std_logic_vector(19 downto 0) := (others => '0');
variable quocienteCalculado : std_logic_vector(7 downto 0) := "00000000";
variable restoCalculado : std_logic_vector(7 downto 0) := "00000000";
-- variable numBin : std_logic_vector(7 downto 0) := "00000000";
variable finishAuxiliar : std_logic;
begin
if (CLK_50M'event and CLK_50M='1') then
prev_ascii_start <= ascii_start;
case getting_number is
when PrimeiroDigA =>
if (prev_ascii_start = '0' and ascii_start = '1') then
if (internal_ascii_code = "0001101") then --enter
getting_number <= PrimeiroDigA;
elsif (internal_ascii_code = "0011011") then
getting_number <= PrimeiroDigA;
else
finishAuxiliar := '0';
entradaA_aux := "0" & internal_ascii_code;
entradaA_obtida(3 downto 0) := entradaA_aux(3 downto 0);
-- numBin := entradaA_obtida;
getting_number <= SegundoDigA;
end if;
else
getting_number <= PrimeiroDigA;
end if;
when SegundoDigA =>
if (prev_ascii_start = '0' and ascii_start = '1') then
if (internal_ascii_code = "0001101") then --enter
getting_number <= EsperandoSinal;
else
entradaA_aux := "0" & internal_ascii_code;
entradaA_obtida(7 downto 4) := entradaA_aux(3 downto 0);
-- numBin := entradaA_obtida;
getting_number <= TerceiroDigA;
end if;
else
getting_number <= SegundoDigA;
end if;
when TerceiroDigA =>
if (prev_ascii_start = '0' and ascii_start = '1') then
if (internal_ascii_code = "0001101") then
getting_number <= EsperandoSinal;
else
entradaA_aux := "0" & internal_ascii_code;
entradaA_obtida(11 downto 8) := entradaA_aux(3 downto 0);
-- numBin := entradaA_obtida;
getting_number <= QuartoDigA;
end if;
else
getting_number <= TerceiroDigA;
end if;
when QuartoDigA =>
if (prev_ascii_start = '0' and ascii_start = '1') then
if (internal_ascii_code = "0001101") then --enter
getting_number <= EsperandoSinal;
else
entradaA_aux := "0" & internal_ascii_code;
entradaA_obtida(15 downto 12) := entradaA_aux(3 downto 0);
-- numBin := entradaA_obtida;
getting_number <= QuintoDigA;
end if;
else
getting_number <= QuartoDigA;
end if;
when QuintoDigA =>
if (prev_ascii_start = '0' and ascii_start = '1') then
if (internal_ascii_code = "0001101") then
getting_number <= EsperandoSinal;
else
entradaA_aux := "0" & internal_ascii_code;
entradaA_obtida(19 downto 16) := entradaA_aux(3 downto 0);
-- numBin := entradaA_obtida;
getting_number <= EsperandoSinal;
end if;
else
getting_number <= QuintoDigA;
end if;
when EsperandoSinal =>
if (prev_ascii_start = '0' and ascii_start = '1') then
if (internal_ascii_code = "0001101") then
getting_number <= PrimeiroDigB;
else
getting_number <= EsperandoSinal;
end if;
else
getting_number <= EsperandoSinal;
end if;
when PrimeiroDigB =>
if (prev_ascii_start= '0' and ascii_start = '1') then
if (internal_ascii_code = "0001101") then
getting_number <= PrimeiroDigB;
else
entradaB_aux := "0" & internal_ascii_code;
entradaB_obtida(3 downto 0) := entradaB_aux(3 downto 0);
-- numBin := entradaB_obtida;
getting_number <= SegundoDigB;
end if;
else
getting_number <= PrimeiroDigB;
end if;
when SegundoDigB =>
if (prev_ascii_start = '0' and ascii_start = '1') then
if (internal_ascii_code = "0001101") then
getting_number <= Enviar;
entradaB <= entradaB_obtida;
entradaA <= entradaA_obtida;
else
entradaB_aux := "0" & internal_ascii_code;
entradaB_obtida(7 downto 4) := entradaB_aux(3 downto 0);
-- numBin := entradaB_obtida;
getting_number <= TerceiroDigB;
end if;
else
getting_number <= SegundoDigB;
end if;
when TerceiroDigB =>
if (prev_ascii_start = '0' and ascii_start = '1') then
if (internal_ascii_code = "0001101") then
getting_number <= Enviar;
entradaB <= entradaB_obtida;
entradaA <= entradaA_obtida;
else
entradaB_aux := "0" & internal_ascii_code;
entradaB_obtida(11 downto 8) := entradaB_aux(3 downto 0);
-- numBin := entradaB_obtida;
getting_number <= QuartoDigB;
end if;
else
getting_number <= TerceiroDigB;
end if;
when QuartoDigB =>
if (prev_ascii_start = '0' and ascii_start = '1') then
if (internal_ascii_code = "0001101") then
getting_number <= Enviar;
entradaB <= entradaB_obtida;
entradaA <= entradaA_obtida;
else
entradaB_aux := "0" & internal_ascii_code;
entradaB_obtida(15 downto 12) := entradaB_aux(3 downto 0);
-- numBin := entradaB_obtida;
getting_number <= QuintoDigB;
end if;
else
getting_number <= QuartoDigB;
end if;
when QuintoDigB =>
if (prev_ascii_start = '0' and ascii_start = '1') then
if (internal_ascii_code = "0001101") then
getting_number <= Enviar;
entradaB <= entradaB_obtida;
entradaA <= entradaA_obtida;
else
entradaB_aux := "0" & internal_ascii_code;
entradaB_obtida(19 downto 16) := entradaB_aux(3 downto 0);
-- numBin := entradaB_obtida;
getting_number <= EsperandoEnter;
end if;
else
getting_number <= QuintoDigB;
end if;
when EsperandoEnter =>
if (prev_ascii_start = '0' and ascii_start = '1') then
if (internal_ascii_code = "0001101") then
getting_number <= Enviar;
else
getting_number <= EsperandoEnter;
end if;
else
getting_number <= esperandoEnter;
end if;
when Enviar =>
if (prev_ascii_start = '0' and ascii_start = '1') then
if (internal_ascii_code = "0011011") then
getting_number <= PrimeiroDigA;
MDDreset <= '1';
FINISH <='0';
else
getting_number <= enviar;
MDDreset<='0';
end if;
else
getting_number <= enviar;
entradaB <= entradaB_obtida;
entradaA <= entradaA_obtida;
finishAuxiliar := '1';
MDDreset <= '0';
end if;
end case;
end if;
FINISH <= finishAuxiliar;
end process Carregar_Dados;
end ArcMaquinaDeEstadosPrincipal; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity binary_to_bcd is
port(
binary: in std_logic_vector(7 downto 0);
bcd: out std_logic_vector(7 downto 0)
);
end entity;
architecture struct of binary_to_bcd is
component n_bit_adder
generic(N: integer);
port(
a: in std_logic_vector(N - 1 downto 0);
b: in std_logic_vector(N - 1 downto 0);
cin: in std_logic;
res: out std_logic_vector(N - 1 downto 0);
cout: out std_logic
);
end component;
signal binary_s_1: std_logic_vector(7 downto 0);
signal binary_s_2: std_logic_vector(7 downto 0);
signal binary_s_3: std_logic_vector(7 downto 0);
signal binary_s_4: std_logic_vector(7 downto 0);
signal binary_s_5: std_logic_vector(7 downto 0);
signal binary_s_6: std_logic_vector(7 downto 0);
signal binary_s_7: std_logic_vector(7 downto 0);
signal binary_s_8: std_logic_vector(7 downto 0);
signal binary_s_9: std_logic_vector(7 downto 0);
signal fully_fake_signal: std_logic_vector(8 downto 0);
begin
subtractor_1: n_bit_adder generic map(8)
port map(binary, "00000101", '1', binary_s_1, fully_fake_signal(0));
subtractor_2: n_bit_adder generic map(8)
port map(binary_s_1, "00000101", '1', binary_s_2, fully_fake_signal(1));
subtractor_3: n_bit_adder generic map(8)
port map(binary_s_2, "00000101", '1', binary_s_3, fully_fake_signal(2));
subtractor_4: n_bit_adder generic map(8)
port map(binary_s_3, "00000101", '1', binary_s_4, fully_fake_signal(3));
subtractor_5: n_bit_adder generic map(8)
port map(binary_s_4, "00000101", '1', binary_s_5, fully_fake_signal(4));
subtractor_6: n_bit_adder generic map(8)
port map(binary_s_5, "00000101", '1', binary_s_6, fully_fake_signal(5));
subtractor_7: n_bit_adder generic map(8)
port map(binary_s_6, "00000101", '1', binary_s_7, fully_fake_signal(6));
subtractor_8: n_bit_adder generic map(8)
port map(binary_s_7, "00000101", '1', binary_s_8, fully_fake_signal(7));
subtractor_9: n_bit_adder generic map(8)
port map(binary_s_8, "00000101", '1', binary_s_9, fully_fake_signal(8));
bcd <= binary when to_integer(unsigned(binary)) < 10 else
binary_s_1 when to_integer(unsigned(binary)) < 20 else
binary_s_2 when to_integer(unsigned(binary)) < 30 else
binary_s_3 when to_integer(unsigned(binary)) < 40 else
binary_s_4 when to_integer(unsigned(binary)) < 50 else
binary_s_5 when to_integer(unsigned(binary)) < 60 else
binary_s_6 when to_integer(unsigned(binary)) < 70 else
binary_s_7 when to_integer(unsigned(binary)) < 80 else
binary_s_8 when to_integer(unsigned(binary)) < 90 else
binary_s_9 when to_integer(unsigned(binary)) < 100 else
"XXXXXXXX";
end struct;
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
PACKAGE RS232_test IS
-------------------------------------------------------------------------------
-- Procedure for sending one byte over the RS232 serial input
-------------------------------------------------------------------------------
procedure Transmit (
signal TX : out std_logic; -- serial line
constant DATA : in std_logic_vector(7 downto 0)); -- byte to be sent
END RS232_test;
PACKAGE BODY RS232_test IS
-----------------------------------------------------------------------------
-- Procedure for sending one byte over the RS232 serial input
-----------------------------------------------------------------------------
procedure Transmit (
signal TX : out std_logic; -- serial output
constant DATA : in std_logic_vector(7 downto 0)) is
begin
TX <= '0';
wait for 8680.6 ns; -- about to send byte
for i in 0 to 7 loop
TX <= DATA(i);
wait for 8680.6 ns;
end loop; -- i
TX <= '1';
wait for 8680.6 ns;
TX <= '1';
end Transmit;
END RS232_test;
|
--Helpful resource:
--ftp://www.cs.uregina.ca/pub/class/301/multiplexer/lecture.html
library IEEE;
use IEEE.std_logic_1164.all;
entity mux8_bit is
port(
bit0 : in std_logic := '-';
bit1 : in std_logic := '-';
bit2 : in std_logic := '-';
bit3 : in std_logic := '-';
bit4 : in std_logic := '-';
bit5 : in std_logic := '-';
bit6 : in std_logic := '-';
bit7 : in std_logic := '-';
S : in std_logic_vector(2 downto 0);
R : out std_logic
);
end mux8_bit;
architecture Behavioural of mux8_bit is
begin
with S select
R <= bit0 when "000",
bit1 when "001",
bit2 when "010",
bit3 when "011",
bit4 when "100",
bit5 when "101",
bit6 when "110",
bit7 when others;
end Behavioural;
|
-- niosii_system_usb_0_avalon_usb_slave_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_usb_0_avalon_usb_slave_translator is
generic (
AV_ADDRESS_W : integer := 2;
AV_DATA_W : integer := 16;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 1;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 5;
AV_WRITE_WAIT_CYCLES : integer := 5;
AV_SETUP_WAIT_CYCLES : integer := 5;
AV_DATA_HOLD_CYCLES : integer := 5
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(1 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(15 downto 0); -- .writedata
av_chipselect : out std_logic; -- .chipselect
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_byteenable : out std_logic_vector(0 downto 0);
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_waitrequest : in std_logic := '0';
av_writebyteenable : out std_logic_vector(0 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity niosii_system_usb_0_avalon_usb_slave_translator;
architecture rtl of niosii_system_usb_0_avalon_usb_slave_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(1 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_chipselect : out std_logic; -- chipselect
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
usb_0_avalon_usb_slave_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_chipselect => av_chipselect, -- .chipselect
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of niosii_system_usb_0_avalon_usb_slave_translator
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_972 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_972;
architecture augh of cmp_972 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
ne <= not(tmp);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_972 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_972;
architecture augh of cmp_972 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
ne <= not(tmp);
end architecture;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:axi_nic:1.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY sys_axi_nic_0_0 IS
PORT (
RX_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
RX_VALID : IN STD_LOGIC;
RX_READY : OUT STD_LOGIC;
TX_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TX_VALID : OUT STD_LOGIC;
TX_READY : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC
);
END sys_axi_nic_0_0;
ARCHITECTURE sys_axi_nic_0_0_arch OF sys_axi_nic_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sys_axi_nic_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT nic_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER;
C_S00_AXI_ADDR_WIDTH : INTEGER;
USE_1K_NOT_4K_FIFO_DEPTH : BOOLEAN
);
PORT (
RX_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
RX_VALID : IN STD_LOGIC;
RX_READY : OUT STD_LOGIC;
TX_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TX_VALID : OUT STD_LOGIC;
TX_READY : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC
);
END COMPONENT nic_v1_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF RX_DATA: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TDATA";
ATTRIBUTE X_INTERFACE_INFO OF RX_VALID: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TVALID";
ATTRIBUTE X_INTERFACE_INFO OF RX_READY: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TREADY";
ATTRIBUTE X_INTERFACE_INFO OF TX_DATA: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TDATA";
ATTRIBUTE X_INTERFACE_INFO OF TX_VALID: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TVALID";
ATTRIBUTE X_INTERFACE_INFO OF TX_READY: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RREADY";
BEGIN
U0 : nic_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 5,
USE_1K_NOT_4K_FIFO_DEPTH => false
)
PORT MAP (
RX_DATA => RX_DATA,
RX_VALID => RX_VALID,
RX_READY => RX_READY,
TX_DATA => TX_DATA,
TX_VALID => TX_VALID,
TX_READY => TX_READY,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready
);
END sys_axi_nic_0_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
entity VOICE is
port
(
start:in std_logic;
clk:in std_logic;
clk_voice:out std_logic;
n_wr,n_cs,n_rd,n_rst:out std_logic:='1';
n_int:in std_logic:='0';
add_en:out std_logic:='0';
data_voice:inout std_logic_vector(7 downto 0);
voice_result:out std_logic_vector(7 downto 0):=x"00";
reco_rqu:in std_logic:='0';
reco_fin:out std_logic:='0'
);
end entity;
architecture voicex of VOICE is
component voice_clock is
port
(
inclk0:in std_logic;
c0:out std_logic;
c1:out std_logic
);
end component;
component voice_rom_init is
port
(
clock:in std_logic;
address:in std_logic_vector(5 downto 0);
q:out std_logic_vector(15 downto 0)
);
end component;
component list is
port
(
clock:in std_logic;
address:in std_logic_vector(8 downto 0);
q:out std_logic_vector(7 downto 0)
);
end component;
component VOICE_DELAY is
port
(
clk:in std_logic;
start:in std_logic:='0';
total:in std_logic_vector(7 downto 0);
finish:out std_logic:='1'
);
end component;
-------------------时钟、40MHz---------------------
signal clk_self,clk_out:std_logic;
-----------------------复位------------------------
signal reset:std_logic:='0';
--------------------初始化ROM----------------------
signal rom_init_addr:std_logic_vector(5 downto 0);
signal rom_init_data:std_logic_vector(15 downto 0);
---------------------列表ROM-----------------------
signal rom_list_addr:std_logic_vector(8 downto 0);
signal rom_list_data:std_logic_vector(7 downto 0);
-----------------------延时------------------------
signal delay_start,delay_finish:std_logic:='0';
signal delay_total:std_logic_vector(7 downto 0);
----------------------配置状态----------------------
signal init_done,list_done,all_wait,all_done,all_done_last:std_logic:='0';
----------------------识别状态----------------------
signal reco_allow,reco_allow_last,reco_start:std_logic:='0';
signal reco_rqu_last:std_logic:='0';
signal n_int_last:std_logic:='1';
signal add_en_s:std_logic:='1';
begin
clk_voice<=clk_self;
add_en<=add_en_s;
VOICE_CLOCKX:voice_clock port map(inclk0=>clk,c0=>clk_self,c1=>clk_out);
VOICE_ROM_INITX:voice_rom_init port map(clock=>clk_out,address=>rom_init_addr,q=>rom_init_data);
VOICE_ROM_LIST:list port map(clock=>clk_out,address=>rom_list_addr,q=>rom_list_data);
VOICE_DLLAYX:voice_delay port map(clk=>clk_self,start=>delay_start,finish=>delay_finish,total=>delay_total);
process(clk_self,reset)
variable con_reset:integer range 0 to 127:=0;
variable con_init_start:integer range 0 to 2047:=0;
variable con:integer range 0 to 5:=0;
variable con_total:integer range 0 to 26:=0;
variable con_type:integer range 0 to 31:=0;
variable con_init_fin_start:integer range 0 to 3:=0;
begin
if clk_self'event and clk_self='1' then
--------------------复位-----------------------
if con_reset=127 then
reset<='1';
end if;
if reset='1' then
con_reset:=0;
reset<='0';
reco_fin<='0';
init_done<='0';
list_done<='0';
all_wait<='0';
all_done<='0';
reco_allow<='0';
rom_init_addr<="000000";
rom_list_addr<="000000000";
con_init_start:=0;
end if;
---------------------初始化----------------------
if start='1' then
if con_init_start=2047 then
con_init_start:=2047;
else
con_init_start:=con_init_start+1;
con:=0;
con_type:=0;
con_total:=0;
con_init_fin_start:=0;
end if;
end if;
if con_init_start=500 then
n_rst<='0';
elsif con_init_start=1000 then
n_rst<='1';
elsif con_init_start=1500 then
n_cs<='0';
elsif con_init_start=2000 then
n_cs<='1';
delay_start<='1';
delay_total<=x"5F";
end if;
--------------------初始化---------------------
if con_init_start=2047 and init_done='0' and delay_finish='1' then
if con=5 then
con:=0;
elsif con=0 then
if con_total=26 then
init_done<='1';
con:=0;
con_type:=0;
con_total:=0;
else
con:=con+1;
end if;
else
con:=con+1;
end if;
-------------------------------------------------------
if con_total=0 or con_total=2 then
if con=1 then
delay_start<='0';
if con_type=0 then
add_en_s<='1';
data_voice<=x"06";
else
add_en_s<='0';
data_voice<="ZZZZZZZZ";
end if;
elsif con=2 then
n_cs<='0';
elsif con=3 then
if con_type=0 then
n_wr<='0';
else
n_rd<='0';
end if;
elsif con=4 then
if add_en_s='0' then
delay_total<=x"0A";
delay_start<='1';
end if;
if con_type=0 then
n_wr<='1';
else
n_rd<='1';
end if;
elsif con=5 then
n_cs<='1';
if con_type=1 then
con_type:=0;
con_total:=con_total+1;
else
con_type:=con_type+1;
end if;
end if;
-------------------------------------------------------
else
if con=1 then
delay_start<='0';
if con_type=0 then
add_en_s<='1';
data_voice<=rom_init_data(15 downto 8);
else
add_en_s<='0';
data_voice<=rom_init_data(7 downto 0);
rom_init_addr<=rom_init_addr+1;
end if;
elsif con=2 then
n_cs<='0';
elsif con=3 then
n_wr<='0';
elsif con=4 then
n_wr<='1';
delay_total<=x"0A";
delay_start<='1';
elsif con=5 then
n_cs<='1';
if con_type=1 then
con_type:=0;
con_total:=con_total+1;
else
con_type:=con_type+1;
end if;
end if;
end if;
end if;
-------------------待识别列表写入----------------
if init_done='1' and list_done='0' and delay_finish='1' then
if con=0 then
delay_start<='0';
con:=con+1;
elsif con=1 then
if con_type=0 then
add_en_s<='1';
data_voice<=x"B2";
con:=con+1;
elsif con_type=10 then
add_en_s<='0';
data_voice<="ZZZZZZZZ";
con:=con+1;
elsif con_type=1 then
if rom_list_data=x"FF" then
con_type:=20;
--list_done<='1';
delay_total<=x"5F";
delay_start<='1';
con:=0;
--con_type:=0;
else
add_en_s<='1';
data_voice<=x"C1";
con:=con+1;
con_type:=2;
end if;
elsif con_type=20 then
add_en_s<='1';
data_voice<=x"BF";
con:=con+1;
elsif con_type=21 then
add_en_s<='0';
data_voice<="ZZZZZZZZ";
con:=con+1;
elsif con_type=2 then
add_en_s<='0';
data_voice<=rom_list_data;
con:=con+1;
con_type:=12;
elsif con_type=12 then
add_en_s<='1';
data_voice<=x"C3";
con:=con+1;
con_type:=13;
elsif con_type=13 then
add_en_s<='0';
data_voice<=x"00";
con:=con+1;
con_type:=14;
elsif con_type=14 then
add_en_s<='1';
data_voice<=x"08";
con:=con+1;
con_type:=15;
elsif con_type=15 then
add_en_s<='0';
data_voice<=x"04";
con:=con+1;
con_type:=16;
elsif con_type=16 then
add_en_s<='1';
data_voice<=x"08";
con:=con+1;
con_type:=17;
elsif con_type=17 then
add_en_s<='0';
data_voice<=x"00";
con:=con+1;
con_type:=3;
elsif con_type=3 then
add_en_s<='1';
data_voice<=x"05";
con:=con+1;
con_type:=11;
rom_list_addr<=rom_list_addr+1;
elsif con_type=4 then
add_en_s<='1';
data_voice<=x"B9";
con:=con+1;
con_type:=5;
rom_list_addr<=rom_list_addr+1;
elsif con_type=5 then
add_en_s<='0';
data_voice<=rom_list_data;
con:=con+1;
con_type:=6;
elsif con_type=6 then
add_en_s<='1';
data_voice<=x"B2";
con:=con+1;
con_type:=7;
elsif con_type=7 then
add_en_s<='0';
data_voice<=x"FF";
con:=con+1;
con_type:=8;
elsif con_type=8 then
add_en_s<='1';
data_voice<=x"37";
con:=con+1;
con_type:=9;
elsif con_type=9 then
add_en_s<='0';
data_voice<=x"04";
con:=con+1;
con_type:=0;
rom_list_addr<=rom_list_addr+1;
elsif con_type=11 then
if rom_list_data=x"FF" then
con_type:=4;
con:=0;
else
add_en_s<='0';
data_voice<=rom_list_data;
rom_list_addr<=rom_list_addr+1;
con:=con+1;
end if;
end if;
elsif con=2 then
n_cs<='0';
con:=con+1;
elsif con=3 then
con:=con+1;
if con_type=10 or con_type=21 then
n_rd<='0';
else
n_wr<='0';
end if;
elsif con=4 then
con:=con+1;
if add_en_s='0' and con_type/=11 then
delay_total<=x"01";
delay_start<='1';
end if;
if con_type=21 or con_type=10 then
n_rd<='1';
else
n_wr<='1';
end if;
elsif con=5 then
n_cs<='1';
con:=0;
if con_type=10 then
if data_voice=x"21" then
con_type:=1;
else
delay_total<=x"0A";
delay_start<='1';
con_type:=0;
con_reset:=con_reset+1;
end if;
elsif con_type=0 then
con_type:=10;
elsif con_type=20 then
con_type:=21;
elsif con_type=21 then
if data_voice=x"31" then
con_type:=0;
list_done<='1';
con:=0;
con_type:=0;
else
reset<='1';
end if;
end if;
end if;
end if;
-------------------------识别准备------------------------
reco_rqu_last<=reco_rqu;
if reco_rqu_last='0' and reco_rqu='1' then
reco_start<='1';
end if;
if list_done='1' and all_wait='0' and reco_start='1' and delay_finish='1' then
if con_init_fin_start=3 then
con_init_fin_start:=3;
else
rom_init_addr<="100000";
con_init_fin_start:=con_init_fin_start+1;
end if;
if con_init_fin_start=3 then
if con=5 then
con:=0;
elsif con=0 then
if con_total=5 then
all_wait<='1';
reco_start<='0';
con:=0;
con_type:=0;
con_total:=0;
con_reset:=0;
elsif con_total=0 then
con:=con+1;
else
con:=con+1;
end if;
else
con:=con+1;
end if;
if con=0 then
delay_start<='0';
elsif con=1 then
if con_type=0 then
add_en_s<='1';
data_voice<=rom_init_data(15 downto 8);
else
add_en_s<='0';
data_voice<=rom_init_data(7 downto 0);
rom_init_addr<=rom_init_addr+1;
end if;
elsif con=2 then
n_cs<='0';
elsif con=3 then
n_wr<='0';
elsif con=4 then
n_wr<='1';
if add_en_s='0' then
delay_total<=x"01";
delay_start<='1';
end if;
elsif con=5 then
n_cs<='1';
if con_type=1 then
con_type:=0;
con_total:=con_total+1;
else
con_type:=con_type+1;
end if;
end if;
end if;
end if;
---------------------------识别--------------------------
if all_wait='1' and delay_finish='1' then
if con=5 then
con:=0;
elsif con=0 then
if con_total=7 then
con_total:=0;
con_type:=0;
con:=0;
all_wait<='0';
all_done<='1';
else
con:=con+1;
end if;
else
con:=con+1;
end if;
if con=0 then
delay_start<='0';
elsif con=1 then
if con_type=0 then
add_en_s<='1';
if con_total=0 then
data_voice<=x"B2";
elsif con_total=3 then
data_voice<=x"BF";
else
data_voice<=rom_init_data(15 downto 8);
end if;
else
add_en_s<='0';
if con_total=0 or con_total=3 then
data_voice<="ZZZZZZZZ";
else
data_voice<=rom_init_data(7 downto 0);
rom_init_addr<=rom_init_addr+1;
end if;
end if;
elsif con=2 then
n_cs<='0';
elsif con=3 then
if (con_total=0 or con_total=3) and con_type=1 then
n_rd<='0';
else
n_wr<='0';
end if;
elsif con=4 then
if (con_total=0 or con_total=3) and con_type=1 then
n_rd<='1';
else
n_wr<='1';
end if;
if add_en_s='0' then
if con_total=2 then
delay_total<=x"05";
else
delay_total<=x"01";
end if;
delay_start<='1';
end if;
elsif con=5 then
n_cs<='1';
if con_total=0 and con_type=1 then
if data_voice=x"21" then
con_total:=con_total+1;
else
con_reset:=con_reset+1;
con_total:=0;
end if;
elsif con_total=3 and con_type=1 then
if data_voice=x"31" then
con_total:=con_total+1;
else
reco_fin<='1';
data_voice<=x"FF";
reset<='1';
end if;
elsif con_type=1 then
con_total:=con_total+1;
end if;
if con_type=1 then
con_type:=0;
else
con_type:=con_type+1;
end if;
end if;
end if;
-----------------------识别结果---------------------
if all_done='1' and delay_finish='1' then
n_int_last<=n_int;
if n_int_last='1' and n_int='0' then
reco_allow<='1';
end if;
end if;
reco_allow_last<=reco_allow;
if reco_allow_last='1' and reco_allow='0' then
reco_fin<='0';
end if;
if reco_allow='1' then
if con=5 then
con:=0;
else
con:=con+1;
end if;
if con=0 then
if con_total=6 then
reco_allow<='0';
all_done<='0';
con:=0;
con_type:=0;
con_total:=0;
end if;
elsif con=1 then
if con_type=0 then
add_en_s<='1';
if con_total=0 then
data_voice<=x"29";
elsif con_total=1 then
data_voice<=x"02";
elsif con_total=2 then
data_voice<=x"BF";
elsif con_total=3 then
data_voice<=x"2B";
elsif con_total=4 then
data_voice<=x"BA";
elsif con_total=5 then
data_voice<=x"C5";
end if;
else
add_en_s<='0';
if con_total<2 then
data_voice<=x"00";
else
data_voice<="ZZZZZZZZ";
end if;
end if;
elsif con=2 then
n_cs<='0';
elsif con=3 then
if con_total>1 and con_type=1 then
n_rd<='0';
else
n_wr<='0';
end if;
elsif con=4 then
if con_total>1 and con_type=1 then
n_rd<='1';
else
n_wr<='1';
end if;
elsif con=5 then
n_cs<='1';
if con_type=1 then
con_type:=0;
if con_total<2 then
con_total:=con_total+1;
elsif con_total=2 and data_voice=x"35" then
con_total:=con_total+1;
elsif con_total=3 and data_voice(3)='0' then
con_total:=con_total+1;
elsif con_total=4 then
if data_voice>x"00" and data_voice<x"05" then
con_total:=con_total+1;
else
voice_result<=x"FD";
reco_allow<='0';
reco_fin<='1';
all_done<='0';
con:=0;
con_type:=0;
con_total:=0;
end if;
elsif con_total=5 then
reco_fin<='1';
voice_result<=data_voice;
con_total:=con_total+1;
else
reset<='1';
end if;
else
con_type:=con_type+1;
end if;
end if;
end if;
end if;
end process;
end voicex;
|
-- top.vhd
-- this VHDL design instatiates a Qsys system with a Nios II processor that has access to the many diffent peripherals
-- on the BeMicro Max 10 board.
--
-- There are many different software examples included in the software folder.
library ieee;
use ieee.std_logic_1164.all;
-- The following is the entity declaration section of this VHDL block.
-- An entity declaraction defines the pins of the block and is analogous to
-- a schematic symbol.
--
-- Since the bemicro_m10_nios2_top entity is the top level entity of our FPGA design,
-- the ports listed below are the pins of our MAX 10 FPGA device.
--
entity bemicro_m10_nios2_top is
port
(
SYS_CLK : in std_logic := 'X'; -- clk
USER_CLK : in std_logic;
PB : in std_logic_vector(4 downto 1) := (others => 'X'); -- export
USER_LED : out std_logic_vector(8 downto 1); -- export
SDRAM_A : out std_logic_vector(12 downto 0);
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_CASN : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSN : out std_logic;
SDRAM_DQ : inout std_logic_vector(15 downto 0);
SDRAM_DQM : out std_logic_vector(1 downto 0);
SDRAM_RASN : out std_logic;
SDRAM_WEN : out std_logic;
SDRAM_CLK : out std_logic;
ADXL362_MISO : in std_logic;
ADXL362_MOSI : out std_logic;
ADXL362_SCLK : out std_logic;
ADXL362_CSn : out std_logic;
ADXL362_INT1 : in std_logic;
ADXL362_INT2 : in std_logic;
ADT7420_SCL : inout std_logic;
ADT7420_SDA : inout std_logic;
SFLASH_DCLK : out std_logic;
SFLASH_CSn : out std_logic;
SFLASH_DATA : in std_logic; -- input data from spi flash
SFLASH_ASDI : out std_logic; -- this feeds out to the data input of the spi flash
AD5681R_LDACn : out std_logic;
AD5681R_RSTn : out std_logic;
AD5681R_SCL : out std_logic;
AD5681R_SDA : out std_logic;
AD5681R_SYNCn : out std_logic
);
end entity;
-- The following is the architecture section of the bemicro_m10_nios2_top entity declared
-- above. The architecture section is the actual design of the VHDL block and is analogous
-- to the contents of a schematic sheet.
--
-- The architecture of bemicro_m10_nios2_top contains primarily one large block, which is
-- the nios2_bemicro_system block generated by QSys. This ports of this block are mapped
-- to the pins of the device. There is a small amount of additional logic to tie off others
-- signals and to generate resets.
--
architecture rtl of bemicro_m10_nios2_top is
-- VHDL component declaration for the QSys sytem. This is copy/pasted from the generated
-- file nios2_bemicro_system/nios2_bemicro_system_inst.vhd
component nios2_bemicro_system is
port (
reset_reset_n : in std_logic := 'X'; -- reset_n
clk_clk : in std_logic := 'X'; -- clk
led_pio_external_export : out std_logic_vector(7 downto 0); -- export
button_pio_external_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
i2c_temp_sense_scl_pad_io : inout std_logic := 'X'; -- scl_pad_io
i2c_temp_sense_sda_pad_io : inout std_logic := 'X'; -- sda_pad_io
sdram_addr : out std_logic_vector(11 downto 0); -- addr
sdram_ba : out std_logic_vector(1 downto 0); -- ba
sdram_cas_n : out std_logic; -- cas_n
sdram_cke : out std_logic; -- cke
sdram_cs_n : out std_logic; -- cs_n
sdram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
sdram_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_ras_n : out std_logic; -- ras_n
sdram_we_n : out std_logic; -- we_n
serial_flash_dclk : out std_logic; -- dclk
serial_flash_sce : out std_logic; -- sce
serial_flash_sdo : out std_logic; -- sdo
serial_flash_data0 : in std_logic := 'X'; -- data0
sdram_pll_areset_conduit_export : in std_logic := 'X'; -- export
sdram_pll_locked_conduit_export : out std_logic; -- export
sdram_pll_phasedone_conduit_export : out std_logic; -- export
adc_pll_areset_conduit_export : in std_logic := 'X'; -- export
adc_pll_phasedone_conduit_export : out std_logic; -- export
spi_accelerometer_MISO : in std_logic := 'X'; -- MISO
spi_accelerometer_MOSI : out std_logic; -- MOSI
spi_accelerometer_SCLK : out std_logic; -- SCLK
spi_accelerometer_SS_n : out std_logic; -- SS_n
spi_dac_MISO : in std_logic := 'X'; -- MISO
spi_dac_MOSI : out std_logic; -- MOSI
spi_dac_SCLK : out std_logic; -- SCLK
spi_dac_SS_n : out std_logic; -- SS_n
sdram_pll_80shift_clk : out std_logic -- clk
);
end component nios2_bemicro_system;
signal async_reset_n : std_logic;
signal reset_n : std_logic;
signal pll_areset : std_logic;
signal reset_sync_n : std_logic_vector(1 downto 0);
signal led_export : std_logic_vector(8 downto 1);
begin
-- push_buttons are active low
-- reset the Nios when PB4 and PB1 are pushed simultaneously
async_reset_n <= '0' when PB(4) = '0' and PB(1) = '0' else '1';
--reset synchronizer
-- this logic will asynchronously reset the whole system, yet
-- will synchronously release reset
process(SYS_CLK)
begin
if(async_reset_n = '0') then
reset_sync_n <= "00"; -- clear 2-bit reset sync register
else
if rising_edge(SYS_CLK) then
reset_sync_n(0) <= '1';
reset_sync_n(1) <= reset_sync_n(0);
end if;
end if;
end process;
reset_n <= reset_sync_n(1);
pll_areset <= not reset_sync_n(1);
-- VHDL port mapping of the QSys system's ports to signals in the top level. A port mapping
-- template is found in the generated file nios2_bemicro_system/nios2_bemicro_system_inst.vhd
u0 : component nios2_bemicro_system
port map (
clk_clk => SYS_CLK,
reset_reset_n => reset_n,
button_pio_external_export => PB,
led_pio_external_export => led_export,
i2c_temp_sense_scl_pad_io => ADT7420_SCL,
i2c_temp_sense_sda_pad_io => ADT7420_SDA,
sdram_addr => SDRAM_A(11 downto 0),
sdram_ba => SDRAM_BA,
sdram_cas_n => SDRAM_CASN,
sdram_cke => SDRAM_CKE,
sdram_cs_n => SDRAM_CSN,
sdram_dq => SDRAM_DQ,
sdram_dqm => SDRAM_DQM,
sdram_ras_n => SDRAM_RASN,
sdram_we_n => SDRAM_WEN,
sdram_pll_80shift_clk => SDRAM_CLK,
sdram_pll_areset_conduit_export => pll_areset,
sdram_pll_locked_conduit_export => open,
sdram_pll_phasedone_conduit_export => open,
adc_pll_areset_conduit_export => pll_areset,
adc_pll_phasedone_conduit_export => open,
serial_flash_dclk => SFLASH_DCLK,
serial_flash_sce => SFLASH_CSn,
serial_flash_sdo => SFLASH_ASDI,
serial_flash_data0 => SFLASH_DATA,
spi_accelerometer_MISO => ADXL362_MISO,
spi_accelerometer_MOSI => ADXL362_MOSI,
spi_accelerometer_SCLK => ADXL362_SCLK,
spi_accelerometer_SS_n => ADXL362_CSn,
spi_dac_MISO => '1',
spi_dac_MOSI => AD5681R_SDA,
spi_dac_SCLK => AD5681R_SCL,
spi_dac_SS_n => AD5681R_SYNCn
);
SDRAM_a(12) <= '0'; --extra address bit used for larger SDRAM devices
--the leds are active low, need to invert
USER_LED(8 downto 1) <= not led_export(8 downto 1);
AD5681R_LDACn <= '1'; -- LDAC is used to transfer data from the DAC register to the output generating vout. this can also be done in sw
AD5681R_RSTn <= reset_n;
end rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity tb_prescaler is
end tb_prescaler;
-- Beim Testen den Prescaler anpassen
architecture sim of tb_prescaler is
component prescaler
port (
clk50 : in std_logic;
reset_n : in std_logic;
clk1 : out std_logic);
end component;
signal s_clk50 : std_logic := '0';
signal s_reset_n : std_logic := '0';
signal s_clk1 : std_logic := '0';
begin
i_prescaler : prescaler
port map (
clk50 => s_clk50,
reset_n => s_reset_n,
clk1 => s_clk1);
s_clk50 <= not s_clk50 after 1 ps;
p_test : process
begin
s_reset_n <= '0';
wait for 20 ps;
s_reset_n <= '1';
wait for 40000 ps;
end process;
end sim; |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Components declaration of the types_pll package.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Target names declaration
library techmap;
use techmap.gencomp.all;
--! @brief Declaration of 'virtual' PLL components
package types_pll is
--! @brief Declaration of the "virtual" PLL component.
--! @details This module instantiates the certain PLL implementation
--! depending generic argument.
--! @param[in] tech Generic PLL implementation selector
--! @param[in] i_reset Reset value. Active high.
--! @param[in] i_int_clkrf ADC source select:
--! 0 = External ADC clock (Real RF front-end)
--! 1 = Disable external ADC/enable internal ADC simulation.
--! @param[in] i_clkp Differential clock input positive
--! @param[in] i_clkn Differential clock input negative
--! @param[in] i_clk_adc External ADC clock
--! @param[out] o_clk_bus System Bus clock 100MHz/40MHz (Virtex6/Spartan6)
--! @param[out] o_clk_adc ADC simulation clock = 26MHz (default).
--! @param[out] o_locked PLL locked status.
component SysPLL_tech is
generic(
tech : integer range 0 to NTECH := 0;
tmode_always_ena : boolean := false
);
port (
i_reset : in std_logic;
i_clkp : in std_logic;
i_clkn : in std_logic;
o_clk_bus : out std_logic;
o_clk_50 : out std_logic;
o_clk_50_quad : out std_logic;
o_locked : out std_logic);
end component;
--! @name Technology specific PLL components.
--! @param[in] CLK_IN1_P Differential clock input positive
--! @param[in] CLK_IN1_N Differential clock input negative
--! @param[out] CLK_OUT1 PLL clock output.
--! @param[out] CLK_OUT2 ADC clock simulation.
--! @param[in] RESET Reset value. Active high.
--! @param[out] LOCKED PLL locked status.
--! @{
--! @brief Declaration of the PLL component used for RTL simulation.
component SysPLL_inferred is
port (
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic );
end component;
--! @brief Declaration of the PLL component used for ML605 board.
--! @details This module was generated by Xilinx CoreGen for Virtex6 FPGA.
component SysPLL_v6 is
port (
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic );
end component;
--! @brief Declaration of the PLL component used for KC705 board.
--! @details This module was generated by Xilinx CoreGen for Kintex7 FPGA.
component SysPLL_k7 is
port (
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic );
end component;
component SysPLL_a7
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic;
clk_out2 : out std_logic;
clk_out3 : out std_logic;
clk_out4 : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic
);
end component;
--! @brief Declaration of the PLL component used Mikron 180nm ASIC.
--! @details This module is made as the netlist generated by fabric.
component SysPLL_micron180 is
port (
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic );
end component;
--! @brief Virtual Clock phase rotator.
--! @param[in] tech Technology selector.
--! @param[in] freq Clock frequency in KHz.
--! @param[in] i_rst Reset signal. Active HIGH.
component clkp90_tech is
generic (
tech : integer range 0 to NTECH := 0;
freq : integer := 125000
);
port (
i_rst : in std_logic;
i_clk : in std_logic;
o_clk : out std_logic;
o_clkp90 : out std_logic;
o_clk2x : out std_logic;
o_lock : out std_logic
);
end component;
--! @}
end;
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Components declaration of the types_pll package.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Target names declaration
library techmap;
use techmap.gencomp.all;
--! @brief Declaration of 'virtual' PLL components
package types_pll is
--! @brief Declaration of the "virtual" PLL component.
--! @details This module instantiates the certain PLL implementation
--! depending generic argument.
--! @param[in] tech Generic PLL implementation selector
--! @param[in] i_reset Reset value. Active high.
--! @param[in] i_int_clkrf ADC source select:
--! 0 = External ADC clock (Real RF front-end)
--! 1 = Disable external ADC/enable internal ADC simulation.
--! @param[in] i_clkp Differential clock input positive
--! @param[in] i_clkn Differential clock input negative
--! @param[in] i_clk_adc External ADC clock
--! @param[out] o_clk_bus System Bus clock 100MHz/40MHz (Virtex6/Spartan6)
--! @param[out] o_clk_adc ADC simulation clock = 26MHz (default).
--! @param[out] o_locked PLL locked status.
component SysPLL_tech is
generic(
tech : integer range 0 to NTECH := 0;
tmode_always_ena : boolean := false
);
port (
i_reset : in std_logic;
i_clkp : in std_logic;
i_clkn : in std_logic;
o_clk_bus : out std_logic;
o_clk_50 : out std_logic;
o_clk_50_quad : out std_logic;
o_locked : out std_logic);
end component;
--! @name Technology specific PLL components.
--! @param[in] CLK_IN1_P Differential clock input positive
--! @param[in] CLK_IN1_N Differential clock input negative
--! @param[out] CLK_OUT1 PLL clock output.
--! @param[out] CLK_OUT2 ADC clock simulation.
--! @param[in] RESET Reset value. Active high.
--! @param[out] LOCKED PLL locked status.
--! @{
--! @brief Declaration of the PLL component used for RTL simulation.
component SysPLL_inferred is
port (
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic );
end component;
--! @brief Declaration of the PLL component used for ML605 board.
--! @details This module was generated by Xilinx CoreGen for Virtex6 FPGA.
component SysPLL_v6 is
port (
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic );
end component;
--! @brief Declaration of the PLL component used for KC705 board.
--! @details This module was generated by Xilinx CoreGen for Kintex7 FPGA.
component SysPLL_k7 is
port (
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic );
end component;
component SysPLL_a7
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic;
clk_out2 : out std_logic;
clk_out3 : out std_logic;
clk_out4 : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic
);
end component;
--! @brief Declaration of the PLL component used Mikron 180nm ASIC.
--! @details This module is made as the netlist generated by fabric.
component SysPLL_micron180 is
port (
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic );
end component;
--! @brief Virtual Clock phase rotator.
--! @param[in] tech Technology selector.
--! @param[in] freq Clock frequency in KHz.
--! @param[in] i_rst Reset signal. Active HIGH.
component clkp90_tech is
generic (
tech : integer range 0 to NTECH := 0;
freq : integer := 125000
);
port (
i_rst : in std_logic;
i_clk : in std_logic;
o_clk : out std_logic;
o_clkp90 : out std_logic;
o_clk2x : out std_logic;
o_lock : out std_logic
);
end component;
--! @}
end;
|
-- Test extended identifiers
entity bar is
end entity;
architecture foo of bar is
signal \foo bar\ : integer;
signal \a\\b\ : integer;
signal \Thing!!! \ : integer;
signal \name\ : integer;
signal name : integer;
signal \foo.bar.baz\ : integer;
signal \hello\ : integer;
begin
\foo.bar.baz\ <= \hello\;
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:49:02 09/11/2011
-- Design Name:
-- Module Name: picas - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity picas is
Port ( sw1 : in STD_LOGIC_VECTOR (2 downto 0);
sw2 : in STD_LOGIC_VECTOR (2 downto 0);
sw3 : in STD_LOGIC_VECTOR (2 downto 0);
nu1 : in STD_LOGIC_VECTOR (2 downto 0);
nu2 : in STD_LOGIC_VECTOR (2 downto 0);
nu3 : in STD_LOGIC_VECTOR (2 downto 0);
picas : out std_logic_vector (2 downto 0));
end picas;
architecture Behavioral of picas is
begin
picas(0) <= (((sw1(0) xnor nu2(0))and(sw1(1) xnor nu2(1))and(sw1(2) xnor nu2(2))) or
((sw1(0) xnor nu3(0))and(sw1(1) xnor nu3(1))and(sw1(2) xnor nu3(2))));
picas(1) <= (((sw2(0) xnor nu1(0))and(sw2(1) xnor nu1(1))and(sw2(2) xnor nu1(2))) or
((sw2(0) xnor nu3(0))and(sw2(1) xnor nu3(1))and(sw2(2) xnor nu3(2))));
picas(2) <= (((sw3(0) xnor nu2(0))and(sw3(1) xnor nu2(1))and(sw3(2) xnor nu2(2))) or
((sw3(0) xnor nu1(0))and(sw3(1) xnor nu1(1))and(sw3(2) xnor nu1(2))));
end Behavioral;
|
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 55616)
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`protect begin_protected
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`protect end_protected
|
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 11.11.2013 13:56:52
-- Design Name:
-- Module Name: aeg_design_0_switch_port
-- Description: This module describes one port for the Ethernet switch
-- It consists of:
-- - The rx_path: the logic processing the received data before
-- sending to the fabric
-- - The tx_path: the logic receiving data from the fabric and
-- handling the transmission of frames
-- - The TEMAC receives/sends frames
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity aeg_design_0_switch_port is
Generic (
RECEIVER_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer;
FABRIC_DATA_WIDTH : integer;
NR_PORTS : integer;
FRAME_LENGTH_WIDTH : integer;
NR_IQ_FIFOS : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
GMII_DATA_WIDTH : integer;
TX_IFG_DELAY_WIDTH : integer;
PAUSE_VAL_WIDTH : integer;
PORT_ID : integer
);
Port (
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
latency : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
debug0_sig : out std_logic;
debug1_sig : out std_logic;
debug2_sig : out std_logic;
debug3_sig : out std_logic;
-- Receiver Interface
-----------------------------------------
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
-- RX Switch Fabric Intrface
------------------------------------------
rx_path_clock : in std_logic;
rx_path_resetn : in std_logic;
rx_out_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
rx_out_valid : out std_logic;
rx_out_last : out std_logic;
rx_out_ports_req : out std_logic_vector(NR_PORTS-1 downto 0);
rx_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
rx_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
rx_out_length : out std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
rx_out_ports_gnt : in std_logic_vector(NR_PORTS-1 downto 0);
-- Transmitter Interface
--------------------------------------------
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(TX_IFG_DELAY_WIDTH-1 downto 0);
-- TX Switch Fabric Intrface
---------------------------------------------
tx_path_clock : in std_logic;
tx_path_resetn : in std_logic;
tx_in_data : in std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
tx_in_valid : in std_logic;
tx_in_length : in std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
tx_in_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
tx_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
tx_in_req : in std_logic;
tx_in_accept_frame : out std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(PAUSE_VAL_WIDTH-1 downto 0);
-- GMII Interface
-------------------
gmii_txd : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
phy_interrupt_n : in std_logic;
-- MDIO Interface
-------------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic
);
end aeg_design_0_switch_port;
architecture rtl of aeg_design_0_switch_port is
component tri_mode_ethernet_mac_block
Generic (
RECEIVER_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer;
GMII_DATA_WIDTH : integer;
TX_IFG_DELAY_WIDTH : integer;
PAUSE_VAL_WIDTH : integer
);
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
-- Receiver Statistics Interface
-----------------------------------------
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
-- mac to rxpath interface
------------------------------------------
mac_out_clock : in std_logic;
mac_out_resetn : in std_logic;
mac_out_data : out std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
mac_out_valid : out std_logic;
mac_out_last : out std_logic;
mac_out_error : out std_logic;
-- Transmitter Statistics Interface
--------------------------------------------
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(TX_IFG_DELAY_WIDTH-1 downto 0);
-- txpath to mac interface
---------------------------------------------
mac_in_clock : in std_logic;
mac_in_resetn : in std_logic;
mac_in_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
mac_in_valid : in std_logic;
mac_in_ready : out std_logic;
mac_in_last : in std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(PAUSE_VAL_WIDTH-1 downto 0);
-- GMII Interface
-------------------
gmii_txd : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
-- MDIO Interface
-------------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
mac_interrupt : out std_logic
);
end component;
component config_mac_phy_sm
port (
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
phy_interrupt_n : in std_logic;
mac_interrupt : in std_logic;
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
serial_command : in std_logic;
serial_response : out std_logic;
debug0_sig : out std_logic;
debug1_sig : out std_logic;
debug2_sig : out std_logic;
debug3_sig : out std_logic;
s_axi_awaddr : out std_logic_vector(11 downto 0) := (others => '0');
s_axi_awvalid : out std_logic := '0';
s_axi_awready : in std_logic;
s_axi_wdata : out std_logic_vector(31 downto 0) := (others => '0');
s_axi_wvalid : out std_logic := '0';
s_axi_wready : in std_logic;
s_axi_bresp : in std_logic_vector(1 downto 0);
s_axi_bvalid : in std_logic;
s_axi_bready : out std_logic;
s_axi_araddr : out std_logic_vector(11 downto 0) := (others => '0');
s_axi_arvalid : out std_logic := '0';
s_axi_arready : in std_logic;
s_axi_rdata : in std_logic_vector(31 downto 0);
s_axi_rresp : in std_logic_vector(1 downto 0);
s_axi_rvalid : in std_logic;
s_axi_rready : out std_logic := '0'
);
end component;
component switch_port_rx_path is
Generic (
RECEIVER_DATA_WIDTH : integer;
FABRIC_DATA_WIDTH : integer;
NR_PORTS : integer;
FRAME_LENGTH_WIDTH : integer;
NR_IQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
PORT_ID : integer
);
Port (
rx_path_clock : in std_logic;
rx_path_resetn : in std_logic;
-- mac to rx_path interface
rx_in_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
rx_in_valid : in std_logic;
rx_in_last : in std_logic;
rx_in_error : in std_logic;
rx_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- rx_path interface to fabric
rx_out_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
rx_out_valid : out std_logic;
rx_out_last : out std_logic;
rx_out_ports_req : out std_logic_vector(NR_PORTS-1 downto 0);
rx_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
rx_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
rx_out_length : out std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
rx_out_ports_gnt : in std_logic_vector(NR_PORTS-1 downto 0)
);
end component;
component switch_port_tx_path is
Generic (
FABRIC_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer;
FRAME_LENGTH_WIDTH : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer
);
Port (
tx_path_clock : in std_logic;
tx_path_resetn : in std_logic;
-- tx_path interface to fabric
tx_in_data : in std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
tx_in_valid : in std_logic;
tx_in_length : in std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
tx_in_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
tx_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
tx_in_req : in std_logic;
tx_in_accept_frame : out std_logic;
-- timestamp
tx_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
tx_out_latency : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- tx_path interface to mac
tx_out_data : out std_logic_vector(TRANSMITTER_DATA_WIDTH-1 downto 0);
tx_out_valid : out std_logic;
tx_out_ready : in std_logic;
tx_out_last : out std_logic
);
end component;
signal mac2rx_data_sig : std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
signal mac2rx_valid_sig : std_logic;
signal mac2rx_last_sig : std_logic;
signal mac2rx_error_sig : std_logic;
signal tx2mac_data_sig : std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
signal tx2mac_valid_sig : std_logic;
signal tx2mac_ready_sig : std_logic;
signal tx2mac_last_sig : std_logic;
signal s_axi_awaddr : std_logic_vector(11 downto 0) := (others => '0');
signal s_axi_awvalid : std_logic := '0';
signal s_axi_awready : std_logic := '0';
signal s_axi_wdata : std_logic_vector(31 downto 0) := (others => '0');
signal s_axi_wvalid : std_logic := '0';
signal s_axi_wready : std_logic := '0';
signal s_axi_bresp : std_logic_vector(1 downto 0) := (others => '0');
signal s_axi_bvalid : std_logic := '0';
signal s_axi_bready : std_logic := '0';
signal s_axi_araddr : std_logic_vector(11 downto 0) := (others => '0');
signal s_axi_arvalid : std_logic := '0';
signal s_axi_arready : std_logic := '0';
signal s_axi_rdata : std_logic_vector(31 downto 0) := (others => '0');
signal s_axi_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal s_axi_rvalid : std_logic := '0';
signal s_axi_rready : std_logic := '0';
signal mac_interrupt : std_logic := '0';
-- attribute mark_debug : string;
-- attribute mark_debug of mac2rx_data_sig : signal is "true";
-- attribute mark_debug of mac2rx_valid_sig : signal is "true";
-- attribute mark_debug of mac2rx_last_sig : signal is "true";
-- attribute mark_debug of mac2rx_error_sig : signal is "true";
begin
------------------------------------------------------------------------------
-- Instantiate the TRIMAC core FIFO Block wrapper
------------------------------------------------------------------------------
trimac_block : tri_mode_ethernet_mac_block
Generic map (
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
TRANSMITTER_DATA_WIDTH => TRANSMITTER_DATA_WIDTH,
GMII_DATA_WIDTH => GMII_DATA_WIDTH,
TX_IFG_DELAY_WIDTH => TX_IFG_DELAY_WIDTH,
PAUSE_VAL_WIDTH => PAUSE_VAL_WIDTH
)
port map (
gtx_clk => gtx_clk,
-- asynchronous reset
glbl_rstn => glbl_rstn,
rx_axi_rstn => rx_axi_rstn,
tx_axi_rstn => tx_axi_rstn,
-- Reference clock for IDELAYCTRL's
refclk => refclk,
-- Receiver Statistics Interface
-----------------------------------------
rx_mac_aclk => rx_mac_aclk,
rx_reset => rx_reset,
-- Receiver => AXI-S Interface
------------------------------------------
mac_out_clock => rx_path_clock,
mac_out_resetn => rx_path_resetn,
mac_out_data => mac2rx_data_sig,
mac_out_valid => mac2rx_valid_sig,
mac_out_last => mac2rx_last_sig,
mac_out_error => mac2rx_error_sig,
-- Transmitter Statistics Interface
--------------------------------------------
tx_mac_aclk => tx_mac_aclk,
tx_reset => tx_reset,
tx_ifg_delay => tx_ifg_delay,
-- Transmitter => AXI-S Interface
---------------------------------------------
mac_in_clock => tx_path_clock,
mac_in_resetn => tx_path_resetn,
mac_in_data => tx2mac_data_sig,
mac_in_valid => tx2mac_valid_sig,
mac_in_ready => tx2mac_ready_sig,
mac_in_last => tx2mac_last_sig,
-- MAC Control Interface
--------------------------
pause_req => pause_req,
pause_val => pause_val,
-- GMII Interface
-------------------
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
mii_tx_clk => mii_tx_clk,
-- MDIO Interface
-------------------
mdio => mdio,
mdc => mdc,
-- AXI-Lite Interface
-----------------
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
mac_interrupt => mac_interrupt
);
config_mac_phy : config_mac_phy_sm
port map(
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
phy_interrupt_n => phy_interrupt_n,
mac_interrupt => mac_interrupt,
mac_speed => "01",
update_speed => '0',
serial_command => '0',
serial_response => open,
debug0_sig => debug0_sig,
debug1_sig => debug1_sig,
debug2_sig => debug2_sig,
debug3_sig => debug3_sig,
-- AXI-Lite Interface
-----------
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
rx_path : switch_port_rx_path
Generic map(
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
FABRIC_DATA_WIDTH => FABRIC_DATA_WIDTH,
NR_PORTS => NR_PORTS,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
NR_IQ_FIFOS => NR_IQ_FIFOS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH,
PORT_ID => PORT_ID
)
Port map(
rx_path_clock => rx_path_clock,
rx_path_resetn => rx_path_resetn,
-- mac to rx_path interface
rx_in_data => mac2rx_data_sig,
rx_in_valid => mac2rx_valid_sig,
rx_in_last => mac2rx_last_sig,
rx_in_error => mac2rx_error_sig,
rx_in_timestamp_cnt => timestamp_cnt,
-- rx_path interface to fabric
rx_out_data => rx_out_data,
rx_out_valid => rx_out_valid,
rx_out_last => rx_out_last,
rx_out_ports_req => rx_out_ports_req,
rx_out_prio => rx_out_prio,
rx_out_timestamp => rx_out_timestamp,
rx_out_length => rx_out_length,
rx_out_ports_gnt => rx_out_ports_gnt
);
tx_path : switch_port_tx_path
Generic map(
FABRIC_DATA_WIDTH => FABRIC_DATA_WIDTH,
TRANSMITTER_DATA_WIDTH => TRANSMITTER_DATA_WIDTH,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
NR_OQ_FIFOS => NR_OQ_FIFOS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH
)
Port map(
tx_path_clock => tx_path_clock,
tx_path_resetn => tx_path_resetn,
-- tx_path interface to fabric
tx_in_data => tx_in_data,
tx_in_valid => tx_in_valid,
tx_in_length => tx_in_length,
tx_in_prio => tx_in_prio,
tx_in_timestamp => tx_in_timestamp,
tx_in_req => tx_in_req,
tx_in_accept_frame => tx_in_accept_frame,
-- timestamp
tx_in_timestamp_cnt => timestamp_cnt,
tx_out_latency => latency,
-- tx_path interface to mac
tx_out_data => tx2mac_data_sig,
tx_out_valid => tx2mac_valid_sig,
tx_out_ready => tx2mac_ready_sig,
tx_out_last => tx2mac_last_sig
);
end rtl;
|
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 11.11.2013 13:56:52
-- Design Name:
-- Module Name: aeg_design_0_switch_port
-- Description: This module describes one port for the Ethernet switch
-- It consists of:
-- - The rx_path: the logic processing the received data before
-- sending to the fabric
-- - The tx_path: the logic receiving data from the fabric and
-- handling the transmission of frames
-- - The TEMAC receives/sends frames
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity aeg_design_0_switch_port is
Generic (
RECEIVER_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer;
FABRIC_DATA_WIDTH : integer;
NR_PORTS : integer;
FRAME_LENGTH_WIDTH : integer;
NR_IQ_FIFOS : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
GMII_DATA_WIDTH : integer;
TX_IFG_DELAY_WIDTH : integer;
PAUSE_VAL_WIDTH : integer;
PORT_ID : integer
);
Port (
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
latency : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
debug0_sig : out std_logic;
debug1_sig : out std_logic;
debug2_sig : out std_logic;
debug3_sig : out std_logic;
-- Receiver Interface
-----------------------------------------
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
-- RX Switch Fabric Intrface
------------------------------------------
rx_path_clock : in std_logic;
rx_path_resetn : in std_logic;
rx_out_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
rx_out_valid : out std_logic;
rx_out_last : out std_logic;
rx_out_ports_req : out std_logic_vector(NR_PORTS-1 downto 0);
rx_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
rx_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
rx_out_length : out std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
rx_out_ports_gnt : in std_logic_vector(NR_PORTS-1 downto 0);
-- Transmitter Interface
--------------------------------------------
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(TX_IFG_DELAY_WIDTH-1 downto 0);
-- TX Switch Fabric Intrface
---------------------------------------------
tx_path_clock : in std_logic;
tx_path_resetn : in std_logic;
tx_in_data : in std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
tx_in_valid : in std_logic;
tx_in_length : in std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
tx_in_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
tx_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
tx_in_req : in std_logic;
tx_in_accept_frame : out std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(PAUSE_VAL_WIDTH-1 downto 0);
-- GMII Interface
-------------------
gmii_txd : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
phy_interrupt_n : in std_logic;
-- MDIO Interface
-------------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic
);
end aeg_design_0_switch_port;
architecture rtl of aeg_design_0_switch_port is
component tri_mode_ethernet_mac_block
Generic (
RECEIVER_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer;
GMII_DATA_WIDTH : integer;
TX_IFG_DELAY_WIDTH : integer;
PAUSE_VAL_WIDTH : integer
);
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
-- Receiver Statistics Interface
-----------------------------------------
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
-- mac to rxpath interface
------------------------------------------
mac_out_clock : in std_logic;
mac_out_resetn : in std_logic;
mac_out_data : out std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
mac_out_valid : out std_logic;
mac_out_last : out std_logic;
mac_out_error : out std_logic;
-- Transmitter Statistics Interface
--------------------------------------------
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(TX_IFG_DELAY_WIDTH-1 downto 0);
-- txpath to mac interface
---------------------------------------------
mac_in_clock : in std_logic;
mac_in_resetn : in std_logic;
mac_in_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
mac_in_valid : in std_logic;
mac_in_ready : out std_logic;
mac_in_last : in std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(PAUSE_VAL_WIDTH-1 downto 0);
-- GMII Interface
-------------------
gmii_txd : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
-- MDIO Interface
-------------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
mac_interrupt : out std_logic
);
end component;
component config_mac_phy_sm
port (
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
phy_interrupt_n : in std_logic;
mac_interrupt : in std_logic;
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
serial_command : in std_logic;
serial_response : out std_logic;
debug0_sig : out std_logic;
debug1_sig : out std_logic;
debug2_sig : out std_logic;
debug3_sig : out std_logic;
s_axi_awaddr : out std_logic_vector(11 downto 0) := (others => '0');
s_axi_awvalid : out std_logic := '0';
s_axi_awready : in std_logic;
s_axi_wdata : out std_logic_vector(31 downto 0) := (others => '0');
s_axi_wvalid : out std_logic := '0';
s_axi_wready : in std_logic;
s_axi_bresp : in std_logic_vector(1 downto 0);
s_axi_bvalid : in std_logic;
s_axi_bready : out std_logic;
s_axi_araddr : out std_logic_vector(11 downto 0) := (others => '0');
s_axi_arvalid : out std_logic := '0';
s_axi_arready : in std_logic;
s_axi_rdata : in std_logic_vector(31 downto 0);
s_axi_rresp : in std_logic_vector(1 downto 0);
s_axi_rvalid : in std_logic;
s_axi_rready : out std_logic := '0'
);
end component;
component switch_port_rx_path is
Generic (
RECEIVER_DATA_WIDTH : integer;
FABRIC_DATA_WIDTH : integer;
NR_PORTS : integer;
FRAME_LENGTH_WIDTH : integer;
NR_IQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
PORT_ID : integer
);
Port (
rx_path_clock : in std_logic;
rx_path_resetn : in std_logic;
-- mac to rx_path interface
rx_in_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
rx_in_valid : in std_logic;
rx_in_last : in std_logic;
rx_in_error : in std_logic;
rx_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- rx_path interface to fabric
rx_out_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
rx_out_valid : out std_logic;
rx_out_last : out std_logic;
rx_out_ports_req : out std_logic_vector(NR_PORTS-1 downto 0);
rx_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
rx_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
rx_out_length : out std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
rx_out_ports_gnt : in std_logic_vector(NR_PORTS-1 downto 0)
);
end component;
component switch_port_tx_path is
Generic (
FABRIC_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer;
FRAME_LENGTH_WIDTH : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer
);
Port (
tx_path_clock : in std_logic;
tx_path_resetn : in std_logic;
-- tx_path interface to fabric
tx_in_data : in std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
tx_in_valid : in std_logic;
tx_in_length : in std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
tx_in_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
tx_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
tx_in_req : in std_logic;
tx_in_accept_frame : out std_logic;
-- timestamp
tx_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
tx_out_latency : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- tx_path interface to mac
tx_out_data : out std_logic_vector(TRANSMITTER_DATA_WIDTH-1 downto 0);
tx_out_valid : out std_logic;
tx_out_ready : in std_logic;
tx_out_last : out std_logic
);
end component;
signal mac2rx_data_sig : std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
signal mac2rx_valid_sig : std_logic;
signal mac2rx_last_sig : std_logic;
signal mac2rx_error_sig : std_logic;
signal tx2mac_data_sig : std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
signal tx2mac_valid_sig : std_logic;
signal tx2mac_ready_sig : std_logic;
signal tx2mac_last_sig : std_logic;
signal s_axi_awaddr : std_logic_vector(11 downto 0) := (others => '0');
signal s_axi_awvalid : std_logic := '0';
signal s_axi_awready : std_logic := '0';
signal s_axi_wdata : std_logic_vector(31 downto 0) := (others => '0');
signal s_axi_wvalid : std_logic := '0';
signal s_axi_wready : std_logic := '0';
signal s_axi_bresp : std_logic_vector(1 downto 0) := (others => '0');
signal s_axi_bvalid : std_logic := '0';
signal s_axi_bready : std_logic := '0';
signal s_axi_araddr : std_logic_vector(11 downto 0) := (others => '0');
signal s_axi_arvalid : std_logic := '0';
signal s_axi_arready : std_logic := '0';
signal s_axi_rdata : std_logic_vector(31 downto 0) := (others => '0');
signal s_axi_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal s_axi_rvalid : std_logic := '0';
signal s_axi_rready : std_logic := '0';
signal mac_interrupt : std_logic := '0';
-- attribute mark_debug : string;
-- attribute mark_debug of mac2rx_data_sig : signal is "true";
-- attribute mark_debug of mac2rx_valid_sig : signal is "true";
-- attribute mark_debug of mac2rx_last_sig : signal is "true";
-- attribute mark_debug of mac2rx_error_sig : signal is "true";
begin
------------------------------------------------------------------------------
-- Instantiate the TRIMAC core FIFO Block wrapper
------------------------------------------------------------------------------
trimac_block : tri_mode_ethernet_mac_block
Generic map (
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
TRANSMITTER_DATA_WIDTH => TRANSMITTER_DATA_WIDTH,
GMII_DATA_WIDTH => GMII_DATA_WIDTH,
TX_IFG_DELAY_WIDTH => TX_IFG_DELAY_WIDTH,
PAUSE_VAL_WIDTH => PAUSE_VAL_WIDTH
)
port map (
gtx_clk => gtx_clk,
-- asynchronous reset
glbl_rstn => glbl_rstn,
rx_axi_rstn => rx_axi_rstn,
tx_axi_rstn => tx_axi_rstn,
-- Reference clock for IDELAYCTRL's
refclk => refclk,
-- Receiver Statistics Interface
-----------------------------------------
rx_mac_aclk => rx_mac_aclk,
rx_reset => rx_reset,
-- Receiver => AXI-S Interface
------------------------------------------
mac_out_clock => rx_path_clock,
mac_out_resetn => rx_path_resetn,
mac_out_data => mac2rx_data_sig,
mac_out_valid => mac2rx_valid_sig,
mac_out_last => mac2rx_last_sig,
mac_out_error => mac2rx_error_sig,
-- Transmitter Statistics Interface
--------------------------------------------
tx_mac_aclk => tx_mac_aclk,
tx_reset => tx_reset,
tx_ifg_delay => tx_ifg_delay,
-- Transmitter => AXI-S Interface
---------------------------------------------
mac_in_clock => tx_path_clock,
mac_in_resetn => tx_path_resetn,
mac_in_data => tx2mac_data_sig,
mac_in_valid => tx2mac_valid_sig,
mac_in_ready => tx2mac_ready_sig,
mac_in_last => tx2mac_last_sig,
-- MAC Control Interface
--------------------------
pause_req => pause_req,
pause_val => pause_val,
-- GMII Interface
-------------------
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
mii_tx_clk => mii_tx_clk,
-- MDIO Interface
-------------------
mdio => mdio,
mdc => mdc,
-- AXI-Lite Interface
-----------------
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
mac_interrupt => mac_interrupt
);
config_mac_phy : config_mac_phy_sm
port map(
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
phy_interrupt_n => phy_interrupt_n,
mac_interrupt => mac_interrupt,
mac_speed => "01",
update_speed => '0',
serial_command => '0',
serial_response => open,
debug0_sig => debug0_sig,
debug1_sig => debug1_sig,
debug2_sig => debug2_sig,
debug3_sig => debug3_sig,
-- AXI-Lite Interface
-----------
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
rx_path : switch_port_rx_path
Generic map(
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
FABRIC_DATA_WIDTH => FABRIC_DATA_WIDTH,
NR_PORTS => NR_PORTS,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
NR_IQ_FIFOS => NR_IQ_FIFOS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH,
PORT_ID => PORT_ID
)
Port map(
rx_path_clock => rx_path_clock,
rx_path_resetn => rx_path_resetn,
-- mac to rx_path interface
rx_in_data => mac2rx_data_sig,
rx_in_valid => mac2rx_valid_sig,
rx_in_last => mac2rx_last_sig,
rx_in_error => mac2rx_error_sig,
rx_in_timestamp_cnt => timestamp_cnt,
-- rx_path interface to fabric
rx_out_data => rx_out_data,
rx_out_valid => rx_out_valid,
rx_out_last => rx_out_last,
rx_out_ports_req => rx_out_ports_req,
rx_out_prio => rx_out_prio,
rx_out_timestamp => rx_out_timestamp,
rx_out_length => rx_out_length,
rx_out_ports_gnt => rx_out_ports_gnt
);
tx_path : switch_port_tx_path
Generic map(
FABRIC_DATA_WIDTH => FABRIC_DATA_WIDTH,
TRANSMITTER_DATA_WIDTH => TRANSMITTER_DATA_WIDTH,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
NR_OQ_FIFOS => NR_OQ_FIFOS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH
)
Port map(
tx_path_clock => tx_path_clock,
tx_path_resetn => tx_path_resetn,
-- tx_path interface to fabric
tx_in_data => tx_in_data,
tx_in_valid => tx_in_valid,
tx_in_length => tx_in_length,
tx_in_prio => tx_in_prio,
tx_in_timestamp => tx_in_timestamp,
tx_in_req => tx_in_req,
tx_in_accept_frame => tx_in_accept_frame,
-- timestamp
tx_in_timestamp_cnt => timestamp_cnt,
tx_out_latency => latency,
-- tx_path interface to mac
tx_out_data => tx2mac_data_sig,
tx_out_valid => tx2mac_valid_sig,
tx_out_ready => tx2mac_ready_sig,
tx_out_last => tx2mac_last_sig
);
end rtl;
|
-------------------------------------------------------------------------------
-- Title : Configurable Cordic core
-- Project :
-------------------------------------------------------------------------------
-- File : cordic_core.vhd
-- Author : Aylons <aylons@aylons-yoga2>
-- Company :
-- Created : 2014-05-03
-- Last update: 2015-10-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This CORDIC allow configuration of its number of stages and
-- accepts any bus size for its inputs and ouputs. The calculation to be done
-- is defined by a generic value, and there's no need for external codes due to
-- any parameter change.
-------------------------------------------------------------------------------
-- This file is part of Concordic.
--
-- Concordic is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Concordic is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- Copyright (c) 2014 Aylons Hazzud
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-03 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.dsp_cores_pkg.all;
-------------------------------------------------------------------------------
entity cordic_core is
generic (
g_stages : natural := 20;
g_bit_growth : natural := 2;
g_mode : string := "rect_to_polar"
);
-- x represents the x axis in rectangular coordinates or amplitude in polar
-- y represents the y axis in rectangular coordinates
-- z represents phase in polar coordinates
port (
x_i : in signed;
y_i : in signed;
z_i : in signed;
clk_i : in std_logic;
ce_i : in std_logic;
rst_i : in std_logic;
valid_i : in std_logic;
x_o : out signed;
y_o : out signed;
z_o : out signed;
valid_o : out std_logic
);
end entity cordic_core;
-------------------------------------------------------------------------------
architecture str of cordic_core is
constant c_width : natural := x_i'length + g_bit_growth + 2;
type wiring is array (0 to g_stages) of signed(c_width-1 downto 0);
type control_wiring is array (0 to g_stages) of boolean;
type z_wiring is array (0 to g_stages) of signed(x_i'length-1 downto 0);
signal x_inter : wiring := (others => (others => '0'));
signal y_inter : wiring := (others => (others => '0'));
signal z_inter : z_wiring := (others => (others => '0'));
signal x_shifted : wiring := (others => (others => '0'));
signal y_shifted : wiring := (others => (others => '0'));
signal control_x : control_wiring := (others => false);
signal control_y : control_wiring := (others => false);
function stage_constant(mode, stage, width : natural) return signed is
variable const_vector : signed(width-1 downto 0) := (others => '0');
begin
-- Each iteration must sum or subtract arctg(1/(2^(stage-1)))
-- Only works for cordics up to 32 bits. Wider constants require
-- pre-generated tables, due to limitations in most VHDL tool's
const_vector := to_signed(integer(arctan(2.0**(real(1-stage)))/(MATH_2_PI)*(2.0**real(width))), width);
return const_vector;
end function;
begin -- architecture str
--TODO: for now, it only generates a rect_to_polar CORDIC. Adapt so we can
--generate other algorithms while reusing as much code as possible, so it
--will be easy to maintain and evolve - hardware is already hard enough.
x_inter(0) <= resize(x_i, x_i'length+2) & (g_bit_growth-1 downto 0 => '0');
y_inter(0) <= resize(y_i, y_i'length+2) & (g_bit_growth-1 downto 0 => '0');
z_inter(0) <= z_i; -- left aligned
control_x(0) <= y_i(y_i'left) = '1';
control_y(0) <= y_i(y_i'left) = '0';
cmp_valid_pipe : pipeline
generic map (
g_width => 1,
g_depth => g_stages)
port map (
data_i(0) => valid_i,
clk_i => clk_i,
ce_i => ce_i,
data_o(0) => valid_o);
CORE_STAGES : for stage in 1 to g_stages generate
--control_x(stage) <= y_inter(stage-1) < 0;
--control_y(stage) <= y_inter(stage-1) > 0;
x_shifted(stage) <= shift_right(x_inter(stage-1), stage-1);
y_shifted(stage) <= shift_right(y_inter(stage-1), stage-1);
cmp_x_stage : addsub
port map(
a_i => x_inter(stage-1),
b_i => y_shifted(stage),
sub_i => control_x(stage-1),
clk_i => clk_i,
ce_i => ce_i,
rst_i => rst_i,
result_o => x_inter(stage),
positive_o => open,
negative_o => open);
cmp_y_stage : addsub
port map(
a_i => y_inter(stage-1),
b_i => x_shifted(stage),
sub_i => control_y(stage-1),
clk_i => clk_i,
ce_i => ce_i,
rst_i => rst_i,
result_o => y_inter(stage),
positive_o => control_y(stage),
negative_o => control_x(stage));
cmp_z_stage : addsub
port map (
a_i => z_inter(stage-1),
b_i => stage_constant(1, stage, x_i'length),
sub_i => control_x(stage-1),
clk_i => clk_i,
ce_i => ce_i,
rst_i => rst_i,
result_o => z_inter(stage),
positive_o => open,
negative_o => open);
end generate;
--TODO: Round the output
x_o <= x_inter(g_stages)(c_width-1 downto g_bit_growth+2);
y_o <= y_inter(g_stages)(c_width-1 downto g_bit_growth+2);
z_o <= z_inter(g_stages);
end architecture str;
|
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : types_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
use ieee_proposed.standard_textio_additions.all;
package types_pkg is
file ALERT_FILE : text;
file LOG_FILE : text;
constant C_LOG_HDR_FOR_WAVEVIEW_WIDTH : natural := 100; -- For string in waveview indicating last log header
type t_void is (VOID);
type t_natural_array is array (natural range <>) of natural;
type t_integer_array is array (natural range <>) of integer;
-- Note: Most types below have a matching to_string() in 'string_methods_pkg.vhd'
type t_info_target is (LOG_INFO, ALERT_INFO, USER_INFO);
type t_alert_level is (NOTE, TB_NOTE, WARNING, TB_WARNING, MANUAL_CHECK, ERROR, TB_ERROR, FAILURE, TB_FAILURE);
type t_enabled is (ENABLED, DISABLED);
type t_attention is (REGARD, EXPECT, IGNORE);
type t_radix is (BIN, HEX, DEC, HEX_BIN_IF_INVALID);
type t_radix_prefix is (EXCL_RADIX, INCL_RADIX);
type t_order is (INTERMEDIATE, FINAL);
type t_ascii_allow is (ALLOW_ALL, ALLOW_PRINTABLE_ONLY);
type t_blocking_mode is (BLOCKING, NON_BLOCKING);
type t_from_point_in_time is (FROM_NOW, FROM_LAST_EVENT);
type t_format_zeros is (AS_IS, SKIP_LEADING_0);
type t_format_string is (AS_IS, TRUNCATE, SKIP_LEADING_SPACE);
type t_log_format is (FORMATTED, UNFORMATTED);
type t_log_if_block_empty is (WRITE_HDR_IF_BLOCK_EMPTY, SKIP_LOG_IF_BLOCK_EMPTY, NOTIFY_IF_BLOCK_EMPTY);
type t_alert_counters is array (t_alert_level'left to t_alert_level'right) of natural;
type t_alert_attention is array (t_alert_level'left to t_alert_level'right) of t_attention;
type t_attention_counters is array (t_attention'left to t_attention'right) of natural; -- Only used to build below type
type t_alert_attention_counters is array (t_alert_level'left to t_alert_level'right) of t_attention_counters;
type t_quietness is (NON_QUIET, QUIET);
type t_deprecate_setting is (NO_DEPRECATE, DEPRECATE_ONCE, ALWAYS_DEPRECATE);
type t_deprecate_list is array(0 to 9) of string(1 to 100);
type t_global_ctrl is record
attention : t_alert_attention;
stop_limit : t_alert_counters;
end record;
type t_current_log_hdr is record
normal : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
large : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
xl : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
end record;
-------------------------------------
-- BFMs and above
-------------------------------------
type t_transaction_result is (ACK, NAK, ERROR); -- add more when needed
end package types_pkg;
package body types_pkg is
end package body types_pkg;
|
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : types_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
use ieee_proposed.standard_textio_additions.all;
package types_pkg is
file ALERT_FILE : text;
file LOG_FILE : text;
constant C_LOG_HDR_FOR_WAVEVIEW_WIDTH : natural := 100; -- For string in waveview indicating last log header
type t_void is (VOID);
type t_natural_array is array (natural range <>) of natural;
type t_integer_array is array (natural range <>) of integer;
-- Note: Most types below have a matching to_string() in 'string_methods_pkg.vhd'
type t_info_target is (LOG_INFO, ALERT_INFO, USER_INFO);
type t_alert_level is (NOTE, TB_NOTE, WARNING, TB_WARNING, MANUAL_CHECK, ERROR, TB_ERROR, FAILURE, TB_FAILURE);
type t_enabled is (ENABLED, DISABLED);
type t_attention is (REGARD, EXPECT, IGNORE);
type t_radix is (BIN, HEX, DEC, HEX_BIN_IF_INVALID);
type t_radix_prefix is (EXCL_RADIX, INCL_RADIX);
type t_order is (INTERMEDIATE, FINAL);
type t_ascii_allow is (ALLOW_ALL, ALLOW_PRINTABLE_ONLY);
type t_blocking_mode is (BLOCKING, NON_BLOCKING);
type t_from_point_in_time is (FROM_NOW, FROM_LAST_EVENT);
type t_format_zeros is (AS_IS, SKIP_LEADING_0);
type t_format_string is (AS_IS, TRUNCATE, SKIP_LEADING_SPACE);
type t_log_format is (FORMATTED, UNFORMATTED);
type t_log_if_block_empty is (WRITE_HDR_IF_BLOCK_EMPTY, SKIP_LOG_IF_BLOCK_EMPTY, NOTIFY_IF_BLOCK_EMPTY);
type t_alert_counters is array (t_alert_level'left to t_alert_level'right) of natural;
type t_alert_attention is array (t_alert_level'left to t_alert_level'right) of t_attention;
type t_attention_counters is array (t_attention'left to t_attention'right) of natural; -- Only used to build below type
type t_alert_attention_counters is array (t_alert_level'left to t_alert_level'right) of t_attention_counters;
type t_quietness is (NON_QUIET, QUIET);
type t_deprecate_setting is (NO_DEPRECATE, DEPRECATE_ONCE, ALWAYS_DEPRECATE);
type t_deprecate_list is array(0 to 9) of string(1 to 100);
type t_global_ctrl is record
attention : t_alert_attention;
stop_limit : t_alert_counters;
end record;
type t_current_log_hdr is record
normal : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
large : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
xl : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
end record;
-------------------------------------
-- BFMs and above
-------------------------------------
type t_transaction_result is (ACK, NAK, ERROR); -- add more when needed
end package types_pkg;
package body types_pkg is
end package body types_pkg;
|
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : types_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
use ieee_proposed.standard_textio_additions.all;
package types_pkg is
file ALERT_FILE : text;
file LOG_FILE : text;
constant C_LOG_HDR_FOR_WAVEVIEW_WIDTH : natural := 100; -- For string in waveview indicating last log header
type t_void is (VOID);
type t_natural_array is array (natural range <>) of natural;
type t_integer_array is array (natural range <>) of integer;
-- Note: Most types below have a matching to_string() in 'string_methods_pkg.vhd'
type t_info_target is (LOG_INFO, ALERT_INFO, USER_INFO);
type t_alert_level is (NOTE, TB_NOTE, WARNING, TB_WARNING, MANUAL_CHECK, ERROR, TB_ERROR, FAILURE, TB_FAILURE);
type t_enabled is (ENABLED, DISABLED);
type t_attention is (REGARD, EXPECT, IGNORE);
type t_radix is (BIN, HEX, DEC, HEX_BIN_IF_INVALID);
type t_radix_prefix is (EXCL_RADIX, INCL_RADIX);
type t_order is (INTERMEDIATE, FINAL);
type t_ascii_allow is (ALLOW_ALL, ALLOW_PRINTABLE_ONLY);
type t_blocking_mode is (BLOCKING, NON_BLOCKING);
type t_from_point_in_time is (FROM_NOW, FROM_LAST_EVENT);
type t_format_zeros is (AS_IS, SKIP_LEADING_0);
type t_format_string is (AS_IS, TRUNCATE, SKIP_LEADING_SPACE);
type t_log_format is (FORMATTED, UNFORMATTED);
type t_log_if_block_empty is (WRITE_HDR_IF_BLOCK_EMPTY, SKIP_LOG_IF_BLOCK_EMPTY, NOTIFY_IF_BLOCK_EMPTY);
type t_alert_counters is array (t_alert_level'left to t_alert_level'right) of natural;
type t_alert_attention is array (t_alert_level'left to t_alert_level'right) of t_attention;
type t_attention_counters is array (t_attention'left to t_attention'right) of natural; -- Only used to build below type
type t_alert_attention_counters is array (t_alert_level'left to t_alert_level'right) of t_attention_counters;
type t_quietness is (NON_QUIET, QUIET);
type t_deprecate_setting is (NO_DEPRECATE, DEPRECATE_ONCE, ALWAYS_DEPRECATE);
type t_deprecate_list is array(0 to 9) of string(1 to 100);
type t_global_ctrl is record
attention : t_alert_attention;
stop_limit : t_alert_counters;
end record;
type t_current_log_hdr is record
normal : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
large : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
xl : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
end record;
-------------------------------------
-- BFMs and above
-------------------------------------
type t_transaction_result is (ACK, NAK, ERROR); -- add more when needed
end package types_pkg;
package body types_pkg is
end package body types_pkg;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: DAQ_MEM_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : virtex5
-- C_XDEVICEFAMILY : virtex5
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 1
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 14
-- C_READ_WIDTH_A : 14
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 7
-- C_READ_WIDTH_B : 7
-- C_WRITE_DEPTH_B : 2048
-- C_READ_DEPTH_B : 2048
-- C_ADDRB_WIDTH : 11
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY DAQ_MEM_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END DAQ_MEM_prod;
ARCHITECTURE xilinx OF DAQ_MEM_prod IS
COMPONENT DAQ_MEM_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : DAQ_MEM_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
|
entity test is
type t is range 0 to 2#1#;
end;
|
package pkg is
type prot_t is protected
procedure proc(x : out integer);
end protected;
end package;
package body pkg is
type prot_t is protected body
procedure proc(x : out integer) is
function nested_fun return integer is
begin
return 5;
end function;
procedure nested_proc is
begin
x := nested_fun;
end procedure;
function nested_ifun return integer is
begin
return 0;
end function;
begin
nested_proc;
end procedure;
end protected body;
end package body;
-------------------------------------------------------------------------------
entity issue201 is
end entity;
use work.pkg.all;
architecture test of issue201 is
shared variable p : prot_t;
begin
process is
variable x : integer;
begin
p.proc(x);
assert x = 5;
wait;
end process;
end architecture;
|
package pkg is
type prot_t is protected
procedure proc(x : out integer);
end protected;
end package;
package body pkg is
type prot_t is protected body
procedure proc(x : out integer) is
function nested_fun return integer is
begin
return 5;
end function;
procedure nested_proc is
begin
x := nested_fun;
end procedure;
function nested_ifun return integer is
begin
return 0;
end function;
begin
nested_proc;
end procedure;
end protected body;
end package body;
-------------------------------------------------------------------------------
entity issue201 is
end entity;
use work.pkg.all;
architecture test of issue201 is
shared variable p : prot_t;
begin
process is
variable x : integer;
begin
p.proc(x);
assert x = 5;
wait;
end process;
end architecture;
|
package pkg is
type prot_t is protected
procedure proc(x : out integer);
end protected;
end package;
package body pkg is
type prot_t is protected body
procedure proc(x : out integer) is
function nested_fun return integer is
begin
return 5;
end function;
procedure nested_proc is
begin
x := nested_fun;
end procedure;
function nested_ifun return integer is
begin
return 0;
end function;
begin
nested_proc;
end procedure;
end protected body;
end package body;
-------------------------------------------------------------------------------
entity issue201 is
end entity;
use work.pkg.all;
architecture test of issue201 is
shared variable p : prot_t;
begin
process is
variable x : integer;
begin
p.proc(x);
assert x = 5;
wait;
end process;
end architecture;
|
package pkg is
type prot_t is protected
procedure proc(x : out integer);
end protected;
end package;
package body pkg is
type prot_t is protected body
procedure proc(x : out integer) is
function nested_fun return integer is
begin
return 5;
end function;
procedure nested_proc is
begin
x := nested_fun;
end procedure;
function nested_ifun return integer is
begin
return 0;
end function;
begin
nested_proc;
end procedure;
end protected body;
end package body;
-------------------------------------------------------------------------------
entity issue201 is
end entity;
use work.pkg.all;
architecture test of issue201 is
shared variable p : prot_t;
begin
process is
variable x : integer;
begin
p.proc(x);
assert x = 5;
wait;
end process;
end architecture;
|
package pkg is
type prot_t is protected
procedure proc(x : out integer);
end protected;
end package;
package body pkg is
type prot_t is protected body
procedure proc(x : out integer) is
function nested_fun return integer is
begin
return 5;
end function;
procedure nested_proc is
begin
x := nested_fun;
end procedure;
function nested_ifun return integer is
begin
return 0;
end function;
begin
nested_proc;
end procedure;
end protected body;
end package body;
-------------------------------------------------------------------------------
entity issue201 is
end entity;
use work.pkg.all;
architecture test of issue201 is
shared variable p : prot_t;
begin
process is
variable x : integer;
begin
p.proc(x);
assert x = 5;
wait;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Company: ITESM CQ
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 11:37:33 11/10/2015
-- Design Name:
-- Module Name: FSM_motor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Finite State Machine for Motor
--
-- Dependencies:
--
-- Revision:
-- Revision 0.0.1 - File Created
-- Revision 1.0.0 - Motor Implementation
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.PKG_ROBOT_SUMO.all;
entity FSM_motor is
port (
in_pres_state : in motor_state_values;
in_th : in integer;
in_tl : in integer;
out_next_state: out motor_state_values;
state_duration : out integer);
end FSM_motor;
architecture Behavioral of FSM_motor is
begin
-- Proceso que describe el modulo "Next State Logic"
--agrupar las seniales de entrada
fsm: process (in_pres_state, in_th, in_tl)
begin
case in_pres_state is
when MOTOR_HIGH =>
out_next_state <= MOTOR_LOW;
state_duration <= in_th;
when MOTOR_LOW =>
out_next_state <= MOTOR_HIGH;
state_duration <= in_tl ;
when others =>
out_next_state <= MOTOR_LOW;
state_duration <= in_th;
end case;
end process fsm;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: ITESM CQ
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 11:37:33 11/10/2015
-- Design Name:
-- Module Name: FSM_motor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Finite State Machine for Motor
--
-- Dependencies:
--
-- Revision:
-- Revision 0.0.1 - File Created
-- Revision 1.0.0 - Motor Implementation
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.PKG_ROBOT_SUMO.all;
entity FSM_motor is
port (
in_pres_state : in motor_state_values;
in_th : in integer;
in_tl : in integer;
out_next_state: out motor_state_values;
state_duration : out integer);
end FSM_motor;
architecture Behavioral of FSM_motor is
begin
-- Proceso que describe el modulo "Next State Logic"
--agrupar las seniales de entrada
fsm: process (in_pres_state, in_th, in_tl)
begin
case in_pres_state is
when MOTOR_HIGH =>
out_next_state <= MOTOR_LOW;
state_duration <= in_th;
when MOTOR_LOW =>
out_next_state <= MOTOR_HIGH;
state_duration <= in_tl ;
when others =>
out_next_state <= MOTOR_LOW;
state_duration <= in_th;
end case;
end process fsm;
end Behavioral;
|
architecture RTL of FIFO is
constant c_width : integer := 16;
constant c_depth : integer := 512;
constant c_word : integer:= 1024;
begin
end architecture RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2129.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02129ent IS
END c07s02b04x00p20n01i02129ent;
ARCHITECTURE c07s02b04x00p20n01i02129arch OF c07s02b04x00p20n01i02129ent IS
TYPE boolean_v is array (integer range <>) of boolean;
SUBTYPE boolean_5 is boolean_v (1 to 5);
SUBTYPE boolean_4 is boolean_v (1 to 4);
BEGIN
TESTING: PROCESS
variable result : boolean_5;
variable l_operand : boolean := true;
variable r_operand : boolean_4 := (true, false, true, false);
BEGIN
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result = (true, true, false, true, false)) and (result(1) = true))
report "***PASSED TEST: c07s02b04x00p20n01i02129"
severity NOTE;
assert ((result = (true, true, false, true, false)) and (result(1) = true))
report "***FAILED TEST: c07s02b04x00p20n01i02129 - Concatenation of element and BOOLEAN array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02129arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2129.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02129ent IS
END c07s02b04x00p20n01i02129ent;
ARCHITECTURE c07s02b04x00p20n01i02129arch OF c07s02b04x00p20n01i02129ent IS
TYPE boolean_v is array (integer range <>) of boolean;
SUBTYPE boolean_5 is boolean_v (1 to 5);
SUBTYPE boolean_4 is boolean_v (1 to 4);
BEGIN
TESTING: PROCESS
variable result : boolean_5;
variable l_operand : boolean := true;
variable r_operand : boolean_4 := (true, false, true, false);
BEGIN
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result = (true, true, false, true, false)) and (result(1) = true))
report "***PASSED TEST: c07s02b04x00p20n01i02129"
severity NOTE;
assert ((result = (true, true, false, true, false)) and (result(1) = true))
report "***FAILED TEST: c07s02b04x00p20n01i02129 - Concatenation of element and BOOLEAN array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02129arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2129.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02129ent IS
END c07s02b04x00p20n01i02129ent;
ARCHITECTURE c07s02b04x00p20n01i02129arch OF c07s02b04x00p20n01i02129ent IS
TYPE boolean_v is array (integer range <>) of boolean;
SUBTYPE boolean_5 is boolean_v (1 to 5);
SUBTYPE boolean_4 is boolean_v (1 to 4);
BEGIN
TESTING: PROCESS
variable result : boolean_5;
variable l_operand : boolean := true;
variable r_operand : boolean_4 := (true, false, true, false);
BEGIN
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result = (true, true, false, true, false)) and (result(1) = true))
report "***PASSED TEST: c07s02b04x00p20n01i02129"
severity NOTE;
assert ((result = (true, true, false, true, false)) and (result(1) = true))
report "***FAILED TEST: c07s02b04x00p20n01i02129 - Concatenation of element and BOOLEAN array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02129arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2616.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02616ent IS
END c13s03b01x00p02n01i02616ent;
ARCHITECTURE c13s03b01x00p02n01i02616arch OF c13s03b01x00p02n01i02616ent IS
BEGIN
TESTING: PROCESS
variable k*k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02616 - Identifier can not contain '*'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02616arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2616.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02616ent IS
END c13s03b01x00p02n01i02616ent;
ARCHITECTURE c13s03b01x00p02n01i02616arch OF c13s03b01x00p02n01i02616ent IS
BEGIN
TESTING: PROCESS
variable k*k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02616 - Identifier can not contain '*'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02616arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2616.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02616ent IS
END c13s03b01x00p02n01i02616ent;
ARCHITECTURE c13s03b01x00p02n01i02616arch OF c13s03b01x00p02n01i02616ent IS
BEGIN
TESTING: PROCESS
variable k*k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02616 - Identifier can not contain '*'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02616arch;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/RADIX22FFT_SDNF1_3_block.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_3_block
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/RADIX22FFT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_3_block IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_2_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_2_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_4_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_4_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_3_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_3_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_3_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_3_block;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_3_block IS
-- Signals
SIGNAL twdlXdin_2_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_2_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_4_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_4_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_3_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_3_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_4_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_4_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
BEGIN
twdlXdin_2_re_signed <= signed(twdlXdin_2_re);
twdlXdin_2_im_signed <= signed(twdlXdin_2_im);
twdlXdin_4_re_signed <= signed(twdlXdin_4_re);
twdlXdin_4_im_signed <= signed(twdlXdin_4_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_2_re_signed,
twdlXdin_2_im_signed, twdlXdin_4_re_signed, twdlXdin_4_im_signed,
twdlXdin_1_vld)
VARIABLE add_cast : signed(16 DOWNTO 0);
VARIABLE add_cast_0 : signed(16 DOWNTO 0);
VARIABLE sra_temp : signed(16 DOWNTO 0);
VARIABLE sub_cast : signed(16 DOWNTO 0);
VARIABLE sub_cast_0 : signed(16 DOWNTO 0);
VARIABLE sra_temp_0 : signed(16 DOWNTO 0);
VARIABLE add_cast_1 : signed(16 DOWNTO 0);
VARIABLE add_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp_2 : signed(16 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
add_cast := resize(twdlXdin_2_re_signed, 17);
add_cast_0 := resize(twdlXdin_4_re_signed, 17);
Radix22ButterflyG1_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(twdlXdin_2_re_signed, 17);
sub_cast_0 := resize(twdlXdin_4_re_signed, 17);
Radix22ButterflyG1_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_1 := resize(twdlXdin_2_im_signed, 17);
add_cast_2 := resize(twdlXdin_4_im_signed, 17);
Radix22ButterflyG1_NF_btf1_im_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(twdlXdin_2_im_signed, 17);
sub_cast_2 := resize(twdlXdin_4_im_signed, 17);
Radix22ButterflyG1_NF_btf2_im_reg_next <= sub_cast_1 - sub_cast_2;
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_re_reg, 1);
dout_3_re_tmp <= sra_temp(15 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_im_reg, 1);
dout_3_im_tmp <= sra_temp_0(15 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_re_reg, 1);
dout_4_re_tmp <= sra_temp_1(15 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_im_reg, 1);
dout_4_im_tmp <= sra_temp_2(15 DOWNTO 0);
dout_3_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_3_re <= std_logic_vector(dout_3_re_tmp);
dout_3_im <= std_logic_vector(dout_3_im_tmp);
dout_4_re <= std_logic_vector(dout_4_re_tmp);
dout_4_im <= std_logic_vector(dout_4_im_tmp);
END rtl;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF2_4_block6.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_4_block6
-- Source Path: fft_16_bit/FFT HDL Optimized/RADIX22FFT_SDNF2_4
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_4_block6 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
rotate_15 : IN std_logic; -- ufix1
dout_14_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20
dout_14_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20
dout_16_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20
dout_16_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_15_re : OUT std_logic_vector(20 DOWNTO 0); -- sfix21
dout_15_im : OUT std_logic_vector(20 DOWNTO 0); -- sfix21
dout_16_re_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21
dout_16_im_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21
dout_4_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_4_block6;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_4_block6 IS
-- Signals
SIGNAL dout_14_re_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_re : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_14_im_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_im : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_16_re_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din2_re : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_16_im_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din2_im : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(21 DOWNTO 0); -- sfix22
SIGNAL dout_15_re_tmp : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_15_im_tmp : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_16_re_tmp : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_16_im_tmp : signed(20 DOWNTO 0); -- sfix21
BEGIN
dout_14_re_signed <= signed(dout_14_re);
din1_re <= resize(dout_14_re_signed, 21);
dout_14_im_signed <= signed(dout_14_im);
din1_im <= resize(dout_14_im_signed, 21);
dout_16_re_signed <= signed(dout_16_re);
din2_re <= resize(dout_16_re_signed, 21);
dout_16_im_signed <= signed(dout_16_im);
din2_im <= resize(dout_16_im_signed, 21);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#000000#, 22);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#000000#, 22);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#000000#, 22);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#000000#, 22);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, din1_re, din1_im, din2_re, din2_im,
dout_1_vld, rotate_15)
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_15 /= '0' THEN
IF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(din1_re, 22) + resize(din2_im, 22);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(din1_re, 22) - resize(din2_im, 22);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(din1_im, 22) + resize(din2_re, 22);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(din1_im, 22) - resize(din2_re, 22);
END IF;
ELSIF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(din1_re, 22) + resize(din2_re, 22);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(din1_re, 22) - resize(din2_re, 22);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(din1_im, 22) + resize(din2_im, 22);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(din1_im, 22) - resize(din2_im, 22);
END IF;
dout_15_re_tmp <= Radix22ButterflyG2_NF_btf1_re_reg(20 DOWNTO 0);
dout_15_im_tmp <= Radix22ButterflyG2_NF_btf1_im_reg(20 DOWNTO 0);
dout_16_re_tmp <= Radix22ButterflyG2_NF_btf2_re_reg(20 DOWNTO 0);
dout_16_im_tmp <= Radix22ButterflyG2_NF_btf2_im_reg(20 DOWNTO 0);
dout_4_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_15_re <= std_logic_vector(dout_15_re_tmp);
dout_15_im <= std_logic_vector(dout_15_im_tmp);
dout_16_re_1 <= std_logic_vector(dout_16_re_tmp);
dout_16_im_1 <= std_logic_vector(dout_16_im_tmp);
END rtl;
|
-------------------------------------------------------------------------------
--
-- File: PkgZmodDAC.vhd
-- Author: Tudor Gherman
-- Original Project: Zmod DAC 1411 Low Level Controller
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This package contains the constants and functions used for the
-- ZmodDAC1411_Controller IP
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package PkgZmodDAC is
--Timing parameters
constant ktS : time := 2 ns; -- Setup time between CSB and SCLK
constant ktH : time := 2 ns; -- Hold time between CSB and SCLK
constant ktDS : time := 2 ns; -- Setup time between the data and the rising edge of SCLK
constant ktDH : time := 2 ns; -- Hold time between the data and the rising edge of SCLK
constant ktclk : time := 40 ns; -- minimum period of the SCLK
constant kSclkHigh : time := 10 ns; -- SCLK pulse width high (min)
constant kSclkLow : time := 10 ns; -- SCLK pulse width low (min)
--constant kSclkT_Max : time := 10 ns; -- SCLK pulse width low (min)
constant kSclkT_Min : time := 50 ns; -- SCLK pulse width low (min)
--constant kNoCommandBits : integer := 16; -- minimum period of the SCLK
constant kNoDataBits : integer := 8; -- minimum period of the SCLK
constant kTdcoMax : time := 4.4 ns;
constant kRelayConfigTime : time := 3ms; -- relay set and reset signals
--ADC Model Registers
constant aReg00_Mask : std_logic_vector(7 downto 0) := "01100110";
--Implementation constants
constant kCS_PulseWidthHigh : integer := 31; --CS pulse width high not specified for AD8717
constant kSPI_DataWidth : integer := 8; --ADI_SPI module data width
constant kSPI_CommandWidth : integer := 8; --ADI_SPI module command width
constant kSPI_AddrWidth : integer := kSPI_CommandWidth - 3; --ADI_SPI module command width
constant kSPI_SysClkDiv : integer := 4; --ADI_SPI module system clock divide constant
--No minimum SPI clock frequency specified by AD9717. The maximum frequency is 25MHz.
constant kCount20us : unsigned := to_unsigned (1999, 24); --Constant used to measure 20us with a clock frequency of 100MHz
constant kCount4ms : unsigned := to_unsigned (399999, 24); --Constant used to measure 4ms with a clock frequency of 100MHz
constant kCount150ms : unsigned := to_unsigned (14999999, 24); --Constant used to measure 150ms with a clock frequency of 100MHz
constant kCfgTimeout : unsigned := to_unsigned (14999999, 24); --Constant used to measure 150ms with a clock frequency of 100MHz
type FsmStatesSPI_t is (StIdle, StWrite, StRead1, StRead2, StRead3, StDone, StAssertCS);
type FsmStates_t is (StStart, StWriteConfigReg, StWaitDoneWriteReg, StReadControlReg,
StWaitDoneReadReg, StCheckCmdCnt, StInitDone, StIdle, StExtSPI_WrCmd,
StWaitDoneExtWrReg, StExtSPI_RdCmd, StWaitDoneExtRdReg, StRegExtRxData, StError);
type DAC_SPI_Commands_t is array (13 downto 0) of std_logic_vector(15 downto 0);
type DAC_SPI_Readback_t is array (13 downto 0) of std_logic_vector(7 downto 0);
-- List of commands sent to the AD9717 during the initialization process.
constant kDAC_SPI_Cmd : DAC_SPI_Commands_t := (
x"0E00", -- 13. Cal Control: Disable calibration clock.
x"1200", -- 12. Memory R/W: clear CALEN.
x"0FC0", -- 11. Cal Memory: Read CALSTAT. Read ONLY!
x"1210", -- 10. Memory R/W: CALEN - initialize self calibration.
x"0E3A", -- 9. Cal Control - step 3: Select Q DAC, I DAC self calibration.
x"0E0A", -- 8. Cal Control - step 2: Enable calibration clock.
x"0E02", -- 7. Cal Control - step 1: DIVSEL - calibration clock divide ratio from DAC clock rate set to 64.
x"1200", -- 6. Memory R/W: Self calibration step 1 (Write 0x00 to Register 0x12).
x"1400", -- 5. CLKMODE: Clear Reaquire bit in CLKMODE register.
x"1408", -- 4. CLKMODE: Toggle (step 2-set) Reaquire bit in CLKMODE register.
x"1400", -- 3. CLKMODE: Toggle (step 1-clear) Reaquire bit in CLKMODE register.
x"02B4", -- 2. Data Control: 2's Complement input data format, IDATA latched on DCLKIO rising edge,
-- I first of pair on data input pads, data clock input enable, data clock output disable.
x"0000", -- 1. SPI Control : Clear Reset.
x"0020" -- 0. SPI Control : Set Reset.
);
-- List of data expected to be read back fro the AD9717 at each step (after each register write) of the initialization process.
constant DAC_SPI_mask : DAC_SPI_Readback_t := (
x"00",
x"00",
x"3F",
x"EF",
x"00",
x"00",
x"00",
x"EF",
x"C3",
x"CB",
x"C3",
x"40",
x"80",
x"80"
);
constant kCmdTotal : integer := 13;
constant kCmdRdCalstatIndex : integer := 11; --Read ID command index in kADC_SPI_Cmd and kADC_SPI_Rdbck arrays
-- Constant used to measure 300 calibration clock cycles with a calibration clock divide ratio from DAC clock rate set to 64.
constant kCalTimeout : unsigned := to_unsigned (19200, 24);
-- Number of commands to load in the TX command FIFO for the CommandFIFO module
constant kCmdFIFO_NoWrCmds : integer := 4;
-- Command list loaded in the TX command FIFO of the CommandFIFO module
type CmdFIFO_WrCmdList_t is array (kCmdFIFO_NoWrCmds downto 0) of std_logic_vector(23 downto 0);
constant kCmdFIFO_WrList : CmdFIFO_WrCmdList_t := (
x"801F04", -- read Version register
x"0002B4", -- write Data Control register
x"8002B0", -- read Data Control register
x"0002B0", -- write Data Control register
x"000000" -- dummy
);
-- Number of commands expected to be returned and loaded in the RX command FIFO of
-- the SPI_IAP_AD9717_TestModule module in the tb_TestTop test bench.
-- It should be equal to the number of read commands in the kCmdFIFO_WrList.
constant kCmdFIFO_NoRdCmds : integer := 2;
-- Data expected in return after sending the kCmdFIFO_WrList commands by the CommandFIFO module
type CmdFIFO_RdCmdList_t is array (kCmdFIFO_NoRdCmds-1 downto 0) of std_logic_vector(7 downto 0);
constant kCmdFIFO_RdList : CmdFIFO_RdCmdList_t := (x"04",x"B0");
constant kCmdFIFO_RdListMask : CmdFIFO_RdCmdList_t := (x"00",x"40");
constant kCmdFIFO_Timeout : unsigned (23 downto 0) := x"000600";
end PkgZmodDAC;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2340.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02340ent IS
END c07s02b07x00p02n02i02340ent;
ARCHITECTURE c07s02b07x00p02n02i02340arch OF c07s02b07x00p02n02i02340ent IS
BEGIN
TESTING: PROCESS
type BYTE is array(7 downto 0) of BIT;
variable BYTEV : BYTE;
variable INTV : INTEGER;
BEGIN
INTV := BYTEV ** 2;
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02340 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02340arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2340.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02340ent IS
END c07s02b07x00p02n02i02340ent;
ARCHITECTURE c07s02b07x00p02n02i02340arch OF c07s02b07x00p02n02i02340ent IS
BEGIN
TESTING: PROCESS
type BYTE is array(7 downto 0) of BIT;
variable BYTEV : BYTE;
variable INTV : INTEGER;
BEGIN
INTV := BYTEV ** 2;
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02340 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02340arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2340.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02340ent IS
END c07s02b07x00p02n02i02340ent;
ARCHITECTURE c07s02b07x00p02n02i02340arch OF c07s02b07x00p02n02i02340ent IS
BEGIN
TESTING: PROCESS
type BYTE is array(7 downto 0) of BIT;
variable BYTEV : BYTE;
variable INTV : INTEGER;
BEGIN
INTV := BYTEV ** 2;
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02340 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02340arch;
|
-------------------------------------------------------------------------------
-- $Id: xbic_addr_be_support.vhd,v 1.2.2.1 2008/12/16 22:23:17 dougt Exp $
-------------------------------------------------------------------------------
-- xbic_addr_be_support.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2007, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: xbic_addr_be_support.vhd
--
-- Description:
-- This VHDL file implements the logic to combine the used portion of the
-- PLB_UABus with the PLB_ABus to form the actual internal address bus.
-- The module also implements the BE Mux that is required when the Slave
-- Native Data Width is less than the PLB data Bus width
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- xps_bram_if_cntlr.vhd
-- |
-- |- xbic_slave_attach_sngl
-- | |
-- | |- xbic_addr_decode
-- | |- xbic_addr_be_support
-- | |- xbic_data_steer_mirror
-- |
-- |- xbic_slave_attach_burst
-- |
-- |- xbic_addr_decode
-- |- xbic_addr_be_support
-- |- xbic_data_steer_mirror
-- |- xbic_addr_cntr
-- | |
-- | |- xbic_be_reset_gen.vhd
-- |
-- |- xbic_dbeat_control
-- |- xbic_data_steer_mirror
--
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.2.2.1 $
-- Date: $2/12/2007$
--
-- History:
-- DET 2/12/2007 Initial Version
--
-- DET 9/9/2008 v1_00_b for EDK 11.x release
-- ~~~~~~
-- - Updated Disclaimer in header section.
-- ^^^^^^
--
-- DET 12/16/2008 v1_01_b
-- ~~~~~~
-- - Updated eula/header to latest version.
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim; -- Required for Xilinx primitives
use unisim.all;
-------------------------------------------------------------------------------
entity xbic_addr_be_support is
generic (
C_SPLB_DWIDTH : Integer := 32;
C_SPLB_AWIDTH : Integer := 32;
C_SPLB_NATIVE_DWIDTH : Integer := 32
);
port (
-- Inputs from PLB
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_BE : in std_logic_vector(0 to (C_SPLB_DWIDTH/8)-1);
PLB_Msize : In std_logic_vector(0 to 1);
-- Outputs to Internal logic
Internal_ABus : out std_logic_vector(0 to C_SPLB_AWIDTH-1);
Internal_BE : out std_logic_vector(0 to (C_SPLB_NATIVE_DWIDTH/8)-1)
);
end entity xbic_addr_be_support;
architecture implementation of xbic_addr_be_support is
-- Constants
Constant UPPER_ADDR_SIZE : integer := C_SPLB_AWIDTH-32;
-- Signals
signal sig_combined_abus : std_logic_vector(0 to C_SPLB_AWIDTH-1);
begin --(architecture implementation)
Internal_ABus <= sig_combined_abus;
------------------------------------------------------------
-- If Generate
--
-- Label: ADDRESS_EQ_32
--
-- If Generate Description:
-- This IfGen hooks up the PLB_ABus when the
-- total number of address bits used is equal to 32.
-- In this case, the PLB_UABus is ignored.
------------------------------------------------------------
ADDRESS_EQ_32 : if (C_SPLB_AWIDTH = 32) generate
begin
sig_combined_abus <= PLB_ABus;
end generate ADDRESS_EQ_32;
------------------------------------------------------------
-- If Generate
--
-- Label: ADDRESS_GT_32
--
-- If Generate Description:
-- This IfGen combines the used portion of the PLB_UABus
-- with the PLB_ABus when the total number of address bits
-- used is greater than 32 but less than 64.
--
------------------------------------------------------------
ADDRESS_GT_32 : if (C_SPLB_AWIDTH > 32 and
C_SPLB_AWIDTH < 64) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: ASSIGN_ADDR
--
-- Process Description:
-- Combine the Upper and Lower address bus values into the
-- address bus used internally.
--
-------------------------------------------------------------
ASSIGN_ADDR : process (PLB_UABus,
PLB_ABus)
begin
-- Rip the used upper PLB addr bus bits and merge
-- into the most significant address bits
sig_combined_abus(0 to UPPER_ADDR_SIZE-1) <=
PLB_UABus((32-UPPER_ADDR_SIZE) to 31);
-- Assign least significant addr bus bits
sig_combined_abus(C_SPLB_AWIDTH-32 to
C_SPLB_AWIDTH-1)
<= PLB_ABus;
end process ASSIGN_ADDR;
end generate ADDRESS_GT_32;
------------------------------------------------------------
-- If Generate
--
-- Label: ADDRESS_EQ_64
--
-- If Generate Description:
-- This IfGen merges the PLB_UABus and the PLB_ABus when
-- the total number of address bits used is equal to 64.
--
------------------------------------------------------------
ADDRESS_EQ_64 : if (C_SPLB_AWIDTH = 64) generate
begin
sig_combined_abus(0 to 31) <= PLB_UABus ;
sig_combined_abus(32 to 63) <= PLB_ABus ;
end generate ADDRESS_EQ_64;
------------------------------------------------------------
-- If Generate
--
-- Label: PLB_EQ_SLAVE
--
-- If Generate Description:
-- Connects the PLB Be to the internal BE bus. No muxing
-- required when the PLB and the Slave are the same data width.
--
------------------------------------------------------------
PLB_EQ_SLAVE : if (C_SPLB_DWIDTH = C_SPLB_NATIVE_DWIDTH) generate
begin
Internal_BE <= PLB_BE;
end generate PLB_EQ_SLAVE;
------------------------------------------------------------
-- If Generate
--
-- Label: PLB64_SLAVE32
--
-- If Generate Description:
-- Muxes the PLB BE to the internal BE bus when the PLB
-- data Width is 64 bits and the Slave data width is 32 bits.
--
------------------------------------------------------------
PLB64_SLAVE32 : if (C_SPLB_DWIDTH = 64 and
C_SPLB_NATIVE_DWIDTH = 32) generate
begin
Internal_BE <= PLB_BE(4 to 7)
When PLB_ABus(29) = '1'
Else PLB_BE(0 to 3);
end generate PLB64_SLAVE32;
------------------------------------------------------------
-- If Generate
--
-- Label: PLB128_SLAVE32
--
-- If Generate Description:
-- Muxes the PLB BE to the internal BE bus when the PLB
-- data Width is 128 bits and the Slave data width is 32 bits.
--
------------------------------------------------------------
PLB128_SLAVE32 : if (C_SPLB_DWIDTH = 128 and
C_SPLB_NATIVE_DWIDTH = 32) generate
begin
Internal_BE <= PLB_BE(12 to 15)
When PLB_ABus(28 to 29) = "11"
Else PLB_BE(8 to 11)
When PLB_ABus(28 to 29) = "10"
Else PLB_BE(4 to 7)
When PLB_ABus(28 to 29) = "01"
Else PLB_BE(0 to 3);
end generate PLB128_SLAVE32;
------------------------------------------------------------
-- If Generate
--
-- Label: PLB128_SLAVE64
--
-- If Generate Description:
-- Muxes the PLB BE to the internal BE bus when the PLB
-- data Width is 128 bits and the Slave data width is 64 bits.
--
------------------------------------------------------------
PLB128_SLAVE64 : if (C_SPLB_DWIDTH = 128 and
C_SPLB_NATIVE_DWIDTH = 64) generate
begin
Internal_BE <= PLB_BE(8 to 15)
When PLB_ABus(28) = '1'
Else PLB_BE(0 to 7);
end generate PLB128_SLAVE64;
end implementation;
|
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