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-- File: elevator.vhd
-- Generated by MyHDL 0.8.1
-- Date: Sun Jun 14 22:11:56 2015
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_081.all;
entity elevator is
port (
clk: in std_logic;
reset: in std_logic;
en: in std_logic;
F: in unsigned(3 downto 0);
D: inout unsigned(3 downto 0);
Q: inout unsigned(3 downto 0);
A: inout std_logic;
B: inout std_logic;
A_latch: inout std_logic;
B_latch: inout std_logic;
LED: out unsigned(3 downto 0)
);
end entity elevator;
architecture MyHDL of elevator is
begin
ELEVATOR_ENCODER: process (en, F) is
begin
if (bool(F) and bool(en)) then
A <= stdl(bool(F(3)) or (bool(F(1)) and (not bool(F(2)))));
B <= stdl(bool(F(2)) or bool(F(3)));
end if;
end process ELEVATOR_ENCODER;
ELEVATOR_LATCH: process (reset, A, B, en, F) is
begin
if bool(reset) then
A_latch <= '0';
B_latch <= '0';
elsif (bool(F) and bool(en)) then
A_latch <= A;
B_latch <= B;
end if;
end process ELEVATOR_LATCH;
D <= unsigned'((((not bool(Q(3))) and (not bool(Q(2))) and (not bool(Q(1))) and (not bool(Q(0))) and bool(B_latch) and bool(A_latch)) or ((not bool(Q(3))) and (not bool(Q(2))) and bool(Q(1)) and (not bool(Q(0))) and (not bool(B_latch)) and (not bool(A_latch))) or (bool(Q(3)) and bool(Q(2)) and bool(Q(1)) and (not bool(Q(0)))) or ((not bool(Q(3))) and (not bool(Q(2))) and bool(Q(1)) and bool(Q(0)) and (not bool(B_latch)))) & (((not bool(Q(3))) and (not bool(Q(2))) and bool(Q(1)) and bool(Q(0)) and (not bool(B_latch)) and (not bool(A_latch))) or ((not bool(Q(3))) and (not bool(Q(2))) and (not bool(Q(1))) and bool(B_latch) and bool(A_latch)) or (bool(Q(3)) and bool(Q(2)) and (not bool(Q(1))) and bool(Q(0))) or ((not bool(Q(3))) and (not bool(Q(2))) and (not bool(Q(1))) and (not bool(Q(0))) and bool(B_latch))) & (((not bool(Q(3))) and (not bool(Q(2))) and bool(Q(1)) and bool(Q(0)) and (not bool(B_latch))) or ((not bool(Q(3))) and (not bool(Q(2))) and bool(Q(0)) and bool(B_latch)) or (bool(Q(2)) and (not bool(Q(1))) and bool(Q(0))) or ((not bool(Q(3))) and bool(Q(1)) and (not bool(Q(0))) and bool(B_latch)) or ((not bool(Q(3))) and bool(Q(2)) and bool(Q(1)) and (not bool(Q(0))))) & (((not bool(Q(3))) and (not bool(Q(2))) and bool(Q(1)) and (not bool(Q(0))) and (not bool(B_latch)) and (not bool(A_latch))) or ((not bool(Q(3))) and (not bool(Q(2))) and (not bool(Q(1))) and (not bool(B_latch)) and bool(A_latch)) or ((not bool(Q(3))) and (not bool(Q(2))) and bool(Q(1)) and bool(B_latch) and bool(A_latch)) or ((not bool(Q(3))) and (not bool(Q(2))) and (not bool(Q(1))) and (not bool(Q(0))) and bool(B_latch)) or (bool(Q(3)) and bool(Q(1)) and (not bool(Q(0)))) or ((not bool(Q(3))) and bool(Q(2)) and bool(Q(1)) and (not bool(Q(0)))) or (bool(Q(1)) and (not bool(Q(0))) and bool(A_latch))));
ELEVATOR_DFF: process (clk, reset) is
begin
if (reset = '1') then
Q <= to_unsigned(0, 4);
elsif rising_edge(clk) then
if bool(en) then
Q <= D;
end if;
end if;
end process ELEVATOR_DFF;
LED <= unsigned'((bool(Q(1)) and bool(Q(0))) & (bool(Q(1)) and (not bool(Q(0)))) & ((not bool(Q(1))) and bool(Q(0))) & ((not bool(Q(1))) and (not bool(Q(0)))));
end architecture MyHDL;
|
----------------------------------------------
-- Design Name : Test bench utils for apf27
-- File Name : apf27_test_pkg.vhd
-- Function : Defines communication functions between imx and fpga
-- Author : Fabien Marteau <[email protected]>
-- Version : 1.00
---------------------------------------------
-----------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package apf27_test_pkg is
CONSTANT CS_MIN : time := 13.6 ns;
CONSTANT CLOCK_PERIOD : time := 7.5188 ns;
CONSTANT WE3 : time := 2.25 ns;
CONSTANT WE4 : time := 2.25 ns;
-- write procedures
-- Params :
-- address : Write address
-- value : value to write
-- gls_clk : clock signal
-- imx_cs_n : Chip select
-- imx_oe_n : Read signal
-- imx_eb3_n : Write signal
-- imx_address : Address signal
-- imx_data : Data signal
-- WSC : Value of imx WSC (see MC9328MXLRM.pdf p169) for sync=0
procedure imx_write(
address : in std_logic_vector (15 downto 0);
value : in std_logic_vector (15 downto 0);
signal gls_clk : in std_logic ;
signal imx_cs_n : out std_logic ;
signal imx_oe_n : out std_logic ;
signal imx_eb3_n : out std_logic ;
signal imx_address : out std_logic_vector (12 downto 1);
signal imx_data : out std_logic_vector (15 downto 0);
WSC : natural
);
-- read procedures
-- Params :
-- address : Write address
-- value : value returned
-- gls_clk : clock signal
-- imx_cs_n : Chip select
-- imx_oe_n : Read signal
-- imx_eb3_n : Write signal
-- imx_address : Address signal
-- imx_data : Data signal
-- WSC : Value of imx WSC (see MC9328MXLRM.pdf p169) for sync=0
procedure imx_read(
address : in std_logic_vector (15 downto 0);
signal value : out std_logic_vector (15 downto 0);
signal gls_clk : in std_logic ;
signal imx_cs_n : out std_logic ;
signal imx_oe_n : out std_logic ;
signal imx_eb3_n : out std_logic ;
signal imx_address : out std_logic_vector (12 downto 1);
signal imx_data : in std_logic_vector (15 downto 0);
WSC : natural
);
end package apf27_test_pkg;
package body apf27_test_pkg is
-- Write value from imx
procedure imx_write(
address : in std_logic_vector (15 downto 0);
value : in std_logic_vector (15 downto 0);
signal gls_clk : in std_logic ;
signal imx_cs_n : out std_logic ;
signal imx_oe_n : out std_logic ;
signal imx_eb3_n : out std_logic ;
signal imx_address : out std_logic_vector (12 downto 1);
signal imx_data : out std_logic_vector (15 downto 0);
WSC : natural
) is
begin
-- Write value
wait until falling_edge(gls_clk);
wait for 4 ns;
imx_address <= address(12 downto 1);
imx_cs_n <= '0';
imx_eb3_n <= '0';
wait until falling_edge(gls_clk);
wait for 2500 ps;
imx_data <= value;
if WSC <= 1 then
wait until falling_edge(gls_clk);
else
for n in 1 to WSC loop
wait until falling_edge(gls_clk); -- WSC = 2
end loop;
end if;
wait for 1 ns;
imx_cs_n <= '1';
imx_eb3_n <= '1';
imx_address <= (others => 'Z');
imx_data <= (others => 'Z');
end procedure imx_write;
-- Read a value from imx
procedure imx_read(
address : in std_logic_vector (15 downto 0);
signal value : out std_logic_vector (15 downto 0);
signal gls_clk : in std_logic ;
signal imx_cs_n : out std_logic ;
signal imx_oe_n : out std_logic ;
signal imx_eb3_n : out std_logic ;
signal imx_address : out std_logic_vector (12 downto 1);
signal imx_data : in std_logic_vector (15 downto 0);
WSC : natural
) is
begin
-- Read value
wait until falling_edge(gls_clk);
wait for WE3;
imx_address <= address(12 downto 1);
imx_cs_n <= '0';
imx_oe_n <= '0';
wait for CS_MIN; -- minimum chip select time
if WSC > 1 then
for n in 2 to WSC loop
wait until falling_edge(gls_clk);
end loop;
--wait for CLOCK_PERIOD*(WSC-1);
end if;
wait for WE4;
value <= imx_data;
imx_cs_n <= '1';
imx_oe_n <= '1';
imx_address <= (others => 'Z');
end procedure imx_read;
end package body apf27_test_pkg;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 15:28:57 11/14/2015
-- Design Name:
-- Module Name: Register_Files - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Register_Files is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
ASel : in STD_LOGIC_VECTOR (3 downto 0);
BSel : in STD_LOGIC_VECTOR (3 downto 0);
WSel : in STD_LOGIC_VECTOR (3 downto 0);
WE : in STD_LOGIC;
WVal : in STD_LOGIC_VECTOR (15 downto 0);
AVal : out STD_LOGIC_VECTOR (15 downto 0);
BVal : out STD_LOGIC_VECTOR (15 downto 0);
RAVal : out STD_LOGIC_VECTOR (15 downto 0);
SPVal : out STD_LOGIC_VECTOR (15 downto 0);
IHVal : out STD_LOGIC_VECTOR (15 downto 0)
);
end Register_Files;
architecture Behavioral of Register_Files is
type regs is array (0 to 10) of STD_LOGIC_VECTOR(15 downto 0);
-- 8 universal regs (R0 ~ R7) and 3 special regs (RA 1000, SP 1001, IH 1010)
signal regfiles : regs := (others => (others => '0'));
begin
process (clk, reset)
begin
if (reset = '0') then
RAVal <= (others => '0');
SPVal <= (others => '0');
IHVal <= (others => '0');
AVal <= (others => '0');
BVal <= (others => '0');
regfiles <= (others => (others => '0'));
elsif (clk'event and clk = '1') then
if (WE = '1' and WSel /= "1111") then
regfiles(CONV_INTEGER(unsigned(WSel))) <= WVal;
if ("1000" = WSel) then
RAVal <= WVal;
else
RAVal <= regfiles(8);
end if;
if ("1001" = WSel) then
SPVal <= WVal;
else
SPVal <= regfiles(9);
end if;
if ("1010" = WSel) then
IHVal <= WVal;
else
IHVal <= regfiles(10);
end if;
if (ASel = WSel) then
AVal <= WVal;
else
AVal <= regfiles(CONV_INTEGER(unsigned(ASel(2 downto 0))));
end if;
if (BSel = WSel) then
BVal <= WVal;
else
BVal <= regfiles(CONV_INTEGER(unsigned(BSel(2 downto 0))));
end if;
else
RAVal <= regfiles(8);
SPVal <= regfiles(9);
IHVal <= regfiles(10);
AVal <= regfiles(CONV_INTEGER(unsigned(ASel(2 downto 0))));
BVal <= regfiles(CONV_INTEGER(unsigned(BSel(2 downto 0))));
end if;
end if;
end process;
end Behavioral;
|
-- Create Date: 16:41:40 09/28/2017
-- Design Name:
-- Module Name: Mod5Seu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Mod5Seu is
Port ( imm13 : in STD_LOGIC_VECTOR (12 downto 0);
SEUimm32 : out STD_LOGIC_VECTOR (31 downto 0));
end Mod5Seu;
architecture Behavioral of Mod5Seu is
begin
process (imm13)
begin
if imm13(12) = '1' then
SEUimm32 <= "1111111111111111111"&imm13;
else
SEUimm32<= "0000000000000000000"&imm13;
end if;
end process;
end Behavioral;
|
-- Create Date: 16:41:40 09/28/2017
-- Design Name:
-- Module Name: Mod5Seu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Mod5Seu is
Port ( imm13 : in STD_LOGIC_VECTOR (12 downto 0);
SEUimm32 : out STD_LOGIC_VECTOR (31 downto 0));
end Mod5Seu;
architecture Behavioral of Mod5Seu is
begin
process (imm13)
begin
if imm13(12) = '1' then
SEUimm32 <= "1111111111111111111"&imm13;
else
SEUimm32<= "0000000000000000000"&imm13;
end if;
end process;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc490.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p01n01i00490ent IS
END c03s02b02x00p01n01i00490ent;
ARCHITECTURE c03s02b02x00p01n01i00490arch OF c03s02b02x00p01n01i00490ent IS
type T0 is record
el1 : real;
el2 : real;
el3 : real;
el4 : real;
el5 : real;
el6 : real;
el7 : real;
el8 : real;
el9 : real;
el10 : real;
end record;
type T1 is record
el1 : real;
el2 : real;
el3 : real;
el4 : real;
el5 : real;
el6 : real;
end record;
type T2 is record
el5 : real;
el6 : real;
el7 : real;
end record;
function FUNC1(signal recd1: T0) return T1 is
variable recd2:T1;
begin -- procedure FUNC1
recd2.el1 := recd1.el6;
recd2.el2 := recd1.el1;
recd2.el3 := recd1.el3;
recd2.el4 := recd1.el2;
recd2.el5 := recd1.el6;
recd2.el6 := recd1.el10;
return recd2;
end FUNC1;
function FUNC3(signal recd1: T0) return T2 is
variable recd2:T2;
begin -- procedure FUNC3
recd2.el5 := recd1.el5;
recd2.el6 := recd1.el6;
recd2.el7 := recd1.el1;
return recd2;
end FUNC3;
function FUNC4(signal recd1: T2) return T2 is
variable recd2:T2;
begin -- procedure FUNC4
recd2.el5 := recd1.el7;
recd2.el6 := recd1.el5;
recd2.el7 := recd1.el5;
return recd2;
end FUNC4;
signal rec1: T0;
signal s1,v2:T1;
signal s3,s4:T2;
BEGIN
TESTING: PROCESS
BEGIN
rec1 <= (1.1,2.2,3.3,4.4,5.5,6.6,7.7,8.8,9.9,10.01);
wait for 1 ns;
s1 <= FUNC1(rec1);
s3 <= FUNC3(rec1);
wait for 1 ns;
s4 <= FUNC4(s3);
wait for 1 ns;
assert NOT( (s1 = (6.6,1.1,3.3,2.2,6.6,10.01)) AND
(s3 = (5.5,6.6,1.1)) AND
(s4 = (1.1,5.5,5.5)))
report "***PASSED TEST: c03s02b02x00p01n01i00490"
severity NOTE;
assert ( (s1 = (6.6,1.1,3.3,2.2,6.6,10.01)) AND
(s3 = (5.5,6.6,1.1)) AND
(s4 = (1.1,5.5,5.5)))
report "***FAILED TEST: c03s02b02x00p01n01i00490 - Values of a record object consist of the value of its elements."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p01n01i00490arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc490.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p01n01i00490ent IS
END c03s02b02x00p01n01i00490ent;
ARCHITECTURE c03s02b02x00p01n01i00490arch OF c03s02b02x00p01n01i00490ent IS
type T0 is record
el1 : real;
el2 : real;
el3 : real;
el4 : real;
el5 : real;
el6 : real;
el7 : real;
el8 : real;
el9 : real;
el10 : real;
end record;
type T1 is record
el1 : real;
el2 : real;
el3 : real;
el4 : real;
el5 : real;
el6 : real;
end record;
type T2 is record
el5 : real;
el6 : real;
el7 : real;
end record;
function FUNC1(signal recd1: T0) return T1 is
variable recd2:T1;
begin -- procedure FUNC1
recd2.el1 := recd1.el6;
recd2.el2 := recd1.el1;
recd2.el3 := recd1.el3;
recd2.el4 := recd1.el2;
recd2.el5 := recd1.el6;
recd2.el6 := recd1.el10;
return recd2;
end FUNC1;
function FUNC3(signal recd1: T0) return T2 is
variable recd2:T2;
begin -- procedure FUNC3
recd2.el5 := recd1.el5;
recd2.el6 := recd1.el6;
recd2.el7 := recd1.el1;
return recd2;
end FUNC3;
function FUNC4(signal recd1: T2) return T2 is
variable recd2:T2;
begin -- procedure FUNC4
recd2.el5 := recd1.el7;
recd2.el6 := recd1.el5;
recd2.el7 := recd1.el5;
return recd2;
end FUNC4;
signal rec1: T0;
signal s1,v2:T1;
signal s3,s4:T2;
BEGIN
TESTING: PROCESS
BEGIN
rec1 <= (1.1,2.2,3.3,4.4,5.5,6.6,7.7,8.8,9.9,10.01);
wait for 1 ns;
s1 <= FUNC1(rec1);
s3 <= FUNC3(rec1);
wait for 1 ns;
s4 <= FUNC4(s3);
wait for 1 ns;
assert NOT( (s1 = (6.6,1.1,3.3,2.2,6.6,10.01)) AND
(s3 = (5.5,6.6,1.1)) AND
(s4 = (1.1,5.5,5.5)))
report "***PASSED TEST: c03s02b02x00p01n01i00490"
severity NOTE;
assert ( (s1 = (6.6,1.1,3.3,2.2,6.6,10.01)) AND
(s3 = (5.5,6.6,1.1)) AND
(s4 = (1.1,5.5,5.5)))
report "***FAILED TEST: c03s02b02x00p01n01i00490 - Values of a record object consist of the value of its elements."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p01n01i00490arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc490.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p01n01i00490ent IS
END c03s02b02x00p01n01i00490ent;
ARCHITECTURE c03s02b02x00p01n01i00490arch OF c03s02b02x00p01n01i00490ent IS
type T0 is record
el1 : real;
el2 : real;
el3 : real;
el4 : real;
el5 : real;
el6 : real;
el7 : real;
el8 : real;
el9 : real;
el10 : real;
end record;
type T1 is record
el1 : real;
el2 : real;
el3 : real;
el4 : real;
el5 : real;
el6 : real;
end record;
type T2 is record
el5 : real;
el6 : real;
el7 : real;
end record;
function FUNC1(signal recd1: T0) return T1 is
variable recd2:T1;
begin -- procedure FUNC1
recd2.el1 := recd1.el6;
recd2.el2 := recd1.el1;
recd2.el3 := recd1.el3;
recd2.el4 := recd1.el2;
recd2.el5 := recd1.el6;
recd2.el6 := recd1.el10;
return recd2;
end FUNC1;
function FUNC3(signal recd1: T0) return T2 is
variable recd2:T2;
begin -- procedure FUNC3
recd2.el5 := recd1.el5;
recd2.el6 := recd1.el6;
recd2.el7 := recd1.el1;
return recd2;
end FUNC3;
function FUNC4(signal recd1: T2) return T2 is
variable recd2:T2;
begin -- procedure FUNC4
recd2.el5 := recd1.el7;
recd2.el6 := recd1.el5;
recd2.el7 := recd1.el5;
return recd2;
end FUNC4;
signal rec1: T0;
signal s1,v2:T1;
signal s3,s4:T2;
BEGIN
TESTING: PROCESS
BEGIN
rec1 <= (1.1,2.2,3.3,4.4,5.5,6.6,7.7,8.8,9.9,10.01);
wait for 1 ns;
s1 <= FUNC1(rec1);
s3 <= FUNC3(rec1);
wait for 1 ns;
s4 <= FUNC4(s3);
wait for 1 ns;
assert NOT( (s1 = (6.6,1.1,3.3,2.2,6.6,10.01)) AND
(s3 = (5.5,6.6,1.1)) AND
(s4 = (1.1,5.5,5.5)))
report "***PASSED TEST: c03s02b02x00p01n01i00490"
severity NOTE;
assert ( (s1 = (6.6,1.1,3.3,2.2,6.6,10.01)) AND
(s3 = (5.5,6.6,1.1)) AND
(s4 = (1.1,5.5,5.5)))
report "***FAILED TEST: c03s02b02x00p01n01i00490 - Values of a record object consist of the value of its elements."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p01n01i00490arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc251.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00251ent IS
END c03s01b02x00p04n01i00251ent;
ARCHITECTURE c03s01b02x00p04n01i00251arch OF c03s01b02x00p04n01i00251ent IS
type I1 is range 1 to 10;
type I2 is range 11 to 20;
constant V1: I1 := 1;
constant V2: I2 := 20;
type I5 is range V1 to V2;
BEGIN
TESTING: PROCESS
variable k : integer := 6;
BEGIN
k := 5;
assert NOT(k=5)
report "***PASSED TEST: c03s01b02x00p04n01i00251"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c03s01b02x00p04n01i00251 - Range constraints in integer type definition need not be of the same integer type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00251arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc251.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00251ent IS
END c03s01b02x00p04n01i00251ent;
ARCHITECTURE c03s01b02x00p04n01i00251arch OF c03s01b02x00p04n01i00251ent IS
type I1 is range 1 to 10;
type I2 is range 11 to 20;
constant V1: I1 := 1;
constant V2: I2 := 20;
type I5 is range V1 to V2;
BEGIN
TESTING: PROCESS
variable k : integer := 6;
BEGIN
k := 5;
assert NOT(k=5)
report "***PASSED TEST: c03s01b02x00p04n01i00251"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c03s01b02x00p04n01i00251 - Range constraints in integer type definition need not be of the same integer type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00251arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc251.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00251ent IS
END c03s01b02x00p04n01i00251ent;
ARCHITECTURE c03s01b02x00p04n01i00251arch OF c03s01b02x00p04n01i00251ent IS
type I1 is range 1 to 10;
type I2 is range 11 to 20;
constant V1: I1 := 1;
constant V2: I2 := 20;
type I5 is range V1 to V2;
BEGIN
TESTING: PROCESS
variable k : integer := 6;
BEGIN
k := 5;
assert NOT(k=5)
report "***PASSED TEST: c03s01b02x00p04n01i00251"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c03s01b02x00p04n01i00251 - Range constraints in integer type definition need not be of the same integer type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00251arch;
|
entity test is
end test;
architecture only of test is
begin -- only
p: process
type color is ( red, blue, green );
variable x : color;
begin -- process p
for i in red to green loop
x := i;
end loop; -- i
assert x = green report "TEST FAILED x was " & color'image(x) severity ERROR;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
begin -- only
p: process
type color is ( red, blue, green );
variable x : color;
begin -- process p
for i in red to green loop
x := i;
end loop; -- i
assert x = green report "TEST FAILED x was " & color'image(x) severity ERROR;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
begin -- only
p: process
type color is ( red, blue, green );
variable x : color;
begin -- process p
for i in red to green loop
x := i;
end loop; -- i
assert x = green report "TEST FAILED x was " & color'image(x) severity ERROR;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
-- $Id: tst_snhumanio.vhd 416 2011-10-15 13:32:57Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tst_snhumanio - syn
-- Description: simple stand-alone tester for sn_humanio
--
-- Dependencies: -
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-15 416 1.0.2 fix sensitivity list of proc_next
-- 2011-10-08 412 1.0.1 use better rndm init (so that swi=0 is non-const)
-- 2011-09-17 410 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.comlib.all;
-- ----------------------------------------------------------------------------
entity tst_snhumanio is -- tester for rlink
generic (
BWIDTH : positive := 4); -- BTN port width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_MSEC : in slbit; -- msec pulse
SWI : in slv8; -- switch settings
BTN : in slv(BWIDTH-1 downto 0); -- button settings
LED : out slv8; -- led data
DSP_DAT : out slv16; -- display data
DSP_DP : out slv4 -- display decimal points
);
end tst_snhumanio;
architecture syn of tst_snhumanio is
constant c_mode_rndm : slv2 := "00";
constant c_mode_cnt : slv2 := "01";
constant c_mode_swi : slv2 := "10";
constant c_mode_btst : slv2 := "11";
type regs_type is record
mode : slv2; -- current mode
allon : slbit; -- all LEDs on if set
cnt : slv16; -- counter
tcnt : slv16; -- swi/btn toggle counter
rndm : slv8; -- random number
swi_1 : slv8; -- last SWI state
btn_1 : slv(BWIDTH-1 downto 0); -- last BTN state
led : slv8; -- LED output state
dsp : slv16; -- display data
dp : slv4; -- display decimal points
end record regs_type;
-- the rndm start value is /= 0 because a seed of 0 with a SWI setting of 0
-- will result in a 0-0-0 sequence. The 01010101 start will get trapped in a
-- constant sequence with a 01100011 switch setting, which is rather unlikely.
constant rndminit : slv8 := "01010101";
constant btnzero : slv(BWIDTH-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
c_mode_rndm, -- mode
'0', -- allon
(others=>'0'), -- cnt
(others=>'0'), -- tcnt
rndminit, -- rndm
(others=>'0'), -- swi_1
btnzero, -- btn_1
(others=>'0'), -- led
(others=>'0'), -- dsp
(others=>'0') -- dp
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal BTN4 : slbit := '0';
begin
assert BWIDTH>=4
report "assert(BWIDTH>=4): at least 4 BTNs available"
severity failure;
B4YES: if BWIDTH > 4 generate
BTN4 <= BTN(4);
end generate B4YES;
B4NO: if BWIDTH = 4 generate
BTN4 <= '0';
end generate B4NO;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_MSEC, SWI, BTN, BTN4)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable btn03 : slv4 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
n.swi_1 := SWI;
n.btn_1 := BTN;
if SWI/=r.swi_1 or BTN/=r.btn_1 then
n.tcnt := slv(unsigned(r.tcnt) + 1);
end if;
btn03 := BTN(3 downto 0);
n.allon := BTN4;
if unsigned(BTN) /= 0 then -- is a button being pressed ?
if r.mode /= c_mode_btst then -- not in btst mode
case btn03 is
when "0001" => -- 0001 single button -> rndm mode
n.mode := c_mode_rndm;
n.rndm := rndminit;
when "0010" => -- 0010 single button -> cnt mode
n.mode := c_mode_cnt;
when "0100" => -- 0100 single button -> swi mode
n.mode := c_mode_swi;
when "1000" => -- 1001 single button -> btst mode
n.mode := c_mode_btst;
n.tcnt := (others=>'0');
when others => -- any 2+ button combo -> led test
n.allon := '1';
end case;
else -- button press in btst mode
case btn03 is
when "1001" => -- 1001 double btn -> rndm mode
n.mode := c_mode_rndm;
when "1010" => -- 1010 double btn -> rndm cnt
n.mode := c_mode_cnt;
when "1100" => -- 1100 double btn -> rndm swi
n.mode := c_mode_swi;
when others => null;
end case;
end if;
else -- no button being pressed
if CE_MSEC = '1' then -- on every usec
n.cnt := slv(unsigned(r.cnt) + 1); -- inc counter
if unsigned(r.cnt(8 downto 0)) = 0 then -- every 1/2 sec (approx.)
n.rndm := crc8_update(r.rndm, SWI); -- update rndm state
end if;
end if;
end if;
if r.allon = '1' then -- if led test selected
n.led := (others=>'1'); -- all led,dsp,dp on
n.dsp := (others=>'1');
n.dp := (others=>'1');
else -- no led test, normal output
case r.mode is
when c_mode_rndm =>
n.led := r.rndm;
n.dsp(7 downto 0) := r.rndm;
n.dsp(15 downto 8) := not r.rndm;
when c_mode_cnt =>
n.led := r.cnt(14 downto 7);
n.dsp := r.cnt;
when c_mode_swi =>
n.led := SWI;
n.dsp(7 downto 0) := SWI;
n.dsp(15 downto 8) := not SWI;
when c_mode_btst =>
n.led := SWI;
n.dsp := r.tcnt;
when others => null;
end case;
n.dp := BTN(3 downto 0);
end if;
N_REGS <= n;
LED <= r.led;
DSP_DAT <= r.dsp;
DSP_DP <= r.dp;
end process proc_next;
end syn;
|
-- $Id: tst_snhumanio.vhd 416 2011-10-15 13:32:57Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tst_snhumanio - syn
-- Description: simple stand-alone tester for sn_humanio
--
-- Dependencies: -
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-15 416 1.0.2 fix sensitivity list of proc_next
-- 2011-10-08 412 1.0.1 use better rndm init (so that swi=0 is non-const)
-- 2011-09-17 410 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.comlib.all;
-- ----------------------------------------------------------------------------
entity tst_snhumanio is -- tester for rlink
generic (
BWIDTH : positive := 4); -- BTN port width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_MSEC : in slbit; -- msec pulse
SWI : in slv8; -- switch settings
BTN : in slv(BWIDTH-1 downto 0); -- button settings
LED : out slv8; -- led data
DSP_DAT : out slv16; -- display data
DSP_DP : out slv4 -- display decimal points
);
end tst_snhumanio;
architecture syn of tst_snhumanio is
constant c_mode_rndm : slv2 := "00";
constant c_mode_cnt : slv2 := "01";
constant c_mode_swi : slv2 := "10";
constant c_mode_btst : slv2 := "11";
type regs_type is record
mode : slv2; -- current mode
allon : slbit; -- all LEDs on if set
cnt : slv16; -- counter
tcnt : slv16; -- swi/btn toggle counter
rndm : slv8; -- random number
swi_1 : slv8; -- last SWI state
btn_1 : slv(BWIDTH-1 downto 0); -- last BTN state
led : slv8; -- LED output state
dsp : slv16; -- display data
dp : slv4; -- display decimal points
end record regs_type;
-- the rndm start value is /= 0 because a seed of 0 with a SWI setting of 0
-- will result in a 0-0-0 sequence. The 01010101 start will get trapped in a
-- constant sequence with a 01100011 switch setting, which is rather unlikely.
constant rndminit : slv8 := "01010101";
constant btnzero : slv(BWIDTH-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
c_mode_rndm, -- mode
'0', -- allon
(others=>'0'), -- cnt
(others=>'0'), -- tcnt
rndminit, -- rndm
(others=>'0'), -- swi_1
btnzero, -- btn_1
(others=>'0'), -- led
(others=>'0'), -- dsp
(others=>'0') -- dp
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal BTN4 : slbit := '0';
begin
assert BWIDTH>=4
report "assert(BWIDTH>=4): at least 4 BTNs available"
severity failure;
B4YES: if BWIDTH > 4 generate
BTN4 <= BTN(4);
end generate B4YES;
B4NO: if BWIDTH = 4 generate
BTN4 <= '0';
end generate B4NO;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_MSEC, SWI, BTN, BTN4)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable btn03 : slv4 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
n.swi_1 := SWI;
n.btn_1 := BTN;
if SWI/=r.swi_1 or BTN/=r.btn_1 then
n.tcnt := slv(unsigned(r.tcnt) + 1);
end if;
btn03 := BTN(3 downto 0);
n.allon := BTN4;
if unsigned(BTN) /= 0 then -- is a button being pressed ?
if r.mode /= c_mode_btst then -- not in btst mode
case btn03 is
when "0001" => -- 0001 single button -> rndm mode
n.mode := c_mode_rndm;
n.rndm := rndminit;
when "0010" => -- 0010 single button -> cnt mode
n.mode := c_mode_cnt;
when "0100" => -- 0100 single button -> swi mode
n.mode := c_mode_swi;
when "1000" => -- 1001 single button -> btst mode
n.mode := c_mode_btst;
n.tcnt := (others=>'0');
when others => -- any 2+ button combo -> led test
n.allon := '1';
end case;
else -- button press in btst mode
case btn03 is
when "1001" => -- 1001 double btn -> rndm mode
n.mode := c_mode_rndm;
when "1010" => -- 1010 double btn -> rndm cnt
n.mode := c_mode_cnt;
when "1100" => -- 1100 double btn -> rndm swi
n.mode := c_mode_swi;
when others => null;
end case;
end if;
else -- no button being pressed
if CE_MSEC = '1' then -- on every usec
n.cnt := slv(unsigned(r.cnt) + 1); -- inc counter
if unsigned(r.cnt(8 downto 0)) = 0 then -- every 1/2 sec (approx.)
n.rndm := crc8_update(r.rndm, SWI); -- update rndm state
end if;
end if;
end if;
if r.allon = '1' then -- if led test selected
n.led := (others=>'1'); -- all led,dsp,dp on
n.dsp := (others=>'1');
n.dp := (others=>'1');
else -- no led test, normal output
case r.mode is
when c_mode_rndm =>
n.led := r.rndm;
n.dsp(7 downto 0) := r.rndm;
n.dsp(15 downto 8) := not r.rndm;
when c_mode_cnt =>
n.led := r.cnt(14 downto 7);
n.dsp := r.cnt;
when c_mode_swi =>
n.led := SWI;
n.dsp(7 downto 0) := SWI;
n.dsp(15 downto 8) := not SWI;
when c_mode_btst =>
n.led := SWI;
n.dsp := r.tcnt;
when others => null;
end case;
n.dp := BTN(3 downto 0);
end if;
N_REGS <= n;
LED <= r.led;
DSP_DAT <= r.dsp;
DSP_DP <= r.dp;
end process proc_next;
end syn;
|
-- SIMON 64/128
-- key scheduling function
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- r: round index
-- k_0..k_3: key
-- subkey_out: round subkey
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity key_schedule is
port (
r : in std_logic_vector(7 downto 0);
-- we don't need k_2 here because of the way we schedule k(r) in the simon component
k_0 : in std_logic_vector(31 downto 0);
k_1 : in std_logic_vector(31 downto 0);
k_3 : in std_logic_vector(31 downto 0);
subkey_out : out std_logic_vector(31 downto 0));
end key_schedule;
architecture Behavioral of key_schedule is
signal op_3_s : std_logic_vector(31 downto 0);
signal op_xor_0 : std_logic_vector(31 downto 0);
signal op_1_s : std_logic_vector(31 downto 0);
signal seqC : std_logic_vector(31 downto 0);
signal sequence : std_logic_vector(61 downto 0);
begin
-- C ^ sequence[(r-4) % 62]
sequence <= "11110000101100111001010001001000000111101001100011010111011011"; -- z3
-- 0xFFFFFFFFFFFFFFFC xor sequence[(r-4) % 62]
-- TODO: 1-bit latch for seqC(0) is used, not recommended...
seqC <= ("1111111111111111111111111111110" & sequence((to_integer(unsigned(r)) - 4) mod 62)) when (to_integer(unsigned(r)) > 3) else "11111111111111111111111111111100";
-- tmp = K[3] >> 3
op_3_s <= std_logic_vector(rotate_right(unsigned(k_3), 3));
-- tmp = tmp xor k[1]
op_xor_0 <= (op_3_s xor k_1);
-- tmp >> 1
op_1_s <= std_logic_vector(rotate_right(unsigned(op_xor_0), 1));
-- Original NSA specification lists ~K[0] ^ 3 but this can be rewritten to K[0] ^ ((1 << word_size)-4) where the latter can be stored as a constant for speed
subkey_out <= k_0 when (to_integer(unsigned(r)) < 4) else (op_1_s xor op_xor_0 xor k_0 xor seqC);
end Behavioral; |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity resolve_tri_state_logic is
end entity resolve_tri_state_logic;
architecture test of resolve_tri_state_logic is
-- code from book (in text)
type tri_state_logic is ('0', '1', 'Z');
type tri_state_logic_array is array (integer range <>) of tri_state_logic;
-- end code from book
-- code from book
function resolve_tri_state_logic ( values : in tri_state_logic_array )
return tri_state_logic is
variable result : tri_state_logic := 'Z';
begin
for index in values'range loop
if values(index) /= 'Z' then
result := values(index);
end if;
end loop;
return result;
end function resolve_tri_state_logic;
-- end code from book
-- code from book (in text)
signal s1 : resolve_tri_state_logic tri_state_logic;
subtype resolved_logic is resolve_tri_state_logic tri_state_logic;
signal s2, s3 : resolved_logic;
-- end code from book
begin
source_1 : s1 <= 'Z',
'0' after 10 ns,
'Z' after 20 ns,
'1' after 30 ns,
'Z' after 40 ns,
'1' after 200 ns,
'Z' after 220 ns;
source_2 : s1 <= 'Z',
'0' after 110 ns,
'Z' after 120 ns,
'1' after 130 ns,
'Z' after 140 ns,
'1' after 200 ns,
'0' after 210 ns,
'Z' after 220 ns;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity resolve_tri_state_logic is
end entity resolve_tri_state_logic;
architecture test of resolve_tri_state_logic is
-- code from book (in text)
type tri_state_logic is ('0', '1', 'Z');
type tri_state_logic_array is array (integer range <>) of tri_state_logic;
-- end code from book
-- code from book
function resolve_tri_state_logic ( values : in tri_state_logic_array )
return tri_state_logic is
variable result : tri_state_logic := 'Z';
begin
for index in values'range loop
if values(index) /= 'Z' then
result := values(index);
end if;
end loop;
return result;
end function resolve_tri_state_logic;
-- end code from book
-- code from book (in text)
signal s1 : resolve_tri_state_logic tri_state_logic;
subtype resolved_logic is resolve_tri_state_logic tri_state_logic;
signal s2, s3 : resolved_logic;
-- end code from book
begin
source_1 : s1 <= 'Z',
'0' after 10 ns,
'Z' after 20 ns,
'1' after 30 ns,
'Z' after 40 ns,
'1' after 200 ns,
'Z' after 220 ns;
source_2 : s1 <= 'Z',
'0' after 110 ns,
'Z' after 120 ns,
'1' after 130 ns,
'Z' after 140 ns,
'1' after 200 ns,
'0' after 210 ns,
'Z' after 220 ns;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity resolve_tri_state_logic is
end entity resolve_tri_state_logic;
architecture test of resolve_tri_state_logic is
-- code from book (in text)
type tri_state_logic is ('0', '1', 'Z');
type tri_state_logic_array is array (integer range <>) of tri_state_logic;
-- end code from book
-- code from book
function resolve_tri_state_logic ( values : in tri_state_logic_array )
return tri_state_logic is
variable result : tri_state_logic := 'Z';
begin
for index in values'range loop
if values(index) /= 'Z' then
result := values(index);
end if;
end loop;
return result;
end function resolve_tri_state_logic;
-- end code from book
-- code from book (in text)
signal s1 : resolve_tri_state_logic tri_state_logic;
subtype resolved_logic is resolve_tri_state_logic tri_state_logic;
signal s2, s3 : resolved_logic;
-- end code from book
begin
source_1 : s1 <= 'Z',
'0' after 10 ns,
'Z' after 20 ns,
'1' after 30 ns,
'Z' after 40 ns,
'1' after 200 ns,
'Z' after 220 ns;
source_2 : s1 <= 'Z',
'0' after 110 ns,
'Z' after 120 ns,
'1' after 130 ns,
'Z' after 140 ns,
'1' after 200 ns,
'0' after 210 ns,
'Z' after 220 ns;
end architecture test;
|
-- A very basic sanity test of wait statements
entity wait1 is
end entity;
architecture test of wait1 is
begin
process is
begin
assert now = 0 ns;
wait_1: wait for 1 ns;
assert now = 1 ns;
wait for 1 fs;
assert now = 1000001 fs;
end_wait: wait;
end process;
end architecture;
|
-- A very basic sanity test of wait statements
entity wait1 is
end entity;
architecture test of wait1 is
begin
process is
begin
assert now = 0 ns;
wait_1: wait for 1 ns;
assert now = 1 ns;
wait for 1 fs;
assert now = 1000001 fs;
end_wait: wait;
end process;
end architecture;
|
-- A very basic sanity test of wait statements
entity wait1 is
end entity;
architecture test of wait1 is
begin
process is
begin
assert now = 0 ns;
wait_1: wait for 1 ns;
assert now = 1 ns;
wait for 1 fs;
assert now = 1000001 fs;
end_wait: wait;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1583.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p02n01i01583ent IS
END c08s11b00x00p02n01i01583ent;
ARCHITECTURE c08s11b00x00p02n01i01583arch OF c08s11b00x00p02n01i01583ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
while k < 10 loop
exit ;
k := 5;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c08s11b00x00p02n01i01583"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s11b00x00p02n01i01583 - The when clause in the exit statement is optional"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p02n01i01583arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1583.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p02n01i01583ent IS
END c08s11b00x00p02n01i01583ent;
ARCHITECTURE c08s11b00x00p02n01i01583arch OF c08s11b00x00p02n01i01583ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
while k < 10 loop
exit ;
k := 5;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c08s11b00x00p02n01i01583"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s11b00x00p02n01i01583 - The when clause in the exit statement is optional"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p02n01i01583arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1583.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p02n01i01583ent IS
END c08s11b00x00p02n01i01583ent;
ARCHITECTURE c08s11b00x00p02n01i01583arch OF c08s11b00x00p02n01i01583ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
while k < 10 loop
exit ;
k := 5;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c08s11b00x00p02n01i01583"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s11b00x00p02n01i01583 - The when clause in the exit statement is optional"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p02n01i01583arch;
|
-- --------------------------------------------------------------------
-- Title : Standard VHDL Synthesis Packages (1076.3, NUMERIC_STD_UNSIGNED)
--
-- This package overloaded the arithmetic operaters for
-- "STD_ULOGIC_VECTOR", and treats this vector like an
-- "UNSIGNED" from "numeric_std".
--
-- This is the updated (proposed) new package to be
-- balloted in January.
--
-- New subprograms are at the end of the package header
-- and the package body. These are to be revised, ID's
-- assigned, and voted into the ballot version.
--
-- Other changes will be noted here.
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package NUMERIC_STD_UNSIGNED is
-- begin LCS-2006-141
-- Replace all subsequent occurrences of STD_LOGIC_VECTOR
-- with STD_ULOGIC_ECTOR.
-- end LCS-2006-141
-- Id: A.3
function "+" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.3R
function "+"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.3 where R is a one bit STD_ULOGIC_VECTOR
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.5
function "+" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
--============================================================================
-- Id: A.9
function "-" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.9R
function "-"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.11
function "-" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.17
function "*" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.23
function "/" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.29
function "rem" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.35
function "mod" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- begin LCS-2006-129
--============================================================================
-- Id: A.39
function find_leftmost (ARG : STD_ULOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.41
function find_rightmost (ARG : STD_ULOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- end LCS-2006-129
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.5
function ">" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.11
function "<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.17
function "<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.23
function ">=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.29
function "=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.35
function "/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.37
function MINIMUM (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the lesser of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.39
function MINIMUM (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the lesser of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.41
function MINIMUM (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the lesser of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.43
function MAXIMUM (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the greater of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.45
function MAXIMUM (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the greater of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.47
function MAXIMUM (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the greater of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.49
function \?>\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.51
function \?>\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.53
function \?>\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.55
function \?<\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.57
function \?<\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.59
function \?<\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.61
function \?<=\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.63
function \?<=\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.65
function \?<=\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.67
function \?>=\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.69
function \?>=\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.71
function \?>=\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.73
function \?=\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.75
function \?=\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.77
function \?=\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.79
function \?/=\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.81
function \?/=\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.83
function \?/=\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : STD_ULOGIC_VECTOR; COUNT : INTEGER) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : STD_ULOGIC_VECTOR; COUNT : INTEGER) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_ULOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
-- size_res versions of these functions (Bugzilla 165)
function RESIZE (ARG, SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_ULOGIC_VECTOR) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.3
function To_StdLogicVector (ARG, SIZE : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified SIZE.
-- begin LCS-2006-130
alias To_Std_Logic_Vector is
To_StdLogicVector[NATURAL, NATURAL return STD_LOGIC_VECTOR];
alias To_SLV is
To_StdLogicVector[NATURAL, NATURAL return STD_LOGIC_VECTOR];
-- size_res versions of these functions (Bugzilla 165)
function To_StdLogicVector (ARG : NATURAL; SIZE_RES : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
-- end LCS-2006-130
-- Id: D.5
function To_StdULogicVector (ARG, SIZE : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified SIZE.
-- size_res versions of these functions (Bugzilla 165)
function To_StdULogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
-- begin LCS-2006-130
alias To_Std_ULogic_Vector is
To_StdULogicVector[NATURAL, NATURAL return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[NATURAL, NATURAL return STD_ULOGIC_VECTOR];
alias To_Std_ULogic_Vector is
To_StdULogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_ULOGIC_VECTOR];
-- end LCS-2006-130
--============================================================================
-- Translation Functions
--============================================================================
-- Id: T.1
function TO_01 (S : STD_ULOGIC_VECTOR; XMAP : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
-- begin LCS-2006-141
-- Replace all subsequent occurrences of STD_LOGIC_VECTOR
-- with STD_ULOGIC_ECTOR.
-- end LCS-2006-141
-- Id: A.3
function "+" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.3R
function "+"(L : STD_LOGIC_VECTOR; R : STD_ULOGIC) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.3 where R is a one bit STD_LOGIC_VECTOR
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.5
function "+" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
--============================================================================
-- Id: A.9
function "-" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.9R
function "-"(L : STD_LOGIC_VECTOR; R : STD_ULOGIC) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.11
function "-" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.17
function "*" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.23
function "/" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.29
function "rem" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.35
function "mod" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- begin LCS-2006-129
--============================================================================
-- Id: A.39
function find_leftmost (ARG : STD_LOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.41
function find_rightmost (ARG : STD_LOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- end LCS-2006-129
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.5
function ">" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.11
function "<" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.17
function "<=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.23
function ">=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.29
function "=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.35
function "/=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.37
function MINIMUM (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the lesser of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.39
function MINIMUM (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the lesser of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.41
function MINIMUM (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the lesser of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.43
function MAXIMUM (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the greater of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.45
function MAXIMUM (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the greater of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.47
function MAXIMUM (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the greater of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.49
function \?>\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.51
function \?>\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.53
function \?>\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.55
function \?<\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.57
function \?<\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.59
function \?<\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.61
function \?<=\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.63
function \?<=\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.65
function \?<=\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.67
function \?>=\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.69
function \?>=\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.71
function \?>=\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.73
function \?=\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.75
function \?=\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.77
function \?=\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.79
function \?/=\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.81
function \?/=\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.83
function \?/=\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)
return STD_LOGIC_VECTOR;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : STD_LOGIC_VECTOR; COUNT : INTEGER) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : STD_LOGIC_VECTOR; COUNT : INTEGER) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_LOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
-- size_res versions of these functions (Bugzilla 165)
function RESIZE (ARG, SIZE_RES : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_LOGIC_VECTOR) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- end LCS-2006-130
--============================================================================
-- Translation Functions
--============================================================================
-- Id: T.1
function TO_01 (S : STD_LOGIC_VECTOR; XMAP : STD_ULOGIC := '0')
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
end package NUMERIC_STD_UNSIGNED;
-------------------------------------------------------------------------------
-- Proposed package body for the VHDL-200x-FT NUMERIC_STD_UNSIGNED package
-- This package body supplies a recommended implementation of these functions
-- Version: $Revision: 1.4 $
-- Date: $Date: 2009/08/26 19:56:30 $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use work.numeric_std_additions.all;
package body NUMERIC_STD_UNSIGNED is
-- Id: A.3
function "+" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + UNSIGNED(R));
end function "+";
-- Id: A.3R
function "+"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
-- Id: A.5
function "+" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
--============================================================================
-- Id: A.9
function "-" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - UNSIGNED(R));
end function "-";
-- Id: A.9R
function "-"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
-- Id: A.11
function "-" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
--============================================================================
-- Id: A.15
function "*" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) * UNSIGNED(R));
end function "*";
-- Id: A.17
function "*" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) * R);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L * UNSIGNED(R));
end function "*";
--============================================================================
-- Id: A.21
function "/" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) / UNSIGNED(R));
end function "/";
-- Id: A.23
function "/" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) / R);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L / UNSIGNED(R));
end function "/";
--============================================================================
-- Id: A.27
function "rem" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) rem UNSIGNED(R));
end function "rem";
-- Id: A.29
function "rem" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) rem R);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L rem UNSIGNED(R));
end function "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) mod UNSIGNED(R));
end function "mod";
-- Id: A.35
function "mod" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) mod R);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L mod UNSIGNED(R));
end function "mod";
-- begin LCS-2006-129
--============================================================================
-- Id: A.39
function find_leftmost (ARG: STD_ULOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_leftmost(UNSIGNED(ARG), Y);
end function find_leftmost;
-- Id: A.41
function find_rightmost (ARG: STD_ULOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_rightmost(UNSIGNED(ARG), Y);
end function find_rightmost;
-- end LCS-2006-129
--============================================================================
-- Id: C.1
function ">" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) > UNSIGNED(R);
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L > UNSIGNED(R);
end function ">";
-- Id: C.5
function ">" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) > R;
end function ">";
--============================================================================
-- Id: C.7
function "<" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) < UNSIGNED(R);
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L < UNSIGNED(R);
end function "<";
-- Id: C.11
function "<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) < R;
end function "<";
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) <= UNSIGNED(R);
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L <= UNSIGNED(R);
end function "<=";
-- Id: C.17
function "<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) <= R;
end function "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) >= UNSIGNED(R);
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L >= UNSIGNED(R);
end function ">=";
-- Id: C.23
function ">=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) >= R;
end function ">=";
--============================================================================
-- Id: C.25
function "=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end function "=";
-- Id: C.29
function "=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end function "=";
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end function "/=";
-- Id: C.35
function "/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end function "/=";
--============================================================================
-- Id: C.37
function MINIMUM (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MINIMUM;
-- Id: C.39
function MINIMUM (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(L, UNSIGNED(R)));
end function MINIMUM;
-- Id: C.41
function MINIMUM (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(UNSIGNED(L), R));
end function MINIMUM;
--============================================================================
-- Id: C.43
function MAXIMUM (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.45
function MAXIMUM (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(L, UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(UNSIGNED(L), R));
end function MAXIMUM;
--============================================================================
-- Id: C.49
function \?>\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>\ (UNSIGNED(L), UNSIGNED(R));
end function \?>\;
-- Id: C.51
function \?>\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>\ (L, UNSIGNED(R));
end function \?>\;
-- Id: C.53
function \?>\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?>\ (UNSIGNED(L), R);
end function \?>\;
--============================================================================
-- Id: C.55
function \?<\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<\ (UNSIGNED(L), UNSIGNED(R));
end function \?<\;
-- Id: C.57
function \?<\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<\ (L, UNSIGNED(R));
end function \?<\;
-- Id: C.59
function \?<\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?<\ (UNSIGNED(L), R);
end function \?<\;
--============================================================================
-- Id: C.61
function \?<=\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<=\ (UNSIGNED(L), UNSIGNED(R));
end function \?<=\;
-- Id: C.63
function \?<=\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<=\ (L, UNSIGNED(R));
end function \?<=\;
-- Id: C.65
function \?<=\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?<=\ (UNSIGNED(L), R);
end function \?<=\;
--============================================================================
-- Id: C.67
function \?>=\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>=\ (UNSIGNED(L), UNSIGNED(R));
end function \?>=\;
-- Id: C.69
function \?>=\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>=\ (L, UNSIGNED(R));
end function \?>=\;
-- Id: C.71
function \?>=\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?>=\ (UNSIGNED(L), R);
end function \?>=\;
--============================================================================
-- Id: C.73
function \?=\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?=\ (UNSIGNED(L), UNSIGNED(R));
end function \?=\;
-- Id: C.75
function \?=\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?=\ (L, UNSIGNED(R));
end function \?=\;
-- Id: C.77
function \?=\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?=\ (UNSIGNED(L), R);
end function \?=\;
--============================================================================
-- Id: C.79
function \?/=\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?/=\ (UNSIGNED(L), UNSIGNED(R));
end function \?/=\;
-- Id: C.81
function \?/=\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?/=\ (L, UNSIGNED(R));
end function \?/=\;
-- Id: C.83
function \?/=\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?/=\ (UNSIGNED(L), R);
end function \?/=\;
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is
begin
return std_ulogic_vector (SHIFT_LEFT(unsigned(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is
begin
return std_ulogic_vector (SHIFT_RIGHT(unsigned(ARG), COUNT));
end function SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is
begin
return std_ulogic_vector (ROTATE_LEFT(unsigned(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is
begin
return std_ulogic_vector (ROTATE_RIGHT(unsigned(ARG), COUNT));
end function ROTATE_RIGHT;
--============================================================================
-- Id: S.17
function "sla" (ARG: STD_ULOGIC_VECTOR; COUNT: INTEGER) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(ARG) sla COUNT);
end function "sla";
-- Id: S.19
function "sra" (ARG: STD_ULOGIC_VECTOR; COUNT: INTEGER) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(ARG) sra COUNT);
end function "sra";
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_ULOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => NEW_SIZE));
end function RESIZE;
function RESIZE (ARG, SIZE_RES : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => SIZE_RES'length));
end function RESIZE;
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_ULOGIC_VECTOR) return NATURAL is
begin
return TO_INTEGER(UNSIGNED(ARG));
end function TO_INTEGER;
-- Id: D.3
function To_StdLogicVector (ARG, SIZE : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE));
end function To_StdLogicVector;
function To_StdLogicVector (ARG : NATURAL; SIZE_RES : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE_RES'length));
end function To_StdLogicVector;
-- Id: D.5
function To_StdULogicVector (ARG, SIZE : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE));
end function To_StdULogicVector;
function To_StdULogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE_RES'length));
end function To_StdULogicVector;
--============================================================================
-- function TO_01 is used to convert vectors to the
-- correct form for exported functions,
-- and to report if there is an element which
-- is not in (0, 1, H, L).
-- Id: T.1
function TO_01 (S : STD_ULOGIC_VECTOR; XMAP : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (
TO_01 (S => UNSIGNED(S),
XMAP => XMAP));
end function TO_01;
-- Id: A.3
function "+" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) + UNSIGNED(R));
end function "+";
-- Id: A.3R
function "+"(L : STD_LOGIC_VECTOR; R : STD_ULOGIC) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
-- Id: A.5
function "+" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
--============================================================================
-- Id: A.9
function "-" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) - UNSIGNED(R));
end function "-";
-- Id: A.9R
function "-"(L : STD_LOGIC_VECTOR; R : STD_ULOGIC) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
-- Id: A.11
function "-" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
--============================================================================
-- Id: A.15
function "*" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) * UNSIGNED(R));
end function "*";
-- Id: A.17
function "*" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) * R);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L * UNSIGNED(R));
end function "*";
--============================================================================
-- Id: A.21
function "/" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) / UNSIGNED(R));
end function "/";
-- Id: A.23
function "/" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) / R);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L / UNSIGNED(R));
end function "/";
--============================================================================
-- Id: A.27
function "rem" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) rem UNSIGNED(R));
end function "rem";
-- Id: A.29
function "rem" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) rem R);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L rem UNSIGNED(R));
end function "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) mod UNSIGNED(R));
end function "mod";
-- Id: A.35
function "mod" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) mod R);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L mod UNSIGNED(R));
end function "mod";
-- begin LCS-2006-129
--============================================================================
-- Id: A.39
function find_leftmost (ARG: STD_LOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_leftmost(UNSIGNED(ARG), Y);
end function find_leftmost;
-- Id: A.41
function find_rightmost (ARG: STD_LOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_rightmost(UNSIGNED(ARG), Y);
end function find_rightmost;
-- end LCS-2006-129
--============================================================================
-- Id: C.1
function ">" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) > UNSIGNED(R);
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L > UNSIGNED(R);
end function ">";
-- Id: C.5
function ">" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) > R;
end function ">";
--============================================================================
-- Id: C.7
function "<" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) < UNSIGNED(R);
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L < UNSIGNED(R);
end function "<";
-- Id: C.11
function "<" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) < R;
end function "<";
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) <= UNSIGNED(R);
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L <= UNSIGNED(R);
end function "<=";
-- Id: C.17
function "<=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) <= R;
end function "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) >= UNSIGNED(R);
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L >= UNSIGNED(R);
end function ">=";
-- Id: C.23
function ">=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) >= R;
end function ">=";
--============================================================================
-- Id: C.25
function "=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end function "=";
-- Id: C.29
function "=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end function "=";
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end function "/=";
-- Id: C.35
function "/=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end function "/=";
--============================================================================
-- Id: C.37
function MINIMUM (L, R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MINIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MINIMUM;
-- Id: C.39
function MINIMUM (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MINIMUM(L, UNSIGNED(R)));
end function MINIMUM;
-- Id: C.41
function MINIMUM (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MINIMUM(UNSIGNED(L), R));
end function MINIMUM;
--============================================================================
-- Id: C.43
function MAXIMUM (L, R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MAXIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.45
function MAXIMUM (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MAXIMUM(L, UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MAXIMUM(UNSIGNED(L), R));
end function MAXIMUM;
--============================================================================
-- Id: C.49
function \?>\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>\ (UNSIGNED(L), UNSIGNED(R));
end function \?>\;
-- Id: C.51
function \?>\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>\ (L, UNSIGNED(R));
end function \?>\;
-- Id: C.53
function \?>\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?>\ (UNSIGNED(L), R);
end function \?>\;
--============================================================================
-- Id: C.55
function \?<\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<\ (UNSIGNED(L), UNSIGNED(R));
end function \?<\;
-- Id: C.57
function \?<\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<\ (L, UNSIGNED(R));
end function \?<\;
-- Id: C.59
function \?<\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?<\ (UNSIGNED(L), R);
end function \?<\;
--============================================================================
-- Id: C.61
function \?<=\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<=\ (UNSIGNED(L), UNSIGNED(R));
end function \?<=\;
-- Id: C.63
function \?<=\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<=\ (L, UNSIGNED(R));
end function \?<=\;
-- Id: C.65
function \?<=\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?<=\ (UNSIGNED(L), R);
end function \?<=\;
--============================================================================
-- Id: C.67
function \?>=\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>=\ (UNSIGNED(L), UNSIGNED(R));
end function \?>=\;
-- Id: C.69
function \?>=\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>=\ (L, UNSIGNED(R));
end function \?>=\;
-- Id: C.71
function \?>=\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?>=\ (UNSIGNED(L), R);
end function \?>=\;
--============================================================================
-- Id: C.73
function \?=\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?=\ (UNSIGNED(L), UNSIGNED(R));
end function \?=\;
-- Id: C.75
function \?=\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?=\ (L, UNSIGNED(R));
end function \?=\;
-- Id: C.77
function \?=\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?=\ (UNSIGNED(L), R);
end function \?=\;
--============================================================================
-- Id: C.79
function \?/=\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?/=\ (UNSIGNED(L), UNSIGNED(R));
end function \?/=\;
-- Id: C.81
function \?/=\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?/=\ (L, UNSIGNED(R));
end function \?/=\;
-- Id: C.83
function \?/=\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?/=\ (UNSIGNED(L), R);
end function \?/=\;
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (SHIFT_LEFT(unsigned(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (SHIFT_RIGHT(unsigned(ARG), COUNT));
end function SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (ROTATE_LEFT(unsigned(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (ROTATE_RIGHT(unsigned(ARG), COUNT));
end function ROTATE_RIGHT;
--============================================================================
-- Id: S.17
function "sla" (ARG: STD_LOGIC_VECTOR; COUNT: INTEGER) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(ARG) sla COUNT);
end function "sla";
-- Id: S.19
function "sra" (ARG: STD_LOGIC_VECTOR; COUNT: INTEGER) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(ARG) sra COUNT);
end function "sra";
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_LOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => NEW_SIZE));
end function RESIZE;
function RESIZE (ARG, SIZE_RES : STD_LOGIC_VECTOR)
return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => SIZE_RES'length));
end function RESIZE;
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_LOGIC_VECTOR) return NATURAL is
begin
return TO_INTEGER(UNSIGNED(ARG));
end function TO_INTEGER;
--============================================================================
-- function TO_01 is used to convert vectors to the
-- correct form for exported functions,
-- and to report if there is an element which
-- is not in (0, 1, H, L).
-- Id: T.1
function TO_01 (S : STD_LOGIC_VECTOR; XMAP : STD_ULOGIC := '0')
return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (
TO_01 (S => UNSIGNED(S),
XMAP => XMAP));
end function TO_01;
end package body NUMERIC_STD_UNSIGNED;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2619.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02619ent IS
END c13s03b01x00p02n01i02619ent;
ARCHITECTURE c13s03b01x00p02n01i02619arch OF c13s03b01x00p02n01i02619ent IS
BEGIN
TESTING: PROCESS
variable k+k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02619 - Identifier can not contain '+'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02619arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2619.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02619ent IS
END c13s03b01x00p02n01i02619ent;
ARCHITECTURE c13s03b01x00p02n01i02619arch OF c13s03b01x00p02n01i02619ent IS
BEGIN
TESTING: PROCESS
variable k+k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02619 - Identifier can not contain '+'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02619arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2619.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02619ent IS
END c13s03b01x00p02n01i02619ent;
ARCHITECTURE c13s03b01x00p02n01i02619arch OF c13s03b01x00p02n01i02619ent IS
BEGIN
TESTING: PROCESS
variable k+k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02619 - Identifier can not contain '+'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02619arch;
|
----------------------------------------------------------------
-- uut:
-- recode.vhd
-- circbuf_fast.vhd
-- description:
-- simple test_bench to verify recode behavior in normal conditions
-- with a fifo just before
-- and a fifo just after
-- expected result:
-- recode should be configured in weight configuration mode
-- in normal mode, recode should act as:
-- output = (input < 0) ? 0 : input + cst[addr]
-- recode should correctly interact with input and output fifos
----------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
Library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use unimacro.Vcomponents.all;
use ieee.numeric_std.all;
-- entity declaration for your testbench.Dont declare any ports here
ENTITY test_fifo_recode_fifo IS
END test_fifo_recode_fifo;
ARCHITECTURE behavior OF test_fifo_recode_fifo IS
-- add component under test
-- Parameters for the neurons
constant WDATA : natural := 32;
constant WOUT : natural := WDATA;
constant WWEIGHT : natural := 16;
constant WACCU : natural := 32;
-- Parameters for frame and number of neurons
constant FSIZE : natural := 4;
constant NBNEU : natural := 4;
constant DATAW : natural := 32;
constant DEPTH : natural := 8;
constant CNTW : natural := 16;
component recode
generic(
WDATA : natural := WDATA;
WWEIGHT : natural := WWEIGHT;
WOUT : natural := WOUT;
FSIZE : natural := NBNEU -- warning, this is NB_NEU
);
port(
clk : in std_logic;
-- Ports for address control
addr_clear : in std_logic;
-- Ports for Write into memory
write_mode : in std_logic;
write_data : in std_logic_vector(WDATA - 1 downto 0);
write_enable : in std_logic;
write_ready : out std_logic;
-- The user-specified number of neurons
user_nbneu : in std_logic_vector(15 downto 0);
-- Data input
data_in : in std_logic_vector(WDATA-1 downto 0);
data_in_valid : in std_logic;
data_in_ready : out std_logic;
-- Data output
data_out : out std_logic_vector(WOUT-1 downto 0);
data_out_valid : out std_logic;
-- The output data enters a FIFO. This indicates the available room.
out_fifo_room : in std_logic_vector(15 downto 0)
);
end component;
component circbuf_fast is
generic (
DATAW : natural := DATAW;
DEPTH : natural := DEPTH;
CNTW : natural := CNTW
);
port (
reset : in std_logic;
clk : in std_logic;
fifo_in_data : in std_logic_vector(DATAW-1 downto 0);
fifo_in_rdy : out std_logic;
fifo_in_ack : in std_logic;
fifo_in_cnt : out std_logic_vector(CNTW-1 downto 0);
fifo_out_data : out std_logic_vector(DATAW-1 downto 0);
fifo_out_rdy : out std_logic;
fifo_out_ack : in std_logic;
fifo_out_cnt : out std_logic_vector(CNTW-1 downto 0)
);
end component;
-- clock period definition
constant clk_period : time := 1 ns;
signal clear : std_logic := '0';
signal clk : std_logic := '0';
-- recode signals
signal addr_clear : std_logic;
signal write_mode : std_logic;
signal write_data : std_logic_vector(WDATA - 1 downto 0);
signal write_enable : std_logic;
signal write_ready : std_logic;
signal user_nbneu : std_logic_vector(15 downto 0);
signal data_in : std_logic_vector(WDATA-1 downto 0);
signal data_in_valid : std_logic;
signal data_in_ready : std_logic;
signal data_out : std_logic_vector(WOUT-1 downto 0);
signal data_out_valid : std_logic;
signal out_fifo_room : std_logic_vector(15 downto 0);
-- for the fifo_1
signal fifo_in_data_1 : std_logic_vector(DATAW-1 downto 0);
signal fifo_in_rdy_1 : std_logic;
signal fifo_in_ack_1 : std_logic;
signal fifo_in_cnt_1 : std_logic_vector(CNTW-1 downto 0);
signal fifo_out_data_1 : std_logic_vector(DATAW-1 downto 0);
signal fifo_out_rdy_1 : std_logic;
signal fifo_out_ack_1 : std_logic;
signal fifo_out_cnt_1 : std_logic_vector(CNTW-1 downto 0);
-- for the fifo_2
signal fifo_in_data_2 : std_logic_vector(DATAW-1 downto 0);
signal fifo_in_rdy_2 : std_logic;
signal fifo_in_ack_2 : std_logic;
signal fifo_in_cnt_2 : std_logic_vector(CNTW-1 downto 0);
signal fifo_out_data_2 : std_logic_vector(DATAW-1 downto 0);
signal fifo_out_rdy_2 : std_logic;
signal fifo_out_ack_2 : std_logic;
signal fifo_out_cnt_2 : std_logic_vector(CNTW-1 downto 0);
begin
fifo_1: circbuf_fast
port map (
reset => clear,
clk => clk,
fifo_in_data => fifo_in_data_1,
fifo_in_rdy => fifo_in_rdy_1,
fifo_in_ack => fifo_in_ack_1,
fifo_in_cnt => fifo_in_cnt_1,
fifo_out_data => fifo_out_data_1,
fifo_out_rdy => fifo_out_rdy_1,
fifo_out_ack => fifo_out_ack_1,
fifo_out_cnt => fifo_out_cnt_1
);
fifo_2: circbuf_fast
port map (
reset => clear,
clk => clk,
fifo_in_data => fifo_in_data_2,
fifo_in_rdy => fifo_in_rdy_2,
fifo_in_ack => fifo_in_ack_2,
fifo_in_cnt => fifo_in_cnt_2,
fifo_out_data => fifo_out_data_2,
fifo_out_rdy => fifo_out_rdy_2,
fifo_out_ack => fifo_out_ack_2,
fifo_out_cnt => fifo_out_cnt_2
);
recode_1 : recode
port map (
clk => clk,
addr_clear => addr_clear,
write_mode => write_mode,
write_data => write_data,
write_enable => write_enable,
write_ready => write_ready,
user_nbneu => user_nbneu,
data_in => data_in,
data_in_valid => data_in_valid,
data_in_ready => data_in_ready,
data_out => data_out,
data_out_valid => data_out_valid,
out_fifo_room => out_fifo_room
);
write_data <= fifo_out_data_1;
write_enable <= fifo_out_rdy_1;
data_in <= fifo_out_data_1;
data_in_valid <= fifo_out_rdy_1;
--data_in_ready <= fifo_out_ack;
fifo_out_ack_1 <= data_in_ready or write_ready;
fifo_in_ack_2 <= data_out_valid;
fifo_in_data_2 <= data_out;
out_fifo_room <= fifo_in_cnt_2;
-- Clock process definitions( clock with 50% duty cycle is generated here.
clk_process : process
begin
clk <= '1';
wait for clk_period/2; --for 0.5 ns signal is '1'.
clk <= '0';
wait for clk_period/2; --for next 0.5 ns signal is '0'.
end process;
stim_proc: process
variable counter : integer := 0;
variable neurons : integer := 0;
begin
-------------------------------
-- TEST CHARGEMENT DES POIDS --
-------------------------------
-- reset
clear <= '1';
fifo_in_data_1 <= std_logic_vector(to_unsigned(0, 32));
fifo_in_ack_1 <= '0';
wait for 3*clk_period;
clear <= '0';
write_mode <= '1'; -- load weights
-- load data into the fifo
fifo_in_data_1 <= std_logic_vector(to_unsigned(3, 32));
fifo_in_ack_1 <= '1';
--while neurons < NBNEU loop
counter := 0;
neurons := neurons + 1;
wait for clk_period;
wait for clk_period;
counter := 0;
fifo_in_data_1 <= std_logic_vector(to_signed(4, 32));
fifo_in_ack_1 <= '1';
neurons := neurons +1;
wait for clk_period;
counter := 0;
fifo_in_data_1 <= std_logic_vector(to_signed(5, 32));
fifo_in_ack_1 <= '1';
neurons := neurons +1;
wait for clk_period;
counter := 0;
fifo_in_data_1 <= std_logic_vector(to_signed(1, 32));
fifo_in_ack_1 <= '1';
neurons := neurons +1;
wait for clk_period;
fifo_in_data_1 <= std_logic_vector(to_signed(10, 32));
fifo_in_ack_1 <= '0';
--end loop;
wait for clk_period;
wait for clk_period;
wait for clk_period;
wait for clk_period;
wait for clk_period;
write_mode <= '0'; -- accu add
fifo_in_ack_1 <= '1';
wait for clk_period;
----------------------------
-- TEST MODE ACCUMULATION --
----------------------------
write_mode <= '0'; -- accu add
fifo_in_data_1 <= std_logic_vector(to_unsigned(64, 32));
counter := 0;
while (counter < FSIZE) loop
wait for clk_period;
fifo_in_data_1 <= std_logic_vector(to_unsigned(128, 32));
counter := counter + 1;
wait for clk_period;
fifo_in_data_1 <= std_logic_vector(to_unsigned(64, 32));
end loop;
wait;
end process;
END;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity resistor is
port ( terminal node1, node2 : electrical );
end entity resistor;
architecture ideal of resistor is
constant R : real := 1000.0;
quantity v across i through node1 to node2;
begin
v == i * R;
end architecture ideal;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity resistor is
port ( terminal node1, node2 : electrical );
end entity resistor;
architecture ideal of resistor is
constant R : real := 1000.0;
quantity v across i through node1 to node2;
begin
v == i * R;
end architecture ideal;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity resistor is
port ( terminal node1, node2 : electrical );
end entity resistor;
architecture ideal of resistor is
constant R : real := 1000.0;
quantity v across i through node1 to node2;
begin
v == i * R;
end architecture ideal;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_aa
--
-- Generated
-- by: wig
-- on: Tue Nov 29 13:29:43 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_aa-e.vhd,v 1.3 2005/11/30 14:04:01 wig Exp $
-- $Date: 2005/11/30 14:04:01 $
-- $Log: ent_aa-e.vhd,v $
-- Revision 1.3 2005/11/30 14:04:01 wig
-- Updated testcase references
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.42 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_aa
--
entity ent_aa is
-- Generics:
-- No Generated Generics for Entity ent_aa
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_aa
port_aa_1 : out std_ulogic; -- Use internally test1
port_aa_2 : out std_ulogic; -- Use internally test2, no port generated __I_AUTO_REDUCED_BUS2SIGNAL
port_aa_3 : out std_ulogic; -- Interhierachy link, will create p_mix_sig_3_go
port_aa_4 : in std_ulogic; -- Interhierachy link, will create p_mix_sig_4_gi
port_aa_5 : out std_ulogic_vector(3 downto 0); -- Bus, single bits go to outside
port_aa_6 : out std_ulogic_vector(3 downto 0); -- Conflicting definition
sig_07 : out std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : out std_ulogic_vector(8 downto 2); -- VHDL intermediate needed (port name)
sig_13 : out std_ulogic_vector(4 downto 0) -- Create internal signal name
-- End of Generated Port for Entity ent_aa
);
end ent_aa;
--
-- End of Generated Entity ent_aa
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- Title : CLock
-- Project :
-------------------------------------------------------------------------------
-- File : regs.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-03-13
-- Last update: 2018-04-22
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Register interface to the EPC bus
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-03-13 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
--
-- Address range: 0x8060_0000 - 0x8060_FFFF
-- | 3 | 2 | 1 | 0 |
-- |1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|
--
-- 0x8060_0000 | GIT Abbreviated Commit Hash |
--
-- 0x8060_0004 | Hr 10 | Hr 1 | Min 10| Min 1 | Build |
--
-- 0x8060_0008 | Year | Year | Year | Year | Mon 10| Mon 1 | Day 10| Day 1 |
--
--
-- -----------------------------------------------------------------------------
-- | 3 | 2 | 1 | 0 |
-- |1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|
--
-- 0x8060_0100 | TSC LSB |
--
-- 0x8060_0104 | TSC MSB |
--
-- 0x8060_0108 | TSC LSB @ last second |
--
-- 0x8060_010c | TSC MSB @ last second |
--
-- 0x8060_0110 | 1PPS Phase Error |
--
-- 0x8060_0114 | 1PPS Frequency Error |
--
-- 0x8060_0118 | GPS 1PPS Count |
--
-- 0x8060_011c | 10 h | 1 h | 10 m | 1 m | 10 s | 1 s | 100 ms| 10 ms |
--
-- 0x8060_0120 | | 10 h | 1 h | 10 m | 1 m | 10 s | 1 s |
--
-- 0x8060_0124 | | | | | | | | DAC value |
-- | | | |
-- GPS 3D Fix | | Sync clock
-- | Sync PFD
-- |
-- PFD Status
--
-- 0x8060_0128 | | | |
-- | |
-- GPS PPS IRQ ENA |
-- TSC PPS IRQ ENA
--
-- 0x8060_012c | | | | |
-- | | |
-- PPS IRQ Status GPS PPS IRQ |
-- TSC PPS IRQ
--
-- 0x8060_0130 | | | | |
-- | | |
-- PFD trigger IRQ ENA | |
-- PFD GPS PPS IRQ ENA |
-- PFD TSC PPS IRQ ENA
--
-- 0x8060_0134 | | | | | |
-- | | | |
-- PLL IRQ Status PFD trigger IRQ | |
-- PFD GPS PPS IRQ |
-- PFD TSC PPS IRQ
--
--
-- -----------------------------------------------------------------------------
-- | 3 | 2 | 1 | 0 |
-- |1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|
--
-- 0x8060_0200 | uSPR | | Fan pwm |
--
--
-- -----------------------------------------------------------------------------
-- | 3 | 2 | 1 | 0 |
-- |1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|
--
-- 0x8060_0300 | | disp page | | stat | disp pdm |
--
--
-- -----------------------------------------------------------------------------
-- | 3 | 2 | 1 | 0 |
-- |1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|
--
-- 0x8060_1000 | xor 1 | digit 1 | xor 0 | digit 0 |
--
-- 0x8060_1004 | xor 3 | digit 3 | xor 2 | digit 2 |
--
-- 0x8060_1008 | xor 5 | digit 5 | xor 4 | digit 4 |
--
-- 0x8060_100c | xor 7 | digit 7 | xor 6 | digit 6 |
--
-- 0x8060_1010 | xor 9 | digit 9 | xor 8 | digit 8 |
--
-- 0x8060_1014 | xor 11 | digit 11 | xor 10 | digit 10 |
--
-- 0x8060_1018 | xor 13 | digit 13 | xor 12 | digit 12 |
--
-- 0x8060_101c | xor 15 | digit 15 | xor 14 | digit 14 |
--
-- 0x8060_1020 | xor 17 | digit 17 | xor 16 | digit 16 |
--
-- 0x8060_1024 | xor 19 | digit 19 | xor 18 | digit 18 |
--
-- 0x8060_1028 | xor 21 | digit 21 | xor 20 | digit 20 |
--
-- 0x8060_102c | xor 23 | digit 23 | xor 22 | digit 22 |
--
-- 0x8060_1030 | xor 25 | digit 25 | xor 24 | digit 24 |
--
-- 0x8060_1034 | xor 27 | digit 27 | xor 26 | digit 26 |
--
-- 0x8060_1038 | xor 29 | digit 29 | xor 28 | digit 28 |
--
-- 0x8060_103c | xor 31 | digit 31 | xor 30 | digit 30 |
--
-- 0x8060_1040 | RAM Page 1 |
-- 0x8060_1080 | RAM Page 2 |
-- | ... |
-- 0x8060_1080 | RAM Page 1f |
-- 0x8060_17FC | RAM |
--
-- 0x8060_1800 | lut 3 | lut 2 | lut 1 | lut 0 |
--
-- 0x8060_1804 | lut 7 | lut 6 | lut 5 | lut 4 |
--
-- 0x8060_1808 | lut 11 | lut 10 | lut 9 | lut 8 |
--
-- 0x8060_180c | lut 15 | lut 14 | lut 13 | lut 12 |
--
-- 0x8060_1810 | lut 19 | lut 18 | lut 17 | lut 16 |
--
--
-- 0x8060_187C | lut 127 | lut 126 | lut 125 | lut 124 |
--
-- 0x8060_1880 | RAM |
-- 0x8060_1FFC | RAM |
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.types_pkg.all;
use work.version_pkg.all;
entity regs is
port (
rst_n : in std_logic;
clk : in std_logic;
EPC_INTF_addr : in std_logic_vector(0 to 31);
EPC_INTF_be : in std_logic_vector(0 to 3);
EPC_INTF_burst : in std_logic;
EPC_INTF_cs_n : in std_logic;
EPC_INTF_data_i : out std_logic_vector(0 to 31);
EPC_INTF_data_o : in std_logic_vector(0 to 31);
EPC_INTF_rdy : out std_logic;
EPC_INTF_rnw : in std_logic; -- Write when '0'
-- Time stamp counter
tsc_cnt : in std_logic_vector(63 downto 0);
tsc_cnt1 : in std_logic_vector(63 downto 0);
tsc_read : out std_logic;
-- Time setting
cur_time : in time_ty;
set : out std_logic;
set_time : out time_ty;
-- PLL control
gps_3dfix_d : in std_logic;
gps_1pps_d : in std_logic;
tsc_1pps_d : in std_logic;
pll_trig : in std_logic;
pfd_status : in std_logic;
pdiff_1pps : in std_logic_vector(31 downto 0);
fdiff_1pps : in std_logic_vector(31 downto 0);
tsc_sync : out std_logic;
pfd_resync : out std_logic;
dac_val : out std_logic_vector(15 downto 0);
pps_irq : out std_logic;
pll_irq : out std_logic;
-- Fan us per revolution, percent speed
fan_uspr : in std_logic_vector(19 downto 0);
fan_pct : out std_logic_vector(7 downto 0);
-- Display memory
sram_addr : out std_logic_vector(9 downto 0);
sram_we : out std_logic;
sram_datao : out std_logic_vector(31 downto 0);
sram_datai : in std_logic_vector(31 downto 0);
stat_src : out std_logic_vector(3 downto 0);
disp_page : out std_logic_vector(7 downto 0);
disp_pdm : out std_logic_vector(7 downto 0)
);
end regs;
architecture rtl of regs is
type reg_arr is array (natural range <>) of std_logic_vector(31 downto 0);
signal time_regs : reg_arr(13 downto 0);
signal fan_regs : reg_arr(0 downto 0);
signal disp_regs : reg_arr(0 downto 0);
signal addr : std_logic_vector(31 downto 0);
signal be : std_logic_vector(3 downto 0);
signal data_i : std_logic_vector(31 downto 0);
signal data_o : std_logic_vector(31 downto 0);
signal cs_n_d : std_logic;
signal cs_dp_r : std_logic;
signal cs_dp_w : std_logic;
signal rnw : std_logic;
signal rdy_d : std_logic_vector(2 downto 0);
signal decode : std_logic_vector(3 downto 0);
signal sram : std_logic;
SIGNAL gps_1pps_cnt : std_logic_vector(31 downto 0);
signal ver_regs_mux : std_logic_vector(31 downto 0);
signal time_regs_mux : std_logic_vector(31 downto 0);
signal fan_regs_mux : std_logic_vector(31 downto 0);
signal disp_regs_mux : std_logic_vector(31 downto 0);
signal sram_regs_mux : std_logic_vector(31 downto 0);
begin
-- Big endian to little endian
addr <= EPC_INTF_addr;
be <= EPC_INTF_be;
data_o <= EPC_INTF_data_o;
-- Little endian to big endian
EPC_INTF_data_i <= data_i;
-- Chip select falling edge detect
process (rst_n, clk) is
begin
if (rst_n = '0') then
rnw <= '0';
cs_n_d <= '1';
cs_dp_r <= '0'; -- Chip select read pulse
cs_dp_w <= '0'; -- Chip select write pulse
decode <= (others => '0');
sram <= '0';
elsif (clk'event and clk = '1') then
rnw <= not EPC_INTF_rnw;
cs_n_d <= EPC_INTF_cs_n;
cs_dp_r <= not EPC_INTF_cs_n and cs_n_d and EPC_INTF_rnw;
cs_dp_w <= not EPC_INTF_cs_n and cs_n_d and not EPC_INTF_rnw;
-- First level decode
if (EPC_INTF_cs_n = '0') then
if (addr(12) = '1') then
decode <= (others => '0');
sram <= '1';
else
decode(conv_integer(addr(9 downto 8))) <= '1';
sram <= '0';
end if;
else
decode <= (others => '0');
sram <= '0';
end if;
end if;
end process;
-- Ready signal generator, 4 cycles after delayed chip select
-- Hold ready active until the chip select goes inactive
process (rst_n, clk) is
begin
if (rst_n = '0') then
rdy_d <= (others => '1');
EPC_INTF_rdy <= '0';
elsif (clk'event and clk = '1') then
rdy_d(0) <= cs_dp_r or cs_dp_w;
rdy_d(1) <= rdy_d(0);
rdy_d(2) <= rdy_d(1);
if (EPC_INTF_cs_n = '1') then
EPC_INTF_rdy <= '0';
elsif (rdy_d(2) = '1') then
EPC_INTF_rdy <= '1';
end if;
end if;
end process;
-- Top decode read mux
process (rst_n, clk) is
begin
if (rst_n = '0') then
data_i <= (others => '0');
elsif (clk'event and clk = '1') then
if (sram = '1') then
data_i <= sram_regs_mux;
elsif (decode(0) = '1') then
data_i <= ver_regs_mux;
elsif (decode(1) = '1') then
data_i <= time_regs_mux;
elsif (decode(2) = '1') then
data_i <= fan_regs_mux;
elsif (decode(3) = '1') then
data_i <= disp_regs_mux;
end if;
end if;
end process;
-- Read Mux
process (rst_n, clk) is
begin
if (rst_n = '0') then
ver_regs_mux <= (others => '0');
fan_regs_mux <= (others => '0');
disp_regs_mux <= (others => '0');
sram_regs_mux <= (others => '0');
elsif (clk'event and clk = '1') then
if (cs_n_d = '0') then
sram_regs_mux <= sram_datai;
case addr(5 downto 2) is
when "0000" =>
ver_regs_mux <= GIT_COMMIT;
fan_regs_mux <= fan_regs(0);
fan_regs_mux(31 downto 12) <= fan_uspr;
disp_regs_mux <= disp_regs(0);
when "0001" =>
ver_regs_mux <= TIME_CODE;
fan_regs_mux <= (others => '0');
disp_regs_mux <= (others => '0');
when "0010" =>
ver_regs_mux <= DATE_CODE;
fan_regs_mux <= (others => '0');
disp_regs_mux <= (others => '0');
when others =>
ver_regs_mux <= (others => '0');
fan_regs_mux <= (others => '0');
disp_regs_mux <= (others => '0');
end case;
end if;
end if;
end process;
-- Read Mux (time_regs)
process (rst_n, clk) is
begin
if (rst_n = '0') then
time_regs_mux <= (others => '0');
tsc_read <= '0';
elsif (clk'event and clk = '1') then
if (cs_n_d = '0') then
case addr(5 downto 2) is
when "0000" =>
time_regs_mux <= tsc_cnt(31 downto 0);
when "0001" =>
time_regs_mux <= tsc_cnt(63 downto 32);
when "0010" =>
time_regs_mux <= tsc_cnt1(31 downto 0);
when "0011" =>
time_regs_mux <= tsc_cnt1(63 downto 32);
when "0100" =>
time_regs_mux <= pdiff_1pps;
when "0101" =>
time_regs_mux <= fdiff_1pps;
when "0110" =>
time_regs_mux <= gps_1pps_cnt;
when "0111" =>
time_regs_mux <= cur_time.t_10h & cur_time.t_1h &
cur_time.t_10m & cur_time.t_1m &
cur_time.t_10s & cur_time.t_1s &
cur_time.t_100ms & cur_time.t_10ms;
when "1000" =>
time_regs_mux <= time_regs(8);
when "1001" =>
time_regs_mux <= time_regs(9);
time_regs_mux(31) <= gps_3dfix_d;
time_regs_mux(23) <= pfd_status;
when "1010" =>
time_regs_mux <= time_regs(10);
when "1011" =>
time_regs_mux <= time_regs(11);
when "1100" =>
time_regs_mux <= time_regs(12);
when "1101" =>
time_regs_mux <= time_regs(13);
when others =>
time_regs_mux <= (others => '0');
end case;
end if;
-- Latch tsc value on LSW read
if (cs_dp_r = '1' and decode(1) = '1' and addr(5 downto 2) = "0000") then
tsc_read <= '1';
else
tsc_read <= '0';
end if;
end if;
end process;
-- time control registers
process (rst_n, clk) is
variable pps_irq_status : std_logic;
variable pll_irq_status : std_logic;
begin
if (rst_n = '0') then
for i in time_regs'range loop
time_regs(i) <= (others => '0');
end loop;
pps_irq <= '0';
pll_irq <= '0';
set <= '0';
time_regs(9)(15 downto 0) <= x"8000";
elsif (clk'event and clk = '1') then
if (cs_dp_w = '1' and decode(1) = '1') then
case addr(5 downto 2) is
when "0000" =>
time_regs(0) <= data_o;
when "0001" =>
time_regs(1) <= data_o;
when "0010" =>
time_regs(2) <= data_o;
when "0011" =>
time_regs(3) <= data_o;
when "0100" =>
time_regs(4) <= data_o;
when "0101" =>
time_regs(5) <= data_o;
when "0110" =>
time_regs(6) <= data_o;
when "0111" =>
time_regs(7) <= data_o;
when "1000" =>
time_regs(8) <= data_o;
when "1001" =>
time_regs(9) <= data_o;
when "1010" =>
time_regs(10) <= data_o;
when "1011" =>
time_regs(11)(30 downto 2) <= data_o(30 downto 2);
-- Clear interrupt with 1 is written back
if (data_o(1) = '1') then
time_regs(11)(1) <= '0';
end if;
if (data_o(0) = '1') then
time_regs(11)(0) <= '0';
end if;
when "1100" =>
time_regs(12) <= data_o;
when "1101" =>
time_regs(13)(30 downto 3) <= data_o(30 downto 3);
-- Clear interrupt with 1 is written back
if (data_o(2) = '1') then
time_regs(13)(2) <= '0';
end if;
if (data_o(1) = '1') then
time_regs(13)(1) <= '0';
end if;
if (data_o(0) = '1') then
time_regs(13)(0) <= '0';
end if;
when others =>
null;
end case;
end if;
pps_irq_status := (time_regs(10)(1) and time_regs(11)(1)) or
(time_regs(10)(0) and time_regs(11)(0));
pps_irq <= pps_irq_status;
time_regs(11)(31) <= pps_irq_status;
-- Set interrupt on incoming pps pulses
-- Higher priority than clear (above)
if (gps_1pps_d = '1') then
time_regs(11)(1) <= '1';
end if;
if (tsc_1pps_d = '1') then
time_regs(11)(0) <= '1';
end if;
pll_irq_status := (time_regs(12)(2) and time_regs(13)(2)) or
(time_regs(12)(1) and time_regs(13)(1)) or
(time_regs(12)(0) and time_regs(13)(0));
pll_irq <= pll_irq_status;
time_regs(13)(31) <= pll_irq_status;
-- Set interrupt on incoming pps pulses and pll trigger
-- Higher priority than clear (above)
if (pll_trig = '1') then
time_regs(13)(2) <= '1';
end if;
if (gps_1pps_d = '1') then
time_regs(13)(1) <= '1';
end if;
if (tsc_1pps_d = '1') then
time_regs(13)(0) <= '1';
end if;
-- Trigger time set
if (cs_dp_w = '1' and decode(1) = '1' and addr(5 downto 2) = "1000") then
set <= '1';
else
set <= '0';
end if;
-- Clear the sync flag after its done
if (gps_1pps_d = '1' and time_regs(9)(20) = '1') then
time_regs(9)(20) <= '0';
end if;
-- Clear the pfd sync control when the PFD is in the sync state
if (pfd_status = '1') then
time_regs(9)(21) <= '0';
end if;
end if;
end process;
set_time.t_1ms <= (others => '0');
set_time.t_10ms <= (others => '0');
set_time.t_100ms <= (others => '0');
set_time.t_1s <= time_regs(8)(3 downto 0);
set_time.t_10s <= time_regs(8)(7 downto 4);
set_time.t_1m <= time_regs(8)(11 downto 8);
set_time.t_10m <= time_regs(8)(15 downto 12);
set_time.t_1h <= time_regs(8)(19 downto 16);
set_time.t_10h <= time_regs(8)(23 downto 20);
dac_val <= time_regs(9)(15 downto 0);
tsc_sync <= time_regs(9)(20);
pfd_resync <= time_regs(9)(21);
-- Fan control registers
process (rst_n, clk) is
begin
if (rst_n = '0') then
for i in 0 to 0 loop
fan_regs(i) <= (others => '0');
end loop;
fan_regs(0)(7 downto 0) <= x"ff";
elsif (clk'event and clk = '1') then
if (cs_dp_w = '1' and decode(2) = '1') then
case addr(5 downto 2) is
when "0000" =>
fan_regs(0) <= data_o;
when others =>
null;
end case;
end if;
end if;
end process;
fan_pct <= fan_regs(0)(7 downto 0);
-- disp control registers
process (rst_n, clk) is
begin
if (rst_n = '0') then
for i in 0 to 0 loop
disp_regs(i) <= (others => '0');
end loop;
disp_regs(0)(7 downto 0) <= x"ff";
sram_addr <= (others => '0');
sram_we <= '0';
sram_datao <= (others => '0');
elsif (clk'event and clk = '1') then
if (cs_dp_w = '1' and decode(3) = '1') then
case addr(5 downto 2) is
when "0000" =>
disp_regs(0) <= data_o;
when others =>
null;
end case;
end if;
sram_addr <= addr(11 downto 2);
sram_we <= sram and cs_dp_w;
sram_datao <= data_o;
end if;
end process;
disp_pdm <= disp_regs(0)(7 downto 0);
stat_src <= disp_regs(0)(11 downto 8);
disp_page <= disp_regs(0)(23 downto 16);
-- GPS 1pps count register
process (rst_n, clk) is
begin
if (rst_n = '0') then
gps_1pps_cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (gps_1pps_d = '1') then
gps_1pps_cnt <= gps_1pps_cnt + 1;
end if;
end if;
end process;
end rtl;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_tb IS
END ENTITY;
ARCHITECTURE system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
CONSTANT rd_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4000 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_synth
system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_synth_inst:system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 29
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
architecture rtl of fifo is
constant cons1 : t_type :=
(
1 => func1(std_logic_vector(G_GEN), G_GEN2),
2 => func1(std_logic_vector(G_GEN3), G_GEN4)
);
constant cons1 : t_type :=
(
1 => func1(std_logic_vector(G_GEN), G_GEN2),
2 => func1( std_logic_vector(G_GEN3), G_GEN4)
);
constant cons1 : t_type :=
(
1 => func1(std_logic_vector(G_GEN), G_GEN2),
(others => '0'),
2 => func2(std_logic( G_GEN), G_GEN2)
);
begin
end architecture rtl;
|
--------------------------------------------------------------------
-- i2c_clkgen.vhd -- I2C base clock generator
-- with clock stretching feature
-- generate 1 pulse every clk_cnt clk cycles, for 1 clk duration
--------------------------------------------------------------------
-- Author : Cédric Gaudin
-- Version : 0.2 alpha
-- History :
-- 20-apr-2002 CG 0.1 Initial alpha release
-- 27-apr-2002 CG 0.2 minor cosmetic changes
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_clkgen is
port(
signal clk : in std_logic;
signal rst : in std_logic;
-- count used for dividing clk signal
signal clk_cnt : in std_logic_vector(7 downto 0);
-- I2C clock output generated
signal sclk : out std_logic;
-- I2C clock line SCL (used for clock stretching)
signal scl_in : in std_logic;
signal scl_out : in std_logic
);
end i2c_clkgen;
architecture behavioral of i2c_clkgen is
signal clk_ctr : unsigned(7 downto 0);
signal clk_wait : std_logic;
signal i_clk_out : std_logic;
begin
sclk <= i_clk_out;
process(clk, rst)
begin
if (rst = '1') then
clk_ctr <= (others => '0');
i_clk_out <= '1';
elsif (rising_edge(clk)) then
if (clk_ctr >= unsigned(clk_cnt)) then
clk_ctr <= (others => '0');
i_clk_out <= '1';
else
if (clk_wait = '0') then
clk_ctr <= clk_ctr + 1;
end if;
i_clk_out <= '0';
end if;
end if;
end process;
-- clk_wait <= '1' when (scl_out = '1' and scl_in = '0') else '0'; -- problem rencontres avec ce mode
clk_wait <= '0';
end behavioral;
|
--------------------------------------------------------------------
-- i2c_clkgen.vhd -- I2C base clock generator
-- with clock stretching feature
-- generate 1 pulse every clk_cnt clk cycles, for 1 clk duration
--------------------------------------------------------------------
-- Author : Cédric Gaudin
-- Version : 0.2 alpha
-- History :
-- 20-apr-2002 CG 0.1 Initial alpha release
-- 27-apr-2002 CG 0.2 minor cosmetic changes
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_clkgen is
port(
signal clk : in std_logic;
signal rst : in std_logic;
-- count used for dividing clk signal
signal clk_cnt : in std_logic_vector(7 downto 0);
-- I2C clock output generated
signal sclk : out std_logic;
-- I2C clock line SCL (used for clock stretching)
signal scl_in : in std_logic;
signal scl_out : in std_logic
);
end i2c_clkgen;
architecture behavioral of i2c_clkgen is
signal clk_ctr : unsigned(7 downto 0);
signal clk_wait : std_logic;
signal i_clk_out : std_logic;
begin
sclk <= i_clk_out;
process(clk, rst)
begin
if (rst = '1') then
clk_ctr <= (others => '0');
i_clk_out <= '1';
elsif (rising_edge(clk)) then
if (clk_ctr >= unsigned(clk_cnt)) then
clk_ctr <= (others => '0');
i_clk_out <= '1';
else
if (clk_wait = '0') then
clk_ctr <= clk_ctr + 1;
end if;
i_clk_out <= '0';
end if;
end if;
end process;
-- clk_wait <= '1' when (scl_out = '1' and scl_in = '0') else '0'; -- problem rencontres avec ce mode
clk_wait <= '0';
end behavioral;
|
--------------------------------------------------------------------
-- i2c_clkgen.vhd -- I2C base clock generator
-- with clock stretching feature
-- generate 1 pulse every clk_cnt clk cycles, for 1 clk duration
--------------------------------------------------------------------
-- Author : Cédric Gaudin
-- Version : 0.2 alpha
-- History :
-- 20-apr-2002 CG 0.1 Initial alpha release
-- 27-apr-2002 CG 0.2 minor cosmetic changes
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_clkgen is
port(
signal clk : in std_logic;
signal rst : in std_logic;
-- count used for dividing clk signal
signal clk_cnt : in std_logic_vector(7 downto 0);
-- I2C clock output generated
signal sclk : out std_logic;
-- I2C clock line SCL (used for clock stretching)
signal scl_in : in std_logic;
signal scl_out : in std_logic
);
end i2c_clkgen;
architecture behavioral of i2c_clkgen is
signal clk_ctr : unsigned(7 downto 0);
signal clk_wait : std_logic;
signal i_clk_out : std_logic;
begin
sclk <= i_clk_out;
process(clk, rst)
begin
if (rst = '1') then
clk_ctr <= (others => '0');
i_clk_out <= '1';
elsif (rising_edge(clk)) then
if (clk_ctr >= unsigned(clk_cnt)) then
clk_ctr <= (others => '0');
i_clk_out <= '1';
else
if (clk_wait = '0') then
clk_ctr <= clk_ctr + 1;
end if;
i_clk_out <= '0';
end if;
end if;
end process;
-- clk_wait <= '1' when (scl_out = '1' and scl_in = '0') else '0'; -- problem rencontres avec ce mode
clk_wait <= '0';
end behavioral;
|
--------------------------------------------------------------------
-- i2c_clkgen.vhd -- I2C base clock generator
-- with clock stretching feature
-- generate 1 pulse every clk_cnt clk cycles, for 1 clk duration
--------------------------------------------------------------------
-- Author : Cédric Gaudin
-- Version : 0.2 alpha
-- History :
-- 20-apr-2002 CG 0.1 Initial alpha release
-- 27-apr-2002 CG 0.2 minor cosmetic changes
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_clkgen is
port(
signal clk : in std_logic;
signal rst : in std_logic;
-- count used for dividing clk signal
signal clk_cnt : in std_logic_vector(7 downto 0);
-- I2C clock output generated
signal sclk : out std_logic;
-- I2C clock line SCL (used for clock stretching)
signal scl_in : in std_logic;
signal scl_out : in std_logic
);
end i2c_clkgen;
architecture behavioral of i2c_clkgen is
signal clk_ctr : unsigned(7 downto 0);
signal clk_wait : std_logic;
signal i_clk_out : std_logic;
begin
sclk <= i_clk_out;
process(clk, rst)
begin
if (rst = '1') then
clk_ctr <= (others => '0');
i_clk_out <= '1';
elsif (rising_edge(clk)) then
if (clk_ctr >= unsigned(clk_cnt)) then
clk_ctr <= (others => '0');
i_clk_out <= '1';
else
if (clk_wait = '0') then
clk_ctr <= clk_ctr + 1;
end if;
i_clk_out <= '0';
end if;
end if;
end process;
-- clk_wait <= '1' when (scl_out = '1' and scl_in = '0') else '0'; -- problem rencontres avec ce mode
clk_wait <= '0';
end behavioral;
|
--------------------------------------------------------------------
-- i2c_clkgen.vhd -- I2C base clock generator
-- with clock stretching feature
-- generate 1 pulse every clk_cnt clk cycles, for 1 clk duration
--------------------------------------------------------------------
-- Author : Cédric Gaudin
-- Version : 0.2 alpha
-- History :
-- 20-apr-2002 CG 0.1 Initial alpha release
-- 27-apr-2002 CG 0.2 minor cosmetic changes
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_clkgen is
port(
signal clk : in std_logic;
signal rst : in std_logic;
-- count used for dividing clk signal
signal clk_cnt : in std_logic_vector(7 downto 0);
-- I2C clock output generated
signal sclk : out std_logic;
-- I2C clock line SCL (used for clock stretching)
signal scl_in : in std_logic;
signal scl_out : in std_logic
);
end i2c_clkgen;
architecture behavioral of i2c_clkgen is
signal clk_ctr : unsigned(7 downto 0);
signal clk_wait : std_logic;
signal i_clk_out : std_logic;
begin
sclk <= i_clk_out;
process(clk, rst)
begin
if (rst = '1') then
clk_ctr <= (others => '0');
i_clk_out <= '1';
elsif (rising_edge(clk)) then
if (clk_ctr >= unsigned(clk_cnt)) then
clk_ctr <= (others => '0');
i_clk_out <= '1';
else
if (clk_wait = '0') then
clk_ctr <= clk_ctr + 1;
end if;
i_clk_out <= '0';
end if;
end if;
end process;
-- clk_wait <= '1' when (scl_out = '1' and scl_in = '0') else '0'; -- problem rencontres avec ce mode
clk_wait <= '0';
end behavioral;
|
-- megafunction wizard: %ALTIOBUF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altiobuf_bidir
-- ============================================================
-- File Name: bidir_dq_iobuf_inst.vhd
-- Megafunction Name(s):
-- altiobuf_bidir
--
-- Simulation Library Files(s):
-- stratixiii
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2007 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altiobuf_bidir CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix III" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=8 OPEN_DRAIN_OUTPUT="FALSE" USE_DIFFERENTIAL_MODE="FALSE" USE_DYNAMIC_TERMINATION_CONTROL="TRUE" USE_TERMINATION_CONTROL="FALSE" datain dataio dataout dynamicterminationcontrol oe
--VERSION_BEGIN 7.2SP3 cbx_altiobuf_in 2007:08:30:02:46:00:SJ cbx_mgl 2007:08:03:23:48:12:SJ cbx_stratixiii 2007:06:29:01:16:20:SJ VERSION_END
LIBRARY stratixiii;
USE stratixiii.all;
--synthesis_resources = stratixiii_io_ibuf 8 stratixiii_io_obuf 8
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY bidir_dq_iobuf_inst_iobuf_bidir_8jr IS
PORT
(
datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
dataio : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
dynamicterminationcontrol : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
oe : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END bidir_dq_iobuf_inst_iobuf_bidir_8jr;
ARCHITECTURE RTL OF bidir_dq_iobuf_inst_iobuf_bidir_8jr IS
-- ATTRIBUTE synthesis_clearbox : boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL wire_ibufa_i : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_ibufa_o : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_obufa_dynamicterminationcontrol : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_obufa_i : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_obufa_o : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_obufa_oe : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT stratixiii_io_ibuf
GENERIC
(
bus_hold : STRING := "false";
differential_mode : STRING := "false";
lpm_type : STRING := "stratixiii_io_ibuf"
);
PORT
(
i : IN STD_LOGIC := '0';
ibar : IN STD_LOGIC := '0';
o : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixiii_io_obuf
GENERIC
(
bus_hold : STRING := "false";
open_drain_output : STRING := "false";
shift_series_termination_control : STRING := "false";
lpm_type : STRING := "stratixiii_io_obuf"
);
PORT
(
dynamicterminationcontrol : IN STD_LOGIC := '0';
i : IN STD_LOGIC := '0';
o : OUT STD_LOGIC;
obar : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
parallelterminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
seriesterminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
dataio <= wire_obufa_o;
dataout <= wire_ibufa_o;
wire_ibufa_i <= dataio;
loop0 : FOR i IN 0 TO 7 GENERATE
ibufa : stratixiii_io_ibuf
GENERIC MAP (
bus_hold => "false",
differential_mode => "false"
)
PORT MAP (
i => wire_ibufa_i(i),
o => wire_ibufa_o(i)
);
END GENERATE loop0;
wire_obufa_dynamicterminationcontrol <= dynamicterminationcontrol;
wire_obufa_i <= datain;
wire_obufa_oe <= oe;
loop1 : FOR i IN 0 TO 7 GENERATE
obufa : stratixiii_io_obuf
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false"
)
PORT MAP (
dynamicterminationcontrol => wire_obufa_dynamicterminationcontrol(i),
i => wire_obufa_i(i),
o => wire_obufa_o(i),
oe => wire_obufa_oe(i)
);
END GENERATE loop1;
END RTL; --bidir_dq_iobuf_inst_iobuf_bidir_8jr
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY bidir_dq_iobuf_inst IS
PORT
(
datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
dyn_term_ctrl : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
oe : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
dataio : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END bidir_dq_iobuf_inst;
ARCHITECTURE RTL OF bidir_dq_iobuf_inst IS
-- ATTRIBUTE synthesis_clearbox: boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS TRUE;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT bidir_dq_iobuf_inst_iobuf_bidir_8jr
PORT (
dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
dataio : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
oe : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
dynamicterminationcontrol : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
dataout <= sub_wire0(7 DOWNTO 0);
bidir_dq_iobuf_inst_iobuf_bidir_8jr_component : bidir_dq_iobuf_inst_iobuf_bidir_8jr
PORT MAP (
datain => datain,
oe => oe,
dynamicterminationcontrol => dyn_term_ctrl,
dataout => sub_wire0,
dataio => dataio
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE"
-- Retrieval info: CONSTANT: number_of_channels NUMERIC "8"
-- Retrieval info: CONSTANT: open_drain_output STRING "FALSE"
-- Retrieval info: CONSTANT: use_differential_mode STRING "FALSE"
-- Retrieval info: CONSTANT: use_dynamic_termination_control STRING "TRUE"
-- Retrieval info: CONSTANT: use_termination_control STRING "FALSE"
-- Retrieval info: USED_PORT: datain 0 0 8 0 INPUT NODEFVAL "datain[7..0]"
-- Retrieval info: USED_PORT: dataio 0 0 8 0 BIDIR NODEFVAL "dataio[7..0]"
-- Retrieval info: USED_PORT: dataout 0 0 8 0 OUTPUT NODEFVAL "dataout[7..0]"
-- Retrieval info: USED_PORT: dyn_term_ctrl 0 0 8 0 INPUT NODEFVAL "dyn_term_ctrl[7..0]"
-- Retrieval info: USED_PORT: oe 0 0 8 0 INPUT NODEFVAL "oe[7..0]"
-- Retrieval info: CONNECT: @datain 0 0 8 0 datain 0 0 8 0
-- Retrieval info: CONNECT: @dynamicterminationcontrol 0 0 8 0 dyn_term_ctrl 0 0 8 0
-- Retrieval info: CONNECT: @oe 0 0 8 0 oe 0 0 8 0
-- Retrieval info: CONNECT: dataout 0 0 8 0 @dataout 0 0 8 0
-- Retrieval info: CONNECT: dataio 0 0 8 0 @dataio 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL bidir_dq_iobuf_inst.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL bidir_dq_iobuf_inst.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL bidir_dq_iobuf_inst.cmp FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL bidir_dq_iobuf_inst.bsf FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL bidir_dq_iobuf_inst_inst.vhd FALSE FALSE
-- Retrieval info: LIB_FILE: stratixiii
|
-- Author: Varun Nagpal
-- Net Id: vxn180010
-- Microprocessor Systems Project
-- December, 6th 2018
--
-- Package: Modifiable Paramaters, non-modifiable constants and types (ports)
-- for the Generic Nth order (L = N+1 taps) Transposed Direct-form FIR-filter
--
-- Modifiable variables for Design of the FIR Filter:
-- FIR_ORDER = order of the filter (N). Note L = N+1 = taps
-- X_BIT_SIZE = bit width (n) of input samples (signed 2's complement)
-- H_BIT_SIZE = bit width (m) of coefficients (signed 2's complement)
--
-- Modifiable variables for testbench of the FIR Filter:
-- CLK_CYCLE_TIME = clock cycle time
-- CLK_HIGH_TIME = time for which clock is high
--
-- All remaining parameters in the package are non-modifiable constants which
-- must not be modified manually as there values are calculated during using values
-- of modifiable variables during compilation of VHDL files
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_logic_unsigned.all;
package fir_filter_shared_package is
-- modifiable variables for design of FIR filter
constant FIR_ORDER : natural := 26; -- order of the filter (N). Note L = N+1 = taps
constant X_BIT_SIZE : natural := 8; -- bit width (n) of input samples (signed 2's complement)
constant H_BIT_SIZE : natural := 8; -- bit width (m) of coefficients (signed 2's complement)
-- modifiable variables for testbench of FIR filter (uncomment if simulating filter in isolation)
--constant CLK_CYCLE_TIME : time := 10 ns;
--constant CLK_HIGH_TIME : time := 5 ns;
-- modifiable constants for testbench of FIR filter (uncomment if simulating filter in isolation)
--constant CLK_LOW_TIME : time := CLK_CYCLE_TIME - CLK_HIGH_TIME;
-- non-modifiable constants
constant MULT_BIT_SIZE : natural := X_BIT_SIZE+H_BIT_SIZE; -- bit width (n+m) of signed multiplier
constant EXTR_BIT_SIZE : natural := natural(ceil(log2(real(FIR_ORDER+1))))-1; -- extra bits for accumulation = ceil(log2(L))-1
constant Y_BIT_SIZE : natural := MULT_BIT_SIZE+EXTR_BIT_SIZE; -- bit width of output samples (signed 2's complement) or signed adder
-- N = no. of register delays or additions
subtype ADD_REG_TYPE is signed(Y_BIT_SIZE-1 downto 0);
type ADD_REG_ARRAY is array (0 to FIR_ORDER) of ADD_REG_TYPE;
-- L = N+1 no. of taps or coefficients or multiplications
subtype MULT_SIG_TYPE is signed(MULT_BIT_SIZE-1 downto 0);
type MULT_SIG_ARRAY is array (0 to FIR_ORDER) of MULT_SIG_TYPE;
subtype COEFF_REG_TYPE is signed(H_BIT_SIZE-1 downto 0);
type COEFF_REG_ARRAY is array (0 to FIR_ORDER) of COEFF_REG_TYPE;
end fir_filter_shared_package;
package body fir_filter_shared_package is
-- empty
end fir_filter_shared_package; |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mul is
generic (
src1_bits : natural := 32;
src2_bits : natural := 32
);
port (
unsgnd : in std_ulogic;
src1 : in std_ulogic_vector(src1_bits-1 downto 0);
src2 : in std_ulogic_vector(src2_bits-1 downto 0);
result : out std_ulogic_vector(src1_bits+src2_bits-1 downto 0)
);
end;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:microblaze:10.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY microblaze_v10_0_1;
USE microblaze_v10_0_1.MicroBlaze;
ENTITY system_microblaze_0_0 IS
PORT (
Clk : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Interrupt : IN STD_LOGIC;
Interrupt_Address : IN STD_LOGIC_VECTOR(0 TO 31);
Interrupt_Ack : OUT STD_LOGIC_VECTOR(0 TO 1);
Instr_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Instr : IN STD_LOGIC_VECTOR(0 TO 31);
IFetch : OUT STD_LOGIC;
I_AS : OUT STD_LOGIC;
IReady : IN STD_LOGIC;
IWAIT : IN STD_LOGIC;
ICE : IN STD_LOGIC;
IUE : IN STD_LOGIC;
Data_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Data_Read : IN STD_LOGIC_VECTOR(0 TO 31);
Data_Write : OUT STD_LOGIC_VECTOR(0 TO 31);
D_AS : OUT STD_LOGIC;
Read_Strobe : OUT STD_LOGIC;
Write_Strobe : OUT STD_LOGIC;
DReady : IN STD_LOGIC;
DWait : IN STD_LOGIC;
DCE : IN STD_LOGIC;
DUE : IN STD_LOGIC;
Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
M_AXI_DP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWVALID : OUT STD_LOGIC;
M_AXI_DP_AWREADY : IN STD_LOGIC;
M_AXI_DP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_WVALID : OUT STD_LOGIC;
M_AXI_DP_WREADY : IN STD_LOGIC;
M_AXI_DP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_BVALID : IN STD_LOGIC;
M_AXI_DP_BREADY : OUT STD_LOGIC;
M_AXI_DP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARVALID : OUT STD_LOGIC;
M_AXI_DP_ARREADY : IN STD_LOGIC;
M_AXI_DP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_RVALID : IN STD_LOGIC;
M_AXI_DP_RREADY : OUT STD_LOGIC;
Dbg_Clk : IN STD_LOGIC;
Dbg_TDI : IN STD_LOGIC;
Dbg_TDO : OUT STD_LOGIC;
Dbg_Reg_En : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Shift : IN STD_LOGIC;
Dbg_Capture : IN STD_LOGIC;
Dbg_Update : IN STD_LOGIC;
Debug_Rst : IN STD_LOGIC;
Dbg_Disable : IN STD_LOGIC;
M_AXI_IC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWLOCK : OUT STD_LOGIC;
M_AXI_IC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWVALID : OUT STD_LOGIC;
M_AXI_IC_AWREADY : IN STD_LOGIC;
M_AXI_IC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_WLAST : OUT STD_LOGIC;
M_AXI_IC_WVALID : OUT STD_LOGIC;
M_AXI_IC_WREADY : IN STD_LOGIC;
M_AXI_IC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_BVALID : IN STD_LOGIC;
M_AXI_IC_BREADY : OUT STD_LOGIC;
M_AXI_IC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARLOCK : OUT STD_LOGIC;
M_AXI_IC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARVALID : OUT STD_LOGIC;
M_AXI_IC_ARREADY : IN STD_LOGIC;
M_AXI_IC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RLAST : IN STD_LOGIC;
M_AXI_IC_RVALID : IN STD_LOGIC;
M_AXI_IC_RREADY : OUT STD_LOGIC;
M_AXI_DC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWLOCK : OUT STD_LOGIC;
M_AXI_DC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWVALID : OUT STD_LOGIC;
M_AXI_DC_AWREADY : IN STD_LOGIC;
M_AXI_DC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_WLAST : OUT STD_LOGIC;
M_AXI_DC_WVALID : OUT STD_LOGIC;
M_AXI_DC_WREADY : IN STD_LOGIC;
M_AXI_DC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BVALID : IN STD_LOGIC;
M_AXI_DC_BREADY : OUT STD_LOGIC;
M_AXI_DC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARLOCK : OUT STD_LOGIC;
M_AXI_DC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARVALID : OUT STD_LOGIC;
M_AXI_DC_ARREADY : IN STD_LOGIC;
M_AXI_DC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RLAST : IN STD_LOGIC;
M_AXI_DC_RVALID : IN STD_LOGIC;
M_AXI_DC_RREADY : OUT STD_LOGIC
);
END system_microblaze_0_0;
ARCHITECTURE system_microblaze_0_0_arch OF system_microblaze_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_microblaze_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT MicroBlaze IS
GENERIC (
C_SCO : INTEGER;
C_FREQ : INTEGER;
C_USE_CONFIG_RESET : INTEGER;
C_NUM_SYNC_FF_CLK : INTEGER;
C_NUM_SYNC_FF_CLK_IRQ : INTEGER;
C_NUM_SYNC_FF_CLK_DEBUG : INTEGER;
C_NUM_SYNC_FF_DBG_CLK : INTEGER;
C_FAULT_TOLERANT : INTEGER;
C_ECC_USE_CE_EXCEPTION : INTEGER;
C_LOCKSTEP_SLAVE : INTEGER;
C_LOCKSTEP_MASTER : INTEGER;
C_ENDIANNESS : INTEGER;
C_FAMILY : STRING;
C_DATA_SIZE : INTEGER;
C_INSTR_SIZE : INTEGER;
C_IADDR_SIZE : INTEGER;
C_DADDR_SIZE : INTEGER;
C_INSTANCE : STRING;
C_AVOID_PRIMITIVES : INTEGER;
C_AREA_OPTIMIZED : INTEGER;
C_OPTIMIZATION : INTEGER;
C_INTERCONNECT : INTEGER;
C_BASE_VECTORS : STD_LOGIC_VECTOR;
C_M_AXI_DP_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_DP_DATA_WIDTH : INTEGER;
C_M_AXI_DP_ADDR_WIDTH : INTEGER;
C_M_AXI_DP_EXCLUSIVE_ACCESS : INTEGER;
C_M_AXI_D_BUS_EXCEPTION : INTEGER;
C_M_AXI_IP_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_IP_DATA_WIDTH : INTEGER;
C_M_AXI_IP_ADDR_WIDTH : INTEGER;
C_M_AXI_I_BUS_EXCEPTION : INTEGER;
C_D_LMB : INTEGER;
C_D_AXI : INTEGER;
C_I_LMB : INTEGER;
C_I_AXI : INTEGER;
C_USE_MSR_INSTR : INTEGER;
C_USE_PCMP_INSTR : INTEGER;
C_USE_BARREL : INTEGER;
C_USE_DIV : INTEGER;
C_USE_HW_MUL : INTEGER;
C_USE_FPU : INTEGER;
C_USE_REORDER_INSTR : INTEGER;
C_UNALIGNED_EXCEPTIONS : INTEGER;
C_ILL_OPCODE_EXCEPTION : INTEGER;
C_DIV_ZERO_EXCEPTION : INTEGER;
C_FPU_EXCEPTION : INTEGER;
C_FSL_LINKS : INTEGER;
C_USE_EXTENDED_FSL_INSTR : INTEGER;
C_FSL_EXCEPTION : INTEGER;
C_USE_STACK_PROTECTION : INTEGER;
C_IMPRECISE_EXCEPTIONS : INTEGER;
C_USE_INTERRUPT : INTEGER;
C_USE_EXT_BRK : INTEGER;
C_USE_EXT_NM_BRK : INTEGER;
C_USE_NON_SECURE : INTEGER;
C_USE_MMU : INTEGER;
C_MMU_DTLB_SIZE : INTEGER;
C_MMU_ITLB_SIZE : INTEGER;
C_MMU_TLB_ACCESS : INTEGER;
C_MMU_ZONES : INTEGER;
C_MMU_PRIVILEGED_INSTR : INTEGER;
C_USE_BRANCH_TARGET_CACHE : INTEGER;
C_BRANCH_TARGET_CACHE_SIZE : INTEGER;
C_PC_WIDTH : INTEGER;
C_PVR : INTEGER;
C_PVR_USER1 : STD_LOGIC_VECTOR(0 TO 7);
C_PVR_USER2 : STD_LOGIC_VECTOR(0 TO 31);
C_DYNAMIC_BUS_SIZING : INTEGER;
C_RESET_MSR : STD_LOGIC_VECTOR(0 TO 31);
C_OPCODE_0x0_ILLEGAL : INTEGER;
C_DEBUG_ENABLED : INTEGER;
C_DEBUG_INTERFACE : INTEGER;
C_NUMBER_OF_PC_BRK : INTEGER;
C_NUMBER_OF_RD_ADDR_BRK : INTEGER;
C_NUMBER_OF_WR_ADDR_BRK : INTEGER;
C_DEBUG_EVENT_COUNTERS : INTEGER;
C_DEBUG_LATENCY_COUNTERS : INTEGER;
C_DEBUG_COUNTER_WIDTH : INTEGER;
C_DEBUG_TRACE_SIZE : INTEGER;
C_DEBUG_EXTERNAL_TRACE : INTEGER;
C_DEBUG_PROFILE_SIZE : INTEGER;
C_INTERRUPT_IS_EDGE : INTEGER;
C_EDGE_IS_POSITIVE : INTEGER;
C_ASYNC_INTERRUPT : INTEGER;
C_ASYNC_WAKEUP : INTEGER;
C_M0_AXIS_DATA_WIDTH : INTEGER;
C_S0_AXIS_DATA_WIDTH : INTEGER;
C_M1_AXIS_DATA_WIDTH : INTEGER;
C_S1_AXIS_DATA_WIDTH : INTEGER;
C_M2_AXIS_DATA_WIDTH : INTEGER;
C_S2_AXIS_DATA_WIDTH : INTEGER;
C_M3_AXIS_DATA_WIDTH : INTEGER;
C_S3_AXIS_DATA_WIDTH : INTEGER;
C_M4_AXIS_DATA_WIDTH : INTEGER;
C_S4_AXIS_DATA_WIDTH : INTEGER;
C_M5_AXIS_DATA_WIDTH : INTEGER;
C_S5_AXIS_DATA_WIDTH : INTEGER;
C_M6_AXIS_DATA_WIDTH : INTEGER;
C_S6_AXIS_DATA_WIDTH : INTEGER;
C_M7_AXIS_DATA_WIDTH : INTEGER;
C_S7_AXIS_DATA_WIDTH : INTEGER;
C_M8_AXIS_DATA_WIDTH : INTEGER;
C_S8_AXIS_DATA_WIDTH : INTEGER;
C_M9_AXIS_DATA_WIDTH : INTEGER;
C_S9_AXIS_DATA_WIDTH : INTEGER;
C_M10_AXIS_DATA_WIDTH : INTEGER;
C_S10_AXIS_DATA_WIDTH : INTEGER;
C_M11_AXIS_DATA_WIDTH : INTEGER;
C_S11_AXIS_DATA_WIDTH : INTEGER;
C_M12_AXIS_DATA_WIDTH : INTEGER;
C_S12_AXIS_DATA_WIDTH : INTEGER;
C_M13_AXIS_DATA_WIDTH : INTEGER;
C_S13_AXIS_DATA_WIDTH : INTEGER;
C_M14_AXIS_DATA_WIDTH : INTEGER;
C_S14_AXIS_DATA_WIDTH : INTEGER;
C_M15_AXIS_DATA_WIDTH : INTEGER;
C_S15_AXIS_DATA_WIDTH : INTEGER;
C_ICACHE_BASEADDR : STD_LOGIC_VECTOR;
C_ICACHE_HIGHADDR : STD_LOGIC_VECTOR;
C_USE_ICACHE : INTEGER;
C_ALLOW_ICACHE_WR : INTEGER;
C_ADDR_TAG_BITS : INTEGER;
C_CACHE_BYTE_SIZE : INTEGER;
C_ICACHE_LINE_LEN : INTEGER;
C_ICACHE_ALWAYS_USED : INTEGER;
C_ICACHE_STREAMS : INTEGER;
C_ICACHE_VICTIMS : INTEGER;
C_ICACHE_FORCE_TAG_LUTRAM : INTEGER;
C_ICACHE_DATA_WIDTH : INTEGER;
C_M_AXI_IC_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_IC_DATA_WIDTH : INTEGER;
C_M_AXI_IC_ADDR_WIDTH : INTEGER;
C_M_AXI_IC_USER_VALUE : INTEGER;
C_M_AXI_IC_AWUSER_WIDTH : INTEGER;
C_M_AXI_IC_ARUSER_WIDTH : INTEGER;
C_M_AXI_IC_WUSER_WIDTH : INTEGER;
C_M_AXI_IC_RUSER_WIDTH : INTEGER;
C_M_AXI_IC_BUSER_WIDTH : INTEGER;
C_DCACHE_BASEADDR : STD_LOGIC_VECTOR;
C_DCACHE_HIGHADDR : STD_LOGIC_VECTOR;
C_USE_DCACHE : INTEGER;
C_ALLOW_DCACHE_WR : INTEGER;
C_DCACHE_ADDR_TAG : INTEGER;
C_DCACHE_BYTE_SIZE : INTEGER;
C_DCACHE_LINE_LEN : INTEGER;
C_DCACHE_ALWAYS_USED : INTEGER;
C_DCACHE_USE_WRITEBACK : INTEGER;
C_DCACHE_VICTIMS : INTEGER;
C_DCACHE_FORCE_TAG_LUTRAM : INTEGER;
C_DCACHE_DATA_WIDTH : INTEGER;
C_M_AXI_DC_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_DC_DATA_WIDTH : INTEGER;
C_M_AXI_DC_ADDR_WIDTH : INTEGER;
C_M_AXI_DC_EXCLUSIVE_ACCESS : INTEGER;
C_M_AXI_DC_USER_VALUE : INTEGER;
C_M_AXI_DC_AWUSER_WIDTH : INTEGER;
C_M_AXI_DC_ARUSER_WIDTH : INTEGER;
C_M_AXI_DC_WUSER_WIDTH : INTEGER;
C_M_AXI_DC_RUSER_WIDTH : INTEGER;
C_M_AXI_DC_BUSER_WIDTH : INTEGER
);
PORT (
Clk : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Mb_Reset : IN STD_LOGIC;
Config_Reset : IN STD_LOGIC;
Scan_Reset : IN STD_LOGIC;
Scan_Reset_Sel : IN STD_LOGIC;
RAM_Static : IN STD_LOGIC_VECTOR(1023 DOWNTO 0);
Interrupt : IN STD_LOGIC;
Interrupt_Address : IN STD_LOGIC_VECTOR(0 TO 31);
Interrupt_Ack : OUT STD_LOGIC_VECTOR(0 TO 1);
Ext_BRK : IN STD_LOGIC;
Ext_NM_BRK : IN STD_LOGIC;
Dbg_Stop : IN STD_LOGIC;
Dbg_Intr : OUT STD_LOGIC;
MB_Halted : OUT STD_LOGIC;
MB_Error : OUT STD_LOGIC;
Wakeup : IN STD_LOGIC_VECTOR(0 TO 1);
Sleep : OUT STD_LOGIC;
Hibernate : OUT STD_LOGIC;
Suspend : OUT STD_LOGIC;
Dbg_Wakeup : OUT STD_LOGIC;
Dbg_Continue : OUT STD_LOGIC;
Reset_Mode : IN STD_LOGIC_VECTOR(0 TO 1);
Pause : IN STD_LOGIC;
Pause_Ack : OUT STD_LOGIC;
Non_Secure : IN STD_LOGIC_VECTOR(0 TO 3);
LOCKSTEP_Slave_In : IN STD_LOGIC_VECTOR(0 TO 4095);
LOCKSTEP_Master_Out : OUT STD_LOGIC_VECTOR(0 TO 4095);
LOCKSTEP_Out : OUT STD_LOGIC_VECTOR(0 TO 4095);
Instr_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Instr : IN STD_LOGIC_VECTOR(0 TO 31);
IFetch : OUT STD_LOGIC;
I_AS : OUT STD_LOGIC;
IReady : IN STD_LOGIC;
IWAIT : IN STD_LOGIC;
ICE : IN STD_LOGIC;
IUE : IN STD_LOGIC;
M_AXI_IP_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IP_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_AWLOCK : OUT STD_LOGIC;
M_AXI_IP_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_AWVALID : OUT STD_LOGIC;
M_AXI_IP_AWREADY : IN STD_LOGIC;
M_AXI_IP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_WLAST : OUT STD_LOGIC;
M_AXI_IP_WVALID : OUT STD_LOGIC;
M_AXI_IP_WREADY : IN STD_LOGIC;
M_AXI_IP_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_BVALID : IN STD_LOGIC;
M_AXI_IP_BREADY : OUT STD_LOGIC;
M_AXI_IP_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IP_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_ARLOCK : OUT STD_LOGIC;
M_AXI_IP_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_ARVALID : OUT STD_LOGIC;
M_AXI_IP_ARREADY : IN STD_LOGIC;
M_AXI_IP_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_RLAST : IN STD_LOGIC;
M_AXI_IP_RVALID : IN STD_LOGIC;
M_AXI_IP_RREADY : OUT STD_LOGIC;
Data_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Data_Read : IN STD_LOGIC_VECTOR(0 TO 31);
Data_Write : OUT STD_LOGIC_VECTOR(0 TO 31);
D_AS : OUT STD_LOGIC;
Read_Strobe : OUT STD_LOGIC;
Write_Strobe : OUT STD_LOGIC;
DReady : IN STD_LOGIC;
DWait : IN STD_LOGIC;
DCE : IN STD_LOGIC;
DUE : IN STD_LOGIC;
Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
M_AXI_DP_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DP_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_AWLOCK : OUT STD_LOGIC;
M_AXI_DP_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_AWVALID : OUT STD_LOGIC;
M_AXI_DP_AWREADY : IN STD_LOGIC;
M_AXI_DP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_WLAST : OUT STD_LOGIC;
M_AXI_DP_WVALID : OUT STD_LOGIC;
M_AXI_DP_WREADY : IN STD_LOGIC;
M_AXI_DP_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_BVALID : IN STD_LOGIC;
M_AXI_DP_BREADY : OUT STD_LOGIC;
M_AXI_DP_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DP_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_ARLOCK : OUT STD_LOGIC;
M_AXI_DP_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_ARVALID : OUT STD_LOGIC;
M_AXI_DP_ARREADY : IN STD_LOGIC;
M_AXI_DP_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_RLAST : IN STD_LOGIC;
M_AXI_DP_RVALID : IN STD_LOGIC;
M_AXI_DP_RREADY : OUT STD_LOGIC;
Dbg_Clk : IN STD_LOGIC;
Dbg_TDI : IN STD_LOGIC;
Dbg_TDO : OUT STD_LOGIC;
Dbg_Reg_En : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Shift : IN STD_LOGIC;
Dbg_Capture : IN STD_LOGIC;
Dbg_Update : IN STD_LOGIC;
Dbg_Trig_In : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trace_Clk : IN STD_LOGIC;
Dbg_Trace_Data : OUT STD_LOGIC_VECTOR(0 TO 35);
Dbg_Trace_Ready : IN STD_LOGIC;
Dbg_Trace_Valid : OUT STD_LOGIC;
Debug_Rst : IN STD_LOGIC;
Dbg_Disable : IN STD_LOGIC;
Dbg_AWADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID : IN STD_LOGIC;
Dbg_AWREADY : OUT STD_LOGIC;
Dbg_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID : IN STD_LOGIC;
Dbg_WREADY : OUT STD_LOGIC;
Dbg_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID : OUT STD_LOGIC;
Dbg_BREADY : IN STD_LOGIC;
Dbg_ARADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID : IN STD_LOGIC;
Dbg_ARREADY : OUT STD_LOGIC;
Dbg_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID : OUT STD_LOGIC;
Dbg_RREADY : IN STD_LOGIC;
DEBUG_ACLK : IN STD_LOGIC;
DEBUG_ARESETN : IN STD_LOGIC;
Trace_Instruction : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Valid_Instr : OUT STD_LOGIC;
Trace_PC : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Reg_Write : OUT STD_LOGIC;
Trace_Reg_Addr : OUT STD_LOGIC_VECTOR(0 TO 4);
Trace_MSR_Reg : OUT STD_LOGIC_VECTOR(0 TO 14);
Trace_PID_Reg : OUT STD_LOGIC_VECTOR(0 TO 7);
Trace_New_Reg_Value : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Exception_Taken : OUT STD_LOGIC;
Trace_Exception_Kind : OUT STD_LOGIC_VECTOR(0 TO 4);
Trace_Jump_Taken : OUT STD_LOGIC;
Trace_Delay_Slot : OUT STD_LOGIC;
Trace_Data_Address : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Data_Write_Value : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Data_Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
Trace_Data_Access : OUT STD_LOGIC;
Trace_Data_Read : OUT STD_LOGIC;
Trace_Data_Write : OUT STD_LOGIC;
Trace_DCache_Req : OUT STD_LOGIC;
Trace_DCache_Hit : OUT STD_LOGIC;
Trace_DCache_Rdy : OUT STD_LOGIC;
Trace_DCache_Read : OUT STD_LOGIC;
Trace_ICache_Req : OUT STD_LOGIC;
Trace_ICache_Hit : OUT STD_LOGIC;
Trace_ICache_Rdy : OUT STD_LOGIC;
Trace_OF_PipeRun : OUT STD_LOGIC;
Trace_EX_PipeRun : OUT STD_LOGIC;
Trace_MEM_PipeRun : OUT STD_LOGIC;
Trace_MB_Halted : OUT STD_LOGIC;
Trace_Jump_Hit : OUT STD_LOGIC;
M0_AXIS_TLAST : OUT STD_LOGIC;
M0_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M0_AXIS_TVALID : OUT STD_LOGIC;
M0_AXIS_TREADY : IN STD_LOGIC;
M1_AXIS_TLAST : OUT STD_LOGIC;
M1_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M1_AXIS_TVALID : OUT STD_LOGIC;
M1_AXIS_TREADY : IN STD_LOGIC;
M2_AXIS_TLAST : OUT STD_LOGIC;
M2_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M2_AXIS_TVALID : OUT STD_LOGIC;
M2_AXIS_TREADY : IN STD_LOGIC;
M3_AXIS_TLAST : OUT STD_LOGIC;
M3_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M3_AXIS_TVALID : OUT STD_LOGIC;
M3_AXIS_TREADY : IN STD_LOGIC;
M4_AXIS_TLAST : OUT STD_LOGIC;
M4_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M4_AXIS_TVALID : OUT STD_LOGIC;
M4_AXIS_TREADY : IN STD_LOGIC;
M5_AXIS_TLAST : OUT STD_LOGIC;
M5_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M5_AXIS_TVALID : OUT STD_LOGIC;
M5_AXIS_TREADY : IN STD_LOGIC;
M6_AXIS_TLAST : OUT STD_LOGIC;
M6_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M6_AXIS_TVALID : OUT STD_LOGIC;
M6_AXIS_TREADY : IN STD_LOGIC;
M7_AXIS_TLAST : OUT STD_LOGIC;
M7_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M7_AXIS_TVALID : OUT STD_LOGIC;
M7_AXIS_TREADY : IN STD_LOGIC;
M8_AXIS_TLAST : OUT STD_LOGIC;
M8_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M8_AXIS_TVALID : OUT STD_LOGIC;
M8_AXIS_TREADY : IN STD_LOGIC;
M9_AXIS_TLAST : OUT STD_LOGIC;
M9_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M9_AXIS_TVALID : OUT STD_LOGIC;
M9_AXIS_TREADY : IN STD_LOGIC;
M10_AXIS_TLAST : OUT STD_LOGIC;
M10_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M10_AXIS_TVALID : OUT STD_LOGIC;
M10_AXIS_TREADY : IN STD_LOGIC;
M11_AXIS_TLAST : OUT STD_LOGIC;
M11_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M11_AXIS_TVALID : OUT STD_LOGIC;
M11_AXIS_TREADY : IN STD_LOGIC;
M12_AXIS_TLAST : OUT STD_LOGIC;
M12_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M12_AXIS_TVALID : OUT STD_LOGIC;
M12_AXIS_TREADY : IN STD_LOGIC;
M13_AXIS_TLAST : OUT STD_LOGIC;
M13_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M13_AXIS_TVALID : OUT STD_LOGIC;
M13_AXIS_TREADY : IN STD_LOGIC;
M14_AXIS_TLAST : OUT STD_LOGIC;
M14_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M14_AXIS_TVALID : OUT STD_LOGIC;
M14_AXIS_TREADY : IN STD_LOGIC;
M15_AXIS_TLAST : OUT STD_LOGIC;
M15_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M15_AXIS_TVALID : OUT STD_LOGIC;
M15_AXIS_TREADY : IN STD_LOGIC;
S0_AXIS_TLAST : IN STD_LOGIC;
S0_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXIS_TVALID : IN STD_LOGIC;
S0_AXIS_TREADY : OUT STD_LOGIC;
S1_AXIS_TLAST : IN STD_LOGIC;
S1_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXIS_TVALID : IN STD_LOGIC;
S1_AXIS_TREADY : OUT STD_LOGIC;
S2_AXIS_TLAST : IN STD_LOGIC;
S2_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXIS_TVALID : IN STD_LOGIC;
S2_AXIS_TREADY : OUT STD_LOGIC;
S3_AXIS_TLAST : IN STD_LOGIC;
S3_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S3_AXIS_TVALID : IN STD_LOGIC;
S3_AXIS_TREADY : OUT STD_LOGIC;
S4_AXIS_TLAST : IN STD_LOGIC;
S4_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S4_AXIS_TVALID : IN STD_LOGIC;
S4_AXIS_TREADY : OUT STD_LOGIC;
S5_AXIS_TLAST : IN STD_LOGIC;
S5_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S5_AXIS_TVALID : IN STD_LOGIC;
S5_AXIS_TREADY : OUT STD_LOGIC;
S6_AXIS_TLAST : IN STD_LOGIC;
S6_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S6_AXIS_TVALID : IN STD_LOGIC;
S6_AXIS_TREADY : OUT STD_LOGIC;
S7_AXIS_TLAST : IN STD_LOGIC;
S7_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S7_AXIS_TVALID : IN STD_LOGIC;
S7_AXIS_TREADY : OUT STD_LOGIC;
S8_AXIS_TLAST : IN STD_LOGIC;
S8_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S8_AXIS_TVALID : IN STD_LOGIC;
S8_AXIS_TREADY : OUT STD_LOGIC;
S9_AXIS_TLAST : IN STD_LOGIC;
S9_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S9_AXIS_TVALID : IN STD_LOGIC;
S9_AXIS_TREADY : OUT STD_LOGIC;
S10_AXIS_TLAST : IN STD_LOGIC;
S10_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S10_AXIS_TVALID : IN STD_LOGIC;
S10_AXIS_TREADY : OUT STD_LOGIC;
S11_AXIS_TLAST : IN STD_LOGIC;
S11_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S11_AXIS_TVALID : IN STD_LOGIC;
S11_AXIS_TREADY : OUT STD_LOGIC;
S12_AXIS_TLAST : IN STD_LOGIC;
S12_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S12_AXIS_TVALID : IN STD_LOGIC;
S12_AXIS_TREADY : OUT STD_LOGIC;
S13_AXIS_TLAST : IN STD_LOGIC;
S13_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S13_AXIS_TVALID : IN STD_LOGIC;
S13_AXIS_TREADY : OUT STD_LOGIC;
S14_AXIS_TLAST : IN STD_LOGIC;
S14_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S14_AXIS_TVALID : IN STD_LOGIC;
S14_AXIS_TREADY : OUT STD_LOGIC;
S15_AXIS_TLAST : IN STD_LOGIC;
S15_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S15_AXIS_TVALID : IN STD_LOGIC;
S15_AXIS_TREADY : OUT STD_LOGIC;
M_AXI_IC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWLOCK : OUT STD_LOGIC;
M_AXI_IC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWVALID : OUT STD_LOGIC;
M_AXI_IC_AWREADY : IN STD_LOGIC;
M_AXI_IC_AWUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_AWDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWSNOOP : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_WLAST : OUT STD_LOGIC;
M_AXI_IC_WVALID : OUT STD_LOGIC;
M_AXI_IC_WREADY : IN STD_LOGIC;
M_AXI_IC_WUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_BVALID : IN STD_LOGIC;
M_AXI_IC_BREADY : OUT STD_LOGIC;
M_AXI_IC_BUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_WACK : OUT STD_LOGIC;
M_AXI_IC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARLOCK : OUT STD_LOGIC;
M_AXI_IC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARVALID : OUT STD_LOGIC;
M_AXI_IC_ARREADY : IN STD_LOGIC;
M_AXI_IC_ARUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_ARDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARSNOOP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RLAST : IN STD_LOGIC;
M_AXI_IC_RVALID : IN STD_LOGIC;
M_AXI_IC_RREADY : OUT STD_LOGIC;
M_AXI_IC_RUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RACK : OUT STD_LOGIC;
M_AXI_IC_ACVALID : IN STD_LOGIC;
M_AXI_IC_ACADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ACSNOOP : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ACPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ACREADY : OUT STD_LOGIC;
M_AXI_IC_CRVALID : OUT STD_LOGIC;
M_AXI_IC_CRRESP : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_CRREADY : IN STD_LOGIC;
M_AXI_IC_CDVALID : OUT STD_LOGIC;
M_AXI_IC_CDDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_CDLAST : OUT STD_LOGIC;
M_AXI_IC_CDREADY : IN STD_LOGIC;
M_AXI_DC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWLOCK : OUT STD_LOGIC;
M_AXI_DC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWVALID : OUT STD_LOGIC;
M_AXI_DC_AWREADY : IN STD_LOGIC;
M_AXI_DC_AWUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_AWDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWSNOOP : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_WLAST : OUT STD_LOGIC;
M_AXI_DC_WVALID : OUT STD_LOGIC;
M_AXI_DC_WREADY : IN STD_LOGIC;
M_AXI_DC_WUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BVALID : IN STD_LOGIC;
M_AXI_DC_BREADY : OUT STD_LOGIC;
M_AXI_DC_BUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_WACK : OUT STD_LOGIC;
M_AXI_DC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARLOCK : OUT STD_LOGIC;
M_AXI_DC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARVALID : OUT STD_LOGIC;
M_AXI_DC_ARREADY : IN STD_LOGIC;
M_AXI_DC_ARUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_ARDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARSNOOP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RLAST : IN STD_LOGIC;
M_AXI_DC_RVALID : IN STD_LOGIC;
M_AXI_DC_RREADY : OUT STD_LOGIC;
M_AXI_DC_RUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RACK : OUT STD_LOGIC;
M_AXI_DC_ACVALID : IN STD_LOGIC;
M_AXI_DC_ACADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ACSNOOP : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ACPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ACREADY : OUT STD_LOGIC;
M_AXI_DC_CRVALID : OUT STD_LOGIC;
M_AXI_DC_CRRESP : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_CRREADY : IN STD_LOGIC;
M_AXI_DC_CDVALID : OUT STD_LOGIC;
M_AXI_DC_CDDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_CDLAST : OUT STD_LOGIC;
M_AXI_DC_CDREADY : IN STD_LOGIC
);
END COMPONENT MicroBlaze;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF Reset: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt_Address: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ADDRESS";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt_Ack: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ACK";
ATTRIBUTE X_INTERFACE_INFO OF Instr_Addr: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF Instr: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF IFetch: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF I_AS: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF IReady: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READY";
ATTRIBUTE X_INTERFACE_INFO OF IWAIT: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF ICE: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB CE";
ATTRIBUTE X_INTERFACE_INFO OF IUE: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Data_Addr: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF Data_Read: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Data_Write: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF D_AS: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF Read_Strobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF Write_Strobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF DReady: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READY";
ATTRIBUTE X_INTERFACE_INFO OF DWait: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF DCE: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB CE";
ATTRIBUTE X_INTERFACE_INFO OF DUE: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Byte_Enable: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB BE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RREADY";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Clk: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG CLK";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDI: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG TDI";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDO: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG TDO";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Reg_En: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG REG_EN";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Shift: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG SHIFT";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Capture: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG CAPTURE";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Update: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG UPDATE";
ATTRIBUTE X_INTERFACE_INFO OF Debug_Rst: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG RST";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Disable: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG DISABLE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RREADY";
BEGIN
U0 : MicroBlaze
GENERIC MAP (
C_SCO => 0,
C_FREQ => 100000000,
C_USE_CONFIG_RESET => 0,
C_NUM_SYNC_FF_CLK => 2,
C_NUM_SYNC_FF_CLK_IRQ => 1,
C_NUM_SYNC_FF_CLK_DEBUG => 2,
C_NUM_SYNC_FF_DBG_CLK => 1,
C_FAULT_TOLERANT => 0,
C_ECC_USE_CE_EXCEPTION => 0,
C_LOCKSTEP_SLAVE => 0,
C_LOCKSTEP_MASTER => 0,
C_ENDIANNESS => 1,
C_FAMILY => "artix7",
C_DATA_SIZE => 32,
C_INSTR_SIZE => 32,
C_IADDR_SIZE => 32,
C_DADDR_SIZE => 32,
C_INSTANCE => "system_microblaze_0_0",
C_AVOID_PRIMITIVES => 0,
C_AREA_OPTIMIZED => 0,
C_OPTIMIZATION => 0,
C_INTERCONNECT => 2,
C_BASE_VECTORS => X"0000000000000000",
C_M_AXI_DP_THREAD_ID_WIDTH => 1,
C_M_AXI_DP_DATA_WIDTH => 32,
C_M_AXI_DP_ADDR_WIDTH => 32,
C_M_AXI_DP_EXCLUSIVE_ACCESS => 0,
C_M_AXI_D_BUS_EXCEPTION => 0,
C_M_AXI_IP_THREAD_ID_WIDTH => 1,
C_M_AXI_IP_DATA_WIDTH => 32,
C_M_AXI_IP_ADDR_WIDTH => 32,
C_M_AXI_I_BUS_EXCEPTION => 0,
C_D_LMB => 1,
C_D_AXI => 1,
C_I_LMB => 1,
C_I_AXI => 0,
C_USE_MSR_INSTR => 0,
C_USE_PCMP_INSTR => 0,
C_USE_BARREL => 0,
C_USE_DIV => 0,
C_USE_HW_MUL => 0,
C_USE_FPU => 0,
C_USE_REORDER_INSTR => 1,
C_UNALIGNED_EXCEPTIONS => 0,
C_ILL_OPCODE_EXCEPTION => 0,
C_DIV_ZERO_EXCEPTION => 0,
C_FPU_EXCEPTION => 0,
C_FSL_LINKS => 0,
C_USE_EXTENDED_FSL_INSTR => 0,
C_FSL_EXCEPTION => 0,
C_USE_STACK_PROTECTION => 0,
C_IMPRECISE_EXCEPTIONS => 0,
C_USE_INTERRUPT => 2,
C_USE_EXT_BRK => 0,
C_USE_EXT_NM_BRK => 0,
C_USE_NON_SECURE => 0,
C_USE_MMU => 0,
C_MMU_DTLB_SIZE => 4,
C_MMU_ITLB_SIZE => 2,
C_MMU_TLB_ACCESS => 3,
C_MMU_ZONES => 16,
C_MMU_PRIVILEGED_INSTR => 0,
C_USE_BRANCH_TARGET_CACHE => 0,
C_BRANCH_TARGET_CACHE_SIZE => 0,
C_PC_WIDTH => 32,
C_PVR => 0,
C_PVR_USER1 => X"00",
C_PVR_USER2 => X"00000000",
C_DYNAMIC_BUS_SIZING => 0,
C_RESET_MSR => X"00000000",
C_OPCODE_0x0_ILLEGAL => 0,
C_DEBUG_ENABLED => 1,
C_DEBUG_INTERFACE => 0,
C_NUMBER_OF_PC_BRK => 1,
C_NUMBER_OF_RD_ADDR_BRK => 0,
C_NUMBER_OF_WR_ADDR_BRK => 0,
C_DEBUG_EVENT_COUNTERS => 5,
C_DEBUG_LATENCY_COUNTERS => 1,
C_DEBUG_COUNTER_WIDTH => 32,
C_DEBUG_TRACE_SIZE => 8192,
C_DEBUG_EXTERNAL_TRACE => 0,
C_DEBUG_PROFILE_SIZE => 0,
C_INTERRUPT_IS_EDGE => 0,
C_EDGE_IS_POSITIVE => 1,
C_ASYNC_INTERRUPT => 1,
C_ASYNC_WAKEUP => 3,
C_M0_AXIS_DATA_WIDTH => 32,
C_S0_AXIS_DATA_WIDTH => 32,
C_M1_AXIS_DATA_WIDTH => 32,
C_S1_AXIS_DATA_WIDTH => 32,
C_M2_AXIS_DATA_WIDTH => 32,
C_S2_AXIS_DATA_WIDTH => 32,
C_M3_AXIS_DATA_WIDTH => 32,
C_S3_AXIS_DATA_WIDTH => 32,
C_M4_AXIS_DATA_WIDTH => 32,
C_S4_AXIS_DATA_WIDTH => 32,
C_M5_AXIS_DATA_WIDTH => 32,
C_S5_AXIS_DATA_WIDTH => 32,
C_M6_AXIS_DATA_WIDTH => 32,
C_S6_AXIS_DATA_WIDTH => 32,
C_M7_AXIS_DATA_WIDTH => 32,
C_S7_AXIS_DATA_WIDTH => 32,
C_M8_AXIS_DATA_WIDTH => 32,
C_S8_AXIS_DATA_WIDTH => 32,
C_M9_AXIS_DATA_WIDTH => 32,
C_S9_AXIS_DATA_WIDTH => 32,
C_M10_AXIS_DATA_WIDTH => 32,
C_S10_AXIS_DATA_WIDTH => 32,
C_M11_AXIS_DATA_WIDTH => 32,
C_S11_AXIS_DATA_WIDTH => 32,
C_M12_AXIS_DATA_WIDTH => 32,
C_S12_AXIS_DATA_WIDTH => 32,
C_M13_AXIS_DATA_WIDTH => 32,
C_S13_AXIS_DATA_WIDTH => 32,
C_M14_AXIS_DATA_WIDTH => 32,
C_S14_AXIS_DATA_WIDTH => 32,
C_M15_AXIS_DATA_WIDTH => 32,
C_S15_AXIS_DATA_WIDTH => 32,
C_ICACHE_BASEADDR => X"0000000080000000",
C_ICACHE_HIGHADDR => X"000000008FFFFFFF",
C_USE_ICACHE => 1,
C_ALLOW_ICACHE_WR => 1,
C_ADDR_TAG_BITS => 14,
C_CACHE_BYTE_SIZE => 16384,
C_ICACHE_LINE_LEN => 4,
C_ICACHE_ALWAYS_USED => 1,
C_ICACHE_STREAMS => 0,
C_ICACHE_VICTIMS => 0,
C_ICACHE_FORCE_TAG_LUTRAM => 0,
C_ICACHE_DATA_WIDTH => 0,
C_M_AXI_IC_THREAD_ID_WIDTH => 1,
C_M_AXI_IC_DATA_WIDTH => 32,
C_M_AXI_IC_ADDR_WIDTH => 32,
C_M_AXI_IC_USER_VALUE => 31,
C_M_AXI_IC_AWUSER_WIDTH => 5,
C_M_AXI_IC_ARUSER_WIDTH => 5,
C_M_AXI_IC_WUSER_WIDTH => 1,
C_M_AXI_IC_RUSER_WIDTH => 1,
C_M_AXI_IC_BUSER_WIDTH => 1,
C_DCACHE_BASEADDR => X"0000000080000000",
C_DCACHE_HIGHADDR => X"000000008fffffff",
C_USE_DCACHE => 1,
C_ALLOW_DCACHE_WR => 1,
C_DCACHE_ADDR_TAG => 14,
C_DCACHE_BYTE_SIZE => 16384,
C_DCACHE_LINE_LEN => 4,
C_DCACHE_ALWAYS_USED => 1,
C_DCACHE_USE_WRITEBACK => 0,
C_DCACHE_VICTIMS => 0,
C_DCACHE_FORCE_TAG_LUTRAM => 0,
C_DCACHE_DATA_WIDTH => 0,
C_M_AXI_DC_THREAD_ID_WIDTH => 1,
C_M_AXI_DC_DATA_WIDTH => 32,
C_M_AXI_DC_ADDR_WIDTH => 32,
C_M_AXI_DC_EXCLUSIVE_ACCESS => 0,
C_M_AXI_DC_USER_VALUE => 31,
C_M_AXI_DC_AWUSER_WIDTH => 5,
C_M_AXI_DC_ARUSER_WIDTH => 5,
C_M_AXI_DC_WUSER_WIDTH => 1,
C_M_AXI_DC_RUSER_WIDTH => 1,
C_M_AXI_DC_BUSER_WIDTH => 1
)
PORT MAP (
Clk => Clk,
Reset => Reset,
Mb_Reset => '0',
Config_Reset => '0',
Scan_Reset => '0',
Scan_Reset_Sel => '0',
RAM_Static => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1024)),
Interrupt => Interrupt,
Interrupt_Address => Interrupt_Address,
Interrupt_Ack => Interrupt_Ack,
Ext_BRK => '0',
Ext_NM_BRK => '0',
Dbg_Stop => '0',
Wakeup => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Reset_Mode => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Pause => '0',
Non_Secure => X"0",
LOCKSTEP_Slave_In => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4096)),
Instr_Addr => Instr_Addr,
Instr => Instr,
IFetch => IFetch,
I_AS => I_AS,
IReady => IReady,
IWAIT => IWAIT,
ICE => ICE,
IUE => IUE,
M_AXI_IP_AWREADY => '0',
M_AXI_IP_WREADY => '0',
M_AXI_IP_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IP_BRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_IP_BVALID => '0',
M_AXI_IP_ARREADY => '0',
M_AXI_IP_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IP_RDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_IP_RRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_IP_RLAST => '0',
M_AXI_IP_RVALID => '0',
Data_Addr => Data_Addr,
Data_Read => Data_Read,
Data_Write => Data_Write,
D_AS => D_AS,
Read_Strobe => Read_Strobe,
Write_Strobe => Write_Strobe,
DReady => DReady,
DWait => DWait,
DCE => DCE,
DUE => DUE,
Byte_Enable => Byte_Enable,
M_AXI_DP_AWADDR => M_AXI_DP_AWADDR,
M_AXI_DP_AWPROT => M_AXI_DP_AWPROT,
M_AXI_DP_AWVALID => M_AXI_DP_AWVALID,
M_AXI_DP_AWREADY => M_AXI_DP_AWREADY,
M_AXI_DP_WDATA => M_AXI_DP_WDATA,
M_AXI_DP_WSTRB => M_AXI_DP_WSTRB,
M_AXI_DP_WVALID => M_AXI_DP_WVALID,
M_AXI_DP_WREADY => M_AXI_DP_WREADY,
M_AXI_DP_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DP_BRESP => M_AXI_DP_BRESP,
M_AXI_DP_BVALID => M_AXI_DP_BVALID,
M_AXI_DP_BREADY => M_AXI_DP_BREADY,
M_AXI_DP_ARADDR => M_AXI_DP_ARADDR,
M_AXI_DP_ARPROT => M_AXI_DP_ARPROT,
M_AXI_DP_ARVALID => M_AXI_DP_ARVALID,
M_AXI_DP_ARREADY => M_AXI_DP_ARREADY,
M_AXI_DP_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DP_RDATA => M_AXI_DP_RDATA,
M_AXI_DP_RRESP => M_AXI_DP_RRESP,
M_AXI_DP_RLAST => '0',
M_AXI_DP_RVALID => M_AXI_DP_RVALID,
M_AXI_DP_RREADY => M_AXI_DP_RREADY,
Dbg_Clk => Dbg_Clk,
Dbg_TDI => Dbg_TDI,
Dbg_TDO => Dbg_TDO,
Dbg_Reg_En => Dbg_Reg_En,
Dbg_Shift => Dbg_Shift,
Dbg_Capture => Dbg_Capture,
Dbg_Update => Dbg_Update,
Dbg_Trig_Ack_In => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Out => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trace_Clk => '0',
Dbg_Trace_Ready => '0',
Debug_Rst => Debug_Rst,
Dbg_Disable => Dbg_Disable,
Dbg_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 13)),
Dbg_AWVALID => '0',
Dbg_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_WVALID => '0',
Dbg_BREADY => '0',
Dbg_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 13)),
Dbg_ARVALID => '0',
Dbg_RREADY => '0',
DEBUG_ACLK => '0',
DEBUG_ARESETN => '0',
M0_AXIS_TREADY => '0',
M1_AXIS_TREADY => '0',
M2_AXIS_TREADY => '0',
M3_AXIS_TREADY => '0',
M4_AXIS_TREADY => '0',
M5_AXIS_TREADY => '0',
M6_AXIS_TREADY => '0',
M7_AXIS_TREADY => '0',
M8_AXIS_TREADY => '0',
M9_AXIS_TREADY => '0',
M10_AXIS_TREADY => '0',
M11_AXIS_TREADY => '0',
M12_AXIS_TREADY => '0',
M13_AXIS_TREADY => '0',
M14_AXIS_TREADY => '0',
M15_AXIS_TREADY => '0',
S0_AXIS_TLAST => '0',
S0_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S0_AXIS_TVALID => '0',
S1_AXIS_TLAST => '0',
S1_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S1_AXIS_TVALID => '0',
S2_AXIS_TLAST => '0',
S2_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S2_AXIS_TVALID => '0',
S3_AXIS_TLAST => '0',
S3_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S3_AXIS_TVALID => '0',
S4_AXIS_TLAST => '0',
S4_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S4_AXIS_TVALID => '0',
S5_AXIS_TLAST => '0',
S5_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S5_AXIS_TVALID => '0',
S6_AXIS_TLAST => '0',
S6_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S6_AXIS_TVALID => '0',
S7_AXIS_TLAST => '0',
S7_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S7_AXIS_TVALID => '0',
S8_AXIS_TLAST => '0',
S8_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S8_AXIS_TVALID => '0',
S9_AXIS_TLAST => '0',
S9_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S9_AXIS_TVALID => '0',
S10_AXIS_TLAST => '0',
S10_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S10_AXIS_TVALID => '0',
S11_AXIS_TLAST => '0',
S11_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S11_AXIS_TVALID => '0',
S12_AXIS_TLAST => '0',
S12_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S12_AXIS_TVALID => '0',
S13_AXIS_TLAST => '0',
S13_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S13_AXIS_TVALID => '0',
S14_AXIS_TLAST => '0',
S14_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S14_AXIS_TVALID => '0',
S15_AXIS_TLAST => '0',
S15_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S15_AXIS_TVALID => '0',
M_AXI_IC_AWID => M_AXI_IC_AWID,
M_AXI_IC_AWADDR => M_AXI_IC_AWADDR,
M_AXI_IC_AWLEN => M_AXI_IC_AWLEN,
M_AXI_IC_AWSIZE => M_AXI_IC_AWSIZE,
M_AXI_IC_AWBURST => M_AXI_IC_AWBURST,
M_AXI_IC_AWLOCK => M_AXI_IC_AWLOCK,
M_AXI_IC_AWCACHE => M_AXI_IC_AWCACHE,
M_AXI_IC_AWPROT => M_AXI_IC_AWPROT,
M_AXI_IC_AWQOS => M_AXI_IC_AWQOS,
M_AXI_IC_AWVALID => M_AXI_IC_AWVALID,
M_AXI_IC_AWREADY => M_AXI_IC_AWREADY,
M_AXI_IC_WDATA => M_AXI_IC_WDATA,
M_AXI_IC_WSTRB => M_AXI_IC_WSTRB,
M_AXI_IC_WLAST => M_AXI_IC_WLAST,
M_AXI_IC_WVALID => M_AXI_IC_WVALID,
M_AXI_IC_WREADY => M_AXI_IC_WREADY,
M_AXI_IC_BID => M_AXI_IC_BID,
M_AXI_IC_BRESP => M_AXI_IC_BRESP,
M_AXI_IC_BVALID => M_AXI_IC_BVALID,
M_AXI_IC_BREADY => M_AXI_IC_BREADY,
M_AXI_IC_BUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IC_ARID => M_AXI_IC_ARID,
M_AXI_IC_ARADDR => M_AXI_IC_ARADDR,
M_AXI_IC_ARLEN => M_AXI_IC_ARLEN,
M_AXI_IC_ARSIZE => M_AXI_IC_ARSIZE,
M_AXI_IC_ARBURST => M_AXI_IC_ARBURST,
M_AXI_IC_ARLOCK => M_AXI_IC_ARLOCK,
M_AXI_IC_ARCACHE => M_AXI_IC_ARCACHE,
M_AXI_IC_ARPROT => M_AXI_IC_ARPROT,
M_AXI_IC_ARQOS => M_AXI_IC_ARQOS,
M_AXI_IC_ARVALID => M_AXI_IC_ARVALID,
M_AXI_IC_ARREADY => M_AXI_IC_ARREADY,
M_AXI_IC_RID => M_AXI_IC_RID,
M_AXI_IC_RDATA => M_AXI_IC_RDATA,
M_AXI_IC_RRESP => M_AXI_IC_RRESP,
M_AXI_IC_RLAST => M_AXI_IC_RLAST,
M_AXI_IC_RVALID => M_AXI_IC_RVALID,
M_AXI_IC_RREADY => M_AXI_IC_RREADY,
M_AXI_IC_RUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IC_ACVALID => '0',
M_AXI_IC_ACADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_IC_ACSNOOP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
M_AXI_IC_ACPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
M_AXI_IC_CRREADY => '0',
M_AXI_IC_CDREADY => '0',
M_AXI_DC_AWID => M_AXI_DC_AWID,
M_AXI_DC_AWADDR => M_AXI_DC_AWADDR,
M_AXI_DC_AWLEN => M_AXI_DC_AWLEN,
M_AXI_DC_AWSIZE => M_AXI_DC_AWSIZE,
M_AXI_DC_AWBURST => M_AXI_DC_AWBURST,
M_AXI_DC_AWLOCK => M_AXI_DC_AWLOCK,
M_AXI_DC_AWCACHE => M_AXI_DC_AWCACHE,
M_AXI_DC_AWPROT => M_AXI_DC_AWPROT,
M_AXI_DC_AWQOS => M_AXI_DC_AWQOS,
M_AXI_DC_AWVALID => M_AXI_DC_AWVALID,
M_AXI_DC_AWREADY => M_AXI_DC_AWREADY,
M_AXI_DC_WDATA => M_AXI_DC_WDATA,
M_AXI_DC_WSTRB => M_AXI_DC_WSTRB,
M_AXI_DC_WLAST => M_AXI_DC_WLAST,
M_AXI_DC_WVALID => M_AXI_DC_WVALID,
M_AXI_DC_WREADY => M_AXI_DC_WREADY,
M_AXI_DC_BRESP => M_AXI_DC_BRESP,
M_AXI_DC_BID => M_AXI_DC_BID,
M_AXI_DC_BVALID => M_AXI_DC_BVALID,
M_AXI_DC_BREADY => M_AXI_DC_BREADY,
M_AXI_DC_BUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DC_ARID => M_AXI_DC_ARID,
M_AXI_DC_ARADDR => M_AXI_DC_ARADDR,
M_AXI_DC_ARLEN => M_AXI_DC_ARLEN,
M_AXI_DC_ARSIZE => M_AXI_DC_ARSIZE,
M_AXI_DC_ARBURST => M_AXI_DC_ARBURST,
M_AXI_DC_ARLOCK => M_AXI_DC_ARLOCK,
M_AXI_DC_ARCACHE => M_AXI_DC_ARCACHE,
M_AXI_DC_ARPROT => M_AXI_DC_ARPROT,
M_AXI_DC_ARQOS => M_AXI_DC_ARQOS,
M_AXI_DC_ARVALID => M_AXI_DC_ARVALID,
M_AXI_DC_ARREADY => M_AXI_DC_ARREADY,
M_AXI_DC_RID => M_AXI_DC_RID,
M_AXI_DC_RDATA => M_AXI_DC_RDATA,
M_AXI_DC_RRESP => M_AXI_DC_RRESP,
M_AXI_DC_RLAST => M_AXI_DC_RLAST,
M_AXI_DC_RVALID => M_AXI_DC_RVALID,
M_AXI_DC_RREADY => M_AXI_DC_RREADY,
M_AXI_DC_RUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DC_ACVALID => '0',
M_AXI_DC_ACADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_DC_ACSNOOP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
M_AXI_DC_ACPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
M_AXI_DC_CRREADY => '0',
M_AXI_DC_CDREADY => '0'
);
END system_microblaze_0_0_arch;
|
--------------------------------------------------------------------------------
-- Title : Transmitter FIFO with AxiStream interfaces
-- Version : 1.3
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_tx_client_fifo.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is a transmitter side FIFO for the design example
-- of the Tri-Mode Ethernet MAC core. AxiStream interfaces are used.
--
-- The FIFO is built around an Inferred Dual Port RAM,
-- giving a total memory capacity of 4096 bytes.
--
-- Valid frame data received from the user interface is written
-- into the Block RAM on the tx_fifo_aclkk. The FIFO will store
-- frames up to 4kbytes in length. If larger frames are written
-- to the FIFO, the AxiStream interface will accept the rest of the
-- frame, but that frame will be dropped by the FIFO and the
-- overflow signal will be asserted.
--
-- The FIFO is designed to work with a minimum frame length of 14
-- bytes.
--
-- When there is at least one complete frame in the FIFO, the MAC
-- transmitter AxiStream interface will be driven to request frame
-- transmission by placing the first byte of the frame onto
-- tx_axis_mac_tdata and by asserting tx_axis_mac_tvalid. The MAC will later
-- respond by asserting tx_axis_mac_tready. At this point the remaining
-- frame data is read out of the FIFO subject to tx_axis_mac_tready.
-- Data is read out of the FIFO on the tx_mac_aclk.
--
-- If the generic FULL_DUPLEX_ONLY is set to false, the FIFO will
-- requeue and retransmit frames as requested by the MAC. Once a
-- frame has been transmitted by the FIFO it is stored until the
-- possible retransmit window for that frame has expired.
--
-- The FIFO has been designed to operate with different clocks
-- on the write and read sides. The minimum write clock
-- frequency is the read clock frequency divided by 2.
--
-- The FIFO memory size can be increased by expanding the rd_addr
-- and wr_addr signal widths, to address further BRAMs.
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
-- Entity declaration for the Transmitter FIFO
--------------------------------------------------------------------------------
entity tri_mode_ethernet_mac_0_tx_client_fifo is
generic (
FULL_DUPLEX_ONLY : boolean := false);
port (
-- User-side (write-side) AxiStream interface
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
-- MAC-side (read-side) AxiStream interface
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
-- FIFO status and overflow indication,
-- synchronous to write-side (tx_user_aclk) interface
fifo_overflow : out std_logic;
fifo_status : out std_logic_vector(3 downto 0);
-- FIFO collision and retransmission requests from MAC
tx_collision : in std_logic;
tx_retransmit : in std_logic
);
end tri_mode_ethernet_mac_0_tx_client_fifo;
architecture RTL of tri_mode_ethernet_mac_0_tx_client_fifo is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
------------------------------------------------------------------------------
-- Component declaration for the synchronisation flip-flop pair
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the block RAM
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_bram_tdp
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 12
);
port (
-- Port A
a_clk : in std_logic;
a_rst : in std_logic;
a_wr : in std_logic;
a_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
a_din : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- Port B
b_clk : in std_logic;
b_en : in std_logic;
b_rst : in std_logic;
b_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
b_dout : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end component;
------------------------------------------------------------------------------
-- Define internal signals
------------------------------------------------------------------------------
-- Encoded read state machine states.
type rd_state_typ is (IDLE_s,
QUEUE1_s,
QUEUE2_s,
QUEUE3_s,
START_DATA1_s,
DATA_PRELOAD1_s,
DATA_PRELOAD2_s,
WAIT_HANDSHAKE_s,
FRAME_s,
HANDSHAKE_s,
FINISH_s,
DROP_ERR_s,
DROP_s,
RETRANSMIT_ERR_s,
RETRANSMIT_s);
signal rd_state : rd_state_typ;
signal rd_nxt_state : rd_state_typ;
-- Encoded write state machine states,
type wr_state_typ is (WAIT_s,
DATA_s,
EOF_s,
OVFLOW_s);
signal wr_state : wr_state_typ;
signal wr_nxt_state : wr_state_typ;
type data_pipe is array (0 to 1) of std_logic_vector(7 downto 0);
type cntl_pipe is array (0 to 1) of std_logic;
signal wr_eof_data_bram : std_logic_vector(8 downto 0);
signal wr_data_bram : std_logic_vector(7 downto 0);
signal wr_data_pipe : data_pipe;
signal wr_sof_pipe : cntl_pipe;
signal wr_eof_pipe : cntl_pipe;
signal wr_accept_pipe : cntl_pipe;
signal wr_accept_bram : std_logic;
signal wr_sof_int : std_logic;
signal wr_eof_bram : std_logic_vector(0 downto 0);
signal wr_eof_reg : std_logic;
signal wr_addr : unsigned(11 downto 0) := (others => '0');
signal wr_addr_inc : std_logic;
signal wr_start_addr_load : std_logic;
signal wr_addr_reload : std_logic;
signal wr_start_addr : unsigned(11 downto 0) := (others => '0');
signal wr_fifo_full : std_logic;
signal wr_en : std_logic;
signal wr_ovflow_dst_rdy : std_logic;
signal tx_axis_fifo_tready_int_n : std_logic;
signal data_count : unsigned(3 downto 0) := (others => '0');
signal frame_in_fifo : std_logic;
signal frames_in_fifo : std_logic;
signal frame_in_fifo_valid : std_logic;
signal frame_in_fifo_valid_tog : std_logic := '0';
signal frame_in_fifo_valid_sync : std_logic;
signal frame_in_fifo_valid_delay : std_logic;
signal rd_eof : std_logic;
signal rd_eof_pipe : std_logic;
signal rd_eof_reg : std_logic;
signal rd_addr : unsigned(11 downto 0) := (others => '0');
signal rd_addr_inc : std_logic;
signal rd_addr_reload : std_logic;
signal rd_eof_data_bram : std_logic_vector(8 downto 0);
signal rd_data_bram : std_logic_vector(7 downto 0);
signal rd_data_pipe : std_logic_vector(7 downto 0) := (others => '0');
signal rd_data_delay : std_logic_vector(7 downto 0) := (others => '0');
signal rd_eof_bram : std_logic_vector(0 downto 0);
signal rd_en : std_logic;
signal rd_tran_frame_tog : std_logic := '0';
signal wr_tran_frame_sync : std_logic;
signal wr_tran_frame_delay : std_logic := '0';
signal rd_retran_frame_tog : std_logic := '0';
signal wr_retran_frame_sync : std_logic;
signal wr_retran_frame_delay : std_logic := '0';
signal wr_store_frame : std_logic;
signal wr_eof_state : std_logic;
signal wr_eof_state_reg : std_logic;
signal wr_transmit_frame : std_logic;
signal wr_transmit_frame_delay : std_logic;
signal wr_retransmit_frame : std_logic;
signal wr_frames : unsigned(8 downto 0) := (others => '0');
signal wr_frame_in_fifo : std_logic;
signal wr_frames_in_fifo : std_logic;
signal rd_16_count : unsigned(3 downto 0) := (others => '0');
signal rd_txfer_en : std_logic;
signal rd_addr_txfer : unsigned(11 downto 0) := (others => '0');
signal rd_txfer_tog : std_logic := '0';
signal wr_txfer_tog_sync : std_logic;
signal wr_txfer_tog_delay : std_logic := '0';
signal wr_txfer_en : std_logic;
signal wr_rd_addr : unsigned(11 downto 0) := (others => '0');
signal wr_addr_diff : unsigned(11 downto 0) := (others => '0');
signal wr_fifo_status : unsigned(3 downto 0) := (others => '0');
signal rd_drop_frame : std_logic;
signal rd_retransmit : std_logic;
signal rd_start_addr : unsigned(11 downto 0) := (others => '0');
signal rd_start_addr_load : std_logic;
signal rd_start_addr_reload : std_logic;
signal rd_dec_addr : unsigned(11 downto 0) := (others => '0');
signal rd_transmit_frame : std_logic;
signal rd_retransmit_frame : std_logic;
signal rd_col_window_expire : std_logic;
signal rd_col_window_pipe : cntl_pipe;
signal wr_col_window_pipe : cntl_pipe;
signal wr_fifo_overflow : std_logic;
signal rd_slot_timer : unsigned(9 downto 0) := (others => '0');
signal wr_col_window_expire : std_logic;
signal rd_idle_state : std_logic;
signal tx_axis_mac_tdata_int_frame : std_logic_vector(7 downto 0);
signal tx_axis_mac_tdata_int_handshake : std_logic_vector(7 downto 0);
signal tx_axis_mac_tdata_int : std_logic_vector(7 downto 0) := (others => '0');
signal tx_axis_mac_tvalid_int_finish : std_logic;
signal tx_axis_mac_tvalid_int_droperr : std_logic;
signal tx_axis_mac_tvalid_int_retransmiterr : std_logic;
signal tx_axis_mac_tlast_int_frame_handshake : std_logic;
signal tx_axis_mac_tlast_int_finish : std_logic;
signal tx_axis_mac_tlast_int_droperr : std_logic;
signal tx_axis_mac_tlast_int_retransmiterr : std_logic;
signal tx_axis_mac_tuser_int_droperr : std_logic;
signal tx_axis_mac_tuser_int_retransmit : std_logic;
signal tx_fifo_reset : std_logic;
signal tx_mac_reset : std_logic;
-- Small delay for simulation purposes.
constant dly : time := 1 ps;
------------------------------------------------------------------------------
-- Attributes for FIFO simulation and synthesis
------------------------------------------------------------------------------
-- ASYNC_REG attributes added to simulate actual behaviour under
-- asynchronous operating conditions.
attribute ASYNC_REG : string;
attribute ASYNC_REG of wr_rd_addr : signal is "TRUE";
attribute ASYNC_REG of wr_col_window_pipe : signal is "TRUE";
------------------------------------------------------------------------------
-- Begin FIFO architecture
------------------------------------------------------------------------------
begin
-- invert reset sense as architecture is optimised for active high resets
tx_fifo_reset <= not tx_fifo_resetn;
tx_mac_reset <= not tx_mac_resetn;
------------------------------------------------------------------------------
-- Write state machine and control
------------------------------------------------------------------------------
-- Write state machine.
-- States are WAIT, DATA, EOF, OVFLOW.
-- Clock state to next state.
clock_wrs_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
wr_state <= WAIT_s after dly;
else
wr_state <= wr_nxt_state after dly;
end if;
end if;
end process clock_wrs_p;
-- Decode next state, combinitorial.
next_wrs_p : process(wr_state, wr_sof_pipe(1), wr_eof_pipe(0), wr_eof_pipe(1),
wr_eof_bram(0), wr_fifo_overflow, data_count)
begin
case wr_state is
when WAIT_s =>
if wr_sof_pipe(1) = '1' and wr_eof_pipe(1) = '0' then
wr_nxt_state <= DATA_s;
else
wr_nxt_state <= WAIT_s;
end if;
when DATA_s =>
-- Wait for the end of frame to be detected.
if wr_fifo_overflow = '1' and wr_eof_pipe(0) = '0'
and wr_eof_pipe(1) = '0' then
wr_nxt_state <= OVFLOW_s;
elsif wr_eof_pipe(1) = '1' then
if data_count(3 downto 2) /= "11" then
wr_nxt_state <= OVFLOW_s;
else
wr_nxt_state <= EOF_s;
end if;
else
wr_nxt_state <= DATA_s;
end if;
when EOF_s =>
-- If the start of frame is already in the pipe, a back-to-back frame
-- transmission has occured. Move straight back to frame state.
if wr_sof_pipe(1) = '1' and wr_eof_pipe(1) = '0' then
wr_nxt_state <= DATA_s;
elsif wr_eof_bram(0) = '1' then
wr_nxt_state <= WAIT_s;
else
wr_nxt_state <= EOF_s;
end if;
when OVFLOW_s =>
-- Wait until the end of frame is reached before clearing the overflow.
if wr_eof_bram(0) = '1' then
wr_nxt_state <= WAIT_s;
else
wr_nxt_state <= OVFLOW_s;
end if;
when others =>
wr_nxt_state <= WAIT_s;
end case;
end process;
-- small frame count - frames smaller than 10 bytes are problematic as the frame_in_fifo cannot
-- react quickly enough - empty detect could be used in the read domain but this doesn't fully cover all cases
-- the cleanest fix is to simply ignore frames smaller than 10 bytes
-- generate a counter which is cleaered on an sof and counts in data
data_count_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
data_count <= (others => '0') after dly;
else
if wr_sof_pipe(1) = '1' then
data_count <= (others => '0');
else
if data_count(3 downto 2) /= "11" then
data_count <= data_count + "0001";
end if;
end if;
end if;
end if;
end process data_count_p;
-- Decode output signals, combinatorial.
-- wr_en is used to enable the BRAM write and the address to increment.
wr_en <= '0' when wr_state = OVFLOW_s else wr_accept_bram;
wr_addr_inc <= wr_en;
wr_addr_reload <= '1' when wr_state = OVFLOW_s else '0';
wr_start_addr_load <= '1' when wr_state = EOF_s and wr_nxt_state = WAIT_s
else
'1' when wr_state = EOF_s and wr_nxt_state = DATA_s
else '0';
-- Pause the AxiStream handshake when the FIFO is full.
tx_axis_fifo_tready_int_n <= wr_ovflow_dst_rdy when wr_state = OVFLOW_s
else wr_fifo_full;
tx_axis_fifo_tready <= not tx_axis_fifo_tready_int_n;
-- Generate user overflow indicator.
fifo_overflow <= '1' when wr_state = OVFLOW_s else '0';
-- When in overflow and have captured ovflow EOF, set tx_axis_fifo_tready again.
p_ovflow_dst_rdy : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_ovflow_dst_rdy <= '0' after dly;
else
if wr_fifo_overflow = '1' and wr_state = DATA_s then
wr_ovflow_dst_rdy <= '0' after dly;
elsif tx_axis_fifo_tvalid = '1' and tx_axis_fifo_tlast = '1' then
wr_ovflow_dst_rdy <= '1' after dly;
end if;
end if;
end if;
end process;
-- EOF signals for use in overflow logic.
wr_eof_state <= '1' when wr_state = EOF_s else '0';
p_reg_eof_st : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_eof_state_reg <= '0' after dly;
else
wr_eof_state_reg <= wr_eof_state after dly;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Read state machine and control
------------------------------------------------------------------------------
-- Read state machine.
-- States are IDLE, QUEUE1, QUEUE2, QUEUE3, QUEUE_ACK, WAIT_ACK, FRAME,
-- HANDSHAKE, FINISH, DROP_ERR, DROP, RETRANSMIT_ERR, RETRANSMIT.
-- Clock state to next state.
clock_rds_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_state <= IDLE_s after dly;
else
rd_state <= rd_nxt_state after dly;
end if;
end if;
end process clock_rds_p;
------------------------------------------------------------------------------
-- Full duplex-only state machine.
gen_fd_sm : if (FULL_DUPLEX_ONLY = TRUE) generate
-- Decode next state, combinatorial.
next_rds_p : process(rd_state, frame_in_fifo, frames_in_fifo, frame_in_fifo_valid, rd_eof, rd_eof_reg, tx_axis_mac_tready)
begin
case rd_state is
when IDLE_s =>
-- If there is a frame in the FIFO, start to queue the new frame
-- to the output.
if (frame_in_fifo = '1' and frame_in_fifo_valid = '1') or frames_in_fifo = '1' then
rd_nxt_state <= QUEUE1_s;
else
rd_nxt_state <= IDLE_s;
end if;
-- Load the output pipeline, which takes three clock cycles.
when QUEUE1_s =>
rd_nxt_state <= QUEUE2_s;
when QUEUE2_s =>
rd_nxt_state <= QUEUE3_s;
when QUEUE3_s =>
rd_nxt_state <= START_DATA1_s;
when START_DATA1_s =>
-- The pipeline is full and the frame output starts now.
rd_nxt_state <= DATA_PRELOAD1_s;
when DATA_PRELOAD1_s =>
-- Await the tx_axis_mac_tready acknowledge before moving on.
if tx_axis_mac_tready = '1' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= DATA_PRELOAD1_s;
end if;
when FRAME_s =>
-- Read the frame out of the FIFO. If the MAC deasserts
-- tx_axis_mac_tready, stall in the handshake state. If the EOF
-- flag is encountered, move to the finish state.
if tx_axis_mac_tready = '0' then
rd_nxt_state <= HANDSHAKE_s;
elsif rd_eof = '1' then
rd_nxt_state <= FINISH_s;
else
rd_nxt_state <= FRAME_s;
end if;
when HANDSHAKE_s =>
-- Await tx_axis_mac_tready before continuing frame transmission.
-- If the EOF flag is encountered, move to the finish state.
if tx_axis_mac_tready = '1' and rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '0' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= HANDSHAKE_s;
end if;
when FINISH_s =>
-- Frame has finished. Assure that the MAC has accepted the final
-- byte by transitioning to idle only when tx_axis_mac_tready is high.
if tx_axis_mac_tready = '1' then
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= FINISH_s;
end if;
when others =>
rd_nxt_state <= IDLE_s;
end case;
end process next_rds_p;
end generate gen_fd_sm;
------------------------------------------------------------------------------
-- Full and half duplex state machine.
gen_hd_sm : if (FULL_DUPLEX_ONLY = FALSE) generate
-- Decode the next state, combinatorial.
next_rds_p : process(rd_state, frame_in_fifo, frames_in_fifo, frame_in_fifo_valid, rd_eof_reg, tx_axis_mac_tready,
rd_drop_frame, rd_retransmit)
begin
case rd_state is
when IDLE_s =>
-- If a retransmit request is detected then prepare to retransmit.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
-- If there is a frame in the FIFO, then queue the new frame to
-- the output.
elsif (frame_in_fifo = '1' and frame_in_fifo_valid = '1') or frames_in_fifo = '1' then
rd_nxt_state <= QUEUE1_s;
else
rd_nxt_state <= IDLE_s;
end if;
-- Load the output pipeline, which takes three clock cycles.
when QUEUE1_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
else
rd_nxt_state <= QUEUE2_s;
end if;
when QUEUE2_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
else
rd_nxt_state <= QUEUE3_s;
end if;
when QUEUE3_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
else
rd_nxt_state <= START_DATA1_s;
end if;
when START_DATA1_s =>
-- The pipeline is full and the frame output starts now.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
else
rd_nxt_state <= DATA_PRELOAD1_s;
end if;
when DATA_PRELOAD1_s =>
-- Await the tx_axis_mac_tready acknowledge before moving on.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
elsif tx_axis_mac_tready = '1' then
rd_nxt_state <= DATA_PRELOAD2_s;
else
rd_nxt_state <= DATA_PRELOAD1_s;
end if;
when DATA_PRELOAD2_s =>
-- If a collision-only request, then must drop the rest of the
-- current frame. If collision and retransmit, then prepare
-- to retransmit the frame.
if rd_drop_frame = '1' then
rd_nxt_state <= DROP_ERR_s;
elsif rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
-- Read the frame out of the FIFO. If the MAC deasserts
-- tx_axis_mac_tready, stall in the handshake state. If the EOF
-- flag is encountered, move to the finish state.
elsif tx_axis_mac_tready = '0' then
rd_nxt_state <= WAIT_HANDSHAKE_s;
elsif rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
else
rd_nxt_state <= DATA_PRELOAD2_s;
end if;
when WAIT_HANDSHAKE_s =>
-- Await tx_axis_mac_tready before continuing frame transmission.
-- If the EOF flag is encountered, move to the finish state.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '0' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= WAIT_HANDSHAKE_s;
end if;
when FRAME_s =>
-- If a collision-only request, then must drop the rest of the
-- current frame. If a collision and retransmit, then prepare
-- to retransmit the frame.
if rd_drop_frame = '1' then
rd_nxt_state <= DROP_ERR_s;
elsif rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
-- Read the frame out of the FIFO. If the MAC deasserts
-- tx_axis_mac_tready, stall in the handshake state. If the EOF
-- flag is encountered, move to the finish state.
elsif tx_axis_mac_tready = '0' then
rd_nxt_state <= HANDSHAKE_s;
elsif rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
else
rd_nxt_state <= FRAME_s;
end if;
when HANDSHAKE_s =>
-- Await tx_axis_mac_tready before continuing frame transmission.
-- If the EOF flag is encountered, move to the finish state.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '0' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= HANDSHAKE_s;
end if;
when FINISH_s =>
-- Frame has finished. Assure that the MAC has accepted the final
-- byte by transitioning to idle only when tx_axis_mac_tready is high.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
elsif tx_axis_mac_tready = '1' then
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= FINISH_s;
end if;
when DROP_ERR_s =>
-- FIFO is ready to drop the frame. Assure that the MAC has
-- accepted the final byte and err signal before dropping.
if tx_axis_mac_tready = '1' then
rd_nxt_state <= DROP_s;
else
rd_nxt_state <= DROP_ERR_s;
end if;
when DROP_s =>
-- Wait until rest of frame has been cleared.
if rd_eof_reg = '1' then
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= DROP_s;
end if;
when RETRANSMIT_ERR_s =>
-- FIFO is ready to retransmit the frame. Assure that the MAC has
-- accepted the final byte and err signal before retransmitting.
if tx_axis_mac_tready = '1' then
rd_nxt_state <= RETRANSMIT_s;
else
rd_nxt_state <= RETRANSMIT_ERR_s;
end if;
when RETRANSMIT_s =>
-- Reload the data pipeline from the start of the frame.
rd_nxt_state <= QUEUE1_s;
when others =>
rd_nxt_state <= IDLE_s;
end case;
end process next_rds_p;
end generate gen_hd_sm;
-- Combinatorially select tdata candidates.
tx_axis_mac_tdata_int_frame <= tx_axis_mac_tdata_int when rd_nxt_state = HANDSHAKE_s or rd_nxt_state = WAIT_HANDSHAKE_s
else rd_data_pipe;
tx_axis_mac_tdata_int_handshake <= rd_data_pipe when rd_nxt_state = FINISH_s
else tx_axis_mac_tdata_int;
tx_axis_mac_tdata <= tx_axis_mac_tdata_int;
-- Decode output tdata based on current and next read state.
rd_data_decode_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_nxt_state = FRAME_s or rd_nxt_state = DATA_PRELOAD2_s then
tx_axis_mac_tdata_int <= rd_data_pipe after dly;
elsif (rd_nxt_state = RETRANSMIT_ERR_s or rd_nxt_state = DROP_ERR_s)
then tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int after dly;
else
case rd_state is
when START_DATA1_s =>
tx_axis_mac_tdata_int <= rd_data_pipe after dly;
when FRAME_s | DATA_PRELOAD2_s =>
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int_frame after dly;
when HANDSHAKE_s | WAIT_HANDSHAKE_s =>
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int_handshake after dly;
when others =>
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int after dly;
end case;
end if;
end if;
end process rd_data_decode_p;
-- Combinatorially select tvalid candidates.
tx_axis_mac_tvalid_int_finish <= '0' when rd_nxt_state = IDLE_s
else '1';
tx_axis_mac_tvalid_int_droperr <= '0' when rd_nxt_state = DROP_s
else '1';
tx_axis_mac_tvalid_int_retransmiterr <= '0' when rd_nxt_state = RETRANSMIT_s
else '1';
-- Decode output tvalid based on current and next read state.
rd_dv_decode_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_nxt_state = FRAME_s or rd_nxt_state = DATA_PRELOAD2_s then
tx_axis_mac_tvalid <= '1' after dly;
elsif (rd_nxt_state = RETRANSMIT_ERR_s or rd_nxt_state = DROP_ERR_s)
then tx_axis_mac_tvalid <= '1' after dly;
else
case rd_state is
when START_DATA1_s =>
tx_axis_mac_tvalid <= '1' after dly;
when DATA_PRELOAD1_s =>
tx_axis_mac_tvalid <= '1' after dly;
when FRAME_s | DATA_PRELOAD2_s =>
tx_axis_mac_tvalid <= '1' after dly;
when HANDSHAKE_s | WAIT_HANDSHAKE_s =>
tx_axis_mac_tvalid <= '1' after dly;
when FINISH_s =>
tx_axis_mac_tvalid <= tx_axis_mac_tvalid_int_finish after dly;
when DROP_ERR_s =>
tx_axis_mac_tvalid <= tx_axis_mac_tvalid_int_droperr after dly;
when RETRANSMIT_ERR_s =>
tx_axis_mac_tvalid <= tx_axis_mac_tvalid_int_retransmiterr after dly;
when others =>
tx_axis_mac_tvalid <= '0' after dly;
end case;
end if;
end if;
end process rd_dv_decode_p;
-- Combinatorially select tlast candidates.
tx_axis_mac_tlast_int_frame_handshake <= rd_eof_reg when rd_nxt_state = FINISH_s
else '0';
tx_axis_mac_tlast_int_finish <= '0' when rd_nxt_state = IDLE_s
else rd_eof_reg;
tx_axis_mac_tlast_int_droperr <= '0' when rd_nxt_state = DROP_s
else '1';
tx_axis_mac_tlast_int_retransmiterr <= '0' when rd_nxt_state = RETRANSMIT_s
else '1';
-- Decode output tlast based on current and next read state.
rd_last_decode_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_nxt_state = FRAME_s or rd_nxt_state = DATA_PRELOAD2_s then
tx_axis_mac_tlast <= rd_eof after dly;
elsif (rd_nxt_state = RETRANSMIT_ERR_s or rd_nxt_state = DROP_ERR_s)
then tx_axis_mac_tlast <= '1' after dly;
else
case rd_state is
when DATA_PRELOAD1_s =>
tx_axis_mac_tlast <= rd_eof after dly;
when FRAME_s | DATA_PRELOAD2_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_frame_handshake after dly;
when HANDSHAKE_s | WAIT_HANDSHAKE_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_frame_handshake after dly;
when FINISH_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_finish after dly;
when DROP_ERR_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_droperr after dly;
when RETRANSMIT_ERR_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_retransmiterr after dly;
when others =>
tx_axis_mac_tlast <= '0' after dly;
end case;
end if;
end if;
end process rd_last_decode_p;
-- Combinatorially select tuser candidates.
tx_axis_mac_tuser_int_droperr <= '0' when rd_nxt_state = DROP_s
else '1';
tx_axis_mac_tuser_int_retransmit <= '0' when rd_nxt_state = RETRANSMIT_s
else '1';
-- Decode output tuser based on current and next read state.
rd_user_decode_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if (rd_nxt_state = RETRANSMIT_ERR_s or rd_nxt_state = DROP_ERR_s)
then tx_axis_mac_tuser <= '1' after dly;
else
case rd_state is
when DROP_ERR_s =>
tx_axis_mac_tuser <= tx_axis_mac_tuser_int_droperr after dly;
when RETRANSMIT_ERR_s =>
tx_axis_mac_tuser <= tx_axis_mac_tuser_int_retransmit after dly;
when others =>
tx_axis_mac_tuser <= '0' after dly;
end case;
end if;
end if;
end process rd_user_decode_p;
------------------------------------------------------------------------------
-- Decode full duplex-only control signals.
gen_fd_decode : if (FULL_DUPLEX_ONLY = TRUE) generate
-- rd_en is used to enable the BRAM read and load the output pipeline.
rd_en <= '0' when rd_state = IDLE_s else
'1' when rd_nxt_state = FRAME_s else
'0' when (rd_state = FRAME_s and rd_nxt_state = HANDSHAKE_s) else
'0' when rd_nxt_state = HANDSHAKE_s else
'0' when rd_state = FINISH_s else
'0' when rd_state = DATA_PRELOAD1_s else '1';
-- When the BRAM is being read, enable the read address to be incremented.
rd_addr_inc <= rd_en;
rd_addr_reload <= '1' when rd_state /= FINISH_s and rd_nxt_state = FINISH_s
else '0';
-- Transmit frame pulse must never be more frequent than once per 64 clocks to
-- allow toggle to cross clock domain.
rd_transmit_frame <= '1' when rd_state = DATA_PRELOAD1_s and rd_nxt_state = FRAME_s
else '0';
-- Unused for full duplex only.
rd_start_addr_reload <= '0';
rd_start_addr_load <= '0';
rd_retransmit_frame <= '0';
end generate gen_fd_decode;
------------------------------------------------------------------------------
-- Decode full and half duplex control signals.
gen_hd_decode : if (FULL_DUPLEX_ONLY = FALSE) generate
-- rd_en is used to enable the BRAM read and load the output pipeline.
rd_en <= '0' when rd_state = IDLE_s else
'0' when rd_nxt_state = DROP_ERR_s else
'0' when (rd_nxt_state = DROP_s and rd_eof = '1') else
'1' when rd_nxt_state = FRAME_s or rd_nxt_state = DATA_PRELOAD2_s else
'0' when (rd_state = DATA_PRELOAD2_s and rd_nxt_state = WAIT_HANDSHAKE_s) else
'0' when (rd_state = FRAME_s and rd_nxt_state = HANDSHAKE_s) else
'0' when (rd_nxt_state = HANDSHAKE_s or rd_nxt_state = WAIT_HANDSHAKE_s) else
'0' when rd_state = FINISH_s else
'0' when rd_state = RETRANSMIT_ERR_s else
'0' when rd_state = RETRANSMIT_s else
'0' when rd_state = DATA_PRELOAD1_s else '1';
-- When the BRAM is being read, enable the read address to be incremented.
rd_addr_inc <= rd_en;
rd_addr_reload <= '1' when rd_state /= FINISH_s and rd_nxt_state = FINISH_s
else
'1' when rd_state = DROP_s and rd_nxt_state = IDLE_s
else '0';
-- Assertion indicates that the starting address must be reloaded to enable
-- the current frame to be retransmitted.
rd_start_addr_reload <= '1' when rd_state = RETRANSMIT_s else '0';
rd_start_addr_load <= '1' when rd_state= WAIT_HANDSHAKE_s and rd_nxt_state = FRAME_s
else
'1' when rd_col_window_expire = '1' else '0';
-- Transmit frame pulse must never be more frequent than once per 64 clocks to
-- allow toggle to cross clock domain.
rd_transmit_frame <= '1' when rd_state = WAIT_HANDSHAKE_s and rd_nxt_state = FRAME_s
else '0';
-- Retransmit frame pulse must never be more frequent than once per 16 clocks
-- to allow toggle to cross clock domain.
rd_retransmit_frame <= '1' when rd_state = RETRANSMIT_s else '0';
end generate gen_hd_decode; -- half duplex control signals
------------------------------------------------------------------------------
-- Frame count
-- We need to maintain a count of frames in the FIFO, so that we know when a
-- frame is available for transmission. The counter must be held on the write
-- clock domain as this is the faster clock if they differ.
------------------------------------------------------------------------------
-- A frame has been written to the FIFO.
wr_store_frame <= '1' when wr_state = EOF_s and wr_nxt_state /= EOF_s
else '0';
-- Generate a toggle to indicate when a frame has been transmitted by the FIFO.
p_rd_trans_tog : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if rd_transmit_frame = '1' then
rd_tran_frame_tog <= not rd_tran_frame_tog after dly;
end if;
end if;
end process;
-- Synchronize the read transmit frame signal into the write clock domain.
resync_rd_tran_frame_tog : tri_mode_ethernet_mac_0_sync_block
port map (
clk => tx_fifo_aclk,
data_in => rd_tran_frame_tog,
data_out => wr_tran_frame_sync
);
-- Edge-detect of the resynchronized transmit frame signal.
p_delay_wr_trans : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
wr_tran_frame_delay <= wr_tran_frame_sync after dly;
end if;
end process p_delay_wr_trans;
p_sync_wr_trans : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_transmit_frame <= '0' after dly;
else
-- Edge detector
if (wr_tran_frame_delay xor wr_tran_frame_sync) = '1' then
wr_transmit_frame <= '1' after dly;
else
wr_transmit_frame <= '0' after dly;
end if;
end if;
end if;
end process p_sync_wr_trans;
------------------------------------------------------------------------------
-- Full duplex-only frame count.
gen_fd_count : if (FULL_DUPLEX_ONLY = TRUE) generate
-- Count the number of frames in the FIFO. The counter is incremented when a
-- frame is stored and decremented when a frame is transmitted. Need to keep
-- the counter on the write clock as this is the fastest clock if they differ.
p_wr_frames : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_frames <= (others => '0') after dly;
else
if (wr_store_frame and not wr_transmit_frame) = '1' then
wr_frames <= wr_frames + 1 after dly;
elsif (not wr_store_frame and wr_transmit_frame) = '1' then
wr_frames <= wr_frames - 1 after dly;
end if;
end if;
end if;
end process p_wr_frames;
end generate gen_fd_count;
------------------------------------------------------------------------------
-- Full and half duplex frame count.
gen_hd_count : if (FULL_DUPLEX_ONLY = FALSE) generate
-- Generate a toggle to indicate when a frame has been retransmitted from
-- the FIFO.
p_rd_retran_tog : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if rd_retransmit_frame = '1' then
rd_retran_frame_tog <= not rd_retran_frame_tog after dly;
end if;
end if;
end process;
-- Synchronize the read retransmit frame signal into the write clock domain.
resync_rd_tran_frame_tog : tri_mode_ethernet_mac_0_sync_block
port map (
clk => tx_fifo_aclk,
data_in => rd_retran_frame_tog,
data_out => wr_retran_frame_sync
);
-- Edge detect of the resynchronized read transmit frame signal.
p_delay_wr_trans : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
wr_retran_frame_delay <= wr_retran_frame_sync after dly;
end if;
end process p_delay_wr_trans;
p_sync_wr_trans : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_retransmit_frame <= '0' after dly;
else
-- Edge detector
if (wr_retran_frame_delay xor wr_retran_frame_sync) = '1' then
wr_retransmit_frame <= '1' after dly;
else
wr_retransmit_frame <= '0' after dly;
end if;
end if;
end if;
end process p_sync_wr_trans;
-- Count the number of frames in the FIFO. The counter is incremented when a
-- frame is stored or retransmitted and decremented when a frame is
-- transmitted. Need to keep the counter on the write clock as this is the
-- fastest clock if they differ. Logic assumes transmit and retransmit cannot
-- happen at same time.
p_wr_frames : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_frames <= (others => '0') after dly;
else
if (wr_store_frame and wr_retransmit_frame) = '1' then
wr_frames <= wr_frames + 2 after dly;
elsif ((wr_store_frame or wr_retransmit_frame)
and not wr_transmit_frame) = '1' then
wr_frames <= wr_frames + 1 after dly;
elsif (wr_transmit_frame and not wr_store_frame) = '1' then
wr_frames <= wr_frames - 1 after dly;
end if;
end if;
end if;
end process p_wr_frames;
end generate gen_hd_count;
-- send wr_transmit_frame back to read domain to ensure it waits until the frame_in_fifo logic has been updated
p_delay_wr_transmit : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_transmit_frame_delay <= '0' after dly;
else
wr_transmit_frame_delay <= wr_transmit_frame after dly;
end if;
end if;
end process p_delay_wr_transmit;
p_wr_tx : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if wr_transmit_frame_delay = '1' then
frame_in_fifo_valid_tog <= not frame_in_fifo_valid_tog after dly;
end if;
end if;
end process p_wr_tx;
-- Generate a frame in FIFO signal for use in control logic.
p_wr_avail : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_frame_in_fifo <= '0' after dly;
else
if wr_frames /= (wr_frames'range => '0') then
wr_frame_in_fifo <= '1' after dly;
else
wr_frame_in_fifo <= '0' after dly;
end if;
end if;
end if;
end process p_wr_avail;
-- Generate a multiple frames in FIFO signal for use in control logic.
p_mult_wr_avail : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_frames_in_fifo <= '0' after dly;
else
if wr_frames >= "0000000010" then
wr_frames_in_fifo <= '1' after dly;
else
wr_frames_in_fifo <= '0' after dly;
end if;
end if;
end if;
end process p_mult_wr_avail;
-- Synchronize it back onto read domain for use in the read logic.
resync_wr_frame_in_fifo : tri_mode_ethernet_mac_0_sync_block
port map (
clk => tx_mac_aclk,
data_in => wr_frame_in_fifo,
data_out => frame_in_fifo
);
-- Synchronize it back onto read domain for use in the read logic.
resync_wr_frames_in_fifo : tri_mode_ethernet_mac_0_sync_block
port map (
clk => tx_mac_aclk,
data_in => wr_frames_in_fifo,
data_out => frames_in_fifo
);
-- in he case where only one frame is in the fifo we have to be careful about the faling edge of
-- the frame in fifo signal as for short frames this could occur after the state machine completes
resync_fif_valid_tog : tri_mode_ethernet_mac_0_sync_block
port map (
clk => tx_mac_aclk,
data_in => frame_in_fifo_valid_tog,
data_out => frame_in_fifo_valid_sync
);
-- Edge detect of the re-resynchronized read transmit frame signal.
p_delay_fif_valid : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
frame_in_fifo_valid_delay <= frame_in_fifo_valid_sync after dly;
end if;
end process p_delay_fif_valid;
p_sync_fif_valid : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if tx_mac_reset = '1' then
frame_in_fifo_valid <= '1' after dly;
else
-- Edge detector
if (frame_in_fifo_valid_delay xor frame_in_fifo_valid_sync) = '1' then
frame_in_fifo_valid <= '1' after dly;
elsif rd_transmit_frame = '1' then
frame_in_fifo_valid <= '0' after dly;
end if;
end if;
end if;
end process p_sync_fif_valid;
------------------------------------------------------------------------------
-- Address counters
------------------------------------------------------------------------------
-- Write address is incremented when write enable signal has been asserted
wr_addr_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
wr_addr <= (others => '0') after dly;
elsif wr_addr_reload = '1' then
wr_addr <= wr_start_addr after dly;
elsif wr_addr_inc = '1' then
wr_addr <= wr_addr + 1 after dly;
end if;
end if;
end process wr_addr_p;
-- Store the start address in case the address must be reset.
wr_staddr_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
wr_start_addr <= (others => '0') after dly;
elsif wr_start_addr_load = '1' then
wr_start_addr <= wr_addr + 1 after dly;
end if;
end if;
end process wr_staddr_p;
------------------------------------------------------------------------------
-- Half duplex-only read address counters.
gen_fd_addr : if (FULL_DUPLEX_ONLY = TRUE) generate
-- Read address is incremented when read enable signal has been asserted.
rd_addr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_addr <= (others => '0') after dly;
else
if rd_addr_reload = '1' then
rd_addr <= rd_dec_addr after dly;
elsif rd_addr_inc = '1' then
rd_addr <= rd_addr + 1 after dly;
end if;
end if;
end if;
end process rd_addr_p;
-- Do not need to keep a start address, but the address is needed to
-- calculate FIFO occupancy.
rd_start_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_start_addr <= (others => '0') after dly;
else
rd_start_addr <= rd_addr after dly;
end if;
end if;
end process rd_start_p;
end generate gen_fd_addr;
------------------------------------------------------------------------------
-- Full and half duplex read address counters
gen_hd_addr : if (FULL_DUPLEX_ONLY = FALSE) generate
-- Read address is incremented when read enable signal has been asserted.
rd_addr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_addr <= (others => '0') after dly;
else
if rd_addr_reload = '1' then
rd_addr <= rd_dec_addr after dly;
elsif rd_start_addr_reload = '1' then
rd_addr <= rd_start_addr after dly;
elsif rd_addr_inc = '1' then
rd_addr <= rd_addr + 1 after dly;
end if;
end if;
end if;
end process rd_addr_p;
rd_staddr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_start_addr <= (others => '0') after dly;
else
if rd_start_addr_load = '1' then
rd_start_addr <= rd_addr - 6 after dly;
end if;
end if;
end if;
end process rd_staddr_p;
-- Collision window expires after MAC has been transmitting for required slot
-- time. This is 512 clock cycles at 1Gbps. Also if the end of frame has fully
-- been transmitted by the MAC then a collision cannot occur. This collision
-- expiration signal goes high at 768 cycles from the start of the frame.
-- This is inefficient for short frames, however it should be enough to
-- prevent the FIFO from locking up.
rd_col_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_col_window_expire <= '0' after dly;
else
if rd_transmit_frame = '1' then
rd_col_window_expire <= '0' after dly;
elsif rd_slot_timer(9 downto 7) = "110" then
rd_col_window_expire <= '1' after dly;
end if;
end if;
end if;
end process;
rd_idle_state <= '1' when rd_state = IDLE_s else '0';
rd_colreg_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
rd_col_window_pipe(0) <= rd_col_window_expire
and rd_idle_state after dly;
if rd_txfer_en = '1' then
rd_col_window_pipe(1) <= rd_col_window_pipe(0) after dly;
end if;
end if;
end process;
rd_slot_time_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
-- Will not count until after the first frame is sent.
if tx_mac_reset = '1' then
rd_slot_timer <= "1111111111" after dly;
else
-- Reset counter.
if rd_transmit_frame = '1' then
rd_slot_timer <= (others => '0') after dly;
-- Do not allow counter to roll over, and
-- only count when frame is being transmitted.
elsif rd_slot_timer /= "1111111111" then
rd_slot_timer <= rd_slot_timer + 1 after dly;
end if;
end if;
end if;
end process;
end generate gen_hd_addr;
-- Read address generation
rd_decaddr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_dec_addr <= (others => '0') after dly;
else
if rd_addr_inc = '1' then
rd_dec_addr <= rd_addr - 1 after dly;
end if;
end if;
end if;
end process rd_decaddr_p;
------------------------------------------------------------------------------
-- Data pipelines
------------------------------------------------------------------------------
-- Register data inputs to BRAM.
-- No resets to allow for SRL16 target.
reg_din_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
wr_data_pipe(0) <= tx_axis_fifo_tdata after dly;
if wr_accept_pipe(0) = '1' then
wr_data_pipe(1) <= wr_data_pipe(0) after dly;
end if;
if wr_accept_pipe(1) = '1' then
wr_data_bram <= wr_data_pipe(1) after dly;
end if;
end if;
end process reg_din_p;
-- Start of frame set when tvalid is asserted and previous frame has ended.
wr_sof_int <= tx_axis_fifo_tvalid and wr_eof_reg;
-- Set end of frame flag when tlast and tvalid are asserted together.
-- Reset to logic 1 to enable first frame's start of frame flag.
reg_eofreg_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
wr_eof_reg <= '1';
else
if tx_axis_fifo_tvalid = '1' and tx_axis_fifo_tready_int_n = '0' then
wr_eof_reg <= tx_axis_fifo_tlast;
end if;
end if;
end if;
end process reg_eofreg_p;
-- Pipeline the start of frame flag when the pipe is enabled.
reg_sof_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
wr_sof_pipe(0) <= wr_sof_int and not tx_axis_fifo_tlast after dly;
if wr_accept_pipe(0) = '1' then
wr_sof_pipe(1) <= wr_sof_pipe(0) after dly;
end if;
end if;
end process reg_sof_p;
-- Pipeline the pipeline enable signal, which is derived from simultaneous
-- assertion of tvalid and tready.
reg_acc_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if (tx_fifo_reset = '1') then
wr_accept_pipe(0) <= '0' after dly;
wr_accept_pipe(1) <= '0' after dly;
wr_accept_bram <= '0' after dly;
else
wr_accept_pipe(0) <= tx_axis_fifo_tvalid and (not tx_axis_fifo_tready_int_n) and
not (tx_axis_fifo_tlast and wr_sof_int) after dly;
wr_accept_pipe(1) <= wr_accept_pipe(0) after dly;
wr_accept_bram <= wr_accept_pipe(1) after dly;
end if;
end if;
end process reg_acc_p;
-- Pipeline the end of frame flag when the pipe is enabled.
reg_eof_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
wr_eof_pipe(0) <= tx_axis_fifo_tvalid and tx_axis_fifo_tlast and not wr_sof_int after dly;
if wr_accept_pipe(0) = '1' then
wr_eof_pipe(1) <= wr_eof_pipe(0) after dly;
end if;
if wr_accept_pipe(1) = '1' then
wr_eof_bram(0) <= wr_eof_pipe(1) after dly;
end if;
end if;
end process reg_eof_p;
-- Register data outputs from BRAM.
-- No resets to allow SRL16 target.
reg_dout_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_en = '1' then
rd_data_delay <= rd_data_bram after dly;
rd_data_pipe <= rd_data_delay after dly;
end if;
end if;
end process reg_dout_p;
reg_eofout_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_en = '1' then
rd_eof_pipe <= rd_eof_bram(0) after dly;
rd_eof <= rd_eof_pipe after dly;
rd_eof_reg <= rd_eof or rd_eof_pipe after dly;
end if;
end if;
end process reg_eofout_p;
------------------------------------------------------------------------------
-- Half duplex-only drop and retransmission controls.
gen_hd_input : if (FULL_DUPLEX_ONLY = FALSE) generate
-- Register the collision without retransmit signal, which is a pulse that
-- causes the FIFO to drop the frame.
reg_col_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
rd_drop_frame <= tx_collision and (not tx_retransmit) after dly;
end if;
end process reg_col_p;
-- Register the collision with retransmit signal, which is a pulse that
-- causes the FIFO to retransmit the frame.
reg_retr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
rd_retransmit <= tx_collision and tx_retransmit after dly;
end if;
end process reg_retr_p;
end generate gen_hd_input;
------------------------------------------------------------------------------
-- FIFO full functionality
------------------------------------------------------------------------------
-- Full functionality is the difference between read and write addresses.
-- We cannot use gray code this time as the read address and read start
-- addresses jump by more than 1.
-- We generate an enable pulse for the read side every 16 read clocks. This
-- provides for the worst-case situation where the write clock is 20MHz and
-- read clock is 125MHz.
p_rd_16_pulse : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if tx_mac_reset = '1' then
rd_16_count <= (others => '0') after dly;
else
rd_16_count <= rd_16_count + 1 after dly;
end if;
end if;
end process;
rd_txfer_en <= '1' when rd_16_count = "1111" else '0';
-- Register the start address on the enable pulse.
p_rd_addr_txfer : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if tx_mac_reset = '1' then
rd_addr_txfer <= (others => '0') after dly;
else
if rd_txfer_en = '1' then
rd_addr_txfer <= rd_start_addr after dly;
end if;
end if;
end if;
end process;
-- Generate a toggle to indicate that the address has been loaded.
p_rd_tog_txfer : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if rd_txfer_en = '1' then
rd_txfer_tog <= not rd_txfer_tog after dly;
end if;
end if;
end process;
-- Synchronize the toggle to the write side.
resync_rd_txfer_tog : tri_mode_ethernet_mac_0_sync_block
port map (
clk => tx_fifo_aclk,
data_in => rd_txfer_tog,
data_out => wr_txfer_tog_sync
);
-- Delay the synchronized toggle by one cycle.
p_wr_tog_txfer : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
wr_txfer_tog_delay <= wr_txfer_tog_sync after dly;
end if;
end process;
-- Generate an enable pulse from the toggle. The address should have been
-- steady on the wr clock input for at least one clock.
wr_txfer_en <= wr_txfer_tog_delay xor wr_txfer_tog_sync;
-- Capture the address on the write clock when the enable pulse is high.
p_wr_addr_txfer : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_rd_addr <= (others => '0') after dly;
elsif wr_txfer_en = '1' then
wr_rd_addr <= rd_addr_txfer after dly;
end if;
end if;
end process;
-- Obtain the difference between write and read pointers
p_wr_addr_diff : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_addr_diff <= (others => '0') after dly;
else
wr_addr_diff <= wr_rd_addr - wr_addr after dly;
end if;
end if;
end process;
-- Detect when the FIFO is full.
-- The FIFO is considered to be full if the write address pointer is
-- within 0 to 3 of the read address pointer.
p_wr_full : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_fifo_full <= '0' after dly;
else
if wr_addr_diff(11 downto 4) = 0
and wr_addr_diff(3 downto 2) /= "00" then
wr_fifo_full <= '1' after dly;
else
wr_fifo_full <= '0' after dly;
end if;
end if;
end if;
end process p_wr_full;
-- Memory overflow occurs when the FIFO is full and there are no frames
-- available in the FIFO for transmission. If the collision window has
-- expired and there are no frames in the FIFO and the FIFO is full, then the
-- FIFO is in an overflow state. We must accept the rest of the incoming
-- frame in overflow condition.
gen_fd_ovflow : if (FULL_DUPLEX_ONLY = TRUE) generate
-- In full duplex mode, the FIFO memory can only overflow if the FIFO goes
-- full but there is no frame available to be retranmsitted. Therefore,
-- prevent signal from being asserted when store_frame signal is high, as
-- frame count is being updated.
wr_fifo_overflow <= '1' when wr_fifo_full = '1' and wr_frame_in_fifo = '0'
and wr_eof_state = '0' and wr_eof_state_reg = '0'
else '0';
-- Tie off unused half-duplex signals
wr_col_window_pipe(0) <= '0';
wr_col_window_pipe(1) <= '0';
end generate gen_fd_ovflow;
gen_hd_ovflow : if (FULL_DUPLEX_ONLY = FALSE) generate
-- In half duplex mode, register write collision window to give address
-- counter sufficient time to update. This will prevent the signal from
-- being asserted when the store_frame signal is high, as the frame count
-- is being updated.
wr_fifo_overflow <= '1' when wr_fifo_full = '1' and wr_frame_in_fifo = '0'
and wr_eof_state = '0' and wr_eof_state_reg = '0'
and wr_col_window_expire = '1'
else '0';
-- Register rd_col_window signal.
-- This signal is long, and will remain high until overflow functionality
-- has finished, so save just to register the once.
p_wr_col_expire : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_col_window_pipe(0) <= '0' after dly;
wr_col_window_pipe(1) <= '0' after dly;
wr_col_window_expire <= '0' after dly;
else
if wr_txfer_en = '1' then
wr_col_window_pipe(0) <= rd_col_window_pipe(1) after dly;
end if;
wr_col_window_pipe(1) <= wr_col_window_pipe(0) after dly;
wr_col_window_expire <= wr_col_window_pipe(1) after dly;
end if;
end if;
end process;
end generate gen_hd_ovflow;
------------------------------------------------------------------------------
-- FIFO status signals
------------------------------------------------------------------------------
-- The FIFO status is four bits which represents the occupancy of the FIFO
-- in sixteenths. To generate this signal we therefore only need to compare
-- the 4 most significant bits of the write address pointer with the 4 most
-- significant bits of the read address pointer.
p_fifo_status : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_fifo_status <= "0000" after dly;
else
if wr_addr_diff = (wr_addr_diff'range => '0') then
wr_fifo_status <= "0000" after dly;
else
wr_fifo_status(3) <= not wr_addr_diff(11) after dly;
wr_fifo_status(2) <= not wr_addr_diff(10) after dly;
wr_fifo_status(1) <= not wr_addr_diff(9) after dly;
wr_fifo_status(0) <= not wr_addr_diff(8) after dly;
end if;
end if;
end if;
end process p_fifo_status;
fifo_status <= std_logic_vector(wr_fifo_status);
------------------------------------------------------------------------------
-- Instantiate FIFO block memory
------------------------------------------------------------------------------
wr_eof_data_bram(8) <= wr_eof_bram(0);
wr_eof_data_bram(7 downto 0) <= wr_data_bram;
rd_eof_bram(0) <= rd_eof_data_bram(8);
rd_data_bram <= rd_eof_data_bram(7 downto 0);
tx_ramgen_i : tri_mode_ethernet_mac_0_bram_tdp
generic map (
DATA_WIDTH => 9,
ADDR_WIDTH => 12
)
port map (
b_dout => rd_eof_data_bram,
a_addr => std_logic_vector(wr_addr(11 downto 0)),
b_addr => std_logic_vector(rd_addr(11 downto 0)),
a_clk => tx_fifo_aclk,
b_clk => tx_mac_aclk,
a_din => wr_eof_data_bram,
b_en => rd_en,
a_rst => tx_fifo_reset,
b_rst => tx_mac_reset,
a_wr => wr_en
);
end RTL;
|
-------------------------------------------------------------------------------
-- counter_bit_imp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2009/10/06 21:15:00 $
--
-- History:
-- tise 2001-04-04 First Version
--
-- KC 2002-01-23 Remove used generics and removed unused code
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_bit is
port (
Clk : in std_logic;
Rst : in std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end entity counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_bit is
component LUT4 is
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component LUT4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
I_ALU_LUT : LUT4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub, -- [out]
I0 => Count_In, -- [in]
I1 => Count_Down, -- [in]
I2 => Count_Load, -- [in]
I3 => Load_In); -- [in]
MUXCY_I : MUXCY_L
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
LO => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg, -- [out]
C => Clk, -- [in]
CE => Clock_Enable, -- [in]
D => count_Result, -- [in]
R => Rst -- [in]
);
Result <= count_Result_Reg;
end imp;
|
-------------------------------------------------------------------------------
-- counter_bit_imp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2009/10/06 21:15:00 $
--
-- History:
-- tise 2001-04-04 First Version
--
-- KC 2002-01-23 Remove used generics and removed unused code
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_bit is
port (
Clk : in std_logic;
Rst : in std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end entity counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_bit is
component LUT4 is
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component LUT4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
I_ALU_LUT : LUT4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub, -- [out]
I0 => Count_In, -- [in]
I1 => Count_Down, -- [in]
I2 => Count_Load, -- [in]
I3 => Load_In); -- [in]
MUXCY_I : MUXCY_L
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
LO => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg, -- [out]
C => Clk, -- [in]
CE => Clock_Enable, -- [in]
D => count_Result, -- [in]
R => Rst -- [in]
);
Result <= count_Result_Reg;
end imp;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2627.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02627ent IS
END c13s03b01x00p02n01i02627ent;
ARCHITECTURE c13s03b01x00p02n01i02627arch OF c13s03b01x00p02n01i02627ent IS
BEGIN
TESTING: PROCESS
variable k]k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02627 - Identifier can not contain ']'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02627arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2627.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02627ent IS
END c13s03b01x00p02n01i02627ent;
ARCHITECTURE c13s03b01x00p02n01i02627arch OF c13s03b01x00p02n01i02627ent IS
BEGIN
TESTING: PROCESS
variable k]k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02627 - Identifier can not contain ']'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02627arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2627.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02627ent IS
END c13s03b01x00p02n01i02627ent;
ARCHITECTURE c13s03b01x00p02n01i02627arch OF c13s03b01x00p02n01i02627ent IS
BEGIN
TESTING: PROCESS
variable k]k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02627 - Identifier can not contain ']'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02627arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cpu_disas
-- File: cpu_disas.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Module for disassembly
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use std.textio.all;
use grlib.sparc_disas.all;
-- pragma translate_on
entity cpu_disas is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result: in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic);
end;
architecture behav of cpu_disas is
begin
dummy <= '1';
-- pragma translate_off
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
valid := (((not annul) and pv) = '1') and (not ((fpins or fpld) and (trap = '0')));
valid := valid and (holdn = '1');
if rising_edge(clk) and (rstn = '1') then
print_insn (conv_integer(index), pc(31 downto 2) & "00", inst,
result, valid, trap = '1', wreg = '1'
);
end if;
end process;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use std.textio.all;
use grlib.sparc_disas.all;
-- pragma translate_on
entity gaisler_cpu_disas is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result: in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic);
end;
architecture behav of gaisler_cpu_disas is
begin
dummy <= '1';
-- pragma translate_off
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
valid := (((not annul) and pv) = '1') and (not ((fpins or fpld) and (trap = '0')));
valid := valid and (holdn = '1');
if rising_edge(clk) and (rstn = '1') then
print_insn (conv_integer(index), pc(31 downto 2) & "00", inst,
result, valid, trap = '1', wreg = '1'
);
end if;
end process;
-- pragma translate_on
end;
|
--************************************************************************************************
-- Address decoder
-- Version 0.11A
-- Designed by Ruslan Lepetenok
-- Modified 31.07.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.MemAccessCtrlPack.all;
entity RAMAdrDcd is port(
ramadr : in std_logic_vector(15 downto 0);
ramre : in std_logic;
ramwe : in std_logic;
-- Memory mapped I/O i/f
stb_IO : out std_logic;
stb_IOmod : out std_logic_vector(CNumOfSlaves-1 downto 0);
-- Data memory i/f
ram_we : out std_logic;
ram_ce : out std_logic;
ram_sel : out std_logic
);
end RAMAdrDcd;
architecture RTL of RAMAdrDcd is
signal ram_sel_int : std_logic;
begin
stb_IO <= '1' when (ramadr(ramadr'high downto ramadr'high-CMemMappedIOBaseAdr'high) = CMemMappedIOBaseAdr) else '0';
--MMIOAdrDcd:process(ramadr)
--begin
-- stb_IOmod <= (others => '0');
-- for i in 0 to CNumOfSlaves-1 loop
-- if(ramadr(7 downto 4)=i) then
-- stb_IOmod(i) <= '1';
-- end if;
-- end loop;
--end process;
-- For the purpose of test only
--stb_IOmod(0) <= '1' when ramadr(15 downto 4)=x"017" else '0';
--stb_IOmod(1) <= '1' when ramadr(15 downto 4)=x"018" else '0';
stb_IOmod(0) <= '1' when ramadr(7 downto 4)=x"0" else '0';
stb_IOmod(1) <= '1' when ramadr(7 downto 4)=x"1" else '0';
-- For the purpose of test only
-- RAM i/f
ram_sel_int <= '1'when (ramadr(ramadr'high downto ramadr'high-CDRAMBaseAdr'high) = CDRAMBaseAdr) else '0';
ram_sel <= ram_sel_int;
ram_we <= ram_sel_int and ramwe;
ram_ce <= ram_sel_int and (ramwe or ramre);
end RTL;
|
--************************************************************************************************
-- Address decoder
-- Version 0.11A
-- Designed by Ruslan Lepetenok
-- Modified 31.07.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.MemAccessCtrlPack.all;
entity RAMAdrDcd is port(
ramadr : in std_logic_vector(15 downto 0);
ramre : in std_logic;
ramwe : in std_logic;
-- Memory mapped I/O i/f
stb_IO : out std_logic;
stb_IOmod : out std_logic_vector(CNumOfSlaves-1 downto 0);
-- Data memory i/f
ram_we : out std_logic;
ram_ce : out std_logic;
ram_sel : out std_logic
);
end RAMAdrDcd;
architecture RTL of RAMAdrDcd is
signal ram_sel_int : std_logic;
begin
stb_IO <= '1' when (ramadr(ramadr'high downto ramadr'high-CMemMappedIOBaseAdr'high) = CMemMappedIOBaseAdr) else '0';
--MMIOAdrDcd:process(ramadr)
--begin
-- stb_IOmod <= (others => '0');
-- for i in 0 to CNumOfSlaves-1 loop
-- if(ramadr(7 downto 4)=i) then
-- stb_IOmod(i) <= '1';
-- end if;
-- end loop;
--end process;
-- For the purpose of test only
--stb_IOmod(0) <= '1' when ramadr(15 downto 4)=x"017" else '0';
--stb_IOmod(1) <= '1' when ramadr(15 downto 4)=x"018" else '0';
stb_IOmod(0) <= '1' when ramadr(7 downto 4)=x"0" else '0';
stb_IOmod(1) <= '1' when ramadr(7 downto 4)=x"1" else '0';
-- For the purpose of test only
-- RAM i/f
ram_sel_int <= '1'when (ramadr(ramadr'high downto ramadr'high-CDRAMBaseAdr'high) = CDRAMBaseAdr) else '0';
ram_sel <= ram_sel_int;
ram_we <= ram_sel_int and ramwe;
ram_ce <= ram_sel_int and (ramwe or ramre);
end RTL;
|
--************************************************************************************************
-- Address decoder
-- Version 0.11A
-- Designed by Ruslan Lepetenok
-- Modified 31.07.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.MemAccessCtrlPack.all;
entity RAMAdrDcd is port(
ramadr : in std_logic_vector(15 downto 0);
ramre : in std_logic;
ramwe : in std_logic;
-- Memory mapped I/O i/f
stb_IO : out std_logic;
stb_IOmod : out std_logic_vector(CNumOfSlaves-1 downto 0);
-- Data memory i/f
ram_we : out std_logic;
ram_ce : out std_logic;
ram_sel : out std_logic
);
end RAMAdrDcd;
architecture RTL of RAMAdrDcd is
signal ram_sel_int : std_logic;
begin
stb_IO <= '1' when (ramadr(ramadr'high downto ramadr'high-CMemMappedIOBaseAdr'high) = CMemMappedIOBaseAdr) else '0';
--MMIOAdrDcd:process(ramadr)
--begin
-- stb_IOmod <= (others => '0');
-- for i in 0 to CNumOfSlaves-1 loop
-- if(ramadr(7 downto 4)=i) then
-- stb_IOmod(i) <= '1';
-- end if;
-- end loop;
--end process;
-- For the purpose of test only
--stb_IOmod(0) <= '1' when ramadr(15 downto 4)=x"017" else '0';
--stb_IOmod(1) <= '1' when ramadr(15 downto 4)=x"018" else '0';
stb_IOmod(0) <= '1' when ramadr(7 downto 4)=x"0" else '0';
stb_IOmod(1) <= '1' when ramadr(7 downto 4)=x"1" else '0';
-- For the purpose of test only
-- RAM i/f
ram_sel_int <= '1'when (ramadr(ramadr'high downto ramadr'high-CDRAMBaseAdr'high) = CDRAMBaseAdr) else '0';
ram_sel <= ram_sel_int;
ram_we <= ram_sel_int and ramwe;
ram_ce <= ram_sel_int and (ramwe or ramre);
end RTL;
|
--************************************************************************************************
-- Address decoder
-- Version 0.11A
-- Designed by Ruslan Lepetenok
-- Modified 31.07.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.MemAccessCtrlPack.all;
entity RAMAdrDcd is port(
ramadr : in std_logic_vector(15 downto 0);
ramre : in std_logic;
ramwe : in std_logic;
-- Memory mapped I/O i/f
stb_IO : out std_logic;
stb_IOmod : out std_logic_vector(CNumOfSlaves-1 downto 0);
-- Data memory i/f
ram_we : out std_logic;
ram_ce : out std_logic;
ram_sel : out std_logic
);
end RAMAdrDcd;
architecture RTL of RAMAdrDcd is
signal ram_sel_int : std_logic;
begin
stb_IO <= '1' when (ramadr(ramadr'high downto ramadr'high-CMemMappedIOBaseAdr'high) = CMemMappedIOBaseAdr) else '0';
--MMIOAdrDcd:process(ramadr)
--begin
-- stb_IOmod <= (others => '0');
-- for i in 0 to CNumOfSlaves-1 loop
-- if(ramadr(7 downto 4)=i) then
-- stb_IOmod(i) <= '1';
-- end if;
-- end loop;
--end process;
-- For the purpose of test only
--stb_IOmod(0) <= '1' when ramadr(15 downto 4)=x"017" else '0';
--stb_IOmod(1) <= '1' when ramadr(15 downto 4)=x"018" else '0';
stb_IOmod(0) <= '1' when ramadr(7 downto 4)=x"0" else '0';
stb_IOmod(1) <= '1' when ramadr(7 downto 4)=x"1" else '0';
-- For the purpose of test only
-- RAM i/f
ram_sel_int <= '1'when (ramadr(ramadr'high downto ramadr'high-CDRAMBaseAdr'high) = CDRAMBaseAdr) else '0';
ram_sel <= ram_sel_int;
ram_we <= ram_sel_int and ramwe;
ram_ce <= ram_sel_int and (ramwe or ramre);
end RTL;
|
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity top is
port(
SYSCLK_P : in std_logic;
SYSCLK_N : in std_logic;
GPIO_LED : out std_logic_vector (6 downto 0));
end top;
architecture Behavioral of top is
signal clk_200Mhz : std_logic;
signal clk_5hz : std_logic;
signal clk_2hz : std_logic;
signal clk_1hz : std_logic;
component dynamic
port (
clk_1hz : in std_logic;
leds : out std_logic_vector (3 downto 0)
);
end component;
begin
clock_station_i : entity work.clock_station port map(
clk_p => SYSCLK_P,
clk_n => SYSCLK_N,
clk_5hz => clk_5hz,
clk_2hz => clk_2hz,
clk_1hz => clk_1hz
);
static_i : entity work.static port map(
clk_5hz => clk_5hz,
clk_2hz => clk_2hz,
clk_1hz => clk_1hz,
leds => GPIO_LED(6 downto 4)
);
dynamic_i : dynamic port map(
clk_1hz => clk_1hz,
leds => GPIO_LED(3 downto 0)
);
end Behavioral; |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:58:50 07/05/05
-- Design Name:
-- Module Name: combination - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity combination is
port( x1 : in std_logic_vector(8 downto 0);
x2 : in std_logic_vector(8 downto 0);
x3 : in std_logic_vector(8 downto 0);
-- x4_1 : in std_logic_vector(8 downto 0);
-- x5_1 : in std_logic_vector(8 downto 0);
Output : out std_logic_vector(10 downto 0));
end combination;
architecture Behavioral of combination is
component Do_2
port( Data_in : in std_logic_vector(8 downto 0);
Data_out : out std_logic_vector(8 downto 0)
);
end component;
component half_adder
port(x,y : in std_logic;
Hsum,Hcarry : out std_logic );
end component;
component CSA
port(x_1 : in std_logic_vector(8 downto 0);
x_2 : in std_logic_vector(8 downto 0);
x_3 : in std_logic_vector(8 downto 0);
Sum : out std_logic_vector(8 downto 0);
Carry : out std_logic_vector(8 downto 0)
);
end component;
component CPA
port( A , B : in std_logic_vector(7 downto 0);
-- C0 : in std_logic;
S : out std_logic_vector(7 downto 0);
C8 : out std_logic );
end component;
signal S1 : std_logic_vector( 8 downto 0);
signal C1 : std_logic_vector( 8 downto 0);
--signal S2 : std_logic_vector( 8 downto 0);
--signal C2 : std_logic_vector( 8 downto 0);
--signal S3 : std_logic_vector( 7 downto 0);
--signal C3 : std_logic_vector( 7 downto 0);
--signal C1_1 : std_logic_vector( 7 downto 0);
--signal HC_S : std_logic;
--signal HC_C : std_logic;
--signal S4 : std_logic_vector(7 downto 0);
--signal C4 : std_logic_vector(7 downto 0);
--signal S5 : std_logic_vector( 7 downto 0);
--signal C5 : std_logic_vector( 7 downto 0);
signal add : std_logic_vector(7 downto 0);
--signal C4 : std_logic_vector(8 downto 0);
--signal C5 : std_logic_vector(10 downto 0);
signal C8_1 : std_logic;
signal CF_S : std_logic;
signal CF_C : std_logic;
--signal x4_2 : std_logic_vector(8 downto 0);
--signal x5_2 : std_logic_vector(8 downto 0);
--signal x4 : std_logic_vector(8 downto 0);
--signal x5 : std_logic_vector(8 downto 0);
--signal x1 : std_logic_vector(8 downto 0);
--signal x2 : std_logic_vector(8 downto 0);
--signal x3 : std_logic_vector(8 downto 0);
signal ChenS : std_logic_vector(7 downto 0);
signal ChenC : std_logic_vector(7 downto 0);
begin
--x1 <= x1_1(8)& x1_1(8)& x1_1(7) & x1_1(6) & x1_1(5) & x1_1(4) & x1_1(3) & x1_1(2) &x1_1(1); --x1 /2
--x2 <= x2_1(8)& x2_1(8)& x2_1(7) & x2_1(6) & x2_1(5) & x2_1(4) & x2_1(3) & x2_1(2) &x2_1(1); --x2 /2
--x3 <= x3_1(8)& x3_1(8)& x3_1(8) & x3_1(7) & x3_1(6) & x3_1(5) & x3_1(4) & x3_1(3) &x3_1(2) ; --x3 /4
--x4_2 <= x4_1(8)& x4_1(8)& x4_1(8) & x4_1(8) & x4_1(7) & x4_1(6) & x4_1(5) & x4_1(4) &x4_1(3) ; --x4 /8
--x5_2 <= x5_1(8)& x5_1(8)& x5_1(8) & x5_1(8) & x5_1(7) & x5_1(6) & x5_1(5) & x5_1(4) &x5_1(3) ; --x5 /8
--T1 : Do_2 port map(x4_2,x4);
--T2 : Do_2 port map(x5_2,x5);
--x4 <= (x4_1);
--x5 <= (x5_1);
--combination : for i in 0 to 8 generate
D1: CSA port map (x1 , x2 , x3 , S1, C1);
--end generate;
ChenS <= S1(8) & S1(7) & S1(6) & S1(5) & S1(4) & S1(3) & S1(2) & S1(1);
ChenC <= C1(7) & C1(6) & C1(5) & C1(4) & C1(3) & C1(2) & C1(1) & C1(0);
--combination2 : for i in 0 to 8 generate
-- D2: CSA port map (x4 , x5 , S1 , S2 ,C2);
--end generate;
-- S3 <= S2(8) & S2(7) & S2(6) & S2(5) & S2(4) & S2(3) & S2(2) & S2(1) ;
-- C3 <= C2(7) & C2(6) & C2(5) & C2(4) & C2(3) & C2(2) & C2(1) & C2(0) ;
-- C1_1 <= C1(7) & C1(6) & C1(5) & C1(4) & C1(3) & C1(2) & C1(1) & C1(0) ;
--combination3 : for i in 0 to 8 generate
-- D3 : CSA2 port map (S3 , C3 , C1_1 , S4, C4) ;
-- D5 : half_adder port map(C2(8) ,C1(8) ,HC_S,HC_C);
--end generate;
-- S5 <= HC_S & S4(7) & S4(6) & S4(5) & S4(4) & S4(3) & S4(2) & S4(1) ;
-- C5 <= C4(7) & C4(6) & C4(5) & C4(4) & C4(3) & C4(2) & C4(1) & C4(0);
D4: CPA port map (ChenS,ChenC,add,C8_1);
-- add <= signed(S5(8)&S5) + signed(C3);
D6 : half_adder port map(C8_1 , C1(8) , CF_S,CF_C ) ;
-- Output <= add(6)&add(5)&add(4)&add(3)&add(2)&add(1)&add(0) & S4(0) & S2(0); -- CF_C& CF_S &
Output <= CF_C & CF_S & add & S1(0);
end Behavioral;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:router:1.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY sys_router_0_1 IS
PORT (
CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
L_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VIN : IN STD_LOGIC;
L_RIN : OUT STD_LOGIC;
L_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VOUT : OUT STD_LOGIC;
L_ROUT : IN STD_LOGIC;
N_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VIN : IN STD_LOGIC;
N_RIN : OUT STD_LOGIC;
N_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VOUT : OUT STD_LOGIC;
N_ROUT : IN STD_LOGIC;
S_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VIN : IN STD_LOGIC;
S_RIN : OUT STD_LOGIC;
S_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VOUT : OUT STD_LOGIC;
S_ROUT : IN STD_LOGIC;
E_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VIN : IN STD_LOGIC;
E_RIN : OUT STD_LOGIC;
E_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VOUT : OUT STD_LOGIC;
E_ROUT : IN STD_LOGIC
);
END sys_router_0_1;
ARCHITECTURE sys_router_0_1_arch OF sys_router_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sys_router_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT router_struct IS
GENERIC (
ADDR_X : INTEGER;
ADDR_Y : INTEGER;
N_INST : BOOLEAN;
S_INST : BOOLEAN;
E_INST : BOOLEAN;
W_INST : BOOLEAN
);
PORT (
CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
L_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VIN : IN STD_LOGIC;
L_RIN : OUT STD_LOGIC;
L_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VOUT : OUT STD_LOGIC;
L_ROUT : IN STD_LOGIC;
N_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VIN : IN STD_LOGIC;
N_RIN : OUT STD_LOGIC;
N_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VOUT : OUT STD_LOGIC;
N_ROUT : IN STD_LOGIC;
S_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VIN : IN STD_LOGIC;
S_RIN : OUT STD_LOGIC;
S_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VOUT : OUT STD_LOGIC;
S_ROUT : IN STD_LOGIC;
E_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VIN : IN STD_LOGIC;
E_RIN : OUT STD_LOGIC;
E_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VOUT : OUT STD_LOGIC;
E_ROUT : IN STD_LOGIC;
W_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VIN : IN STD_LOGIC;
W_RIN : OUT STD_LOGIC;
W_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VOUT : OUT STD_LOGIC;
W_ROUT : IN STD_LOGIC
);
END COMPONENT router_struct;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF sys_router_0_1_arch: ARCHITECTURE IS "router_struct,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF sys_router_0_1_arch : ARCHITECTURE IS "sys_router_0_1,router_struct,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLOCK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLOCK CLK";
ATTRIBUTE X_INTERFACE_INFO OF RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF L_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF L_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF L_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF L_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF L_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF L_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF N_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 N_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF N_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 N_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF N_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 N_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF N_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 N_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF N_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 N_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF N_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 N_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 S_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 S_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 S_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 S_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 S_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 S_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF E_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 E_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF E_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 E_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF E_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 E_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF E_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 E_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF E_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 E_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF E_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 E_OUT TREADY";
BEGIN
U0 : router_struct
GENERIC MAP (
ADDR_X => 0,
ADDR_Y => 1,
N_INST => true,
S_INST => true,
E_INST => true,
W_INST => false
)
PORT MAP (
CLOCK => CLOCK,
RESET => RESET,
L_DIN => L_DIN,
L_VIN => L_VIN,
L_RIN => L_RIN,
L_DOUT => L_DOUT,
L_VOUT => L_VOUT,
L_ROUT => L_ROUT,
N_DIN => N_DIN,
N_VIN => N_VIN,
N_RIN => N_RIN,
N_DOUT => N_DOUT,
N_VOUT => N_VOUT,
N_ROUT => N_ROUT,
S_DIN => S_DIN,
S_VIN => S_VIN,
S_RIN => S_RIN,
S_DOUT => S_DOUT,
S_VOUT => S_VOUT,
S_ROUT => S_ROUT,
E_DIN => E_DIN,
E_VIN => E_VIN,
E_RIN => E_RIN,
E_DOUT => E_DOUT,
E_VOUT => E_VOUT,
E_ROUT => E_ROUT,
W_DIN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
W_VIN => '0',
W_ROUT => '0'
);
END sys_router_0_1_arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity issue is
end issue;
architecture sim of issue is
signal clk : std_logic := '1';
signal a, b : std_logic := '0';
begin
clk <= not clk after 5 ns;
a <= '1' after 20 ns,
'0' after 30 ns,
'1' after 40 ns,
'0' after 50 ns;
b <= '1' after 50 ns,
'0' after 60 ns,
'1' after 70 ns,
'0' after 80 ns;
-- All is sensitive to rising edge of clk
-- psl default clock is rising_edge(clk);
-- This assertion holds
-- psl NEXT_0_a : assert always (a -> next_e[3 to 5] (b));
end architecture sim;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library util;
use util.types_pkg.all;
use util.logic_pkg.all;
library tech;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of cache_core_1r1w is
constant assoc : natural := 2**log2_assoc;
type comb_type is record
tag_we : std_ulogic;
tag_wbanken : std_ulogic_vector(assoc-1 downto 0);
tag_waddr : std_ulogic_vector(index_bits-1 downto 0);
tag_wdata : std_ulogic_vector2(assoc-1 downto 0, tag_bits-1 downto 0);
tag_re : std_ulogic;
tag_rbanken : std_ulogic_vector(assoc-1 downto 0);
tag_raddr : std_ulogic_vector(index_bits-1 downto 0);
tag_rdata : std_ulogic_vector2(assoc-1 downto 0, tag_bits-1 downto 0);
data_we : std_ulogic;
data_wbanken : std_ulogic_vector(assoc-1 downto 0);
data_waddr : std_ulogic_vector(index_bits+offset_bits-1 downto 0);
data_wdata : std_ulogic_vector2(assoc-1 downto 0, word_bits-1 downto 0);
data_re : std_ulogic;
data_rbanken : std_ulogic_vector(assoc-1 downto 0);
data_raddr : std_ulogic_vector(index_bits+offset_bits-1 downto 0);
data_rdata : std_ulogic_vector2(assoc-1 downto 0, word_bits-1 downto 0);
end record;
signal c : comb_type;
begin
c.tag_we <= we and wtagen;
c.tag_wbanken <= wway;
c.tag_waddr <= windex;
c.tag_re <= re and rtagen;
c.tag_rbanken <= rway;
c.tag_raddr <= rindex;
c.data_we <= we and wdataen;
c.data_wbanken <= wway;
c.data_waddr <= windex & woffset;
c.data_re <= re and rdataen;
c.data_rbanken <= rway;
c.data_raddr <= rindex & roffset;
way_loop : for n in assoc-1 downto 0 generate
tag_bit_loop : for m in tag_bits-1 downto 0 generate
c.tag_wdata(n, m) <= wtag(m);
rtag(n, m) <= c.tag_rdata(n, m);
end generate;
data_bit_loop : for m in word_bits-1 downto 0 generate
c.data_wdata(n, m) <= wdata(m);
rdata(n, m) <= c.data_rdata(n, m);
end generate;
end generate;
tag_sram : entity tech.syncram_banked_1r1w(rtl)
generic map (
addr_bits => index_bits,
word_bits => tag_bits,
log2_banks => log2_assoc
)
port map (
clk => clk,
we => c.tag_we,
wbanken => c.tag_wbanken,
waddr => c.tag_waddr,
wdata => c.tag_wdata,
re => c.tag_re,
rbanken => c.tag_rbanken,
raddr => c.tag_raddr,
rdata => c.tag_rdata
);
data_sram : entity tech.syncram_banked_1r1w(rtl)
generic map (
addr_bits => index_bits + offset_bits,
word_bits => word_bits,
log2_banks => log2_assoc
)
port map (
clk => clk,
we => c.data_we,
wbanken => c.data_wbanken,
waddr => c.data_waddr,
wdata => c.data_wdata,
re => c.data_re,
rbanken => c.data_rbanken,
raddr => c.data_raddr,
rdata => c.data_rdata
);
end;
|
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Provides a phase generator controlled by a phase accumulator. It is
-- recommended to use increments only up to the half of the accumulator´s
-- capacity (MSB=1, all others 0). This ensures a duty cycle of 50% in the MSB
-- of the phase when it is used as a frequency signal. The current phase might
-- be used for DDS signal generation.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PhaseGenerator is
generic
(
-- The width of the phase values.
phase_width: natural := 32
);
port
(
-- The system clock.
clk: in std_logic;
-- The increment to be added to the phase accumulator in each clock cycle.
phase_increment: in unsigned (phase_width-1 downto 0);
-- A signal used to reset the generator´s phase.
reset_phase: in std_logic;
-- The current phase value.
phase: out unsigned (phase_width-1 downto 0) := (others => '0')
);
end entity;
architecture stdarch of PhaseGenerator is
type reg_type is record
phase_accumulator: unsigned (phase_width-1 downto 0);
end record;
signal state, next_state: reg_type := (phase_accumulator => (others => '0'));
begin
--------------------------------------------------------------------------------
-- State register.
--------------------------------------------------------------------------------
state_register: process is
begin
wait until rising_edge(clk);
state <= next_state;
end process;
--------------------------------------------------------------------------------
-- Next state logic.
--------------------------------------------------------------------------------
next_state.phase_accumulator <=
(next_state.phase_accumulator'range => '0') when reset_phase = '1'
else state.phase_accumulator + phase_increment;
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
phase <= state.phase_accumulator;
end architecture;
|
-------------------------------------------------------------------------------
--! @file statusControlReg.vhd
--
--! @brief Host interface Status-/Control Registers
--
--! @details The host interface status/control registers provide memory mapped
--! control of the interrupt generator (irqGen) and bridge (magicBridge).
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use global library
use work.global.all;
--! use host interface package for specific types
use work.hostInterfacePkg.all;
entity statusControlReg is
generic (
--! Magic
gMagic : natural := 16#504C4B00#;
-- Version
--! Version major
gVersionMajor : natural := 16#FF#;
--! Version minor
gVersionMinor : natural := 16#FF#;
--! Version revision
gVersionRevision : natural := 16#FF#;
--! Version count pattern
gVersionCount : natural := 0;
-- BaseSets
--! BaseSets by Host
gHostBaseSet : natural := 2;
--! BaseSets by Pcp
gPcpBaseSet : natural := 10;
--! Interrupt source number
gIrqSourceCount : natural range 1 to 15 := 3
);
port (
-- Global
--! component wide clock signal
iClk : in std_logic;
--! component wide reset signal
iRst : in std_logic;
-- slave Host interface
--! host read
iHostRead : in std_logic;
--! host write
iHostWrite : in std_logic;
--! host byteenable
iHostByteenable : in std_logic_vector(cDword/8-1 downto 0);
--! host address
iHostAddress : in std_logic_vector(10 downto 2);
--! host readdata
oHostReaddata : out std_logic_vector(cDword-1 downto 0);
--! host writedata
iHostWritedata : in std_logic_vector(cDword-1 downto 0);
--! host waitrequest
oHostWaitrequest : out std_logic;
-- slave PCP interface
--! pcp read
iPcpRead : in std_logic;
--! pcp write
iPcpWrite : in std_logic;
--! pcp byteenable
iPcpByteenable : in std_logic_vector(cDword/8-1 downto 0);
--! pcp address
iPcpAddress : in std_logic_vector(10 downto 2);
--! pcp readdata
oPcpReaddata : out std_logic_vector(cDword-1 downto 0);
--! pcp writedata
iPcpWritedata : in std_logic_vector(cDword-1 downto 0);
--! pcp waitrequest
oPcpWaitrequest : out std_logic;
-- BaseSet link
--! BaseSet write strobe
oBaseSetWrite : out std_logic;
--! BaseSet read strobe
oBaseSetRead : out std_logic;
--! BaseSet byteenable
oBaseSetByteenable : out std_logic_vector;
--! BaseSet address bus
oBaseSetAddress : out std_logic_vector(LogDualis(gHostBaseSet+gPcpBaseSet)+2-1 downto 2);
--! BaseSet read data bus
iBaseSetData : in std_logic_vector;
--! BaseSet write data bus
oBaseSetData : out std_logic_vector;
--! BaseSet acknowledge
iBaseSetAck : in std_logic;
-- Interrupt control
--! master enable
oIrqMasterEnable : out std_logic;
--! interrupt source enable vector ('right is sync)
oIrqSourceEnable : out std_logic_vector(gIrqSourceCount downto 0);
--! interrupt acknowledge (pulse, 'right is sync)
oIrqAcknowledge : out std_logic_vector(gIrqSourceCount downto 0);
--! interrup set (pulse, no sync!)
oIrqSet : out std_logic_vector(gIrqSourceCount downto 1);
--! interrupt source pending
iIrqPending : in std_logic_vector(gIrqSourceCount downto 0);
--! external sync source enable
oExtSyncEnable : out std_logic;
--! external sync source config
oExtSyncConfig : out std_logic_vector(cExtSyncEdgeConfigWidth-1 downto 0);
-- miscellaneous
--! Node Id
iNodeId : in std_logic_vector(cByte-1 downto 0);
--! LED
oPLed : out std_logic_vector(1 downto 0);
--! bridge activates
oBridgeEnable : out std_logic
);
end statusControlReg;
architecture Rtl of statusControlReg is
-- base for register content
--! magic base
constant cBaseMagic : natural := 16#0000#;
--! version base
constant cBaseVersion : natural := 16#0004#;
--! boot base
constant cBaseBootBase : natural := 16#0008#;
--! init base
constant cBaseInitBase : natural := 16#000C#;
--! bridge enable base
constant cBaseBridgeEnable : natural := 16#0200#;
--! command base
constant cBaseCommand : natural := 16#0204#;
--! state base
constant cBaseState : natural := 16#0206#;
--! error base
constant cBaseError : natural := 16#0208#;
--! heart beat
constant cBaseHeartBeat : natural := 16#020A#;
--! node id in base
constant cBaseNodeIdIn : natural := 16#020C#;
--! led control base
constant cBaseLedControl : natural := 16#0210#;
--! irq enable base
constant cBaseIrqEnable : natural := 16#0300#;
--! irq pending base
constant cBaseIrqPending : natural := 16#0302#;
--! irq master enable base
constant cBaseIrqMasterEnable : natural := 16#0304#;
--! irq ack base (host only)
constant cBaseIrqAck : natural := 16#0306#;
--! irq set base (pcp only)
constant cBaseIrqSet : natural := 16#0306#;
--! sync config base
constant cBaseSyncConfig : natural := 16#030C#;
--! base for base set
constant cBaseBaseSet : natural := 16#0400#;
--! base reserved
constant cBaseReserved : natural := 16#0500#;
--! LED count
constant cLedCount : natural range 1 to 16 := 2;
--! General Purpose Inputs
--! type base registers (stored content)
type tRegisterInfo is record
--magic
--version
bootBase : std_logic_vector(cDword-1 downto 0);
initBase : std_logic_vector(cDword-1 downto 0);
end record;
--! type control register (stored content)
type tRegisterControl is record
bridgeEnable : std_logic;
command : std_logic_vector(cWord-1 downto 0);
state : std_logic_vector(cWord-1 downto 0);
error : std_logic_vector(cWord-1 downto 0);
heartBeat : std_logic_vector(cWord-1 downto 0);
led : std_logic_vector(cLedCount-1 downto 0);
end record;
--! type synchronization register (stored content)
type tRegisterSynchronization is record
irqSrcEnableHost : std_logic_vector(gIrqSourceCount downto 0);
irqSrcEnablePcp : std_logic_vector(gIrqSourceCount downto 0);
irqMasterEnable : std_logic;
syncConfig : std_logic_vector(cExtSyncConfigWidth-1 downto 0);
end record;
--! info register
signal regInfo, regInfo_next : tRegisterInfo;
--! info register initialisation
constant cRegInfoInit : tRegisterInfo := (
bootBase => (others => cInactivated),
initBase => (others => cInactivated)
);
--! control register
signal regControl : tRegisterControl;
--! control register next
signal regControl_next : tRegisterControl;
--! control register initialisation
constant cRegControlInit : tRegisterControl := (
bridgeEnable => cInactivated,
command => (others => cInactivated),
state => (others => cInactivated),
error => (others => cInactivated),
heartBeat => (others => cInactivated),
led => (others => cInactivated)
);
--! synchronization register
signal regSynchron : tRegisterSynchronization;
--! synchronization register next
signal regSynchron_next : tRegisterSynchronization;
--! synchronization register initialisation
constant cRegSynchronInit : tRegisterSynchronization := (
irqSrcEnableHost => (others => cInactivated),
irqSrcEnablePcp => (others => cInactivated),
irqMasterEnable => cInactivated,
syncConfig => (others => cInactivated)
);
--! host base writedata
signal hostBaseSetData : std_logic_vector(iBaseSetData'range);
--! host base write
signal hostBaseSetWrite : std_logic;
--! host base read
signal hostBaseSetRead : std_logic;
--! pcp base writedata
signal pcpBaseSetData : std_logic_vector(iBaseSetData'range);
--! pcp base write
signal pcpBaseSetWrite : std_logic;
--! pcp base read
signal pcpBaseSetRead : std_logic;
begin
--! register process creates storage of values
regClk : process(iClk)
begin
if rising_edge(iClk) then
if iRst = cActivated then
regInfo <= cRegInfoInit;
regControl <= cRegControlInit;
regSynchron <= cRegSynchronInit;
else
regInfo <= regInfo_next;
regControl <= regControl_next;
regSynchron <= regSynchron_next;
end if;
end if;
end process;
oHostWaitrequest <= not iBaseSetAck when (hostBaseSetRead = cActivated or
hostBaseSetWrite = cActivated) else
not(iHostWrite or iHostRead);
oPcpWaitrequest <= not iBaseSetAck when (pcpBaseSetRead = cActivated or
pcpBaseSetWrite = cActivated) else
not(iPcpWrite or iPcpRead);
oIrqMasterEnable <= regSynchron.irqMasterEnable;
oIrqSourceEnable <= regSynchron.irqSrcEnableHost and regSynchron.irqSrcEnablePcp;
oExtSyncEnable <= regSynchron.syncConfig(0);
oExtSyncConfig <= regSynchron.syncConfig(2 downto 1);
oPLed <= regControl.led;
oBridgeEnable <= regControl.bridgeEnable;
-- pcp overrules host!
oBaseSetData <= pcpBaseSetData when pcpBaseSetWrite = cActivated else
pcpBaseSetData when pcpBaseSetRead = cActivated else
hostBaseSetData;
oBaseSetByteenable <= iPcpByteenable when pcpBaseSetWrite = cActivated else
iPcpByteenable when pcpBaseSetRead = cActivated else
iHostByteenable;
oBaseSetAddress <= std_logic_vector(unsigned(iPcpAddress(oBaseSetAddress'range))+gHostBaseSet)
when pcpBaseSetRead = cActivated or pcpBaseSetWrite = cActivated else
iHostAddress(oBaseSetAddress'range);
oBaseSetWrite <= pcpBaseSetWrite or hostBaseSetWrite;
oBaseSetRead <= pcpBaseSetRead or hostBaseSetRead;
--! register access
regAcc : process (
iHostWrite,
iHostByteenable,
iHostAddress,
iHostWritedata,
iPcpWrite,
iPcpByteenable,
iPcpAddress,
iPcpWritedata,
iNodeId,
regInfo,
regControl,
regSynchron,
iIrqPending,
iBaseSetData
)
variable vHostSelAddr : natural;
variable vPcpSelAddr : natural;
begin
-- default
-- registers
regInfo_next <= regInfo;
regControl_next <= regControl;
regSynchron_next <= regSynchron;
-- outputs
oHostReaddata <= (others => cInactivated);
oIrqAcknowledge <= (others => cInactivated);
hostBaseSetData <= (others => cInactivated);
hostBaseSetWrite <= cInactivated;
hostBaseSetRead <= cInactivated;
oIrqSet <= (others => cInactivated);
oPcpReaddata <= (others => cInactivated);
pcpBaseSetData <= (others => cInactivated);
pcpBaseSetWrite <= cInactivated;
pcpBaseSetRead <= cInactivated;
-- HOST
-- select content
-- write to content
-- and read from content
vHostSelAddr := to_integer(unsigned(iHostAddress))*4;
case vHostSelAddr is
when cBaseMagic =>
oHostReaddata <= std_logic_vector(to_unsigned(gMagic, cDword));
--magic is RO
when cBaseVersion =>
oHostReaddata <=
std_logic_vector(to_unsigned(gVersionMajor, cByte)) &
std_logic_vector(to_unsigned(gVersionMinor, cByte)) &
std_logic_vector(to_unsigned(gVersionRevision, cByte)) &
std_logic_vector(to_unsigned(gVersionCount, cByte));
--version is RO
when cBaseBootBase =>
oHostReaddata <= regInfo.bootBase;
--bootBase is RO
when cBaseInitBase =>
oHostReaddata <= regInfo.initBase;
--initBase is RO
when cBaseBridgeEnable =>
oHostReaddata(0) <= regControl.bridgeEnable;
--bridge enable is RO
when cBaseState | cBaseCommand =>
oHostReaddata <= regControl.state & regControl.command;
if iHostWrite = cActivated then
--state is RO
if iHostByteenable(1) = cActivated then
regControl_next.command(cWord-1 downto cByte) <= iHostWritedata(cWord-1 downto cByte);
end if;
if iHostByteenable(0) = cActivated then
regControl_next.command(cByte-1 downto 0) <= iHostWritedata(cByte-1 downto 0);
end if;
end if;
when cBaseHeartBeat | cBaseError =>
oHostReaddata <= regControl.heartBeat & regControl.error;
--heartbeat and error are RO
when cBaseNodeIdIn =>
oHostReaddata(iNodeId'length-1 downto 0) <= iNodeId;
--node id are RO
when cBaseLedControl =>
oHostReaddata(cLedCount-1 downto 0) <= regControl.led;
if iHostWrite = cActivated then
for i in cWord-1 downto 0 loop
if iHostByteenable(i/cByte) = cActivated and
i < cLedCount then
regControl_next.led(i) <= iHostWritedata(i);
end if;
end loop;
end if;
when cBaseIrqPending | cBaseIrqEnable =>
oHostReaddata(cWord+gIrqSourceCount downto cWord) <= iIrqPending;
oHostReaddata(gIrqSourceCount downto 0) <= regSynchron.irqSrcEnableHost;
if iHostWrite = cActivated then
for i in cWord-1 downto 0 loop
if iHostByteenable(i/cByte) = cActivated and
i <= gIrqSourceCount then
regSynchron_next.irqSrcEnableHost(i) <= iHostWritedata(i);
end if;
end loop;
end if;
when cBaseIrqAck | cBaseIrqMasterEnable =>
-- irq ack is SC
oHostReaddata(0) <= regSynchron.irqMasterEnable;
if iHostWrite = cActivated then
if iHostByteenable(0) = cActivated then
regSynchron_next.irqMasterEnable <= iHostWritedata(0);
end if;
for i in cDword-1 downto cWord loop
if iHostByteenable(i/cByte) = cActivated and
(i-cWord) <= gIrqSourceCount then
oIrqAcknowledge(i-cWord) <= iHostWritedata(i);
end if;
end loop;
end if;
when cBaseSyncConfig =>
oHostReaddata(cExtSyncConfigWidth-1 downto 0) <= regSynchron.syncConfig;
if iHostWrite = cActivated then
for i in cWord-1 downto 0 loop
if iHostByteenable(i/cByte) = cActivated and
i < cExtSyncConfigWidth then
regSynchron_next.syncConfig(i) <= iHostWritedata(i);
end if;
end loop;
end if;
when cBaseBaseSet to cBaseReserved-1 =>
if vHostSelAddr < cBaseBaseSet+gHostBaseSet*cDword/cByte then
oHostReaddata(iBaseSetData'range) <= iBaseSetData;
if iHostWrite = cActivated then
hostBaseSetData <= iHostWritedata(hostBaseSetData'range);
hostBaseSetWrite <= cActivated;
else
hostBaseSetRead <= cActivated;
end if;
end if;
when others => null;
end case;
-- PCP
-- select content
-- write to content
-- and read from content
vPcpSelAddr := to_integer(unsigned(iPcpAddress)) * 4;
case vPcpSelAddr is
when cBaseMagic =>
oPcpReaddata <= std_logic_vector(to_unsigned(gMagic, cDword));
--magic is RO
when cBaseVersion =>
oPcpReaddata <=
std_logic_vector(to_unsigned(gVersionMajor, cByte)) &
std_logic_vector(to_unsigned(gVersionMinor, cByte)) &
std_logic_vector(to_unsigned(gVersionRevision, cByte)) &
std_logic_vector(to_unsigned(gVersionCount, cByte));
--version is RO
when cBaseBootBase =>
oPcpReaddata <= regInfo.bootBase;
if iPcpWrite = cActivated then
for i in cDword-1 downto 0 loop
if iPcpByteenable(i/cByte) = cActivated then
regInfo_next.bootBase(i) <= iPcpWritedata(i);
end if;
end loop;
end if;
when cBaseInitBase =>
oPcpReaddata <= regInfo.initBase;
if iPcpWrite = cActivated then
for i in cDword-1 downto 0 loop
if iPcpByteenable(i/cByte) = cActivated then
regInfo_next.initBase(i) <= iPcpWritedata(i);
end if;
end loop;
end if;
when cBaseBridgeEnable =>
oPcpReaddata(0) <= regControl.bridgeEnable;
if iPcpWrite = cActivated then
regControl_next.bridgeEnable <= iPcpWritedata(0);
end if;
when cBaseState | cBaseCommand =>
oPcpReaddata <= regControl.state & regControl.command;
if iPcpWrite = cActivated then
for i in cDword-1 downto cWord loop
if iPcpByteenable(i/cByte) = cActivated then
regControl_next.state(i-cWord) <= iPcpWritedata(i);
end if;
end loop;
for i in cWord-1 downto 0 loop
if iPcpByteenable(i/cByte) = cActivated then
regControl_next.command(i) <= iPcpWritedata(i);
end if;
end loop;
end if;
when cBaseHeartBeat | cBaseError =>
oPcpReaddata <= regControl.heartBeat & regControl.error;
if iPcpWrite = cActivated then
for i in cDword-1 downto cWord loop
if iPcpByteenable(i/cByte) = cActivated then
regControl_next.heartBeat(i-cWord) <= iPcpWritedata(i);
end if;
end loop;
for i in cWord-1 downto 0 loop
if iPcpByteenable(i/cByte) = cActivated then
regControl_next.error(i) <= iPcpWritedata(i);
end if;
end loop;
end if;
when cBaseNodeIdIn =>
oPcpReaddata(iNodeId'length-1 downto 0) <= iNodeId;
when cBaseLedControl =>
oPcpReaddata(cLedCount-1 downto 0) <= regControl.led;
when cBaseIrqPending | cBaseIrqEnable =>
oPcpReaddata(cWord+gIrqSourceCount downto cWord) <= iIrqPending;
oPcpReaddata(gIrqSourceCount downto 0) <= regSynchron.irqSrcEnablePcp;
if iPcpWrite = cActivated then
for i in cWord-1 downto 0 loop
if iPcpByteenable(i/cByte) = cActivated and
i <= gIrqSourceCount then
regSynchron_next.irqSrcEnablePcp(i) <= iPcpWritedata(i);
end if;
end loop;
end if;
when cBaseIrqSet | cBaseIrqMasterEnable =>
-- irq set is self-clearing
oPcpReaddata(0) <= regSynchron.irqMasterEnable;
if iPcpWrite = cActivated then
for i in cDword-1 downto cWord+1 loop
if iPcpByteenable(i/cByte) = cActivated and
(i-cWord) <= gIrqSourceCount then
oIrqSet(i-cWord) <= iPcpWritedata(i);
end if;
end loop;
end if;
when cBaseSyncConfig =>
oPcpReaddata(cExtSyncConfigWidth-1 downto 0) <=
regSynchron.syncConfig;
when cBaseBaseSet to cBaseReserved-1 =>
if vPcpSelAddr < cBaseBaseSet+gPcpBaseSet*cDword/cByte then
oPcpReaddata(iBaseSetData'range) <= iBaseSetData;
if iPcpWrite = cActivated then
pcpBaseSetData <= iPcpWritedata(pcpBaseSetData'range);
pcpBaseSetWrite <= cActivated;
else
pcpBaseSetRead <= cActivated;
end if;
end if;
when others => null;
end case;
end process;
end Rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity crc8_blkrom is
port(
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(31 downto 0)
);
end entity;
architecture behavior of crc8_blkrom is
type array256x32 is array(0 to 255) of std_logic_vector(31 downto 0);
constant data_array : array256x32 := (
"00000000000000000000000000000000",
"00000100110000010001110110110111",
"00001001100000100011101101101110",
"00001101010000110010011011011001",
"00010011000001000111011011011100",
"00010111110001010110101101101011",
"00011010100001100100110110110010",
"00011110010001110101000000000101",
"00100110000010001110110110111000",
"00100010110010011111000000001111",
"00101111100010101101011011010110",
"00101011010010111100101101100001",
"00110101000011001001101101100100",
"00110001110011011000011011010011",
"00111100100011101010000000001010",
"00111000010011111011110110111101",
"01001100000100011101101101110000",
"01001000110100001100011011000111",
"01000101100100111110000000011110",
"01000001010100101111110110101001",
"01011111000101011010110110101100",
"01011011110101001011000000011011",
"01010110100101111001011011000010",
"01010010010101101000101101110101",
"01101010000110010011011011001000",
"01101110110110000010101101111111",
"01100011100110110000110110100110",
"01100111010110100001000000010001",
"01111001000111010100000000010100",
"01111101110111000101110110100011",
"01110000100111110111101101111010",
"01110100010111100110011011001101",
"10011000001000111011011011100000",
"10011100111000101010101101010111",
"10010001101000011000110110001110",
"10010101011000001001000000111001",
"10001011001001111100000000111100",
"10001111111001101101110110001011",
"10000010101001011111101101010010",
"10000110011001001110011011100101",
"10111110001010110101101101011000",
"10111010111010100100011011101111",
"10110111101010010110000000110110",
"10110011011010000111110110000001",
"10101101001011110010110110000100",
"10101001111011100011000000110011",
"10100100101011010001011011101010",
"10100000011011000000101101011101",
"11010100001100100110110110010000",
"11010000111100110111000000100111",
"11011101101100000101011011111110",
"11011001011100010100101101001001",
"11000111001101100001101101001100",
"11000011111101110000011011111011",
"11001110101101000010000000100010",
"11001010011101010011110110010101",
"11110010001110101000000000101000",
"11110110111110111001110110011111",
"11111011101110001011101101000110",
"11111111011110011010011011110001",
"11100001001111101111011011110100",
"11100101111111111110101101000011",
"11101000101111001100110110011010",
"11101100011111011101000000101101",
"00110100100001100111000001110111",
"00110000010001110110110111000000",
"00111101000001000100101100011001",
"00111001110001010101011010101110",
"00100111100000100000011010101011",
"00100011010000110001101100011100",
"00101110000000000011110111000101",
"00101010110000010010000001110010",
"00010010100011101001110111001111",
"00010110010011111000000001111000",
"00011011000011001010011010100001",
"00011111110011011011101100010110",
"00000001100010101110101100010011",
"00000101010010111111011010100100",
"00001000000010001101000001111101",
"00001100110010011100110111001010",
"01111000100101111010101100000111",
"01111100010101101011011010110000",
"01110001000101011001000001101001",
"01110101110101001000110111011110",
"01101011100100111101110111011011",
"01101111010100101100000001101100",
"01100010000100011110011010110101",
"01100110110100001111101100000010",
"01011110100111110100011010111111",
"01011010010111100101101100001000",
"01010111000111010111110111010001",
"01010011110111000110000001100110",
"01001101100110110011000001100011",
"01001001010110100010110111010100",
"01000100000110010000101100001101",
"01000000110110000001011010111010",
"10101100101001011100011010010111",
"10101000011001001101101100100000",
"10100101001001111111110111111001",
"10100001111001101110000001001110",
"10111111101000011011000001001011",
"10111011011000001010110111111100",
"10110110001000111000101100100101",
"10110010111000101001011010010010",
"10001010101011010010101100101111",
"10001110011011000011011010011000",
"10000011001011110001000001000001",
"10000111111011100000110111110110",
"10011001101010010101110111110011",
"10011101011010000100000001000100",
"10010000001010110110011010011101",
"10010100111010100111101100101010",
"11100000101101000001110111100111",
"11100100011101010000000001010000",
"11101001001101100010011010001001",
"11101101111101110011101100111110",
"11110011101100000110101100111011",
"11110111011100010111011010001100",
"11111010001100100101000001010101",
"11111110111100110100110111100010",
"11000110101111001111000001011111",
"11000010011111011110110111101000",
"11001111001111101100101100110001",
"11001011111111111101011010000110",
"11010101101110001000011010000011",
"11010001011110011001101100110100",
"11011100001110101011110111101101",
"11011000111110111010000001011010",
"01101001000011001110000011101110",
"01101101110011011111110101011001",
"01100000100011101101101110000000",
"01100100010011111100011000110111",
"01111010000010001001011000110010",
"01111110110010011000101110000101",
"01110011100010101010110101011100",
"01110111010010111011000011101011",
"01001111000001000000110101010110",
"01001011110001010001000011100001",
"01000110100001100011011000111000",
"01000010010001110010101110001111",
"01011100000000000111101110001010",
"01011000110000010110011000111101",
"01010101100000100100000011100100",
"01010001010000110101110101010011",
"00100101000111010011101110011110",
"00100001110111000010011000101001",
"00101100100111110000000011110000",
"00101000010111100001110101000111",
"00110110000110010100110101000010",
"00110010110110000101000011110101",
"00111111100110110111011000101100",
"00111011010110100110101110011011",
"00000011000101011101011000100110",
"00000111110101001100101110010001",
"00001010100101111110110101001000",
"00001110010101101111000011111111",
"00010000000100011010000011111010",
"00010100110100001011110101001101",
"00011001100100111001101110010100",
"00011101010100101000011000100011",
"11110001001011110101011000001110",
"11110101111011100100101110111001",
"11111000101011010110110101100000",
"11111100011011000111000011010111",
"11100010001010110010000011010010",
"11100110111010100011110101100101",
"11101011101010010001101110111100",
"11101111011010000000011000001011",
"11010111001001111011101110110110",
"11010011111001101010011000000001",
"11011110101001011000000011011000",
"11011010011001001001110101101111",
"11000100001000111100110101101010",
"11000000111000101101000011011101",
"11001101101000011111011000000100",
"11001001011000001110101110110011",
"10111101001111101000110101111110",
"10111001111111111001000011001001",
"10110100101111001011011000010000",
"10110000011111011010101110100111",
"10101110001110101111101110100010",
"10101010111110111110011000010101",
"10100111101110001100000011001100",
"10100011011110011101110101111011",
"10011011001101100110000011000110",
"10011111111101110111110101110001",
"10010010101101000101101110101000",
"10010110011101010100011000011111",
"10001000001100100001011000011010",
"10001100111100110000101110101101",
"10000001101100000010110101110100",
"10000101011100010011000011000011",
"01011101100010101001000010011001",
"01011001010010111000110100101110",
"01010100000010001010101111110111",
"01010000110010011011011001000000",
"01001110100011101110011001000101",
"01001010010011111111101111110010",
"01000111000011001101110100101011",
"01000011110011011100000010011100",
"01111011100000100111110100100001",
"01111111010000110110000010010110",
"01110010000000000100011001001111",
"01110110110000010101101111111000",
"01101000100001100000101111111101",
"01101100010001110001011001001010",
"01100001000001000011000010010011",
"01100101110001010010110100100100",
"00010001100110110100101111101001",
"00010101010110100101011001011110",
"00011000000110010111000010000111",
"00011100110110000110110100110000",
"00000010100111110011110100110101",
"00000110010111100010000010000010",
"00001011000111010000011001011011",
"00001111110111000001101111101100",
"00110111100100111010011001010001",
"00110011010100101011101111100110",
"00111110000100011001110100111111",
"00111010110100001000000010001000",
"00100100100101111101000010001101",
"00100000010101101100110100111010",
"00101101000101011110101111100011",
"00101001110101001111011001010100",
"11000101101010010010011001111001",
"11000001011010000011101111001110",
"11001100001010110001110100010111",
"11001000111010100000000010100000",
"11010110101011010101000010100101",
"11010010011011000100110100010010",
"11011111001011110110101111001011",
"11011011111011100111011001111100",
"11100011101000011100101111000001",
"11100111011000001101011001110110",
"11101010001000111111000010101111",
"11101110111000101110110100011000",
"11110000101001011011110100011101",
"11110100011001001010000010101010",
"11111001001001111000011001110011",
"11111101111001101001101111000100",
"10001001101110001111110100001001",
"10001101011110011110000010111110",
"10000000001110101100011001100111",
"10000100111110111101101111010000",
"10011010101111001000101111010101",
"10011110011111011001011001100010",
"10010011001111101011000010111011",
"10010111111111111010110100001100",
"10101111101100000001000010110001",
"10101011011100010000110100000110",
"10100110001100100010101111011111",
"10100010111100110011011001101000",
"10111100101101000110011001101101",
"10111000011101010111101111011010",
"10110101001101100101110100000011",
"10110001111101110100000010110100");
begin
process( clk )
begin
if rising_edge( clk ) then
dout <= data_array(conv_integer(addr));
end if;
end process;
end behavior;
|
-- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
---------------------------------------------------------------------------------------------------------}}}
entity RTM is
-- ports {{{
port(
clk : in std_logic;
rtm_rdAddr : in unsigned(RTM_ADDR_W-1 downto 0); -- level 13.
rtm_rdData : out unsigned(RTM_DATA_W-1 downto 0) := (others=> '0'); -- level 15.
rtm_wrData_cv : in unsigned(DATA_W-1 downto 0) := (others => '0');
rtm_wrAddr_cv : in unsigned(N_WF_CU_W+2-1 downto 0) := (others => '0');
rtm_we_cv : in std_logic := '0';
rtm_wrAddr_wg : in unsigned(RTM_ADDR_W-1 downto 0) := (others => '0');
rtm_wrData_wg : in unsigned(RTM_DATA_W-1 downto 0) := (others => '0'); -- from _wg_dispatcher
rtm_we_wg : in std_logic;
WGsDispatched : in std_logic;
start_CUs : in std_logic;
nrst : in std_logic
);
-- }}}
end RTM;
architecture Behavioral of RTM is
-- signals definitions {{{
signal rtm : rtm_ram_type(0 to RTM_SIZE-1) := (others => (others => '0'));
signal rtm_wrData, rtm_wrData_n : unsigned(RTM_DATA_W-1 downto 0) := (others => '0');
signal rtm_rdData_n : unsigned(RTM_DATA_W-1 downto 0) := (others => '0');
signal rtm_wrAddr, rtm_wrAddr_n : unsigned(RTM_ADDR_W-1 downto 0) := (others => '0');
signal rtm_we, rtm_we_n : std_logic := '0';
type st_rtm_write_type is (wg_dispatcher, cv_Dispatcher);
signal st_rtm_write : st_rtm_write_type := wg_dispatcher;
signal st_rtm_write_n : st_rtm_write_type := wg_dispatcher;
-- }}}
begin
-- Local Memory -------------------------------------------------------------------------------------------{{{
---------------------------------------------------------------------------------------------------------}}}
-- RTM ram ------------------------------------------------------------------------------------ {{{
process(clk)
begin
if rising_edge(clk) then
if rtm_we = '1' then
rtm(to_integer(rtm_wrAddr)) <= rtm_wrData;
end if;
rtm_rdData_n <= rtm(to_integer(rtm_rdAddr)); -- @ 14.
rtm_rdData <= rtm_rdData_n; -- @ 15.
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
rtm_wrData <= rtm_wrData_n;
rtm_wrAddr <= rtm_wrAddr_n;
if nrst = '0' then
st_rtm_write <= wg_dispatcher;
rtm_we <= '0';
else
st_rtm_write <= st_rtm_write_n;
rtm_we <= rtm_we_n;
end if;
end if;
end process;
process(st_rtm_write, start_CUs, WGsDispatched, rtm_wrAddr_cv, rtm_wrAddr_wg, rtm_wrData_cv, rtm_wrData_wg, rtm_we_cv, rtm_we_wg, rtm_wrData, rtm_wrAddr, rtm_we)
begin
st_rtm_write_n <= st_rtm_write;
rtm_wrAddr_n <= rtm_wrAddr;
rtm_wrData_n <= rtm_wrData;
rtm_we_n <= rtm_we;
case st_rtm_write is
when wg_dispatcher =>
if start_CUs = '1' then
st_rtm_write_n <= cv_Dispatcher;
end if;
rtm_wrAddr_n <= rtm_wrAddr_wg;
rtm_wrData_n <= rtm_wrData_wg;
rtm_we_n <= rtm_we_wg;
when cv_Dispatcher =>
if WGsDispatched = '1' then
st_rtm_write_n <= wg_dispatcher;
end if;
rtm_wrAddr_n(RTM_ADDR_W-1) <= '1';
rtm_wrAddr_n(RTM_ADDR_W-2 downto PHASE_W) <= rtm_wrAddr_cv;
rtm_wrAddr_n(PHASE_W-1 downto 0) <= (others=>'0');
rtm_wrData_n(DATA_W-1 downto 0) <= rtm_wrData_cv;
rtm_we_n <= rtm_we_cv;
end case;
end process;
---------------------------------------------------------------------------------------------------------}}}
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity comp200 is
port(
clkcmp2: in std_logic ;
codopcmp2: in std_logic_vector ( 3 downto 0 );
portAcmp2: in std_logic_vector ( 7 downto 0 );
inFlagcmp2: in std_logic;
outcmp2: out std_logic_vector ( 7 downto 0 );
outFlagcmp2: out std_logic );
end;
architecture comp20 of comp200 is
begin
pcomp2: process(codopcmp2, portAcmp2)
begin
if(codopcmp2 = "0111") then
outcmp2 <= not(portAcmp2)+1;
outFlagcmp2 <= '1';
else
outcmp2 <= (others => 'Z');
outFlagcmp2 <= 'Z';
end if;
end process pcomp2;
-- pnand: process(clknd, codopnd, inFlagnd)
-- --variable auxnd: bit:='0';
-- begin
-- if (clknd = '1') then
----clknd'event and
-- if (codopnd = "0100") then
-- if (inFlagnd = '1') then
-- --if (auxnd = '0') then
-- --auxnd:= '1';
-- outnd <= portAnd nand portBnd;
-- outFlagnd <= '1';
-- --end if;
-- else
-- outFlagnd <= '0';
-- end if;
-- else
-- outnd <= (others => 'Z');
-- outFlagnd <= 'Z';
-- --auxnd:='0';
-- end if;
-- end if;
-- end process pnand;
end comp20;
|
-------------------------------------------------------------------------------
--! @project Unrolled (factor 2) hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DiffusionLayer is
generic( SHIFT1 : integer range 0 to 63;
SHIFT2 : integer range 0 to 63);
port( Input : in std_logic_vector(63 downto 0);
Output : out std_logic_vector(63 downto 0));
end entity DiffusionLayer;
architecture structural of DiffusionLayer is
begin
DiffLayer: process(Input) is
variable Temp0,Temp1 : std_logic_vector(63 downto 0);
begin
Temp0(63 downto 64-SHIFT1) := Input(SHIFT1-1 downto 0);
Temp0(63-SHIFT1 downto 0) := Input(63 downto SHIFT1);
Temp1(63 downto 64-SHIFT2) := Input(SHIFT2-1 downto 0);
Temp1(63-SHIFT2 downto 0) := Input(63 downto SHIFT2);
Output <= Temp0 xor Temp1 xor Input;
end process DiffLayer;
end architecture structural;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hls_saturation_endEe_DSP48_0 is
port (
in0: in std_logic_vector(20 - 1 downto 0);
in1: in std_logic_vector(16 - 1 downto 0);
in2: in std_logic_vector(27 - 1 downto 0);
dout: out std_logic_vector(36 - 1 downto 0));
end entity;
architecture behav of hls_saturation_endEe_DSP48_0 is
signal a : signed(25-1 downto 0);
signal b : signed(18-1 downto 0);
signal c : signed(48-1 downto 0);
signal m : signed(43-1 downto 0);
signal p : signed(48-1 downto 0);
begin
a <= signed(resize(unsigned(in0), 25));
b <= signed(resize(signed(in1), 18));
c <= signed(resize(unsigned(in2), 48));
m <= a * b;
p <= m + c;
dout <= std_logic_vector(resize(unsigned(p), 36));
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity hls_saturation_endEe is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
din2 : IN STD_LOGIC_VECTOR(din2_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of hls_saturation_endEe is
component hls_saturation_endEe_DSP48_0 is
port (
in0 : IN STD_LOGIC_VECTOR;
in1 : IN STD_LOGIC_VECTOR;
in2 : IN STD_LOGIC_VECTOR;
dout : OUT STD_LOGIC_VECTOR);
end component;
begin
hls_saturation_endEe_DSP48_0_U : component hls_saturation_endEe_DSP48_0
port map (
in0 => din0,
in1 => din1,
in2 => din2,
dout => dout);
end architecture;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY keyboard IS
PORT( keyboard_clk, keyboard_data, clock_48Mhz ,
reset, read : IN STD_LOGIC;
scan_code : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
scan_ready : OUT STD_LOGIC);
END keyboard;
ARCHITECTURE a OF keyboard IS
SIGNAL INCNT : std_logic_vector(3 downto 0);
SIGNAL SHIFTIN : std_logic_vector(8 downto 0);
SIGNAL READ_CHAR, clock_enable : std_logic;
SIGNAL INFLAG, ready_set : std_logic;
SIGNAL keyboard_clk_filtered : std_logic;
SIGNAL filter : std_logic_vector(7 downto 0);
BEGIN
PROCESS (read, ready_set)
BEGIN
IF read = '1' THEN scan_ready <= '0';
ELSIF ready_set'EVENT and ready_set = '1' THEN
scan_ready <= '1';
END IF;
END PROCESS;
--This process filters the raw clock signal coming from the keyboard using a shift register and two AND gates
Clock_filter: PROCESS
BEGIN
WAIT UNTIL clock_48Mhz'EVENT AND clock_48Mhz= '1';
clock_enable <= NOT clock_enable;
IF clock_enable = '1' THEN
filter (6 DOWNTO 0) <= filter(7 DOWNTO 1) ;
filter(7) <= keyboard_clk;
IF filter = "11111111" THEN keyboard_clk_filtered <= '1';
ELSIF filter= "00000000" THEN keyboard_clk_filtered <= '0';
END IF;
END IF;
END PROCESS Clock_filter;
--This process reads in serial data coming from the terminal
PROCESS
BEGIN
WAIT UNTIL (KEYBOARD_CLK_filtered'EVENT AND KEYBOARD_CLK_filtered='1');
IF RESET='0' THEN
INCNT <= "0000";
READ_CHAR <= '0';
ready_set<= '0';
ELSE
IF KEYBOARD_DATA='0' AND READ_CHAR='0' THEN
READ_CHAR<= '1';
ready_set<= '0';
ELSE
-- Shift in next 8 data bits to assemble a scan code
IF READ_CHAR = '1' THEN
IF INCNT < "1001" THEN
INCNT <= INCNT + 1;
SHIFTIN(7 DOWNTO 0) <= SHIFTIN(8 DOWNTO 1);
SHIFTIN(8) <= KEYBOARD_DATA;
-- End of scan code character, so set flags and exit loop
ELSE
scan_code <= SHIFTIN(7 DOWNTO 0);
READ_CHAR <= '0';
ready_set <= '1';
INCNT <= "0000";
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END a;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: FiFo512Core32W32R_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.FiFo512Core32W32R_pkg.ALL;
ENTITY FiFo512Core32W32R_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF FiFo512Core32W32R_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:FiFo512Core32W32R_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:FiFo512Core32W32R_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ROM is
port(
clk : in std_logic;
cs : in std_logic;
read : in std_logic;
address : in std_logic_vector(9 downto 0);
rddata : out std_logic_vector(31 downto 0));
end ROM;
architecture synth of ROM is
component ROM_Block is
port(
address : in std_logic_vector(9 downto 0);
clock : in std_logic;
q : out std_logic_vector(31 downto 0)
);
end component;
-- internal signal for the ROM rddata
signal in_rddata : std_logic_vector(31 downto 0);
signal reg_read : std_logic;
begin
rom_block_0: ROM_Block port map(
address => address,
clock => clk,
q => in_rddata);
-- 1 cycle latency
process(clk)
begin
if(rising_edge(clk))then
reg_read <= read and cs;
end if;
end process;
-- read in memory
process(reg_read, in_rddata)
begin
rddata <= (others => 'Z');
if(reg_read='1')then
rddata <= in_rddata;
end if;
end process;
end synth;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 14 10:15:34 2017
-- Host : PC4719 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.vhdl
-- Design : ila_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2016.3";
begin
end;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY memory IS
GENERIC(N : POSITIVE := 8);
PORT(
clk, rst, R0s, R1s, R2s, R3s, R4s, R5s, R6s, R7s : STD_LOGIC;
din : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
R0out, R1out, R2out, R3out, R4out, R5out, R6out, R7out : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0)
);
END ENTITY memory;
Architecture Behavior OF memory IS
COMPONENT shiftregG IS
GENERIC(N : POSITIVE := 8);
PORT(
clk,rst,set : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
shift0 : shiftregG GENERIC MAP(N) PORT MAP(clk, rst, R0s, din, R0out);
shift1 : shiftregG GENERIC MAP(N) PORT MAP(clk, rst, R1s, din, R1out);
shift2 : shiftregG GENERIC MAP(N) PORT MAP(clk, rst, R2s, din, R2out);
shift3 : shiftregG GENERIC MAP(N) PORT MAP(clk, rst, R3s, din, R3out);
shift4 : shiftregG GENERIC MAP(N) PORT MAP(clk, rst, R4s, din, R4out);
shift5 : shiftregG GENERIC MAP(N) PORT MAP(clk, rst, R5s, din, R5out);
shift6 : shiftregG GENERIC MAP(N) PORT MAP(clk, rst, R6s, din, R6out);
shift7 : shiftregG GENERIC MAP(N) PORT MAP(clk, rst, R7s, din, R7out);
END Architecture Behavior;
|
architecture rtl of fifo is
begin
connect_ports(port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow);
connect_ports(
port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow);
connect_ports(port_1 => data,
port_2 => enable,
port_3 => overflow,
port_4 => underflow);
connect_ports(port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow
);
connect_ports(
port_1 => data,
port_2 => enable,
port_3 => overflow,
port_4 => underflow
);
connect_ports
(
port_1 => data,
port_2 => enable,
port_3 => overflow,
port_4 => underflow
);
process
begin
connect_ports(
port_1 => data,
port_2=> enable,
port_3 => overflow,
port_4 => underflow
);
end process;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- File: ddrrec.vhd
-- Author: David Lindh - Gaisler Research
-- Description: DDR-RAM memory controller interface records
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
use techmap.allmem.all;
package ddrrec is
-------------------------------------------------------------------------------
-- Options
-------------------------------------------------------------------------------
-- This can be changed
constant buffersize : integer := 4; -- Data buffer size, 2,4,8.,.-1024 (8 word) bursts
-------------------------------------------------------------------------------
-- Data sizes, should not haveto be changed
-------------------------------------------------------------------------------
type dm_arr is array(4 to 16) of integer;
constant dmvector : dm_arr := (2,others => 1);
constant maxdqsize : integer := 64;
constant maxdmsize : integer := 16;
constant maxstrobesize : integer := 16;
constant adrbits : integer := 16; -- BA + row/col address -1 (2+14-1)
constant ahbadr : integer := 32; -- AHB addressbits
constant ahbdata : integer := 32; -- AHB databits
constant bufferadr : integer := log2(buffersize)+2;
constant ddrcfg_reset : std_logic_vector(31 downto 0):=
'1' & --refresh
"00" & -- CAS
"00" & -- Memcmd
"10" & -- Burst length
'0' & -- Auto Precharge
"11" & -- Read prediction
"00" & -- Write protection
x"00000";
--Memory commands (RAS, CAS, WE)
constant CMD_READ : std_logic_vector(2 downto 0) := "101";
constant CMD_WRITE : std_logic_vector(2 downto 0) := "100";
constant CMD_NOP : std_logic_vector(2 downto 0) := "111";
constant CMD_ACTIVE : std_logic_vector(2 downto 0) := "011";
constant CMD_BT : std_logic_vector(2 downto 0) := "110";
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_AR : std_logic_vector(2 downto 0) := "001";
constant CMD_LMR : std_logic_vector(2 downto 0) := "000";
constant BANK0 : std_logic_vector(1 downto 0) := "10";
constant BANK1 : std_logic_vector(1 downto 0) := "01";
constant BANK01 : std_logic_vector(1 downto 0) := "00";
type burst_mask_type is array (buffersize-1 downto 0) of integer range 1 to 8;
type two_burst_mask_type is array (1 downto 0) of burst_mask_type;
type two_buf_adr_type is array (1 downto 0) of std_logic_vector((log2(buffersize)-1) downto 0);
type two_buf_data_type is array (1 downto 0) of std_logic_vector((bufferadr-1) downto 0);
type pre_row_type is array (7 downto 0) of std_logic_vector(adrbits-1 downto 0);
type two_ddr_adr_type is array (1 downto 0) of std_logic_vector(adrbits-1 downto 0);
type two_ddr_bank_type is array (1 downto 0) of std_logic_vector(1 downto 0);
type two_pre_bank_type is array (1 downto 0) of integer range 0 to 7;
type blwaittype is array (6 downto 0) of integer range 2 to 8;
type mlwaittype is array (1 downto 0) of integer range 1 to 8;
type bufwaittype is array (6 downto 0) of std_logic_vector((log2(buffersize)-1) downto 0);
type ahbwaittype is array (6 downto 0) of integer range 0 to 1;
-------------------------------------------------------------------------------
-- Records
-------------------------------------------------------------------------------
-- APB controller
type apb_ctrl_in_type is record
apbsi : apb_slv_in_type;
apb_cmd_done : std_ulogic;
ready : std_ulogic;
end record;
type apb_ctrl_out_type is record
apbso : apb_slv_out_type;
ddrcfg_reg : std_logic_vector(31 downto 0);
end record;
-------------------------------------------------------------------------------
-- Sync ram dp (data-fifo)
type syncram_dp_in_type is record
address1 : std_logic_vector((bufferadr -1) downto 0);
datain1 : std_logic_vector(2*(maxdqsize+maxdmsize)-1 downto 0);
enable1 : std_ulogic;
write1 : std_ulogic;
address2 : std_logic_vector((bufferadr-1) downto 0);
datain2 : std_logic_vector(2*(maxdqsize+maxdmsize)-1 downto 0);
enable2 : std_ulogic;
write2 : std_ulogic;
end record;
type syncram_dp_out_type is record
dataout1 : std_logic_vector(2*(maxdqsize+maxdmsize)-1 downto 0);
dataout2 : std_logic_vector(2*(maxdqsize+maxdmsize)-1 downto 0);
end record;
type two_syncram_dp_out_type is array (1 downto 0) of syncram_dp_out_type;
type two_syncram_dp_in_type is array (1 downto 0) of syncram_dp_in_type;
-------------------------------------------------------------------------------
-- Sync ram 2p (adr-fifo)
type syncram_2p_in_type is record
renable : std_ulogic;
raddress : std_logic_vector((log2(buffersize) -1) downto 0);
write : std_ulogic;
waddress : std_logic_vector((log2(buffersize)-1) downto 0);
datain : std_logic_vector((ahbadr-1+1) downto 0);
end record;
type syncram_2p_out_type is record
dataout : std_logic_vector((ahbadr-1+1) downto 0);
end record;
-----------------------------------------------------------------------------
-- High speed interface towards memory
type hs_in_type is record
bl : integer range 2 to 8;
ml : integer range 1 to 8;
cas : std_logic_vector(1 downto 0);
buf : std_logic_vector((log2(buffersize)-1) downto 0);
ahb : integer range 0 to 1;
cs : std_logic_vector(1 downto 0);
adr : std_logic_vector(adrbits-1 downto 0);
cmd : std_logic_vector(2 downto 0);
cmd_valid : std_ulogic;
dsramso : two_syncram_dp_out_type;
ddso : ddrmem_out_type;
end record;
type hs_out_type is record
hs_busy : std_ulogic;
cmdDone : two_buf_adr_type;
dsramsi : two_syncram_dp_in_type;
ddsi : ddrmem_in_type;
end record;
-----------------------------------------------------------------------------
-- AHB controller
type ahb_ctrl_in_type is record
ahbsi : ahb_slv_in_type;
asramsi : syncram_2p_in_type;
dsramsi : syncram_dp_in_type;
burstlength : integer range 2 to 8;
r_predict : std_ulogic;
w_prot : std_ulogic;
locked : std_ulogic;
rw_cmd_done : std_logic_vector((log2(buffersize) -1) downto 0);
end record;
type ahb_ctrl_out_type is record
ahbso : ahb_slv_out_type;
asramso : syncram_2p_out_type;
dsramso : syncram_dp_out_type;
rw_cmd_valid : std_logic_vector((log2(buffersize) -1) downto 0);
w_data_valid : std_logic_vector((log2(buffersize) -1) downto 0);
burst_dm : burst_mask_type;
end record;
type two_ahb_ctrl_out_type is array (1 downto 0) of ahb_ctrl_out_type;
type two_ahb_ctrl_in_type is array (1 downto 0) of ahb_ctrl_in_type;
-----------------------------------------------------------------------------
-- Main controller
type main_ctrl_in_type is record
apbctrlso : apb_ctrl_out_type;
ahbctrlso : two_ahb_ctrl_out_type;
hsso : hs_out_type;
end record;
type main_ctrl_out_type is record
apbctrlsi : apb_ctrl_in_type;
ahbctrlsi : two_ahb_ctrl_in_type;
hssi : hs_in_type;
end record;
-------------------------------------------------------------------------------
-- DDRCFG register
type config_out_type is record
refresh : std_ulogic;
cas : std_logic_vector(1 downto 0);
memcmd : std_logic_vector(1 downto 0);
bl : std_logic_vector(1 downto 0);
autopre : std_ulogic;
r_predict : std_logic_vector(1 downto 0);
w_prot : std_logic_vector(1 downto 0);
ready : std_ulogic;
end record;
-------------------------------------------------------------------------------
-- State machines
-------------------------------------------------------------------------------
type apbcycletype is (idle, refresh, cmd, wait_lmr1, wait_lmr2, cmdlmr, cmdDone, cmdDone2);
type timercycletype is (t1, t2, t3, t4);
type initcycletype is (idle, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11);
type maincycletype is (init, idle, pre1, act1, w1, r1, rw, c1, c2);
type rwcycletype is (idle, r, w);
type cmdbuffercycletype is (no_cmd, new_cmd);
type cmdcycletype is(idle, hold);
-----------------------------------------------------------------------------
-- AHB - Local variables
type ahb_reg_type is record
readcounter : integer range 0 to 8;
writecounter : integer range 0 to 8;
blockburstlength : integer range 0 to 8;
hready : std_ulogic;
hresp : std_logic_vector(1 downto 0);
rwadrbuffer : std_logic_vector((ahbadr-1) downto 0);
use_read_buffer : std_logic_vector((log2(buffersize)-1) downto 0);
pre_read_buffer : std_logic_vector((log2(buffersize)-1) downto 0);
pre_read_adr : std_logic_vector((ahbadr-1) downto 0);
pre_read_valid : std_ulogic;
use_write_buffer : std_logic_vector((log2(buffersize)-1) downto 0);
rw_cmd_valid : std_logic_vector((log2(buffersize)-1) downto 0);
w_data_valid : std_logic_vector((log2(buffersize)-1) downto 0);
sync_adr : std_logic_vector((bufferadr-1) downto 0);
sync_wdata : std_logic_vector(2*(maxdqsize+maxdmsize)-1 downto 0);
sync_write : std_ulogic;
sync_busy : std_ulogic;
sync_busy_adr : std_logic_vector((bufferadr-1) downto 0);
sync2_adr : std_logic_vector((log2(buffersize)-1) downto 0);
sync2_wdata : std_logic_vector((ahbadr-1+1) downto 0);
sync2_write : std_ulogic;
sync2_busy : std_ulogic;
doRead : std_ulogic;
doWrite : std_ulogic;
new_burst : std_ulogic;
startp : integer range 0 to 7;
ahbstartp : integer range 0 to 7;
even_odd_write : integer range 0 to 1;
burst_hsize : integer range 1 to 8;
offset : std_logic_vector(2 downto 0);
ahboffset : std_logic_vector(2 downto 0);
read_data : std_logic_vector(maxdqsize-1 downto 0);
cur_hrdata : std_logic_vector((ahbdata-1) downto 0);
cur_hready : std_ulogic;
cur_hresp : std_logic_vector(1 downto 0);
prev_retry : std_ulogic;
prev_error : std_ulogic;
burst_dm : burst_mask_type;
end record;
-------------------------------------------------------------------------------
-- APB controller - Local variables
type apb_reg_type is record
ddrcfg_reg : std_logic_vector(31 downto 0);
end record;
-------------------------------------------------------------------------------
-- High speed RW - Local variables
type rw_reg_type is record
cbufstate : cmdbuffercycletype;
cmdstate : cmdcycletype;
rwstate : rwcycletype;
cur_buf : two_buf_adr_type;
cur_ahb : integer range 0 to 1;
use_bl : integer range 2 to 8;
use_ml : integer range 1 to 8;
use_buf : std_logic_vector((log2(buffersize)-1) downto 0);
use_ahb : integer range 0 to 1;
use_cas : std_ulogic;
rw_cmd : std_logic_vector(2 downto 0);
rw_bl : integer range 2 to 8;
rw_cas : integer range 2 to 3;
next_bl : integer range 2 to 8;
next_ml : integer range 1 to 8;
next_buf : std_logic_vector((log2(buffersize)-1) downto 0);
next_ahb : integer range 0 to 1;
next_cas : std_logic_vector(1 downto 0);
next_adr : std_logic_vector(adrbits-1 downto 0);
next_cs : std_logic_vector(1 downto 0);
next_cmd : std_logic_vector(2 downto 0);
set_cmd : std_logic_vector(2 downto 0);
set_adr : std_logic_vector(adrbits-1 downto 0);
set_cs : std_logic_vector(1 downto 0);
set_cke : std_ulogic;
hs_busy : std_ulogic;
cmdDone : two_buf_adr_type;
begin_read : std_ulogic;
begin_write : std_ulogic;
dq_dqs_oe : std_ulogic;
w_ce : std_ulogic;
r_ce : std_ulogic;
cnt : integer range 0 to 8;
holdcnt : integer range 0 to 31;
r2wholdcnt : integer range 0 to 15;
act2precnt : integer range 0 to 15;
wait_time : integer range 0 to 31;
readwait : std_logic_vector(6 downto 0);
writewait : std_logic_vector(1 downto 0);
bufwait : bufwaittype;
ahbwait : ahbwaittype;
blwait : blwaittype;
mlwait : mlwaittype;
caswait : std_logic_vector(6 downto 0);
dm1_o : std_logic_vector((maxdmsize-1) downto 0);
dm2_o : std_logic_vector((maxdmsize-1) downto 0);
dqs1_o : std_ulogic;
sync_adr : two_buf_data_type;
sync_write : std_logic_vector(1 downto 0);
sync_wdata : std_logic_vector(2*(maxdqsize+maxdmsize)-1 downto 0);
end record;
-------------------------------------------------------------------------------
-- High speed CMD - Local variables
type cmd_reg_type is record
cur_cmd : std_logic_vector(2 downto 0);
cur_cs : std_logic_vector(1 downto 0);
cur_adr : std_logic_vector(adrbits-1 downto 0);
next_cmd : std_logic_vector(2 downto 0);
next_cs : std_logic_vector(1 downto 0);
next_adr : std_logic_vector(adrbits-1 downto 0);
end record;
-------------------------------------------------------------------------------
-- Main controller - Local variables
type main_reg_type is record
-- For main controller
mainstate : maincycletype;
loadcmdbuffer : std_ulogic;
cmdbufferdata : std_logic_vector(2 downto 0);
adrbufferdata : std_logic_vector(adrbits-1 downto 0);
use_ahb : integer range 0 to 1;
use_bl : integer range 2 to 8;
use_cas : std_logic_vector(1 downto 0);
use_buf : std_logic_vector((log2(buffersize)-1) downto 0);
burstlength : integer range 2 to 8;
rw_cmd_done : two_buf_adr_type;
lmradr : std_logic_vector(adrbits-1 downto 0);
memCmdDone : std_ulogic;
lockAHB : std_logic_vector(1 downto 0);
pre_row : pre_row_type;
pre_chg : std_logic_vector(7 downto 0);
pre_bankadr : two_pre_bank_type;
sync2_adr : two_buf_adr_type;
-- For init statemachine
initstate : initcycletype;
doMemInit : std_ulogic;
memInitDone : std_ulogic;
initDelay : integer range 0 to 255;
cs : std_logic_vector(1 downto 0);
-- For address calculator
coladdress : two_ddr_adr_type;
tmpcoladdress : two_ddr_adr_type;
rowaddress : two_ddr_adr_type;
addressrange : integer range 0 to 31;
tmpcolbits : integer range 0 to 15;
colbits : integer range 0 to 15;
rowbits : integer range 0 to 15;
bankselect : two_ddr_bank_type;
intbankbits : two_ddr_bank_type;
-- For refresh timer statemachine
timerstate : timercycletype;
doRefresh : std_ulogic;
refreshDone : std_ulogic;
refreshTime : integer range 0 to 4095;
maxRefreshTime : integer range 0 to 32767;
idlecnt : integer range 0 to 10;
refreshcnt : integer range 0 to 65535;
-- For DDRCFG register (APB)
apbstate : apbcycletype;
apb_cmd_done : std_ulogic;
ready : std_ulogic;
ddrcfg : config_out_type;
end record;
-------------------------------------------------------------------------------
-- Components
-------------------------------------------------------------------------------
component ahb_slv
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f80#;
sepclk : integer := 0;
dqsize : integer := 64;
dmsize : integer := 8;
tech : integer := virtex2);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
clk0 : in std_ulogic;
csi : in ahb_ctrl_in_type;
cso : out ahb_ctrl_out_type);
end component;
component ddr_in
generic (
tech : integer);
port (
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
-- DQS : in std_logic; -- used for lattice
-- DDRCLKPOL: in std_logic; -- used for lattice
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component ddr_out
generic (
tech : integer);
port (
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component hs
generic(
tech : in integer;
dqsize : in integer;
dmsize : in integer;
strobesize: in integer;
clkperiod : in integer);
port (
rst : in std_ulogic;
clk0 : in std_ulogic;
clk90 : in std_ulogic;
clk180 : in std_ulogic;
clk270 : in std_ulogic;
hclk : in std_ulogic;
hssi : in hs_in_type;
hsso : out hs_out_type);
end component;
end ddrrec;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- File: ddrrec.vhd
-- Author: David Lindh - Gaisler Research
-- Description: DDR-RAM memory controller interface records
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
use techmap.allmem.all;
package ddrrec is
-------------------------------------------------------------------------------
-- Options
-------------------------------------------------------------------------------
-- This can be changed
constant buffersize : integer := 4; -- Data buffer size, 2,4,8.,.-1024 (8 word) bursts
-------------------------------------------------------------------------------
-- Data sizes, should not haveto be changed
-------------------------------------------------------------------------------
type dm_arr is array(4 to 16) of integer;
constant dmvector : dm_arr := (2,others => 1);
constant maxdqsize : integer := 64;
constant maxdmsize : integer := 16;
constant maxstrobesize : integer := 16;
constant adrbits : integer := 16; -- BA + row/col address -1 (2+14-1)
constant ahbadr : integer := 32; -- AHB addressbits
constant ahbdata : integer := 32; -- AHB databits
constant bufferadr : integer := log2(buffersize)+2;
constant ddrcfg_reset : std_logic_vector(31 downto 0):=
'1' & --refresh
"00" & -- CAS
"00" & -- Memcmd
"10" & -- Burst length
'0' & -- Auto Precharge
"11" & -- Read prediction
"00" & -- Write protection
x"00000";
--Memory commands (RAS, CAS, WE)
constant CMD_READ : std_logic_vector(2 downto 0) := "101";
constant CMD_WRITE : std_logic_vector(2 downto 0) := "100";
constant CMD_NOP : std_logic_vector(2 downto 0) := "111";
constant CMD_ACTIVE : std_logic_vector(2 downto 0) := "011";
constant CMD_BT : std_logic_vector(2 downto 0) := "110";
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_AR : std_logic_vector(2 downto 0) := "001";
constant CMD_LMR : std_logic_vector(2 downto 0) := "000";
constant BANK0 : std_logic_vector(1 downto 0) := "10";
constant BANK1 : std_logic_vector(1 downto 0) := "01";
constant BANK01 : std_logic_vector(1 downto 0) := "00";
type burst_mask_type is array (buffersize-1 downto 0) of integer range 1 to 8;
type two_burst_mask_type is array (1 downto 0) of burst_mask_type;
type two_buf_adr_type is array (1 downto 0) of std_logic_vector((log2(buffersize)-1) downto 0);
type two_buf_data_type is array (1 downto 0) of std_logic_vector((bufferadr-1) downto 0);
type pre_row_type is array (7 downto 0) of std_logic_vector(adrbits-1 downto 0);
type two_ddr_adr_type is array (1 downto 0) of std_logic_vector(adrbits-1 downto 0);
type two_ddr_bank_type is array (1 downto 0) of std_logic_vector(1 downto 0);
type two_pre_bank_type is array (1 downto 0) of integer range 0 to 7;
type blwaittype is array (6 downto 0) of integer range 2 to 8;
type mlwaittype is array (1 downto 0) of integer range 1 to 8;
type bufwaittype is array (6 downto 0) of std_logic_vector((log2(buffersize)-1) downto 0);
type ahbwaittype is array (6 downto 0) of integer range 0 to 1;
-------------------------------------------------------------------------------
-- Records
-------------------------------------------------------------------------------
-- APB controller
type apb_ctrl_in_type is record
apbsi : apb_slv_in_type;
apb_cmd_done : std_ulogic;
ready : std_ulogic;
end record;
type apb_ctrl_out_type is record
apbso : apb_slv_out_type;
ddrcfg_reg : std_logic_vector(31 downto 0);
end record;
-------------------------------------------------------------------------------
-- Sync ram dp (data-fifo)
type syncram_dp_in_type is record
address1 : std_logic_vector((bufferadr -1) downto 0);
datain1 : std_logic_vector(2*(maxdqsize+maxdmsize)-1 downto 0);
enable1 : std_ulogic;
write1 : std_ulogic;
address2 : std_logic_vector((bufferadr-1) downto 0);
datain2 : std_logic_vector(2*(maxdqsize+maxdmsize)-1 downto 0);
enable2 : std_ulogic;
write2 : std_ulogic;
end record;
type syncram_dp_out_type is record
dataout1 : std_logic_vector(2*(maxdqsize+maxdmsize)-1 downto 0);
dataout2 : std_logic_vector(2*(maxdqsize+maxdmsize)-1 downto 0);
end record;
type two_syncram_dp_out_type is array (1 downto 0) of syncram_dp_out_type;
type two_syncram_dp_in_type is array (1 downto 0) of syncram_dp_in_type;
-------------------------------------------------------------------------------
-- Sync ram 2p (adr-fifo)
type syncram_2p_in_type is record
renable : std_ulogic;
raddress : std_logic_vector((log2(buffersize) -1) downto 0);
write : std_ulogic;
waddress : std_logic_vector((log2(buffersize)-1) downto 0);
datain : std_logic_vector((ahbadr-1+1) downto 0);
end record;
type syncram_2p_out_type is record
dataout : std_logic_vector((ahbadr-1+1) downto 0);
end record;
-----------------------------------------------------------------------------
-- High speed interface towards memory
type hs_in_type is record
bl : integer range 2 to 8;
ml : integer range 1 to 8;
cas : std_logic_vector(1 downto 0);
buf : std_logic_vector((log2(buffersize)-1) downto 0);
ahb : integer range 0 to 1;
cs : std_logic_vector(1 downto 0);
adr : std_logic_vector(adrbits-1 downto 0);
cmd : std_logic_vector(2 downto 0);
cmd_valid : std_ulogic;
dsramso : two_syncram_dp_out_type;
ddso : ddrmem_out_type;
end record;
type hs_out_type is record
hs_busy : std_ulogic;
cmdDone : two_buf_adr_type;
dsramsi : two_syncram_dp_in_type;
ddsi : ddrmem_in_type;
end record;
-----------------------------------------------------------------------------
-- AHB controller
type ahb_ctrl_in_type is record
ahbsi : ahb_slv_in_type;
asramsi : syncram_2p_in_type;
dsramsi : syncram_dp_in_type;
burstlength : integer range 2 to 8;
r_predict : std_ulogic;
w_prot : std_ulogic;
locked : std_ulogic;
rw_cmd_done : std_logic_vector((log2(buffersize) -1) downto 0);
end record;
type ahb_ctrl_out_type is record
ahbso : ahb_slv_out_type;
asramso : syncram_2p_out_type;
dsramso : syncram_dp_out_type;
rw_cmd_valid : std_logic_vector((log2(buffersize) -1) downto 0);
w_data_valid : std_logic_vector((log2(buffersize) -1) downto 0);
burst_dm : burst_mask_type;
end record;
type two_ahb_ctrl_out_type is array (1 downto 0) of ahb_ctrl_out_type;
type two_ahb_ctrl_in_type is array (1 downto 0) of ahb_ctrl_in_type;
-----------------------------------------------------------------------------
-- Main controller
type main_ctrl_in_type is record
apbctrlso : apb_ctrl_out_type;
ahbctrlso : two_ahb_ctrl_out_type;
hsso : hs_out_type;
end record;
type main_ctrl_out_type is record
apbctrlsi : apb_ctrl_in_type;
ahbctrlsi : two_ahb_ctrl_in_type;
hssi : hs_in_type;
end record;
-------------------------------------------------------------------------------
-- DDRCFG register
type config_out_type is record
refresh : std_ulogic;
cas : std_logic_vector(1 downto 0);
memcmd : std_logic_vector(1 downto 0);
bl : std_logic_vector(1 downto 0);
autopre : std_ulogic;
r_predict : std_logic_vector(1 downto 0);
w_prot : std_logic_vector(1 downto 0);
ready : std_ulogic;
end record;
-------------------------------------------------------------------------------
-- State machines
-------------------------------------------------------------------------------
type apbcycletype is (idle, refresh, cmd, wait_lmr1, wait_lmr2, cmdlmr, cmdDone, cmdDone2);
type timercycletype is (t1, t2, t3, t4);
type initcycletype is (idle, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11);
type maincycletype is (init, idle, pre1, act1, w1, r1, rw, c1, c2);
type rwcycletype is (idle, r, w);
type cmdbuffercycletype is (no_cmd, new_cmd);
type cmdcycletype is(idle, hold);
-----------------------------------------------------------------------------
-- AHB - Local variables
type ahb_reg_type is record
readcounter : integer range 0 to 8;
writecounter : integer range 0 to 8;
blockburstlength : integer range 0 to 8;
hready : std_ulogic;
hresp : std_logic_vector(1 downto 0);
rwadrbuffer : std_logic_vector((ahbadr-1) downto 0);
use_read_buffer : std_logic_vector((log2(buffersize)-1) downto 0);
pre_read_buffer : std_logic_vector((log2(buffersize)-1) downto 0);
pre_read_adr : std_logic_vector((ahbadr-1) downto 0);
pre_read_valid : std_ulogic;
use_write_buffer : std_logic_vector((log2(buffersize)-1) downto 0);
rw_cmd_valid : std_logic_vector((log2(buffersize)-1) downto 0);
w_data_valid : std_logic_vector((log2(buffersize)-1) downto 0);
sync_adr : std_logic_vector((bufferadr-1) downto 0);
sync_wdata : std_logic_vector(2*(maxdqsize+maxdmsize)-1 downto 0);
sync_write : std_ulogic;
sync_busy : std_ulogic;
sync_busy_adr : std_logic_vector((bufferadr-1) downto 0);
sync2_adr : std_logic_vector((log2(buffersize)-1) downto 0);
sync2_wdata : std_logic_vector((ahbadr-1+1) downto 0);
sync2_write : std_ulogic;
sync2_busy : std_ulogic;
doRead : std_ulogic;
doWrite : std_ulogic;
new_burst : std_ulogic;
startp : integer range 0 to 7;
ahbstartp : integer range 0 to 7;
even_odd_write : integer range 0 to 1;
burst_hsize : integer range 1 to 8;
offset : std_logic_vector(2 downto 0);
ahboffset : std_logic_vector(2 downto 0);
read_data : std_logic_vector(maxdqsize-1 downto 0);
cur_hrdata : std_logic_vector((ahbdata-1) downto 0);
cur_hready : std_ulogic;
cur_hresp : std_logic_vector(1 downto 0);
prev_retry : std_ulogic;
prev_error : std_ulogic;
burst_dm : burst_mask_type;
end record;
-------------------------------------------------------------------------------
-- APB controller - Local variables
type apb_reg_type is record
ddrcfg_reg : std_logic_vector(31 downto 0);
end record;
-------------------------------------------------------------------------------
-- High speed RW - Local variables
type rw_reg_type is record
cbufstate : cmdbuffercycletype;
cmdstate : cmdcycletype;
rwstate : rwcycletype;
cur_buf : two_buf_adr_type;
cur_ahb : integer range 0 to 1;
use_bl : integer range 2 to 8;
use_ml : integer range 1 to 8;
use_buf : std_logic_vector((log2(buffersize)-1) downto 0);
use_ahb : integer range 0 to 1;
use_cas : std_ulogic;
rw_cmd : std_logic_vector(2 downto 0);
rw_bl : integer range 2 to 8;
rw_cas : integer range 2 to 3;
next_bl : integer range 2 to 8;
next_ml : integer range 1 to 8;
next_buf : std_logic_vector((log2(buffersize)-1) downto 0);
next_ahb : integer range 0 to 1;
next_cas : std_logic_vector(1 downto 0);
next_adr : std_logic_vector(adrbits-1 downto 0);
next_cs : std_logic_vector(1 downto 0);
next_cmd : std_logic_vector(2 downto 0);
set_cmd : std_logic_vector(2 downto 0);
set_adr : std_logic_vector(adrbits-1 downto 0);
set_cs : std_logic_vector(1 downto 0);
set_cke : std_ulogic;
hs_busy : std_ulogic;
cmdDone : two_buf_adr_type;
begin_read : std_ulogic;
begin_write : std_ulogic;
dq_dqs_oe : std_ulogic;
w_ce : std_ulogic;
r_ce : std_ulogic;
cnt : integer range 0 to 8;
holdcnt : integer range 0 to 31;
r2wholdcnt : integer range 0 to 15;
act2precnt : integer range 0 to 15;
wait_time : integer range 0 to 31;
readwait : std_logic_vector(6 downto 0);
writewait : std_logic_vector(1 downto 0);
bufwait : bufwaittype;
ahbwait : ahbwaittype;
blwait : blwaittype;
mlwait : mlwaittype;
caswait : std_logic_vector(6 downto 0);
dm1_o : std_logic_vector((maxdmsize-1) downto 0);
dm2_o : std_logic_vector((maxdmsize-1) downto 0);
dqs1_o : std_ulogic;
sync_adr : two_buf_data_type;
sync_write : std_logic_vector(1 downto 0);
sync_wdata : std_logic_vector(2*(maxdqsize+maxdmsize)-1 downto 0);
end record;
-------------------------------------------------------------------------------
-- High speed CMD - Local variables
type cmd_reg_type is record
cur_cmd : std_logic_vector(2 downto 0);
cur_cs : std_logic_vector(1 downto 0);
cur_adr : std_logic_vector(adrbits-1 downto 0);
next_cmd : std_logic_vector(2 downto 0);
next_cs : std_logic_vector(1 downto 0);
next_adr : std_logic_vector(adrbits-1 downto 0);
end record;
-------------------------------------------------------------------------------
-- Main controller - Local variables
type main_reg_type is record
-- For main controller
mainstate : maincycletype;
loadcmdbuffer : std_ulogic;
cmdbufferdata : std_logic_vector(2 downto 0);
adrbufferdata : std_logic_vector(adrbits-1 downto 0);
use_ahb : integer range 0 to 1;
use_bl : integer range 2 to 8;
use_cas : std_logic_vector(1 downto 0);
use_buf : std_logic_vector((log2(buffersize)-1) downto 0);
burstlength : integer range 2 to 8;
rw_cmd_done : two_buf_adr_type;
lmradr : std_logic_vector(adrbits-1 downto 0);
memCmdDone : std_ulogic;
lockAHB : std_logic_vector(1 downto 0);
pre_row : pre_row_type;
pre_chg : std_logic_vector(7 downto 0);
pre_bankadr : two_pre_bank_type;
sync2_adr : two_buf_adr_type;
-- For init statemachine
initstate : initcycletype;
doMemInit : std_ulogic;
memInitDone : std_ulogic;
initDelay : integer range 0 to 255;
cs : std_logic_vector(1 downto 0);
-- For address calculator
coladdress : two_ddr_adr_type;
tmpcoladdress : two_ddr_adr_type;
rowaddress : two_ddr_adr_type;
addressrange : integer range 0 to 31;
tmpcolbits : integer range 0 to 15;
colbits : integer range 0 to 15;
rowbits : integer range 0 to 15;
bankselect : two_ddr_bank_type;
intbankbits : two_ddr_bank_type;
-- For refresh timer statemachine
timerstate : timercycletype;
doRefresh : std_ulogic;
refreshDone : std_ulogic;
refreshTime : integer range 0 to 4095;
maxRefreshTime : integer range 0 to 32767;
idlecnt : integer range 0 to 10;
refreshcnt : integer range 0 to 65535;
-- For DDRCFG register (APB)
apbstate : apbcycletype;
apb_cmd_done : std_ulogic;
ready : std_ulogic;
ddrcfg : config_out_type;
end record;
-------------------------------------------------------------------------------
-- Components
-------------------------------------------------------------------------------
component ahb_slv
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f80#;
sepclk : integer := 0;
dqsize : integer := 64;
dmsize : integer := 8;
tech : integer := virtex2);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
clk0 : in std_ulogic;
csi : in ahb_ctrl_in_type;
cso : out ahb_ctrl_out_type);
end component;
component ddr_in
generic (
tech : integer);
port (
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
-- DQS : in std_logic; -- used for lattice
-- DDRCLKPOL: in std_logic; -- used for lattice
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component ddr_out
generic (
tech : integer);
port (
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component hs
generic(
tech : in integer;
dqsize : in integer;
dmsize : in integer;
strobesize: in integer;
clkperiod : in integer);
port (
rst : in std_ulogic;
clk0 : in std_ulogic;
clk90 : in std_ulogic;
clk180 : in std_ulogic;
clk270 : in std_ulogic;
hclk : in std_ulogic;
hssi : in hs_in_type;
hsso : out hs_out_type);
end component;
end ddrrec;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY example_ap_fadd_3_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END example_ap_fadd_3_full_dsp_32;
ARCHITECTURE example_ap_fadd_3_full_dsp_32_arch OF example_ap_fadd_3_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF example_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF example_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF example_ap_fadd_3_full_dsp_32_arch : ARCHITECTURE IS "example_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF example_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "example_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END example_ap_fadd_3_full_dsp_32_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--------------------------------------
entity reg_mux_tb is
generic (tp: time := 10 ns);
end entity reg_mux_tb;
--------------------------------------
architecture circuit of reg_mux_tb is
-- DUT declaration
component reg_mux is
port( a, b, c, d: in std_logic_vector(3 downto 0);
sel: in std_logic_vector(1 downto 0) ;
clk: in std_logic;
x, y: out std_logic_vector(3 downto 0));
end component reg_mux;
-- signals declarations
signal a_tb: std_logic_vector(3 downto 0) := "0010";
signal b_tb: std_logic_vector(3 downto 0) := "0100";
signal c_tb: std_logic_vector(3 downto 0) := "0110";
signal d_tb: std_logic_vector(3 downto 0) := "1000";
signal sel_tb: std_logic_vector(1 downto 0) := "00";
signal clk_tb: std_logic := '0';
signal x_tb: std_logic_vector(3 downto 0);
signal y_tb: std_logic_vector(3 downto 0);
signal expected: std_logic_vector(3 downto 0) := "0000";
begin
-- dut instantiation
dut: reg_mux port map (
a => a_tb,
b => b_tb,
c => c_tb,
d => d_tb,
sel => sel_tb,
clk => clk_tb,
x => x_tb,
y => y_tb
);
-- stimuli generation
clk_tb <= not clk_tb after 40 ns;
a_tb <= "0011" after 80 ns, "0000" after 640 ns;
b_tb <= "0101" after 240 ns;
c_tb <= "0111" after 400 ns;
d_tb <= "1001" after 560 ns;
sel_tb <= "01" after 160 ns,
"10" after 320 ns,
"11" after 480 ns,
"00" after 640 ns;
-- output verification
-- (i) generate template
expected <= "0010" after 40 ns + tp,
"0011" after 120 ns + tp,
"0100" after 200 ns + tp,
"0101" after 280 ns + tp,
"0110" after 360 ns + tp,
"0111" after 440 ns + tp,
"1000" after 520 ns + tp,
"1001" after 600 ns + tp,
"0000" after 680 ns + tp;
--(ii) make comparison:
process
begin
wait for 40 ns + tp; -- before 40ns (first rising edge) y_tb is X because it isn't assigned a proper value that's why I needed to modify the example code and add 40 ns
if (now < 800 ns) then
assert (y_tb = expected)
report "Mismatch at t=" & time'image(now) & " y_tb=" & integer'image(conv_integer(y_tb)) & " y_exp=" & integer'image(conv_integer(expected))
severity failure;
else
assert false
report "No error found (t=" & time'image(now) & ")"
severity note;
end if;
end process;
end architecture circuit;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.16:15:41)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesafp_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21: IN unsigned(0 TO 3);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 4));
END mesafp_random_entity;
ARCHITECTURE mesafp_random_description OF mesafp_random_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register12: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register13: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register14: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register15: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register16: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register17: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
register3 := input3 * 3;
WHEN "00000010" =>
register2 := register2 + 5;
register4 := input4 * 6;
register5 := input5 * 7;
WHEN "00000011" =>
register4 := register4 + 9;
register6 := input6 * 10;
register7 := input7 + 11;
register8 := input8 * 12;
register9 := input9 * 13;
register10 := input10 + 14;
register11 := input11 + 15;
register12 := input12 * 16;
WHEN "00000100" =>
register8 := register8 + 18;
register13 := input13 * 19;
register11 := register12 + register11;
register12 := input14 + 20;
register14 := input15 + 21;
register15 := input16 + 22;
register16 := input17 * 23;
WHEN "00000101" =>
register12 := register12 + 25;
register17 := input18 * 26;
register10 := register13 + register10;
WHEN "00000110" =>
register13 := register17 + register15;
register15 := input19 * 27;
register5 := register5 + 29;
register17 := input20 * 30;
register6 := register6 + register10;
register10 := input21 * 31;
register9 := register9 + register14;
register11 := register16 + register11;
WHEN "00000111" =>
register11 := ((NOT register11) + 1) XOR register11;
WHEN "00001000" =>
output1 <= register11(0 TO 1) & register8(0 TO 2);
register7 := register10 + register7;
register8 := register15 + register13;
WHEN "00001001" =>
register7 := register17 + register7;
register6 := ((NOT register6) + 1) XOR register6;
register3 := register3 + register9;
WHEN "00001010" =>
register7 := ((NOT register7) + 1) XOR register7;
register6 := register6 / 2;
register3 := ((NOT register3) + 1) XOR register3;
register8 := ((NOT register8) + 1) XOR register8;
WHEN "00001011" =>
register7 := register6 * register7;
WHEN "00001100" =>
output2 <= register7(0 TO 1) & register5(0 TO 2);
register5 := register6 * register8;
register7 := ((NOT register12) + 1) XOR register12;
WHEN "00001101" =>
output3 <= register5(0 TO 1) & register4(0 TO 2);
register3 := register6 * register3;
WHEN "00001110" =>
output4 <= register3(0 TO 1) & register2(0 TO 2);
register1 := register1 + 51;
WHEN "00001111" =>
register1 := ((NOT register1) + 1) XOR register1;
WHEN "00010000" =>
IF (register7 = 54 or register1 = 54) THEN
output5 <= register7;
ELSE
output5 <= "10110";
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesafp_random_description; |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Provides an SPI slave buffer that can be used for buffering data received or to
-- be sent. The buffer can be either controlled by the rising edge or by the level
-- of the enable signal, both synchronous to CLK).
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SPI_SlaveDataBuffer is
generic
(
-- The width of the data.
width: positive;
-- Indicates whether the buffer is triggered on a rising edge of the enable
-- signal instead of the enable signal being high.
edge_triggered: boolean
);
port
(
-- The system clock.
clk: in std_logic;
-- Controls when the buffer passes the input data to its output (behaviour
-- depends on the edge_triggered generic: either on the rising edge or when
-- '1', both synchronous to CLK).
buffer_enable: in std_logic;
-- The parallel unbuffered data.
data: in std_logic_vector(width-1 downto 0);
-- The parallel buffered data.
buffered_data: out std_logic_vector(width-1 downto 0) := (others => '0');
-- Indicates whether the buffered data are stable.
ready: out std_logic := '0'
);
end entity;
architecture stdarch of SPI_SlaveDataBuffer is
type reg_type is record
buffer_enable: std_logic;
data: std_logic_vector(width-1 downto 0);
end record;
signal state, next_state: reg_type :=
(
buffer_enable => '0',
data => (others => '0')
);
begin
--------------------------------------------------------------------------------
-- State register.
--------------------------------------------------------------------------------
state_register: process is
begin
wait until rising_edge(clk);
state <= next_state;
end process;
--------------------------------------------------------------------------------
-- Next state logic.
--------------------------------------------------------------------------------
next_state_logic: process(state, buffer_enable, data) is
begin
-- Defaults.
next_state <= state;
next_state.buffer_enable <= buffer_enable;
-- Buffer the input data either on a rising buffer_enable edge or when
-- buffer_enable is '1'.
if ((edge_triggered and state.buffer_enable = '0' and buffer_enable = '1') or
((not edge_triggered) and buffer_enable = '1')) then
next_state.data <= data;
end if;
end process;
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
buffered_data <= state.data;
ready <= state.buffer_enable;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2527.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p06n04i02527ent IS
END c07s03b05x00p06n04i02527ent;
ARCHITECTURE c07s03b05x00p06n04i02527arch OF c07s03b05x00p06n04i02527ent IS
BEGIN
TESTING: PROCESS
variable V1 : Integer;
BEGIN
V1 := Integer (10.2);
assert NOT( V1 = 10 )
report "***PASSED TEST: c07s03b05x00p06n04i02527"
severity NOTE;
assert ( V1 = 10 )
report "***FAILED TEST: c07s03b05x00p06n04i02527 - The conversion of a floating point value to an integer type rounds to the nearest integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p06n04i02527arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2527.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p06n04i02527ent IS
END c07s03b05x00p06n04i02527ent;
ARCHITECTURE c07s03b05x00p06n04i02527arch OF c07s03b05x00p06n04i02527ent IS
BEGIN
TESTING: PROCESS
variable V1 : Integer;
BEGIN
V1 := Integer (10.2);
assert NOT( V1 = 10 )
report "***PASSED TEST: c07s03b05x00p06n04i02527"
severity NOTE;
assert ( V1 = 10 )
report "***FAILED TEST: c07s03b05x00p06n04i02527 - The conversion of a floating point value to an integer type rounds to the nearest integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p06n04i02527arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2527.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p06n04i02527ent IS
END c07s03b05x00p06n04i02527ent;
ARCHITECTURE c07s03b05x00p06n04i02527arch OF c07s03b05x00p06n04i02527ent IS
BEGIN
TESTING: PROCESS
variable V1 : Integer;
BEGIN
V1 := Integer (10.2);
assert NOT( V1 = 10 )
report "***PASSED TEST: c07s03b05x00p06n04i02527"
severity NOTE;
assert ( V1 = 10 )
report "***FAILED TEST: c07s03b05x00p06n04i02527 - The conversion of a floating point value to an integer type rounds to the nearest integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p06n04i02527arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
entity proc_core is
generic (
vector_page : std_logic_vector(15 downto 4) := X"FFF";
support_bcd : boolean := true );
port(
clock : in std_logic;
clock_en : in std_logic;
reset : in std_logic;
irq_n : in std_logic := '1';
nmi_n : in std_logic := '1';
so_n : in std_logic := '1';
sync_out : out std_logic;
pc_out : out std_logic_vector(15 downto 0);
addr_out : out std_logic_vector(16 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
read_write_n : out std_logic );
end proc_core;
architecture structural of proc_core is
signal index_carry : std_logic;
signal pc_carry : std_logic;
signal branch_taken : boolean;
signal i_reg : std_logic_vector(7 downto 0);
signal d_reg : std_logic_vector(7 downto 0);
signal a_reg : std_logic_vector(7 downto 0);
signal x_reg : std_logic_vector(7 downto 0);
signal y_reg : std_logic_vector(7 downto 0);
signal s_reg : std_logic_vector(7 downto 0);
signal p_reg : std_logic_vector(7 downto 0);
signal latch_dreg : std_logic;
signal reg_update : std_logic;
signal copy_d2p : std_logic;
signal sync : std_logic;
signal rwn : std_logic;
signal vect_bit : std_logic;
signal a_mux : t_amux;
signal pc_oper : t_pc_oper;
signal s_oper : t_sp_oper;
signal adl_oper : t_adl_oper;
signal adh_oper : t_adh_oper;
signal dout_mux : t_dout_mux;
signal alu_out : std_logic_vector(7 downto 0);
signal mem_out : std_logic_vector(7 downto 0);
signal impl_out : std_logic_vector(7 downto 0);
signal set_a : std_logic;
signal set_x : std_logic;
signal set_y : std_logic;
signal set_s : std_logic;
signal vect_addr : std_logic_vector(3 downto 0);
signal interrupt : std_logic;
signal new_flags : std_logic_vector(7 downto 0);
signal n_out : std_logic;
signal v_out : std_logic;
signal c_out : std_logic;
signal z_out : std_logic;
signal d_out : std_logic;
signal i_out : std_logic;
signal set_b : std_logic;
signal clear_b : std_logic;
signal a16 : std_logic;
begin
new_flags(7) <= n_out;
new_flags(6) <= v_out;
new_flags(5) <= '1';
new_flags(4) <= p_reg(4);
new_flags(3) <= d_out;
new_flags(2) <= i_out;
new_flags(1) <= z_out;
new_flags(0) <= c_out;
ctrl: entity work.proc_control
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
interrupt => interrupt,
i_reg => i_reg,
index_carry => index_carry,
pc_carry => pc_carry,
branch_taken => branch_taken,
sync => sync,
latch_dreg => latch_dreg,
reg_update => reg_update,
set_b => set_b,
copy_d2p => copy_d2p,
vect_bit => vect_bit,
a16 => a16,
rwn => rwn,
a_mux => a_mux,
dout_mux => dout_mux,
pc_oper => pc_oper,
s_oper => s_oper,
adl_oper => adl_oper,
adh_oper => adh_oper );
oper: entity work.data_oper
generic map (
support_bcd => support_bcd )
port map (
inst => i_reg,
n_in => p_reg(7),
v_in => p_reg(6),
z_in => p_reg(1),
c_in => p_reg(0),
d_in => p_reg(3),
i_in => p_reg(2),
data_in => d_reg,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
s_reg => s_reg,
alu_out => alu_out,
mem_out => mem_out,
impl_out => impl_out,
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
n_out => n_out,
v_out => v_out,
z_out => z_out,
c_out => c_out,
d_out => d_out,
i_out => i_out );
regs: entity work.proc_registers
generic map (
vector_page => vector_page )
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
-- package pins
data_in => data_in,
data_out => data_out,
so_n => so_n,
-- data from "data_oper"
alu_data => alu_out,
mem_data => mem_out,
new_flags => new_flags,
-- from implied handler
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
set_data => impl_out,
-- from interrupt controller
vect_addr => vect_addr,
interrupt => interrupt,
set_b => set_b,
clear_b => clear_b,
-- from processor state machine and decoder
sync => sync,
latch_dreg => latch_dreg,
vect_bit => vect_bit,
reg_update => reg_update,
copy_d2p => copy_d2p,
a_mux => a_mux,
dout_mux => dout_mux,
pc_oper => pc_oper,
s_oper => s_oper,
adl_oper => adl_oper,
adh_oper => adh_oper,
-- outputs to processor state machine
i_reg => i_reg,
index_carry => index_carry,
pc_carry => pc_carry,
branch_taken => branch_taken,
-- register outputs
addr_out => addr_out(15 downto 0),
d_reg => d_reg,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
s_reg => s_reg,
p_reg => p_reg,
pc_out => pc_out );
intr: entity work.proc_interrupt
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
irq_n => irq_n,
nmi_n => nmi_n,
i_flag => p_reg(2),
clear_b => clear_b,
vect_bit => vect_bit,
interrupt => interrupt,
vect_addr => vect_addr );
read_write_n <= rwn;
addr_out(16) <= a16;
sync_out <= sync;
end structural;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
entity proc_core is
generic (
vector_page : std_logic_vector(15 downto 4) := X"FFF";
support_bcd : boolean := true );
port(
clock : in std_logic;
clock_en : in std_logic;
reset : in std_logic;
irq_n : in std_logic := '1';
nmi_n : in std_logic := '1';
so_n : in std_logic := '1';
sync_out : out std_logic;
pc_out : out std_logic_vector(15 downto 0);
addr_out : out std_logic_vector(16 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
read_write_n : out std_logic );
end proc_core;
architecture structural of proc_core is
signal index_carry : std_logic;
signal pc_carry : std_logic;
signal branch_taken : boolean;
signal i_reg : std_logic_vector(7 downto 0);
signal d_reg : std_logic_vector(7 downto 0);
signal a_reg : std_logic_vector(7 downto 0);
signal x_reg : std_logic_vector(7 downto 0);
signal y_reg : std_logic_vector(7 downto 0);
signal s_reg : std_logic_vector(7 downto 0);
signal p_reg : std_logic_vector(7 downto 0);
signal latch_dreg : std_logic;
signal reg_update : std_logic;
signal copy_d2p : std_logic;
signal sync : std_logic;
signal rwn : std_logic;
signal vect_bit : std_logic;
signal a_mux : t_amux;
signal pc_oper : t_pc_oper;
signal s_oper : t_sp_oper;
signal adl_oper : t_adl_oper;
signal adh_oper : t_adh_oper;
signal dout_mux : t_dout_mux;
signal alu_out : std_logic_vector(7 downto 0);
signal mem_out : std_logic_vector(7 downto 0);
signal impl_out : std_logic_vector(7 downto 0);
signal set_a : std_logic;
signal set_x : std_logic;
signal set_y : std_logic;
signal set_s : std_logic;
signal vect_addr : std_logic_vector(3 downto 0);
signal interrupt : std_logic;
signal new_flags : std_logic_vector(7 downto 0);
signal n_out : std_logic;
signal v_out : std_logic;
signal c_out : std_logic;
signal z_out : std_logic;
signal d_out : std_logic;
signal i_out : std_logic;
signal set_b : std_logic;
signal clear_b : std_logic;
signal a16 : std_logic;
begin
new_flags(7) <= n_out;
new_flags(6) <= v_out;
new_flags(5) <= '1';
new_flags(4) <= p_reg(4);
new_flags(3) <= d_out;
new_flags(2) <= i_out;
new_flags(1) <= z_out;
new_flags(0) <= c_out;
ctrl: entity work.proc_control
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
interrupt => interrupt,
i_reg => i_reg,
index_carry => index_carry,
pc_carry => pc_carry,
branch_taken => branch_taken,
sync => sync,
latch_dreg => latch_dreg,
reg_update => reg_update,
set_b => set_b,
copy_d2p => copy_d2p,
vect_bit => vect_bit,
a16 => a16,
rwn => rwn,
a_mux => a_mux,
dout_mux => dout_mux,
pc_oper => pc_oper,
s_oper => s_oper,
adl_oper => adl_oper,
adh_oper => adh_oper );
oper: entity work.data_oper
generic map (
support_bcd => support_bcd )
port map (
inst => i_reg,
n_in => p_reg(7),
v_in => p_reg(6),
z_in => p_reg(1),
c_in => p_reg(0),
d_in => p_reg(3),
i_in => p_reg(2),
data_in => d_reg,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
s_reg => s_reg,
alu_out => alu_out,
mem_out => mem_out,
impl_out => impl_out,
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
n_out => n_out,
v_out => v_out,
z_out => z_out,
c_out => c_out,
d_out => d_out,
i_out => i_out );
regs: entity work.proc_registers
generic map (
vector_page => vector_page )
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
-- package pins
data_in => data_in,
data_out => data_out,
so_n => so_n,
-- data from "data_oper"
alu_data => alu_out,
mem_data => mem_out,
new_flags => new_flags,
-- from implied handler
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
set_data => impl_out,
-- from interrupt controller
vect_addr => vect_addr,
interrupt => interrupt,
set_b => set_b,
clear_b => clear_b,
-- from processor state machine and decoder
sync => sync,
latch_dreg => latch_dreg,
vect_bit => vect_bit,
reg_update => reg_update,
copy_d2p => copy_d2p,
a_mux => a_mux,
dout_mux => dout_mux,
pc_oper => pc_oper,
s_oper => s_oper,
adl_oper => adl_oper,
adh_oper => adh_oper,
-- outputs to processor state machine
i_reg => i_reg,
index_carry => index_carry,
pc_carry => pc_carry,
branch_taken => branch_taken,
-- register outputs
addr_out => addr_out(15 downto 0),
d_reg => d_reg,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
s_reg => s_reg,
p_reg => p_reg,
pc_out => pc_out );
intr: entity work.proc_interrupt
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
irq_n => irq_n,
nmi_n => nmi_n,
i_flag => p_reg(2),
clear_b => clear_b,
vect_bit => vect_bit,
interrupt => interrupt,
vect_addr => vect_addr );
read_write_n <= rwn;
addr_out(16) <= a16;
sync_out <= sync;
end structural;
|
-- EMACS settings: -*- tab-width:2 -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-------------------------------------------------------------------------------
-- Description: Hardware Testbench for remote_terminal_control.
-- See DUT description for details.
-- Authors: Thomas B. Preußer <[email protected]>
-------------------------------------------------------------------------------
-- Copyright 2007-2014 Technische Universität Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity remote_terminal_control_top is
generic (
CLK_FREQ : positive := 50000000; -- 50 MHz
BAUD : positive := 115200
);
port (
clk : in std_logic;
rxd : in std_logic;
txd : out std_logic;
sw : in std_logic_vector(7 downto 0);
led : out std_logic_vector(7 downto 0)
);
end remote_terminal_control_top;
library IEEE;
use IEEE.numeric_std.all;
library poc;
use poc.functions.all;
use poc.uart.all;
architecture rtl of remote_terminal_control_top is
-- Control
component remote_terminal_control is
generic (
RESET_COUNT : natural;
PULSE_COUNT : natural;
SWITCH_COUNT : natural;
LIGHT_COUNT : natural;
DIGIT_COUNT : natural
);
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
-- UART Connectivity
idat : in std_logic_vector(6 downto 0);
istb : in std_logic;
odat : out std_logic_vector(6 downto 0);
ordy : in std_logic;
oput : out std_logic;
-- Control Outputs
resets : out std_logic_vector(imax(RESET_COUNT -1, 0) downto 0);
pulses : out std_logic_vector(imax(PULSE_COUNT -1, 0) downto 0);
switches : out std_logic_vector(imax(SWITCH_COUNT-1, 0) downto 0);
-- Monitor Inputs
lights : in std_logic_vector(imax( LIGHT_COUNT-1, 0) downto 0);
digits : in std_logic_vector(imax(4*DIGIT_COUNT-1, 0) downto 0)
);
end component;
signal rst : std_logic;
signal idat : std_logic_vector(7 downto 0);
signal istb : std_logic;
signal odat : std_logic_vector(7 downto 0);
signal oput : std_logic;
signal ordy : std_logic;
begin -- rtl
rst <= '0';
blkUART: block
signal bclk : std_logic;
signal bclk_x8 : std_logic;
begin
rx: uart_rx
generic map (
OUT_REGS => true
)
port map (
clk => clk,
rst => rst,
bclk_x8_r => bclk_x8,
rxd => rxd,
dos => istb,
dout => idat
);
tx: uart_tx
port map (
clk => clk,
rst => rst,
bclk_r => bclk,
stb => oput,
din => odat,
rdy => ordy,
txd => txd
);
bclk_gen: uart_bclk
generic map (
CLK_FREQ => CLK_FREQ,
BAUD => BAUD
)
port map (
clk => clk,
rst => rst,
bclk_r => bclk,
bclk_x8_r => bclk_x8
);
end block blkUART;
term_ctrl: remote_terminal_control
generic map (
RESET_COUNT => 0,
PULSE_COUNT => 0,
SWITCH_COUNT => 8,
LIGHT_COUNT => 8,
DIGIT_COUNT => 2
)
port map (
clk => clk,
rst => rst,
idat => idat(6 downto 0),
istb => istb,
odat => odat(6 downto 0),
ordy => ordy,
oput => oput,
resets => open,
pulses => open,
switches => led,
lights => sw,
digits => sw
);
odat(7) <= '0';
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.usb_pkg.all;
entity nano_minimal_io is
generic (
g_support_suspend : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
-- i/o interface
io_addr : in unsigned(7 downto 0);
io_write : in std_logic;
io_read : in std_logic;
io_wdata : in std_logic_vector(15 downto 0);
io_rdata : out std_logic_vector(15 downto 0);
stall : out std_logic;
-- Register access
reg_read : out std_logic := '0';
reg_write : out std_logic := '0';
reg_ack : in std_logic;
reg_address : out std_logic_vector(5 downto 0) := (others => '0');
reg_wdata : out std_logic_vector(7 downto 0) := X"00";
reg_rdata : in std_logic_vector(7 downto 0);
status : in std_logic_vector(7 downto 0);
-- Low level
do_chirp : out std_logic;
chirp_data : out std_logic;
-- Functional Level
cmd_response : in std_logic_vector(15 downto 0) := X"0BAD";
frame_count : in unsigned(15 downto 0) := (others => '0');
mem_ctrl_ready : in std_logic := '0';
connected : out std_logic; -- '1' when a USB device is connected
operational : out std_logic; -- '1' when a USB device is successfully reset
suspended : out std_logic; -- '1' when the USB bus is in the suspended state
sof_enable : out std_logic; -- '1' when SOFs shall be generated
sof_tick : in std_logic := '0';
interrupt_out : out std_logic := '0';
speed : out std_logic_vector(1 downto 0) ); -- speed indicator of current link
end entity;
architecture gideon of nano_minimal_io is
signal stall_i : std_logic := '0';
signal ulpi_access : std_logic;
signal filter_cnt : unsigned(7 downto 0);
signal filter_st1 : std_logic;
signal filter_cnt2 : unsigned(8 downto 0);
signal bus_low : std_logic := '0';
signal speed_i : std_logic_vector(1 downto 0);
signal reset_filter_st1 : std_logic;
signal disconn : std_logic;
signal disconn_latched : std_logic;
signal sof_tick_latch : std_logic;
begin
disconn <= '1' when (status(5 downto 4) = "10") or (bus_low = '1' and speed_i(1)='0') else '0';
speed <= speed_i;
process(clock)
variable adlo : unsigned(3 downto 0);
variable adhi : unsigned(7 downto 4);
begin
if rising_edge(clock) then
adlo := io_addr(3 downto 0);
adhi := io_addr(7 downto 4);
-- filter for chirp detection
if reset_filter_st1 = '1' then
filter_cnt <= (others => '0');
filter_st1 <= '0';
elsif status(1) = '0' then
filter_cnt <= (others => '0');
else -- status(1) = '1'
filter_cnt <= filter_cnt + 1;
if filter_cnt = 255 then
filter_st1 <= '1';
end if;
end if;
-- filter for disconnect detection
if status(1 downto 0) = "00" then
filter_cnt2 <= filter_cnt2 + 1;
if filter_cnt2 = 511 then
bus_low <= '1';
end if;
else
filter_cnt2 <= (others => '0');
bus_low <= '0';
end if;
-- register access defaults
if reg_ack='1' then
reg_write <= '0';
reg_read <= '0';
stall_i <= '0';
end if;
interrupt_out <= '0';
reset_filter_st1 <= '0';
if io_write='1' then
reg_address <= std_logic_vector(io_addr(5 downto 0));
case adhi is
-- set registers
when X"2" =>
case adlo is
when X"0" =>
do_chirp <= '1';
when X"1" =>
chirp_data <= '1';
when X"2" =>
connected <= '1';
when X"3" =>
operational <= '1';
when X"4" =>
suspended <= '1';
when X"6" =>
speed_i <= io_wdata(1 downto 0);
when X"7" =>
sof_enable <= '1';
when X"8" =>
interrupt_out <= '1';
when X"9" =>
reset_filter_st1 <= '1';
when others =>
null;
end case;
-- clear registers
when X"3" =>
case adlo is
when X"0" =>
do_chirp <= '0';
when X"1" =>
chirp_data <= '0';
when X"2" =>
connected <= '0';
when X"3" =>
operational <= '0';
when X"4" =>
suspended <= '0';
when X"7" =>
sof_enable <= '0';
when X"E" =>
disconn_latched <= '0';
when X"C" =>
sof_tick_latch <= '0';
when others =>
null;
end case;
when X"C"|X"D"|X"E"|X"F" =>
reg_wdata <= io_wdata(7 downto 0);
reg_write <= '1';
stall_i <= '1';
when others =>
null;
end case;
end if;
if sof_tick = '1' then
sof_tick_latch <= '1';
end if;
if io_read = '1' then
reg_address <= std_logic_vector(io_addr(5 downto 0));
if io_addr(7 downto 6) = "10" then
reg_read <= '1';
stall_i <= '1';
end if;
end if;
if disconn='1' then
disconn_latched <= '1';
end if;
if reset='1' then
do_chirp <= '0';
chirp_data <= '0';
connected <= '0';
operational <= '0';
suspended <= '0';
sof_enable <= '0';
disconn_latched <= '0';
filter_st1 <= '0';
reg_read <= '0';
reg_write <= '0';
stall_i <= '0';
speed_i <= "01";
end if;
end if;
end process;
ulpi_access <= io_addr(7);
stall <= stall_i and not reg_ack; -- stall right away, and continue right away also when the data is returned
-- process( reg_rdata, io_addr, status, disconn_latched, filter_st1, mem_ctrl_ready, frame_count, sof_tick_latch)
process(clock)
variable adlo : unsigned(3 downto 0);
variable adhi : unsigned(7 downto 4);
begin
if rising_edge(clock) then
io_rdata <= (others => '0');
adlo := io_addr(3 downto 0);
adhi := io_addr(7 downto 4);
case adhi is
when X"3" =>
case adlo is
when X"9" =>
io_rdata(15) <= filter_st1;
when X"B" =>
io_rdata <= std_logic_vector(frame_count);
when X"C" =>
io_rdata(15) <= sof_tick_latch;
when X"D" =>
io_rdata(15) <= mem_ctrl_ready;
when X"E" =>
io_rdata(15) <= disconn_latched;
when X"F" =>
io_rdata(7 downto 0) <= status;
when others =>
null;
end case;
when X"6" =>
case adlo is
when X"4" =>
io_rdata <= cmd_response;
when others =>
null;
end case;
when X"8"|X"9"|X"A"|X"B" =>
io_rdata <= X"00" & reg_rdata;
when others =>
null;
end case;
end if;
end process;
end architecture;
|
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`protect end_protected
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 29 22:11:05 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_xlconstant_0_1/system_xlconstant_0_1_sim_netlist.vhdl
-- Design : system_xlconstant_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xlconstant_0_1 is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_xlconstant_0_1 : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_xlconstant_0_1 : entity is "yes";
end system_xlconstant_0_1;
architecture STRUCTURE of system_xlconstant_0_1 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
dout(31) <= \<const0>\;
dout(30) <= \<const0>\;
dout(29) <= \<const0>\;
dout(28) <= \<const0>\;
dout(27) <= \<const0>\;
dout(26) <= \<const0>\;
dout(25) <= \<const0>\;
dout(24) <= \<const0>\;
dout(23) <= \<const0>\;
dout(22) <= \<const0>\;
dout(21) <= \<const0>\;
dout(20) <= \<const0>\;
dout(19) <= \<const0>\;
dout(18) <= \<const0>\;
dout(17) <= \<const0>\;
dout(16) <= \<const0>\;
dout(15) <= \<const0>\;
dout(14) <= \<const0>\;
dout(13) <= \<const1>\;
dout(12) <= \<const0>\;
dout(11) <= \<const0>\;
dout(10) <= \<const1>\;
dout(9) <= \<const1>\;
dout(8) <= \<const1>\;
dout(7) <= \<const0>\;
dout(6) <= \<const0>\;
dout(5) <= \<const0>\;
dout(4) <= \<const1>\;
dout(3) <= \<const0>\;
dout(2) <= \<const0>\;
dout(1) <= \<const0>\;
dout(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.uart_pif_pkg.all;
entity uart_pif is
port(
arst : in std_logic;
clk : in std_logic;
-- CPU interface
cs : in std_logic;
addr : in unsigned;
wr : in std_logic;
rd : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0) := (others => '0');
--
p2c : out t_p2c;
c2p : in t_c2p
);
end uart_pif;
architecture rtl of uart_pif is
signal p2c_i : t_p2c; -- internal version of output
signal rdata_i : std_logic_vector(7 downto 0) := (others => '0');
begin
-- Assigning internally used signals to outputs
p2c <= p2c_i;
--
-- Auxiliary Register Control.
--
-- Provides read/write/trigger strobes and write data to auxiliary
-- registers and fields, i.e., registers and fields implemented in core.
--
p_aux : process (wdata, addr, cs, wr, rd)
begin
-- Defaults
p2c_i.awo_tx_data <= (others => '0');
p2c_i.awo_tx_data_we <= '0';
p2c_i.aro_rx_data_re <= '0';
-- Write decoding
if wr = '1' and cs = '1' then
case to_integer(addr) is
when C_ADDR_TX_DATA =>
p2c_i.awo_tx_data <= wdata;
p2c_i.awo_tx_data_we <= '1';
when others =>
null;
end case;
end if;
-- Read Enable Decoding
if rd = '1' and cs = '1' then
case to_integer(addr) is
when C_ADDR_RX_DATA =>
p2c_i.aro_rx_data_re <= '1';
when others =>
null;
end case;
end if;
end process p_aux;
p_read_reg : process(cs, addr, rd, c2p, p2c_i)
begin
-- default values
rdata_i <= (others => '0');
if cs = '1' and rd = '1' then
case to_integer(addr) is
when C_ADDR_RX_DATA =>
rdata_i(7 downto 0) <= c2p.aro_rx_data;
when C_ADDR_RX_DATA_VALID =>
rdata_i(0) <= c2p.aro_rx_data_valid;
when C_ADDR_TX_READY =>
rdata_i(0) <= c2p.aro_tx_ready;
when others =>
null;
end case;
end if;
end process p_read_reg;
rdata <= rdata_i;
end rtl;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.uart_pif_pkg.all;
entity uart_pif is
port(
arst : in std_logic;
clk : in std_logic;
-- CPU interface
cs : in std_logic;
addr : in unsigned;
wr : in std_logic;
rd : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0) := (others => '0');
--
p2c : out t_p2c;
c2p : in t_c2p
);
end uart_pif;
architecture rtl of uart_pif is
signal p2c_i : t_p2c; -- internal version of output
signal rdata_i : std_logic_vector(7 downto 0) := (others => '0');
begin
-- Assigning internally used signals to outputs
p2c <= p2c_i;
--
-- Auxiliary Register Control.
--
-- Provides read/write/trigger strobes and write data to auxiliary
-- registers and fields, i.e., registers and fields implemented in core.
--
p_aux : process (wdata, addr, cs, wr, rd)
begin
-- Defaults
p2c_i.awo_tx_data <= (others => '0');
p2c_i.awo_tx_data_we <= '0';
p2c_i.aro_rx_data_re <= '0';
-- Write decoding
if wr = '1' and cs = '1' then
case to_integer(addr) is
when C_ADDR_TX_DATA =>
p2c_i.awo_tx_data <= wdata;
p2c_i.awo_tx_data_we <= '1';
when others =>
null;
end case;
end if;
-- Read Enable Decoding
if rd = '1' and cs = '1' then
case to_integer(addr) is
when C_ADDR_RX_DATA =>
p2c_i.aro_rx_data_re <= '1';
when others =>
null;
end case;
end if;
end process p_aux;
p_read_reg : process(cs, addr, rd, c2p, p2c_i)
begin
-- default values
rdata_i <= (others => '0');
if cs = '1' and rd = '1' then
case to_integer(addr) is
when C_ADDR_RX_DATA =>
rdata_i(7 downto 0) <= c2p.aro_rx_data;
when C_ADDR_RX_DATA_VALID =>
rdata_i(0) <= c2p.aro_rx_data_valid;
when C_ADDR_TX_READY =>
rdata_i(0) <= c2p.aro_tx_ready;
when others =>
null;
end case;
end if;
end process p_read_reg;
rdata <= rdata_i;
end rtl;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.uart_pif_pkg.all;
entity uart_pif is
port(
arst : in std_logic;
clk : in std_logic;
-- CPU interface
cs : in std_logic;
addr : in unsigned;
wr : in std_logic;
rd : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0) := (others => '0');
--
p2c : out t_p2c;
c2p : in t_c2p
);
end uart_pif;
architecture rtl of uart_pif is
signal p2c_i : t_p2c; -- internal version of output
signal rdata_i : std_logic_vector(7 downto 0) := (others => '0');
begin
-- Assigning internally used signals to outputs
p2c <= p2c_i;
--
-- Auxiliary Register Control.
--
-- Provides read/write/trigger strobes and write data to auxiliary
-- registers and fields, i.e., registers and fields implemented in core.
--
p_aux : process (wdata, addr, cs, wr, rd)
begin
-- Defaults
p2c_i.awo_tx_data <= (others => '0');
p2c_i.awo_tx_data_we <= '0';
p2c_i.aro_rx_data_re <= '0';
-- Write decoding
if wr = '1' and cs = '1' then
case to_integer(addr) is
when C_ADDR_TX_DATA =>
p2c_i.awo_tx_data <= wdata;
p2c_i.awo_tx_data_we <= '1';
when others =>
null;
end case;
end if;
-- Read Enable Decoding
if rd = '1' and cs = '1' then
case to_integer(addr) is
when C_ADDR_RX_DATA =>
p2c_i.aro_rx_data_re <= '1';
when others =>
null;
end case;
end if;
end process p_aux;
p_read_reg : process(cs, addr, rd, c2p, p2c_i)
begin
-- default values
rdata_i <= (others => '0');
if cs = '1' and rd = '1' then
case to_integer(addr) is
when C_ADDR_RX_DATA =>
rdata_i(7 downto 0) <= c2p.aro_rx_data;
when C_ADDR_RX_DATA_VALID =>
rdata_i(0) <= c2p.aro_rx_data_valid;
when C_ADDR_TX_READY =>
rdata_i(0) <= c2p.aro_tx_ready;
when others =>
null;
end case;
end if;
end process p_read_reg;
rdata <= rdata_i;
end rtl;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/Complex3Multiply_block3.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Complex3Multiply_block3
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/TWDLMULT_SDNF1_3/Complex3Multiply
-- Hierarchy Level: 3
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Complex3Multiply_block3 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
din1_re_dly3 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
din1_im_dly3 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
din1_vld_dly3 : IN std_logic;
twdl_3_7_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_7_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
softReset : IN std_logic;
twdlXdin_7_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_7_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin1_vld : OUT std_logic
);
END Complex3Multiply_block3;
ARCHITECTURE rtl OF Complex3Multiply_block3 IS
-- Signals
SIGNAL din1_re_dly3_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din_re_reg : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_im_dly3_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din_im_reg : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL adder_add_cast : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL adder_add_cast_1 : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL din_sum : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL twdl_3_7_re_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_re_reg : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_7_im_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_im_reg : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL adder_add_cast_2 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL adder_add_cast_3 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL twdl_sum : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL Complex3Multiply_din1_re_pipe1 : signed(15 DOWNTO 0); -- sfix16
SIGNAL Complex3Multiply_din1_im_pipe1 : signed(15 DOWNTO 0); -- sfix16
SIGNAL Complex3Multiply_din1_sum_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_prodOfRe_pipe1 : signed(31 DOWNTO 0); -- sfix32
SIGNAL Complex3Multiply_ProdOfIm_pipe1 : signed(31 DOWNTO 0); -- sfix32
SIGNAL Complex3Multiply_prodOfSum_pipe1 : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Multiply_twiddle_re_pipe1 : signed(15 DOWNTO 0); -- sfix16
SIGNAL Complex3Multiply_twiddle_im_pipe1 : signed(15 DOWNTO 0); -- sfix16
SIGNAL Complex3Multiply_twiddle_sum_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL prodOfRe : signed(31 DOWNTO 0); -- sfix32_En27
SIGNAL prodOfIm : signed(31 DOWNTO 0); -- sfix32_En27
SIGNAL prodOfSum : signed(33 DOWNTO 0); -- sfix34_En27
SIGNAL din_vld_dly1 : std_logic;
SIGNAL din_vld_dly2 : std_logic;
SIGNAL din_vld_dly3 : std_logic;
SIGNAL prod_vld : std_logic;
SIGNAL Complex3Add_tmpResult_reg : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Add_multRes_re_reg1 : signed(32 DOWNTO 0); -- sfix33
SIGNAL Complex3Add_multRes_re_reg2 : signed(32 DOWNTO 0); -- sfix33
SIGNAL Complex3Add_multRes_im_reg : signed(34 DOWNTO 0); -- sfix35
SIGNAL Complex3Add_prod_vld_reg1 : std_logic;
SIGNAL Complex3Add_prod_vld_reg2 : std_logic;
SIGNAL Complex3Add_prodOfSum_reg : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Add_tmpResult_reg_next : signed(33 DOWNTO 0); -- sfix34_En27
SIGNAL Complex3Add_multRes_re_reg1_next : signed(32 DOWNTO 0); -- sfix33_En27
SIGNAL Complex3Add_multRes_re_reg2_next : signed(32 DOWNTO 0); -- sfix33_En27
SIGNAL Complex3Add_multRes_im_reg_next : signed(34 DOWNTO 0); -- sfix35_En27
SIGNAL Complex3Add_prod_vld_reg1_next : std_logic;
SIGNAL Complex3Add_prod_vld_reg2_next : std_logic;
SIGNAL Complex3Add_prodOfSum_reg_next : signed(33 DOWNTO 0); -- sfix34_En27
SIGNAL multResFP_re : signed(32 DOWNTO 0); -- sfix33_En27
SIGNAL multResFP_im : signed(34 DOWNTO 0); -- sfix35_En27
SIGNAL twdlXdin_7_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_7_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
BEGIN
din1_re_dly3_signed <= signed(din1_re_dly3);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_re_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
din_re_reg <= to_signed(16#0000#, 16);
ELSE
din_re_reg <= din1_re_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_process;
din1_im_dly3_signed <= signed(din1_im_dly3);
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_im_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
din_im_reg <= to_signed(16#0000#, 16);
ELSE
din_im_reg <= din1_im_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_1_process;
adder_add_cast <= resize(din_re_reg, 17);
adder_add_cast_1 <= resize(din_im_reg, 17);
din_sum <= adder_add_cast + adder_add_cast_1;
twdl_3_7_re_signed <= signed(twdl_3_7_re);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_re_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
twdl_re_reg <= to_signed(16#0000#, 16);
ELSE
twdl_re_reg <= twdl_3_7_re_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_2_process;
twdl_3_7_im_signed <= signed(twdl_3_7_im);
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_im_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
twdl_im_reg <= to_signed(16#0000#, 16);
ELSE
twdl_im_reg <= twdl_3_7_im_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_3_process;
adder_add_cast_2 <= resize(twdl_re_reg, 17);
adder_add_cast_3 <= resize(twdl_im_reg, 17);
twdl_sum <= adder_add_cast_2 + adder_add_cast_3;
-- Complex3Multiply
Complex3Multiply_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
prodOfRe <= Complex3Multiply_prodOfRe_pipe1;
prodOfIm <= Complex3Multiply_ProdOfIm_pipe1;
prodOfSum <= Complex3Multiply_prodOfSum_pipe1;
Complex3Multiply_twiddle_re_pipe1 <= twdl_re_reg;
Complex3Multiply_twiddle_im_pipe1 <= twdl_im_reg;
Complex3Multiply_twiddle_sum_pipe1 <= twdl_sum;
Complex3Multiply_din1_re_pipe1 <= din_re_reg;
Complex3Multiply_din1_im_pipe1 <= din_im_reg;
Complex3Multiply_din1_sum_pipe1 <= din_sum;
Complex3Multiply_prodOfRe_pipe1 <= Complex3Multiply_din1_re_pipe1 * Complex3Multiply_twiddle_re_pipe1;
Complex3Multiply_ProdOfIm_pipe1 <= Complex3Multiply_din1_im_pipe1 * Complex3Multiply_twiddle_im_pipe1;
Complex3Multiply_prodOfSum_pipe1 <= Complex3Multiply_din1_sum_pipe1 * Complex3Multiply_twiddle_sum_pipe1;
END IF;
END IF;
END PROCESS Complex3Multiply_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly1 <= din1_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly2 <= din_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly3 <= din_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
prod_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
prod_vld <= din_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_7_process;
-- Complex3Add
Complex3Add_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Complex3Add_prodOfSum_reg <= to_signed(0, 34);
Complex3Add_tmpResult_reg <= to_signed(0, 34);
Complex3Add_multRes_re_reg1 <= to_signed(0, 33);
Complex3Add_multRes_re_reg2 <= to_signed(0, 33);
Complex3Add_multRes_im_reg <= to_signed(0, 35);
Complex3Add_prod_vld_reg1 <= '0';
Complex3Add_prod_vld_reg2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Complex3Add_tmpResult_reg <= Complex3Add_tmpResult_reg_next;
Complex3Add_multRes_re_reg1 <= Complex3Add_multRes_re_reg1_next;
Complex3Add_multRes_re_reg2 <= Complex3Add_multRes_re_reg2_next;
Complex3Add_multRes_im_reg <= Complex3Add_multRes_im_reg_next;
Complex3Add_prod_vld_reg1 <= Complex3Add_prod_vld_reg1_next;
Complex3Add_prod_vld_reg2 <= Complex3Add_prod_vld_reg2_next;
Complex3Add_prodOfSum_reg <= Complex3Add_prodOfSum_reg_next;
END IF;
END IF;
END PROCESS Complex3Add_process;
Complex3Add_output : PROCESS (Complex3Add_tmpResult_reg, Complex3Add_multRes_re_reg1,
Complex3Add_multRes_re_reg2, Complex3Add_multRes_im_reg,
Complex3Add_prod_vld_reg1, Complex3Add_prod_vld_reg2,
Complex3Add_prodOfSum_reg, prodOfRe, prodOfIm, prodOfSum, prod_vld)
VARIABLE sub_cast : signed(32 DOWNTO 0);
VARIABLE sub_cast_0 : signed(32 DOWNTO 0);
VARIABLE sub_cast_1 : signed(34 DOWNTO 0);
VARIABLE sub_cast_2 : signed(34 DOWNTO 0);
VARIABLE add_cast : signed(32 DOWNTO 0);
VARIABLE add_cast_0 : signed(32 DOWNTO 0);
VARIABLE add_temp : signed(32 DOWNTO 0);
BEGIN
Complex3Add_tmpResult_reg_next <= Complex3Add_tmpResult_reg;
Complex3Add_multRes_re_reg1_next <= Complex3Add_multRes_re_reg1;
Complex3Add_prodOfSum_reg_next <= Complex3Add_prodOfSum_reg;
Complex3Add_multRes_re_reg2_next <= Complex3Add_multRes_re_reg1;
IF prod_vld = '1' THEN
sub_cast := resize(prodOfRe, 33);
sub_cast_0 := resize(prodOfIm, 33);
Complex3Add_multRes_re_reg1_next <= sub_cast - sub_cast_0;
END IF;
sub_cast_1 := resize(Complex3Add_prodOfSum_reg, 35);
sub_cast_2 := resize(Complex3Add_tmpResult_reg, 35);
Complex3Add_multRes_im_reg_next <= sub_cast_1 - sub_cast_2;
IF prod_vld = '1' THEN
add_cast := resize(prodOfRe, 33);
add_cast_0 := resize(prodOfIm, 33);
add_temp := add_cast + add_cast_0;
Complex3Add_tmpResult_reg_next <= resize(add_temp, 34);
END IF;
IF prod_vld = '1' THEN
Complex3Add_prodOfSum_reg_next <= prodOfSum;
END IF;
Complex3Add_prod_vld_reg2_next <= Complex3Add_prod_vld_reg1;
Complex3Add_prod_vld_reg1_next <= prod_vld;
multResFP_re <= Complex3Add_multRes_re_reg2;
multResFP_im <= Complex3Add_multRes_im_reg;
twdlXdin1_vld <= Complex3Add_prod_vld_reg2;
END PROCESS Complex3Add_output;
twdlXdin_7_re_tmp <= multResFP_re(29 DOWNTO 14);
twdlXdin_7_re <= std_logic_vector(twdlXdin_7_re_tmp);
twdlXdin_7_im_tmp <= multResFP_im(29 DOWNTO 14);
twdlXdin_7_im <= std_logic_vector(twdlXdin_7_im_tmp);
END rtl;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 18/03/2015
--! Module Name: EPROC_OUT2
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee,work;
use ieee.std_logic_1164.all;
use work.all;
--! E-link processor, 2bit output
entity EPROC_OUT2 is
generic (do_generate : boolean := true);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
getDataTrig : out std_logic; -- @ bitCLKx4
ENCODING : in std_logic_vector (3 downto 0);
EDATA_OUT : out std_logic_vector (1 downto 0);
TTCin : in std_logic_vector (1 downto 0);
DATA_IN : in std_logic_vector (9 downto 0);
DATA_RDY : in std_logic
);
end EPROC_OUT2;
architecture Behavioral of EPROC_OUT2 is
constant zeros2bit : std_logic_vector (1 downto 0) := (others=>'0');
signal EdataOUT_ENC8b10b_case, EdataOUT_direct_case, EdataOUT_HDLC_case, EdataOUT_TTC0_case : std_logic_vector (1 downto 0);
signal rst_s, rst_case000, rst_case001, rst_case010, rst_case011 : std_logic;
signal getDataTrig_ENC8b10b_case, getDataTrig_direct_case, getDataTrig_HDLC_case, getDataTrig_TTC_case : std_logic;
begin
gen_enabled: if do_generate = true generate
rst_s <= rst or (not ENA);
-------------------------------------------------------------------------------------------
-- case 0: direct data, no delimeter...
-------------------------------------------------------------------------------------------
rst_case000 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "000")) else '1';
--
direct_case: entity work.EPROC_OUT2_direct
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case000,
getDataTrig => getDataTrig_direct_case,
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_direct_case
);
--
-------------------------------------------------------------------------------------------
-- case 1: DEC8b10b
-------------------------------------------------------------------------------------------
rst_case001 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "001")) else '1';
--
ENC8b10b_case: entity work.EPROC_OUT2_ENC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case001,
getDataTrig => getDataTrig_ENC8b10b_case,
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_ENC8b10b_case
);
--
-------------------------------------------------------------------------------------------
-- case 2: HDLC
-------------------------------------------------------------------------------------------
rst_case010 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "010")) else '1';
--
HDLC_case: entity work.EPROC_OUT2_HDLC
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case010,
getDataTrig => getDataTrig_HDLC_case, -- output, data request
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_HDLC_case
);
--
-------------------------------------------------------------------------------------------
-- case 3: TTC-0
-------------------------------------------------------------------------------------------
rst_case011 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "011")) else '1';
--
getDataTrig_TTC_case <= '0'; --'1' when (ENCODING(2 downto 0) = "011") else '0';
--
ttc_r: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst_case011 = '1' then
EdataOUT_TTC0_case <= zeros2bit;
else
EdataOUT_TTC0_case <= TTCin;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- output data and busy according to the encoding settings
-------------------------------------------------------------------------------------------
dataOUTmux: entity work.MUX4_Nbit
generic map (N=>2)
port map(
data0 => EdataOUT_direct_case,
data1 => EdataOUT_ENC8b10b_case,
data2 => EdataOUT_HDLC_case,
data3 => EdataOUT_TTC0_case,
sel => ENCODING(1 downto 0),
data_out => EDATA_OUT
);
--
getDataTrig <= ENA and (getDataTrig_TTC_case or getDataTrig_HDLC_case or getDataTrig_ENC8b10b_case or getDataTrig_direct_case);
--
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
EDATA_OUT <= (others=>'0');
getDataTrig <= '0';
end generate gen_disabled;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use ieee.numeric_std.all;
entity tb is
generic(
address_width: integer := 14;
memory_file : string := "code.txt";
log_file: string := "out.txt";
uart_support : string := "no"
);
end tb;
architecture tb of tb is
signal clock_in, reset, data, stall, stall_sig: std_logic := '0';
signal uart_read, uart_write: std_logic;
signal boot_enable_n, ram_enable_n, ram_dly: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal gpioa_in, gpioa_out, gpioa_ddr: std_logic_vector(7 downto 0);
signal gpio_sig: std_logic := '0';
begin
process --25Mhz system clock
begin
clock_in <= not clock_in;
wait for 20 ns;
clock_in <= not clock_in;
wait for 20 ns;
end process;
process
begin
wait for 4 ms;
gpio_sig <= not gpio_sig;
wait for 100 us;
gpio_sig <= not gpio_sig;
end process;
gpioa_in <= "0000" & gpio_sig & "000";
process
begin
stall <= not stall;
wait for 123 ns;
stall <= not stall;
wait for 123 ns;
end process;
reset <= '0', '1' after 5 ns, '0' after 500 ns;
stall_sig <= '0'; --stall;
ext_irq <= "0000000" & periph_irq;
boot_enable_n <= '0' when (address(31 downto 28) = "0000" and stall_sig = '0') or reset = '1' else '1';
ram_enable_n <= '0' when (address(31 downto 28) = "0100" and stall_sig = '0') or reset = '1' else '1';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
process(clock_in, reset)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
elsif clock_in'event and clock_in = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
end if;
end process;
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock_in,
rst_i => reset,
stall_i => stall_sig,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s;
data_write_periph <= data_write;
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock_in,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr
);
-- boot ROM
boot0lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 0)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(7 downto 0)
);
boot0ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 1)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(15 downto 8)
);
boot1lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 2)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(23 downto 16)
);
boot1ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 3)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(31 downto 24)
);
-- RAM
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
-- debug process
debug:
if uart_support = "no" generate
process(clock_in, address)
file store_file : text open write_mode is "debug.txt";
variable hex_file_line : line;
variable c : character;
variable index : natural;
variable line_length : natural := 0;
begin
if clock_in'event and clock_in = '1' then
if address = x"f00000d0" and data = '0' then
data <= '1';
index := conv_integer(data_write(6 downto 0));
if index /= 10 then
c := character'val(index);
write(hex_file_line, c);
line_length := line_length + 1;
end if;
if index = 10 or line_length >= 72 then
writeline(store_file, hex_file_line);
line_length := 0;
end if;
else
data <= '0';
end if;
end if;
end process;
end generate;
process(clock_in, reset, address)
begin
if reset = '1' then
elsif clock_in'event and clock_in = '0' then
assert address /= x"e0000000" report "end of simulation" severity failure;
assert (address < x"50000000") or (address >= x"e0000000") report "out of memory region" severity failure;
assert address /= x"40000104" report "handling IRQ" severity warning;
end if;
end process;
end tb;
|
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2015 <[email protected]>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pp_types.all;
use work.pp_utilities.all;
--! @brief Wishbone adapter, for connecting the processor to a Wishbone bus when not using caches.
entity pp_wb_adapter is
port(
clk : in std_logic;
reset : in std_logic;
-- Processor data memory signals:
signal mem_address : in std_logic_vector(31 downto 0);
signal mem_data_in : in std_logic_vector(31 downto 0); -- Data in from the bus
signal mem_data_out : out std_logic_vector(31 downto 0); -- Data out to the bus
signal mem_data_size : in std_logic_vector( 1 downto 0);
signal mem_read_req : in std_logic;
signal mem_read_ack : out std_logic;
signal mem_write_req : in std_logic;
signal mem_write_ack : out std_logic;
-- Wishbone interface:
wb_inputs : in wishbone_master_inputs;
wb_outputs : out wishbone_master_outputs
);
end entity pp_wb_adapter;
architecture behaviour of pp_wb_adapter is
type states is (IDLE, READ_WAIT_ACK, WRITE_WAIT_ACK);
signal state : states;
signal mem_r_ack : std_logic;
function get_data_shift(size : in std_logic_vector(1 downto 0); address : in std_logic_vector)
return natural is
begin
case size is
when b"01" =>
case address(1 downto 0) is
when b"00" =>
return 0;
when b"01" =>
return 8;
when b"10" =>
return 16;
when b"11" =>
return 24;
when others =>
return 0;
end case;
when b"10" =>
if address(1) = '0' then
return 0;
else
return 16;
end if;
when others =>
return 0;
end case;
end function get_data_shift;
begin
mem_write_ack <= '1' when state = WRITE_WAIT_ACK and wb_inputs.ack = '1' else '0';
mem_read_ack <= mem_r_ack;
wishbone: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
state <= IDLE;
wb_outputs.cyc <= '0';
wb_outputs.stb <= '0';
mem_r_ack <= '0';
else
case state is
when IDLE =>
mem_r_ack <= '0';
-- Prioritize requests from the data memory:
if mem_write_req = '1' then
wb_outputs.adr <= mem_address;
wb_outputs.dat <= std_logic_vector(shift_left(unsigned(mem_data_in),
get_data_shift(mem_data_size, mem_address)));
wb_outputs.sel <= wb_get_data_sel(mem_data_size, mem_address);
wb_outputs.cyc <= '1';
wb_outputs.stb <= '1';
wb_outputs.we <= '1';
state <= WRITE_WAIT_ACK;
elsif mem_read_req = '1' then
wb_outputs.adr <= mem_address;
wb_outputs.sel <= wb_get_data_sel(mem_data_size, mem_address);
wb_outputs.cyc <= '1';
wb_outputs.stb <= '1';
wb_outputs.we <= '0';
state <= READ_WAIT_ACK;
end if;
when READ_WAIT_ACK =>
if wb_inputs.ack = '1' then
mem_data_out <= std_logic_vector(shift_right(unsigned(wb_inputs.dat),
get_data_shift(mem_data_size, mem_address)));
wb_outputs.cyc <= '0';
wb_outputs.stb <= '0';
mem_r_ack <= '1';
state <= IDLE;
end if;
when WRITE_WAIT_ACK =>
if wb_inputs.ack = '1' then
wb_outputs.cyc <= '0';
wb_outputs.stb <= '0';
wb_outputs.we <= '0';
state <= IDLE;
end if;
end case;
end if;
end if;
end process wishbone;
end architecture behaviour;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:37:54 04/11/2017
-- Design Name:
-- Module Name: debounce - logic
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY debounce IS
GENERIC(
counter_size : INTEGER := 20); --counter size (19 bits gives 10.5ms with 50MHz clock)
PORT(
clk : IN STD_LOGIC; --input clock
button : IN STD_LOGIC; --input signal to be debounced
result : OUT STD_LOGIC); --debounced signal
END debounce;
ARCHITECTURE logic OF debounce IS
SIGNAL flipflops : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops
SIGNAL counter_set : STD_LOGIC; --sync reset to zero
SIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0'); --counter output
BEGIN
counter_set <= flipflops(0) xor flipflops(1); --determine when to start/reset counter
PROCESS(clk)
BEGIN
IF(clk'EVENT and clk = '1') THEN
flipflops(0) <= button;
flipflops(1) <= flipflops(0);
If(counter_set = '1') THEN --reset counter because input is changing
counter_out <= (OTHERS => '0');
ELSIF(counter_out(counter_size) = '0') THEN --stable input time is not yet met
counter_out <= counter_out + 1;
ELSE --stable input time is met
result <= flipflops(1);
END IF;
END IF;
END PROCESS;
END logic; |
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