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----------------------------------------------------------------------------------
--
-- full_tb.vhd
--
-- (c) 2015
-- L. Schrittwieser
-- N. Huesser
--
----------------------------------------------------------------------------------
--
-- A testbench to test the logger core with real inputs.
--
----------------------------------------------------------------------------------
library UNISIM;
use UNISIM.VCOMPONENTS.all;
library UNIMACRO;
use UNIMACRO.VCOMPONENTS.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.math_real.all;
entity full_tb is
end full_tb;
architecture Behavioral of full_tb is
-- TODO:
-- create testsignals here
signal tbClkxC : std_logic := '0';
signal tbRstxRB : std_logic := '0';
signal tbDataxD : std_logic_vector(31 downto 0) := (others => '0');
signal tbCntxD: signed(15 downto 0) := to_signed(-430, 16);
signal tbValidxS : std_logic := '0';
signal tbReadyxS: std_logic := '0';
signal tbData0xDO: std_logic_vector(15 downto 0) := (others => '0');
signal tbData1xDO: std_logic_vector(15 downto 0) := (others => '0');
signal tbStrobexS: std_logic := '0';
begin
-- generate clock
tbClkxC <= not tbClkxC after 1ns;
tbDataxD <= std_logic_vector(tbCntxD) & std_logic_vector(tbCntxD);
DUT : entity work.axis_to_data_lanes
generic map (
Decimation => 3
)
port map (
ClkxCI => tbClkxC,
RstxRBI => tbRstxRB,
AxiTDataxDI=> tbDataxD,
AxiTValid => tbValidxS,
AxiTReady => tbReadyxS,
Data0xDO => tbData0xDO,
Data1xDO => tbData1xDO,
DataStrobexDO => tbStrobexS
);
process
begin
-- TODO:
-- write chain of events here
tbRstxRB <= '0';
wait until rising_edge(tbClkxC);
wait until rising_edge(tbClkxC);
tbRstxRB <= '1';
wait until rising_edge(tbClkxC);
tbValidxS <= '0';
for i in 0 to 30 loop
wait until rising_edge(tbClkxC);
end loop;
tbValidxS <= '1';
for i in 0 to 30 loop
wait until rising_edge(tbClkxC);
end loop;
wait;
end process;
process(tbClkxC, tbRstxRB, tbCntxD)
begin
if rising_edge(tbClkxC) then
tbCntxD <= to_signed(-430, 16);
if tbRstxRB = '1' then
tbCntxD <= tbCntxD + 1;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- Ver 0.82 Fixed RCR X,CL --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE work.cpu86pack.ALL;
ENTITY ALU IS
PORT(
alu_inbusa : IN std_logic_vector (15 DOWNTO 0);
alu_inbusb : IN std_logic_vector (15 DOWNTO 0);
aluopr : IN std_logic_vector (6 DOWNTO 0);
ax_s : IN std_logic_vector (15 DOWNTO 0);
clk : IN std_logic;
cx_s : IN std_logic_vector (15 DOWNTO 0);
dx_s : IN std_logic_vector (15 DOWNTO 0);
reset : IN std_logic;
w : IN std_logic;
wralu : IN std_logic;
wrcc : IN std_logic;
wrtemp : IN std_logic;
alubus : OUT std_logic_vector (15 DOWNTO 0);
ccbus : OUT std_logic_vector (15 DOWNTO 0);
div_err : OUT std_logic
);
END ALU ;
architecture rtl of alu is
component divider is -- Generic Divider
generic(
WIDTH_DIVID : Integer := 32; -- Width Dividend
WIDTH_DIVIS : Integer := 16; -- Width Divisor
WIDTH_SHORT : Integer := 8); -- Check Overflow against short Byte/Word
port(
clk : in std_logic; -- System Clock, not used in this architecture
reset : in std_logic; -- Active high, not used in this architecture
dividend : in std_logic_vector (WIDTH_DIVID-1 DOWNTO 0);
divisor : in std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0);
quotient : out std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0); -- changed to 16 bits!! (S not D)
remainder : out std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0);
twocomp : in std_logic; -- '1' = 2's Complement, '0' = Unsigned
w : in std_logic; -- '0'=byte, '1'=word (cpu processor)
overflow : out std_logic; -- '1' if div by 0 or overflow
start : in std_logic; -- not used in this architecture
done : out std_logic); -- not used in this architecture
end component divider;
component multiplier is -- Generic Multiplier
generic (WIDTH : integer := 16);
port (multiplicant : in std_logic_vector (WIDTH-1 downto 0);
multiplier : in std_logic_vector (WIDTH-1 downto 0);
product : out std_logic_vector (WIDTH+WIDTH-1 downto 0);-- result
twocomp : in std_logic);
end component multiplier;
signal product_s : std_logic_vector(31 downto 0); -- result multiplier
signal dividend_s : std_logic_vector(31 downto 0); -- Input divider
signal remainder_s : std_logic_vector(15 downto 0); -- Divider result
signal quotient_s : std_logic_vector(15 downto 0); -- Divider result
signal divresult_s : std_logic_vector(31 DOWNTO 0); -- Output divider to alubus
signal div_err_s : std_logic; -- Divide by 0
signal twocomp_s : std_logic; -- Sign Extend for IMUL and IDIV
signal wl_s : std_logic; -- Latched w signal, used for muliplier/divider
signal alubus_s : std_logic_vector (15 DOWNTO 0);
signal abus_s : std_logic_vector(15 downto 0);
signal bbus_s : std_logic_vector(15 downto 0);
signal dxbus_s : std_logic_vector(15 downto 0); -- DX register
signal addbbus_s : std_logic_vector(15 downto 0); -- bbus connected to full adder
signal cbus_s : std_logic_vector(16 downto 0); -- Carry Bus
signal outbus_s : std_logic_vector(15 downto 0); -- outbus=abus+bbus
signal sign16a_s : std_logic_vector(15 downto 0); -- sign extended alu_busa(7 downto 0)
signal sign16b_s : std_logic_vector(15 downto 0); -- sign extended alu_busb(7 downto 0)
signal sign32a_s : std_logic_vector(15 downto 0); -- 16 bits alu_busa(15) vector (CWD)
signal aasbus_s : std_logic_vector(15 downto 0); -- used for AAS instruction
signal aas1bus_s : std_logic_vector(15 downto 0);
signal daabus_s : std_logic_vector(7 downto 0); -- used for DAA instruction
signal dasbus_s : std_logic_vector(7 downto 0); -- used for DAS instruction
signal aaabus_s : std_logic_vector(15 downto 0); -- used for AAA instruction
signal aaa1bus_s : std_logic_vector(15 downto 0);
signal aadbus_s : std_logic_vector(15 downto 0); -- used for AAD instruction
signal aad1bus_s : std_logic_vector(10 downto 0);
signal aad2bus_s : std_logic_vector(10 downto 0);
signal setaas_s : std_logic; -- '1' set CF & AF else both 0
signal setaaa_s : std_logic; -- '1' set CF & AF else both 0
signal setdaa_s : std_logic_vector(1 downto 0); -- "11" set CF & AF
signal setdas_s : std_logic_vector(1 downto 0); -- "11" set CF & AF
signal bit4_s : std_logic; -- used for AF flag
signal cout_s : std_logic;
signal psrreg_s : std_logic_vector(15 downto 0); -- 16 bits flag register
signal zflaglow_s : std_logic; -- low byte zero flag (w=0)
signal zflaghigh_s : std_logic; -- high byte zero flag (w=1)
signal zeroflag_s : std_logic; -- zero flag, asserted when zero
signal c1flag_s : std_logic; -- Asserted when CX=1(w=1) or CL=1(w=0)
signal zflagdx_s : std_logic; -- Result (DX) zero flag, asserted when not zero (used for mul/imul)
signal zflagah_s : std_logic; -- '1' if IMUL(15..8)/=0
signal hflagah_s : std_logic; -- Used for IMUL
signal hflagdx_s : std_logic; -- Used for IMUL
signal overflow_s : std_logic;
signal parityflag_s: std_logic;
signal signflag_s : std_logic;
alias OFLAG : std_logic is psrreg_s(11);
alias DFLAG : std_logic is psrreg_s(10);
alias IFLAG : std_logic is psrreg_s(9);
alias TFLAG : std_logic is psrreg_s(8);
alias SFLAG : std_logic is psrreg_s(7);
alias ZFLAG : std_logic is psrreg_s(6);
alias AFLAG : std_logic is psrreg_s(4);
alias PFLAG : std_logic is psrreg_s(2);
alias CFLAG : std_logic is psrreg_s(0);
signal alureg_s : std_logic_vector(31 downto 0); -- 31 bits temp register for alu_inbusa & alu_inbusb
signal alucout_s : std_logic; -- ALUREG Carry Out signal
signal alu_temp_s : std_logic_vector(15 downto 0); -- Temp/scratchpad register, use ALU_TEMP to select
signal done_s : std_logic; -- Serial divider conversion done
signal startdiv_s : std_logic; -- Serial divider start pulse
begin
ALUU1 : divider
generic map (WIDTH_DIVID => 32, WIDTH_DIVIS => 16, WIDTH_SHORT => 8)
port map (clk => clk,
reset => reset,
dividend => dividend_s, -- DX:AX
divisor => alureg_s(15 downto 0), -- 0&byte/word
--divisor => bbus_s, -- byte/word
quotient => quotient_s, -- 16 bits
remainder => remainder_s, -- 16 bits
twocomp => twocomp_s,
w => wl_s, -- Byte/Word
overflow => div_err_s, -- Divider Overflow. generate int0
start => startdiv_s, -- start conversion, generated by proc
done => done_s); -- conversion done, latch results
ALUU2 : multiplier
generic map (WIDTH => 16) -- Result is 2*WIDTH bits
port map (multiplicant=> alureg_s(31 downto 16),
multiplier => alureg_s(15 downto 0),
product => product_s, -- 32 bits!
twocomp => twocomp_s);
dividend_s <= X"000000"&alureg_s(23 downto 16) when aluopr=ALU_AAM else dxbus_s & alureg_s(31 downto 16);-- DX is sign extended for byte IDIV
-- start serial divider 1 cycle after wralu pulse received. The reason is that the dividend is loaded into the
-- accumulator thus the data must be valid when this happens.
process (clk, reset)
begin
if reset='1' then
startdiv_s <= '0';
elsif rising_edge(clk) then
if (wralu='1' and (aluopr=ALU_DIV or aluopr=ALU_IDIV OR aluopr=ALU_AAM)) then
startdiv_s <= '1';
else
startdiv_s <= '0';
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Create Full adder
----------------------------------------------------------------------------
fulladd: for bit_nr in 0 to 15 generate
outbus_s(bit_nr) <= abus_s(bit_nr) xor addbbus_s(bit_nr) xor cbus_s(bit_nr);
cbus_s(bit_nr+1) <= (abus_s(bit_nr) and addbbus_s(bit_nr)) or
(abus_s(bit_nr) and cbus_s(bit_nr)) or
(addbbus_s(bit_nr) and cbus_s(bit_nr));
end generate fulladd;
bit4_s <= cbus_s(4);
sign16a_s <= alu_inbusa(7) &alu_inbusa(7) &alu_inbusa(7) &alu_inbusa(7)&alu_inbusa(7)&
alu_inbusa(7) &alu_inbusa(7) &alu_inbusa(7) &alu_inbusa(7 downto 0);
sign16b_s <= alu_inbusb(7) &alu_inbusb(7) &alu_inbusb(7) &alu_inbusb(7)&alu_inbusb(7)&
alu_inbusb(7) &alu_inbusb(7) &alu_inbusb(7) &alu_inbusb(7 downto 0);
sign32a_s <= alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&
alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&
alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&
alu_inbusa(15);
-- Invert bus for subtract instructions
addbbus_s <= not bbus_s when ((aluopr=ALU_CMP) or (aluopr=ALU_CMP_SE) or (aluopr=ALU_CMPS) or (aluopr=ALU_DEC)
or (aluopr=ALU_SBB) or (aluopr=ALU_SBB_SE) or (aluopr=ALU_PUSH) or (aluopr=ALU_SUB)
or (aluopr=ALU_SUB_SE) or (aluopr=ALU_SCAS)) else bbus_s;
-- sign extend for IDIV and IMUL instructions
twocomp_s <= '1' when ((aluopr=ALU_IDIV) or (aluopr=ALU_IMUL) or
(aluopr=ALU_IDIV2)or (aluopr=ALU_IMUL2)) else '0';
----------------------------------------------------------------------------
-- Sign Extend Logic abus & bbus & dxbus
----------------------------------------------------------------------------
process (w, alu_inbusa, alu_inbusb, sign16a_s, sign16b_s, aluopr, ax_s, alureg_s)
begin
if (w='1') then -- Word, no sign extend, unless signextend is specified
case aluopr is
when ALU_CMPS =>
abus_s <= alu_inbusa; -- no sign extend
bbus_s <= alureg_s(15 downto 0); -- previous read ES:[DI]
when ALU_NEG | ALU_NOT =>
abus_s <= not(alu_inbusa); -- NEG instruction, not(operand)+1
bbus_s <= alu_inbusb; -- 0001 (0000 for NOT)
when ALU_ADD_SE | ALU_ADC_SE | ALU_SBB_SE | ALU_SUB_SE | ALU_CMP_SE |
ALU_OR_SE | ALU_AND_SE | ALU_XOR_SE=>
abus_s <= alu_inbusa; -- no sign extend
bbus_s <= sign16b_s; -- Sign extend on 8 bits immediate values (see O80I2RM)
when others =>
abus_s <= alu_inbusa; -- no sign extend
bbus_s <= alu_inbusb;
end case;
else
case aluopr is
when ALU_CMPS =>
abus_s <= alu_inbusa;
bbus_s <= alureg_s(15 downto 0);
when ALU_DIV | ALU_DIV2 =>
abus_s <= ax_s;
bbus_s <= alu_inbusb;
when ALU_IDIV| ALU_IDIV2 =>
abus_s <= ax_s;
bbus_s <= sign16b_s;
when ALU_MUL | ALU_MUL2 | ALU_SCAS =>
abus_s <= alu_inbusa;
bbus_s <= alu_inbusb;
when ALU_NEG | ALU_NOT =>
abus_s <= not(alu_inbusa); -- NEG instruction, not(operand)+1
bbus_s <= alu_inbusb; -- 0001 (0000 for NOT)
when others =>
abus_s <= sign16a_s;
bbus_s <= sign16b_s;
end case;
end if;
end process;
process (wl_s, aluopr, dx_s, alu_inbusa) -- dxbus for DIV/IDIV only
begin
if (wl_s='1') then -- Word, no sign extend
dxbus_s <= dx_s;
else -- Byte
if (((aluopr=ALU_IDIV) or (aluopr=ALU_IDIV2)) and (alu_inbusa(15)='1')) then -- signed DX<-SE(AX)/bbus<-SE(byte)
dxbus_s <= X"FFFF"; -- DX=FFFF (ignored for mul)
else
dxbus_s <= X"0000"; -- DX=0000 (ignored for mul)
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Carry In logic
----------------------------------------------------------------------------
process (aluopr, psrreg_s)
begin
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_INC | ALU_POP | ALU_NEG | ALU_NOT
=> cbus_s(0) <= '0';
when ALU_SBB | ALU_SBB_SE
=> cbus_s(0) <= not CFLAG;
when ALU_SUB | ALU_SUB_SE | ALU_DEC | ALU_PUSH | ALU_CMP | ALU_CMP_SE
| ALU_CMPS | ALU_SCAS
=> cbus_s(0) <= '1';
when others => cbus_s(0) <= CFLAG; -- ALU_ADC, ALU_SUB, ALU_SBB
end case;
end process;
----------------------------------------------------------------------------
-- Carry Out logic
-- cout is inverted for ALU_SUB and ALU_SBB before written to psrreg_s
----------------------------------------------------------------------------
process (aluopr, w, psrreg_s, cbus_s, alu_inbusa)
begin
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_ADC | ALU_ADC_SE | ALU_SUB | ALU_SUB_SE | ALU_SBB | ALU_SBB_SE |
ALU_CMP | ALU_CMP_SE | ALU_CMPS| ALU_SCAS =>
if (w='1') then cout_s <= cbus_s(16);
else cout_s <= cbus_s(8);
end if;
when ALU_NEG => -- CF=0 if operand=0, else 1
if (alu_inbusa=X"0000") then
cout_s <= '1'; -- Note CFLAG=NOT(cout_s)
else
cout_s <= '0'; -- Note CFLAG=NOT(cout_s)
end if;
when others =>
cout_s <= CFLAG; -- Keep previous value
end case;
end process;
----------------------------------------------------------------------------
-- Overflow Logic
----------------------------------------------------------------------------
process (aluopr, w, psrreg_s, cbus_s, alureg_s, alucout_s, zflaghigh_s, zflagdx_s,hflagdx_s,zflagah_s,
hflagah_s, wl_s, product_s, c1flag_s)
begin
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_ADC | ALU_ADC_SE | ALU_INC | ALU_DEC | ALU_SUB | ALU_SUB_SE |
ALU_SBB | ALU_SBB_SE | ALU_CMP | ALU_CMP_SE | ALU_CMPS | ALU_SCAS | ALU_NEG =>
if w='1' then -- 16 bits
overflow_s <= cbus_s(16) xor cbus_s(15);
else
overflow_s <= cbus_s(8) xor cbus_s(7);
end if;
when ALU_ROL1 | ALU_RCL1 | ALU_SHL1 => -- count=1 using constants as in rcl bx,1
if (((w='1') and (alureg_s(15)/=alucout_s)) or
((w='0') and (alureg_s(7) /=alucout_s))) then
overflow_s <= '1';
else
overflow_s <= '0';
end if;
when ALU_ROL | ALU_RCL | ALU_SHL => -- cl/cx=1
if (( c1flag_s='1' and w='1' and (alureg_s(15)/=alucout_s)) or
( c1flag_s='1' and w='0' and (alureg_s(7) /=alucout_s))) then
overflow_s <= '1';
else
overflow_s <= '0';
end if;
when ALU_ROR1 | ALU_RCR1 | ALU_SHR1 | ALU_SAR1 =>
if (((w='1') and (alureg_s(15)/=alureg_s(14))) or
((w='0') and (alureg_s(7) /=alureg_s(6)))) then
overflow_s <= '1';
else
overflow_s <= '0';
end if;
when ALU_ROR | ALU_RCR | ALU_SHR | ALU_SAR => -- if cl/cx=1
if ((c1flag_s='1' and w='1' and (alureg_s(15)/=alureg_s(14))) or
(c1flag_s='1' and w='0' and (alureg_s(7) /=alureg_s(6)))) then
overflow_s <= '1';
else
overflow_s <= '0';
end if;
when ALU_MUL | ALU_MUL2 =>
if (wl_s='0') then
overflow_s <= zflaghigh_s;
else
overflow_s <= zflagdx_s; -- MSW multiply/divide result
end if;
when ALU_IMUL | ALU_IMUL2 => -- if MSbit(1)='1' & AH=FF/DX=FFFF
if ((wl_s='0' and product_s(7)='1' and hflagah_s='1') or
(wl_s='0' and product_s(7)='0' and zflagah_s='0') or
(wl_s='1' and product_s(15)='1' and hflagdx_s='1') or
(wl_s='1' and product_s(15)='0' and zflagdx_s='0')) then
overflow_s <= '0';
else
overflow_s <= '1';
end if;
when others =>
overflow_s <= OFLAG; -- Keep previous value
end case;
end process;
----------------------------------------------------------------------------
-- Zeroflag set if result=0, zflagdx_s=1 when dx/=0, zflagah_s=1 when ah/=0
----------------------------------------------------------------------------
zflaglow_s <= alubus_s(7) or alubus_s(6) or alubus_s(5) or alubus_s(4) or
alubus_s(3) or alubus_s(2) or alubus_s(1) or alubus_s(0);
zflaghigh_s <= alubus_s(15) or alubus_s(14) or alubus_s(13) or alubus_s(12) or
alubus_s(11) or alubus_s(10) or alubus_s(9) or alubus_s(8);
zeroflag_s <= not(zflaghigh_s or zflaglow_s) when w='1' else not(zflaglow_s);
zflagdx_s <= product_s(31) or product_s(30) or product_s(29) or product_s(28) or
product_s(27) or product_s(26) or product_s(25) or product_s(24) or
product_s(23) or product_s(22) or product_s(21) or product_s(20) or
product_s(19) or product_s(18) or product_s(17) or product_s(16);
zflagah_s <= product_s(15) or product_s(14) or product_s(13) or product_s(12) or
product_s(11) or product_s(10) or product_s(09) or product_s(08);
----------------------------------------------------------------------------
-- hflag set if IMUL result AH=FF or DX=FFFF
----------------------------------------------------------------------------
hflagah_s <= product_s(15) and product_s(14) and product_s(13) and product_s(12) and
product_s(11) and product_s(10) and product_s(9) and product_s(8);
hflagdx_s <= product_s(31) and product_s(30) and product_s(29) and product_s(28) and
product_s(27) and product_s(26) and product_s(25) and product_s(24) and
product_s(23) and product_s(22) and product_s(21) and product_s(20) and
product_s(19) and product_s(18) and product_s(17) and product_s(16);
----------------------------------------------------------------------------
-- Parity flag set if even number of bits in LSB
----------------------------------------------------------------------------
parityflag_s <=not(alubus_s(7) xor alubus_s(6) xor alubus_s(5) xor alubus_s(4) xor
alubus_s(3) xor alubus_s(2) xor alubus_s(1) xor alubus_s(0));
----------------------------------------------------------------------------
-- Sign flag
----------------------------------------------------------------------------
signflag_s <= alubus_s(15) when w='1' else alubus_s(7);
----------------------------------------------------------------------------
-- c1flag asserted if CL or CX=1, used to update the OF flags during
-- rotate/shift instructions
----------------------------------------------------------------------------
c1flag_s <= '1' when (cx_s=X"0001" and w='1') OR (cx_s(7 downto 0)=X"01" and w='0') else '0';
----------------------------------------------------------------------------
-- Temp/ScratchPad Register
-- alureg_s can also be used as temp storage
-- temp<=bbus;
----------------------------------------------------------------------------
process (clk, reset)
begin
if reset='1' then
alu_temp_s<= (others => '0');
elsif rising_edge(clk) then
if (wrtemp='1') then
alu_temp_s <= bbus_s;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- ALU Register used for xchg and rotate/shift instruction
-- latch Carry Out alucout_s signal
----------------------------------------------------------------------------
process (clk, reset)
begin
if reset='1' then
alureg_s <= (others => '0');
alucout_s<= '0';
wl_s <= '0';
elsif rising_edge(clk) then
if (wralu='1') then
alureg_s(31 downto 16) <= abus_s; -- alu_inbusa;
wl_s <= w; -- Latched w version
if w='1' then -- word operation
case aluopr is
when ALU_ROL | ALU_ROL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 0) & alureg_s(15);
alucout_s<= alureg_s(15);
when ALU_ROR | ALU_ROR1 => alureg_s(15 downto 0) <= alureg_s(0) & alureg_s(15 downto 1);
alucout_s<= alureg_s(0);
when ALU_RCL | ALU_RCL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 0) & alucout_s; -- shift carry in
alucout_s<= alureg_s(15);
when ALU_RCR | ALU_RCR1 => alureg_s(15 downto 0) <= alucout_s & alureg_s(15 downto 1);
alucout_s<= alureg_s(0);
when ALU_SHL | ALU_SHL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 0) & '0';
alucout_s<= alureg_s(15);
when ALU_SHR | ALU_SHR1 => alureg_s(15 downto 0) <= '0' & alureg_s(15 downto 1);
alucout_s<= alureg_s(0);
when ALU_SAR | ALU_SAR1 => alureg_s(15 downto 0) <= alureg_s(15) & alureg_s(15 downto 1);
alucout_s<= alureg_s(0);
when ALU_TEMP => alureg_s(15 downto 0) <= bbus_s;
alucout_s<= '-'; -- Don't care!
when ALU_AAM => alureg_s(15 downto 0) <= X"000A";
alucout_s<= '-'; -- Don't care!
when others => alureg_s(15 downto 0) <= bbus_s ;--alu_inbusb; -- ALU_PASSB
alucout_s<= CFLAG;
end case;
else
case aluopr is -- To aid resource sharing add MSB byte as above
when ALU_ROL | ALU_ROL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 7) & (alureg_s(6 downto 0) & alureg_s(7));
alucout_s<= alureg_s(7);
when ALU_ROR | ALU_ROR1 => alureg_s(15 downto 0) <= alureg_s(0) & alureg_s(15 downto 9) & (alureg_s(0) & alureg_s(7 downto 1));
alucout_s<= alureg_s(0);
when ALU_RCL | ALU_RCL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 7) & (alureg_s(6 downto 0) & alucout_s); -- shift carry in
alucout_s<= alureg_s(7);
-- when ALU_RCR | ALU_RCR1 => alureg_s(15 downto 0) <= alucout_s & alureg_s(15 downto 9) & (psrreg_s(0) & alureg_s(7 downto 1));
when ALU_RCR | ALU_RCR1 => alureg_s(15 downto 0) <= alucout_s & alureg_s(15 downto 9) & (alucout_s & alureg_s(7 downto 1)); -- Ver 0.82
alucout_s<= alureg_s(0);
when ALU_SHL | ALU_SHL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 7) & (alureg_s(6 downto 0) & '0');
alucout_s<= alureg_s(7);
when ALU_SHR | ALU_SHR1 => alureg_s(15 downto 0) <= '0' & alureg_s(15 downto 9) & ('0' & alureg_s(7 downto 1));
alucout_s<= alureg_s(0);
when ALU_SAR | ALU_SAR1 => alureg_s(15 downto 0) <= alureg_s(15) & alureg_s(15 downto 9)& (alureg_s(7) & alureg_s(7 downto 1));
alucout_s<= alureg_s(0);
when ALU_TEMP => alureg_s(15 downto 0) <= bbus_s;
alucout_s<= '-'; -- Don't care!
when ALU_AAM => alureg_s(15 downto 0) <= X"000A";
alucout_s<= '-'; -- Don't care!
when others => alureg_s(15 downto 0) <= bbus_s ;--alu_inbusb -- ALU_PASSB
alucout_s<= CFLAG;
end case;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- AAS Instruction 3F
----------------------------------------------------------------------------
process (alu_inbusa,psrreg_s,aas1bus_s)
begin
aas1bus_s<=alu_inbusa-X"0106";
if ((alu_inbusa(3 downto 0) > "1001") or (psrreg_s(4)='1')) then
aasbus_s <= aas1bus_s(15 downto 8)&X"0"&aas1bus_s(3 downto 0);
setaas_s <= '1'; -- Set CF and AF flag
else
aasbus_s(7 downto 0) <= X"0"&(alu_inbusa(3 downto 0)); -- AL=AL&0Fh
aasbus_s(15 downto 8)<= alu_inbusa(15 downto 8); -- leave AH unchanged
setaas_s <= '0'; -- Clear CF and AF flag
end if;
end process;
----------------------------------------------------------------------------
-- AAA Instruction 37
----------------------------------------------------------------------------
process (alu_inbusa,psrreg_s,aaa1bus_s)
begin
aaa1bus_s<=alu_inbusa+X"0106";
if ((alu_inbusa(3 downto 0) > "1001") or (psrreg_s(4)='1')) then
aaabus_s <= aaa1bus_s(15 downto 8)&X"0"&aaa1bus_s(3 downto 0);
setaaa_s <= '1'; -- Set CF and AF flag
else
aaabus_s(7 downto 0) <= X"0"&alu_inbusa(3 downto 0); -- AL=AL&0Fh
aaabus_s(15 downto 8)<= alu_inbusa(15 downto 8); -- AH Unchanged
setaaa_s <= '0'; -- Clear CF and AF flag
end if;
end process;
----------------------------------------------------------------------------
-- DAA Instruction 27
----------------------------------------------------------------------------
process (alu_inbusa,psrreg_s,setdaa_s)
begin
if ((alu_inbusa(3 downto 0) > X"9") or (psrreg_s(4)='1')) then
setdaa_s(0) <= '1'; -- set AF
else
setdaa_s(0) <= '0'; -- clr AF
end if;
if ((alu_inbusa(7 downto 0) > X"9F") or (psrreg_s(0)='1') or (alu_inbusa(7 downto 0) > X"99")) then
setdaa_s(1) <= '1'; -- set CF
else
setdaa_s(1) <= '0'; -- clr CF
end if;
case setdaa_s is
when "00" => daabus_s <= alu_inbusa(7 downto 0);
when "01" => daabus_s <= alu_inbusa(7 downto 0) + X"06";
when "10" => daabus_s <= alu_inbusa(7 downto 0) + X"60";
when others => daabus_s <= alu_inbusa(7 downto 0) + X"66";
end case;
end process;
----------------------------------------------------------------------------
-- DAS Instruction 2F
----------------------------------------------------------------------------
process (alu_inbusa,psrreg_s,setdas_s)
begin
if ((alu_inbusa(3 downto 0) > X"9") or (psrreg_s(4)='1')) then
setdas_s(0) <= '1'; -- set AF
else
setdas_s(0) <= '0'; -- clr AF
end if;
if ((alu_inbusa(7 downto 0) > X"9F") or (psrreg_s(0)='1') or (alu_inbusa(7 downto 0) > X"99")) then
setdas_s(1) <= '1'; -- set CF
else
setdas_s(1) <= '0'; -- clr CF
end if;
case setdas_s is
when "00" => dasbus_s <= alu_inbusa(7 downto 0);
when "01" => dasbus_s <= alu_inbusa(7 downto 0) - X"06";
when "10" => dasbus_s <= alu_inbusa(7 downto 0) - X"60";
when others => dasbus_s <= alu_inbusa(7 downto 0) - X"66";
end case;
end process;
----------------------------------------------------------------------------
-- AAD Instruction 5D 0A
----------------------------------------------------------------------------
process (alu_inbusa,aad1bus_s,aad2bus_s)
begin
aad1bus_s <= ("00" & alu_inbusa(15 downto 8) & '0') + (alu_inbusa(15 downto 8) & "000"); -- AH*2 + AH*8
aad2bus_s <= aad1bus_s + ("000" & alu_inbusa(7 downto 0)); -- + AL
aadbus_s<= "00000000" & aad2bus_s(7 downto 0);
end process;
----------------------------------------------------------------------------
-- ALU Operation
----------------------------------------------------------------------------
process (aluopr,abus_s,bbus_s,outbus_s,psrreg_s,alureg_s,aasbus_s,aaabus_s,daabus_s,sign16a_s,
sign16b_s,sign32a_s,dasbus_s,product_s,divresult_s,alu_temp_s,aadbus_s,quotient_s,remainder_s)
begin
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_INC | ALU_POP | ALU_SUB | ALU_SUB_SE | ALU_DEC | ALU_PUSH | ALU_CMP | ALU_CMP_SE |
ALU_CMPS | ALU_ADC | ALU_ADC_SE | ALU_SBB | ALU_SBB_SE | ALU_SCAS | ALU_NEG | ALU_NOT
=> alubus_s <= outbus_s;
when ALU_OR | ALU_OR_SE
=> alubus_s <= abus_s OR bbus_s;
when ALU_AND | ALU_AND_SE | ALU_TEST0 | ALU_TEST1 | ALU_TEST2
=> alubus_s <= abus_s AND bbus_s;
when ALU_XOR | ALU_XOR_SE
=> alubus_s <= abus_s XOR bbus_s;
when ALU_LAHF => alubus_s <= psrreg_s(15 downto 2)&'1'&psrreg_s(0);-- flags onto ALUBUS, note reserved bit1=1
when ALU_MUL | ALU_IMUL
=> alubus_s <= product_s(15 downto 0); -- AX of Multiplier
when ALU_MUL2| ALU_IMUL2
=> alubus_s <= product_s(31 downto 16); -- DX of Multiplier
when ALU_DIV | ALU_IDIV
=> alubus_s <= divresult_s(15 downto 0);-- AX of Divider (quotient)
when ALU_DIV2| ALU_IDIV2
=> alubus_s <= divresult_s(31 downto 16);-- DX of Divider (remainder)
when ALU_SEXT => alubus_s <= sign16a_s; -- Used for CBW Instruction
when ALU_SEXTW => alubus_s <= sign32a_s; -- Used for CWD Instruction
when ALU_AAS => alubus_s <= aasbus_s; -- Used for AAS Instruction
when ALU_AAA => alubus_s <= aaabus_s; -- Used for AAA Instruction
when ALU_DAA => alubus_s <= abus_s(15 downto 8) & daabus_s;-- Used for DAA Instruction
when ALU_DAS => alubus_s <= abus_s(15 downto 8) & dasbus_s;-- Used for DAS Instruction
when ALU_AAD => alubus_s <= aadbus_s; -- Used for AAD Instruction
when ALU_AAM => alubus_s <= quotient_s(7 downto 0) & remainder_s(7 downto 0); -- Used for AAM Instruction
when ALU_ROL | ALU_ROL1 | ALU_ROR | ALU_ROR1 | ALU_RCL | ALU_RCL1 | ALU_RCR | ALU_RCR1 |
ALU_SHL | ALU_SHL1 | ALU_SHR | ALU_SHR1 | ALU_SAR | ALU_SAR1 | ALU_REGL
=> alubus_s <= alureg_s(15 downto 0); -- alu_inbusb to output
when ALU_REGH => alubus_s <= alureg_s(31 downto 16); -- alu_inbusa to output
when ALU_PASSA => alubus_s <= abus_s;
--when ALU_PASSB => alubus_s <= bbus_s;
when ALU_TEMP => alubus_s <= alu_temp_s;
when others => alubus_s <= DONTCARE(15 downto 0);
end case;
end process;
alubus <= alubus_s; -- Connect to entity
----------------------------------------------------------------------------
-- Processor Status Register (Flags)
-- bit Flag
-- 15 Reserved
-- 14 Reserved
-- 13 Reserved Set to 1?
-- 12 Reserved Set to 1?
-- 11 Overflow Flag OF
-- 10 Direction Flag DF
-- 9 Interrupt Flag IF
-- 8 Trace Flag TF
-- 7 Sign Flag SF
-- 6 Zero Flag ZF
-- 5 Reserved
-- 4 Auxiliary Carry AF
-- 3 Reserved
-- 2 Parity Flag PF
-- 1 Reserved Set to 1 ????
-- 0 Carry Flag
----------------------------------------------------------------------------
process (clk, reset)
begin
if reset='1' then
psrreg_s <= "1111000000000010";
elsif rising_edge(clk) then
if (wrcc='1') then
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_ADC | ALU_ADC_SE | ALU_INC =>
OFLAG <= overflow_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
AFLAG <= bit4_s;
PFLAG <= parityflag_s;
CFLAG <= cout_s;
when ALU_DEC => -- Same as for ALU_SUB exclusing the CFLAG :-(
OFLAG <= overflow_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
AFLAG <= not bit4_s;
PFLAG <= parityflag_s;
when ALU_SUB | ALU_SUB_SE | ALU_SBB | ALU_SBB_SE | ALU_CMP |
ALU_CMP_SE | ALU_CMPS | ALU_SCAS | ALU_NEG =>
OFLAG <= overflow_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
AFLAG <= not bit4_s;
PFLAG <= parityflag_s;
CFLAG <= not cout_s;
when ALU_OR | ALU_OR_SE | ALU_AND | ALU_AND_SE | ALU_XOR | ALU_XOR_SE | ALU_TEST0 | ALU_TEST1 | ALU_TEST2 =>
OFLAG <= '0';
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
AFLAG <= '0'; -- None defined, set to 0 to be compatible with debug
PFLAG <= parityflag_s;
CFLAG <= '0';
when ALU_SHL | ALU_SHR | ALU_SAR |
ALU_SHR1 | ALU_SAR1 | ALU_SHL1 =>
OFLAG <= overflow_s;
PFLAG <= parityflag_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
CFLAG <= alucout_s;
when ALU_CLC =>
CFLAG <= '0';
when ALU_CMC =>
CFLAG <= not CFLAG;
when ALU_STC =>
CFLAG <= '1';
when ALU_CLD =>
DFLAG <= '0';
when ALU_STD =>
DFLAG <= '1';
when ALU_CLI =>
IFLAG <= '0';
when ALU_STI =>
IFLAG <= '1';
when ALU_POP => -- Note only POPF executes a WRCC command, thus save for other pops
psrreg_s <= "1111" & alu_inbusa(11 downto 0);
when ALU_SAHF => -- Write all AH bits (not compatible!)
psrreg_s(7 downto 0) <= alu_inbusa(7 downto 6) & '0' & alu_inbusa(4) & '0' &
alu_inbusa(2) & '0' & alu_inbusa(0);-- SAHF only writes bits 7,6,4,2,0
when ALU_AAS =>
AFLAG <= setaas_s; -- set or clear CF/AF flag
CFLAG <= setaas_s;
SFLAG <= '0';
when ALU_AAA =>
AFLAG <= setaaa_s; -- set or clear CF/AF flag
CFLAG <= setaaa_s;
when ALU_DAA =>
AFLAG <= setdaa_s(0); -- set or clear CF/AF flag
CFLAG <= setdaa_s(1);
PFLAG <= parityflag_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
when ALU_AAD =>
SFLAG <= alubus_s(7); --signflag_s;
PFLAG <= parityflag_s;
ZFLAG <= zeroflag_s;
when ALU_AAM =>
SFLAG <= signflag_s;
PFLAG <= parityflag_s;
ZFLAG <= not(zflaglow_s); -- signflag on AL only
when ALU_DAS =>
AFLAG <= setdas_s(0); -- set or clear CF/AF flag
CFLAG <= setdas_s(1);
PFLAG <= parityflag_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
-- Shift Rotate Instructions
when ALU_ROL | ALU_ROR | ALU_RCL | ALU_RCR |
ALU_ROL1 | ALU_RCL1 | ALU_ROR1 | ALU_RCR1 =>
CFLAG <= alucout_s;
OFLAG <= overflow_s;
when ALU_MUL | ALU_MUL2 | ALU_IMUL | ALU_IMUL2 => -- Multiply affects CF&OF only
CFLAG <= overflow_s;
OFLAG <= overflow_s;
when ALU_CLRTIF => -- Clear TF and IF flag
IFLAG <= '0';
TFLAG <= '0';
when others =>
psrreg_s <= psrreg_s;
end case;
end if;
end if;
end process;
ccbus <= psrreg_s; -- Connect to entity
-- Latch Divide by 0 error flag & latched divresult.
-- Requires a MCP from all registers to these endpoint registers!
process (clk, reset)
begin
if reset='1' then
div_err <= '0';
divresult_s <= (others => '0');
elsif rising_edge(clk) then
if done_s='1' then -- Latched pulse generated by serial divider
div_err <= div_err_s; -- Divide Overflow
-- pragma synthesis_off
assert div_err_s='0' report "**** Divide Overflow ***" severity note;
-- pragma synthesis_on
if wl_s='1' then -- Latched version required?
divresult_s <= remainder_s & quotient_s;
else
divresult_s <= remainder_s & remainder_s(7 downto 0) & quotient_s(7 downto 0);
end if;
else
div_err <= '0';
end if;
end if;
end process;
end rtl;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- Ver 0.82 Fixed RCR X,CL --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE work.cpu86pack.ALL;
ENTITY ALU IS
PORT(
alu_inbusa : IN std_logic_vector (15 DOWNTO 0);
alu_inbusb : IN std_logic_vector (15 DOWNTO 0);
aluopr : IN std_logic_vector (6 DOWNTO 0);
ax_s : IN std_logic_vector (15 DOWNTO 0);
clk : IN std_logic;
cx_s : IN std_logic_vector (15 DOWNTO 0);
dx_s : IN std_logic_vector (15 DOWNTO 0);
reset : IN std_logic;
w : IN std_logic;
wralu : IN std_logic;
wrcc : IN std_logic;
wrtemp : IN std_logic;
alubus : OUT std_logic_vector (15 DOWNTO 0);
ccbus : OUT std_logic_vector (15 DOWNTO 0);
div_err : OUT std_logic
);
END ALU ;
architecture rtl of alu is
component divider is -- Generic Divider
generic(
WIDTH_DIVID : Integer := 32; -- Width Dividend
WIDTH_DIVIS : Integer := 16; -- Width Divisor
WIDTH_SHORT : Integer := 8); -- Check Overflow against short Byte/Word
port(
clk : in std_logic; -- System Clock, not used in this architecture
reset : in std_logic; -- Active high, not used in this architecture
dividend : in std_logic_vector (WIDTH_DIVID-1 DOWNTO 0);
divisor : in std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0);
quotient : out std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0); -- changed to 16 bits!! (S not D)
remainder : out std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0);
twocomp : in std_logic; -- '1' = 2's Complement, '0' = Unsigned
w : in std_logic; -- '0'=byte, '1'=word (cpu processor)
overflow : out std_logic; -- '1' if div by 0 or overflow
start : in std_logic; -- not used in this architecture
done : out std_logic); -- not used in this architecture
end component divider;
component multiplier is -- Generic Multiplier
generic (WIDTH : integer := 16);
port (multiplicant : in std_logic_vector (WIDTH-1 downto 0);
multiplier : in std_logic_vector (WIDTH-1 downto 0);
product : out std_logic_vector (WIDTH+WIDTH-1 downto 0);-- result
twocomp : in std_logic);
end component multiplier;
signal product_s : std_logic_vector(31 downto 0); -- result multiplier
signal dividend_s : std_logic_vector(31 downto 0); -- Input divider
signal remainder_s : std_logic_vector(15 downto 0); -- Divider result
signal quotient_s : std_logic_vector(15 downto 0); -- Divider result
signal divresult_s : std_logic_vector(31 DOWNTO 0); -- Output divider to alubus
signal div_err_s : std_logic; -- Divide by 0
signal twocomp_s : std_logic; -- Sign Extend for IMUL and IDIV
signal wl_s : std_logic; -- Latched w signal, used for muliplier/divider
signal alubus_s : std_logic_vector (15 DOWNTO 0);
signal abus_s : std_logic_vector(15 downto 0);
signal bbus_s : std_logic_vector(15 downto 0);
signal dxbus_s : std_logic_vector(15 downto 0); -- DX register
signal addbbus_s : std_logic_vector(15 downto 0); -- bbus connected to full adder
signal cbus_s : std_logic_vector(16 downto 0); -- Carry Bus
signal outbus_s : std_logic_vector(15 downto 0); -- outbus=abus+bbus
signal sign16a_s : std_logic_vector(15 downto 0); -- sign extended alu_busa(7 downto 0)
signal sign16b_s : std_logic_vector(15 downto 0); -- sign extended alu_busb(7 downto 0)
signal sign32a_s : std_logic_vector(15 downto 0); -- 16 bits alu_busa(15) vector (CWD)
signal aasbus_s : std_logic_vector(15 downto 0); -- used for AAS instruction
signal aas1bus_s : std_logic_vector(15 downto 0);
signal daabus_s : std_logic_vector(7 downto 0); -- used for DAA instruction
signal dasbus_s : std_logic_vector(7 downto 0); -- used for DAS instruction
signal aaabus_s : std_logic_vector(15 downto 0); -- used for AAA instruction
signal aaa1bus_s : std_logic_vector(15 downto 0);
signal aadbus_s : std_logic_vector(15 downto 0); -- used for AAD instruction
signal aad1bus_s : std_logic_vector(10 downto 0);
signal aad2bus_s : std_logic_vector(10 downto 0);
signal setaas_s : std_logic; -- '1' set CF & AF else both 0
signal setaaa_s : std_logic; -- '1' set CF & AF else both 0
signal setdaa_s : std_logic_vector(1 downto 0); -- "11" set CF & AF
signal setdas_s : std_logic_vector(1 downto 0); -- "11" set CF & AF
signal bit4_s : std_logic; -- used for AF flag
signal cout_s : std_logic;
signal psrreg_s : std_logic_vector(15 downto 0); -- 16 bits flag register
signal zflaglow_s : std_logic; -- low byte zero flag (w=0)
signal zflaghigh_s : std_logic; -- high byte zero flag (w=1)
signal zeroflag_s : std_logic; -- zero flag, asserted when zero
signal c1flag_s : std_logic; -- Asserted when CX=1(w=1) or CL=1(w=0)
signal zflagdx_s : std_logic; -- Result (DX) zero flag, asserted when not zero (used for mul/imul)
signal zflagah_s : std_logic; -- '1' if IMUL(15..8)/=0
signal hflagah_s : std_logic; -- Used for IMUL
signal hflagdx_s : std_logic; -- Used for IMUL
signal overflow_s : std_logic;
signal parityflag_s: std_logic;
signal signflag_s : std_logic;
alias OFLAG : std_logic is psrreg_s(11);
alias DFLAG : std_logic is psrreg_s(10);
alias IFLAG : std_logic is psrreg_s(9);
alias TFLAG : std_logic is psrreg_s(8);
alias SFLAG : std_logic is psrreg_s(7);
alias ZFLAG : std_logic is psrreg_s(6);
alias AFLAG : std_logic is psrreg_s(4);
alias PFLAG : std_logic is psrreg_s(2);
alias CFLAG : std_logic is psrreg_s(0);
signal alureg_s : std_logic_vector(31 downto 0); -- 31 bits temp register for alu_inbusa & alu_inbusb
signal alucout_s : std_logic; -- ALUREG Carry Out signal
signal alu_temp_s : std_logic_vector(15 downto 0); -- Temp/scratchpad register, use ALU_TEMP to select
signal done_s : std_logic; -- Serial divider conversion done
signal startdiv_s : std_logic; -- Serial divider start pulse
begin
ALUU1 : divider
generic map (WIDTH_DIVID => 32, WIDTH_DIVIS => 16, WIDTH_SHORT => 8)
port map (clk => clk,
reset => reset,
dividend => dividend_s, -- DX:AX
divisor => alureg_s(15 downto 0), -- 0&byte/word
--divisor => bbus_s, -- byte/word
quotient => quotient_s, -- 16 bits
remainder => remainder_s, -- 16 bits
twocomp => twocomp_s,
w => wl_s, -- Byte/Word
overflow => div_err_s, -- Divider Overflow. generate int0
start => startdiv_s, -- start conversion, generated by proc
done => done_s); -- conversion done, latch results
ALUU2 : multiplier
generic map (WIDTH => 16) -- Result is 2*WIDTH bits
port map (multiplicant=> alureg_s(31 downto 16),
multiplier => alureg_s(15 downto 0),
product => product_s, -- 32 bits!
twocomp => twocomp_s);
dividend_s <= X"000000"&alureg_s(23 downto 16) when aluopr=ALU_AAM else dxbus_s & alureg_s(31 downto 16);-- DX is sign extended for byte IDIV
-- start serial divider 1 cycle after wralu pulse received. The reason is that the dividend is loaded into the
-- accumulator thus the data must be valid when this happens.
process (clk, reset)
begin
if reset='1' then
startdiv_s <= '0';
elsif rising_edge(clk) then
if (wralu='1' and (aluopr=ALU_DIV or aluopr=ALU_IDIV OR aluopr=ALU_AAM)) then
startdiv_s <= '1';
else
startdiv_s <= '0';
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Create Full adder
----------------------------------------------------------------------------
fulladd: for bit_nr in 0 to 15 generate
outbus_s(bit_nr) <= abus_s(bit_nr) xor addbbus_s(bit_nr) xor cbus_s(bit_nr);
cbus_s(bit_nr+1) <= (abus_s(bit_nr) and addbbus_s(bit_nr)) or
(abus_s(bit_nr) and cbus_s(bit_nr)) or
(addbbus_s(bit_nr) and cbus_s(bit_nr));
end generate fulladd;
bit4_s <= cbus_s(4);
sign16a_s <= alu_inbusa(7) &alu_inbusa(7) &alu_inbusa(7) &alu_inbusa(7)&alu_inbusa(7)&
alu_inbusa(7) &alu_inbusa(7) &alu_inbusa(7) &alu_inbusa(7 downto 0);
sign16b_s <= alu_inbusb(7) &alu_inbusb(7) &alu_inbusb(7) &alu_inbusb(7)&alu_inbusb(7)&
alu_inbusb(7) &alu_inbusb(7) &alu_inbusb(7) &alu_inbusb(7 downto 0);
sign32a_s <= alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&
alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&
alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&
alu_inbusa(15);
-- Invert bus for subtract instructions
addbbus_s <= not bbus_s when ((aluopr=ALU_CMP) or (aluopr=ALU_CMP_SE) or (aluopr=ALU_CMPS) or (aluopr=ALU_DEC)
or (aluopr=ALU_SBB) or (aluopr=ALU_SBB_SE) or (aluopr=ALU_PUSH) or (aluopr=ALU_SUB)
or (aluopr=ALU_SUB_SE) or (aluopr=ALU_SCAS)) else bbus_s;
-- sign extend for IDIV and IMUL instructions
twocomp_s <= '1' when ((aluopr=ALU_IDIV) or (aluopr=ALU_IMUL) or
(aluopr=ALU_IDIV2)or (aluopr=ALU_IMUL2)) else '0';
----------------------------------------------------------------------------
-- Sign Extend Logic abus & bbus & dxbus
----------------------------------------------------------------------------
process (w, alu_inbusa, alu_inbusb, sign16a_s, sign16b_s, aluopr, ax_s, alureg_s)
begin
if (w='1') then -- Word, no sign extend, unless signextend is specified
case aluopr is
when ALU_CMPS =>
abus_s <= alu_inbusa; -- no sign extend
bbus_s <= alureg_s(15 downto 0); -- previous read ES:[DI]
when ALU_NEG | ALU_NOT =>
abus_s <= not(alu_inbusa); -- NEG instruction, not(operand)+1
bbus_s <= alu_inbusb; -- 0001 (0000 for NOT)
when ALU_ADD_SE | ALU_ADC_SE | ALU_SBB_SE | ALU_SUB_SE | ALU_CMP_SE |
ALU_OR_SE | ALU_AND_SE | ALU_XOR_SE=>
abus_s <= alu_inbusa; -- no sign extend
bbus_s <= sign16b_s; -- Sign extend on 8 bits immediate values (see O80I2RM)
when others =>
abus_s <= alu_inbusa; -- no sign extend
bbus_s <= alu_inbusb;
end case;
else
case aluopr is
when ALU_CMPS =>
abus_s <= alu_inbusa;
bbus_s <= alureg_s(15 downto 0);
when ALU_DIV | ALU_DIV2 =>
abus_s <= ax_s;
bbus_s <= alu_inbusb;
when ALU_IDIV| ALU_IDIV2 =>
abus_s <= ax_s;
bbus_s <= sign16b_s;
when ALU_MUL | ALU_MUL2 | ALU_SCAS =>
abus_s <= alu_inbusa;
bbus_s <= alu_inbusb;
when ALU_NEG | ALU_NOT =>
abus_s <= not(alu_inbusa); -- NEG instruction, not(operand)+1
bbus_s <= alu_inbusb; -- 0001 (0000 for NOT)
when others =>
abus_s <= sign16a_s;
bbus_s <= sign16b_s;
end case;
end if;
end process;
process (wl_s, aluopr, dx_s, alu_inbusa) -- dxbus for DIV/IDIV only
begin
if (wl_s='1') then -- Word, no sign extend
dxbus_s <= dx_s;
else -- Byte
if (((aluopr=ALU_IDIV) or (aluopr=ALU_IDIV2)) and (alu_inbusa(15)='1')) then -- signed DX<-SE(AX)/bbus<-SE(byte)
dxbus_s <= X"FFFF"; -- DX=FFFF (ignored for mul)
else
dxbus_s <= X"0000"; -- DX=0000 (ignored for mul)
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Carry In logic
----------------------------------------------------------------------------
process (aluopr, psrreg_s)
begin
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_INC | ALU_POP | ALU_NEG | ALU_NOT
=> cbus_s(0) <= '0';
when ALU_SBB | ALU_SBB_SE
=> cbus_s(0) <= not CFLAG;
when ALU_SUB | ALU_SUB_SE | ALU_DEC | ALU_PUSH | ALU_CMP | ALU_CMP_SE
| ALU_CMPS | ALU_SCAS
=> cbus_s(0) <= '1';
when others => cbus_s(0) <= CFLAG; -- ALU_ADC, ALU_SUB, ALU_SBB
end case;
end process;
----------------------------------------------------------------------------
-- Carry Out logic
-- cout is inverted for ALU_SUB and ALU_SBB before written to psrreg_s
----------------------------------------------------------------------------
process (aluopr, w, psrreg_s, cbus_s, alu_inbusa)
begin
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_ADC | ALU_ADC_SE | ALU_SUB | ALU_SUB_SE | ALU_SBB | ALU_SBB_SE |
ALU_CMP | ALU_CMP_SE | ALU_CMPS| ALU_SCAS =>
if (w='1') then cout_s <= cbus_s(16);
else cout_s <= cbus_s(8);
end if;
when ALU_NEG => -- CF=0 if operand=0, else 1
if (alu_inbusa=X"0000") then
cout_s <= '1'; -- Note CFLAG=NOT(cout_s)
else
cout_s <= '0'; -- Note CFLAG=NOT(cout_s)
end if;
when others =>
cout_s <= CFLAG; -- Keep previous value
end case;
end process;
----------------------------------------------------------------------------
-- Overflow Logic
----------------------------------------------------------------------------
process (aluopr, w, psrreg_s, cbus_s, alureg_s, alucout_s, zflaghigh_s, zflagdx_s,hflagdx_s,zflagah_s,
hflagah_s, wl_s, product_s, c1flag_s)
begin
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_ADC | ALU_ADC_SE | ALU_INC | ALU_DEC | ALU_SUB | ALU_SUB_SE |
ALU_SBB | ALU_SBB_SE | ALU_CMP | ALU_CMP_SE | ALU_CMPS | ALU_SCAS | ALU_NEG =>
if w='1' then -- 16 bits
overflow_s <= cbus_s(16) xor cbus_s(15);
else
overflow_s <= cbus_s(8) xor cbus_s(7);
end if;
when ALU_ROL1 | ALU_RCL1 | ALU_SHL1 => -- count=1 using constants as in rcl bx,1
if (((w='1') and (alureg_s(15)/=alucout_s)) or
((w='0') and (alureg_s(7) /=alucout_s))) then
overflow_s <= '1';
else
overflow_s <= '0';
end if;
when ALU_ROL | ALU_RCL | ALU_SHL => -- cl/cx=1
if (( c1flag_s='1' and w='1' and (alureg_s(15)/=alucout_s)) or
( c1flag_s='1' and w='0' and (alureg_s(7) /=alucout_s))) then
overflow_s <= '1';
else
overflow_s <= '0';
end if;
when ALU_ROR1 | ALU_RCR1 | ALU_SHR1 | ALU_SAR1 =>
if (((w='1') and (alureg_s(15)/=alureg_s(14))) or
((w='0') and (alureg_s(7) /=alureg_s(6)))) then
overflow_s <= '1';
else
overflow_s <= '0';
end if;
when ALU_ROR | ALU_RCR | ALU_SHR | ALU_SAR => -- if cl/cx=1
if ((c1flag_s='1' and w='1' and (alureg_s(15)/=alureg_s(14))) or
(c1flag_s='1' and w='0' and (alureg_s(7) /=alureg_s(6)))) then
overflow_s <= '1';
else
overflow_s <= '0';
end if;
when ALU_MUL | ALU_MUL2 =>
if (wl_s='0') then
overflow_s <= zflaghigh_s;
else
overflow_s <= zflagdx_s; -- MSW multiply/divide result
end if;
when ALU_IMUL | ALU_IMUL2 => -- if MSbit(1)='1' & AH=FF/DX=FFFF
if ((wl_s='0' and product_s(7)='1' and hflagah_s='1') or
(wl_s='0' and product_s(7)='0' and zflagah_s='0') or
(wl_s='1' and product_s(15)='1' and hflagdx_s='1') or
(wl_s='1' and product_s(15)='0' and zflagdx_s='0')) then
overflow_s <= '0';
else
overflow_s <= '1';
end if;
when others =>
overflow_s <= OFLAG; -- Keep previous value
end case;
end process;
----------------------------------------------------------------------------
-- Zeroflag set if result=0, zflagdx_s=1 when dx/=0, zflagah_s=1 when ah/=0
----------------------------------------------------------------------------
zflaglow_s <= alubus_s(7) or alubus_s(6) or alubus_s(5) or alubus_s(4) or
alubus_s(3) or alubus_s(2) or alubus_s(1) or alubus_s(0);
zflaghigh_s <= alubus_s(15) or alubus_s(14) or alubus_s(13) or alubus_s(12) or
alubus_s(11) or alubus_s(10) or alubus_s(9) or alubus_s(8);
zeroflag_s <= not(zflaghigh_s or zflaglow_s) when w='1' else not(zflaglow_s);
zflagdx_s <= product_s(31) or product_s(30) or product_s(29) or product_s(28) or
product_s(27) or product_s(26) or product_s(25) or product_s(24) or
product_s(23) or product_s(22) or product_s(21) or product_s(20) or
product_s(19) or product_s(18) or product_s(17) or product_s(16);
zflagah_s <= product_s(15) or product_s(14) or product_s(13) or product_s(12) or
product_s(11) or product_s(10) or product_s(09) or product_s(08);
----------------------------------------------------------------------------
-- hflag set if IMUL result AH=FF or DX=FFFF
----------------------------------------------------------------------------
hflagah_s <= product_s(15) and product_s(14) and product_s(13) and product_s(12) and
product_s(11) and product_s(10) and product_s(9) and product_s(8);
hflagdx_s <= product_s(31) and product_s(30) and product_s(29) and product_s(28) and
product_s(27) and product_s(26) and product_s(25) and product_s(24) and
product_s(23) and product_s(22) and product_s(21) and product_s(20) and
product_s(19) and product_s(18) and product_s(17) and product_s(16);
----------------------------------------------------------------------------
-- Parity flag set if even number of bits in LSB
----------------------------------------------------------------------------
parityflag_s <=not(alubus_s(7) xor alubus_s(6) xor alubus_s(5) xor alubus_s(4) xor
alubus_s(3) xor alubus_s(2) xor alubus_s(1) xor alubus_s(0));
----------------------------------------------------------------------------
-- Sign flag
----------------------------------------------------------------------------
signflag_s <= alubus_s(15) when w='1' else alubus_s(7);
----------------------------------------------------------------------------
-- c1flag asserted if CL or CX=1, used to update the OF flags during
-- rotate/shift instructions
----------------------------------------------------------------------------
c1flag_s <= '1' when (cx_s=X"0001" and w='1') OR (cx_s(7 downto 0)=X"01" and w='0') else '0';
----------------------------------------------------------------------------
-- Temp/ScratchPad Register
-- alureg_s can also be used as temp storage
-- temp<=bbus;
----------------------------------------------------------------------------
process (clk, reset)
begin
if reset='1' then
alu_temp_s<= (others => '0');
elsif rising_edge(clk) then
if (wrtemp='1') then
alu_temp_s <= bbus_s;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- ALU Register used for xchg and rotate/shift instruction
-- latch Carry Out alucout_s signal
----------------------------------------------------------------------------
process (clk, reset)
begin
if reset='1' then
alureg_s <= (others => '0');
alucout_s<= '0';
wl_s <= '0';
elsif rising_edge(clk) then
if (wralu='1') then
alureg_s(31 downto 16) <= abus_s; -- alu_inbusa;
wl_s <= w; -- Latched w version
if w='1' then -- word operation
case aluopr is
when ALU_ROL | ALU_ROL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 0) & alureg_s(15);
alucout_s<= alureg_s(15);
when ALU_ROR | ALU_ROR1 => alureg_s(15 downto 0) <= alureg_s(0) & alureg_s(15 downto 1);
alucout_s<= alureg_s(0);
when ALU_RCL | ALU_RCL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 0) & alucout_s; -- shift carry in
alucout_s<= alureg_s(15);
when ALU_RCR | ALU_RCR1 => alureg_s(15 downto 0) <= alucout_s & alureg_s(15 downto 1);
alucout_s<= alureg_s(0);
when ALU_SHL | ALU_SHL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 0) & '0';
alucout_s<= alureg_s(15);
when ALU_SHR | ALU_SHR1 => alureg_s(15 downto 0) <= '0' & alureg_s(15 downto 1);
alucout_s<= alureg_s(0);
when ALU_SAR | ALU_SAR1 => alureg_s(15 downto 0) <= alureg_s(15) & alureg_s(15 downto 1);
alucout_s<= alureg_s(0);
when ALU_TEMP => alureg_s(15 downto 0) <= bbus_s;
alucout_s<= '-'; -- Don't care!
when ALU_AAM => alureg_s(15 downto 0) <= X"000A";
alucout_s<= '-'; -- Don't care!
when others => alureg_s(15 downto 0) <= bbus_s ;--alu_inbusb; -- ALU_PASSB
alucout_s<= CFLAG;
end case;
else
case aluopr is -- To aid resource sharing add MSB byte as above
when ALU_ROL | ALU_ROL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 7) & (alureg_s(6 downto 0) & alureg_s(7));
alucout_s<= alureg_s(7);
when ALU_ROR | ALU_ROR1 => alureg_s(15 downto 0) <= alureg_s(0) & alureg_s(15 downto 9) & (alureg_s(0) & alureg_s(7 downto 1));
alucout_s<= alureg_s(0);
when ALU_RCL | ALU_RCL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 7) & (alureg_s(6 downto 0) & alucout_s); -- shift carry in
alucout_s<= alureg_s(7);
-- when ALU_RCR | ALU_RCR1 => alureg_s(15 downto 0) <= alucout_s & alureg_s(15 downto 9) & (psrreg_s(0) & alureg_s(7 downto 1));
when ALU_RCR | ALU_RCR1 => alureg_s(15 downto 0) <= alucout_s & alureg_s(15 downto 9) & (alucout_s & alureg_s(7 downto 1)); -- Ver 0.82
alucout_s<= alureg_s(0);
when ALU_SHL | ALU_SHL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 7) & (alureg_s(6 downto 0) & '0');
alucout_s<= alureg_s(7);
when ALU_SHR | ALU_SHR1 => alureg_s(15 downto 0) <= '0' & alureg_s(15 downto 9) & ('0' & alureg_s(7 downto 1));
alucout_s<= alureg_s(0);
when ALU_SAR | ALU_SAR1 => alureg_s(15 downto 0) <= alureg_s(15) & alureg_s(15 downto 9)& (alureg_s(7) & alureg_s(7 downto 1));
alucout_s<= alureg_s(0);
when ALU_TEMP => alureg_s(15 downto 0) <= bbus_s;
alucout_s<= '-'; -- Don't care!
when ALU_AAM => alureg_s(15 downto 0) <= X"000A";
alucout_s<= '-'; -- Don't care!
when others => alureg_s(15 downto 0) <= bbus_s ;--alu_inbusb -- ALU_PASSB
alucout_s<= CFLAG;
end case;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- AAS Instruction 3F
----------------------------------------------------------------------------
process (alu_inbusa,psrreg_s,aas1bus_s)
begin
aas1bus_s<=alu_inbusa-X"0106";
if ((alu_inbusa(3 downto 0) > "1001") or (psrreg_s(4)='1')) then
aasbus_s <= aas1bus_s(15 downto 8)&X"0"&aas1bus_s(3 downto 0);
setaas_s <= '1'; -- Set CF and AF flag
else
aasbus_s(7 downto 0) <= X"0"&(alu_inbusa(3 downto 0)); -- AL=AL&0Fh
aasbus_s(15 downto 8)<= alu_inbusa(15 downto 8); -- leave AH unchanged
setaas_s <= '0'; -- Clear CF and AF flag
end if;
end process;
----------------------------------------------------------------------------
-- AAA Instruction 37
----------------------------------------------------------------------------
process (alu_inbusa,psrreg_s,aaa1bus_s)
begin
aaa1bus_s<=alu_inbusa+X"0106";
if ((alu_inbusa(3 downto 0) > "1001") or (psrreg_s(4)='1')) then
aaabus_s <= aaa1bus_s(15 downto 8)&X"0"&aaa1bus_s(3 downto 0);
setaaa_s <= '1'; -- Set CF and AF flag
else
aaabus_s(7 downto 0) <= X"0"&alu_inbusa(3 downto 0); -- AL=AL&0Fh
aaabus_s(15 downto 8)<= alu_inbusa(15 downto 8); -- AH Unchanged
setaaa_s <= '0'; -- Clear CF and AF flag
end if;
end process;
----------------------------------------------------------------------------
-- DAA Instruction 27
----------------------------------------------------------------------------
process (alu_inbusa,psrreg_s,setdaa_s)
begin
if ((alu_inbusa(3 downto 0) > X"9") or (psrreg_s(4)='1')) then
setdaa_s(0) <= '1'; -- set AF
else
setdaa_s(0) <= '0'; -- clr AF
end if;
if ((alu_inbusa(7 downto 0) > X"9F") or (psrreg_s(0)='1') or (alu_inbusa(7 downto 0) > X"99")) then
setdaa_s(1) <= '1'; -- set CF
else
setdaa_s(1) <= '0'; -- clr CF
end if;
case setdaa_s is
when "00" => daabus_s <= alu_inbusa(7 downto 0);
when "01" => daabus_s <= alu_inbusa(7 downto 0) + X"06";
when "10" => daabus_s <= alu_inbusa(7 downto 0) + X"60";
when others => daabus_s <= alu_inbusa(7 downto 0) + X"66";
end case;
end process;
----------------------------------------------------------------------------
-- DAS Instruction 2F
----------------------------------------------------------------------------
process (alu_inbusa,psrreg_s,setdas_s)
begin
if ((alu_inbusa(3 downto 0) > X"9") or (psrreg_s(4)='1')) then
setdas_s(0) <= '1'; -- set AF
else
setdas_s(0) <= '0'; -- clr AF
end if;
if ((alu_inbusa(7 downto 0) > X"9F") or (psrreg_s(0)='1') or (alu_inbusa(7 downto 0) > X"99")) then
setdas_s(1) <= '1'; -- set CF
else
setdas_s(1) <= '0'; -- clr CF
end if;
case setdas_s is
when "00" => dasbus_s <= alu_inbusa(7 downto 0);
when "01" => dasbus_s <= alu_inbusa(7 downto 0) - X"06";
when "10" => dasbus_s <= alu_inbusa(7 downto 0) - X"60";
when others => dasbus_s <= alu_inbusa(7 downto 0) - X"66";
end case;
end process;
----------------------------------------------------------------------------
-- AAD Instruction 5D 0A
----------------------------------------------------------------------------
process (alu_inbusa,aad1bus_s,aad2bus_s)
begin
aad1bus_s <= ("00" & alu_inbusa(15 downto 8) & '0') + (alu_inbusa(15 downto 8) & "000"); -- AH*2 + AH*8
aad2bus_s <= aad1bus_s + ("000" & alu_inbusa(7 downto 0)); -- + AL
aadbus_s<= "00000000" & aad2bus_s(7 downto 0);
end process;
----------------------------------------------------------------------------
-- ALU Operation
----------------------------------------------------------------------------
process (aluopr,abus_s,bbus_s,outbus_s,psrreg_s,alureg_s,aasbus_s,aaabus_s,daabus_s,sign16a_s,
sign16b_s,sign32a_s,dasbus_s,product_s,divresult_s,alu_temp_s,aadbus_s,quotient_s,remainder_s)
begin
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_INC | ALU_POP | ALU_SUB | ALU_SUB_SE | ALU_DEC | ALU_PUSH | ALU_CMP | ALU_CMP_SE |
ALU_CMPS | ALU_ADC | ALU_ADC_SE | ALU_SBB | ALU_SBB_SE | ALU_SCAS | ALU_NEG | ALU_NOT
=> alubus_s <= outbus_s;
when ALU_OR | ALU_OR_SE
=> alubus_s <= abus_s OR bbus_s;
when ALU_AND | ALU_AND_SE | ALU_TEST0 | ALU_TEST1 | ALU_TEST2
=> alubus_s <= abus_s AND bbus_s;
when ALU_XOR | ALU_XOR_SE
=> alubus_s <= abus_s XOR bbus_s;
when ALU_LAHF => alubus_s <= psrreg_s(15 downto 2)&'1'&psrreg_s(0);-- flags onto ALUBUS, note reserved bit1=1
when ALU_MUL | ALU_IMUL
=> alubus_s <= product_s(15 downto 0); -- AX of Multiplier
when ALU_MUL2| ALU_IMUL2
=> alubus_s <= product_s(31 downto 16); -- DX of Multiplier
when ALU_DIV | ALU_IDIV
=> alubus_s <= divresult_s(15 downto 0);-- AX of Divider (quotient)
when ALU_DIV2| ALU_IDIV2
=> alubus_s <= divresult_s(31 downto 16);-- DX of Divider (remainder)
when ALU_SEXT => alubus_s <= sign16a_s; -- Used for CBW Instruction
when ALU_SEXTW => alubus_s <= sign32a_s; -- Used for CWD Instruction
when ALU_AAS => alubus_s <= aasbus_s; -- Used for AAS Instruction
when ALU_AAA => alubus_s <= aaabus_s; -- Used for AAA Instruction
when ALU_DAA => alubus_s <= abus_s(15 downto 8) & daabus_s;-- Used for DAA Instruction
when ALU_DAS => alubus_s <= abus_s(15 downto 8) & dasbus_s;-- Used for DAS Instruction
when ALU_AAD => alubus_s <= aadbus_s; -- Used for AAD Instruction
when ALU_AAM => alubus_s <= quotient_s(7 downto 0) & remainder_s(7 downto 0); -- Used for AAM Instruction
when ALU_ROL | ALU_ROL1 | ALU_ROR | ALU_ROR1 | ALU_RCL | ALU_RCL1 | ALU_RCR | ALU_RCR1 |
ALU_SHL | ALU_SHL1 | ALU_SHR | ALU_SHR1 | ALU_SAR | ALU_SAR1 | ALU_REGL
=> alubus_s <= alureg_s(15 downto 0); -- alu_inbusb to output
when ALU_REGH => alubus_s <= alureg_s(31 downto 16); -- alu_inbusa to output
when ALU_PASSA => alubus_s <= abus_s;
--when ALU_PASSB => alubus_s <= bbus_s;
when ALU_TEMP => alubus_s <= alu_temp_s;
when others => alubus_s <= DONTCARE(15 downto 0);
end case;
end process;
alubus <= alubus_s; -- Connect to entity
----------------------------------------------------------------------------
-- Processor Status Register (Flags)
-- bit Flag
-- 15 Reserved
-- 14 Reserved
-- 13 Reserved Set to 1?
-- 12 Reserved Set to 1?
-- 11 Overflow Flag OF
-- 10 Direction Flag DF
-- 9 Interrupt Flag IF
-- 8 Trace Flag TF
-- 7 Sign Flag SF
-- 6 Zero Flag ZF
-- 5 Reserved
-- 4 Auxiliary Carry AF
-- 3 Reserved
-- 2 Parity Flag PF
-- 1 Reserved Set to 1 ????
-- 0 Carry Flag
----------------------------------------------------------------------------
process (clk, reset)
begin
if reset='1' then
psrreg_s <= "1111000000000010";
elsif rising_edge(clk) then
if (wrcc='1') then
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_ADC | ALU_ADC_SE | ALU_INC =>
OFLAG <= overflow_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
AFLAG <= bit4_s;
PFLAG <= parityflag_s;
CFLAG <= cout_s;
when ALU_DEC => -- Same as for ALU_SUB exclusing the CFLAG :-(
OFLAG <= overflow_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
AFLAG <= not bit4_s;
PFLAG <= parityflag_s;
when ALU_SUB | ALU_SUB_SE | ALU_SBB | ALU_SBB_SE | ALU_CMP |
ALU_CMP_SE | ALU_CMPS | ALU_SCAS | ALU_NEG =>
OFLAG <= overflow_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
AFLAG <= not bit4_s;
PFLAG <= parityflag_s;
CFLAG <= not cout_s;
when ALU_OR | ALU_OR_SE | ALU_AND | ALU_AND_SE | ALU_XOR | ALU_XOR_SE | ALU_TEST0 | ALU_TEST1 | ALU_TEST2 =>
OFLAG <= '0';
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
AFLAG <= '0'; -- None defined, set to 0 to be compatible with debug
PFLAG <= parityflag_s;
CFLAG <= '0';
when ALU_SHL | ALU_SHR | ALU_SAR |
ALU_SHR1 | ALU_SAR1 | ALU_SHL1 =>
OFLAG <= overflow_s;
PFLAG <= parityflag_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
CFLAG <= alucout_s;
when ALU_CLC =>
CFLAG <= '0';
when ALU_CMC =>
CFLAG <= not CFLAG;
when ALU_STC =>
CFLAG <= '1';
when ALU_CLD =>
DFLAG <= '0';
when ALU_STD =>
DFLAG <= '1';
when ALU_CLI =>
IFLAG <= '0';
when ALU_STI =>
IFLAG <= '1';
when ALU_POP => -- Note only POPF executes a WRCC command, thus save for other pops
psrreg_s <= "1111" & alu_inbusa(11 downto 0);
when ALU_SAHF => -- Write all AH bits (not compatible!)
psrreg_s(7 downto 0) <= alu_inbusa(7 downto 6) & '0' & alu_inbusa(4) & '0' &
alu_inbusa(2) & '0' & alu_inbusa(0);-- SAHF only writes bits 7,6,4,2,0
when ALU_AAS =>
AFLAG <= setaas_s; -- set or clear CF/AF flag
CFLAG <= setaas_s;
SFLAG <= '0';
when ALU_AAA =>
AFLAG <= setaaa_s; -- set or clear CF/AF flag
CFLAG <= setaaa_s;
when ALU_DAA =>
AFLAG <= setdaa_s(0); -- set or clear CF/AF flag
CFLAG <= setdaa_s(1);
PFLAG <= parityflag_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
when ALU_AAD =>
SFLAG <= alubus_s(7); --signflag_s;
PFLAG <= parityflag_s;
ZFLAG <= zeroflag_s;
when ALU_AAM =>
SFLAG <= signflag_s;
PFLAG <= parityflag_s;
ZFLAG <= not(zflaglow_s); -- signflag on AL only
when ALU_DAS =>
AFLAG <= setdas_s(0); -- set or clear CF/AF flag
CFLAG <= setdas_s(1);
PFLAG <= parityflag_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
-- Shift Rotate Instructions
when ALU_ROL | ALU_ROR | ALU_RCL | ALU_RCR |
ALU_ROL1 | ALU_RCL1 | ALU_ROR1 | ALU_RCR1 =>
CFLAG <= alucout_s;
OFLAG <= overflow_s;
when ALU_MUL | ALU_MUL2 | ALU_IMUL | ALU_IMUL2 => -- Multiply affects CF&OF only
CFLAG <= overflow_s;
OFLAG <= overflow_s;
when ALU_CLRTIF => -- Clear TF and IF flag
IFLAG <= '0';
TFLAG <= '0';
when others =>
psrreg_s <= psrreg_s;
end case;
end if;
end if;
end process;
ccbus <= psrreg_s; -- Connect to entity
-- Latch Divide by 0 error flag & latched divresult.
-- Requires a MCP from all registers to these endpoint registers!
process (clk, reset)
begin
if reset='1' then
div_err <= '0';
divresult_s <= (others => '0');
elsif rising_edge(clk) then
if done_s='1' then -- Latched pulse generated by serial divider
div_err <= div_err_s; -- Divide Overflow
-- pragma synthesis_off
assert div_err_s='0' report "**** Divide Overflow ***" severity note;
-- pragma synthesis_on
if wl_s='1' then -- Latched version required?
divresult_s <= remainder_s & quotient_s;
else
divresult_s <= remainder_s & remainder_s(7 downto 0) & quotient_s(7 downto 0);
end if;
else
div_err <= '0';
end if;
end if;
end process;
end rtl;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- Ver 0.82 Fixed RCR X,CL --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE work.cpu86pack.ALL;
ENTITY ALU IS
PORT(
alu_inbusa : IN std_logic_vector (15 DOWNTO 0);
alu_inbusb : IN std_logic_vector (15 DOWNTO 0);
aluopr : IN std_logic_vector (6 DOWNTO 0);
ax_s : IN std_logic_vector (15 DOWNTO 0);
clk : IN std_logic;
cx_s : IN std_logic_vector (15 DOWNTO 0);
dx_s : IN std_logic_vector (15 DOWNTO 0);
reset : IN std_logic;
w : IN std_logic;
wralu : IN std_logic;
wrcc : IN std_logic;
wrtemp : IN std_logic;
alubus : OUT std_logic_vector (15 DOWNTO 0);
ccbus : OUT std_logic_vector (15 DOWNTO 0);
div_err : OUT std_logic
);
END ALU ;
architecture rtl of alu is
component divider is -- Generic Divider
generic(
WIDTH_DIVID : Integer := 32; -- Width Dividend
WIDTH_DIVIS : Integer := 16; -- Width Divisor
WIDTH_SHORT : Integer := 8); -- Check Overflow against short Byte/Word
port(
clk : in std_logic; -- System Clock, not used in this architecture
reset : in std_logic; -- Active high, not used in this architecture
dividend : in std_logic_vector (WIDTH_DIVID-1 DOWNTO 0);
divisor : in std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0);
quotient : out std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0); -- changed to 16 bits!! (S not D)
remainder : out std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0);
twocomp : in std_logic; -- '1' = 2's Complement, '0' = Unsigned
w : in std_logic; -- '0'=byte, '1'=word (cpu processor)
overflow : out std_logic; -- '1' if div by 0 or overflow
start : in std_logic; -- not used in this architecture
done : out std_logic); -- not used in this architecture
end component divider;
component multiplier is -- Generic Multiplier
generic (WIDTH : integer := 16);
port (multiplicant : in std_logic_vector (WIDTH-1 downto 0);
multiplier : in std_logic_vector (WIDTH-1 downto 0);
product : out std_logic_vector (WIDTH+WIDTH-1 downto 0);-- result
twocomp : in std_logic);
end component multiplier;
signal product_s : std_logic_vector(31 downto 0); -- result multiplier
signal dividend_s : std_logic_vector(31 downto 0); -- Input divider
signal remainder_s : std_logic_vector(15 downto 0); -- Divider result
signal quotient_s : std_logic_vector(15 downto 0); -- Divider result
signal divresult_s : std_logic_vector(31 DOWNTO 0); -- Output divider to alubus
signal div_err_s : std_logic; -- Divide by 0
signal twocomp_s : std_logic; -- Sign Extend for IMUL and IDIV
signal wl_s : std_logic; -- Latched w signal, used for muliplier/divider
signal alubus_s : std_logic_vector (15 DOWNTO 0);
signal abus_s : std_logic_vector(15 downto 0);
signal bbus_s : std_logic_vector(15 downto 0);
signal dxbus_s : std_logic_vector(15 downto 0); -- DX register
signal addbbus_s : std_logic_vector(15 downto 0); -- bbus connected to full adder
signal cbus_s : std_logic_vector(16 downto 0); -- Carry Bus
signal outbus_s : std_logic_vector(15 downto 0); -- outbus=abus+bbus
signal sign16a_s : std_logic_vector(15 downto 0); -- sign extended alu_busa(7 downto 0)
signal sign16b_s : std_logic_vector(15 downto 0); -- sign extended alu_busb(7 downto 0)
signal sign32a_s : std_logic_vector(15 downto 0); -- 16 bits alu_busa(15) vector (CWD)
signal aasbus_s : std_logic_vector(15 downto 0); -- used for AAS instruction
signal aas1bus_s : std_logic_vector(15 downto 0);
signal daabus_s : std_logic_vector(7 downto 0); -- used for DAA instruction
signal dasbus_s : std_logic_vector(7 downto 0); -- used for DAS instruction
signal aaabus_s : std_logic_vector(15 downto 0); -- used for AAA instruction
signal aaa1bus_s : std_logic_vector(15 downto 0);
signal aadbus_s : std_logic_vector(15 downto 0); -- used for AAD instruction
signal aad1bus_s : std_logic_vector(10 downto 0);
signal aad2bus_s : std_logic_vector(10 downto 0);
signal setaas_s : std_logic; -- '1' set CF & AF else both 0
signal setaaa_s : std_logic; -- '1' set CF & AF else both 0
signal setdaa_s : std_logic_vector(1 downto 0); -- "11" set CF & AF
signal setdas_s : std_logic_vector(1 downto 0); -- "11" set CF & AF
signal bit4_s : std_logic; -- used for AF flag
signal cout_s : std_logic;
signal psrreg_s : std_logic_vector(15 downto 0); -- 16 bits flag register
signal zflaglow_s : std_logic; -- low byte zero flag (w=0)
signal zflaghigh_s : std_logic; -- high byte zero flag (w=1)
signal zeroflag_s : std_logic; -- zero flag, asserted when zero
signal c1flag_s : std_logic; -- Asserted when CX=1(w=1) or CL=1(w=0)
signal zflagdx_s : std_logic; -- Result (DX) zero flag, asserted when not zero (used for mul/imul)
signal zflagah_s : std_logic; -- '1' if IMUL(15..8)/=0
signal hflagah_s : std_logic; -- Used for IMUL
signal hflagdx_s : std_logic; -- Used for IMUL
signal overflow_s : std_logic;
signal parityflag_s: std_logic;
signal signflag_s : std_logic;
alias OFLAG : std_logic is psrreg_s(11);
alias DFLAG : std_logic is psrreg_s(10);
alias IFLAG : std_logic is psrreg_s(9);
alias TFLAG : std_logic is psrreg_s(8);
alias SFLAG : std_logic is psrreg_s(7);
alias ZFLAG : std_logic is psrreg_s(6);
alias AFLAG : std_logic is psrreg_s(4);
alias PFLAG : std_logic is psrreg_s(2);
alias CFLAG : std_logic is psrreg_s(0);
signal alureg_s : std_logic_vector(31 downto 0); -- 31 bits temp register for alu_inbusa & alu_inbusb
signal alucout_s : std_logic; -- ALUREG Carry Out signal
signal alu_temp_s : std_logic_vector(15 downto 0); -- Temp/scratchpad register, use ALU_TEMP to select
signal done_s : std_logic; -- Serial divider conversion done
signal startdiv_s : std_logic; -- Serial divider start pulse
begin
ALUU1 : divider
generic map (WIDTH_DIVID => 32, WIDTH_DIVIS => 16, WIDTH_SHORT => 8)
port map (clk => clk,
reset => reset,
dividend => dividend_s, -- DX:AX
divisor => alureg_s(15 downto 0), -- 0&byte/word
--divisor => bbus_s, -- byte/word
quotient => quotient_s, -- 16 bits
remainder => remainder_s, -- 16 bits
twocomp => twocomp_s,
w => wl_s, -- Byte/Word
overflow => div_err_s, -- Divider Overflow. generate int0
start => startdiv_s, -- start conversion, generated by proc
done => done_s); -- conversion done, latch results
ALUU2 : multiplier
generic map (WIDTH => 16) -- Result is 2*WIDTH bits
port map (multiplicant=> alureg_s(31 downto 16),
multiplier => alureg_s(15 downto 0),
product => product_s, -- 32 bits!
twocomp => twocomp_s);
dividend_s <= X"000000"&alureg_s(23 downto 16) when aluopr=ALU_AAM else dxbus_s & alureg_s(31 downto 16);-- DX is sign extended for byte IDIV
-- start serial divider 1 cycle after wralu pulse received. The reason is that the dividend is loaded into the
-- accumulator thus the data must be valid when this happens.
process (clk, reset)
begin
if reset='1' then
startdiv_s <= '0';
elsif rising_edge(clk) then
if (wralu='1' and (aluopr=ALU_DIV or aluopr=ALU_IDIV OR aluopr=ALU_AAM)) then
startdiv_s <= '1';
else
startdiv_s <= '0';
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Create Full adder
----------------------------------------------------------------------------
fulladd: for bit_nr in 0 to 15 generate
outbus_s(bit_nr) <= abus_s(bit_nr) xor addbbus_s(bit_nr) xor cbus_s(bit_nr);
cbus_s(bit_nr+1) <= (abus_s(bit_nr) and addbbus_s(bit_nr)) or
(abus_s(bit_nr) and cbus_s(bit_nr)) or
(addbbus_s(bit_nr) and cbus_s(bit_nr));
end generate fulladd;
bit4_s <= cbus_s(4);
sign16a_s <= alu_inbusa(7) &alu_inbusa(7) &alu_inbusa(7) &alu_inbusa(7)&alu_inbusa(7)&
alu_inbusa(7) &alu_inbusa(7) &alu_inbusa(7) &alu_inbusa(7 downto 0);
sign16b_s <= alu_inbusb(7) &alu_inbusb(7) &alu_inbusb(7) &alu_inbusb(7)&alu_inbusb(7)&
alu_inbusb(7) &alu_inbusb(7) &alu_inbusb(7) &alu_inbusb(7 downto 0);
sign32a_s <= alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&
alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&
alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&
alu_inbusa(15);
-- Invert bus for subtract instructions
addbbus_s <= not bbus_s when ((aluopr=ALU_CMP) or (aluopr=ALU_CMP_SE) or (aluopr=ALU_CMPS) or (aluopr=ALU_DEC)
or (aluopr=ALU_SBB) or (aluopr=ALU_SBB_SE) or (aluopr=ALU_PUSH) or (aluopr=ALU_SUB)
or (aluopr=ALU_SUB_SE) or (aluopr=ALU_SCAS)) else bbus_s;
-- sign extend for IDIV and IMUL instructions
twocomp_s <= '1' when ((aluopr=ALU_IDIV) or (aluopr=ALU_IMUL) or
(aluopr=ALU_IDIV2)or (aluopr=ALU_IMUL2)) else '0';
----------------------------------------------------------------------------
-- Sign Extend Logic abus & bbus & dxbus
----------------------------------------------------------------------------
process (w, alu_inbusa, alu_inbusb, sign16a_s, sign16b_s, aluopr, ax_s, alureg_s)
begin
if (w='1') then -- Word, no sign extend, unless signextend is specified
case aluopr is
when ALU_CMPS =>
abus_s <= alu_inbusa; -- no sign extend
bbus_s <= alureg_s(15 downto 0); -- previous read ES:[DI]
when ALU_NEG | ALU_NOT =>
abus_s <= not(alu_inbusa); -- NEG instruction, not(operand)+1
bbus_s <= alu_inbusb; -- 0001 (0000 for NOT)
when ALU_ADD_SE | ALU_ADC_SE | ALU_SBB_SE | ALU_SUB_SE | ALU_CMP_SE |
ALU_OR_SE | ALU_AND_SE | ALU_XOR_SE=>
abus_s <= alu_inbusa; -- no sign extend
bbus_s <= sign16b_s; -- Sign extend on 8 bits immediate values (see O80I2RM)
when others =>
abus_s <= alu_inbusa; -- no sign extend
bbus_s <= alu_inbusb;
end case;
else
case aluopr is
when ALU_CMPS =>
abus_s <= alu_inbusa;
bbus_s <= alureg_s(15 downto 0);
when ALU_DIV | ALU_DIV2 =>
abus_s <= ax_s;
bbus_s <= alu_inbusb;
when ALU_IDIV| ALU_IDIV2 =>
abus_s <= ax_s;
bbus_s <= sign16b_s;
when ALU_MUL | ALU_MUL2 | ALU_SCAS =>
abus_s <= alu_inbusa;
bbus_s <= alu_inbusb;
when ALU_NEG | ALU_NOT =>
abus_s <= not(alu_inbusa); -- NEG instruction, not(operand)+1
bbus_s <= alu_inbusb; -- 0001 (0000 for NOT)
when others =>
abus_s <= sign16a_s;
bbus_s <= sign16b_s;
end case;
end if;
end process;
process (wl_s, aluopr, dx_s, alu_inbusa) -- dxbus for DIV/IDIV only
begin
if (wl_s='1') then -- Word, no sign extend
dxbus_s <= dx_s;
else -- Byte
if (((aluopr=ALU_IDIV) or (aluopr=ALU_IDIV2)) and (alu_inbusa(15)='1')) then -- signed DX<-SE(AX)/bbus<-SE(byte)
dxbus_s <= X"FFFF"; -- DX=FFFF (ignored for mul)
else
dxbus_s <= X"0000"; -- DX=0000 (ignored for mul)
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Carry In logic
----------------------------------------------------------------------------
process (aluopr, psrreg_s)
begin
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_INC | ALU_POP | ALU_NEG | ALU_NOT
=> cbus_s(0) <= '0';
when ALU_SBB | ALU_SBB_SE
=> cbus_s(0) <= not CFLAG;
when ALU_SUB | ALU_SUB_SE | ALU_DEC | ALU_PUSH | ALU_CMP | ALU_CMP_SE
| ALU_CMPS | ALU_SCAS
=> cbus_s(0) <= '1';
when others => cbus_s(0) <= CFLAG; -- ALU_ADC, ALU_SUB, ALU_SBB
end case;
end process;
----------------------------------------------------------------------------
-- Carry Out logic
-- cout is inverted for ALU_SUB and ALU_SBB before written to psrreg_s
----------------------------------------------------------------------------
process (aluopr, w, psrreg_s, cbus_s, alu_inbusa)
begin
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_ADC | ALU_ADC_SE | ALU_SUB | ALU_SUB_SE | ALU_SBB | ALU_SBB_SE |
ALU_CMP | ALU_CMP_SE | ALU_CMPS| ALU_SCAS =>
if (w='1') then cout_s <= cbus_s(16);
else cout_s <= cbus_s(8);
end if;
when ALU_NEG => -- CF=0 if operand=0, else 1
if (alu_inbusa=X"0000") then
cout_s <= '1'; -- Note CFLAG=NOT(cout_s)
else
cout_s <= '0'; -- Note CFLAG=NOT(cout_s)
end if;
when others =>
cout_s <= CFLAG; -- Keep previous value
end case;
end process;
----------------------------------------------------------------------------
-- Overflow Logic
----------------------------------------------------------------------------
process (aluopr, w, psrreg_s, cbus_s, alureg_s, alucout_s, zflaghigh_s, zflagdx_s,hflagdx_s,zflagah_s,
hflagah_s, wl_s, product_s, c1flag_s)
begin
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_ADC | ALU_ADC_SE | ALU_INC | ALU_DEC | ALU_SUB | ALU_SUB_SE |
ALU_SBB | ALU_SBB_SE | ALU_CMP | ALU_CMP_SE | ALU_CMPS | ALU_SCAS | ALU_NEG =>
if w='1' then -- 16 bits
overflow_s <= cbus_s(16) xor cbus_s(15);
else
overflow_s <= cbus_s(8) xor cbus_s(7);
end if;
when ALU_ROL1 | ALU_RCL1 | ALU_SHL1 => -- count=1 using constants as in rcl bx,1
if (((w='1') and (alureg_s(15)/=alucout_s)) or
((w='0') and (alureg_s(7) /=alucout_s))) then
overflow_s <= '1';
else
overflow_s <= '0';
end if;
when ALU_ROL | ALU_RCL | ALU_SHL => -- cl/cx=1
if (( c1flag_s='1' and w='1' and (alureg_s(15)/=alucout_s)) or
( c1flag_s='1' and w='0' and (alureg_s(7) /=alucout_s))) then
overflow_s <= '1';
else
overflow_s <= '0';
end if;
when ALU_ROR1 | ALU_RCR1 | ALU_SHR1 | ALU_SAR1 =>
if (((w='1') and (alureg_s(15)/=alureg_s(14))) or
((w='0') and (alureg_s(7) /=alureg_s(6)))) then
overflow_s <= '1';
else
overflow_s <= '0';
end if;
when ALU_ROR | ALU_RCR | ALU_SHR | ALU_SAR => -- if cl/cx=1
if ((c1flag_s='1' and w='1' and (alureg_s(15)/=alureg_s(14))) or
(c1flag_s='1' and w='0' and (alureg_s(7) /=alureg_s(6)))) then
overflow_s <= '1';
else
overflow_s <= '0';
end if;
when ALU_MUL | ALU_MUL2 =>
if (wl_s='0') then
overflow_s <= zflaghigh_s;
else
overflow_s <= zflagdx_s; -- MSW multiply/divide result
end if;
when ALU_IMUL | ALU_IMUL2 => -- if MSbit(1)='1' & AH=FF/DX=FFFF
if ((wl_s='0' and product_s(7)='1' and hflagah_s='1') or
(wl_s='0' and product_s(7)='0' and zflagah_s='0') or
(wl_s='1' and product_s(15)='1' and hflagdx_s='1') or
(wl_s='1' and product_s(15)='0' and zflagdx_s='0')) then
overflow_s <= '0';
else
overflow_s <= '1';
end if;
when others =>
overflow_s <= OFLAG; -- Keep previous value
end case;
end process;
----------------------------------------------------------------------------
-- Zeroflag set if result=0, zflagdx_s=1 when dx/=0, zflagah_s=1 when ah/=0
----------------------------------------------------------------------------
zflaglow_s <= alubus_s(7) or alubus_s(6) or alubus_s(5) or alubus_s(4) or
alubus_s(3) or alubus_s(2) or alubus_s(1) or alubus_s(0);
zflaghigh_s <= alubus_s(15) or alubus_s(14) or alubus_s(13) or alubus_s(12) or
alubus_s(11) or alubus_s(10) or alubus_s(9) or alubus_s(8);
zeroflag_s <= not(zflaghigh_s or zflaglow_s) when w='1' else not(zflaglow_s);
zflagdx_s <= product_s(31) or product_s(30) or product_s(29) or product_s(28) or
product_s(27) or product_s(26) or product_s(25) or product_s(24) or
product_s(23) or product_s(22) or product_s(21) or product_s(20) or
product_s(19) or product_s(18) or product_s(17) or product_s(16);
zflagah_s <= product_s(15) or product_s(14) or product_s(13) or product_s(12) or
product_s(11) or product_s(10) or product_s(09) or product_s(08);
----------------------------------------------------------------------------
-- hflag set if IMUL result AH=FF or DX=FFFF
----------------------------------------------------------------------------
hflagah_s <= product_s(15) and product_s(14) and product_s(13) and product_s(12) and
product_s(11) and product_s(10) and product_s(9) and product_s(8);
hflagdx_s <= product_s(31) and product_s(30) and product_s(29) and product_s(28) and
product_s(27) and product_s(26) and product_s(25) and product_s(24) and
product_s(23) and product_s(22) and product_s(21) and product_s(20) and
product_s(19) and product_s(18) and product_s(17) and product_s(16);
----------------------------------------------------------------------------
-- Parity flag set if even number of bits in LSB
----------------------------------------------------------------------------
parityflag_s <=not(alubus_s(7) xor alubus_s(6) xor alubus_s(5) xor alubus_s(4) xor
alubus_s(3) xor alubus_s(2) xor alubus_s(1) xor alubus_s(0));
----------------------------------------------------------------------------
-- Sign flag
----------------------------------------------------------------------------
signflag_s <= alubus_s(15) when w='1' else alubus_s(7);
----------------------------------------------------------------------------
-- c1flag asserted if CL or CX=1, used to update the OF flags during
-- rotate/shift instructions
----------------------------------------------------------------------------
c1flag_s <= '1' when (cx_s=X"0001" and w='1') OR (cx_s(7 downto 0)=X"01" and w='0') else '0';
----------------------------------------------------------------------------
-- Temp/ScratchPad Register
-- alureg_s can also be used as temp storage
-- temp<=bbus;
----------------------------------------------------------------------------
process (clk, reset)
begin
if reset='1' then
alu_temp_s<= (others => '0');
elsif rising_edge(clk) then
if (wrtemp='1') then
alu_temp_s <= bbus_s;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- ALU Register used for xchg and rotate/shift instruction
-- latch Carry Out alucout_s signal
----------------------------------------------------------------------------
process (clk, reset)
begin
if reset='1' then
alureg_s <= (others => '0');
alucout_s<= '0';
wl_s <= '0';
elsif rising_edge(clk) then
if (wralu='1') then
alureg_s(31 downto 16) <= abus_s; -- alu_inbusa;
wl_s <= w; -- Latched w version
if w='1' then -- word operation
case aluopr is
when ALU_ROL | ALU_ROL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 0) & alureg_s(15);
alucout_s<= alureg_s(15);
when ALU_ROR | ALU_ROR1 => alureg_s(15 downto 0) <= alureg_s(0) & alureg_s(15 downto 1);
alucout_s<= alureg_s(0);
when ALU_RCL | ALU_RCL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 0) & alucout_s; -- shift carry in
alucout_s<= alureg_s(15);
when ALU_RCR | ALU_RCR1 => alureg_s(15 downto 0) <= alucout_s & alureg_s(15 downto 1);
alucout_s<= alureg_s(0);
when ALU_SHL | ALU_SHL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 0) & '0';
alucout_s<= alureg_s(15);
when ALU_SHR | ALU_SHR1 => alureg_s(15 downto 0) <= '0' & alureg_s(15 downto 1);
alucout_s<= alureg_s(0);
when ALU_SAR | ALU_SAR1 => alureg_s(15 downto 0) <= alureg_s(15) & alureg_s(15 downto 1);
alucout_s<= alureg_s(0);
when ALU_TEMP => alureg_s(15 downto 0) <= bbus_s;
alucout_s<= '-'; -- Don't care!
when ALU_AAM => alureg_s(15 downto 0) <= X"000A";
alucout_s<= '-'; -- Don't care!
when others => alureg_s(15 downto 0) <= bbus_s ;--alu_inbusb; -- ALU_PASSB
alucout_s<= CFLAG;
end case;
else
case aluopr is -- To aid resource sharing add MSB byte as above
when ALU_ROL | ALU_ROL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 7) & (alureg_s(6 downto 0) & alureg_s(7));
alucout_s<= alureg_s(7);
when ALU_ROR | ALU_ROR1 => alureg_s(15 downto 0) <= alureg_s(0) & alureg_s(15 downto 9) & (alureg_s(0) & alureg_s(7 downto 1));
alucout_s<= alureg_s(0);
when ALU_RCL | ALU_RCL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 7) & (alureg_s(6 downto 0) & alucout_s); -- shift carry in
alucout_s<= alureg_s(7);
-- when ALU_RCR | ALU_RCR1 => alureg_s(15 downto 0) <= alucout_s & alureg_s(15 downto 9) & (psrreg_s(0) & alureg_s(7 downto 1));
when ALU_RCR | ALU_RCR1 => alureg_s(15 downto 0) <= alucout_s & alureg_s(15 downto 9) & (alucout_s & alureg_s(7 downto 1)); -- Ver 0.82
alucout_s<= alureg_s(0);
when ALU_SHL | ALU_SHL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 7) & (alureg_s(6 downto 0) & '0');
alucout_s<= alureg_s(7);
when ALU_SHR | ALU_SHR1 => alureg_s(15 downto 0) <= '0' & alureg_s(15 downto 9) & ('0' & alureg_s(7 downto 1));
alucout_s<= alureg_s(0);
when ALU_SAR | ALU_SAR1 => alureg_s(15 downto 0) <= alureg_s(15) & alureg_s(15 downto 9)& (alureg_s(7) & alureg_s(7 downto 1));
alucout_s<= alureg_s(0);
when ALU_TEMP => alureg_s(15 downto 0) <= bbus_s;
alucout_s<= '-'; -- Don't care!
when ALU_AAM => alureg_s(15 downto 0) <= X"000A";
alucout_s<= '-'; -- Don't care!
when others => alureg_s(15 downto 0) <= bbus_s ;--alu_inbusb -- ALU_PASSB
alucout_s<= CFLAG;
end case;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- AAS Instruction 3F
----------------------------------------------------------------------------
process (alu_inbusa,psrreg_s,aas1bus_s)
begin
aas1bus_s<=alu_inbusa-X"0106";
if ((alu_inbusa(3 downto 0) > "1001") or (psrreg_s(4)='1')) then
aasbus_s <= aas1bus_s(15 downto 8)&X"0"&aas1bus_s(3 downto 0);
setaas_s <= '1'; -- Set CF and AF flag
else
aasbus_s(7 downto 0) <= X"0"&(alu_inbusa(3 downto 0)); -- AL=AL&0Fh
aasbus_s(15 downto 8)<= alu_inbusa(15 downto 8); -- leave AH unchanged
setaas_s <= '0'; -- Clear CF and AF flag
end if;
end process;
----------------------------------------------------------------------------
-- AAA Instruction 37
----------------------------------------------------------------------------
process (alu_inbusa,psrreg_s,aaa1bus_s)
begin
aaa1bus_s<=alu_inbusa+X"0106";
if ((alu_inbusa(3 downto 0) > "1001") or (psrreg_s(4)='1')) then
aaabus_s <= aaa1bus_s(15 downto 8)&X"0"&aaa1bus_s(3 downto 0);
setaaa_s <= '1'; -- Set CF and AF flag
else
aaabus_s(7 downto 0) <= X"0"&alu_inbusa(3 downto 0); -- AL=AL&0Fh
aaabus_s(15 downto 8)<= alu_inbusa(15 downto 8); -- AH Unchanged
setaaa_s <= '0'; -- Clear CF and AF flag
end if;
end process;
----------------------------------------------------------------------------
-- DAA Instruction 27
----------------------------------------------------------------------------
process (alu_inbusa,psrreg_s,setdaa_s)
begin
if ((alu_inbusa(3 downto 0) > X"9") or (psrreg_s(4)='1')) then
setdaa_s(0) <= '1'; -- set AF
else
setdaa_s(0) <= '0'; -- clr AF
end if;
if ((alu_inbusa(7 downto 0) > X"9F") or (psrreg_s(0)='1') or (alu_inbusa(7 downto 0) > X"99")) then
setdaa_s(1) <= '1'; -- set CF
else
setdaa_s(1) <= '0'; -- clr CF
end if;
case setdaa_s is
when "00" => daabus_s <= alu_inbusa(7 downto 0);
when "01" => daabus_s <= alu_inbusa(7 downto 0) + X"06";
when "10" => daabus_s <= alu_inbusa(7 downto 0) + X"60";
when others => daabus_s <= alu_inbusa(7 downto 0) + X"66";
end case;
end process;
----------------------------------------------------------------------------
-- DAS Instruction 2F
----------------------------------------------------------------------------
process (alu_inbusa,psrreg_s,setdas_s)
begin
if ((alu_inbusa(3 downto 0) > X"9") or (psrreg_s(4)='1')) then
setdas_s(0) <= '1'; -- set AF
else
setdas_s(0) <= '0'; -- clr AF
end if;
if ((alu_inbusa(7 downto 0) > X"9F") or (psrreg_s(0)='1') or (alu_inbusa(7 downto 0) > X"99")) then
setdas_s(1) <= '1'; -- set CF
else
setdas_s(1) <= '0'; -- clr CF
end if;
case setdas_s is
when "00" => dasbus_s <= alu_inbusa(7 downto 0);
when "01" => dasbus_s <= alu_inbusa(7 downto 0) - X"06";
when "10" => dasbus_s <= alu_inbusa(7 downto 0) - X"60";
when others => dasbus_s <= alu_inbusa(7 downto 0) - X"66";
end case;
end process;
----------------------------------------------------------------------------
-- AAD Instruction 5D 0A
----------------------------------------------------------------------------
process (alu_inbusa,aad1bus_s,aad2bus_s)
begin
aad1bus_s <= ("00" & alu_inbusa(15 downto 8) & '0') + (alu_inbusa(15 downto 8) & "000"); -- AH*2 + AH*8
aad2bus_s <= aad1bus_s + ("000" & alu_inbusa(7 downto 0)); -- + AL
aadbus_s<= "00000000" & aad2bus_s(7 downto 0);
end process;
----------------------------------------------------------------------------
-- ALU Operation
----------------------------------------------------------------------------
process (aluopr,abus_s,bbus_s,outbus_s,psrreg_s,alureg_s,aasbus_s,aaabus_s,daabus_s,sign16a_s,
sign16b_s,sign32a_s,dasbus_s,product_s,divresult_s,alu_temp_s,aadbus_s,quotient_s,remainder_s)
begin
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_INC | ALU_POP | ALU_SUB | ALU_SUB_SE | ALU_DEC | ALU_PUSH | ALU_CMP | ALU_CMP_SE |
ALU_CMPS | ALU_ADC | ALU_ADC_SE | ALU_SBB | ALU_SBB_SE | ALU_SCAS | ALU_NEG | ALU_NOT
=> alubus_s <= outbus_s;
when ALU_OR | ALU_OR_SE
=> alubus_s <= abus_s OR bbus_s;
when ALU_AND | ALU_AND_SE | ALU_TEST0 | ALU_TEST1 | ALU_TEST2
=> alubus_s <= abus_s AND bbus_s;
when ALU_XOR | ALU_XOR_SE
=> alubus_s <= abus_s XOR bbus_s;
when ALU_LAHF => alubus_s <= psrreg_s(15 downto 2)&'1'&psrreg_s(0);-- flags onto ALUBUS, note reserved bit1=1
when ALU_MUL | ALU_IMUL
=> alubus_s <= product_s(15 downto 0); -- AX of Multiplier
when ALU_MUL2| ALU_IMUL2
=> alubus_s <= product_s(31 downto 16); -- DX of Multiplier
when ALU_DIV | ALU_IDIV
=> alubus_s <= divresult_s(15 downto 0);-- AX of Divider (quotient)
when ALU_DIV2| ALU_IDIV2
=> alubus_s <= divresult_s(31 downto 16);-- DX of Divider (remainder)
when ALU_SEXT => alubus_s <= sign16a_s; -- Used for CBW Instruction
when ALU_SEXTW => alubus_s <= sign32a_s; -- Used for CWD Instruction
when ALU_AAS => alubus_s <= aasbus_s; -- Used for AAS Instruction
when ALU_AAA => alubus_s <= aaabus_s; -- Used for AAA Instruction
when ALU_DAA => alubus_s <= abus_s(15 downto 8) & daabus_s;-- Used for DAA Instruction
when ALU_DAS => alubus_s <= abus_s(15 downto 8) & dasbus_s;-- Used for DAS Instruction
when ALU_AAD => alubus_s <= aadbus_s; -- Used for AAD Instruction
when ALU_AAM => alubus_s <= quotient_s(7 downto 0) & remainder_s(7 downto 0); -- Used for AAM Instruction
when ALU_ROL | ALU_ROL1 | ALU_ROR | ALU_ROR1 | ALU_RCL | ALU_RCL1 | ALU_RCR | ALU_RCR1 |
ALU_SHL | ALU_SHL1 | ALU_SHR | ALU_SHR1 | ALU_SAR | ALU_SAR1 | ALU_REGL
=> alubus_s <= alureg_s(15 downto 0); -- alu_inbusb to output
when ALU_REGH => alubus_s <= alureg_s(31 downto 16); -- alu_inbusa to output
when ALU_PASSA => alubus_s <= abus_s;
--when ALU_PASSB => alubus_s <= bbus_s;
when ALU_TEMP => alubus_s <= alu_temp_s;
when others => alubus_s <= DONTCARE(15 downto 0);
end case;
end process;
alubus <= alubus_s; -- Connect to entity
----------------------------------------------------------------------------
-- Processor Status Register (Flags)
-- bit Flag
-- 15 Reserved
-- 14 Reserved
-- 13 Reserved Set to 1?
-- 12 Reserved Set to 1?
-- 11 Overflow Flag OF
-- 10 Direction Flag DF
-- 9 Interrupt Flag IF
-- 8 Trace Flag TF
-- 7 Sign Flag SF
-- 6 Zero Flag ZF
-- 5 Reserved
-- 4 Auxiliary Carry AF
-- 3 Reserved
-- 2 Parity Flag PF
-- 1 Reserved Set to 1 ????
-- 0 Carry Flag
----------------------------------------------------------------------------
process (clk, reset)
begin
if reset='1' then
psrreg_s <= "1111000000000010";
elsif rising_edge(clk) then
if (wrcc='1') then
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_ADC | ALU_ADC_SE | ALU_INC =>
OFLAG <= overflow_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
AFLAG <= bit4_s;
PFLAG <= parityflag_s;
CFLAG <= cout_s;
when ALU_DEC => -- Same as for ALU_SUB exclusing the CFLAG :-(
OFLAG <= overflow_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
AFLAG <= not bit4_s;
PFLAG <= parityflag_s;
when ALU_SUB | ALU_SUB_SE | ALU_SBB | ALU_SBB_SE | ALU_CMP |
ALU_CMP_SE | ALU_CMPS | ALU_SCAS | ALU_NEG =>
OFLAG <= overflow_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
AFLAG <= not bit4_s;
PFLAG <= parityflag_s;
CFLAG <= not cout_s;
when ALU_OR | ALU_OR_SE | ALU_AND | ALU_AND_SE | ALU_XOR | ALU_XOR_SE | ALU_TEST0 | ALU_TEST1 | ALU_TEST2 =>
OFLAG <= '0';
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
AFLAG <= '0'; -- None defined, set to 0 to be compatible with debug
PFLAG <= parityflag_s;
CFLAG <= '0';
when ALU_SHL | ALU_SHR | ALU_SAR |
ALU_SHR1 | ALU_SAR1 | ALU_SHL1 =>
OFLAG <= overflow_s;
PFLAG <= parityflag_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
CFLAG <= alucout_s;
when ALU_CLC =>
CFLAG <= '0';
when ALU_CMC =>
CFLAG <= not CFLAG;
when ALU_STC =>
CFLAG <= '1';
when ALU_CLD =>
DFLAG <= '0';
when ALU_STD =>
DFLAG <= '1';
when ALU_CLI =>
IFLAG <= '0';
when ALU_STI =>
IFLAG <= '1';
when ALU_POP => -- Note only POPF executes a WRCC command, thus save for other pops
psrreg_s <= "1111" & alu_inbusa(11 downto 0);
when ALU_SAHF => -- Write all AH bits (not compatible!)
psrreg_s(7 downto 0) <= alu_inbusa(7 downto 6) & '0' & alu_inbusa(4) & '0' &
alu_inbusa(2) & '0' & alu_inbusa(0);-- SAHF only writes bits 7,6,4,2,0
when ALU_AAS =>
AFLAG <= setaas_s; -- set or clear CF/AF flag
CFLAG <= setaas_s;
SFLAG <= '0';
when ALU_AAA =>
AFLAG <= setaaa_s; -- set or clear CF/AF flag
CFLAG <= setaaa_s;
when ALU_DAA =>
AFLAG <= setdaa_s(0); -- set or clear CF/AF flag
CFLAG <= setdaa_s(1);
PFLAG <= parityflag_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
when ALU_AAD =>
SFLAG <= alubus_s(7); --signflag_s;
PFLAG <= parityflag_s;
ZFLAG <= zeroflag_s;
when ALU_AAM =>
SFLAG <= signflag_s;
PFLAG <= parityflag_s;
ZFLAG <= not(zflaglow_s); -- signflag on AL only
when ALU_DAS =>
AFLAG <= setdas_s(0); -- set or clear CF/AF flag
CFLAG <= setdas_s(1);
PFLAG <= parityflag_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
-- Shift Rotate Instructions
when ALU_ROL | ALU_ROR | ALU_RCL | ALU_RCR |
ALU_ROL1 | ALU_RCL1 | ALU_ROR1 | ALU_RCR1 =>
CFLAG <= alucout_s;
OFLAG <= overflow_s;
when ALU_MUL | ALU_MUL2 | ALU_IMUL | ALU_IMUL2 => -- Multiply affects CF&OF only
CFLAG <= overflow_s;
OFLAG <= overflow_s;
when ALU_CLRTIF => -- Clear TF and IF flag
IFLAG <= '0';
TFLAG <= '0';
when others =>
psrreg_s <= psrreg_s;
end case;
end if;
end if;
end process;
ccbus <= psrreg_s; -- Connect to entity
-- Latch Divide by 0 error flag & latched divresult.
-- Requires a MCP from all registers to these endpoint registers!
process (clk, reset)
begin
if reset='1' then
div_err <= '0';
divresult_s <= (others => '0');
elsif rising_edge(clk) then
if done_s='1' then -- Latched pulse generated by serial divider
div_err <= div_err_s; -- Divide Overflow
-- pragma synthesis_off
assert div_err_s='0' report "**** Divide Overflow ***" severity note;
-- pragma synthesis_on
if wl_s='1' then -- Latched version required?
divresult_s <= remainder_s & quotient_s;
else
divresult_s <= remainder_s & remainder_s(7 downto 0) & quotient_s(7 downto 0);
end if;
else
div_err <= '0';
end if;
end if;
end process;
end rtl;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 07:03:52 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_controller_1_0_1/system_ov7670_controller_1_0_sim_netlist.vhdl
-- Design : system_ov7670_controller_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_1_0_i2c_sender is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
sioc : out STD_LOGIC;
p_0_in : out STD_LOGIC;
\busy_sr_reg[1]_0\ : out STD_LOGIC;
siod : out STD_LOGIC;
\busy_sr_reg[31]_0\ : in STD_LOGIC;
clk : in STD_LOGIC;
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
DOADO : in STD_LOGIC_VECTOR ( 15 downto 0 );
\busy_sr_reg[31]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_1_0_i2c_sender : entity is "i2c_sender";
end system_ov7670_controller_1_0_i2c_sender;
architecture STRUCTURE of system_ov7670_controller_1_0_i2c_sender is
signal busy_sr0 : STD_LOGIC;
signal \busy_sr[0]_i_3_n_0\ : STD_LOGIC;
signal \busy_sr[0]_i_5_n_0\ : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[29]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \^busy_sr_reg[1]_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \data_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \data_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[31]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \divider_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \divider_reg__1\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^p_0_in\ : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sioc_i_1_n_0 : STD_LOGIC;
signal sioc_i_2_n_0 : STD_LOGIC;
signal sioc_i_3_n_0 : STD_LOGIC;
signal sioc_i_4_n_0 : STD_LOGIC;
signal sioc_i_5_n_0 : STD_LOGIC;
signal siod_INST_0_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \busy_sr[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \busy_sr[0]_i_5\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \busy_sr[10]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[11]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[12]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[13]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[14]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[15]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[16]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[17]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[18]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[19]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \busy_sr[20]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[21]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[22]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[23]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[24]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[25]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[26]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \busy_sr[27]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[28]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[29]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[2]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[30]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \busy_sr[31]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \busy_sr[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[4]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[8]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[9]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \data_sr[10]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[19]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[31]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \divider[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[6]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \divider[7]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of sioc_i_3 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of sioc_i_4 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of sioc_i_5 : label is "soft_lutpair3";
begin
\busy_sr_reg[1]_0\ <= \^busy_sr_reg[1]_0\;
p_0_in <= \^p_0_in\;
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
I2 => \divider_reg__0\(7),
I3 => \^p_0_in\,
I4 => \^busy_sr_reg[1]_0\,
I5 => p_1_in(0),
O => busy_sr0
);
\busy_sr[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \busy_sr[0]_i_3_n_0\
);
\busy_sr[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(3),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \busy_sr[0]_i_5_n_0\,
O => \^busy_sr_reg[1]_0\
);
\busy_sr[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \divider_reg__1\(5),
I1 => \divider_reg__1\(4),
I2 => \divider_reg__0\(7),
I3 => \divider_reg__0\(6),
O => \busy_sr[0]_i_5_n_0\
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[10]\,
I1 => \^p_0_in\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \^p_0_in\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(0),
I1 => \^p_0_in\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(1),
I1 => \^p_0_in\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[21]\,
I1 => \^p_0_in\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[22]\,
I1 => \^p_0_in\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[23]\,
I1 => \^p_0_in\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[24]\,
I1 => \^p_0_in\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[25]\,
I1 => \^p_0_in\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[26]\,
I1 => \^p_0_in\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[27]\,
I1 => \^p_0_in\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \^p_0_in\,
O => \busy_sr[29]_i_1_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[1]\,
I1 => \^p_0_in\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \^p_0_in\,
O => \busy_sr[30]_i_1_n_0\
);
\busy_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"22222222A2222222"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
I3 => \divider_reg__0\(7),
I4 => \divider_reg__0\(6),
I5 => \busy_sr[0]_i_3_n_0\,
O => \busy_sr[31]_i_1_n_0\
);
\busy_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_0_in\,
I1 => \busy_sr_reg_n_0_[30]\,
O => \busy_sr[31]_i_2_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => p_1_in(0),
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[19]_i_1_n_0\,
Q => p_1_in_0(0),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[20]_i_1_n_0\,
Q => p_1_in_0(1),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[28]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[28]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[29]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[29]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[29]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[30]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[30]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[30]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[31]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[31]_i_2_n_0\,
Q => \^p_0_in\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[31]_i_1_n_0\
);
\data_sr[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
I2 => DOADO(7),
O => \data_sr[10]_i_1_n_0\
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
I2 => DOADO(8),
O => \data_sr[12]_i_1_n_0\
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
I2 => DOADO(9),
O => \data_sr[13]_i_1_n_0\
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
I2 => DOADO(10),
O => \data_sr[14]_i_1_n_0\
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
I2 => DOADO(11),
O => \data_sr[15]_i_1_n_0\
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
I2 => DOADO(12),
O => \data_sr[16]_i_1_n_0\
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
I2 => DOADO(13),
O => \data_sr[17]_i_1_n_0\
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
I2 => DOADO(14),
O => \data_sr[18]_i_1_n_0\
);
\data_sr[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
I2 => DOADO(15),
O => \data_sr[19]_i_1_n_0\
);
\data_sr[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[22]\,
I1 => \data_sr_reg_n_0_[21]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[22]_i_1_n_0\
);
\data_sr[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[27]\,
I1 => \data_sr_reg_n_0_[26]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[27]_i_1_n_0\
);
\data_sr[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
O => \data_sr[30]_i_1_n_0\
);
\data_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => \data_sr_reg_n_0_[30]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[31]_i_1_n_0\
);
\data_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \data_sr[31]_i_2_n_0\
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
I2 => DOADO(0),
O => \data_sr[3]_i_1_n_0\
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
I2 => DOADO(1),
O => \data_sr[4]_i_1_n_0\
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
I2 => DOADO(2),
O => \data_sr[5]_i_1_n_0\
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
I2 => DOADO(3),
O => \data_sr[6]_i_1_n_0\
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
I2 => DOADO(4),
O => \data_sr[7]_i_1_n_0\
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
I2 => DOADO(5),
O => \data_sr[8]_i_1_n_0\
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
I2 => DOADO(6),
O => \data_sr[9]_i_1_n_0\
);
\data_sr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[10]_i_1_n_0\,
Q => \data_sr_reg_n_0_[10]\,
R => '0'
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[10]\,
Q => \data_sr_reg_n_0_[11]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[12]_i_1_n_0\,
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[13]_i_1_n_0\,
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[14]_i_1_n_0\,
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[15]_i_1_n_0\,
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[16]_i_1_n_0\,
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[17]_i_1_n_0\,
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[18]_i_1_n_0\,
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[19]_i_1_n_0\,
Q => \data_sr_reg_n_0_[19]\,
R => '0'
);
\data_sr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \^p_0_in\,
Q => \data_sr_reg_n_0_[1]\,
R => '0'
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[22]_i_1_n_0\,
Q => \data_sr_reg_n_0_[22]\,
R => '0'
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[27]_i_1_n_0\,
Q => \data_sr_reg_n_0_[27]\,
R => '0'
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[28]\,
Q => \data_sr_reg_n_0_[29]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[1]\,
Q => \data_sr_reg_n_0_[2]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[29]\,
Q => \data_sr_reg_n_0_[30]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[31]_i_1_n_0\,
Q => \data_sr_reg_n_0_[31]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[3]_i_1_n_0\,
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[4]_i_1_n_0\,
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[5]_i_1_n_0\,
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[6]_i_1_n_0\,
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[7]_i_1_n_0\,
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[8]_i_1_n_0\,
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[9]_i_1_n_0\,
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \divider_reg__1\(0),
O => \p_0_in__0\(0)
);
\divider[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__1\(0),
I1 => \divider_reg__1\(1),
O => \p_0_in__0\(1)
);
\divider[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \divider_reg__1\(1),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(2),
O => \p_0_in__0\(2)
);
\divider[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(1),
I3 => \divider_reg__1\(3),
O => \p_0_in__0\(3)
);
\divider[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \divider_reg__1\(3),
I1 => \divider_reg__1\(1),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(2),
I4 => \divider_reg__1\(4),
O => \p_0_in__0\(4)
);
\divider[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \p_0_in__0\(5)
);
\divider[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \p_0_in__0\(6)
);
\divider[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \busy_sr[0]_i_3_n_0\,
I2 => \divider_reg__0\(7),
O => \p_0_in__0\(7)
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(0),
Q => \divider_reg__1\(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(1),
Q => \divider_reg__1\(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(2),
Q => \divider_reg__1\(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(3),
Q => \divider_reg__1\(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(4),
Q => \divider_reg__1\(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(5),
Q => \divider_reg__1\(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(6),
Q => \divider_reg__0\(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(7),
Q => \divider_reg__0\(7),
R => '0'
);
sioc_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFCFFF8FFFFFFFF"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => sioc_i_2_n_0,
I2 => sioc_i_3_n_0,
I3 => \busy_sr_reg_n_0_[1]\,
I4 => sioc_i_4_n_0,
I5 => \^p_0_in\,
O => sioc_i_1_n_0
);
sioc_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \divider_reg__0\(7),
O => sioc_i_2_n_0
);
sioc_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"A222"
)
port map (
I0 => sioc_i_5_n_0,
I1 => \busy_sr_reg_n_0_[30]\,
I2 => \divider_reg__0\(6),
I3 => \^p_0_in\,
O => sioc_i_3_n_0
);
sioc_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \busy_sr_reg_n_0_[2]\,
I2 => \^p_0_in\,
I3 => \busy_sr_reg_n_0_[30]\,
O => sioc_i_4_n_0
);
sioc_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \busy_sr_reg_n_0_[1]\,
I2 => \busy_sr_reg_n_0_[29]\,
I3 => \busy_sr_reg_n_0_[2]\,
O => sioc_i_5_n_0
);
sioc_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => sioc_i_1_n_0,
Q => sioc,
R => '0'
);
siod_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => siod_INST_0_i_1_n_0,
O => siod
);
siod_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"B0BBB0BB0000B0BB"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \busy_sr_reg_n_0_[29]\,
I2 => p_1_in_0(0),
I3 => p_1_in_0(1),
I4 => \busy_sr_reg_n_0_[11]\,
I5 => \busy_sr_reg_n_0_[10]\,
O => siod_INST_0_i_1_n_0
);
taken_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \busy_sr_reg[31]_0\,
Q => E(0),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_1_0_ov7670_registers is
port (
DOADO : out STD_LOGIC_VECTOR ( 15 downto 0 );
\divider_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
config_finished : out STD_LOGIC;
taken_reg : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\divider_reg[2]\ : in STD_LOGIC;
p_0_in : in STD_LOGIC;
resend : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_1_0_ov7670_registers : entity is "ov7670_registers";
end system_ov7670_controller_1_0_ov7670_registers;
architecture STRUCTURE of system_ov7670_controller_1_0_ov7670_registers is
signal \^doado\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal address : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_rep[0]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[1]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[2]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[3]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[4]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[5]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[6]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_2_n_0\ : STD_LOGIC;
signal config_finished_INST_0_i_1_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_2_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_3_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_4_n_0 : STD_LOGIC;
signal NLW_sreg_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_sreg_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_sreg_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \address_reg[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg[7]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[7]\ : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address_rep[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[6]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \address_rep[7]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \busy_sr[0]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of config_finished_INST_0 : label is "soft_lutpair30";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of sreg_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of sreg_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of sreg_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of sreg_reg : label is 4096;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of sreg_reg : label is "U0/Inst_ov7670_registers/sreg";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of sreg_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of sreg_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of sreg_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of sreg_reg : label is 15;
begin
DOADO(15 downto 0) <= \^doado\(15 downto 0);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => \address_reg__0\(0),
R => resend
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => \address_reg__0\(1),
R => resend
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => \address_reg__0\(2),
R => resend
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => \address_reg__0\(3),
R => resend
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => \address_reg__0\(4),
R => resend
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => \address_reg__0\(5),
R => resend
);
\address_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => \address_reg__0\(6),
R => resend
);
\address_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => \address_reg__0\(7),
R => resend
);
\address_reg_rep[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => address(0),
R => resend
);
\address_reg_rep[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => address(1),
R => resend
);
\address_reg_rep[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => address(2),
R => resend
);
\address_reg_rep[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => address(3),
R => resend
);
\address_reg_rep[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => address(4),
R => resend
);
\address_reg_rep[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => address(5),
R => resend
);
\address_reg_rep[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => address(6),
R => resend
);
\address_reg_rep[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => address(7),
R => resend
);
\address_rep[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \address_reg__0\(0),
O => \address_rep[0]_i_1_n_0\
);
\address_rep[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \address_reg__0\(0),
I1 => \address_reg__0\(1),
O => \address_rep[1]_i_1_n_0\
);
\address_rep[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \address_reg__0\(1),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(2),
O => \address_rep[2]_i_1_n_0\
);
\address_rep[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \address_reg__0\(2),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(1),
I3 => \address_reg__0\(3),
O => \address_rep[3]_i_1_n_0\
);
\address_rep[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \address_reg__0\(3),
I1 => \address_reg__0\(1),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(2),
I4 => \address_reg__0\(4),
O => \address_rep[4]_i_1_n_0\
);
\address_rep[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[5]_i_1_n_0\
);
\address_rep[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \address_rep[7]_i_2_n_0\,
I1 => \address_reg__0\(6),
O => \address_rep[6]_i_1_n_0\
);
\address_rep[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \address_reg__0\(6),
I1 => \address_rep[7]_i_2_n_0\,
I2 => \address_reg__0\(7),
O => \address_rep[7]_i_1_n_0\
);
\address_rep[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[7]_i_2_n_0\
);
\busy_sr[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => config_finished_INST_0_i_4_n_0,
I1 => config_finished_INST_0_i_3_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_1_n_0,
I4 => p_0_in,
O => p_1_in(0)
);
config_finished_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
O => config_finished
);
config_finished_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(5),
I1 => \^doado\(4),
I2 => \^doado\(7),
I3 => \^doado\(6),
O => config_finished_INST_0_i_1_n_0
);
config_finished_INST_0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(1),
I1 => \^doado\(0),
I2 => \^doado\(3),
I3 => \^doado\(2),
O => config_finished_INST_0_i_2_n_0
);
config_finished_INST_0_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(13),
I1 => \^doado\(12),
I2 => \^doado\(15),
I3 => \^doado\(14),
O => config_finished_INST_0_i_3_n_0
);
config_finished_INST_0_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(9),
I1 => \^doado\(8),
I2 => \^doado\(11),
I3 => \^doado\(10),
O => config_finished_INST_0_i_4_n_0
);
\divider[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFE0000"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
I4 => \divider_reg[2]\,
I5 => p_0_in,
O => \divider_reg[7]\(0)
);
sreg_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"53295217510C50344F4014383A04401004008C003E000C001100120412801280",
INIT_01 => X"229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440",
INIT_02 => X"90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 12) => B"00",
ADDRARDADDR(11 downto 4) => address(7 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 0) => \^doado\(15 downto 0),
DOBDO(15 downto 0) => NLW_sreg_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_sreg_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_sreg_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
taken_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055555554"
)
port map (
I0 => p_0_in,
I1 => config_finished_INST_0_i_1_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_3_n_0,
I4 => config_finished_INST_0_i_4_n_0,
I5 => \divider_reg[2]\,
O => taken_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_1_0_ov7670_controller is
port (
config_finished : out STD_LOGIC;
siod : out STD_LOGIC;
xclk : out STD_LOGIC;
sioc : out STD_LOGIC;
resend : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_1_0_ov7670_controller : entity is "ov7670_controller";
end system_ov7670_controller_1_0_ov7670_controller;
architecture STRUCTURE of system_ov7670_controller_1_0_ov7670_controller is
signal Inst_i2c_sender_n_3 : STD_LOGIC;
signal Inst_ov7670_registers_n_16 : STD_LOGIC;
signal Inst_ov7670_registers_n_18 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal sreg_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
signal sys_clk_i_1_n_0 : STD_LOGIC;
signal taken : STD_LOGIC;
signal \^xclk\ : STD_LOGIC;
begin
xclk <= \^xclk\;
Inst_i2c_sender: entity work.system_ov7670_controller_1_0_i2c_sender
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
\busy_sr_reg[1]_0\ => Inst_i2c_sender_n_3,
\busy_sr_reg[31]_0\ => Inst_ov7670_registers_n_18,
\busy_sr_reg[31]_1\(0) => Inst_ov7670_registers_n_16,
clk => clk,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
sioc => sioc,
siod => siod
);
Inst_ov7670_registers: entity work.system_ov7670_controller_1_0_ov7670_registers
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
clk => clk,
config_finished => config_finished,
\divider_reg[2]\ => Inst_i2c_sender_n_3,
\divider_reg[7]\(0) => Inst_ov7670_registers_n_16,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
resend => resend,
taken_reg => Inst_ov7670_registers_n_18
);
sys_clk_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xclk\,
O => sys_clk_i_1_n_0
);
sys_clk_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => sys_clk_i_1_n_0,
Q => \^xclk\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_1_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_controller_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_controller_1_0 : entity is "system_ov7670_controller_1_0,ov7670_controller,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_controller_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_controller_1_0 : entity is "ov7670_controller,Vivado 2016.4";
end system_ov7670_controller_1_0;
architecture STRUCTURE of system_ov7670_controller_1_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
pwdn <= \<const0>\;
reset <= \<const1>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_ov7670_controller_1_0_ov7670_controller
port map (
clk => clk,
config_finished => config_finished,
resend => resend,
sioc => sioc,
siod => siod,
xclk => xclk
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
|
----------------------------------------------------------------------------------
-- ESQUEMA LEDS 8 SEGMENTOS:
--
-- A
-- ---
-- F | | B
-- -G-
-- E | | C
-- --- . DP
-- D
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity binToSeg is
port (
bin: in std_logic_vector(3 downto 0);
displaySeg: out std_logic_vector(7 downto 0) -- 7 = A / 6 = B / ... / 0 = H
);
end binToSeg;
architecture Converter of binToSeg is
begin
with bin select
displaySeg <= "11111100" when "0000", -- 0 => Leds: A,B,C,D,E,F
"01100000" when "0001", -- 1 => Leds: B,C
"11011010" when "0010", -- 2 => Leds: A,B,G,E,D
"11110010" when "0011", -- 3 => Leds: A,B,C,D,G
"01100110" when "0100", -- 4 => Leds: B,C,F,G
"10110110" when "0101", -- 5 => Leds: A,C,D,F,G
"10111110" when "0110", -- 6 => Leds: A,C,D,E,F,G
"11100000" when "0111", -- 7 => Leds: A,B,C
"11111110" when "1000", -- 8 => Leds: A,B,C,D,E,F,G
"11110110" when "1001", -- 9 => Leds: A,B,C,D,F,G
"11101110" when "1010", -- A(10) => Leds: A,B,C,E,F,G
"00111110" when "1011", -- B(11) => Leds: A,B,C,D,E,F,G
"10011100" when "1100", -- C(12) => Leds: A,D,E,F
"01111010" when "1101", -- D(13) => Leds: A,B,C,D,E,F
"10011110" when "1110", -- E(14) => Leds: A,D,E,F,G
"10001110" when "1111", -- F(15) => Leds: A,E,F,G
"00000001" when others; -- En cualquier otro caso encendemos el "."
end Converter;
|
----------------------------------------------------------------------------------
-- ESQUEMA LEDS 8 SEGMENTOS:
--
-- A
-- ---
-- F | | B
-- -G-
-- E | | C
-- --- . DP
-- D
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity binToSeg is
port (
bin: in std_logic_vector(3 downto 0);
displaySeg: out std_logic_vector(7 downto 0) -- 7 = A / 6 = B / ... / 0 = H
);
end binToSeg;
architecture Converter of binToSeg is
begin
with bin select
displaySeg <= "11111100" when "0000", -- 0 => Leds: A,B,C,D,E,F
"01100000" when "0001", -- 1 => Leds: B,C
"11011010" when "0010", -- 2 => Leds: A,B,G,E,D
"11110010" when "0011", -- 3 => Leds: A,B,C,D,G
"01100110" when "0100", -- 4 => Leds: B,C,F,G
"10110110" when "0101", -- 5 => Leds: A,C,D,F,G
"10111110" when "0110", -- 6 => Leds: A,C,D,E,F,G
"11100000" when "0111", -- 7 => Leds: A,B,C
"11111110" when "1000", -- 8 => Leds: A,B,C,D,E,F,G
"11110110" when "1001", -- 9 => Leds: A,B,C,D,F,G
"11101110" when "1010", -- A(10) => Leds: A,B,C,E,F,G
"00111110" when "1011", -- B(11) => Leds: A,B,C,D,E,F,G
"10011100" when "1100", -- C(12) => Leds: A,D,E,F
"01111010" when "1101", -- D(13) => Leds: A,B,C,D,E,F
"10011110" when "1110", -- E(14) => Leds: A,D,E,F,G
"10001110" when "1111", -- F(15) => Leds: A,E,F,G
"00000001" when others; -- En cualquier otro caso encendemos el "."
end Converter;
|
----------------------------------------------------------------------------------
-- ESQUEMA LEDS 8 SEGMENTOS:
--
-- A
-- ---
-- F | | B
-- -G-
-- E | | C
-- --- . DP
-- D
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity binToSeg is
port (
bin: in std_logic_vector(3 downto 0);
displaySeg: out std_logic_vector(7 downto 0) -- 7 = A / 6 = B / ... / 0 = H
);
end binToSeg;
architecture Converter of binToSeg is
begin
with bin select
displaySeg <= "11111100" when "0000", -- 0 => Leds: A,B,C,D,E,F
"01100000" when "0001", -- 1 => Leds: B,C
"11011010" when "0010", -- 2 => Leds: A,B,G,E,D
"11110010" when "0011", -- 3 => Leds: A,B,C,D,G
"01100110" when "0100", -- 4 => Leds: B,C,F,G
"10110110" when "0101", -- 5 => Leds: A,C,D,F,G
"10111110" when "0110", -- 6 => Leds: A,C,D,E,F,G
"11100000" when "0111", -- 7 => Leds: A,B,C
"11111110" when "1000", -- 8 => Leds: A,B,C,D,E,F,G
"11110110" when "1001", -- 9 => Leds: A,B,C,D,F,G
"11101110" when "1010", -- A(10) => Leds: A,B,C,E,F,G
"00111110" when "1011", -- B(11) => Leds: A,B,C,D,E,F,G
"10011100" when "1100", -- C(12) => Leds: A,D,E,F
"01111010" when "1101", -- D(13) => Leds: A,B,C,D,E,F
"10011110" when "1110", -- E(14) => Leds: A,D,E,F,G
"10001110" when "1111", -- F(15) => Leds: A,E,F,G
"00000001" when others; -- En cualquier otro caso encendemos el "."
end Converter;
|
----------------------------------------------------------------------------------
-- ESQUEMA LEDS 8 SEGMENTOS:
--
-- A
-- ---
-- F | | B
-- -G-
-- E | | C
-- --- . DP
-- D
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity binToSeg is
port (
bin: in std_logic_vector(3 downto 0);
displaySeg: out std_logic_vector(7 downto 0) -- 7 = A / 6 = B / ... / 0 = H
);
end binToSeg;
architecture Converter of binToSeg is
begin
with bin select
displaySeg <= "11111100" when "0000", -- 0 => Leds: A,B,C,D,E,F
"01100000" when "0001", -- 1 => Leds: B,C
"11011010" when "0010", -- 2 => Leds: A,B,G,E,D
"11110010" when "0011", -- 3 => Leds: A,B,C,D,G
"01100110" when "0100", -- 4 => Leds: B,C,F,G
"10110110" when "0101", -- 5 => Leds: A,C,D,F,G
"10111110" when "0110", -- 6 => Leds: A,C,D,E,F,G
"11100000" when "0111", -- 7 => Leds: A,B,C
"11111110" when "1000", -- 8 => Leds: A,B,C,D,E,F,G
"11110110" when "1001", -- 9 => Leds: A,B,C,D,F,G
"11101110" when "1010", -- A(10) => Leds: A,B,C,E,F,G
"00111110" when "1011", -- B(11) => Leds: A,B,C,D,E,F,G
"10011100" when "1100", -- C(12) => Leds: A,D,E,F
"01111010" when "1101", -- D(13) => Leds: A,B,C,D,E,F
"10011110" when "1110", -- E(14) => Leds: A,D,E,F,G
"10001110" when "1111", -- F(15) => Leds: A,E,F,G
"00000001" when others; -- En cualquier otro caso encendemos el "."
end Converter;
|
----------------------------------------------------------------------------------
-- ESQUEMA LEDS 8 SEGMENTOS:
--
-- A
-- ---
-- F | | B
-- -G-
-- E | | C
-- --- . DP
-- D
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity binToSeg is
port (
bin: in std_logic_vector(3 downto 0);
displaySeg: out std_logic_vector(7 downto 0) -- 7 = A / 6 = B / ... / 0 = H
);
end binToSeg;
architecture Converter of binToSeg is
begin
with bin select
displaySeg <= "11111100" when "0000", -- 0 => Leds: A,B,C,D,E,F
"01100000" when "0001", -- 1 => Leds: B,C
"11011010" when "0010", -- 2 => Leds: A,B,G,E,D
"11110010" when "0011", -- 3 => Leds: A,B,C,D,G
"01100110" when "0100", -- 4 => Leds: B,C,F,G
"10110110" when "0101", -- 5 => Leds: A,C,D,F,G
"10111110" when "0110", -- 6 => Leds: A,C,D,E,F,G
"11100000" when "0111", -- 7 => Leds: A,B,C
"11111110" when "1000", -- 8 => Leds: A,B,C,D,E,F,G
"11110110" when "1001", -- 9 => Leds: A,B,C,D,F,G
"11101110" when "1010", -- A(10) => Leds: A,B,C,E,F,G
"00111110" when "1011", -- B(11) => Leds: A,B,C,D,E,F,G
"10011100" when "1100", -- C(12) => Leds: A,D,E,F
"01111010" when "1101", -- D(13) => Leds: A,B,C,D,E,F
"10011110" when "1110", -- E(14) => Leds: A,D,E,F,G
"10001110" when "1111", -- F(15) => Leds: A,E,F,G
"00000001" when others; -- En cualquier otro caso encendemos el "."
end Converter;
|
entity tb_dff06 is
end tb_dff06;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff06 is
signal clk : std_logic;
signal en1 : std_logic;
signal en2 : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.dff06
port map (
q => dout,
d => din,
en1 => en1,
en2 => en2,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
en1 <= '1';
en2 <= '1';
din <= '0';
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '1' severity failure;
en1 <= '0';
din <= '0';
pulse;
assert dout = '1' severity failure;
en1 <= '1';
din <= '0';
pulse;
assert dout = '0' severity failure;
en2 <= '0';
din <= '1';
pulse;
assert dout = '0' severity failure;
en2 <= '1';
din <= '1';
pulse;
assert dout = '1' severity failure;
wait;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--
-- This module connects all other modules
-- for testing.
--
entity disp is
port(
clk: in std_logic;
bcd: in std_logic_vector(3 downto 0);
en: out std_logic_vector(3 downto 0);
sseg: out std_logic_vector(7 downto 0)
);
end disp ;
architecture disp_arch of disp is
signal b0, b1, b2, b3: std_logic_vector(3 downto 0);
signal d0, d1, d2, d3: std_logic_vector(7 downto 0);
begin
b0 <= bcd + 4;
b1 <= bcd + 3;
b2 <= bcd + 2;
b3 <= bcd + 1;
conv0: entity work.bcd_to_sseg(convert)
port map(bcd => b0, sseg => d0, dp => '0');
conv1: entity work.bcd_to_sseg(convert)
port map(bcd => b1, sseg => d1, dp => '0');
conv2: entity work.bcd_to_sseg(convert)
port map(bcd => b2, sseg => d2, dp => '0');
conv3: entity work.bcd_to_sseg(convert)
port map(bcd => b3, sseg => d3, dp => '0');
disp: entity work.sseg_mux(mux_arch)
port map(
clk => clk, reset => '0',
in0 => d0, in1 => d1, in2 => d2, in3 => d3,
en => en,
sseg => sseg
);
end disp_arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Design Name:
-- Module Name: tx_Transact - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision 1.30 - Memory buffer applied and structure regulated for DPR. 25.03.2008
--
-- Revision 1.20 - Literal assignments rewritten. 02.08.2007
--
-- Revision 1.10 - x4 timing constraints met. 02.02.2007
--
-- Revision 1.06 - BRAM output and FIFO output both registered. 01.02.2007
--
-- Revision 1.04 - Timing improved. 17.01.2007
--
-- Revision 1.02 - FIFO added. 20.12.2006
--
-- Revision 1.00 - first release. 14.12.2006
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
use work.genram_pkg.all;
entity tx_Transact is
port (
-- Common ports
user_clk : in std_logic;
user_reset : in std_logic;
user_lnk_up : in std_logic;
-- Transaction
s_axis_tx_tlast : out std_logic;
s_axis_tx_tdata : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
s_axis_tx_tkeep : out std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
s_axis_tx_terrfwd : out std_logic;
s_axis_tx_tvalid : out std_logic;
s_axis_tx_tready : in std_logic;
s_axis_tx_tdsc : out std_logic;
tx_buf_av : in std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
-- Upstream DMA transferred bytes count up
us_DMA_Bytes_Add : out std_logic;
us_DMA_Bytes : out std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- Wishbone Read interface
wb_rdc_sof : out std_logic;
wb_rdc_v : out std_logic;
wb_rdc_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_rdc_full : in std_logic;
-- Wisbbone Buffer read port
wb_FIFO_re : out std_logic;
wb_FIFO_empty : in std_logic;
wb_FIFO_qout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Read interface for Tx port
Regs_RdAddr : out std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_RdQout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Irpt Channel
Irpt_Req : in std_logic;
Irpt_RE : out std_logic;
Irpt_Qout : in std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- PIO MRd Channel
pioCplD_Req : in std_logic;
pioCplD_RE : out std_logic;
pioCplD_Qout : in std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- downstream MRd Channel
dsMRd_Req : in std_logic;
dsMRd_RE : out std_logic;
dsMRd_Qout : in std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- upstream MWr/MRd Channel
usTlp_Req : in std_logic;
usTlp_RE : out std_logic;
usTlp_Qout : in std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
us_FC_stop : out std_logic;
us_Last_sof : out std_logic;
us_Last_eof : out std_logic;
-- Message routing method
Msg_Routing : in std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
-- DDR read port
DDR_rdc_sof : out std_logic;
DDR_rdc_eof : out std_logic;
DDR_rdc_v : out std_logic;
DDR_rdc_Shift : out std_logic;
DDR_rdc_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : in std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : out std_logic;
DDR_FIFO_Empty : in std_logic;
DDR_FIFO_RdQout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Additional
Tx_TimeOut : out std_logic;
Tx_wb_TimeOut : out std_logic;
Tx_Reset : in std_logic;
localID : in std_logic_vector(C_ID_WIDTH-1 downto 0)
);
end tx_Transact;
architecture Behavioral of tx_Transact is
type TxTrnStates is (St_TxIdle, -- Idle
St_d_CmdReq, -- Issue the read command to MemReader
St_d_CmdAck, -- Wait for the read command ACK from MemReader
St_d_Header0, -- 1st Header for TLP with payload
St_d_Header2, -- 2nd Header for TLP with payload
-- St_d_HeaderPlus, -- Extra Header for TLP4 with payload
St_d_1st_Data, -- Last Header for TLP3/4 with payload
St_d_Payload, -- Data for TLP with payload
St_d_Payload_used, -- Data flow from memory buffer discontinued
St_d_Tail, -- Last data for TLP with payload
St_d_Tail_chk, -- Last data extended for TLP with payload
St_nd_Prepare, -- Prepare for 1st Header of TLP without payload
-- St_nd_Header1, -- 1st Header for TLP without payload
St_nd_Header2, -- 2nd Header for TLP without payload
-- St_nd_HeaderPlus, -- Extra Header for TLP4 without payload
St_nd_HeaderLast, -- Tail processing for the last dword of TLP w/o payload
St_nd_Arbitration -- One extra cycle for arbitration
);
-- State variables
signal TxTrn_State : TxTrnStates;
-- Signals with the arbitrator
signal take_an_Arbitration : std_logic;
signal Req_Bundle : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
signal Read_a_Buffer : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
signal Ack_Indice : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
signal b1_Tx_Indicator : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
signal vec_ChQout_Valid : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
signal Tx_Busy : std_logic;
-- Channel buffer output token bits
signal usTLP_is_MWr : std_logic;
signal TLP_is_CplD : std_logic;
-- Bit information, telling whether the outgoing TLP has payload
signal ChBuf_has_Payload : std_logic;
signal ChBuf_No_Payload : std_logic;
-- Channel buffers output OR'ed and registered
signal Trn_Qout_wire : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal Trn_Qout_reg : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Addresses from different channel buffer
signal wbaddr_piocpld : std_logic_vector(C_WB_AWIDTH-1 downto 0);
signal mAddr_usTlp : std_logic_vector(C_PRAM_AWIDTH-1+2 downto 0);
signal DDRAddr_usTlp : std_logic_vector(C_DDR_IAWIDTH-1 downto 0);
signal WBAddr_usTlp : std_logic_vector(C_WB_AWIDTH-1 downto 0);
signal Regs_Addr_pioCplD : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal DDRAddr_pioCplD : std_logic_vector(C_DDR_IAWIDTH-1 downto 0);
-- BAR number
signal BAR_pioCplD : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
signal BAR_usTlp : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
-- Misc. info.
signal AInc_usTlp : std_logic;
signal pioCplD_is_0Leng : std_logic;
-- Delay for requests from Channel Buffers
signal Irpt_Req_r1 : std_logic;
signal pioCplD_Req_r1 : std_logic;
signal dsMRd_Req_r1 : std_logic;
signal usTlp_Req_r1 : std_logic;
-- Registered channel buffer outputs
signal Irpt_Qout_to_TLP : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal pioCplD_Qout_to_TLP : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal dsMRd_Qout_to_TLP : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal usTlp_Qout_to_TLP : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal pioCplD_Req_Min_Leng : std_logic;
signal pioCplD_Req_2DW_Leng : std_logic;
signal usTlp_Req_Min_Leng : std_logic;
signal usTlp_Req_2DW_Leng : std_logic;
-- Channel buffer read enables
signal Irpt_RE_i : std_logic;
signal pioCplD_RE_i : std_logic;
signal dsMRd_RE_i : std_logic;
signal usTlp_RE_i : std_logic;
-- Flow controls
signal us_FC_stop_i : std_logic;
-- Local reset for tx
signal trn_tx_Reset_n : std_logic;
-- Alias for transaction interface signals
signal s_axis_tx_tdata_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal s_axis_tx_tkeep_i : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal s_axis_tx_tlast_i : std_logic;
signal s_axis_tx_tvalid_i : std_logic;
signal s_axis_tx_tdsc_i : std_logic;
signal s_axis_tx_terrfwd_i : std_logic;
signal s_axis_tx_tready_i : std_logic;
signal tx_buf_av_i : std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
signal trn_tsof_n_i : std_logic;
-- Upstream DMA transferred bytes count up
signal us_DMA_Bytes_Add_i : std_logic;
signal us_DMA_Bytes_i : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
--------------------- Memory Reader -----------------------------
---
--- Memory reader is the interface to access all sorts of memories
--- BRAM, FIFO, Registers, as well as possible DDR SDRAM
---
-------------------------------------------------------------------
component
tx_Mem_Reader
port(
DDR_rdc_sof : out std_logic;
DDR_rdc_eof : out std_logic;
DDR_rdc_v : out std_logic;
DDR_rdc_Shift : out std_logic;
DDR_rdc_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : in std_logic;
DDR_FIFO_RdEn : out std_logic;
DDR_FIFO_Empty : in std_logic;
DDR_FIFO_RdQout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Wishbone Read interface
wb_rdc_sof : out std_logic;
wb_rdc_v : out std_logic;
wb_rdc_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_rdc_full : in std_logic;
-- Wisbbone Buffer read port
wb_FIFO_re : out std_logic;
wb_FIFO_empty : in std_logic;
wb_FIFO_qout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Regs_RdAddr : out std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_RdQout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
RdNumber : in std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
RdNumber_eq_One : in std_logic;
RdNumber_eq_Two : in std_logic;
StartAddr : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Shift_1st_QWord : in std_logic;
is_CplD : in std_logic;
BAR_value : in std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
RdCmd_Req : in std_logic;
RdCmd_Ack : out std_logic;
mbuf_WE : out std_logic;
mbuf_Din : out std_logic_vector(C_DBUS_WIDTH*9/8-1 downto 0);
mbuf_Full : in std_logic;
mbuf_aFull : in std_logic;
Tx_TimeOut : out std_logic;
Tx_wb_TimeOut : out std_logic;
mReader_Rst_n : in std_logic;
user_clk : in std_logic
);
end component;
signal RdNumber : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
signal RdNumber_eq_One : std_logic;
signal RdNumber_eq_Two : std_logic;
signal StartAddr : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Shift_1st_QWord : std_logic;
signal is_CplD : std_logic;
signal BAR_value : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
signal RdCmd_Req : std_logic;
signal RdCmd_Ack : std_logic;
signal mbuf_reset_n : std_logic;
signal mbuf_WE : std_logic;
signal mbuf_Din : std_logic_vector(C_DBUS_WIDTH*9/8-1 downto 0);
signal mbuf_Full : std_logic;
signal mbuf_aFull : std_logic;
signal mbuf_RE : std_logic;
signal mbuf_Qout : std_logic_vector(C_DBUS_WIDTH*9/8-1 downto 0);
signal mbuf_Empty : std_logic;
-- Calculated infomation
signal mbuf_RE_ok : std_logic;
signal mbuf_Qvalid : std_logic;
--------------------- Output arbitration ------------------------
---
--- For sake of fairness, the priorities are cycled every time
--- a service is done, after which the priority of the request
--- just serviced is set to the lowest and other lower priorities
--- increased and higher stay.
---
-------------------------------------------------------------------
component
Tx_Output_Arbitor
port(
rst_n : in std_logic;
clk : in std_logic;
arbtake : in std_logic;
Req : in std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0);
bufread : out std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0);
Ack : out std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0)
);
end component;
begin
-- Connect outputs
s_axis_tx_tdata <= s_axis_tx_tdata_i;
s_axis_tx_tkeep <= s_axis_tx_tkeep_i;
s_axis_tx_tlast <= s_axis_tx_tlast_i;
s_axis_tx_tvalid <= s_axis_tx_tvalid_i;
s_axis_tx_tdsc <= s_axis_tx_tdsc_i;
s_axis_tx_terrfwd <= s_axis_tx_terrfwd_i;
us_Last_sof <= usTLP_is_MWr and not trn_tsof_n_i;
us_Last_eof <= usTLP_is_MWr and not s_axis_tx_tlast_i;
-- Connect inputs
s_axis_tx_tready_i <= s_axis_tx_tready;
tx_buf_av_i <= tx_buf_av;
-- Always deasserted
s_axis_tx_tdsc_i <= '0';
s_axis_tx_terrfwd_i <= '0';
-- Upstream DMA transferred bytes counting up
us_DMA_Bytes_Add <= us_DMA_Bytes_Add_i;
us_DMA_Bytes <= us_DMA_Bytes_i;
-- Flow controls
us_FC_stop <= us_FC_stop_i;
---------------------------------------------------------------------------------
-- Synchronous Calculation: us_FC_stop, pio_FC_stop
--
Synch_Calc_FC_stop :
process (user_clk, Tx_Reset)
begin
if Tx_Reset = '1' then
us_FC_stop_i <= '1';
elsif user_clk'event and user_clk = '1' then
if tx_buf_av_i(C_TBUF_AWIDTH-1 downto 1) /= C_ALL_ZEROS(C_TBUF_AWIDTH-1 downto 1) then
us_FC_stop_i <= '0';
else
us_FC_stop_i <= '1';
end if;
end if;
end process;
-- Channel buffer read enable
Irpt_RE <= Irpt_RE_i;
pioCplD_RE <= pioCplD_RE_i;
dsMRd_RE <= dsMRd_RE_i;
usTlp_RE <= usTlp_RE_i;
-- -----------------------------------
-- Synchronized Local reset
--
Syn_Local_Reset :
process (user_clk, user_reset)
begin
if user_reset = '1' then
trn_tx_Reset_n <= '0';
elsif user_clk'event and user_clk = '1' then
trn_tx_Reset_n <= not Tx_Reset;
end if;
end process;
------------------------------------------------------------
--- Memory reader
------------------------------------------------------------
ABB_Tx_MReader :
tx_Mem_Reader
port map(
DDR_rdc_sof => DDR_rdc_sof , -- OUT std_logic;
DDR_rdc_eof => DDR_rdc_eof , -- OUT std_logic;
DDR_rdc_v => DDR_rdc_v , -- OUT std_logic;
DDR_rdc_Shift => DDR_rdc_Shift , -- OUT std_logic;
DDR_rdc_din => DDR_rdc_din , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full => DDR_rdc_full , -- IN std_logic;
DDR_FIFO_RdEn => DDR_FIFO_RdEn , -- OUT std_logic;
DDR_FIFO_Empty => DDR_FIFO_Empty , -- IN std_logic;
DDR_FIFO_RdQout => DDR_FIFO_RdQout , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_rdc_sof => wb_rdc_sof, -- : out std_logic;
wb_rdc_v => wb_rdc_v, -- : out std_logic;
wb_rdc_din => wb_rdc_din, -- : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_rdc_full => wb_rdc_full, --: in std_logic;
wb_FIFO_re => wb_FIFO_re , -- OUT std_logic;
wb_FIFO_empty => wb_FIFO_empty , -- IN std_logic;
wb_FIFO_qout => wb_FIFO_qout , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Regs_RdAddr => Regs_RdAddr , -- OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_RdQout => Regs_RdQout , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
RdNumber => RdNumber , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
RdNumber_eq_One => RdNumber_eq_One , -- IN std_logic;
RdNumber_eq_Two => RdNumber_eq_Two , -- IN std_logic;
StartAddr => StartAddr , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Shift_1st_QWord => Shift_1st_QWord , -- IN std_logic;
is_CplD => is_CplD , -- IN std_logic;
BAR_value => BAR_value , -- IN std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
RdCmd_Req => RdCmd_Req , -- IN std_logic;
RdCmd_Ack => RdCmd_Ack , -- OUT std_logic;
mbuf_WE => mbuf_WE , -- OUT std_logic;
mbuf_Din => mbuf_Din , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
mbuf_Full => mbuf_Full , -- IN std_logic;
mbuf_aFull => mbuf_aFull , -- IN std_logic;
Tx_TimeOut => Tx_TimeOut , -- OUT std_logic;
Tx_wb_TimeOut => Tx_wb_TimeOut , -- OUT std_logic;
mReader_Rst_n => trn_tx_Reset_n , -- IN std_logic;
user_clk => user_clk -- IN std_logic
);
--------------------- Memory Buffer -----------------------------
---
--- A unified memory buffer holding the payload for the next tx TLP
--- 34 bits wide, wherein 2 additional framing bits
--- temporarily 64 data depth, possibly deepened.
---
-------------------------------------------------------------------
ABB_Tx_MBuffer :
generic_sync_fifo
generic map (
g_data_width => 72,
g_size => 128,
g_show_ahead => false,
g_with_empty => true,
g_with_full => true,
g_with_almost_empty => false,
g_with_almost_full => true,
g_with_count => false,
g_almost_full_threshold => 125)
port map(
rst_n_i => mbuf_reset_n,
clk_i => user_clk,
d_i => mbuf_din,
we_i => mbuf_we,
q_o => mbuf_qout,
rd_i => mbuf_re,
empty_o => mbuf_empty,
full_o => mbuf_full,
almost_empty_o => open,
almost_full_o => mbuf_afull,
count_o => open);
mbuf_RE <= mbuf_RE_ok and (s_axis_tx_tready_i or not s_axis_tx_tvalid_i);
---------------------------------------------------------------------------------
-- Synchronous Delay: mbuf_Qout Valid
--
Synchron_Delay_mbuf_Qvalid :
process (user_clk, Tx_Reset)
begin
if Tx_Reset = '1' then
mbuf_Qvalid <= '0';
elsif user_clk'event and user_clk = '1' then
if mbuf_Qvalid = '0' and mbuf_RE = '1' and mbuf_Empty = '0' then -- a valid data is going out
mbuf_Qvalid <= '1';
elsif mbuf_Qvalid = '1' and mbuf_RE = '1' and mbuf_Empty = '1' then -- an invalid data is going out
mbuf_Qvalid <= '0';
else -- state stays
mbuf_Qvalid <= mbuf_Qvalid;
end if;
end if;
end process;
------------------------------------------------------------
--- Output arbitration
------------------------------------------------------------
O_Arbitration :
Tx_Output_Arbitor
port map(
rst_n => trn_tx_Reset_n,
clk => user_clk,
arbtake => take_an_Arbitration,
Req => Req_Bundle,
bufread => Read_a_Buffer,
Ack => Ack_Indice
);
-----------------------------------------------------
-- Synchronous Delay: Channel Requests
--
Synchron_Delay_ChRequests :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
Irpt_Req_r1 <= Irpt_Req;
pioCplD_Req_r1 <= pioCplD_Req;
dsMRd_Req_r1 <= dsMRd_Req;
usTlp_Req_r1 <= usTlp_Req;
end if;
end process;
-----------------------------------------------------
-- Synchronous Delay: Tx_Busy
--
Synchron_Delay_Tx_Busy :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
Tx_Busy <= (b1_Tx_Indicator(C_CHAN_INDEX_IRPT) and vec_ChQout_Valid(C_CHAN_INDEX_IRPT))
or (b1_Tx_Indicator(C_CHAN_INDEX_MRD) and vec_ChQout_Valid(C_CHAN_INDEX_MRD))
or (b1_Tx_Indicator(C_CHAN_INDEX_DMA_DS) and vec_ChQout_Valid(C_CHAN_INDEX_DMA_DS))
or (b1_Tx_Indicator(C_CHAN_INDEX_DMA_US) and vec_ChQout_Valid(C_CHAN_INDEX_DMA_US));
end if;
end process;
-- ---------------------------------------------
-- Reg : Channel Buffer Qout has Payload
--
Reg_ChBuf_with_Payload :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
ChBuf_has_Payload <= (b1_Tx_Indicator(C_CHAN_INDEX_MRD) and TLP_is_CplD and vec_ChQout_Valid(C_CHAN_INDEX_MRD))
or (b1_Tx_Indicator(C_CHAN_INDEX_DMA_US) and usTLP_is_MWr and vec_ChQout_Valid(C_CHAN_INDEX_DMA_US));
end if;
end process;
-- ---------------------------------------------
-- Channel Buffer Qout has no Payload
-- (! subordinate to ChBuf_has_Payload ! )
--
ChBuf_No_Payload <= Tx_Busy;
-- Arbitrator inputs
Req_Bundle(C_CHAN_INDEX_IRPT) <= Irpt_Req_r1;
Req_Bundle(C_CHAN_INDEX_MRD) <= pioCplD_Req_r1;
Req_Bundle(C_CHAN_INDEX_DMA_DS) <= dsMRd_Req_r1;
Req_Bundle(C_CHAN_INDEX_DMA_US) <= usTlp_Req_r1;
-- Arbitrator outputs
b1_Tx_Indicator(C_CHAN_INDEX_IRPT) <= Ack_Indice(C_CHAN_INDEX_IRPT);
b1_Tx_Indicator(C_CHAN_INDEX_MRD) <= Ack_Indice(C_CHAN_INDEX_MRD);
b1_Tx_Indicator(C_CHAN_INDEX_DMA_DS) <= Ack_Indice(C_CHAN_INDEX_DMA_DS);
b1_Tx_Indicator(C_CHAN_INDEX_DMA_US) <= Ack_Indice(C_CHAN_INDEX_DMA_US);
-- Arbitrator reads channel buffers
Irpt_RE_i <= Read_a_Buffer(C_CHAN_INDEX_IRPT);
pioCplD_RE_i <= Read_a_Buffer(C_CHAN_INDEX_MRD);
dsMRd_RE_i <= Read_a_Buffer(C_CHAN_INDEX_DMA_DS);
usTlp_RE_i <= Read_a_Buffer(C_CHAN_INDEX_DMA_US);
-- determine whether the upstream TLP is an MWr or an MRd.
usTLP_is_MWr <= usTlp_Qout (C_CHBUF_FMT_BIT_TOP);
TLP_is_CplD <= pioCplD_Qout(C_CHBUF_FMT_BIT_TOP);
-- check if the Channel buffer output is valid
vec_ChQout_Valid(C_CHAN_INDEX_IRPT) <= Irpt_Qout (C_CHBUF_QVALID_BIT);
vec_ChQout_Valid(C_CHAN_INDEX_MRD) <= pioCplD_Qout(C_CHBUF_QVALID_BIT);
vec_ChQout_Valid(C_CHAN_INDEX_DMA_DS) <= dsMRd_Qout (C_CHBUF_QVALID_BIT);
vec_ChQout_Valid(C_CHAN_INDEX_DMA_US) <= usTlp_Qout (C_CHBUF_QVALID_BIT);
-- -----------------------------------
-- Delay : Channel_Buffer_Qout
-- Bit-mapping is done
--
Delay_Channel_Buffer_Qout :
process (user_clk, trn_tx_Reset_n)
begin
if trn_tx_Reset_n = '0' then
Irpt_Qout_to_TLP <= (others => '0');
pioCplD_Qout_to_TLP <= (others => '0');
dsMRd_Qout_to_TLP <= (others => '0');
usTlp_Qout_to_TLP <= (others => '0');
pioCplD_Req_Min_Leng <= '0';
pioCplD_Req_2DW_Leng <= '0';
usTlp_Req_Min_Leng <= '0';
usTlp_Req_2DW_Leng <= '0';
Regs_Addr_pioCplD <= (others => '1');
wbaddr_piocpld <= (others => '1');
mAddr_usTlp <= (others => '1');
AInc_usTlp <= '1';
BAR_pioCplD <= (others => '1');
BAR_usTlp <= (others => '1');
pioCplD_is_0Leng <= '0';
elsif user_clk'event and user_clk = '1' then
if b1_Tx_Indicator(C_CHAN_INDEX_IRPT) = '1' then
Irpt_Qout_to_TLP <= (others => '0'); -- must be 1st argument
-- 1st header Hi
Irpt_Qout_to_TLP(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) <= Irpt_Qout(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT);
-- Irpt_Qout_to_TLP(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) <= C_TYPE_OF_MSG; --Irpt_Qout(C_CHBUF_MSGTYPE_BIT_TOP downto C_CHBUF_MSGTYPE_BIT_BOT);
Irpt_Qout_to_TLP(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) <= C_TYPE_OF_MSG(C_TLP_TYPE_BIT_TOP
downto C_TLP_TYPE_BIT_BOT+1+C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT)
& Msg_Routing;
Irpt_Qout_to_TLP(C_TLP_TC_BIT_TOP downto C_TLP_TC_BIT_BOT) <= Irpt_Qout(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT);
Irpt_Qout_to_TLP(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT) <= Irpt_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
-- 1st header Lo
Irpt_Qout_to_TLP(C_TLP_REQID_BIT_TOP downto C_TLP_REQID_BIT_BOT) <= localID;
Irpt_Qout_to_TLP(C_TLP_TAG_BIT_TOP downto C_TLP_TAG_BIT_BOT) <= Irpt_Qout(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT);
Irpt_Qout_to_TLP(C_MSG_CODE_BIT_TOP downto C_MSG_CODE_BIT_BOT) <= Irpt_Qout(C_CHBUF_MSG_CODE_BIT_TOP downto C_CHBUF_MSG_CODE_BIT_BOT);
-- 2nd headers all zero
-- ...
else
Irpt_Qout_to_TLP <= (others => '0');
end if;
if b1_Tx_Indicator(C_CHAN_INDEX_MRD) = '1' then
pioCplD_Qout_to_TLP <= (others => '0'); -- must be 1st argument
-- 1st header Hi
pioCplD_Qout_to_TLP(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) <= pioCplD_Qout(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT);
pioCplD_Qout_to_TLP(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) <= C_TYPE_COMPLETION; --pioCplD_Qout(C_CHBUF_TYPE_BIT_TOP downto C_CHBUF_TYPE_BIT_BOT);
pioCplD_Qout_to_TLP(C_TLP_TC_BIT_TOP downto C_TLP_TC_BIT_BOT) <= pioCplD_Qout(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT);
pioCplD_Qout_to_TLP(C_TLP_ATTR_BIT_TOP downto C_TLP_ATTR_BIT_BOT) <= pioCplD_Qout(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT);
pioCplD_Qout_to_TLP(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT) <= pioCplD_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
-- 1st header Lo
pioCplD_Qout_to_TLP(C_CPLD_CPLT_ID_BIT_TOP downto C_CPLD_CPLT_ID_BIT_BOT) <= localID;
pioCplD_Qout_to_TLP(C_CPLD_CS_BIT_TOP downto C_CPLD_CS_BIT_BOT) <= pioCplD_Qout(C_CHBUF_CPLD_CS_BIT_TOP downto C_CHBUF_CPLD_CS_BIT_BOT);
pioCplD_Qout_to_TLP(C_CPLD_BC_BIT_TOP downto C_CPLD_BC_BIT_BOT) <= pioCplD_Qout(C_CHBUF_CPLD_BC_BIT_TOP downto C_CHBUF_CPLD_BC_BIT_BOT);
-- 2nd header Hi
pioCplD_Qout_to_TLP(C_DBUS_WIDTH+C_CPLD_REQID_BIT_TOP downto C_DBUS_WIDTH+C_CPLD_REQID_BIT_BOT) <= pioCplD_Qout(C_CHBUF_CPLD_REQID_BIT_TOP downto C_CHBUF_CPLD_REQID_BIT_BOT);
pioCplD_Qout_to_TLP(C_DBUS_WIDTH+C_CPLD_TAG_BIT_TOP downto C_DBUS_WIDTH+C_CPLD_TAG_BIT_BOT) <= pioCplD_Qout(C_CHBUF_CPLD_TAG_BIT_TOP downto C_CHBUF_CPLD_TAG_BIT_BOT);
pioCplD_Qout_to_TLP(C_DBUS_WIDTH+C_CPLD_LA_BIT_TOP downto C_DBUS_WIDTH+C_CPLD_LA_BIT_BOT) <= pioCplD_Qout(C_CHBUF_CPLD_LA_BIT_TOP downto C_CHBUF_CPLD_LA_BIT_BOT);
-- no 2nd header Lo
if pioCplD_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT)
= CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG)
then
pioCplD_Req_Min_Leng <= '1';
else
pioCplD_Req_Min_Leng <= '0';
end if;
if pioCplD_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT)
= CONV_STD_LOGIC_VECTOR(2, C_TLP_FLD_WIDTH_OF_LENG)
then
pioCplD_Req_2DW_Leng <= '1';
else
pioCplD_Req_2DW_Leng <= '0';
end if;
-- Misc
Regs_Addr_pioCplD <= pioCplD_Qout(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT);
wbaddr_piocpld <= pioCplD_Qout(C_CHBUF_WB_BIT_TOP downto C_CHBUF_WB_BIT_BOT);
DDRAddr_pioCplD <= pioCplD_Qout(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT);
BAR_pioCplD <= pioCplD_Qout(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT);
pioCplD_is_0Leng <= pioCplD_Qout(C_CHBUF_0LENG_BIT);
else
pioCplD_Req_Min_Leng <= '0';
pioCplD_Req_2DW_Leng <= '0';
pioCplD_Qout_to_TLP <= (others => '0');
Regs_Addr_pioCplD <= (others => '1');
wbaddr_piocpld <= (others => '1');
DDRAddr_pioCplD <= (others => '1');
BAR_pioCplD <= (others => '1');
pioCplD_is_0Leng <= '0';
end if;
if b1_Tx_Indicator(C_CHAN_INDEX_DMA_US) = '1' then
usTlp_Qout_to_TLP <= (others => '0'); -- must be 1st argument
-- 1st header HI
usTlp_Qout_to_TLP(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) <= usTlp_Qout(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT);
usTlp_Qout_to_TLP(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) <= C_ALL_ZEROS(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT);
usTlp_Qout_to_TLP(C_TLP_TC_BIT_TOP downto C_TLP_TC_BIT_BOT) <= usTlp_Qout(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT);
usTlp_Qout_to_TLP(C_TLP_ATTR_BIT_TOP downto C_TLP_ATTR_BIT_BOT) <= usTlp_Qout(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT);
usTlp_Qout_to_TLP(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT) <= usTlp_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
-- 1st header LO
usTlp_Qout_to_TLP(C_TLP_REQID_BIT_TOP downto C_TLP_REQID_BIT_BOT) <= localID;
usTlp_Qout_to_TLP(C_TLP_TAG_BIT_TOP downto C_TLP_TAG_BIT_BOT) <= usTlp_Qout(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT);
usTlp_Qout_to_TLP(C_TLP_LAST_BE_BIT_TOP downto C_TLP_LAST_BE_BIT_BOT) <= C_ALL_ONES(C_TLP_LAST_BE_BIT_TOP downto C_TLP_LAST_BE_BIT_BOT);
usTlp_Qout_to_TLP(C_TLP_1ST_BE_BIT_TOP downto C_TLP_1ST_BE_BIT_BOT) <= C_ALL_ONES(C_TLP_1ST_BE_BIT_TOP downto C_TLP_1ST_BE_BIT_BOT);
-- 2nd header HI (Address)
-- usTlp_Qout_to_TLP(2*C_DBUS_WIDTH-1 downto C_DBUS_WIDTH) <= usTlp_Qout(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT);
if usTlp_Qout(C_CHBUF_FMT_BIT_BOT) = '1' then -- 4DW MWr
usTlp_Qout_to_TLP(2*C_DBUS_WIDTH-1 downto C_DBUS_WIDTH+32) <= usTlp_Qout(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT+32);
else
usTlp_Qout_to_TLP(2*C_DBUS_WIDTH-1 downto C_DBUS_WIDTH+32) <= usTlp_Qout(C_CHBUF_HA_BIT_TOP-32 downto C_CHBUF_HA_BIT_BOT);
end if;
-- 2nd header LO (Address)
usTlp_Qout_to_TLP(2*C_DBUS_WIDTH-1-32 downto C_DBUS_WIDTH) <= usTlp_Qout(C_CHBUF_HA_BIT_TOP-32 downto C_CHBUF_HA_BIT_BOT);
--
if usTlp_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT)
= CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG)
then
usTlp_Req_Min_Leng <= '1';
else
usTlp_Req_Min_Leng <= '0';
end if;
if usTlp_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT)
= CONV_STD_LOGIC_VECTOR(2, C_TLP_FLD_WIDTH_OF_LENG)
then
usTlp_Req_2DW_Leng <= '1';
else
usTlp_Req_2DW_Leng <= '0';
end if;
-- Misc
DDRAddr_usTlp <= usTlp_Qout(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT);
WBAddr_usTlp <= usTlp_Qout(C_CHBUF_WB_BIT_TOP downto C_CHBUF_WB_BIT_BOT);
mAddr_usTlp <= usTlp_Qout(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT); -- !! C_CHBUF_MA_BIT_BOT);
AInc_usTlp <= usTlp_Qout(C_CHBUF_AINC_BIT);
BAR_usTlp <= usTlp_Qout(C_CHBUF_DMA_BAR_BIT_TOP downto C_CHBUF_DMA_BAR_BIT_BOT);
else
usTlp_Req_Min_Leng <= '0';
usTlp_Req_2DW_Leng <= '0';
usTlp_Qout_to_TLP <= (others => '0');
DDRAddr_usTlp <= (others => '1');
WBAddr_usTlp <= (others => '1');
mAddr_usTlp <= (others => '1');
AInc_usTlp <= '1';
BAR_usTlp <= (others => '1');
end if;
if b1_Tx_Indicator(C_CHAN_INDEX_DMA_DS) = '1' then
dsMRd_Qout_to_TLP <= (others => '0'); -- must be 1st argument
-- 1st header HI
dsMRd_Qout_to_TLP(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) <= dsMRd_Qout(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT);
dsMRd_Qout_to_TLP(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) <= C_ALL_ZEROS(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT);
dsMRd_Qout_to_TLP(C_TLP_TC_BIT_TOP downto C_TLP_TC_BIT_BOT) <= dsMRd_Qout(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT);
dsMRd_Qout_to_TLP(C_TLP_ATTR_BIT_TOP downto C_TLP_ATTR_BIT_BOT) <= dsMRd_Qout(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT);
dsMRd_Qout_to_TLP(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT) <= dsMRd_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
-- 1st header LO
dsMRd_Qout_to_TLP(C_TLP_REQID_BIT_TOP downto C_TLP_REQID_BIT_BOT) <= localID;
dsMRd_Qout_to_TLP(C_TLP_TAG_BIT_TOP downto C_TLP_TAG_BIT_BOT) <= dsMRd_Qout(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT);
dsMRd_Qout_to_TLP(C_TLP_LAST_BE_BIT_TOP downto C_TLP_LAST_BE_BIT_BOT) <= C_ALL_ONES(C_TLP_LAST_BE_BIT_TOP downto C_TLP_LAST_BE_BIT_BOT);
dsMRd_Qout_to_TLP(C_TLP_1ST_BE_BIT_TOP downto C_TLP_1ST_BE_BIT_BOT) <= C_ALL_ONES(C_TLP_1ST_BE_BIT_TOP downto C_TLP_1ST_BE_BIT_BOT);
-- 2nd header (Address)
dsMRd_Qout_to_TLP(2*C_DBUS_WIDTH-1 downto C_DBUS_WIDTH) <= dsMRd_Qout(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT);
else
dsMRd_Qout_to_TLP <= (others => '0');
end if;
end if;
end process;
-- OR-wired channel buffer outputs
Trn_Qout_wire <= Irpt_Qout_to_TLP
or pioCplD_Qout_to_TLP
or dsMRd_Qout_to_TLP
or usTlp_Qout_to_TLP;
-- ---------------------------------------------------
-- State Machine: Tx output control
--
TxFSM_OutputControl :
process (user_clk, trn_tx_Reset_n)
begin
if trn_tx_Reset_n = '0' then
take_an_Arbitration <= '0';
RdNumber <= (others => '0');
RdNumber_eq_One <= '0';
RdNumber_eq_Two <= '0';
StartAddr <= (others => '0');
Shift_1st_QWord <= '0';
is_CplD <= '0';
BAR_value <= (others => '0');
RdCmd_Req <= '0';
mbuf_reset_n <= '0';
mbuf_RE_ok <= '0';
s_axis_tx_tvalid_i <= '0';
trn_tsof_n_i <= '1';
s_axis_tx_tlast_i <= '0';
s_axis_tx_tdata_i <= (others => '0');
s_axis_tx_tkeep_i <= (others => '1');
TxTrn_State <= St_TxIdle;
Trn_Qout_reg <= (others => '0');
elsif user_clk'event and user_clk = '1' then
case TxTrn_State is
when St_TxIdle =>
s_axis_tx_tvalid_i <= '0';
trn_tsof_n_i <= '1';
s_axis_tx_tlast_i <= '0';
s_axis_tx_tdata_i <= (others => '0');
s_axis_tx_tkeep_i <= (others => '1');
mbuf_RE_ok <= '0';
take_an_Arbitration <= '0';
--ported from TRN to AXI, swap DWORDs
Trn_Qout_reg <= Trn_Qout_wire;
RdNumber <= Trn_Qout_wire (C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
RdNumber_eq_One <= pioCplD_Req_Min_Leng or usTlp_Req_Min_Leng;
RdNumber_eq_Two <= pioCplD_Req_2DW_Leng or usTlp_Req_2DW_Leng;
-- BAR_value <= BAR_pioCplD and BAR_usTlp;
RdCmd_Req <= ChBuf_has_Payload;
if pioCplD_is_0Leng = '1' then
BAR_value <= '0' & CONV_STD_LOGIC_VECTOR(CINT_REGS_SPACE_BAR, C_ENCODE_BAR_NUMBER-1);
StartAddr <= C_ALL_ONES(C_DBUS_WIDTH-1 downto 0);
Shift_1st_QWord <= '1';
is_CplD <= '0';
elsif BAR_pioCplD = CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
BAR_value <= '0' & BAR_pioCplD(C_ENCODE_BAR_NUMBER-2 downto 0);
StartAddr <= (C_ALL_ONES(C_DBUS_WIDTH-1 downto C_DDR_IAWIDTH) & DDRAddr_pioCplD);
Shift_1st_QWord <= '1';
is_CplD <= '1';
elsif BAR_pioCplD = CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
BAR_value <= BAR_pioCplD(C_ENCODE_BAR_NUMBER-1 downto 0);
StartAddr <= (C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_WB_AWIDTH) & wbaddr_piocpld);
Shift_1st_QWord <= '1';
is_CplD <= '1';
-- elsif BAR_usTlp=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
-- BAR_value <= '0' & BAR_usTlp(C_ENCODE_BAR_NUMBER-2 downto 0);
-- StartAddr <= C_ALL_ONES(C_DBUS_WIDTH-1 downto C_PRAM_AWIDTH+4) & mAddr_usTlp & "00";
elsif BAR_usTlp = CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
BAR_value <= '0' & BAR_usTlp(C_ENCODE_BAR_NUMBER-2 downto 0);
StartAddr <= C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_DDR_IAWIDTH) & DDRAddr_usTlp;
Shift_1st_QWord <= not usTlp_Qout_to_TLP(C_TLP_FMT_BIT_BOT);
is_CplD <= '0';
elsif BAR_usTlp = CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
BAR_value <= BAR_usTlp(C_ENCODE_BAR_NUMBER-1 downto 0);
StartAddr <= C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_WB_AWIDTH) & WBAddr_usTlp;
Shift_1st_QWord <= not usTlp_Qout_to_TLP(C_TLP_FMT_BIT_BOT);
is_CplD <= '0';
else
BAR_value <= '0' & BAR_pioCplD(C_ENCODE_BAR_NUMBER-2 downto 0);
StartAddr <= (C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_EP_AWIDTH) & Regs_Addr_pioCplD);
-- and (C_ALL_ONES(C_DBUS_WIDTH-1 downto C_PRAM_AWIDTH+2) & mAddr_usTlp);
Shift_1st_QWord <= '1';
is_CplD <= '0';
end if;
if ChBuf_has_Payload = '1' then
TxTrn_State <= St_d_CmdReq;
mbuf_reset_n <= '1';
elsif ChBuf_No_Payload = '1' then
TxTrn_State <= St_nd_Prepare;
mbuf_reset_n <= '1';
else
TxTrn_State <= St_TxIdle;
mbuf_reset_n <= mbuf_Empty; -- '1';
end if;
--- --- --- --- --- --- --- --- --- --- --- --- ---
--- --- --- --- --- --- --- --- --- --- --- --- ---
when St_nd_Prepare =>
s_axis_tx_tlast_i <= '0';
if s_axis_tx_tready_i = '1' then
TxTrn_State <= St_nd_Header2; -- St_nd_Header1
s_axis_tx_tvalid_i <= '1';
trn_tsof_n_i <= '0';
s_axis_tx_tdata_i <= Trn_Qout_reg (C_DBUS_WIDTH-1 downto 0);
else
TxTrn_State <= St_nd_Prepare;
s_axis_tx_tvalid_i <= '0';
trn_tsof_n_i <= '1';
s_axis_tx_tdata_i <= (others => '0');
end if;
when St_nd_Header2 =>
s_axis_tx_tvalid_i <= '1';
if s_axis_tx_tready_i = '0' then
TxTrn_State <= St_nd_Header2;
take_an_Arbitration <= '0';
trn_tsof_n_i <= trn_tsof_n_i;
s_axis_tx_tlast_i <= '0';
s_axis_tx_tdata_i <= s_axis_tx_tdata_i; -- Trn_Qout_reg (C_DBUS_WIDTH-1 downto 0);
else -- 3DW header
TxTrn_State <= St_nd_HeaderLast;
take_an_Arbitration <= '1';
trn_tsof_n_i <= '1';
s_axis_tx_tlast_i <= '1';
if Trn_Qout_reg (C_TLP_FMT_BIT_BOT) = '1' then -- 4DW header
s_axis_tx_tkeep_i <= X"FF";
s_axis_tx_tdata_i <= Trn_Qout_reg (C_DBUS_WIDTH*2-1 downto C_DBUS_WIDTH);
else
s_axis_tx_tkeep_i <= X"0F";
s_axis_tx_tdata_i <= X"00000000" & Trn_Qout_reg (C_DBUS_WIDTH-1+32 downto C_DBUS_WIDTH);
end if;
end if;
when St_nd_HeaderLast =>
trn_tsof_n_i <= '1';
take_an_Arbitration <= '0';
if s_axis_tx_tready_i = '0' then
TxTrn_State <= St_nd_HeaderLast;
s_axis_tx_tvalid_i <= '1';
s_axis_tx_tlast_i <= '1';
s_axis_tx_tdata_i <= s_axis_tx_tdata_i;
s_axis_tx_tkeep_i <= s_axis_tx_tkeep_i;
else
TxTrn_State <= St_nd_Arbitration; -- St_TxIdle;
s_axis_tx_tvalid_i <= '0';
s_axis_tx_tlast_i <= '0';
s_axis_tx_tdata_i <= s_axis_tx_tdata_i;
s_axis_tx_tkeep_i <= s_axis_tx_tkeep_i;
end if;
when St_nd_Arbitration =>
trn_tsof_n_i <= '1';
TxTrn_State <= St_TxIdle;
s_axis_tx_tvalid_i <= '0';
s_axis_tx_tlast_i <= '0';
s_axis_tx_tdata_i <= s_axis_tx_tdata_i;
s_axis_tx_tkeep_i <= (others => '1');
--- --- --- --- --- --- --- --- --- --- --- --- ---
--- --- --- --- --- --- --- --- --- --- --- --- ---
when St_d_CmdReq =>
if RdCmd_Ack = '1' then
RdCmd_Req <= '0';
TxTrn_State <= St_d_CmdAck;
else
RdCmd_Req <= '1';
TxTrn_State <= St_d_CmdReq;
end if;
when St_d_CmdAck =>
s_axis_tx_tlast_i <= '0';
if mbuf_Empty = '0' and s_axis_tx_tready_i = '1' then
s_axis_tx_tvalid_i <= '0';
trn_tsof_n_i <= '1';
s_axis_tx_tdata_i <= (others => '0');
mbuf_RE_ok <= '1';
TxTrn_State <= St_d_Header0; -- St_d_Header1
else
s_axis_tx_tvalid_i <= '0';
trn_tsof_n_i <= '1';
s_axis_tx_tdata_i <= (others => '0');
mbuf_RE_ok <= '0';
TxTrn_State <= St_d_CmdAck;
end if;
when St_d_Header0 =>
if s_axis_tx_tready_i = '1' then
take_an_Arbitration <= '1';
s_axis_tx_tvalid_i <= '1';
trn_tsof_n_i <= '0';
s_axis_tx_tlast_i <= '0';
s_axis_tx_tdata_i <= Trn_Qout_reg (C_DBUS_WIDTH-1 downto 0);
mbuf_RE_ok <= not Trn_Qout_reg (C_TLP_FMT_BIT_BOT); -- '1'; -- 4DW
TxTrn_State <= St_d_Header2;
else
take_an_Arbitration <= '0';
s_axis_tx_tvalid_i <= '0';
trn_tsof_n_i <= '1';
s_axis_tx_tlast_i <= '0';
s_axis_tx_tdata_i <= s_axis_tx_tdata_i;
mbuf_RE_ok <= '0';
TxTrn_State <= St_d_Header0;
end if;
when St_d_Header2 =>
s_axis_tx_tvalid_i <= '1';
s_axis_tx_tkeep_i <= (others => '1');
take_an_Arbitration <= '0';
if s_axis_tx_tready_i = '0' then
TxTrn_State <= St_d_Header2;
s_axis_tx_tdata_i <= Trn_Qout_reg (C_DBUS_WIDTH-1 downto 0);
trn_tsof_n_i <= '0';
s_axis_tx_tlast_i <= '0';
mbuf_RE_ok <= not Trn_Qout_reg (C_TLP_FMT_BIT_BOT);
elsif Trn_Qout_reg (C_TLP_FMT_BIT_BOT) = '1' then -- 4DW header
TxTrn_State <= St_d_1st_Data; -- St_d_HeaderPlus;
s_axis_tx_tdata_i <= Trn_Qout_reg (C_DBUS_WIDTH*2-1 downto C_DBUS_WIDTH);
trn_tsof_n_i <= '1';
s_axis_tx_tlast_i <= '0';
mbuf_RE_ok <= '1';
else -- 3DW header
s_axis_tx_tdata_i <= mbuf_Qout(C_DBUS_WIDTH-1 downto 32)
& Trn_Qout_reg (C_DBUS_WIDTH+32-1 downto C_DBUS_WIDTH);
trn_tsof_n_i <= '1';
s_axis_tx_tlast_i <= not(mbuf_Qout(C_DBUS_WIDTH));
mbuf_RE_ok <= s_axis_tx_tvalid_i and mbuf_Qout(C_DBUS_WIDTH);
if mbuf_Qout(C_DBUS_WIDTH) = '0' then
TxTrn_State <= St_d_Tail_chk;
else
TxTrn_State <= St_d_1st_Data;
end if;
end if;
when St_d_1st_Data =>
mbuf_RE_ok <= s_axis_tx_tvalid_i and mbuf_Qout(C_DBUS_WIDTH);
take_an_Arbitration <= '0';
if s_axis_tx_tready_i = '0' then
TxTrn_State <= St_d_1st_Data;
s_axis_tx_tlast_i <= '0';
s_axis_tx_tdata_i <= s_axis_tx_tdata_i;
s_axis_tx_tvalid_i <= '1';
elsif mbuf_Qout(C_DBUS_WIDTH) = '0' then
TxTrn_State <= St_d_Tail_chk;
s_axis_tx_tlast_i <= '1';
s_axis_tx_tkeep_i <= X"0" & mbuf_Qout(70) & mbuf_Qout(70)
& mbuf_Qout(70) & mbuf_Qout(70);
s_axis_tx_tdata_i <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
s_axis_tx_tvalid_i <= mbuf_Qvalid; -- '0';
elsif mbuf_Qvalid = '0' then
TxTrn_State <= St_d_Payload_used;
s_axis_tx_tlast_i <= '0';
s_axis_tx_tdata_i <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
s_axis_tx_tvalid_i <= '0';
else
TxTrn_State <= St_d_Payload;
s_axis_tx_tlast_i <= '0';
s_axis_tx_tdata_i <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
s_axis_tx_tvalid_i <= '1';
end if;
when St_d_Payload =>
mbuf_RE_ok <= '1';
take_an_Arbitration <= '0';
if s_axis_tx_tready_i = '0' then
s_axis_tx_tdata_i <= s_axis_tx_tdata_i;
s_axis_tx_tlast_i <= s_axis_tx_tlast_i;
s_axis_tx_tkeep_i <= s_axis_tx_tkeep_i;
s_axis_tx_tvalid_i <= '1';
if mbuf_Qout(C_DBUS_WIDTH) = '0' then
TxTrn_State <= St_d_Tail;
elsif mbuf_Qvalid = '1' then
TxTrn_State <= St_d_Payload;
else
TxTrn_State <= St_d_Payload_used;
end if;
else
s_axis_tx_tdata_i <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
s_axis_tx_tlast_i <= not(mbuf_Qout(C_DBUS_WIDTH));
s_axis_tx_tvalid_i <= not(mbuf_Qout(C_DBUS_WIDTH)) or mbuf_Qvalid;
if mbuf_Qout(C_DBUS_WIDTH) = '0' then
TxTrn_State <= St_d_Tail_chk;
s_axis_tx_tkeep_i <= X"0" & mbuf_Qout(70) & mbuf_Qout(70)
& mbuf_Qout(70) & mbuf_Qout(70);
elsif mbuf_Qvalid = '1' then
s_axis_tx_tkeep_i <= (others => '1');
TxTrn_State <= St_d_Payload;
else
s_axis_tx_tkeep_i <= (others => '1');
TxTrn_State <= St_d_Payload_used;
end if;
end if;
when St_d_Payload_used =>
mbuf_RE_ok <= '1';
take_an_Arbitration <= '0';
if s_axis_tx_tvalid_i = '1' then
s_axis_tx_tdata_i <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
s_axis_tx_tvalid_i <= mbuf_Qvalid and s_axis_tx_tready_i;
if mbuf_Qout(C_DBUS_WIDTH) = '0' then
s_axis_tx_tlast_i <= '1';
s_axis_tx_tkeep_i <= X"0" & mbuf_Qout(70) & mbuf_Qout(70)
& mbuf_Qout(70) & mbuf_Qout(70);
else
s_axis_tx_tlast_i <= '0';
s_axis_tx_tkeep_i <= (others => '1');
end if;
if mbuf_Qvalid = '1' then
TxTrn_State <= St_d_Payload;
else
TxTrn_State <= St_d_Payload_used;
end if;
elsif mbuf_Qvalid = '1' then
s_axis_tx_tdata_i <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
s_axis_tx_tvalid_i <= '1';
if mbuf_Qout(C_DBUS_WIDTH) = '0' then
s_axis_tx_tlast_i <= '1';
s_axis_tx_tkeep_i <= X"0" & mbuf_Qout(70) & mbuf_Qout(70)
& mbuf_Qout(70) & mbuf_Qout(70);
else
s_axis_tx_tlast_i <= '0';
s_axis_tx_tkeep_i <= (others => '1');
end if;
if mbuf_Qout(C_DBUS_WIDTH) = '0' then
TxTrn_State <= St_d_Tail_chk;
else
TxTrn_State <= St_d_Payload;
end if;
else
TxTrn_State <= St_d_Payload_used;
s_axis_tx_tdata_i <= s_axis_tx_tdata_i;
s_axis_tx_tlast_i <= s_axis_tx_tlast_i;
s_axis_tx_tkeep_i <= s_axis_tx_tkeep_i;
s_axis_tx_tvalid_i <= '0';
end if;
when St_d_Tail =>
take_an_Arbitration <= '0';
mbuf_RE_ok <= '0';
s_axis_tx_tvalid_i <= '1';
if s_axis_tx_tready_i = '0' then
TxTrn_State <= St_d_Tail;
s_axis_tx_tlast_i <= s_axis_tx_tlast_i;
s_axis_tx_tkeep_i <= s_axis_tx_tkeep_i;
s_axis_tx_tdata_i <= s_axis_tx_tdata_i;
else
TxTrn_State <= St_d_Tail_chk;
s_axis_tx_tlast_i <= '1';
s_axis_tx_tkeep_i <= X"0" & mbuf_Qout(70) & mbuf_Qout(70)
& mbuf_Qout(70) & mbuf_Qout(70);
s_axis_tx_tdata_i <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
end if;
when St_d_Tail_chk =>
take_an_Arbitration <= '0';
mbuf_RE_ok <= '0';
if s_axis_tx_tready_i = '0' then
s_axis_tx_tvalid_i <= '1';
s_axis_tx_tlast_i <= '1';
s_axis_tx_tkeep_i <= s_axis_tx_tkeep_i;
s_axis_tx_tdata_i <= s_axis_tx_tdata_i;
TxTrn_State <= St_d_Tail_chk;
else
s_axis_tx_tvalid_i <= '0';
s_axis_tx_tlast_i <= '0';
s_axis_tx_tdata_i <= (others => '0');
s_axis_tx_tkeep_i <= (others => '1');
TxTrn_State <= St_TxIdle;
end if;
when others =>
take_an_Arbitration <= '0';
RdNumber <= (others => '0');
RdNumber_eq_One <= '0';
RdNumber_eq_Two <= '0';
StartAddr <= (others => '0');
BAR_value <= (others => '0');
RdCmd_Req <= '0';
mbuf_reset_n <= '1';
mbuf_RE_ok <= '0';
s_axis_tx_tvalid_i <= '0';
trn_tsof_n_i <= '1';
s_axis_tx_tlast_i <= '0';
s_axis_tx_tdata_i <= (others => '0');
s_axis_tx_tkeep_i <= (others => '1');
TxTrn_State <= St_TxIdle;
end case;
end if;
end process;
---------------------------------------------------------------------------------
-- Synchronous Accumulation: us_DMA_Bytes
--
Synch_Acc_us_DMA_Bytes :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
us_DMA_Bytes_i <= '0' & s_axis_tx_tdata_i(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) & "00";
if s_axis_tx_tdata_i(C_TLP_FMT_BIT_TOP) = '1'
and s_axis_tx_tdata_i(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
= C_ALL_ZEROS(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) then
us_DMA_Bytes_Add_i <= not trn_tsof_n_i
and s_axis_tx_tvalid_i
and s_axis_tx_tready_i;
else
us_DMA_Bytes_Add_i <= '0';
end if;
end if;
end process;
end architecture Behavioral;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/RADIX22FFT_SDNF1_3_block.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_3_block
-- Source Path: ifft_16_bit/IFFT HDL Optimized/RADIX22FFT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_3_block IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
twdlXdin_2_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_2_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_4_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_4_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_3_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_3_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_4_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_4_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_3_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_3_block;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_3_block IS
-- Signals
SIGNAL twdlXdin_2_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_2_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_4_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_4_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_3_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_3_im_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_4_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_4_im_tmp : signed(16 DOWNTO 0); -- sfix17
BEGIN
twdlXdin_2_re_signed <= signed(twdlXdin_2_re);
twdlXdin_2_im_signed <= signed(twdlXdin_2_im);
twdlXdin_4_re_signed <= signed(twdlXdin_4_re);
twdlXdin_4_im_signed <= signed(twdlXdin_4_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_2_re_signed,
twdlXdin_2_im_signed, twdlXdin_4_re_signed, twdlXdin_4_im_signed,
twdlXdin_1_vld)
VARIABLE sra_temp : signed(17 DOWNTO 0);
VARIABLE sra_temp_0 : signed(17 DOWNTO 0);
VARIABLE sra_temp_1 : signed(17 DOWNTO 0);
VARIABLE sra_temp_2 : signed(17 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg_next <= resize(twdlXdin_2_re_signed, 18) + resize(twdlXdin_4_re_signed, 18);
Radix22ButterflyG1_NF_btf2_re_reg_next <= resize(twdlXdin_2_re_signed, 18) - resize(twdlXdin_4_re_signed, 18);
Radix22ButterflyG1_NF_btf1_im_reg_next <= resize(twdlXdin_2_im_signed, 18) + resize(twdlXdin_4_im_signed, 18);
Radix22ButterflyG1_NF_btf2_im_reg_next <= resize(twdlXdin_2_im_signed, 18) - resize(twdlXdin_4_im_signed, 18);
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_re_reg, 1);
dout_3_re_tmp <= sra_temp(16 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_im_reg, 1);
dout_3_im_tmp <= sra_temp_0(16 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_re_reg, 1);
dout_4_re_tmp <= sra_temp_1(16 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_im_reg, 1);
dout_4_im_tmp <= sra_temp_2(16 DOWNTO 0);
dout_3_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_3_re <= std_logic_vector(dout_3_re_tmp);
dout_3_im <= std_logic_vector(dout_3_im_tmp);
dout_4_re <= std_logic_vector(dout_4_re_tmp);
dout_4_im <= std_logic_vector(dout_4_im_tmp);
END rtl;
|
entity tb_repro3_1 is
end tb_repro3_1;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_repro3_1 is
signal clk : std_logic;
signal led : std_logic_vector(7 downto 0);
begin
dut: entity work.repro3_1
port map (clk, led);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
pulse;
assert led = x"01" severity failure;
pulse;
assert led = x"02" severity failure;
wait;
end process;
end behav;
|
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utils_pkg.all;
entity temp_controller is
generic
(
CONV_D : natural;
CONV_CMD_D : natural;
OW_US_D : positive;
PWM_N : positive;
PWM_MIN_LVL : positive;
PWM_EN_ON_D : natural;
P_SHIFT_N : integer;
I_SHIFT_N : integer;
TEMP_SETPOINT : integer
);
port
(
clk : in std_logic;
reset : in std_logic;
ow_in : in std_logic;
enable_in : in std_logic;
ow_out : out std_logic;
temp_out : out signed(16 - 1 downto 0);
temp_out_f : out std_logic;
temp_error_out : out std_logic;
pwm_out : out std_logic;
ow_pullup_out : out std_logic
);
end entity;
architecture rtl of temp_controller is
signal reset_ow : std_logic;
signal data_in : std_logic_vector(8 - 1 downto 0);
signal data_in_f : std_logic;
signal receive_data_f : std_logic;
signal busy : std_logic;
signal data_out : std_logic_vector(8 - 1 downto 0);
signal data_out_f : std_logic;
signal err : std_logic;
signal err_id : unsigned(1 downto 0);
signal crc : std_logic_vector(8 - 1 downto 0);
signal pwm_enable : std_logic;
signal temp : signed(16 - 1 downto 0);
signal temp_f : std_logic;
signal pid_out : signed(temp'range);
signal mod_lvl : unsigned(PWM_N - 1 downto 0);
signal mod_lvl_f : std_logic;
signal conv : std_logic;
function trunc_to_unsigned(arg : signed) return unsigned is
begin
return unsigned(std_logic_vector(arg));
end function;
function clamp_to_unsigned(arg : signed) return unsigned is
variable res : unsigned(arg'high - 1 downto 0);
begin
-- Shift value so it is always positive
res := trunc_to_unsigned(resize(arg + to_signed(2**(arg'length - 1) - 1
, arg'length)
, res'length));
return res;
end function;
begin
temp_out <= temp;
temp_out_f <= temp_f;
-- Perform temperature reading at predefined intervals
conv_p: process(clk, reset)
variable timer : unsigned(ceil_log2(CONV_D) downto 0);
begin
if reset = '1' then
timer := to_unsigned(CONV_D, timer'length);
conv <= '0';
elsif rising_edge(clk) then
conv <= '0';
if timer < CONV_D then
timer := timer + 1;
else
conv <= '1';
timer := (others => '0');
end if;
end if;
end process;
ds18b20_p: entity work.ds18b20(rtl)
generic map
(
CONV_DELAY_VAL => CONV_CMD_D
)
port map
(
clk => clk,
reset => reset,
conv_in_f => conv,
data_in => data_out,
data_in_f => data_out_f,
busy_in => busy,
error_in => err,
error_id_in => err_id,
reset_ow_out => reset_ow,
data_out => data_in,
data_out_f => data_in_f,
receive_data_out_f => receive_data_f,
temp_out => temp,
temp_out_f => temp_f,
crc_in => crc,
temp_error_out => temp_error_out,
pullup_out => ow_pullup_out
);
ow_p: entity work.one_wire(rtl)
generic map
(
US_D => OW_US_D
)
port map
(
clk => clk,
reset => reset,
reset_ow => reset_ow,
ow_in => ow_in,
data_in => data_in,
data_in_f => data_in_f,
receive_data_f => receive_data_f,
ow_out => ow_out,
error_out => err,
error_id_out => err_id,
busy_out => busy,
data_out => data_out,
data_out_f => data_out_f,
crc_out => crc
);
pid_p: entity work.pid(rtl)
generic map
(
P_SHIFT_N => P_SHIFT_N,
I_SHIFT_N => I_SHIFT_N,
BITS_N => temp'length,
INIT_OUT_VAL => 0
)
port map
(
clk => clk,
reset => reset,
upd_clk_in => temp_f,
setpoint_in => to_signed(TEMP_SETPOINT, temp'length),
pid_in => temp,
pid_out => pid_out
);
-- Invert, clamp and scale PID output for PWM controller input
mod_lvl <= resize(shift_right(clamp_to_unsigned(-pid_out)
, pid_out'length - mod_lvl'length)
, mod_lvl'length);
pwm_p: entity work.pwm(rtl)
generic map
(
COUNTER_N => PWM_N,
MIN_MOD_LVL => PWM_MIN_LVL,
ENABLE_ON_D => PWM_EN_ON_D
)
port map
(
clk => clk,
reset => reset,
enable_in => enable_in,
mod_lvl_in => mod_lvl,
mod_lvl_f_in => temp_f,
pwm_out => pwm_out
);
end;
|
-----------------------------------------------
-- Module Name: HexDigSSegCntrl - control --
-----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.Hex4Digs_2_SSeg_Package.all;
entity HexDigSSegCntrl is
port ( clock : in std_logic;
sw0 : in std_logic;
btns : in std_logic_vector (3 downto 0);
anodes : out std_logic_vector (3 downto 0);
cathodes : out std_logic_vector (7 downto 0));
end HexDigSSegCntrl;
architecture control of HexDigSSegCntrl is
begin
-- c5Hz: CDiv port map (clock, TC5Hz, clk5Hz);
---- c16Hz: CDiv port map (clock, TC16Hz, clk16Hz);
---- c20Hz: CDiv port map (clock, TC20Hz, clk20Hz);
---- c30Hz: CDiv port map (clock, TC30Hz, clk30Hz);
-- c3Hz: CDiv port map (clock, TC3Hz, clk3Hz);
HexDs: Hex4Digs_2_SSeg port map (clock, sw0, btns, anodes, cathodes);
-- process (sw1, clk5Hz, clk16Hz) -- control clocks
-- process (sw1, clk5Hz, clk20Hz) -- control clocks
-- process (sw1, clk5Hz, clk30Hz) -- control clocks
-- process (sw1, clk5Hz, clk3Hz) -- control clocks
-- begin
-- if (sw1 = '0') then
-- clk <= clk5Hz;
-- else
---- clk <= clk16Hz;
---- clk <= clk20Hz;
---- clk <= clk30Hz;
-- clk <= clk3Hz;
-- end if;
-- end process;
-- process (clk)
-- begin
-- if rising_edge(clk) then
-- en <= not en;
-- end if;
-- end process;
--
-- process (clk)
-- begin
-- if rising_edge(clk) then
-- if en = '1' then
-- c0 <= c0 + 1;
-- cntr(0) <= '1';
-- if (c0 = 15) then
-- c1 <= c1 + 1;
-- cntr(1) <= '1';
-- if (c1 = 15) then
-- c2 <= c2 + 1;
-- cntr(2) <= '1';
-- if (c2 = 15) then
-- c3 <= c3 + 1;
-- cntr(3) <= '1';
-- end if;
-- end if;
-- end if;
-- else
-- cntr <= "0000";
-- end if;
-- end if;
-- end process;
end control;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_b_e
--
-- Generated
-- by: wig
-- on: Wed Jul 19 05:44:57 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-rtl-a.vhd,v 1.2 2006/07/19 07:35:16 wig Exp $
-- $Date: 2006/07/19 07:35:16 $
-- $Log: inst_b_e-rtl-a.vhd,v $
-- Revision 1.2 2006/07/19 07:35:16 wig
-- Updated testcases.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
HOOK: global text to add to head of architecture, here is %::inst%
--
--
-- Start of Generated Architecture rtl of inst_b_e
--
architecture rtl of inst_b_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_xa_e -- mulitple instantiated
-- No Generated Generics
port (
-- Generated Port for Entity inst_xa_e
port_xa_i : in std_ulogic; -- signal test aa to ba
port_xa_o : out std_ulogic -- open signal to create port
-- End of Generated Port for Entity inst_xa_e
);
end component;
-- ---------
component inst_bb_e -- bb instance
-- No Generated Generics
port (
-- Generated Port for Entity inst_bb_e
port_bb_o : out std_ulogic_vector(7 downto 0) -- vector test bb to ab
-- End of Generated Port for Entity inst_bb_e
);
end component;
-- ---------
component inst_vb_e -- verilog udc
-- No Generated Generics
-- Generated Generics for Entity inst_vb_e
-- End of Generated Generics for Entity inst_vb_e
-- No Generated Port
end component;
-- ---------
component inst_be_i -- no verilog udc here
-- No Generated Generics
-- Generated Generics for Entity inst_be_i
-- End of Generated Generics for Entity inst_be_i
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
signal signal_aa_ba : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal signal_bb_ab : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
udc: THIS GOES TO DECL of inst_b_i
begin
udc: THIS ARE TWO LINES in BODY of inst_b_i
SECOND LINE
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
signal_aa_ba <= p_mix_signal_aa_ba_gi; -- __I_I_BIT_PORT
p_mix_signal_bb_ab_go <= signal_bb_ab; -- __I_O_BUS_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_ba_i
inst_ba_i: inst_xa_e -- mulitple instantiated
port map (
port_xa_i => signal_aa_ba, -- signal test aa to ba
port_xa_o => open -- open signal to create port
);
-- End of Generated Instance Port Map for inst_ba_i
-- Generated Instance Port Map for inst_bb_i
inst_bb_i: inst_bb_e -- bb instance
port map (
port_bb_o => signal_bb_ab -- vector test bb to ab
);
-- End of Generated Instance Port Map for inst_bb_i
-- Generated Instance Port Map for inst_bc_i
inst_bc_i: inst_vb_e -- verilog udc
;
-- End of Generated Instance Port Map for inst_bc_i
-- Generated Instance Port Map for inst_bd_i
inst_bd_i: inst_vb_e -- no verilog udc here, but multiple instantiations
;
-- End of Generated Instance Port Map for inst_bd_i
-- Generated Instance Port Map for inst_be_i
inst_be_i: inst_be_i -- no verilog udc here
;
-- End of Generated Instance Port Map for inst_be_i
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
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`protect end_protected
|
package fifo_pkg is
signal sig1 : std_logic;
end package;
package fifo_pkg is
signal sig1 : std_logic;
end package;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity data_logger is
end entity data_logger;
-- code from book
architecture high_level of data_logger is
subtype byte is bit_vector(7 downto 0);
type byte_array is array (integer range <>) of byte;
function resolver ( bytes : byte_array ) return byte is
begin
if bytes'length > 0 then
return bytes( bytes'left );
else
return X"00";
end if;
end function resolver;
subtype resolved_byte is resolver byte;
procedure reg ( signal clock, out_enable : in bit;
signal d : in byte;
signal q : out resolved_byte ) is
variable stored_byte : byte;
begin
loop
if clock = '1' then
stored_byte := d;
end if;
if out_enable = '1' then
q <= stored_byte;
else
q <= null;
end if;
wait on clock, out_enable, d;
end loop;
end procedure reg;
signal data_bus : resolved_byte bus;
-- . . .
-- not in book
signal a_reg_clk, b_reg_clk, a_reg_read, b_reg_read : bit := '0';
signal port_a, port_b : byte := X"00";
-- end not in book
begin
a_reg : reg (a_reg_clk, a_reg_read, port_a, data_bus);
b_reg : reg (b_reg_clk, b_reg_read, port_b, data_bus);
-- . . .
-- not in book
stimulus : process is
begin
port_a <= X"11"; a_reg_clk <= '1', '0' after 5 ns; wait for 10 ns;
a_reg_read <= '1', '0' after 5 ns; wait for 10 ns;
port_b <= X"21"; b_reg_clk <= '1', '0' after 5 ns; wait for 10 ns;
b_reg_read <= '1', '0' after 5 ns; wait for 10 ns;
a_reg_read <= '1', '0' after 5 ns;
b_reg_read <= '1', '0' after 5 ns;
wait;
end process stimulus;
-- end not in book
end architecture high_level;
-- end code from book
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity data_logger is
end entity data_logger;
-- code from book
architecture high_level of data_logger is
subtype byte is bit_vector(7 downto 0);
type byte_array is array (integer range <>) of byte;
function resolver ( bytes : byte_array ) return byte is
begin
if bytes'length > 0 then
return bytes( bytes'left );
else
return X"00";
end if;
end function resolver;
subtype resolved_byte is resolver byte;
procedure reg ( signal clock, out_enable : in bit;
signal d : in byte;
signal q : out resolved_byte ) is
variable stored_byte : byte;
begin
loop
if clock = '1' then
stored_byte := d;
end if;
if out_enable = '1' then
q <= stored_byte;
else
q <= null;
end if;
wait on clock, out_enable, d;
end loop;
end procedure reg;
signal data_bus : resolved_byte bus;
-- . . .
-- not in book
signal a_reg_clk, b_reg_clk, a_reg_read, b_reg_read : bit := '0';
signal port_a, port_b : byte := X"00";
-- end not in book
begin
a_reg : reg (a_reg_clk, a_reg_read, port_a, data_bus);
b_reg : reg (b_reg_clk, b_reg_read, port_b, data_bus);
-- . . .
-- not in book
stimulus : process is
begin
port_a <= X"11"; a_reg_clk <= '1', '0' after 5 ns; wait for 10 ns;
a_reg_read <= '1', '0' after 5 ns; wait for 10 ns;
port_b <= X"21"; b_reg_clk <= '1', '0' after 5 ns; wait for 10 ns;
b_reg_read <= '1', '0' after 5 ns; wait for 10 ns;
a_reg_read <= '1', '0' after 5 ns;
b_reg_read <= '1', '0' after 5 ns;
wait;
end process stimulus;
-- end not in book
end architecture high_level;
-- end code from book
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity data_logger is
end entity data_logger;
-- code from book
architecture high_level of data_logger is
subtype byte is bit_vector(7 downto 0);
type byte_array is array (integer range <>) of byte;
function resolver ( bytes : byte_array ) return byte is
begin
if bytes'length > 0 then
return bytes( bytes'left );
else
return X"00";
end if;
end function resolver;
subtype resolved_byte is resolver byte;
procedure reg ( signal clock, out_enable : in bit;
signal d : in byte;
signal q : out resolved_byte ) is
variable stored_byte : byte;
begin
loop
if clock = '1' then
stored_byte := d;
end if;
if out_enable = '1' then
q <= stored_byte;
else
q <= null;
end if;
wait on clock, out_enable, d;
end loop;
end procedure reg;
signal data_bus : resolved_byte bus;
-- . . .
-- not in book
signal a_reg_clk, b_reg_clk, a_reg_read, b_reg_read : bit := '0';
signal port_a, port_b : byte := X"00";
-- end not in book
begin
a_reg : reg (a_reg_clk, a_reg_read, port_a, data_bus);
b_reg : reg (b_reg_clk, b_reg_read, port_b, data_bus);
-- . . .
-- not in book
stimulus : process is
begin
port_a <= X"11"; a_reg_clk <= '1', '0' after 5 ns; wait for 10 ns;
a_reg_read <= '1', '0' after 5 ns; wait for 10 ns;
port_b <= X"21"; b_reg_clk <= '1', '0' after 5 ns; wait for 10 ns;
b_reg_read <= '1', '0' after 5 ns; wait for 10 ns;
a_reg_read <= '1', '0' after 5 ns;
b_reg_read <= '1', '0' after 5 ns;
wait;
end process stimulus;
-- end not in book
end architecture high_level;
-- end code from book
|
--
-- my_fpga_test.vhdl
--
library ieee;
use ieee.std_logic_1164.all;
use work.tbmsgs.all;
entity my_fpga_test is
end entity;
architecture sim of my_fpga_test is
signal in1 : std_logic := '0';
signal in2 : std_logic := '0';
signal out1 : std_logic;
signal out2 : std_logic;
begin
uut : entity work.my_fpga port map (
in1 => in1,
in2 => in2,
out1 => out1,
out2 => out2
);
test : process
begin
testcase("my_fpga", 4);
wait for 1 us;
check(out1 = '0', "out1 should be '0'");
check(out2 = '0', "out2 should be '0'");
tested("inputs set to 00");
in1 <= '1';
wait for 1 us;
check(out1 = '1', "out1 should be '1'");
check(out2 = '0', "out2 should be '0'");
tested("inputs set to 01");
in2 <= '1';
wait for 1 us;
check(out1 = '1', "out1 should be '1'");
check(out2 = '1', "out2 should be '1'");
tested("inputs set to 11");
in1 <= '0';
wait for 1 us;
check(out1 = '1', "out1 should be '1'");
check(out2 = '0', "out2 should be '0'");
tested("inputs set to 10");
testcase_complete;
wait;
end process;
end;
|
--
-- my_fpga_test.vhdl
--
library ieee;
use ieee.std_logic_1164.all;
use work.tbmsgs.all;
entity my_fpga_test is
end entity;
architecture sim of my_fpga_test is
signal in1 : std_logic := '0';
signal in2 : std_logic := '0';
signal out1 : std_logic;
signal out2 : std_logic;
begin
uut : entity work.my_fpga port map (
in1 => in1,
in2 => in2,
out1 => out1,
out2 => out2
);
test : process
begin
testcase("my_fpga", 4);
wait for 1 us;
check(out1 = '0', "out1 should be '0'");
check(out2 = '0', "out2 should be '0'");
tested("inputs set to 00");
in1 <= '1';
wait for 1 us;
check(out1 = '1', "out1 should be '1'");
check(out2 = '0', "out2 should be '0'");
tested("inputs set to 01");
in2 <= '1';
wait for 1 us;
check(out1 = '1', "out1 should be '1'");
check(out2 = '1', "out2 should be '1'");
tested("inputs set to 11");
in1 <= '0';
wait for 1 us;
check(out1 = '1', "out1 should be '1'");
check(out2 = '0', "out2 should be '0'");
tested("inputs set to 10");
testcase_complete;
wait;
end process;
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:29:01 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_inverter_0_0/system_inverter_0_0_stub.vhdl
-- Design : system_inverter_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_inverter_0_0 is
Port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
end system_inverter_0_0;
architecture stub of system_inverter_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "x,x_not";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "inverter,Vivado 2016.4";
begin
end;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/Complex3Multiply_block6.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Complex3Multiply_block6
-- Source Path: fft_16_bit/FFT HDL Optimized/TWDLMULT_SDNF1_3/Complex3Multiply
-- Hierarchy Level: 3
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Complex3Multiply_block6 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
din1_re_dly3 : IN std_logic_vector(19 DOWNTO 0); -- sfix20
din1_im_dly3 : IN std_logic_vector(19 DOWNTO 0); -- sfix20
din1_vld_dly3 : IN std_logic;
twdl_3_11_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_11_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
softReset : IN std_logic;
twdlXdin_11_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_11_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin1_vld : OUT std_logic
);
END Complex3Multiply_block6;
ARCHITECTURE rtl OF Complex3Multiply_block6 IS
-- Signals
SIGNAL din1_re_dly3_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_im_dly3_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL din_sum : signed(20 DOWNTO 0); -- sfix21
SIGNAL twdl_3_11_re_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_re_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_11_im_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_im_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL adder_add_cast : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL adder_add_cast_1 : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL twdl_sum : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL Complex3Multiply_din1_re_pipe1 : signed(19 DOWNTO 0); -- sfix20
SIGNAL Complex3Multiply_din1_im_pipe1 : signed(19 DOWNTO 0); -- sfix20
SIGNAL Complex3Multiply_din1_sum_pipe1 : signed(20 DOWNTO 0); -- sfix21
SIGNAL Complex3Multiply_prodOfRe_pipe1 : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Multiply_ProdOfIm_pipe1 : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Multiply_prodOfSum_pipe1 : signed(38 DOWNTO 0); -- sfix39
SIGNAL Complex3Multiply_twiddle_re_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_im_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_sum_pipe1 : signed(17 DOWNTO 0); -- sfix18
SIGNAL prodOfRe : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL prodOfIm : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL prodOfSum : signed(38 DOWNTO 0); -- sfix39_En15
SIGNAL din_vld_dly1 : std_logic;
SIGNAL din_vld_dly2 : std_logic;
SIGNAL din_vld_dly3 : std_logic;
SIGNAL prod_vld : std_logic;
SIGNAL Complex3Add_tmpResult_reg : signed(38 DOWNTO 0); -- sfix39
SIGNAL Complex3Add_multRes_re_reg1 : signed(37 DOWNTO 0); -- sfix38
SIGNAL Complex3Add_multRes_re_reg2 : signed(37 DOWNTO 0); -- sfix38
SIGNAL Complex3Add_multRes_im_reg : signed(39 DOWNTO 0); -- sfix40
SIGNAL Complex3Add_prod_vld_reg1 : std_logic;
SIGNAL Complex3Add_prod_vld_reg2 : std_logic;
SIGNAL Complex3Add_prodOfSum_reg : signed(38 DOWNTO 0); -- sfix39
SIGNAL Complex3Add_tmpResult_reg_next : signed(38 DOWNTO 0); -- sfix39_En15
SIGNAL Complex3Add_multRes_re_reg1_next : signed(37 DOWNTO 0); -- sfix38_En15
SIGNAL Complex3Add_multRes_re_reg2_next : signed(37 DOWNTO 0); -- sfix38_En15
SIGNAL Complex3Add_multRes_im_reg_next : signed(39 DOWNTO 0); -- sfix40_En15
SIGNAL Complex3Add_prod_vld_reg1_next : std_logic;
SIGNAL Complex3Add_prod_vld_reg2_next : std_logic;
SIGNAL Complex3Add_prodOfSum_reg_next : signed(38 DOWNTO 0); -- sfix39_En15
SIGNAL multResFP_re : signed(37 DOWNTO 0); -- sfix38_En15
SIGNAL multResFP_im : signed(39 DOWNTO 0); -- sfix40_En15
SIGNAL twdlXdin_11_re_tmp : signed(19 DOWNTO 0); -- sfix20
SIGNAL twdlXdin_11_im_tmp : signed(19 DOWNTO 0); -- sfix20
BEGIN
din1_re_dly3_signed <= signed(din1_re_dly3);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_re_reg <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_re_reg <= to_signed(16#00000#, 20);
ELSE
din_re_reg <= din1_re_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_process;
din1_im_dly3_signed <= signed(din1_im_dly3);
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_im_reg <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_im_reg <= to_signed(16#00000#, 20);
ELSE
din_im_reg <= din1_im_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_1_process;
din_sum <= resize(din_re_reg, 21) + resize(din_im_reg, 21);
twdl_3_11_re_signed <= signed(twdl_3_11_re);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSE
twdl_re_reg <= twdl_3_11_re_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_2_process;
twdl_3_11_im_signed <= signed(twdl_3_11_im);
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSE
twdl_im_reg <= twdl_3_11_im_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_3_process;
adder_add_cast <= resize(twdl_re_reg, 18);
adder_add_cast_1 <= resize(twdl_im_reg, 18);
twdl_sum <= adder_add_cast + adder_add_cast_1;
-- Complex3Multiply
Complex3Multiply_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prodOfRe <= Complex3Multiply_prodOfRe_pipe1;
prodOfIm <= Complex3Multiply_ProdOfIm_pipe1;
prodOfSum <= Complex3Multiply_prodOfSum_pipe1;
Complex3Multiply_twiddle_re_pipe1 <= twdl_re_reg;
Complex3Multiply_twiddle_im_pipe1 <= twdl_im_reg;
Complex3Multiply_twiddle_sum_pipe1 <= twdl_sum;
Complex3Multiply_din1_re_pipe1 <= din_re_reg;
Complex3Multiply_din1_im_pipe1 <= din_im_reg;
Complex3Multiply_din1_sum_pipe1 <= din_sum;
Complex3Multiply_prodOfRe_pipe1 <= Complex3Multiply_din1_re_pipe1 * Complex3Multiply_twiddle_re_pipe1;
Complex3Multiply_ProdOfIm_pipe1 <= Complex3Multiply_din1_im_pipe1 * Complex3Multiply_twiddle_im_pipe1;
Complex3Multiply_prodOfSum_pipe1 <= Complex3Multiply_din1_sum_pipe1 * Complex3Multiply_twiddle_sum_pipe1;
END IF;
END IF;
END PROCESS Complex3Multiply_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly1 <= din1_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly2 <= din_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly3 <= din_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
prod_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prod_vld <= din_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_7_process;
-- Complex3Add
Complex3Add_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Complex3Add_prodOfSum_reg <= to_signed(0, 39);
Complex3Add_tmpResult_reg <= to_signed(0, 39);
Complex3Add_multRes_re_reg1 <= to_signed(0, 38);
Complex3Add_multRes_re_reg2 <= to_signed(0, 38);
Complex3Add_multRes_im_reg <= to_signed(0, 40);
Complex3Add_prod_vld_reg1 <= '0';
Complex3Add_prod_vld_reg2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Complex3Add_tmpResult_reg <= Complex3Add_tmpResult_reg_next;
Complex3Add_multRes_re_reg1 <= Complex3Add_multRes_re_reg1_next;
Complex3Add_multRes_re_reg2 <= Complex3Add_multRes_re_reg2_next;
Complex3Add_multRes_im_reg <= Complex3Add_multRes_im_reg_next;
Complex3Add_prod_vld_reg1 <= Complex3Add_prod_vld_reg1_next;
Complex3Add_prod_vld_reg2 <= Complex3Add_prod_vld_reg2_next;
Complex3Add_prodOfSum_reg <= Complex3Add_prodOfSum_reg_next;
END IF;
END IF;
END PROCESS Complex3Add_process;
Complex3Add_output : PROCESS (Complex3Add_tmpResult_reg, Complex3Add_multRes_re_reg1,
Complex3Add_multRes_re_reg2, Complex3Add_multRes_im_reg,
Complex3Add_prod_vld_reg1, Complex3Add_prod_vld_reg2,
Complex3Add_prodOfSum_reg, prodOfRe, prodOfIm, prodOfSum, prod_vld)
VARIABLE sub_cast : signed(37 DOWNTO 0);
VARIABLE sub_cast_0 : signed(37 DOWNTO 0);
VARIABLE sub_cast_1 : signed(39 DOWNTO 0);
VARIABLE sub_cast_2 : signed(39 DOWNTO 0);
VARIABLE add_cast : signed(37 DOWNTO 0);
VARIABLE add_cast_0 : signed(37 DOWNTO 0);
VARIABLE add_temp : signed(37 DOWNTO 0);
BEGIN
Complex3Add_tmpResult_reg_next <= Complex3Add_tmpResult_reg;
Complex3Add_multRes_re_reg1_next <= Complex3Add_multRes_re_reg1;
Complex3Add_prodOfSum_reg_next <= Complex3Add_prodOfSum_reg;
Complex3Add_multRes_re_reg2_next <= Complex3Add_multRes_re_reg1;
IF prod_vld = '1' THEN
sub_cast := resize(prodOfRe, 38);
sub_cast_0 := resize(prodOfIm, 38);
Complex3Add_multRes_re_reg1_next <= sub_cast - sub_cast_0;
END IF;
sub_cast_1 := resize(Complex3Add_prodOfSum_reg, 40);
sub_cast_2 := resize(Complex3Add_tmpResult_reg, 40);
Complex3Add_multRes_im_reg_next <= sub_cast_1 - sub_cast_2;
IF prod_vld = '1' THEN
add_cast := resize(prodOfRe, 38);
add_cast_0 := resize(prodOfIm, 38);
add_temp := add_cast + add_cast_0;
Complex3Add_tmpResult_reg_next <= resize(add_temp, 39);
END IF;
IF prod_vld = '1' THEN
Complex3Add_prodOfSum_reg_next <= prodOfSum;
END IF;
Complex3Add_prod_vld_reg2_next <= Complex3Add_prod_vld_reg1;
Complex3Add_prod_vld_reg1_next <= prod_vld;
multResFP_re <= Complex3Add_multRes_re_reg2;
multResFP_im <= Complex3Add_multRes_im_reg;
twdlXdin1_vld <= Complex3Add_prod_vld_reg2;
END PROCESS Complex3Add_output;
twdlXdin_11_re_tmp <= multResFP_re(34 DOWNTO 15);
twdlXdin_11_re <= std_logic_vector(twdlXdin_11_re_tmp);
twdlXdin_11_im_tmp <= multResFP_im(34 DOWNTO 15);
twdlXdin_11_im <= std_logic_vector(twdlXdin_11_im_tmp);
END rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.ALL;
entity dp_sram is
port (
-- CLOCK
CLK : in std_logic; -- 32MHz
nRESET : in std_logic;
-- PORT A
DI_A : in STD_LOGIC_VECTOR(7 downto 0);
DO_A : inout STD_LOGIC_VECTOR(7 downto 0);
ADDR_A : in STD_LOGIC_VECTOR(17 downto 0);
nWE_A : in std_logic;
nCS_A : in std_logic;
nOE_A : in std_logic;
nWAIT_A : out std_logic;
-- PORT B
DI_B : in STD_LOGIC_VECTOR(31 downto 0);
DO_B : inout STD_LOGIC_VECTOR(31 downto 0);
ADDR_B : in STD_LOGIC_VECTOR(31 downto 2);
nWE_B : in std_logic;
nCS_B : in std_logic;
nOE_B : in std_logic;
WAIT_B : out std_logic;
MEM_MASK_B : in STD_LOGIC_VECTOR(3 downto 0);
-- SRAM
SRAM_A : out std_logic_vector(17 downto 0);
SRAM_D : inout std_logic_vector(15 downto 0);
SRAM_WE : out std_logic;
SRAM_OE : out std_logic;
SRAM_CE0 : out std_logic;
SRAM_CE1 : out std_logic;
SRAM_LB : out std_logic;
SRAM_UB : out std_logic
);
end dp_sram;
architecture dp_sram_arch of dp_sram is
--"00" = big_endian; "11" = little_endian
constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "11";
-- FSM States
type STATE_TYPE is ( IDLE,
ST_READ1_A,
ST_WRITE1_A,
ST_READ1_B, ST_READ2_B,
ST_WRITE1_B, ST_WRITE2_B, ST_WRITE3_B );
signal STATE : STATE_TYPE := IDLE;
signal A_LOCK : std_logic;
signal B_LOCK : std_logic;
signal nWAIT_B : std_logic;
signal nCS_B_L : std_logic;
signal nWE_B_L : std_logic;
signal MEM_MASK_B_L : STD_LOGIC_VECTOR(3 downto 0);
signal DI_B_L : STD_LOGIC_VECTOR(31 downto 0);
signal ADDR_B_L : STD_LOGIC_VECTOR(31 downto 2);
begin
nWE_B_L <= nWE_B when falling_edge (nCS_B);
MEM_MASK_B_L <= MEM_MASK_B when falling_edge (nCS_B);
DI_B_L <= DI_B when falling_edge (nCS_B);
ADDR_B_L <= ADDR_B when falling_edge (nCS_B);
WAIT_B <= (not nCS_B) or (not nWAIT_B);
CS_B_LATCH: entity work.D_Flip_Flop
PORT MAP(
rst => not nCS_B,
pre => not nRESET,
ce => nWAIT_B,
d => '1',
q => nCS_B_L
);
process (CLK)
begin
if rising_edge(CLK) then
if nRESET = '0' then
STATE <= IDLE;
nWAIT_A <= '1';
nWAIT_B <= '1';
A_LOCK <= '0';
B_LOCK <= '0';
SRAM_WE <= '1';
SRAM_OE <= '1';
SRAM_CE0 <= '1';
SRAM_CE1 <= '1';
SRAM_LB <= '1';
SRAM_UB <= '1';
SRAM_D <= (OTHERS=>'Z');
else
if nCS_A = '1' then
A_LOCK <= '0';
end if;
if nCS_B = '1' then
B_LOCK <= '0';
end if;
if A_LOCK = '0' and nCS_A = '0' and STATE /= IDLE then
nWAIT_A <= '0';
end if;
if B_LOCK = '0' and nCS_B_L = '0' and (STATE /= IDLE or (STATE = IDLE and nCS_A = '0') ) then
nWAIT_B <= '0';
end if;
case STATE is
when IDLE =>
if A_LOCK = '0' and nCS_A = '0' then
nWAIT_A <= '0';
A_LOCK <= '1';
SRAM_CE0 <= '1';
SRAM_CE1 <= '0';
SRAM_LB <= '0';
SRAM_UB <= '1';
SRAM_A <= ADDR_A;
if nWE_A = '1' then
-- Read
SRAM_OE <= '0';
STATE <= ST_READ1_A;
else
-- Write
SRAM_WE <= '0';
SRAM_D(7 DOWNTO 0) <= DI_A;
STATE <= ST_WRITE1_A;
end if;
else
if nCS_B_L = '0' then
nWAIT_B <= '0';
B_LOCK <= '1';
SRAM_CE0 <= '0';
SRAM_CE1 <= '1';
SRAM_A <= ADDR_B_L(18 downto 2) & '0';
if nWE_B_L = '1' then
-- Read
SRAM_UB <= '0';
SRAM_LB <= '0';
SRAM_OE <= '0';
STATE <= ST_READ1_B;
else
-- Write
if (ENDIAN_MODE = "11" and (MEM_MASK_B_L(0) = '1' or MEM_MASK_B_L(1) = '1') )
or (ENDIAN_MODE = "00" and (MEM_MASK_B_L(2) = '1' or MEM_MASK_B_L(3) = '1') )then
if ENDIAN_MODE = "11" then
SRAM_D <= DI_B_L(15 downto 0);
SRAM_UB <= not MEM_MASK_B_L(1);
SRAM_LB <= not MEM_MASK_B_L(0);
else
SRAM_D <= DI_B_L(23 downto 16) & DI_B_L(31 downto 24);
SRAM_UB <= not MEM_MASK_B_L(2);
SRAM_LB <= not MEM_MASK_B_L(3);
end if;
SRAM_WE <= '0';
if (ENDIAN_MODE = "11" and (MEM_MASK_B_L(2) = '1' or MEM_MASK_B_L(3) = '1') )
or (ENDIAN_MODE = "00" and (MEM_MASK_B_L(0) = '1' or MEM_MASK_B_L(1) = '1') ) then
STATE <= ST_WRITE1_B;
else
STATE <= ST_WRITE3_B;
end if;
else
SRAM_A <= ADDR_B_L(18 downto 2) & '1';
if ENDIAN_MODE = "11" then
SRAM_D <= DI_B_L(31 downto 16);
SRAM_UB <= not MEM_MASK_B_L(3);
SRAM_LB <= not MEM_MASK_B_L(2);
else
SRAM_D <= DI_B_L(7 downto 0) & DI_B_L(15 downto 8);
SRAM_UB <= not MEM_MASK_B_L(0);
SRAM_LB <= not MEM_MASK_B_L(1);
end if;
SRAM_WE <= '0';
SRAM_CE0 <= '0';
SRAM_CE1 <= '1';
STATE <= ST_WRITE3_B;
end if;
end if;
end if;
end if;
when ST_READ1_A =>
DO_A <= SRAM_D(7 DOWNTO 0);
nWAIT_A <= '1';
SRAM_D <= (OTHERS=>'Z');
SRAM_WE <= '1';
SRAM_OE <= '1';
SRAM_CE0 <= '1';
SRAM_CE1 <= '1';
SRAM_LB <= '1';
SRAM_UB <= '1';
STATE <= IDLE;
when ST_WRITE1_A =>
nWAIT_A <= '1';
SRAM_D <= (OTHERS=>'Z');
SRAM_WE <= '1';
SRAM_OE <= '1';
SRAM_CE0 <= '1';
SRAM_CE1 <= '1';
SRAM_LB <= '1';
SRAM_UB <= '1';
STATE <= IDLE;
when ST_READ1_B =>
if ENDIAN_MODE = "11" then
DO_B(15 downto 0) <= SRAM_D;
else
DO_B(31 downto 16) <= SRAM_D(7 downto 0) & SRAM_D(15 downto 8);
end if;
SRAM_A <= ADDR_B(18 downto 2) & '1';
STATE <= ST_READ2_B;
when ST_READ2_B =>
if ENDIAN_MODE = "11" then
DO_B(31 downto 16) <= SRAM_D;
else
DO_B(15 downto 0) <= SRAM_D(7 downto 0) & SRAM_D(15 downto 8);
end if;
nWAIT_B <= '1';
SRAM_WE <= '1';
SRAM_OE <= '1';
SRAM_CE0 <= '1';
SRAM_CE1 <= '1';
SRAM_LB <= '1';
SRAM_UB <= '1';
SRAM_D <= (OTHERS=>'Z');
STATE <= IDLE;
when ST_WRITE1_B =>
SRAM_UB <= '1';
SRAM_LB <= '1';
SRAM_WE <= '1';
SRAM_CE0 <= '1';
SRAM_CE1 <= '1';
STATE <= ST_WRITE2_B;
when ST_WRITE2_B =>
SRAM_A <= ADDR_B_L(18 downto 2) & '1';
if ENDIAN_MODE = "11" then
SRAM_D <= DI_B_L(31 downto 16);
SRAM_UB <= not MEM_MASK_B_L(3);
SRAM_LB <= not MEM_MASK_B_L(2);
else
SRAM_D <= DI_B_L(7 downto 0) & DI_B_L(15 downto 8);
SRAM_UB <= not MEM_MASK_B_L(0);
SRAM_LB <= not MEM_MASK_B_L(1);
end if;
SRAM_WE <= '0';
SRAM_CE0 <= '0';
SRAM_CE1 <= '1';
STATE <= ST_WRITE3_B;
when ST_WRITE3_B =>
nWAIT_B <= '1';
SRAM_D <= (OTHERS=>'Z');
SRAM_WE <= '1';
SRAM_OE <= '1';
SRAM_CE0 <= '1';
SRAM_CE1 <= '1';
SRAM_LB <= '1';
SRAM_UB <= '1';
STATE <= IDLE;
when OTHERS =>
STATE <= IDLE;
end case;
end if;
end if;
end process;
end dp_sram_arch; |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY RF_tb IS
END RF_tb;
ARCHITECTURE behavior OF RF_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RF
PORT(
rs1 : IN std_logic_vector(5 downto 0);
rs2 : IN std_logic_vector(5 downto 0);
rd : IN std_logic_vector(5 downto 0);
DWR : IN std_logic_vector(31 downto 0);
rst : IN std_logic;
Crs1 : OUT std_logic_vector(31 downto 0);
Crs2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal rs1 : std_logic_vector(5 downto 0) := (others => '0');
signal rs2 : std_logic_vector(5 downto 0) := (others => '0');
signal rd : std_logic_vector(5 downto 0) := (others => '0');
signal DWR : std_logic_vector(31 downto 0) := (others => '0');
signal rst : std_logic := '0';
--Outputs
signal Crs1 : std_logic_vector(31 downto 0);
signal Crs2 : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RF PORT MAP (
rs1 => rs1,
rs2 => rs2,
rd => rd,
DWR => DWR,
rst => rst,
Crs1 => Crs1,
Crs2 => Crs2
);
-- Stimulus process
stim_proc: process
begin
rst<='1';
wait for 20 ns;
rst<='0';
rs1<=(others=>'0');
rs2<="001000";
rd<="000001";
DWR<="00000000000000000000000000001000";
wait for 40 ns;
rs1<=(others=>'0');
rs2<="011001";
rd<="000010";
DWR<="11111111111111111111111111111001";
wait for 40 ns;
rs1<="000001";
rs2<="000010";
rd<="001000";
DWR<="00000000000001000101111011111111";
wait for 40 ns;
rd<="001001";
DWR<="00000000000000000000000000001000";
wait for 40 ns;
rd<="001010";
DWR<="00000000000000000000000000001001";
wait for 40 ns;
rd<="001011";
DWR<="00000000000000000000000000001010";
wait for 40 ns;
rd<="001100";
DWR<="00000000000000000000000000001011";
wait for 40 ns;
rst<='1';
rs1<="000001";
rs2<="000010";
rd<="001101";
DWR<="00000000000000000000000000001100";
wait;
end process;
END;
|
entity tb_dff13 is
end tb_dff13;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff13 is
signal clk : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.dff13
port map (
q => dout,
d => din,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
din <= '0';
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '1' severity failure;
pulse;
assert dout = '1' severity failure;
din <= '0';
pulse;
assert dout = '0' severity failure;
wait;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
entity Signature is
generic (n:integer := 4);
port(
CLK: in std_logic;
RST: in std_logic;
Pin: in std_logic;
Pout: out std_logic_vector(0 to 2**n-1)
);
end Signature;
architecture behavior of Signature is
signal sreg: std_logic_vector(0 to 2**n-1);
signal sdat: std_logic_vector(0 to 2**n-1);
signal buf: std_logic;
Begin
Main: process (CLK, RST, sdat)
begin
if RST = '1' then
sreg <= (others => '0');
elsif rising_edge(CLK) then
sreg <= sdat;
end if;
end process;
Data: process (Pin, sreg)
begin
buf <= sreg(0) xor sreg(2**n-1);
sdat <= (sreg(2**n-1) xor PIn) & sreg(0 to 2**n-2);
sdat(2) <= buf;
end process;
Pout <= sreg;
End behavior; |
-------------------------------------------------------------------------------
--! @project Unrolled (6) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity OutputGenerator is
port(
In0 : in std_logic_vector(63 downto 0);
DataIn : in std_logic_vector(63 downto 0);
Size : in std_logic_vector(2 downto 0);
Activate : in std_logic;
Out0 : out std_logic_vector(63 downto 0);
DataOut : out std_logic_vector(63 downto 0));
end entity OutputGenerator;
architecture structural of OutputGenerator is
constant ALLZERO : std_logic_vector(63 downto 0) := (others => '0');
signal Temp0,Temp1,Temp2 : std_logic_vector(63 downto 0);
begin
Gen: process(In0,DataIn,Size,Activate,Temp0,Temp1,Temp2) is
-- Truncator0&1
procedure doTruncate0 ( -- Truncate block 0 and 1 together
signal Input : in std_logic_vector(63 downto 0);
signal Size : in std_logic_vector(2 downto 0);
signal Activate : in std_logic;
signal Output : out std_logic_vector(63 downto 0)) is
variable ActSize : std_logic_vector(3 downto 0);
begin
ActSize(3) := Activate;
ActSize(2 downto 0) := Size;
-- if inactive it lets everything trough, if active it lets the first blocksize bits trough
logic: case ActSize is
when "1001" =>
Output(63 downto 56) <= Input(63 downto 56);
Output(55) <= '1';
Output(54 downto 0) <= ALLZERO(54 downto 0);
when "1010" =>
Output(63 downto 48) <= Input(63 downto 48);
Output(47) <= '1';
Output(46 downto 0) <= ALLZERO(46 downto 0);
when "1011" =>
Output(63 downto 40) <= Input(63 downto 40);
Output(39) <= '1';
Output(38 downto 0) <= ALLZERO(38 downto 0);
when "1100" =>
Output(63 downto 32) <= Input(63 downto 32);
Output(31) <= '1';
Output(30 downto 0) <= ALLZERO(30 downto 0);
when "1101" =>
Output(63 downto 24) <= Input(63 downto 24);
Output(23) <= '1';
Output(22 downto 0) <= ALLZERO(22 downto 0);
when "1110" =>
Output(63 downto 16) <= Input(63 downto 16);
Output(15) <= '1';
Output(14 downto 0) <= ALLZERO(14 downto 0);
when "1111" =>
Output(63 downto 8) <= Input(63 downto 8);
Output(7) <= '1';
Output(6 downto 0) <= ALLZERO(6 downto 0);
when others => -- deactivate or blocksize max or invalid input (cas 0xxxx or 10000)
Output <= Input;
end case logic;
end procedure doTruncate0;
-- Truncator2
procedure doTruncate2 ( -- Truncate block 0 and 1 together
signal Input : in std_logic_vector(63 downto 0);
signal Size : in std_logic_vector(2 downto 0);
signal Activate : in std_logic;
signal Output : out std_logic_vector(63 downto 0)) is
variable ActSize : std_logic_vector(3 downto 0);
begin
ActSize(3) := Activate;
ActSize(2 downto 0) := Size;
-- if inactive it lets everything trough, if active it blocks the first blocksize bits
logic: case ActSize is
when "1000" =>
Output <= ALLZERO;
when "1001" =>
Output(63 downto 56) <= ALLZERO(63 downto 56);
Output(55 downto 0) <= Input(55 downto 0);
when "1010" =>
Output(63 downto 48) <= ALLZERO(63 downto 48);
Output(47 downto 0) <= Input(47 downto 0);
when "1011" =>
Output(63 downto 40) <= ALLZERO(63 downto 40);
Output(39 downto 0) <= Input(39 downto 0);
when "1100" =>
Output(63 downto 32) <= ALLZERO(63 downto 32);
Output(31 downto 0) <= Input(31 downto 0);
when "1101" =>
Output(63 downto 24) <= ALLZERO(63 downto 24);
Output(23 downto 0) <= Input(23 downto 0);
when "1110" =>
Output(63 downto 16) <= ALLZERO(63 downto 16);
Output(15 downto 0) <= Input(15 downto 0);
when "1111" =>
Output(63 downto 8) <= ALLZERO(63 downto 8);
Output(7 downto 0) <= Input(7 downto 0);
when others => -- deactivate or blocksize max or invalid input (cas 0xxxx or 10000)
Output <= Input;
end case logic;
end procedure doTruncate2;
begin
-- DataOut
DataOut <= In0 xor DataIn;
-- Stateupdate
doTruncate0(DataIn,Size,Activate,Temp0);
Temp1 <= In0;
doTruncate2(Temp1,Size,Activate,Temp2);
Out0 <= Temp0 xor Temp2;
end process Gen;
end architecture structural;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Rhody_CPU_pipelinev112 is
port ( clk : in std_logic;
rst : in std_logic;
MEM_ADR : out std_logic_vector(31 downto 0);
MEM_IN : in std_logic_vector(31 downto 0);
MEM_OUT : out std_logic_vector(31 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
key : in std_logic;
LEDR : out std_logic_vector(3 downto 0)
);
end;
architecture Structural of Rhody_CPU_pipelinev112 is
-- state machine: CPU_state
type State_type is (S1, S2);
signal update, stage1, stage2, stage3, stage4: State_type;
-- Register File: 8x32
type reg_file_type is array (0 to 7) of std_logic_vector(31 downto 0);
signal register_file : reg_file_type;
-- Internal registers
signal MDR_in, MDR_out, MAR, PSW: std_logic_vector(31 downto 0);
signal PC, SP: unsigned(31 downto 0); --unsigned for arithemtic operations
-- Internal control signals
signal operand0, operand1, ALU_out : std_logic_vector(31 downto 0);
signal carry, overflow, zero : std_logic;
-- Pipeline Istruction registers
signal stall: Boolean;
signal IR2, IR3, IR4: std_logic_vector(31 downto 0);
--Rhody Instruction Format
alias Opcode2: std_logic_vector(5 downto 0) is IR2(31 downto 26);
alias Opcode3: std_logic_vector(5 downto 0) is IR3(31 downto 26);
alias Opcode4: std_logic_vector(5 downto 0) is IR4(31 downto 26);
alias RX2 : std_logic_vector(2 downto 0) is IR2(25 downto 23);
alias RX3 : std_logic_vector(2 downto 0) is IR3(25 downto 23);
alias RX4 : std_logic_vector(2 downto 0) is IR4(25 downto 23);
alias RY2 : std_logic_vector(2 downto 0) is IR2(22 downto 20);
alias RY3 : std_logic_vector(2 downto 0) is IR3(22 downto 20);
alias RZ2 : std_logic_vector(2 downto 0) is IR2(19 downto 17);
alias RA2 : std_logic_vector(2 downto 0) is IR2(16 downto 14);
alias RB2 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RB3 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RC2 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RC3 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RD2 : std_logic_vector(2 downto 0) is IR2(7 downto 5);
alias RE2 : std_logic_vector(2 downto 0) is IR2(4 downto 2);
alias I2 : std_logic_vector(15 downto 0) is IR2(15 downto 0);
alias M2 : std_logic_vector(19 downto 0) is IR2(19 downto 0);
alias M3 : std_logic_vector(19 downto 0) is IR3(19 downto 0);
-- Temporary control signals
signal tmpx, tmpy, tmpz, tmpa: std_logic_vector(31 downto 0);
--Condition Codes
alias Z: std_logic is PSW(0);
alias C: std_logic is PSW(1);
alias S: std_logic is PSW(2);
alias V: std_logic is PSW(3);
--Instruction Opcodes
constant NOP : std_logic_vector(5 downto 0) := "000000";
--constant ADD64: std_logic_vector(5 downto 0) := "000001";
--constant T2 : std_logic_vector(5 downto 0) := "000010";
constant LDM : std_logic_vector(5 downto 0) := "000100";
constant LDR : std_logic_vector(5 downto 0) := "000101";
constant LDIX : std_logic_vector(5 downto 0) := "000110";
constant STIX : std_logic_vector(5 downto 0) := "000111";
constant LDH : std_logic_vector(5 downto 0) := "001000";
constant LDL : std_logic_vector(5 downto 0) := "001001";
constant LDI : std_logic_vector(5 downto 0) := "001010";
constant MOV : std_logic_vector(5 downto 0) := "001011";
constant STM : std_logic_vector(5 downto 0) := "001100";
constant STR : std_logic_vector(5 downto 0) := "001101";
constant ADD : std_logic_vector(5 downto 0) := "010000";
constant ADI : std_logic_vector(5 downto 0) := "010001";
constant SUB : std_logic_vector(5 downto 0) := "010010";
constant MUL : std_logic_vector(5 downto 0) := "010011";
constant IAND : std_logic_vector(5 downto 0) := "010100"; --avoid keyword
constant IOR : std_logic_vector(5 downto 0) := "010101"; --avoid keyword
constant IXOR : std_logic_vector(5 downto 0) := "010110"; --avoid keyword
constant IROR : std_logic_vector(5 downto 0) := "010111"; --avoid keyword
constant JNZ : std_logic_vector(5 downto 0) := "100000";
constant JNS : std_logic_vector(5 downto 0) := "100001";
constant JNV : std_logic_vector(5 downto 0) := "100010";
constant JNC : std_logic_vector(5 downto 0) := "100011";
constant JZ : std_logic_vector(5 downto 0) := "100100";
constant JS : std_logic_vector(5 downto 0) := "100101";
constant JV : std_logic_vector(5 downto 0) := "100110";
constant JC : std_logic_vector(5 downto 0) := "100111";
constant JMP : std_logic_vector(5 downto 0) := "101000";
constant CMP : std_logic_vector(5 downto 0) := "101010";
--constant T11 : std_logic_vector(5 downto 0) := "101110";
--constant T12 : std_logic_vector(5 downto 0) := "101111";
constant CALL : std_logic_vector(5 downto 0) := "110000";
constant CMPI : std_logic_vector(5 downto 0) := "110010";
constant RET : std_logic_vector(5 downto 0) := "110100";
constant RETI : std_logic_vector(5 downto 0) := "110101";
constant PUSH : std_logic_vector(5 downto 0) := "111000";
constant POP : std_logic_vector(5 downto 0) := "111001";
constant SYS : std_logic_vector(5 downto 0) := "111100";
--constant SIG0 : std_logic_vector(5 downto 0) := "111110";
--constant SIG1 : std_logic_vector(5 downto 0) := "111111";
constant MLOAD0 : std_logic_vector(5 downto 0) := "011001";
constant MLOAD1 : std_logic_vector(5 downto 0) := "011010";
constant MLOAD2 : std_logic_vector(5 downto 0) := "011011";
constant MLOAD3 : std_logic_vector(5 downto 0) := "011100";
constant WLOAD : std_logic_vector(5 downto 0) := "011101";
constant ROUND1 : std_logic_vector(5 downto 0) := "101100";
constant FIN : std_logic_vector(5 downto 0) := "101101";
constant MSTM0 : std_logic_vector(5 downto 0) := "101001";
constant MSTM1 : std_logic_vector(5 downto 0) := "101011";
constant LDIXD : std_logic_vector(5 downto 0) := "111010";
constant WPAD : std_logic_vector(5 downto 0) := "111011";
constant WORD_BITS : integer := 64;
subtype WORD_TYPE is std_logic_vector(63 downto 0);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
constant WORD_NULL : WORD_TYPE := (others => '0');
--shared variable w_80 : WORD_VECTOR(0 to 79);
----------------------------------------------------------------
constant K_TABLE : WORD_VECTOR(0 to 79) := (
0 => To_StdLogicVector(bit_vector'(X"428a2f98d728ae22")),
1 => To_StdLogicVector(bit_vector'(X"7137449123ef65cd")),
2 => To_StdLogicVector(bit_vector'(X"b5c0fbcfec4d3b2f")),
3 => To_StdLogicVector(bit_vector'(X"e9b5dba58189dbbc")),
4 => To_StdLogicVector(bit_vector'(X"3956c25bf348b538")),
5 => To_StdLogicVector(bit_vector'(X"59f111f1b605d019")),
6 => To_StdLogicVector(bit_vector'(X"923f82a4af194f9b")),
7 => To_StdLogicVector(bit_vector'(X"ab1c5ed5da6d8118")),
8 => To_StdLogicVector(bit_vector'(X"d807aa98a3030242")),
9 => To_StdLogicVector(bit_vector'(X"12835b0145706fbe")),
10 => To_StdLogicVector(bit_vector'(X"243185be4ee4b28c")),
11 => To_StdLogicVector(bit_vector'(X"550c7dc3d5ffb4e2")),
12 => To_StdLogicVector(bit_vector'(X"72be5d74f27b896f")),
13 => To_StdLogicVector(bit_vector'(X"80deb1fe3b1696b1")),
14 => To_StdLogicVector(bit_vector'(X"9bdc06a725c71235")),
15 => To_StdLogicVector(bit_vector'(X"c19bf174cf692694")),
16 => To_StdLogicVector(bit_vector'(X"e49b69c19ef14ad2")),
17 => To_StdLogicVector(bit_vector'(X"efbe4786384f25e3")),
18 => To_StdLogicVector(bit_vector'(X"0fc19dc68b8cd5b5")),
19 => To_StdLogicVector(bit_vector'(X"240ca1cc77ac9c65")),
20 => To_StdLogicVector(bit_vector'(X"2de92c6f592b0275")),
21 => To_StdLogicVector(bit_vector'(X"4a7484aa6ea6e483")),
22 => To_StdLogicVector(bit_vector'(X"5cb0a9dcbd41fbd4")),
23 => To_StdLogicVector(bit_vector'(X"76f988da831153b5")),
24 => To_StdLogicVector(bit_vector'(X"983e5152ee66dfab")),
25 => To_StdLogicVector(bit_vector'(X"a831c66d2db43210")),
26 => To_StdLogicVector(bit_vector'(X"b00327c898fb213f")),
27 => To_StdLogicVector(bit_vector'(X"bf597fc7beef0ee4")),
28 => To_StdLogicVector(bit_vector'(X"c6e00bf33da88fc2")),
29 => To_StdLogicVector(bit_vector'(X"d5a79147930aa725")),
30 => To_StdLogicVector(bit_vector'(X"06ca6351e003826f")),
31 => To_StdLogicVector(bit_vector'(X"142929670a0e6e70")),
32 => To_StdLogicVector(bit_vector'(X"27b70a8546d22ffc")),
33 => To_StdLogicVector(bit_vector'(X"2e1b21385c26c926")),
34 => To_StdLogicVector(bit_vector'(X"4d2c6dfc5ac42aed")),
35 => To_StdLogicVector(bit_vector'(X"53380d139d95b3df")),
36 => To_StdLogicVector(bit_vector'(X"650a73548baf63de")),
37 => To_StdLogicVector(bit_vector'(X"766a0abb3c77b2a8")),
38 => To_StdLogicVector(bit_vector'(X"81c2c92e47edaee6")),
39 => To_StdLogicVector(bit_vector'(X"92722c851482353b")),
40 => To_StdLogicVector(bit_vector'(X"a2bfe8a14cf10364")),
41 => To_StdLogicVector(bit_vector'(X"a81a664bbc423001")),
42 => To_StdLogicVector(bit_vector'(X"c24b8b70d0f89791")),
43 => To_StdLogicVector(bit_vector'(X"c76c51a30654be30")),
44 => To_StdLogicVector(bit_vector'(X"d192e819d6ef5218")),
45 => To_StdLogicVector(bit_vector'(X"d69906245565a910")),
46 => To_StdLogicVector(bit_vector'(X"f40e35855771202a")),
47 => To_StdLogicVector(bit_vector'(X"106aa07032bbd1b8")),
48 => To_StdLogicVector(bit_vector'(X"19a4c116b8d2d0c8")),
49 => To_StdLogicVector(bit_vector'(X"1e376c085141ab53")),
50 => To_StdLogicVector(bit_vector'(X"2748774cdf8eeb99")),
51 => To_StdLogicVector(bit_vector'(X"34b0bcb5e19b48a8")),
52 => To_StdLogicVector(bit_vector'(X"391c0cb3c5c95a63")),
53 => To_StdLogicVector(bit_vector'(X"4ed8aa4ae3418acb")),
54 => To_StdLogicVector(bit_vector'(X"5b9cca4f7763e373")),
55 => To_StdLogicVector(bit_vector'(X"682e6ff3d6b2b8a3")),
56 => To_StdLogicVector(bit_vector'(X"748f82ee5defb2fc")),
57 => To_StdLogicVector(bit_vector'(X"78a5636f43172f60")),
58 => To_StdLogicVector(bit_vector'(X"84c87814a1f0ab72")),
59 => To_StdLogicVector(bit_vector'(X"8cc702081a6439ec")),
60 => To_StdLogicVector(bit_vector'(X"90befffa23631e28")),
61 => To_StdLogicVector(bit_vector'(X"a4506cebde82bde9")),
62 => To_StdLogicVector(bit_vector'(X"bef9a3f7b2c67915")),
63 => To_StdLogicVector(bit_vector'(X"c67178f2e372532b")),
64 => To_StdLogicVector(bit_vector'(X"ca273eceea26619c")),
65 => To_StdLogicVector(bit_vector'(X"d186b8c721c0c207")),
66 => To_StdLogicVector(bit_vector'(X"eada7dd6cde0eb1e")),
67 => To_StdLogicVector(bit_vector'(X"f57d4f7fee6ed178")),
68 => To_StdLogicVector(bit_vector'(X"06f067aa72176fba")),
69 => To_StdLogicVector(bit_vector'(X"0a637dc5a2c898a6")),
70 => To_StdLogicVector(bit_vector'(X"113f9804bef90dae")),
71 => To_StdLogicVector(bit_vector'(X"1b710b35131c471b")),
72 => To_StdLogicVector(bit_vector'(X"28db77f523047d84")),
73 => To_StdLogicVector(bit_vector'(X"32caab7b40c72493")),
74 => To_StdLogicVector(bit_vector'(X"3c9ebe0a15c9bebc")),
75 => To_StdLogicVector(bit_vector'(X"431d67c49c100d4c")),
76 => To_StdLogicVector(bit_vector'(X"4cc5d4becb3e42b6")),
77 => To_StdLogicVector(bit_vector'(X"597f299cfc657e2a")),
78 => To_StdLogicVector(bit_vector'(X"5fcb6fab3ad6faec")),
79 => To_StdLogicVector(bit_vector'(X"6c44198c4a475817"))
);
constant H0_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"6a09e667f3bcc908"));
constant H1_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"bb67ae8584caa73b"));
constant H2_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"3c6ef372fe94f82b"));
constant H3_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"a54ff53a5f1d36f1"));
constant H4_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"510e527fade682d1"));
constant H5_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"9b05688c2b3e6c1f"));
constant H6_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"1f83d9abfb41bd6b"));
constant H7_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"5be0cd19137e2179"));
-------------------------------------------------------------------------
signal dm0 : std_logic_vector(63 downto 0);
signal dm1 : std_logic_vector(63 downto 0);
signal dm2 : std_logic_vector(63 downto 0);
signal dm3 : std_logic_vector(63 downto 0);
signal dm4 : std_logic_vector(63 downto 0);
signal dm5 : std_logic_vector(63 downto 0);
signal dm6 : std_logic_vector(63 downto 0);
signal dm7 : std_logic_vector(63 downto 0);
signal dm8 : std_logic_vector(63 downto 0);
signal dm9 : std_logic_vector(63 downto 0);
signal dm10 : std_logic_vector(63 downto 0);
signal dm11 : std_logic_vector(63 downto 0);
signal dm12 : std_logic_vector(63 downto 0);
signal dm13 : std_logic_vector(63 downto 0);
signal dm14 : std_logic_vector(63 downto 0);
signal dm15 : std_logic_vector(63 downto 0);
-- a,b,c,d,e,f,g,h
signal wva : WORD_TYPE;
signal wvb : WORD_TYPE;
signal wvc : WORD_TYPE;
signal wvd : WORD_TYPE;
signal wve : WORD_TYPE;
signal wvf : WORD_TYPE;
signal wvg : WORD_TYPE;
signal wvh : WORD_TYPE;
signal t1_val : WORD_TYPE;
signal t2_val : WORD_TYPE;
-- H0,H1,H2,H3,H4,H5,H6,H7
signal h0 : WORD_TYPE;
signal h1 : WORD_TYPE;
signal h2 : WORD_TYPE;
signal h3 : WORD_TYPE;
signal h4 : WORD_TYPE;
signal h5 : WORD_TYPE;
signal h6 : WORD_TYPE;
signal h7 : WORD_TYPE;
signal rcount : integer;
signal tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7: std_logic_vector(63 downto 0);
signal mvect : WORD_VECTOR(0 to 15);
signal wout: std_logic_vector(63 downto 0);
begin
--Display condition code on LEDR for debugging purpose
LEDR(3) <= Z when key='0' else '0';
LEDR(2) <= C when key='0' else '0';
LEDR(1) <= S when key='0' else '0';
LEDR(0) <= V when key='0' else '0';
--CPU bus interface
MEM_OUT <= MDR_out; --Outgoing data bus
MEM_ADR <= MAR; --Address bus
--One clock cycle delay in obtaining CPU_state, e.g. S1->S2
mem_rd <= '1' when ((Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX or Opcode2 = LDIXD) and stage2=S2) else
'1' when (Opcode3 = LDIXD and stage3=S2) else
'1' when (stage1=S2 and not stall) else
'1' when ((Opcode2=POP or Opcode2=RET) and stage2=S2) else
'1' when (Opcode2=RETI and stage2=S2) else
'1' when (Opcode3=RETI and stage3=S2) else
'0'; --Memory read control signal
mem_wr <= '1' when ((Opcode3=STM or Opcode3=STR or Opcode3=STIX) and stage3=S1) else
'1' when ((Opcode3=PUSH or Opcode3=CALL) and stage3=S2) else
'1' when (Opcode3=SYS and stage3=S2) else
'1' when (Opcode4=SYS and stage4=S2) else
'0'; --Memory write control signal
stall <= true when(Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX or Opcode2=STM or Opcode2=STR or Opcode2=STIX or Opcode2=WPAD or Opcode2 = LDIXD) else
true when(Opcode2=CALL or Opcode2=PUSH or Opcode2=POP or Opcode2=RET
or Opcode2=SYS or Opcode2=RETI) else
true when(Opcode3=CALL or Opcode3=RET or Opcode3=PUSH
or Opcode3=SYS or Opcode3=RETI or Opcode3 = LDIXD) else
true when(Opcode4=SYS or Opcode4=RETI) else
false;
--The state machine that is CPU
CPU_State_Machine: process (clk, rst)
begin
if rst='1' then
update <= S1;
stage1 <= S1;
stage2 <= S1;
stage3 <= S1;
stage4 <= S1;
rcount <= 0;
PC <= x"00000000"; --initialize PC
SP <= x"000FF7FF"; --initialize SP
IR2 <= x"00000000";
IR3 <= x"00000000";
IR4 <= x"00000000";
elsif clk'event and clk = '1' then
case update is
when S1 =>
update <= S2;
when S2 =>
if (stall or
(Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z='0') or
(Opcode2=JNS and S='1') or (Opcode2=JS and S='0') or
(Opcode2=JNV and V='1') or (Opcode2=JV and V='0') or
(Opcode2=JNC and C='1') or (Opcode2=JC and C='0') ) then
IR2 <= x"00000000"; --insert NOP
else
IR2 <= MEM_in;
end if;
IR3 <= IR2;
IR4 <= IR3;
update <= S1;
when others =>
null;
end case;
case stage1 is
when S1 =>
if (not stall) then
if(Opcode2=JMP or Opcode2=JNZ or Opcode2=JZ or Opcode2=JNS or
Opcode2=JS or Opcode2=JNV or Opcode2=JV or
Opcode2=JNC or Opcode2=JC) then
MAR <= x"000" & M2;
else
MAR <= std_logic_vector(PC);
end if;
end if;
stage1 <= S2;
when S2 =>
if (not stall) then
if (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= (x"000" & unsigned(M2))+1;
elsif ((Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z = '0') or
(Opcode2=JNS and S = '1')or (Opcode2=JS and S = '0') or
(Opcode2=JNV and V = '1') or (Opcode2=JV and V = '0') or
(Opcode2=JNC and C = '1') or (Opcode2=JC and C = '0')) then
null;
else
PC <= PC + 1;
end if;
end if;
stage1 <= S1;
when others =>
null;
end case;
case stage2 is
when S1 =>
if (Opcode2=LDI) then
register_file(to_integer(unsigned(RX2)))<=(31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDH) then
register_file(to_integer(unsigned(RX2)))
<= I2 & register_file(to_integer(unsigned(RX2)))(15 downto 0);
--(31 downto 16)<= I2;
elsif (Opcode2=LDL) then
register_file(to_integer(unsigned(RX2)))
<= register_file(to_integer(unsigned(RX2)))(31 downto 16) & I2;
--(15 downto 0)<= I2;
elsif (Opcode2=MOV) then
register_file(to_integer(unsigned(RX2)))<=register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=ADD or Opcode2=SUB or Opcode2=MUL or Opcode2=CMP or
Opcode2=IAND or Opcode2=IOR or Opcode2=IXOR) then
operand1 <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=IROR) then
null;
elsif (Opcode2=ADI or Opcode2=CMPI) then
operand1 <= (31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDM) then
MAR <= x"000" & M2;
elsif (Opcode2=LDR) then
MAR <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=LDIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RY2))))
+ unsigned(M2));
elsif (Opcode2=STM) then
MAR <= x"000" & M2; MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2=STR) then
MAR <= register_file(to_integer(unsigned(RX2)));
MDR_out <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=STIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RX2))))
+ unsigned(M2));
MDR_out <=
register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= x"000" & unsigned(M2);
elsif (Opcode2=CALL or Opcode2=PUSH or Opcode2=SYS) then
SP <= SP + 1;
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MAR <= std_logic_vector(SP);
elsif (Opcode2 = WLOAD) then
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
elsif (Opcode2 = WPAD) then
if (rcount < 16) then
wout <= std_logic_vector(mvect(rcount));
else
wout <= std_Logic_vector(
unsigned(unsigned(rotate_right(unsigned(mvect(14)),19)) xor unsigned(rotate_right(unsigned(mvect(14)),61)) xor unsigned(shift_right(unsigned(mvect(14)),6))) +
unsigned(mvect(9)) +
unsigned(unsigned(rotate_right(unsigned(mvect(1)),1)) xor unsigned(rotate_right(unsigned(mvect(1)),8)) xor unsigned(shift_right(unsigned(mvect(1)),7))) +
unsigned(mvect(0)));
end if;
elsif(Opcode2 = LDIXD) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RY2))))
+ unsigned(M2));
elsif (Opcode2 = MLOAD0) then
mvect(0) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(1) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(2) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(3) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD1) then
mvect(4) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(5) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(6) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(7) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD2) then
mvect(8) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(9) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(10) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(11) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD3) then
mvect(12) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(13) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(14) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(15) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2 = MSTM0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm0))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm1))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm1))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm2))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm2))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm3))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm3))(31 downto 0);
elsif (Opcode2 = MSTM1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm4))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm4))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm5))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm5))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm6))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm6))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm7))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm7))(31 downto 0);
elsif (Opcode2 = FIN) then
dm0 <= std_logic_vector(unsigned(wva) + unsigned(h0));
dm1 <= std_logic_vector(unsigned(wvb) + unsigned(h1));
dm2 <= std_logic_vector(unsigned(wvc) + unsigned(h2));
dm3 <= std_logic_vector(unsigned(wvd) + unsigned(h3));
dm4 <= std_logic_vector(unsigned(wve) + unsigned(h4));
dm5 <= std_logic_vector(unsigned(wvf) + unsigned(h5));
dm6 <= std_logic_vector(unsigned(wvg) + unsigned(h6));
dm7 <= std_logic_vector(unsigned(wvh) + unsigned(h7));
end if;
stage2 <= S2;
when S2 =>
if (Opcode2=ADD or Opcode2=SUB or Opcode2=IROR or Opcode2=IAND or
Opcode2=MUL or Opcode2=IOR or Opcode2=IXOR or Opcode2=ADI) then
register_file(to_integer(unsigned(RX2))) <= ALU_out;
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC
elsif (Opcode2=CMP or Opcode2=CMPI) then
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC only
elsif (Opcode2=LDM or Opcode2=LDR or Opcode2=LDIX or Opcode2 = LDIXD) then
MDR_in <= MEM_in;
elsif (Opcode2=STM or Opcode2=STR or Opcode2=STIX) then
null;
elsif (Opcode2=CALL or Opcode2=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= std_logic_vector(PC);
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MDR_in <= MEM_IN; SP <= SP - 1;
elsif (Opcode2=PUSH) then
MAR <= std_logic_vector(SP);
MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2 = WPAD) then
if (rcount < 16) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(rcount)) + unsigned(wout))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
else
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(rcount)) + unsigned(wout))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
end if;
end if;
stage2 <= S1;
when others =>
null;
end case;
case stage3 is
when S1 =>
if (Opcode3=LDM or Opcode3=LDR or Opcode3=LDIX) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3 = LDIXD) then
mvect(to_integer(unsigned(register_file(to_integer(unsigned(RX3))))))(63 downto 32) <= MDR_in;
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RY3))))
+ unsigned(M3) + 1);
elsif (Opcode3=STM or Opcode3=STR or Opcode3=STIX) then
null;
elsif (Opcode3=CALL) then
PC <= x"000" & unsigned(M3);
elsif (Opcode3=POP) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=RET) then
PC <= unsigned(MDR_in);
elsif (Opcode3=RETI) then
PSW <= MDR_in; MAR <= std_logic_vector(SP);
elsif (Opcode3=PUSH) then
null;
elsif (Opcode3=SYS) then
SP <= SP + 1;
elsif(Opcode3 = WPAD) then
if (rcount < 16) then
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
rcount <= rcount + 1;
else
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
mvect(0) <= mvect(1);
mvect(1) <= mvect(2);
mvect(2) <= mvect(3);
mvect(3) <= mvect(4);
mvect(4) <= mvect(5);
mvect(5) <= mvect(6);
mvect(6) <= mvect(7);
mvect(7) <= (mvect(8));
mvect(8) <= (mvect(9));
mvect(9) <= (mvect(10));
mvect(10) <= (mvect(11));
mvect(11) <= (mvect(12));
mvect(12) <= (mvect(13));
mvect(13) <= (mvect(14));
mvect(14) <= (mvect(15));
mvect(15) <= wout;
rcount <= rcount + 1;
end if;
end if;
stage3 <= S2;
when S2 =>
if (Opcode3=RETI) then
MDR_in <= MEM_IN; sp <= sp - 1;
elsif (Opcode3=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= PSW;
elsif(Opcode3 = LDIXD) then
MDR_in <= MEM_in;
end if;
stage3 <= S1;
when others =>
null;
end case;
case stage4 is
when S1 =>
if (Opcode4=RETI) then
PC <= unsigned(MDR_in);
elsif (Opcode4=SYS) then
PC <= X"000FFC0"&unsigned(IR4(3 downto 0));
elsif (Opcode4 = LDIXD) then
mvect(to_integer(unsigned(register_file(to_integer(unsigned(RX4))))))(31 downto 0) <= MDR_in;
else stage4 <= S2;
end if;
stage4 <= S2;
when S2 =>
stage4 <= S1;
when others =>
null;
end case;
end if;
end process;
--------------------ALU----------------------------
Rhody_ALU: entity work.alu port map(
alu_op => IR2(28 downto 26),
operand0 => operand0,
operand1 => operand1,
n => IR2(4 downto 0),
alu_out => ALU_out,
carry => carry,
overflow => overflow);
zero <= '1' when alu_out = X"00000000" else '0';
operand0 <= register_file(to_integer(unsigned(RX2)));
-----------------------------------------------------
end Structural;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aua_types.all;
entity sc_test_slave is
port (
clk : in std_logic;
reset : in std_logic;
-- SimpCon slave interface to IO ctrl
address : in sc_addr_t;
wr_data : in sc_data_t;
rd : in std_logic;
wr : in std_logic;
rd_data : out sc_data_t;
rdy_cnt : out sc_rdy_cnt_t
);
end sc_test_slave;
architecture rtl of sc_test_slave is
signal cycle_cnt, cycle_cnt_nxt : unsigned(3 downto 0);
signal ready, ready_nxt : unsigned(3 downto 0);
signal reg, reg_nxt : sc_data_t;
signal sc_out, sc_out_nxt : sc_data_t;
type state_type is (st_done, st_wait);
signal state : state_type;
signal state_nxt : state_type;
begin
rd_data <= sc_out;
nxt: process(reset, state, cycle_cnt, reg, wr_data, address, wr, rd, ready, sc_out)
begin
cycle_cnt_nxt <= cycle_cnt;
reg_nxt <= reg;
sc_out_nxt <= sc_out;
rdy_cnt <= (others => '0');
ready_nxt <= ready;
state_nxt <= st_done;
if state=st_done then
if address(0)='0' then
if(wr='1') then
cycle_cnt_nxt <= unsigned(wr_data(3 downto 0));
end if;
if rd='1' then
sc_out_nxt <= (sc_out_nxt'length-1 downto cycle_cnt'length => '0')&std_logic_vector(cycle_cnt);
end if;
else
if(wr='1') then
reg_nxt <= wr_data;
state_nxt <= st_wait;
ready_nxt <= cycle_cnt;
end if;
if(rd='1') then
sc_out_nxt <= reg;
state_nxt <= st_wait;
ready_nxt <= cycle_cnt;
end if;
end if;
else
ready_nxt <= ready-1;
sc_out_nxt <= reg;
if ready > 3 then
rdy_cnt <= "11";
else
rdy_cnt <= ready(1 downto 0);
end if;
if ready /= 0 then
state_nxt <= st_wait;
end if;
end if;
end process;
sync: process(clk, reset)
begin
if (reset='1') then
sc_out <= (others => '0');
cycle_cnt <= (others => '0');
reg <= (others => '0');
ready <= (others => '0');
state <= st_done;
elsif rising_edge(clk) then
sc_out <= sc_out_nxt;
cycle_cnt <= cycle_cnt_nxt;
reg <= reg_nxt;
ready <= ready_nxt;
state <= state_nxt;
end if;
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_top is
generic (
numInj : integer := 56;
numIn : integer := 10;
numOut : integer := 10);
port (
aclk : in std_logic; -- interface clock
arst_n : in std_logic; -- interface reset
clk : in std_logic; -- simulation clock (slow)
clk_x32 : in std_logic; -- prng clock (fast)
-- Write channel
awvalid : in std_logic;
awaddr : in std_logic_vector(31 downto 0);
wvalid : in std_logic;
wdata : in std_logic_vector(31 downto 0);
-- Read channel
arvalid : in std_logic;
araddr : in std_logic_vector(31 downto 0);
rvalid : out std_logic;
rdata : out std_logic_vector(31 downto 0)
);
attribute syn_hier : string;
attribute syn_hier of faultify_top : entity is "hard";
end faultify_top;
architecture behav of faultify_top is
component flag_cdc
port (
clkA : in std_logic;
clkB : in std_logic;
FlagIn_clkA : in std_logic;
FlagOut_clkB : out std_logic;
rst_n : in std_logic);
end component;
component faultify_simulator
generic (
numInj : integer;
numIn : integer;
numOut : integer);
port (
clk : in std_logic;
clk_m : in std_logic;
circ_ce : in std_logic;
circ_rst : in std_logic;
test : out std_logic_vector(31 downto 0);
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector_o : out std_logic_vector(numOut-1 downto 0);
resultvector_f : out std_logic_vector(numOut-1 downto 0);
seed_in_en : in std_logic;
seed_in : in std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
shift_en : in std_logic;
rst_n : in std_logic);
end component;
component lfsr
generic (
width : integer;
seed : integer);
port (
clk : in std_logic;
rand_out : out std_logic_vector(width-1 downto 0));
end component;
type vector is array (0 to numOut-1) of std_logic_vector(31 downto 0);
signal errorSum : vector;
signal errorSumReg : vector;
signal errorSumReg_cdc_0 : vector;
signal errorSumReg_cdc_1 : vector;
signal errorVec : std_logic_vector(numOut-1 downto 0);
signal cnt : integer;
signal cnt_cdc_0 : integer;
signal cnt_cdc_1 : integer;
-- Asymmetric ram larger than 36 bit not supported in synplify I-2013
--type seed_ram_matr is array (0 to numInj-1) of std_logic_vector(63 downto 0);
--signal seed_ram : seed_ram_matr;
-- workaround 2 32-bit rams
type seed_ram_matr is array (0 to numInj-1) of std_logic_vector(31 downto 0);
signal seed_ram_low : seed_ram_matr;
signal seed_ram_high : seed_ram_matr;
--subtype seed_ram_matr_word_t is std_logic_vector(63 downto 0);
--type seed_ram_matr_memory_t is array (0 to numInj-1) of seed_ram_matr_word_t;
--signal seed_ram : seed_ram_matr_memory_t;
type prob_ram_matr is array (0 to numInj-1) of std_logic_vector(31 downto 0);
signal prob_ram : prob_ram_matr;
type reg_type is record
control : std_logic_vector(31 downto 0);
status : std_logic_vector(31 downto 0);
pe_location : std_logic_vector(31 downto 0);
pe_seed_low : std_logic_vector(31 downto 0);
pe_seed_high : std_logic_vector(31 downto 0);
pe_probability : std_logic_vector(31 downto 0);
output : std_logic_vector(31 downto 0);
ovalid : std_logic;
simtime : std_logic_vector(31 downto 0);
sel_soe : std_logic_vector(31 downto 0);
adr_soe : std_logic_vector(31 downto 0);
awaddr : std_logic_vector(31 downto 0);
test : std_logic_vector(31 downto 0);
circreset : std_logic_vector(31 downto 0);
cnt_tmp : std_logic_vector(31 downto 0);
sumoferrors : vector;
end record;
signal busy_loading : std_logic;
signal busy_simulating : std_logic;
signal busy_loading_reg : std_logic_vector(1 downto 0);
signal busy_simulating_reg : std_logic_vector(1 downto 0);
signal sim_done : std_logic;
signal r : reg_type;
type load_fsm_states is (IDLE, LOADSEED, LOADPROB);
signal l_state : load_fsm_states;
type sim_states is (IDLE, DELAY_Z, DELAY, SIMULATION, DELAY2, DELAY3, DELAY4, FREE_SIMULATION);
signal s_state : sim_states;
signal testvector : std_logic_vector(numIn-1 downto 0);
signal resultvector_o : std_logic_vector(numOut-1 downto 0);
signal resultvector_f : std_logic_vector(numOut-1 downto 0);
signal seed_in_en : std_logic;
signal seed_in : std_logic;
signal prob_in_en : std_logic;
signal prob_in : std_logic;
signal shift_en : std_logic;
signal shift_en_l : std_logic;
signal shift_en_s : std_logic;
signal load_seed_prob : std_logic;
signal start_simulation : std_logic;
signal start_free_simulation : std_logic;
signal stop_simulation : std_logic;
signal circ_ce, circ_rst, circ_rst_sim : std_logic;
signal tvec : std_logic_vector(127 downto 0);
signal test : std_logic_vector(31 downto 0);
signal rst_cdc, rst_cdc_n : std_logic;
type tb_state_defs is (IDLE, DATA, WAITING);
signal tb_state : tb_state_defs;
begin -- behav
-----------------------------------------------------------------------------
-- PRNG shifting
-----------------------------------------------------------------------------
shift_en <= shift_en_l or shift_en_s;
-----------------------------------------------------------------------------
-- Testvector
-----------------------------------------------------------------------------
--testvector <= (others => '0');
lfsr_1 : lfsr
generic map (
width => 128,
seed => 3498327)
port map (
clk => clk,
rand_out => tvec);
testvector(63 downto 0) <= tvec(63 downto 0);
testvector(66 downto 64) <= "011";
testvector(68 downto 67) <= "00";
--testvector(69) <= tvec(64);
process (clk, circ_rst_sim) is
begin -- process
if circ_rst_sim = '1' then -- asynchronous reset (active low)
testvector(69) <= '0';
tb_state <= IDLE;
elsif clk'event and clk = '1' then -- rising clock edge
case tb_state is
when IDLE =>
tb_state <= DATA;
testvector(69) <= '1';
when DATA =>
tb_state <= WAITING;
testvector(69) <= '0';
when WAITING =>
if resultvector_o(32) = '1' then
tb_state <= DATA;
testvector(69) <= '1';
end if;
end case;
end if;
end process;
-----------------------------------------------------------------------------
-- Simulator
-----------------------------------------------------------------------------
circ_rst <= circ_rst_sim when r.circreset(0) = '1' else '0';
faultify_simulator_1 : faultify_simulator
generic map (
numInj => numInj,
numIn => numIn,
numOut => numOut)
port map (
clk => clk_x32,
clk_m => clk,
circ_ce => circ_ce,
circ_rst => circ_rst,
test => test,
testvector => testvector,
resultvector_o => resultvector_o,
resultvector_f => resultvector_f,
seed_in_en => seed_in_en,
seed_in => seed_in,
prob_in_en => prob_in_en,
prob_in => prob_in,
shift_en => shift_en,
rst_n => arst_n);
-------------------------------------------------------------------------------
-- One Process Flow
-------------------------------------------------------------------------------
register_process : process (aclk, arst_n)
variable write_addr : std_logic_vector(31 downto 0);
begin -- process register_process
if arst_n = '0' then -- asynchronous reset (active low)
r.control <= (others => '0');
r.status <= (others => '0');
r.pe_probability <= (others => '0');
r.pe_seed_high <= (others => '0');
r.pe_seed_low <= (others => '0');
r.pe_location <= (others => '0');
r.ovalid <= '0';
r.simtime <= (others => '0');
r.sel_soe <= (others => '0');
r.adr_soe <= (others => '0');
r.sumoferrors <= (others => (others => '0'));
r.output <= (others => '0');
elsif aclk'event and aclk = '1' then -- rising clock edge
r.control <= (others => '0');
if awvalid = '1' then
r.awaddr <= awaddr;
write_addr := awaddr;
end if;
if wvalid = '1' then
if write_addr = x"00000000" then
r.control <= wdata;
elsif write_addr = x"00000001" then
r.pe_location <= wdata;
elsif write_addr = x"00000002" then
r.pe_seed_low <= wdata;
elsif write_addr = x"00000003" then
r.pe_seed_high <= wdata;
elsif write_addr = x"00000004" then
r.pe_probability <= wdata;
elsif write_addr = x"00000005" then
r.cnt_tmp <= std_logic_vector(to_unsigned(cnt_cdc_1, 32));
r.adr_soe <= wdata;
elsif write_addr = x"00000007" then
r.simtime <= wdata;
elsif write_addr = x"00000009" then
r.circreset <= wdata;
end if;
end if;
if arvalid = '1' then
if araddr = x"0000000F" then
r.output <= r.status;
elsif araddr = x"00000001" then
r.output <= r.pe_location;
elsif araddr = x"00000002" then
r.output <= r.pe_seed_low;
elsif araddr = x"00000003" then
r.output <= r.pe_seed_high;
elsif araddr = x"00000004" then
r.output <= r.pe_probability;
elsif araddr = x"00000006" then
r.output <= r.sel_soe;
elsif araddr = x"00000008" then
r.output <= r.test;
elsif araddr = x"0000000A" then
r.output <= r.cnt_tmp;
end if;
r.ovalid <= '1';
else
r.ovalid <= '0';
end if;
if busy_loading_reg(1) = '1' then
r.status(0) <= '1';
else
r.status(0) <= '0';
end if;
if busy_simulating_reg(1) = '1' then
r.status(1) <= '1';
else
r.status(1) <= '0';
end if;
r.sel_soe <= r.sumoferrors(to_integer(unsigned(r.adr_soe)));
rdata <= r.output;
rvalid <= r.ovalid;
r.sumoferrors <= errorSumReg_cdc_1;
r.test <= errorSum(0);
end if;
end process register_process;
-----------------------------------------------------------------------------
-- simple clock domain crossing
-----------------------------------------------------------------------------
process (aclk, arst_n)
begin -- process
if arst_n = '0' then -- asynchronous reset (active low)
busy_simulating_reg <= (others => '0');
busy_loading_reg <= (others => '0');
elsif aclk'event and aclk = '1' then -- rising clock edge
busy_simulating_reg(0) <= busy_simulating;
busy_loading_reg(0) <= busy_loading;
busy_simulating_reg(1) <= busy_simulating_reg(0);
busy_loading_reg(1) <= busy_loading_reg(0);
cnt_cdc_0 <= cnt;
cnt_cdc_1 <= cnt_cdc_0;
errorSumReg_cdc_0 <= errorSumReg;
errorSumReg_cdc_1 <= errorSumReg_cdc_0;
end if;
end process;
-------------------------------------------------------------------------------
-- Store seeed/prob
-------------------------------------------------------------------------------
store_seed : process (aclk, arst_n)
begin -- process store_seed
if arst_n = '0' then -- asynchronous reset (active low)
elsif aclk'event and aclk = '1' then -- rising clock edge
if r.control(0) = '1' then
-- Synplify bug workaround
--seed_ram(to_integer(unsigned(r.pe_location))) <= r.pe_seed_high & r.pe_seed_low;
seed_ram_low(to_integer(unsigned(r.pe_location))) <= r.pe_seed_low;
seed_ram_high(to_integer(unsigned(r.pe_location))) <= r.pe_seed_high;
prob_ram(to_integer(unsigned(r.pe_location))) <= r.pe_probability;
end if;
end if;
end process store_seed;
-----------------------------------------------------------------------------
-- Seed/prob loading FSM
-----------------------------------------------------------------------------
--flag_cdc_1 : flag_cdc
-- port map (
-- clkA => aclk,
-- clkB => clk_x32,
-- FlagIn_clkA => r.control(1),
-- FlagOut_clkB => load_seed_prob,
-- rst_n => arst_n);
load_seed_prob <= r.control(1);
seed_prob_loading : process (clk_x32, arst_n)
variable cnt_seed : integer range 0 to 64;
variable cnt_inj : integer range 0 to numInj;
variable cnt_prob : integer range 0 to 32;
begin -- process seed_prob_loading
if arst_n = '0' then -- asynchronous reset (active low)
l_state <= IDLE;
seed_in <= '0';
seed_in_en <= '0';
prob_in <= '0';
prob_in_en <= '0';
shift_en_l <= '0';
busy_loading <= '0';
elsif clk_x32'event and clk_x32 = '1' then -- rising clock edge
case l_state is
when IDLE =>
cnt_seed := 0;
cnt_inj := 0;
cnt_prob := 0;
busy_loading <= '0';
seed_in_en <= '0';
prob_in_en <= '0';
shift_en_l <= '0';
if load_seed_prob = '1' then
busy_loading <= '1';
l_state <= LOADSEED;
end if;
when LOADSEED =>
if cnt_seed < 64 then
shift_en_l <= '1';
seed_in_en <= '1';
-- not working in synplify I-2013
--seed_in <= seed_ram(cnt_inj)(cnt_seed);
--
if cnt_seed < 32 then
seed_in <= seed_ram_low(cnt_inj)(cnt_seed);
else
seed_in <= seed_ram_high(cnt_inj)(cnt_seed-32);
end if;
cnt_seed := cnt_seed + 1;
end if;
if cnt_seed = 64 then
cnt_seed := 0;
cnt_inj := cnt_inj + 1;
end if;
if cnt_inj = numInj then
l_state <= LOADPROB;
--seed_in_en <= '0';
cnt_inj := 0;
end if;
when LOADPROB =>
seed_in_en <= '0';
if cnt_prob < 32 then
prob_in_en <= '1';
prob_in <= prob_ram(cnt_inj)(cnt_prob);
cnt_prob := cnt_prob + 1;
end if;
if cnt_prob = 32 then
cnt_prob := 0;
cnt_inj := cnt_inj + 1;
end if;
if cnt_inj = numInj then
l_state <= IDLE;
cnt_inj := 0;
--prob_in_en <= '0';
end if;
end case;
end if;
end process seed_prob_loading;
-----------------------------------------------------------------------------
-- Simulation FSM
-----------------------------------------------------------------------------
flag_cdc_2 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(2),
FlagOut_clkB => start_simulation,
rst_n => arst_n);
flag_cdc_3 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(3),
FlagOut_clkB => start_free_simulation,
rst_n => arst_n);
flag_cdc_4 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(4),
FlagOut_clkB => stop_simulation,
rst_n => arst_n);
rst_cdc_5 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => not arst_n,
FlagOut_clkB => rst_cdc,
rst_n => '1');
rst_cdc_n <= not rst_cdc;
process (clk, rst_cdc_n)
variable simtime : integer;
variable cnt_delay : integer range 0 to 9;
begin -- process
if clk'event and clk = '1' then -- rising clock edge
if rst_cdc_n = '0' then -- asynchronous reset (active low)
s_state <= IDLE;
errorVec <= (others => '0');
errorSum <= (others => (others => '0'));
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
busy_simulating <= '0';
sim_done <= '0';
errorSumReg <= (others => (others => '0'));
else
case s_state is
when IDLE =>
sim_done <= '0';
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
errorVec <= (others => '0');
--errorSum <= errorSum;
errorSum <= (others => (others => '0'));
--cnt <= 0;
busy_simulating <= '0';
cnt_delay := 0;
if start_simulation = '1' then
cnt <= 0;
busy_simulating <= '1';
errorSum <= (others => (others => '0'));
errorSumReg <= (others => (others => '0'));
simtime := to_integer(unsigned(r.simtime));
s_state <= DELAY_Z;
circ_ce <= '1';
circ_rst_sim <= '0';
shift_en_s <= '1';
end if;
if start_free_simulation = '1' then
cnt <= 0;
busy_simulating <= '1';
errorSum <= (others => (others => '0'));
errorSumReg <= (others => (others => '0'));
s_state <= FREE_SIMULATION;
circ_ce <= '1';
circ_rst_sim <= '0';
shift_en_s <= '1';
end if;
when DELAY_z =>
cnt_delay := cnt_delay + 1;
if cnt_delay = 9 then
s_state <= DELAY;
end if;
when DELAY =>
s_state <= SIMULATION;
errorVec <= (others => '0');
errorSum <= (others => (others => '0'));
when SIMULATION =>
circ_rst_sim <= '0';
shift_en_s <= '1';
-- collect errors
if (resultVector_o(32) = '1') then
errorVec <= resultvector_o xor resultvector_f;
else
errorVec <= (others => '0');
end if;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
--
errorSumReg <= errorSum;
if cnt = simtime-1 then
s_state <= DELAY2;
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
end if;
cnt <= cnt +1;
when DELAY2 =>
if (resultVector_o(32) = '1') then
errorVec <= resultvector_o xor resultvector_f;
else
errorVec <= (others => '0');
end if;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
s_state <= DELAY3;
when DELAY3 =>
s_state <= DELAY4;
errorSumReg <= errorSum;
errorSum <= (others => (others => '0'));
when DELAY4 =>
s_state <= IDLE;
sim_done <= '1';
when FREE_SIMULATION =>
circ_rst_sim <= '0';
shift_en_s <= '1';
-- collect errors
if (resultVector_o(32) = '1') then
errorVec <= resultvector_o xor resultvector_f;
else
errorVec <= (others => '0');
end if;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
--
errorSumReg <= errorSum;
if stop_simulation = '1' then
s_state <= IDLE;
sim_done <= '1';
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
end if;
cnt <= cnt +1;
when others =>
s_state <= IDLE;
end case;
end if;
end if;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_top is
generic (
numInj : integer := 56;
numIn : integer := 10;
numOut : integer := 10);
port (
aclk : in std_logic; -- interface clock
arst_n : in std_logic; -- interface reset
clk : in std_logic; -- simulation clock (slow)
clk_x32 : in std_logic; -- prng clock (fast)
-- Write channel
awvalid : in std_logic;
awaddr : in std_logic_vector(31 downto 0);
wvalid : in std_logic;
wdata : in std_logic_vector(31 downto 0);
-- Read channel
arvalid : in std_logic;
araddr : in std_logic_vector(31 downto 0);
rvalid : out std_logic;
rdata : out std_logic_vector(31 downto 0)
);
attribute syn_hier : string;
attribute syn_hier of faultify_top : entity is "hard";
end faultify_top;
architecture behav of faultify_top is
component flag_cdc
port (
clkA : in std_logic;
clkB : in std_logic;
FlagIn_clkA : in std_logic;
FlagOut_clkB : out std_logic;
rst_n : in std_logic);
end component;
component faultify_simulator
generic (
numInj : integer;
numIn : integer;
numOut : integer);
port (
clk : in std_logic;
clk_m : in std_logic;
circ_ce : in std_logic;
circ_rst : in std_logic;
test : out std_logic_vector(31 downto 0);
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector_o : out std_logic_vector(numOut-1 downto 0);
resultvector_f : out std_logic_vector(numOut-1 downto 0);
seed_in_en : in std_logic;
seed_in : in std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
shift_en : in std_logic;
rst_n : in std_logic);
end component;
component lfsr
generic (
width : integer;
seed : integer);
port (
clk : in std_logic;
rand_out : out std_logic_vector(width-1 downto 0));
end component;
type vector is array (0 to numOut-1) of std_logic_vector(31 downto 0);
signal errorSum : vector;
signal errorSumReg : vector;
signal errorSumReg_cdc_0 : vector;
signal errorSumReg_cdc_1 : vector;
signal errorVec : std_logic_vector(numOut-1 downto 0);
signal cnt : integer;
signal cnt_cdc_0 : integer;
signal cnt_cdc_1 : integer;
-- Asymmetric ram larger than 36 bit not supported in synplify I-2013
--type seed_ram_matr is array (0 to numInj-1) of std_logic_vector(63 downto 0);
--signal seed_ram : seed_ram_matr;
-- workaround 2 32-bit rams
type seed_ram_matr is array (0 to numInj-1) of std_logic_vector(31 downto 0);
signal seed_ram_low : seed_ram_matr;
signal seed_ram_high : seed_ram_matr;
--subtype seed_ram_matr_word_t is std_logic_vector(63 downto 0);
--type seed_ram_matr_memory_t is array (0 to numInj-1) of seed_ram_matr_word_t;
--signal seed_ram : seed_ram_matr_memory_t;
type prob_ram_matr is array (0 to numInj-1) of std_logic_vector(31 downto 0);
signal prob_ram : prob_ram_matr;
type reg_type is record
control : std_logic_vector(31 downto 0);
status : std_logic_vector(31 downto 0);
pe_location : std_logic_vector(31 downto 0);
pe_seed_low : std_logic_vector(31 downto 0);
pe_seed_high : std_logic_vector(31 downto 0);
pe_probability : std_logic_vector(31 downto 0);
output : std_logic_vector(31 downto 0);
ovalid : std_logic;
simtime : std_logic_vector(31 downto 0);
sel_soe : std_logic_vector(31 downto 0);
adr_soe : std_logic_vector(31 downto 0);
awaddr : std_logic_vector(31 downto 0);
test : std_logic_vector(31 downto 0);
circreset : std_logic_vector(31 downto 0);
cnt_tmp : std_logic_vector(31 downto 0);
sumoferrors : vector;
end record;
signal busy_loading : std_logic;
signal busy_simulating : std_logic;
signal busy_loading_reg : std_logic_vector(1 downto 0);
signal busy_simulating_reg : std_logic_vector(1 downto 0);
signal sim_done : std_logic;
signal r : reg_type;
type load_fsm_states is (IDLE, LOADSEED, LOADPROB);
signal l_state : load_fsm_states;
type sim_states is (IDLE, DELAY_Z, DELAY, SIMULATION, DELAY2, DELAY3, DELAY4, FREE_SIMULATION);
signal s_state : sim_states;
signal testvector : std_logic_vector(numIn-1 downto 0);
signal resultvector_o : std_logic_vector(numOut-1 downto 0);
signal resultvector_f : std_logic_vector(numOut-1 downto 0);
signal seed_in_en : std_logic;
signal seed_in : std_logic;
signal prob_in_en : std_logic;
signal prob_in : std_logic;
signal shift_en : std_logic;
signal shift_en_l : std_logic;
signal shift_en_s : std_logic;
signal load_seed_prob : std_logic;
signal start_simulation : std_logic;
signal start_free_simulation : std_logic;
signal stop_simulation : std_logic;
signal circ_ce, circ_rst, circ_rst_sim : std_logic;
signal tvec : std_logic_vector(127 downto 0);
signal test : std_logic_vector(31 downto 0);
signal rst_cdc, rst_cdc_n : std_logic;
type tb_state_defs is (IDLE, DATA, WAITING);
signal tb_state : tb_state_defs;
begin -- behav
-----------------------------------------------------------------------------
-- PRNG shifting
-----------------------------------------------------------------------------
shift_en <= shift_en_l or shift_en_s;
-----------------------------------------------------------------------------
-- Testvector
-----------------------------------------------------------------------------
--testvector <= (others => '0');
lfsr_1 : lfsr
generic map (
width => 128,
seed => 3498327)
port map (
clk => clk,
rand_out => tvec);
testvector(63 downto 0) <= tvec(63 downto 0);
testvector(66 downto 64) <= "011";
testvector(68 downto 67) <= "00";
--testvector(69) <= tvec(64);
process (clk, circ_rst_sim) is
begin -- process
if circ_rst_sim = '1' then -- asynchronous reset (active low)
testvector(69) <= '0';
tb_state <= IDLE;
elsif clk'event and clk = '1' then -- rising clock edge
case tb_state is
when IDLE =>
tb_state <= DATA;
testvector(69) <= '1';
when DATA =>
tb_state <= WAITING;
testvector(69) <= '0';
when WAITING =>
if resultvector_o(32) = '1' then
tb_state <= DATA;
testvector(69) <= '1';
end if;
end case;
end if;
end process;
-----------------------------------------------------------------------------
-- Simulator
-----------------------------------------------------------------------------
circ_rst <= circ_rst_sim when r.circreset(0) = '1' else '0';
faultify_simulator_1 : faultify_simulator
generic map (
numInj => numInj,
numIn => numIn,
numOut => numOut)
port map (
clk => clk_x32,
clk_m => clk,
circ_ce => circ_ce,
circ_rst => circ_rst,
test => test,
testvector => testvector,
resultvector_o => resultvector_o,
resultvector_f => resultvector_f,
seed_in_en => seed_in_en,
seed_in => seed_in,
prob_in_en => prob_in_en,
prob_in => prob_in,
shift_en => shift_en,
rst_n => arst_n);
-------------------------------------------------------------------------------
-- One Process Flow
-------------------------------------------------------------------------------
register_process : process (aclk, arst_n)
variable write_addr : std_logic_vector(31 downto 0);
begin -- process register_process
if arst_n = '0' then -- asynchronous reset (active low)
r.control <= (others => '0');
r.status <= (others => '0');
r.pe_probability <= (others => '0');
r.pe_seed_high <= (others => '0');
r.pe_seed_low <= (others => '0');
r.pe_location <= (others => '0');
r.ovalid <= '0';
r.simtime <= (others => '0');
r.sel_soe <= (others => '0');
r.adr_soe <= (others => '0');
r.sumoferrors <= (others => (others => '0'));
r.output <= (others => '0');
elsif aclk'event and aclk = '1' then -- rising clock edge
r.control <= (others => '0');
if awvalid = '1' then
r.awaddr <= awaddr;
write_addr := awaddr;
end if;
if wvalid = '1' then
if write_addr = x"00000000" then
r.control <= wdata;
elsif write_addr = x"00000001" then
r.pe_location <= wdata;
elsif write_addr = x"00000002" then
r.pe_seed_low <= wdata;
elsif write_addr = x"00000003" then
r.pe_seed_high <= wdata;
elsif write_addr = x"00000004" then
r.pe_probability <= wdata;
elsif write_addr = x"00000005" then
r.cnt_tmp <= std_logic_vector(to_unsigned(cnt_cdc_1, 32));
r.adr_soe <= wdata;
elsif write_addr = x"00000007" then
r.simtime <= wdata;
elsif write_addr = x"00000009" then
r.circreset <= wdata;
end if;
end if;
if arvalid = '1' then
if araddr = x"0000000F" then
r.output <= r.status;
elsif araddr = x"00000001" then
r.output <= r.pe_location;
elsif araddr = x"00000002" then
r.output <= r.pe_seed_low;
elsif araddr = x"00000003" then
r.output <= r.pe_seed_high;
elsif araddr = x"00000004" then
r.output <= r.pe_probability;
elsif araddr = x"00000006" then
r.output <= r.sel_soe;
elsif araddr = x"00000008" then
r.output <= r.test;
elsif araddr = x"0000000A" then
r.output <= r.cnt_tmp;
end if;
r.ovalid <= '1';
else
r.ovalid <= '0';
end if;
if busy_loading_reg(1) = '1' then
r.status(0) <= '1';
else
r.status(0) <= '0';
end if;
if busy_simulating_reg(1) = '1' then
r.status(1) <= '1';
else
r.status(1) <= '0';
end if;
r.sel_soe <= r.sumoferrors(to_integer(unsigned(r.adr_soe)));
rdata <= r.output;
rvalid <= r.ovalid;
r.sumoferrors <= errorSumReg_cdc_1;
r.test <= errorSum(0);
end if;
end process register_process;
-----------------------------------------------------------------------------
-- simple clock domain crossing
-----------------------------------------------------------------------------
process (aclk, arst_n)
begin -- process
if arst_n = '0' then -- asynchronous reset (active low)
busy_simulating_reg <= (others => '0');
busy_loading_reg <= (others => '0');
elsif aclk'event and aclk = '1' then -- rising clock edge
busy_simulating_reg(0) <= busy_simulating;
busy_loading_reg(0) <= busy_loading;
busy_simulating_reg(1) <= busy_simulating_reg(0);
busy_loading_reg(1) <= busy_loading_reg(0);
cnt_cdc_0 <= cnt;
cnt_cdc_1 <= cnt_cdc_0;
errorSumReg_cdc_0 <= errorSumReg;
errorSumReg_cdc_1 <= errorSumReg_cdc_0;
end if;
end process;
-------------------------------------------------------------------------------
-- Store seeed/prob
-------------------------------------------------------------------------------
store_seed : process (aclk, arst_n)
begin -- process store_seed
if arst_n = '0' then -- asynchronous reset (active low)
elsif aclk'event and aclk = '1' then -- rising clock edge
if r.control(0) = '1' then
-- Synplify bug workaround
--seed_ram(to_integer(unsigned(r.pe_location))) <= r.pe_seed_high & r.pe_seed_low;
seed_ram_low(to_integer(unsigned(r.pe_location))) <= r.pe_seed_low;
seed_ram_high(to_integer(unsigned(r.pe_location))) <= r.pe_seed_high;
prob_ram(to_integer(unsigned(r.pe_location))) <= r.pe_probability;
end if;
end if;
end process store_seed;
-----------------------------------------------------------------------------
-- Seed/prob loading FSM
-----------------------------------------------------------------------------
--flag_cdc_1 : flag_cdc
-- port map (
-- clkA => aclk,
-- clkB => clk_x32,
-- FlagIn_clkA => r.control(1),
-- FlagOut_clkB => load_seed_prob,
-- rst_n => arst_n);
load_seed_prob <= r.control(1);
seed_prob_loading : process (clk_x32, arst_n)
variable cnt_seed : integer range 0 to 64;
variable cnt_inj : integer range 0 to numInj;
variable cnt_prob : integer range 0 to 32;
begin -- process seed_prob_loading
if arst_n = '0' then -- asynchronous reset (active low)
l_state <= IDLE;
seed_in <= '0';
seed_in_en <= '0';
prob_in <= '0';
prob_in_en <= '0';
shift_en_l <= '0';
busy_loading <= '0';
elsif clk_x32'event and clk_x32 = '1' then -- rising clock edge
case l_state is
when IDLE =>
cnt_seed := 0;
cnt_inj := 0;
cnt_prob := 0;
busy_loading <= '0';
seed_in_en <= '0';
prob_in_en <= '0';
shift_en_l <= '0';
if load_seed_prob = '1' then
busy_loading <= '1';
l_state <= LOADSEED;
end if;
when LOADSEED =>
if cnt_seed < 64 then
shift_en_l <= '1';
seed_in_en <= '1';
-- not working in synplify I-2013
--seed_in <= seed_ram(cnt_inj)(cnt_seed);
--
if cnt_seed < 32 then
seed_in <= seed_ram_low(cnt_inj)(cnt_seed);
else
seed_in <= seed_ram_high(cnt_inj)(cnt_seed-32);
end if;
cnt_seed := cnt_seed + 1;
end if;
if cnt_seed = 64 then
cnt_seed := 0;
cnt_inj := cnt_inj + 1;
end if;
if cnt_inj = numInj then
l_state <= LOADPROB;
--seed_in_en <= '0';
cnt_inj := 0;
end if;
when LOADPROB =>
seed_in_en <= '0';
if cnt_prob < 32 then
prob_in_en <= '1';
prob_in <= prob_ram(cnt_inj)(cnt_prob);
cnt_prob := cnt_prob + 1;
end if;
if cnt_prob = 32 then
cnt_prob := 0;
cnt_inj := cnt_inj + 1;
end if;
if cnt_inj = numInj then
l_state <= IDLE;
cnt_inj := 0;
--prob_in_en <= '0';
end if;
end case;
end if;
end process seed_prob_loading;
-----------------------------------------------------------------------------
-- Simulation FSM
-----------------------------------------------------------------------------
flag_cdc_2 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(2),
FlagOut_clkB => start_simulation,
rst_n => arst_n);
flag_cdc_3 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(3),
FlagOut_clkB => start_free_simulation,
rst_n => arst_n);
flag_cdc_4 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(4),
FlagOut_clkB => stop_simulation,
rst_n => arst_n);
rst_cdc_5 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => not arst_n,
FlagOut_clkB => rst_cdc,
rst_n => '1');
rst_cdc_n <= not rst_cdc;
process (clk, rst_cdc_n)
variable simtime : integer;
variable cnt_delay : integer range 0 to 9;
begin -- process
if clk'event and clk = '1' then -- rising clock edge
if rst_cdc_n = '0' then -- asynchronous reset (active low)
s_state <= IDLE;
errorVec <= (others => '0');
errorSum <= (others => (others => '0'));
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
busy_simulating <= '0';
sim_done <= '0';
errorSumReg <= (others => (others => '0'));
else
case s_state is
when IDLE =>
sim_done <= '0';
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
errorVec <= (others => '0');
--errorSum <= errorSum;
errorSum <= (others => (others => '0'));
--cnt <= 0;
busy_simulating <= '0';
cnt_delay := 0;
if start_simulation = '1' then
cnt <= 0;
busy_simulating <= '1';
errorSum <= (others => (others => '0'));
errorSumReg <= (others => (others => '0'));
simtime := to_integer(unsigned(r.simtime));
s_state <= DELAY_Z;
circ_ce <= '1';
circ_rst_sim <= '0';
shift_en_s <= '1';
end if;
if start_free_simulation = '1' then
cnt <= 0;
busy_simulating <= '1';
errorSum <= (others => (others => '0'));
errorSumReg <= (others => (others => '0'));
s_state <= FREE_SIMULATION;
circ_ce <= '1';
circ_rst_sim <= '0';
shift_en_s <= '1';
end if;
when DELAY_z =>
cnt_delay := cnt_delay + 1;
if cnt_delay = 9 then
s_state <= DELAY;
end if;
when DELAY =>
s_state <= SIMULATION;
errorVec <= (others => '0');
errorSum <= (others => (others => '0'));
when SIMULATION =>
circ_rst_sim <= '0';
shift_en_s <= '1';
-- collect errors
if (resultVector_o(32) = '1') then
errorVec <= resultvector_o xor resultvector_f;
else
errorVec <= (others => '0');
end if;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
--
errorSumReg <= errorSum;
if cnt = simtime-1 then
s_state <= DELAY2;
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
end if;
cnt <= cnt +1;
when DELAY2 =>
if (resultVector_o(32) = '1') then
errorVec <= resultvector_o xor resultvector_f;
else
errorVec <= (others => '0');
end if;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
s_state <= DELAY3;
when DELAY3 =>
s_state <= DELAY4;
errorSumReg <= errorSum;
errorSum <= (others => (others => '0'));
when DELAY4 =>
s_state <= IDLE;
sim_done <= '1';
when FREE_SIMULATION =>
circ_rst_sim <= '0';
shift_en_s <= '1';
-- collect errors
if (resultVector_o(32) = '1') then
errorVec <= resultvector_o xor resultvector_f;
else
errorVec <= (others => '0');
end if;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
--
errorSumReg <= errorSum;
if stop_simulation = '1' then
s_state <= IDLE;
sim_done <= '1';
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
end if;
cnt <= cnt +1;
when others =>
s_state <= IDLE;
end case;
end if;
end if;
end process;
end behav;
|
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: IMG3.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY IMG3 IS
PORT
(
address : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (39 DOWNTO 0)
);
END IMG3;
ARCHITECTURE SYN OF img3 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (39 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (39 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(39 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "./ROM/IMG3.mif",
intended_device_family => "Cyclone IV E",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 128,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 7,
width_a => 40,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "./ROM/IMG3.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "128"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "7"
-- Retrieval info: PRIVATE: WidthData NUMERIC "40"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "./ROM/IMG3.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "40"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 7 0 INPUT NODEFVAL "address[6..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 40 0 OUTPUT NODEFVAL "q[39..0]"
-- Retrieval info: CONNECT: @address_a 0 0 7 0 address 0 0 7 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 40 0 @q_a 0 0 40 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL IMG3.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL IMG3.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL IMG3.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL IMG3.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL IMG3_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
architecture RTl of FIFO is
component fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic; -- Comment
sig2 : std_logic; -- Comment
sig3 : std_logic -- Comment
);
end component fifo;
-- Failures below
component fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic; -- Comment
sig2 : std_logic; -- Comment
sig3 : std_logic -- Comment
);
end component fifo;
begin
end architecture RTL;
|
-- Copyright (c) University of Florida
--
-- This file is part of window_gen.
--
-- window_gen is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- window_gen is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with window_gen. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- Yang Zheng
-- Eric Schwartz
-- University of Florida
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
--use ieee.fixed_float_types.all;
--use ieee.float_pkg.all;
--library ieee_proposed;
--use ieee_proposed.fixed_float_types.all; -- ieee in the release
--use ieee_proposed.float_pkg.all; -- ieee.float_pkg.all; in the release
package tb_pkg is
-----------------------------------------------------------------------
-- Procedure randomIn
-- Description: create random integer within a specified range
--
-- Parameters:
-- seed1/2 : seed values for random number generation
-- min : lower bound on randomly generated number
-- max : upper bound on randomly generated number
-- result : randomly generated integer
--
-- Preconditions: min <= max
-----------------------------------------------------------------------
procedure randomInt
(variable seed1, seed2 : inout positive; min, max : in integer;
variable result : out integer);
----------------------------------------------------------
-- Procedure randDecision
-- Description: randomly decide true/false based on a specified probability
--
-- Parameters:
-- seed1/2 : seed values for random number generation
-- prob : probability that decision will be yes/true
-- decision : the resulting decision
----------------------------------------------------------
procedure randDecision(seed1, seed2 : inout positive;
prob : real;
decision : out boolean);
----------------------------------------------------------
-- Procedure randDelay
-- Description: Create a delay with random cycle length, with specified
-- probability.
--
-- Parameters:
-- seed1/2 : seed values for random number generation
-- clk : The clock signal used for the delay
-- prob : probability that the delay will occur
-- min : the minimum cycle delay
-- max : the maximum cycle delay
----------------------------------------------------------
procedure randDelay(seed1, seed2 : inout positive;
signal clk : std_logic;
prob : real;
min, max : natural);
end tb_pkg;
package body tb_pkg is
-- procedure randomFloat(variable seed1, seed2 : inout positive; min, max : in real; variable result : out std_logic_vector(31 downto 0)) is
-- variable rand : real; -- Random real value in range 0 to 1.0
-- variable result_real : float32;
-- begin
-- assert (min <= max) report "ERROR: In randomFloat(), min must be <= max" severity error;
-- UNIFORM(seed1, seed2, rand); -- generate random number
-- --report"Random value is" & real'image(rand);
-- result_real := to_float((max-min)*rand+min, result_real'high, -result_real'low);
-- result := to_slv(result_real);
-- end randomFloat;
procedure randomInt(variable seed1, seed2 : inout positive; min, max : in integer; variable result : out integer) is
variable rand : real; -- Random real value in range 0 to 1.0
begin
assert (min <= max) report "ERROR: In randomInt(), min must be <= max" severity error;
UNIFORM(seed1, seed2, rand); -- generate random number
result := integer(TRUNC(real(max-min)*rand+real(min)));
--report"Random(int) value is " & integer'image(result);
end randomInt;
procedure randDecision(seed1, seed2 : inout positive;
prob : real;
decision : out boolean) is
variable rand : real;
begin
UNIFORM(seed1, seed2, rand);
if rand < prob then
decision := true;
else
decision := false;
end if;
end procedure;
procedure randDelay(seed1, seed2 : inout positive;
signal clk : std_logic;
prob : real;
min, max : natural) is
variable should_delay : boolean;
variable cycle_delay : natural;
begin
-- decide whether or not to delay
randDecision(seed1, seed2, prob, should_delay);
if should_delay then
-- delay by a random amount between min and max
randomInt(seed1, seed2, min, max, cycle_delay);
if cycle_delay > 0 then
for i in 0 to cycle_delay-1 loop
wait until rising_edge(clk);
end loop;
end if;
end if;
end procedure;
end package body;
|
-- Copyright (c) University of Florida
--
-- This file is part of window_gen.
--
-- window_gen is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- window_gen is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with window_gen. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- Yang Zheng
-- Eric Schwartz
-- University of Florida
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
--use ieee.fixed_float_types.all;
--use ieee.float_pkg.all;
--library ieee_proposed;
--use ieee_proposed.fixed_float_types.all; -- ieee in the release
--use ieee_proposed.float_pkg.all; -- ieee.float_pkg.all; in the release
package tb_pkg is
-----------------------------------------------------------------------
-- Procedure randomIn
-- Description: create random integer within a specified range
--
-- Parameters:
-- seed1/2 : seed values for random number generation
-- min : lower bound on randomly generated number
-- max : upper bound on randomly generated number
-- result : randomly generated integer
--
-- Preconditions: min <= max
-----------------------------------------------------------------------
procedure randomInt
(variable seed1, seed2 : inout positive; min, max : in integer;
variable result : out integer);
----------------------------------------------------------
-- Procedure randDecision
-- Description: randomly decide true/false based on a specified probability
--
-- Parameters:
-- seed1/2 : seed values for random number generation
-- prob : probability that decision will be yes/true
-- decision : the resulting decision
----------------------------------------------------------
procedure randDecision(seed1, seed2 : inout positive;
prob : real;
decision : out boolean);
----------------------------------------------------------
-- Procedure randDelay
-- Description: Create a delay with random cycle length, with specified
-- probability.
--
-- Parameters:
-- seed1/2 : seed values for random number generation
-- clk : The clock signal used for the delay
-- prob : probability that the delay will occur
-- min : the minimum cycle delay
-- max : the maximum cycle delay
----------------------------------------------------------
procedure randDelay(seed1, seed2 : inout positive;
signal clk : std_logic;
prob : real;
min, max : natural);
end tb_pkg;
package body tb_pkg is
-- procedure randomFloat(variable seed1, seed2 : inout positive; min, max : in real; variable result : out std_logic_vector(31 downto 0)) is
-- variable rand : real; -- Random real value in range 0 to 1.0
-- variable result_real : float32;
-- begin
-- assert (min <= max) report "ERROR: In randomFloat(), min must be <= max" severity error;
-- UNIFORM(seed1, seed2, rand); -- generate random number
-- --report"Random value is" & real'image(rand);
-- result_real := to_float((max-min)*rand+min, result_real'high, -result_real'low);
-- result := to_slv(result_real);
-- end randomFloat;
procedure randomInt(variable seed1, seed2 : inout positive; min, max : in integer; variable result : out integer) is
variable rand : real; -- Random real value in range 0 to 1.0
begin
assert (min <= max) report "ERROR: In randomInt(), min must be <= max" severity error;
UNIFORM(seed1, seed2, rand); -- generate random number
result := integer(TRUNC(real(max-min)*rand+real(min)));
--report"Random(int) value is " & integer'image(result);
end randomInt;
procedure randDecision(seed1, seed2 : inout positive;
prob : real;
decision : out boolean) is
variable rand : real;
begin
UNIFORM(seed1, seed2, rand);
if rand < prob then
decision := true;
else
decision := false;
end if;
end procedure;
procedure randDelay(seed1, seed2 : inout positive;
signal clk : std_logic;
prob : real;
min, max : natural) is
variable should_delay : boolean;
variable cycle_delay : natural;
begin
-- decide whether or not to delay
randDecision(seed1, seed2, prob, should_delay);
if should_delay then
-- delay by a random amount between min and max
randomInt(seed1, seed2, min, max, cycle_delay);
if cycle_delay > 0 then
for i in 0 to cycle_delay-1 loop
wait until rising_edge(clk);
end loop;
end if;
end if;
end procedure;
end package body;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_2_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_2_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_2_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_2_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND FULL = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_vdma_0_wrapper_fifo_generator_v9_3_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_vdma_0_wrapper_fifo_generator_v9_3_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity hls_macc_HLS_MACC_PERIPH_BUS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
a :out STD_LOGIC_VECTOR(31 downto 0);
b :out STD_LOGIC_VECTOR(31 downto 0);
accum :in STD_LOGIC_VECTOR(31 downto 0);
accum_ap_vld :in STD_LOGIC;
accum_clr :out STD_LOGIC_VECTOR(0 downto 0)
);
end entity hls_macc_HLS_MACC_PERIPH_BUS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of a
-- bit 31~0 - a[31:0] (Read/Write)
-- 0x14 : reserved
-- 0x18 : Data signal of b
-- bit 31~0 - b[31:0] (Read/Write)
-- 0x1c : reserved
-- 0x20 : Data signal of accum
-- bit 31~0 - accum[31:0] (Read)
-- 0x24 : Control signal of accum
-- bit 0 - accum_ap_vld (Read/COR)
-- others - reserved
-- 0x28 : Data signal of accum_clr
-- bit 0 - accum_clr[0] (Read/Write)
-- others - reserved
-- 0x2c : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of hls_macc_HLS_MACC_PERIPH_BUS_s_axi is
type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states
signal wstate : states := wrreset;
signal rstate : states := rdreset;
signal wnext, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_A_DATA_0 : INTEGER := 16#10#;
constant ADDR_A_CTRL : INTEGER := 16#14#;
constant ADDR_B_DATA_0 : INTEGER := 16#18#;
constant ADDR_B_CTRL : INTEGER := 16#1c#;
constant ADDR_ACCUM_DATA_0 : INTEGER := 16#20#;
constant ADDR_ACCUM_CTRL : INTEGER := 16#24#;
constant ADDR_ACCUM_CLR_DATA_0 : INTEGER := 16#28#;
constant ADDR_ACCUM_CLR_CTRL : INTEGER := 16#2c#;
constant ADDR_BITS : INTEGER := 6;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC := '0';
signal int_ap_start : STD_LOGIC := '0';
signal int_auto_restart : STD_LOGIC := '0';
signal int_gie : STD_LOGIC := '0';
signal int_ier : UNSIGNED(1 downto 0) := (others => '0');
signal int_isr : UNSIGNED(1 downto 0) := (others => '0');
signal int_a : UNSIGNED(31 downto 0) := (others => '0');
signal int_b : UNSIGNED(31 downto 0) := (others => '0');
signal int_accum : UNSIGNED(31 downto 0) := (others => '0');
signal int_accum_ap_vld : STD_LOGIC;
signal int_accum_clr : UNSIGNED(0 downto 0) := (others => '0');
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wrreset;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdreset;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_A_DATA_0 =>
rdata_data <= RESIZE(int_a(31 downto 0), 32);
when ADDR_B_DATA_0 =>
rdata_data <= RESIZE(int_b(31 downto 0), 32);
when ADDR_ACCUM_DATA_0 =>
rdata_data <= RESIZE(int_accum(31 downto 0), 32);
when ADDR_ACCUM_CTRL =>
rdata_data <= (0 => int_accum_ap_vld, others => '0');
when ADDR_ACCUM_CLR_DATA_0 =>
rdata_data <= RESIZE(int_accum_clr(0 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
a <= STD_LOGIC_VECTOR(int_a);
b <= STD_LOGIC_VECTOR(int_b);
accum_clr <= STD_LOGIC_VECTOR(int_accum_clr);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_idle <= '0';
elsif (ACLK_EN = '1') then
if (true) then
int_ap_idle <= ap_idle;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_ready <= '0';
elsif (ACLK_EN = '1') then
if (true) then
int_ap_ready <= ap_ready;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_A_DATA_0) then
int_a(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_a(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_B_DATA_0) then
int_b(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_b(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_accum <= (others => '0');
elsif (ACLK_EN = '1') then
if (accum_ap_vld = '1') then
int_accum <= UNSIGNED(accum); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_accum_ap_vld <= '0';
elsif (ACLK_EN = '1') then
if (accum_ap_vld = '1') then
int_accum_ap_vld <= '1';
elsif (ar_hs = '1' and raddr = ADDR_ACCUM_CTRL) then
int_accum_ap_vld <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_ACCUM_CLR_DATA_0) then
int_accum_clr(0 downto 0) <= (UNSIGNED(WDATA(0 downto 0)) and wmask(0 downto 0)) or ((not wmask(0 downto 0)) and int_accum_clr(0 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity hls_macc_HLS_MACC_PERIPH_BUS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
a :out STD_LOGIC_VECTOR(31 downto 0);
b :out STD_LOGIC_VECTOR(31 downto 0);
accum :in STD_LOGIC_VECTOR(31 downto 0);
accum_ap_vld :in STD_LOGIC;
accum_clr :out STD_LOGIC_VECTOR(0 downto 0)
);
end entity hls_macc_HLS_MACC_PERIPH_BUS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of a
-- bit 31~0 - a[31:0] (Read/Write)
-- 0x14 : reserved
-- 0x18 : Data signal of b
-- bit 31~0 - b[31:0] (Read/Write)
-- 0x1c : reserved
-- 0x20 : Data signal of accum
-- bit 31~0 - accum[31:0] (Read)
-- 0x24 : Control signal of accum
-- bit 0 - accum_ap_vld (Read/COR)
-- others - reserved
-- 0x28 : Data signal of accum_clr
-- bit 0 - accum_clr[0] (Read/Write)
-- others - reserved
-- 0x2c : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of hls_macc_HLS_MACC_PERIPH_BUS_s_axi is
type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states
signal wstate : states := wrreset;
signal rstate : states := rdreset;
signal wnext, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_A_DATA_0 : INTEGER := 16#10#;
constant ADDR_A_CTRL : INTEGER := 16#14#;
constant ADDR_B_DATA_0 : INTEGER := 16#18#;
constant ADDR_B_CTRL : INTEGER := 16#1c#;
constant ADDR_ACCUM_DATA_0 : INTEGER := 16#20#;
constant ADDR_ACCUM_CTRL : INTEGER := 16#24#;
constant ADDR_ACCUM_CLR_DATA_0 : INTEGER := 16#28#;
constant ADDR_ACCUM_CLR_CTRL : INTEGER := 16#2c#;
constant ADDR_BITS : INTEGER := 6;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC := '0';
signal int_ap_start : STD_LOGIC := '0';
signal int_auto_restart : STD_LOGIC := '0';
signal int_gie : STD_LOGIC := '0';
signal int_ier : UNSIGNED(1 downto 0) := (others => '0');
signal int_isr : UNSIGNED(1 downto 0) := (others => '0');
signal int_a : UNSIGNED(31 downto 0) := (others => '0');
signal int_b : UNSIGNED(31 downto 0) := (others => '0');
signal int_accum : UNSIGNED(31 downto 0) := (others => '0');
signal int_accum_ap_vld : STD_LOGIC;
signal int_accum_clr : UNSIGNED(0 downto 0) := (others => '0');
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wrreset;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdreset;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_A_DATA_0 =>
rdata_data <= RESIZE(int_a(31 downto 0), 32);
when ADDR_B_DATA_0 =>
rdata_data <= RESIZE(int_b(31 downto 0), 32);
when ADDR_ACCUM_DATA_0 =>
rdata_data <= RESIZE(int_accum(31 downto 0), 32);
when ADDR_ACCUM_CTRL =>
rdata_data <= (0 => int_accum_ap_vld, others => '0');
when ADDR_ACCUM_CLR_DATA_0 =>
rdata_data <= RESIZE(int_accum_clr(0 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
a <= STD_LOGIC_VECTOR(int_a);
b <= STD_LOGIC_VECTOR(int_b);
accum_clr <= STD_LOGIC_VECTOR(int_accum_clr);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_idle <= '0';
elsif (ACLK_EN = '1') then
if (true) then
int_ap_idle <= ap_idle;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_ready <= '0';
elsif (ACLK_EN = '1') then
if (true) then
int_ap_ready <= ap_ready;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_A_DATA_0) then
int_a(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_a(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_B_DATA_0) then
int_b(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_b(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_accum <= (others => '0');
elsif (ACLK_EN = '1') then
if (accum_ap_vld = '1') then
int_accum <= UNSIGNED(accum); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_accum_ap_vld <= '0';
elsif (ACLK_EN = '1') then
if (accum_ap_vld = '1') then
int_accum_ap_vld <= '1';
elsif (ar_hs = '1' and raddr = ADDR_ACCUM_CTRL) then
int_accum_ap_vld <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_ACCUM_CLR_DATA_0) then
int_accum_clr(0 downto 0) <= (UNSIGNED(WDATA(0 downto 0)) and wmask(0 downto 0)) or ((not wmask(0 downto 0)) and int_accum_clr(0 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity hls_macc_HLS_MACC_PERIPH_BUS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
a :out STD_LOGIC_VECTOR(31 downto 0);
b :out STD_LOGIC_VECTOR(31 downto 0);
accum :in STD_LOGIC_VECTOR(31 downto 0);
accum_ap_vld :in STD_LOGIC;
accum_clr :out STD_LOGIC_VECTOR(0 downto 0)
);
end entity hls_macc_HLS_MACC_PERIPH_BUS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of a
-- bit 31~0 - a[31:0] (Read/Write)
-- 0x14 : reserved
-- 0x18 : Data signal of b
-- bit 31~0 - b[31:0] (Read/Write)
-- 0x1c : reserved
-- 0x20 : Data signal of accum
-- bit 31~0 - accum[31:0] (Read)
-- 0x24 : Control signal of accum
-- bit 0 - accum_ap_vld (Read/COR)
-- others - reserved
-- 0x28 : Data signal of accum_clr
-- bit 0 - accum_clr[0] (Read/Write)
-- others - reserved
-- 0x2c : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of hls_macc_HLS_MACC_PERIPH_BUS_s_axi is
type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states
signal wstate : states := wrreset;
signal rstate : states := rdreset;
signal wnext, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_A_DATA_0 : INTEGER := 16#10#;
constant ADDR_A_CTRL : INTEGER := 16#14#;
constant ADDR_B_DATA_0 : INTEGER := 16#18#;
constant ADDR_B_CTRL : INTEGER := 16#1c#;
constant ADDR_ACCUM_DATA_0 : INTEGER := 16#20#;
constant ADDR_ACCUM_CTRL : INTEGER := 16#24#;
constant ADDR_ACCUM_CLR_DATA_0 : INTEGER := 16#28#;
constant ADDR_ACCUM_CLR_CTRL : INTEGER := 16#2c#;
constant ADDR_BITS : INTEGER := 6;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC := '0';
signal int_ap_start : STD_LOGIC := '0';
signal int_auto_restart : STD_LOGIC := '0';
signal int_gie : STD_LOGIC := '0';
signal int_ier : UNSIGNED(1 downto 0) := (others => '0');
signal int_isr : UNSIGNED(1 downto 0) := (others => '0');
signal int_a : UNSIGNED(31 downto 0) := (others => '0');
signal int_b : UNSIGNED(31 downto 0) := (others => '0');
signal int_accum : UNSIGNED(31 downto 0) := (others => '0');
signal int_accum_ap_vld : STD_LOGIC;
signal int_accum_clr : UNSIGNED(0 downto 0) := (others => '0');
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wrreset;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdreset;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_A_DATA_0 =>
rdata_data <= RESIZE(int_a(31 downto 0), 32);
when ADDR_B_DATA_0 =>
rdata_data <= RESIZE(int_b(31 downto 0), 32);
when ADDR_ACCUM_DATA_0 =>
rdata_data <= RESIZE(int_accum(31 downto 0), 32);
when ADDR_ACCUM_CTRL =>
rdata_data <= (0 => int_accum_ap_vld, others => '0');
when ADDR_ACCUM_CLR_DATA_0 =>
rdata_data <= RESIZE(int_accum_clr(0 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
a <= STD_LOGIC_VECTOR(int_a);
b <= STD_LOGIC_VECTOR(int_b);
accum_clr <= STD_LOGIC_VECTOR(int_accum_clr);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_idle <= '0';
elsif (ACLK_EN = '1') then
if (true) then
int_ap_idle <= ap_idle;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_ready <= '0';
elsif (ACLK_EN = '1') then
if (true) then
int_ap_ready <= ap_ready;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_A_DATA_0) then
int_a(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_a(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_B_DATA_0) then
int_b(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_b(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_accum <= (others => '0');
elsif (ACLK_EN = '1') then
if (accum_ap_vld = '1') then
int_accum <= UNSIGNED(accum); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_accum_ap_vld <= '0';
elsif (ACLK_EN = '1') then
if (accum_ap_vld = '1') then
int_accum_ap_vld <= '1';
elsif (ar_hs = '1' and raddr = ADDR_ACCUM_CTRL) then
int_accum_ap_vld <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_ACCUM_CLR_DATA_0) then
int_accum_clr(0 downto 0) <= (UNSIGNED(WDATA(0 downto 0)) and wmask(0 downto 0)) or ((not wmask(0 downto 0)) and int_accum_clr(0 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
--
-- VoiceRom.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity VoiceRom is
port (
clk : in std_logic;
addr : in VOICE_ID_TYPE;
data : out VOICE_TYPE
);
end VoiceRom;
architecture RTL of VoiceRom is
type VOICE_ARRAY_TYPE is array (VOICE_ID_TYPE'range) of VOICE_VECTOR_TYPE;
constant voices : VOICE_ARRAY_TYPE := (
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"000000000000000000000000000000000000", -- @0(M)
"000000000000000000000000000000000000", -- @0(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"011000010001111001111111000000000000", -- @1(M)
"011000010000000010000111111100010111", -- @1(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"000100110001011111101111111100100011", -- @2(M)
"010000010000000000001111111100010011", -- @2(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"001000111001101001001010001111110000", -- @3(M)
"000000010000000000001111010000100011", -- @3(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"000100010000111001111111101001110000", -- @4(M)
"011000010000000000000110010000010111", -- @4(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"001000100001111001101111000000000000", -- @5(M)
"001000010000000000000111011000101000", -- @5(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"001000010001011001011111000000000000", -- @6(M)
"001000100000000000000111000100011000", -- @6(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"001000010001110101111000001000010000", -- @7(M)
"011000010000000000001000000000000111", -- @7(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"001000110010110101101001000000000000", -- @8(M)
"001000010000000010001001000000000111", -- @8(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"001000010001101101100110010000010000", -- @9(M)
"001000010000000000000110010100010111", -- @9(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"001000010000101110101000010101110000", -- @10(M)
"001000010000000010001010000000000111", -- @10(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"001000111000001100001111111100010000", -- @11(M)
"000000010000000010001011000000000100", -- @11(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"100101110010000001111111111100100010", -- @12(M)
"110000010000000000001111111100010010", -- @12(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"011000010000110001011101001001000000", -- @13(M)
"000000000000000000001111011001000011", -- @13(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"000000010101011000111111010000000011", -- @14(M)
"000000010000000000001111000000000010", -- @14(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"001000011000100100111111000111110000", -- @15(M)
"010000010000000000001111010000100011", -- @15(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"000001110001011000001101111111111111", -- BD(M)
"001000010000000000001111100011111000", -- BD(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"001100010000000000001111011111110111", -- HH
"001100100000000000001111011111110111", -- SD
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"001001010000000000001111100011111000", -- TOM
"000000010000000000001101110001010101" -- CYM
);
begin
process (clk)
begin
if clk'event and clk = '1' then
data <= CONV_VOICE(voices(addr));
end if;
end process;
end RTL; |
--
-- VoiceRom.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity VoiceRom is
port (
clk : in std_logic;
addr : in VOICE_ID_TYPE;
data : out VOICE_TYPE
);
end VoiceRom;
architecture RTL of VoiceRom is
type VOICE_ARRAY_TYPE is array (VOICE_ID_TYPE'range) of VOICE_VECTOR_TYPE;
constant voices : VOICE_ARRAY_TYPE := (
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"000000000000000000000000000000000000", -- @0(M)
"000000000000000000000000000000000000", -- @0(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"011000010001111001111111000000000000", -- @1(M)
"011000010000000010000111111100010111", -- @1(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"000100110001011111101111111100100011", -- @2(M)
"010000010000000000001111111100010011", -- @2(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"001000111001101001001010001111110000", -- @3(M)
"000000010000000000001111010000100011", -- @3(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"000100010000111001111111101001110000", -- @4(M)
"011000010000000000000110010000010111", -- @4(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"001000100001111001101111000000000000", -- @5(M)
"001000010000000000000111011000101000", -- @5(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"001000010001011001011111000000000000", -- @6(M)
"001000100000000000000111000100011000", -- @6(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"001000010001110101111000001000010000", -- @7(M)
"011000010000000000001000000000000111", -- @7(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"001000110010110101101001000000000000", -- @8(M)
"001000010000000010001001000000000111", -- @8(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"001000010001101101100110010000010000", -- @9(M)
"001000010000000000000110010100010111", -- @9(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"001000010000101110101000010101110000", -- @10(M)
"001000010000000010001010000000000111", -- @10(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"001000111000001100001111111100010000", -- @11(M)
"000000010000000010001011000000000100", -- @11(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"100101110010000001111111111100100010", -- @12(M)
"110000010000000000001111111100010010", -- @12(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"011000010000110001011101001001000000", -- @13(M)
"000000000000000000001111011001000011", -- @13(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"000000010101011000111111010000000011", -- @14(M)
"000000010000000000001111000000000010", -- @14(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"001000011000100100111111000111110000", -- @15(M)
"010000010000000000001111010000100011", -- @15(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"000001110001011000001101111111111111", -- BD(M)
"001000010000000000001111100011111000", -- BD(C)
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"001100010000000000001111011111110111", -- HH
"001100100000000000001111011111110111", -- SD
-- APEK<ML>KL< TL >W<F><AR><DR><SL><RR>
"001001010000000000001111100011111000", -- TOM
"000000010000000000001101110001010101" -- CYM
);
begin
process (clk)
begin
if clk'event and clk = '1' then
data <= CONV_VOICE(voices(addr));
end if;
end process;
end RTL; |
-- NEED RESULT: ARCH00098.P1: Multi transport transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00098.P2: Multi transport transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00098.P3: Multi transport transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00098: One transport transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00098: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00098: One transport transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00098: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00098: One transport transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00098: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00098
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00098(ARCH00098)
-- ENT00098_Test_Bench(ARCH00098_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00098 is
port (
s_st_arr1_vector : inout st_arr1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
end ENT00098 ;
--
architecture ARCH00098 of ENT00098 is
begin
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_arr1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_arr1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0 =>
s_st_arr1_vector(lowb) (
st_arr1'Left) <= transport
c_st_arr1_vector_2(highb) (
st_arr1'Right) after 10 ns,
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_2(highb) (
st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_1(highb) (
st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00098.P1" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (
st_arr1'Left) <= transport
c_st_arr1_vector_2(highb) (
st_arr1'Right) after 10 ns,
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 20 ns,
c_st_arr1_vector_2(highb) (
st_arr1'Right) after 30 ns,
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_2(highb) (
st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector(lowb) (
st_arr1'Left) <= transport
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_1(highb) (
st_arr1'Right) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00098" ,
"One transport transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00098" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00098" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_arr2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_arr2_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0 =>
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00098.P2" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns,
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 30 ns,
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00098" ,
"One transport transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00098" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00098" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_arr3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_arr3_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0 =>
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00098.P3" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns,
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 30 ns,
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00098" ,
"One transport transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00098" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00098" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P3 ;
--
--
end ARCH00098 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00098_Test_Bench is
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
end ENT00098_Test_Bench ;
--
architecture ARCH00098_Test_Bench of ENT00098_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_arr1_vector : inout st_arr1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00098 ( ARCH00098 ) ;
begin
CIS1 : UUT
port map (
s_st_arr1_vector
, s_st_arr2_vector
, s_st_arr3_vector
) ;
end block L1 ;
end ARCH00098_Test_Bench ;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Entity: serializer
-- File: serializer.vhd
-- Author: Jan Andersson - Gaisler Research AB
-- [email protected]
--
-- Description: Takes in three vectors and serializes them into one
-- output vector. Intended to be used to serialize
-- RGB VGA data.
--
library ieee;
use ieee.std_logic_1164.all;
entity serializer is
generic (
length : integer := 8 -- vector length
);
port (
clk : in std_ulogic;
sync : in std_ulogic;
ivec0 : in std_logic_vector((length-1) downto 0);
ivec1 : in std_logic_vector((length-1) downto 0);
ivec2 : in std_logic_vector((length-1) downto 0);
ovec : out std_logic_vector((length-1) downto 0)
);
end entity serializer;
architecture rtl of serializer is
type state_type is (vec0, vec1, vec2);
type sreg_type is record
state : state_type;
sync : std_logic_vector(1 downto 0);
end record;
signal r, rin : sreg_type;
begin -- rtl
comb: process (r, clk, sync, ivec0, ivec1, ivec2)
variable v : sreg_type;
begin -- process comb
v := r;
v.sync := r.sync(0) & sync;
case r.state is
when vec0 =>
ovec <= ivec0;
v.state := vec1;
when vec1 =>
ovec <= ivec1;
v.state := vec2;
when vec2 =>
ovec <= ivec2;
v.state := vec0;
end case;
if (r.sync(0) xor sync) = '1' then
v.state := vec1;
end if;
rin <= v;
end process comb;
reg: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process reg;
end rtl;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/RADIX22FFT_SDNF1_1_block5.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_1_block5
-- Source Path: ifft_16_bit/IFFT HDL Optimized/RADIX22FFT_SDNF1_1
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_1_block5 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
twdlXdin_7_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_7_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_15_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_15_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_13_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_13_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_14_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_14_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_13_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_1_block5;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_1_block5 IS
-- Signals
SIGNAL twdlXdin_7_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_7_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_15_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_15_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_13_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_13_im_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_14_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_14_im_tmp : signed(16 DOWNTO 0); -- sfix17
BEGIN
twdlXdin_7_re_signed <= signed(twdlXdin_7_re);
twdlXdin_7_im_signed <= signed(twdlXdin_7_im);
twdlXdin_15_re_signed <= signed(twdlXdin_15_re);
twdlXdin_15_im_signed <= signed(twdlXdin_15_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_7_re_signed,
twdlXdin_7_im_signed, twdlXdin_15_re_signed, twdlXdin_15_im_signed,
twdlXdin_1_vld)
VARIABLE sra_temp : signed(17 DOWNTO 0);
VARIABLE sra_temp_0 : signed(17 DOWNTO 0);
VARIABLE sra_temp_1 : signed(17 DOWNTO 0);
VARIABLE sra_temp_2 : signed(17 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg_next <= resize(twdlXdin_7_re_signed, 18) + resize(twdlXdin_15_re_signed, 18);
Radix22ButterflyG1_NF_btf2_re_reg_next <= resize(twdlXdin_7_re_signed, 18) - resize(twdlXdin_15_re_signed, 18);
Radix22ButterflyG1_NF_btf1_im_reg_next <= resize(twdlXdin_7_im_signed, 18) + resize(twdlXdin_15_im_signed, 18);
Radix22ButterflyG1_NF_btf2_im_reg_next <= resize(twdlXdin_7_im_signed, 18) - resize(twdlXdin_15_im_signed, 18);
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_re_reg, 1);
dout_13_re_tmp <= sra_temp(16 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_im_reg, 1);
dout_13_im_tmp <= sra_temp_0(16 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_re_reg, 1);
dout_14_re_tmp <= sra_temp_1(16 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_im_reg, 1);
dout_14_im_tmp <= sra_temp_2(16 DOWNTO 0);
dout_13_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_13_re <= std_logic_vector(dout_13_re_tmp);
dout_13_im <= std_logic_vector(dout_13_im_tmp);
dout_14_re <= std_logic_vector(dout_14_re_tmp);
dout_14_im <= std_logic_vector(dout_14_im_tmp);
END rtl;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 08/12/2014
--! Module Name: reg8to16bit
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library work, IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
--! width matching register 8 bit to 16 bit
entity reg8to16bit is
Port (
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
flush : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
din_rdy : IN STD_LOGIC;
-----
flushed : OUT STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
dout_rdy : OUT STD_LOGIC
);
end reg8to16bit;
architecture Behavioral of reg8to16bit is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
----
signal dout16bit_s1, dout16bit_s2 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal count, ce, count_1CLK_pulse_valid, flush_s, count_rst, flashed_delayed, count_trig : STD_LOGIC := '0';
signal count_1CLK_pulse_s : STD_LOGIC;
----
begin
-----
--
process(clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
ce <= '1';
end if;
end if;
end process;
---
-----
flush_s <= flush and (not count); -- when count is '0', flush the register
--
process(clk)
begin
if clk'event and clk = '1' then
flushed <= flush_s;
end if;
end process;
---
process(flush_s, clk)
begin
if flush_s = '1' then
flashed_delayed <= '1';
elsif clk'event and clk = '1' then
flashed_delayed <= flush_s;
end if;
end process;
---
--
process(clk)
begin
if clk'event and clk = '1' then
if din_rdy = '1' then
dout16bit_s1 <= din;
dout16bit_s2 <= dout16bit_s1;
end if;
end if;
end process;
---
process(flashed_delayed, dout16bit_s1, dout16bit_s2)
begin
if flashed_delayed = '1' then
dout <= "00000000" & dout16bit_s1;
else
dout <= dout16bit_s1 & dout16bit_s2;
end if;
end process;
---
---
count_rst <= rst; -- or flush_s;
---
process(count_rst, clk)
begin
if count_rst = '1' then
count <= '1';
elsif clk'event and clk = '1' then
if flush_s = '1' then
count <= '1';
elsif din_rdy = '1' then
count <= not count;
end if;
end if;
end process;
---
count_trig <= count;-- and (not flashed_delayed) and (not rst) and ce;
count_1CLK_pulse: pulse_pdxx_pwxx PORT MAP(clk, count_trig, count_1CLK_pulse_s);
--count_1CLK_pulse_valid <= count_1CLK_pulse_s and (not flashed_delayed) and (not rst) and ce;
count_1CLK_pulse_valid <= count_1CLK_pulse_s and (not rst) and ce; --and (not flashed_delayed)
---
dout_rdy <= count_1CLK_pulse_valid; -- or flush_s;
---
end Behavioral;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 08/12/2014
--! Module Name: reg8to16bit
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library work, IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
--! width matching register 8 bit to 16 bit
entity reg8to16bit is
Port (
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
flush : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
din_rdy : IN STD_LOGIC;
-----
flushed : OUT STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
dout_rdy : OUT STD_LOGIC
);
end reg8to16bit;
architecture Behavioral of reg8to16bit is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
----
signal dout16bit_s1, dout16bit_s2 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal count, ce, count_1CLK_pulse_valid, flush_s, count_rst, flashed_delayed, count_trig : STD_LOGIC := '0';
signal count_1CLK_pulse_s : STD_LOGIC;
----
begin
-----
--
process(clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
ce <= '1';
end if;
end if;
end process;
---
-----
flush_s <= flush and (not count); -- when count is '0', flush the register
--
process(clk)
begin
if clk'event and clk = '1' then
flushed <= flush_s;
end if;
end process;
---
process(flush_s, clk)
begin
if flush_s = '1' then
flashed_delayed <= '1';
elsif clk'event and clk = '1' then
flashed_delayed <= flush_s;
end if;
end process;
---
--
process(clk)
begin
if clk'event and clk = '1' then
if din_rdy = '1' then
dout16bit_s1 <= din;
dout16bit_s2 <= dout16bit_s1;
end if;
end if;
end process;
---
process(flashed_delayed, dout16bit_s1, dout16bit_s2)
begin
if flashed_delayed = '1' then
dout <= "00000000" & dout16bit_s1;
else
dout <= dout16bit_s1 & dout16bit_s2;
end if;
end process;
---
---
count_rst <= rst; -- or flush_s;
---
process(count_rst, clk)
begin
if count_rst = '1' then
count <= '1';
elsif clk'event and clk = '1' then
if flush_s = '1' then
count <= '1';
elsif din_rdy = '1' then
count <= not count;
end if;
end if;
end process;
---
count_trig <= count;-- and (not flashed_delayed) and (not rst) and ce;
count_1CLK_pulse: pulse_pdxx_pwxx PORT MAP(clk, count_trig, count_1CLK_pulse_s);
--count_1CLK_pulse_valid <= count_1CLK_pulse_s and (not flashed_delayed) and (not rst) and ce;
count_1CLK_pulse_valid <= count_1CLK_pulse_s and (not rst) and ce; --and (not flashed_delayed)
---
dout_rdy <= count_1CLK_pulse_valid; -- or flush_s;
---
end Behavioral;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 08/12/2014
--! Module Name: reg8to16bit
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library work, IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
--! width matching register 8 bit to 16 bit
entity reg8to16bit is
Port (
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
flush : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
din_rdy : IN STD_LOGIC;
-----
flushed : OUT STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
dout_rdy : OUT STD_LOGIC
);
end reg8to16bit;
architecture Behavioral of reg8to16bit is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
----
signal dout16bit_s1, dout16bit_s2 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal count, ce, count_1CLK_pulse_valid, flush_s, count_rst, flashed_delayed, count_trig : STD_LOGIC := '0';
signal count_1CLK_pulse_s : STD_LOGIC;
----
begin
-----
--
process(clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
ce <= '1';
end if;
end if;
end process;
---
-----
flush_s <= flush and (not count); -- when count is '0', flush the register
--
process(clk)
begin
if clk'event and clk = '1' then
flushed <= flush_s;
end if;
end process;
---
process(flush_s, clk)
begin
if flush_s = '1' then
flashed_delayed <= '1';
elsif clk'event and clk = '1' then
flashed_delayed <= flush_s;
end if;
end process;
---
--
process(clk)
begin
if clk'event and clk = '1' then
if din_rdy = '1' then
dout16bit_s1 <= din;
dout16bit_s2 <= dout16bit_s1;
end if;
end if;
end process;
---
process(flashed_delayed, dout16bit_s1, dout16bit_s2)
begin
if flashed_delayed = '1' then
dout <= "00000000" & dout16bit_s1;
else
dout <= dout16bit_s1 & dout16bit_s2;
end if;
end process;
---
---
count_rst <= rst; -- or flush_s;
---
process(count_rst, clk)
begin
if count_rst = '1' then
count <= '1';
elsif clk'event and clk = '1' then
if flush_s = '1' then
count <= '1';
elsif din_rdy = '1' then
count <= not count;
end if;
end if;
end process;
---
count_trig <= count;-- and (not flashed_delayed) and (not rst) and ce;
count_1CLK_pulse: pulse_pdxx_pwxx PORT MAP(clk, count_trig, count_1CLK_pulse_s);
--count_1CLK_pulse_valid <= count_1CLK_pulse_s and (not flashed_delayed) and (not rst) and ce;
count_1CLK_pulse_valid <= count_1CLK_pulse_s and (not rst) and ce; --and (not flashed_delayed)
---
dout_rdy <= count_1CLK_pulse_valid; -- or flush_s;
---
end Behavioral;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 08/12/2014
--! Module Name: reg8to16bit
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library work, IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
--! width matching register 8 bit to 16 bit
entity reg8to16bit is
Port (
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
flush : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
din_rdy : IN STD_LOGIC;
-----
flushed : OUT STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
dout_rdy : OUT STD_LOGIC
);
end reg8to16bit;
architecture Behavioral of reg8to16bit is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
----
signal dout16bit_s1, dout16bit_s2 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal count, ce, count_1CLK_pulse_valid, flush_s, count_rst, flashed_delayed, count_trig : STD_LOGIC := '0';
signal count_1CLK_pulse_s : STD_LOGIC;
----
begin
-----
--
process(clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
ce <= '1';
end if;
end if;
end process;
---
-----
flush_s <= flush and (not count); -- when count is '0', flush the register
--
process(clk)
begin
if clk'event and clk = '1' then
flushed <= flush_s;
end if;
end process;
---
process(flush_s, clk)
begin
if flush_s = '1' then
flashed_delayed <= '1';
elsif clk'event and clk = '1' then
flashed_delayed <= flush_s;
end if;
end process;
---
--
process(clk)
begin
if clk'event and clk = '1' then
if din_rdy = '1' then
dout16bit_s1 <= din;
dout16bit_s2 <= dout16bit_s1;
end if;
end if;
end process;
---
process(flashed_delayed, dout16bit_s1, dout16bit_s2)
begin
if flashed_delayed = '1' then
dout <= "00000000" & dout16bit_s1;
else
dout <= dout16bit_s1 & dout16bit_s2;
end if;
end process;
---
---
count_rst <= rst; -- or flush_s;
---
process(count_rst, clk)
begin
if count_rst = '1' then
count <= '1';
elsif clk'event and clk = '1' then
if flush_s = '1' then
count <= '1';
elsif din_rdy = '1' then
count <= not count;
end if;
end if;
end process;
---
count_trig <= count;-- and (not flashed_delayed) and (not rst) and ce;
count_1CLK_pulse: pulse_pdxx_pwxx PORT MAP(clk, count_trig, count_1CLK_pulse_s);
--count_1CLK_pulse_valid <= count_1CLK_pulse_s and (not flashed_delayed) and (not rst) and ce;
count_1CLK_pulse_valid <= count_1CLK_pulse_s and (not rst) and ce; --and (not flashed_delayed)
---
dout_rdy <= count_1CLK_pulse_valid; -- or flush_s;
---
end Behavioral;
|
library verilog;
use verilog.vl_types.all;
entity alt_cal_mm is
generic(
number_of_channels: integer := 1;
channel_address_width: integer := 1;
sim_model_mode : string := "TRUE";
lpm_type : string := "alt_cal_mm";
lpm_hint : string := "UNUSED";
idle : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi0, Hi0, Hi0);
ch_wait : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi0, Hi0, Hi1);
testbus_set : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi0, Hi1, Hi0);
offsets_pden_rd : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi0, Hi1, Hi1);
offsets_pden_wr : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi1, Hi0, Hi0);
cal_pd_wr : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi1, Hi0, Hi1);
cal_rx_rd : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi1, Hi1, Hi0);
cal_rx_wr : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi1, Hi1, Hi1);
dprio_wait : vl_logic_vector(0 to 4) := (Hi0, Hi1, Hi0, Hi0, Hi0);
sample_tb : vl_logic_vector(0 to 4) := (Hi0, Hi1, Hi0, Hi0, Hi1);
test_input : vl_logic_vector(0 to 4) := (Hi0, Hi1, Hi0, Hi1, Hi0);
ch_adv : vl_logic_vector(0 to 4) := (Hi0, Hi1, Hi1, Hi0, Hi0);
dprio_read : vl_logic_vector(0 to 4) := (Hi0, Hi1, Hi1, Hi1, Hi0);
dprio_write : vl_logic_vector(0 to 4) := (Hi0, Hi1, Hi1, Hi1, Hi1);
kick_start_rd : vl_logic_vector(0 to 4) := (Hi0, Hi1, Hi1, Hi0, Hi1);
kick_start_wr : vl_logic_vector(0 to 4) := (Hi1, Hi0, Hi0, Hi0, Hi0);
kick_pause : vl_logic_vector(0 to 4) := (Hi1, Hi0, Hi0, Hi0, Hi1);
kick_delay_oc : vl_logic_vector(0 to 4) := (Hi1, Hi0, Hi0, Hi1, Hi0);
sample_length : vl_logic_vector(0 to 7) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0)
);
port(
busy : out vl_logic;
cal_error : out vl_logic_vector;
clock : in vl_logic;
dprio_addr : out vl_logic_vector(15 downto 0);
dprio_busy : in vl_logic;
dprio_datain : in vl_logic_vector(15 downto 0);
dprio_dataout : out vl_logic_vector(15 downto 0);
dprio_rden : out vl_logic;
dprio_wren : out vl_logic;
quad_addr : out vl_logic_vector(8 downto 0);
remap_addr : in vl_logic_vector(11 downto 0);
reset : in vl_logic;
retain_addr : out vl_logic_vector(0 downto 0);
start : in vl_logic;
transceiver_init: in vl_logic;
testbuses : in vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of number_of_channels : constant is 1;
attribute mti_svvh_generic_type of channel_address_width : constant is 1;
attribute mti_svvh_generic_type of sim_model_mode : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of idle : constant is 1;
attribute mti_svvh_generic_type of ch_wait : constant is 1;
attribute mti_svvh_generic_type of testbus_set : constant is 1;
attribute mti_svvh_generic_type of offsets_pden_rd : constant is 1;
attribute mti_svvh_generic_type of offsets_pden_wr : constant is 1;
attribute mti_svvh_generic_type of cal_pd_wr : constant is 1;
attribute mti_svvh_generic_type of cal_rx_rd : constant is 1;
attribute mti_svvh_generic_type of cal_rx_wr : constant is 1;
attribute mti_svvh_generic_type of dprio_wait : constant is 1;
attribute mti_svvh_generic_type of sample_tb : constant is 1;
attribute mti_svvh_generic_type of test_input : constant is 1;
attribute mti_svvh_generic_type of ch_adv : constant is 1;
attribute mti_svvh_generic_type of dprio_read : constant is 1;
attribute mti_svvh_generic_type of dprio_write : constant is 1;
attribute mti_svvh_generic_type of kick_start_rd : constant is 1;
attribute mti_svvh_generic_type of kick_start_wr : constant is 1;
attribute mti_svvh_generic_type of kick_pause : constant is 1;
attribute mti_svvh_generic_type of kick_delay_oc : constant is 1;
attribute mti_svvh_generic_type of sample_length : constant is 1;
end alt_cal_mm;
|
--------------------------------------------------------------------------------
--
-- FileName: i2c_master.vhd
-- Dependencies: none
-- Design Software: Quartus II 64-bit Version 13.1 Build 162 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 11/1/2012 Scott Larson
-- Initial Public Release
-- Version 2.0 06/20/2014 Scott Larson
-- Added ability to interface with different slaves in the same transaction
-- Corrected ack_error bug where ack_error went 'Z' instead of '1' on error
-- Corrected timing of when ack_error signal clears
-- Version 2.1 10/21/2014 Scott Larson
-- Replaced gated clock with clock enable
-- Adjusted timing of SCL during start and stop conditions
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY i2c_master IS
GENERIC(
input_clk : INTEGER := 100_000_000; --input clock speed from user logic in Hz
bus_clk : INTEGER := 100_000); --speed the i2c bus (scl) will run at in Hz
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --active low reset
ena : IN STD_LOGIC; --latch in command
addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
rw : IN STD_LOGIC; --'0' is write, '1' is read
data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
busy : OUT STD_LOGIC; --indicates transaction in progress
data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
sda : INOUT STD_LOGIC; --serial data output of i2c bus
scl : INOUT STD_LOGIC);
END i2c_master;
ARCHITECTURE logic OF i2c_master IS
CONSTANT divider : INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl
TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states
SIGNAL state : machine; --state machine
SIGNAL data_clk : STD_LOGIC; --data clock for sda
SIGNAL data_clk_prev : STD_LOGIC; --data clock during previous system clock
SIGNAL data_clk_m : STD_LOGIC; --data clock during previous system clock
SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl
SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output
SIGNAL sda_int : STD_LOGIC := '1'; --internal sda
SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output
SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write
SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave
SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave
SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction
SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl
BEGIN
--generate the timing for the bus clock (scl_clk) and the data clock (data_clk)
PROCESS(clk, reset_n)
VARIABLE count : INTEGER RANGE 0 TO divider*4; --timing for clock generation
BEGIN
IF(reset_n = '0') THEN --reset asserted
stretch <= '0';
count := 0;
ELSIF(clk'EVENT AND clk = '1') THEN
data_clk_prev <= data_clk; --store previous value of data clock
IF(count = 999) THEN --end of timing cycle
count := 0; --reset timer
ELSIF(stretch = '0') THEN --clock stretching from slave not detected
count := count + 1; --continue clock generation timing
END IF;
CASE count IS
WHEN 0 TO 249 => --first 1/4 cycle of clocking
scl_clk <= '0';
data_clk <= '0';
WHEN 250 TO 499 => --second 1/4 cycle of clocking
scl_clk <= '0';
data_clk <= '1';
WHEN 500 TO 749 => --third 1/4 cycle of clocking
scl_clk <= '1'; --release scl
IF(scl = '0') THEN --detect if slave is stretching clock
stretch <= '1';
ELSE
stretch <= '0';
END IF;
data_clk <= '1';
WHEN OTHERS => --last 1/4 cycle of clocking
scl_clk <= '1';
data_clk <= '0';
END CASE;
END IF;
END PROCESS;
--state machine and writing to sda during scl low (data_clk rising edge)
PROCESS(clk, reset_n)
BEGIN
IF(reset_n = '0') THEN --reset asserted
state <= ready; --return to initial state
busy <= '1'; --indicate not available
scl_ena <= '0'; --sets scl high impedance
sda_int <= '1'; --sets sda high impedance
ack_error <= '0'; --clear acknowledge error flag
bit_cnt <= 7; --restarts data bit counter
data_rd <= "00000000"; --clear data read port
ELSIF(clk'EVENT AND clk = '1') THEN
IF(data_clk = '1' AND data_clk_prev = '0') THEN --data clock rising edge
CASE state IS
WHEN ready => --idle state
IF(ena = '1') THEN --transaction requested
busy <= '1'; --flag busy
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
state <= start; --go to start bit
ELSE --remain idle
busy <= '0'; --unflag busy
state <= ready; --remain idle
END IF;
WHEN start => --start bit of transaction
busy <= '1'; --resume busy if continuous mode
sda_int <= addr_rw(bit_cnt); --set first address bit to bus
state <= command; --go to command
WHEN command => --address and command byte of transaction
IF(bit_cnt = 0) THEN --command transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack1; --go to slave acknowledge (command)
ELSE --next clock cycle of command state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus
state <= command; --continue with command
END IF;
WHEN slv_ack1 => --slave acknowledge bit (command)
IF(addr_rw(0) = '0') THEN --write command
sda_int <= data_tx(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --read command
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
END IF;
WHEN wr => --write byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --write byte transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
-- added the following line to make sure busy = 0 in the slv_ack2 state
busy <= '0'; --continue is accepted (modified by CU)
state <= slv_ack2; --go to slave acknowledge (write)
ELSE --next clock cycle of write state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= data_tx(bit_cnt-1); --write next bit to bus
state <= wr; --continue writing
END IF;
WHEN rd => --read byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --read byte receive finished
IF(ena = '1' AND addr_rw = addr & rw) THEN --continuing with another read at same address
sda_int <= '0'; --acknowledge the byte has been received
ELSE --stopping or continuing with a write
sda_int <= '1'; --send a no-acknowledge (before stop or repeated start)
END IF;
bit_cnt <= 7; --reset bit counter for "byte" states
-- added the following line to make sure busy = 0 in the mstr_ack state
busy <= '0'; --continue is accepted (modified by CU)
data_rd <= data_rx; --output received data
state <= mstr_ack; --go to master acknowledge
ELSE --next clock cycle of read state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
state <= rd; --continue reading
END IF;
WHEN slv_ack2 => --slave acknowledge bit (write)
IF(ena = '1') THEN --continue transaction
-- busy <= '0'; --continue is accepted (modified by CU)
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(addr_rw = addr & rw) THEN --continue transaction with another write
busy <= '1'; --resume busy in the wr state (modified by CU)
sda_int <= data_wr(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --continue transaction with a read or new slave
state <= start; --go to repeated start
END IF;
ELSE --complete transaction
busy <= '0'; --unflag busy (modified by CU)
sda_int <= '1'; --sets sda high impedance (modified by CU)
state <= stop; --go to stop bit
END IF;
WHEN mstr_ack => --master acknowledge bit after a read
IF(ena = '1') THEN --continue transaction
-- busy <= '0'; --continue is accepted (modified by CU)
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(addr_rw = addr & rw) THEN --continue transaction with another read
busy <= '1'; --resume busy in the wr state (modified by CU)
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
ELSE --continue transaction with a write or new slave
state <= start; --repeated start
END IF;
ELSE --complete transaction
busy <= '0'; --unflag busy (modified by CU)
sda_int <= '1'; --sets sda high impedance (modified by CU)
state <= stop; --go to stop bit
END IF;
WHEN stop => --stop bit of transaction
-- busy <= '0'; --unflag busy (modified by CU)
state <= ready; --go to idle state
END CASE;
ELSIF(data_clk = '0' AND data_clk_prev = '1') THEN --data clock falling edge
CASE state IS
WHEN start =>
IF(scl_ena = '0') THEN --starting new transaction
scl_ena <= '1'; --enable scl output
ack_error <= '0'; --reset acknowledge error output
END IF;
WHEN slv_ack1 => --receiving slave acknowledge (command)
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN rd => --receiving slave data
data_rx(bit_cnt) <= sda; --receive current slave data bit
WHEN slv_ack2 => --receiving slave acknowledge (write)
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN stop =>
scl_ena <= '0'; --disable scl
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
END PROCESS;
--set sda output
data_clk_m <= data_clk_prev and data_clk; -- Modification added at CU
WITH state SELECT
sda_ena_n <= data_clk WHEN start, --generate start condition
NOT data_clk_m WHEN stop, --generate stop condition (modification added at CU)
sda_int WHEN OTHERS; --set to internal sda signal
--set scl and sda outputs
scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z';
sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z';
-- Following two signals will be used for tristate obuft (did not work)
-- scl <= '1' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE '0';
-- sda <= '1' WHEN sda_ena_n = '0' ELSE '0';
END logic;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_eb_e
--
-- Generated
-- by: wig
-- on: Wed Jun 7 17:05:33 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_eb_e-e.vhd,v 1.2 2006/06/22 07:19:59 wig Exp $
-- $Date: 2006/06/22 07:19:59 $
-- $Log: inst_eb_e-e.vhd,v $
-- Revision 1.2 2006/06/22 07:19:59 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.45 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_eb_e
--
entity inst_eb_e is
-- Generics:
-- No Generated Generics for Entity inst_eb_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_eb_e
p_mix_tmi_sbist_fail_12_10_go : out std_ulogic_vector(2 downto 0);
p_mix_c_addr_12_0_gi : in std_ulogic_vector(12 downto 0);
p_mix_c_bus_in_31_0_gi : in std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity inst_eb_e
);
end inst_eb_e;
--
-- End of Generated Entity inst_eb_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
--!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! RIVER CPU specific library.
library riverlib;
--! RIVER CPU configuration constants.
use riverlib.river_cfg.all;
entity RiverTop is
generic (
memtech : integer := 0;
hartid : integer := 0;
async_reset : boolean := false;
fpu_ena : boolean := true;
coherence_ena : boolean := false;
tracer_ena : boolean := false
);
port (
i_clk : in std_logic; -- CPU clock
i_nrst : in std_logic; -- Reset. Active LOW.
-- Memory interface:
i_req_mem_ready : in std_logic; -- AXI request was accepted
o_req_mem_path : out std_logic; -- 0=ctrl; 1=data path
o_req_mem_valid : out std_logic; -- AXI memory request is valid
o_req_mem_type : out std_logic_vector(REQ_MEM_TYPE_BITS-1 downto 0);-- AXI memory request is write type
o_req_mem_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- AXI memory request address
o_req_mem_strob : out std_logic_vector(L1CACHE_BYTES_PER_LINE-1 downto 0);-- Writing strob. 1 bit per Byte
o_req_mem_data : out std_logic_vector(L1CACHE_LINE_BITS-1 downto 0); -- Writing data
i_resp_mem_valid : in std_logic; -- AXI response is valid
i_resp_mem_path : in std_logic; -- 0=ctrl; 1=data path
i_resp_mem_data : in std_logic_vector(L1CACHE_LINE_BITS-1 downto 0); -- Read data
i_resp_mem_load_fault : in std_logic; -- Bus response with SLVERR or DECERR on read
i_resp_mem_store_fault : in std_logic; -- Bus response with SLVERR or DECERR on write
-- Interrupt line from external interrupts controller (PLIC).
i_ext_irq : in std_logic;
-- D$ Snoop interface
i_req_snoop_valid : in std_logic;
i_req_snoop_type : in std_logic_vector(SNOOP_REQ_TYPE_BITS-1 downto 0);
o_req_snoop_ready : out std_logic;
i_req_snoop_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_resp_snoop_ready : in std_logic;
o_resp_snoop_valid : out std_logic;
o_resp_snoop_data : out std_logic_vector(L1CACHE_LINE_BITS-1 downto 0);
o_resp_snoop_flags : out std_logic_vector(DTAG_FL_TOTAL-1 downto 0);
-- Debug interface:
i_dport_req_valid : in std_logic; -- Debug access from DSU is valid
i_dport_write : in std_logic; -- Write command flag
i_dport_addr : in std_logic_vector(CFG_DPORT_ADDR_BITS-1 downto 0); -- Debug Port address
i_dport_wdata : in std_logic_vector(RISCV_ARCH-1 downto 0);-- Write value
o_dport_req_ready : out std_logic; -- Ready to accept dbg request
i_dport_resp_ready : in std_logic; -- Read to accept response
o_dport_resp_valid : out std_logic; -- Response is valid
o_dport_rdata : out std_logic_vector(RISCV_ARCH-1 downto 0);-- Response value
o_halted : out std_logic
);
end;
architecture arch_RiverTop of RiverTop is
-- Control path:
signal w_req_ctrl_ready : std_logic;
signal w_req_ctrl_valid : std_logic;
signal wb_req_ctrl_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
signal w_resp_ctrl_valid : std_logic;
signal wb_resp_ctrl_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
signal wb_resp_ctrl_data : std_logic_vector(31 downto 0);
signal w_resp_ctrl_load_fault : std_logic;
signal w_resp_ctrl_executable : std_logic;
signal w_resp_ctrl_ready : std_logic;
-- Data path:
signal w_req_data_ready : std_logic;
signal w_req_data_valid : std_logic;
signal w_req_data_write : std_logic;
signal wb_req_data_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
signal wb_req_data_wdata : std_logic_vector(63 downto 0);
signal wb_req_data_wstrb : std_logic_vector(7 downto 0);
signal w_resp_data_valid : std_logic;
signal wb_resp_data_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
signal wb_resp_data_data : std_logic_vector(63 downto 0);
signal w_resp_data_load_fault : std_logic;
signal w_resp_data_store_fault : std_logic;
signal w_resp_data_er_mpu_load : std_logic;
signal w_resp_data_er_mpu_store : std_logic;
signal wb_resp_data_store_fault_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
signal w_resp_data_ready : std_logic;
signal w_mpu_region_we : std_logic;
signal wb_mpu_region_idx : std_logic_vector(CFG_MPU_TBL_WIDTH-1 downto 0);
signal wb_mpu_region_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
signal wb_mpu_region_mask : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
signal wb_mpu_region_flags : std_logic_vector(CFG_MPU_FL_TOTAL-1 downto 0);
signal wb_flush_address : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
signal w_flush_valid : std_logic;
signal wb_data_flush_address : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
signal w_data_flush_valid : std_logic;
signal w_data_flush_end : std_logic;
begin
proc0 : Processor generic map (
hartid => hartid,
async_reset => async_reset,
fpu_ena => fpu_ena,
tracer_ena => tracer_ena
) port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_req_ctrl_ready => w_req_ctrl_ready,
o_req_ctrl_valid => w_req_ctrl_valid,
o_req_ctrl_addr => wb_req_ctrl_addr,
i_resp_ctrl_valid => w_resp_ctrl_valid,
i_resp_ctrl_addr => wb_resp_ctrl_addr,
i_resp_ctrl_data => wb_resp_ctrl_data,
i_resp_ctrl_load_fault => w_resp_ctrl_load_fault,
i_resp_ctrl_executable => w_resp_ctrl_executable,
o_resp_ctrl_ready => w_resp_ctrl_ready,
i_req_data_ready => w_req_data_ready,
o_req_data_valid => w_req_data_valid,
o_req_data_write => w_req_data_write,
o_req_data_addr => wb_req_data_addr,
o_req_data_wdata => wb_req_data_wdata,
o_req_data_wstrb => wb_req_data_wstrb,
i_resp_data_valid => w_resp_data_valid,
i_resp_data_addr => wb_resp_data_addr,
i_resp_data_data => wb_resp_data_data,
i_resp_data_store_fault_addr => wb_resp_data_store_fault_addr,
i_resp_data_load_fault => w_resp_data_load_fault,
i_resp_data_store_fault => w_resp_data_store_fault,
i_resp_data_er_mpu_load => w_resp_data_er_mpu_load,
i_resp_data_er_mpu_store => w_resp_data_er_mpu_store,
o_resp_data_ready => w_resp_data_ready,
i_ext_irq => i_ext_irq,
o_mpu_region_we => w_mpu_region_we,
o_mpu_region_idx => wb_mpu_region_idx,
o_mpu_region_addr => wb_mpu_region_addr,
o_mpu_region_mask => wb_mpu_region_mask,
o_mpu_region_flags => wb_mpu_region_flags,
i_dport_req_valid => i_dport_req_valid,
i_dport_write => i_dport_write,
i_dport_addr => i_dport_addr,
i_dport_wdata => i_dport_wdata,
o_dport_req_ready => o_dport_req_ready,
i_dport_resp_ready => i_dport_resp_ready,
o_dport_resp_valid => o_dport_resp_valid,
o_dport_rdata => o_dport_rdata,
o_halted => o_halted,
o_flush_address => wb_flush_address,
o_flush_valid => w_flush_valid,
o_data_flush_address => wb_data_flush_address,
o_data_flush_valid => w_data_flush_valid,
i_data_flush_end => w_data_flush_end);
cache0 : CacheTop generic map (
memtech => memtech,
async_reset => async_reset,
coherence_ena => coherence_ena
) port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_req_ctrl_valid => w_req_ctrl_valid,
i_req_ctrl_addr => wb_req_ctrl_addr,
o_req_ctrl_ready => w_req_ctrl_ready,
o_resp_ctrl_valid => w_resp_ctrl_valid,
o_resp_ctrl_addr => wb_resp_ctrl_addr,
o_resp_ctrl_data => wb_resp_ctrl_data,
o_resp_ctrl_load_fault => w_resp_ctrl_load_fault,
o_resp_ctrl_executable => w_resp_ctrl_executable,
i_resp_ctrl_ready => w_resp_ctrl_ready,
i_req_data_valid => w_req_data_valid,
i_req_data_write => w_req_data_write,
i_req_data_addr => wb_req_data_addr,
i_req_data_wdata => wb_req_data_wdata,
i_req_data_wstrb => wb_req_data_wstrb,
o_req_data_ready => w_req_data_ready,
o_resp_data_valid => w_resp_data_valid,
o_resp_data_addr => wb_resp_data_addr,
o_resp_data_data => wb_resp_data_data,
o_resp_data_store_fault_addr => wb_resp_data_store_fault_addr,
o_resp_data_load_fault => w_resp_data_load_fault,
o_resp_data_store_fault => w_resp_data_store_fault,
o_resp_data_er_mpu_load => w_resp_data_er_mpu_load,
o_resp_data_er_mpu_store => w_resp_data_er_mpu_store,
i_resp_data_ready => w_resp_data_ready,
i_req_mem_ready => i_req_mem_ready,
o_req_mem_path => o_req_mem_path,
o_req_mem_valid => o_req_mem_valid,
o_req_mem_type => o_req_mem_type,
o_req_mem_addr => o_req_mem_addr,
o_req_mem_strob => o_req_mem_strob,
o_req_mem_data => o_req_mem_data,
i_resp_mem_valid => i_resp_mem_valid,
i_resp_mem_path => i_resp_mem_path,
i_resp_mem_data => i_resp_mem_data,
i_resp_mem_load_fault => i_resp_mem_load_fault,
i_resp_mem_store_fault => i_resp_mem_store_fault,
i_mpu_region_we => w_mpu_region_we,
i_mpu_region_idx => wb_mpu_region_idx,
i_mpu_region_addr => wb_mpu_region_addr,
i_mpu_region_mask => wb_mpu_region_mask,
i_mpu_region_flags => wb_mpu_region_flags,
i_req_snoop_valid => i_req_snoop_valid,
i_req_snoop_type => i_req_snoop_type,
o_req_snoop_ready => o_req_snoop_ready,
i_req_snoop_addr => i_req_snoop_addr,
i_resp_snoop_ready => i_resp_snoop_ready,
o_resp_snoop_valid => o_resp_snoop_valid,
o_resp_snoop_data => o_resp_snoop_data,
o_resp_snoop_flags => o_resp_snoop_flags,
i_flush_address => wb_flush_address,
i_flush_valid => w_flush_valid,
i_data_flush_address => wb_data_flush_address,
i_data_flush_valid => w_data_flush_valid,
o_data_flush_end => w_data_flush_end);
end;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := artix7;
constant CFG_MEMTECH : integer := artix7;
constant CFG_PADTECH : integer := artix7;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := artix7;
constant CFG_CLKMUL : integer := (10);
constant CFG_CLKDIV : integer := (20);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 4;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 1 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 0;
constant CFG_DDR2SP_INIT : integer := 0;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := 130;
constant CFG_DDR2SP_DATAWIDTH : integer := 64;
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := 9;
constant CFG_DDR2SP_SIZE : integer := 8;
constant CFG_DDR2SP_DELAY0 : integer := 0;
constant CFG_DDR2SP_DELAY1 : integer := 0;
constant CFG_DDR2SP_DELAY2 : integer := 0;
constant CFG_DDR2SP_DELAY3 : integer := 0;
constant CFG_DDR2SP_DELAY4 : integer := 0;
constant CFG_DDR2SP_DELAY5 : integer := 0;
constant CFG_DDR2SP_DELAY6 : integer := 0;
constant CFG_DDR2SP_DELAY7 : integer := 0;
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#F00#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 4;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 1;
end;
|
-------------------------------------------------------------------------------
-- bfm_monitor_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plbv46_monitor_bfm_v1_00_a;
use plbv46_monitor_bfm_v1_00_a.all;
entity bfm_monitor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
M_request : in std_logic_vector(0 to 1);
M_priority : in std_logic_vector(0 to 3);
M_buslock : in std_logic_vector(0 to 1);
M_RNW : in std_logic_vector(0 to 1);
M_BE : in std_logic_vector(0 to 31);
M_msize : in std_logic_vector(0 to 3);
M_size : in std_logic_vector(0 to 7);
M_type : in std_logic_vector(0 to 5);
M_TAttribute : in std_logic_vector(0 to 31);
M_lockErr : in std_logic_vector(0 to 1);
M_abort : in std_logic_vector(0 to 1);
M_UABus : in std_logic_vector(0 to 63);
M_ABus : in std_logic_vector(0 to 63);
M_wrDBus : in std_logic_vector(0 to 255);
M_wrBurst : in std_logic_vector(0 to 1);
M_rdBurst : in std_logic_vector(0 to 1);
PLB_MAddrAck : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic_vector(0 to 1);
PLB_MTimeout : in std_logic_vector(0 to 1);
PLB_MBusy : in std_logic_vector(0 to 1);
PLB_MRdErr : in std_logic_vector(0 to 1);
PLB_MWrErr : in std_logic_vector(0 to 1);
PLB_MIRQ : in std_logic_vector(0 to 1);
PLB_MWrDAck : in std_logic_vector(0 to 1);
PLB_MRdDBus : in std_logic_vector(0 to 255);
PLB_MRdWdAddr : in std_logic_vector(0 to 7);
PLB_MRdDAck : in std_logic_vector(0 to 1);
PLB_MRdBTerm : in std_logic_vector(0 to 1);
PLB_MWrBTerm : in std_logic_vector(0 to 1);
PLB_Mssize : in std_logic_vector(0 to 3);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic_vector(0 to 1);
PLB_wrPrim : in std_logic_vector(0 to 1);
PLB_MasterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_wait : in std_logic_vector(0 to 1);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 255);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_MBusy : in std_logic_vector(0 to 3);
Sl_MRdErr : in std_logic_vector(0 to 3);
Sl_MWrErr : in std_logic_vector(0 to 3);
Sl_MIRQ : in std_logic_vector(0 to 3);
Sl_ssize : in std_logic_vector(0 to 3);
PLB_SaddrAck : in std_logic;
PLB_Swait : in std_logic;
PLB_Srearbitrate : in std_logic;
PLB_SwrDAck : in std_logic;
PLB_SwrComp : in std_logic;
PLB_SwrBTerm : in std_logic;
PLB_SrdDBus : in std_logic_vector(0 to 127);
PLB_SrdWdAddr : in std_logic_vector(0 to 3);
PLB_SrdDAck : in std_logic;
PLB_SrdComp : in std_logic;
PLB_SrdBTerm : in std_logic;
PLB_SMBusy : in std_logic_vector(0 to 1);
PLB_SMRdErr : in std_logic_vector(0 to 1);
PLB_SMWrErr : in std_logic_vector(0 to 1);
PLB_SMIRQ : in std_logic_vector(0 to 1);
PLB_Sssize : in std_logic_vector(0 to 1)
);
end bfm_monitor_wrapper;
architecture STRUCTURE of bfm_monitor_wrapper is
component plbv46_monitor_bfm is
generic (
PLB_MONITOR_NUM : std_logic_vector(0 to 3);
PLB_SLAVE0_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE0_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE0_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE0_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_HI_1 : std_logic_vector(0 to 31);
C_MON_PLB_AWIDTH : integer;
C_MON_PLB_DWIDTH : integer;
C_MON_PLB_NUM_MASTERS : integer;
C_MON_PLB_NUM_SLAVES : integer;
C_MON_PLB_MID_WIDTH : integer
);
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
M_request : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_priority : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_MASTERS)-1));
M_buslock : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_RNW : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_BE : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_DWIDTH/8)-1));
M_msize : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_MASTERS)-1));
M_size : in std_logic_vector(0 to ((4*C_MON_PLB_NUM_MASTERS)-1));
M_type : in std_logic_vector(0 to ((3*C_MON_PLB_NUM_MASTERS)-1));
M_TAttribute : in std_logic_vector(0 to 16*C_MON_PLB_NUM_MASTERS-1);
M_lockErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_UABus : in std_logic_vector(0 to ((C_MON_PLB_AWIDTH*C_MON_PLB_NUM_MASTERS)-1));
M_ABus : in std_logic_vector(0 to ((C_MON_PLB_AWIDTH*C_MON_PLB_NUM_MASTERS)-1));
M_wrDBus : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH*C_MON_PLB_NUM_MASTERS)-1));
M_wrBurst : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_rdBurst : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MAddrAck : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRearbitrate : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MTimeout : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MBusy : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRdErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MWrErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MIRQ : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MWrDAck : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRdDBus : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH*C_MON_PLB_NUM_MASTERS)-1));
PLB_MRdWdAddr : in std_logic_vector(0 to ((4*C_MON_PLB_NUM_MASTERS)-1));
PLB_MRdDAck : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRdBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MWrBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_Mssize : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_MASTERS)-1));
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
PLB_wrPrim : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
PLB_MasterID : in std_logic_vector(0 to C_MON_PLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH/8)-1));
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to (C_MON_PLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wait : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rearbitrate : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH*C_MON_PLB_NUM_SLAVES)-1));
Sl_rdWdAddr : in std_logic_vector(0 to ((4*C_MON_PLB_NUM_SLAVES)-1));
Sl_rdDAck : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rdBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_MBusy : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_MRdErr : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_MWrErr : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_MIRQ : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_ssize : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_SLAVES)-1));
PLB_SaddrAck : in std_logic;
PLB_Swait : in std_logic;
PLB_Srearbitrate : in std_logic;
PLB_SwrDAck : in std_logic;
PLB_SwrComp : in std_logic;
PLB_SwrBTerm : in std_logic;
PLB_SrdDBus : in std_logic_vector(0 to C_MON_PLB_DWIDTH-1);
PLB_SrdWdAddr : in std_logic_vector(0 to 3);
PLB_SrdDAck : in std_logic;
PLB_SrdComp : in std_logic;
PLB_SrdBTerm : in std_logic;
PLB_SMBusy : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_SMRdErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_SMWrErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_SMIRQ : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_Sssize : in std_logic_vector(0 to 1)
);
end component;
begin
bfm_monitor : plbv46_monitor_bfm
generic map (
PLB_MONITOR_NUM => B"0000",
PLB_SLAVE0_ADDR_LO_0 => X"00000000",
PLB_SLAVE0_ADDR_HI_0 => X"00000000",
PLB_SLAVE1_ADDR_LO_0 => X"00000000",
PLB_SLAVE1_ADDR_HI_0 => X"00000000",
PLB_SLAVE2_ADDR_LO_0 => X"00000000",
PLB_SLAVE2_ADDR_HI_0 => X"00000000",
PLB_SLAVE3_ADDR_LO_0 => X"00000000",
PLB_SLAVE3_ADDR_HI_0 => X"00000000",
PLB_SLAVE4_ADDR_LO_0 => X"00000000",
PLB_SLAVE4_ADDR_HI_0 => X"00000000",
PLB_SLAVE5_ADDR_LO_0 => X"00000000",
PLB_SLAVE5_ADDR_HI_0 => X"00000000",
PLB_SLAVE6_ADDR_LO_0 => X"00000000",
PLB_SLAVE6_ADDR_HI_0 => X"00000000",
PLB_SLAVE7_ADDR_LO_0 => X"00000000",
PLB_SLAVE7_ADDR_HI_0 => X"00000000",
PLB_SLAVE0_ADDR_LO_1 => X"00000000",
PLB_SLAVE0_ADDR_HI_1 => X"00000000",
PLB_SLAVE1_ADDR_LO_1 => X"00000000",
PLB_SLAVE1_ADDR_HI_1 => X"00000000",
PLB_SLAVE2_ADDR_LO_1 => X"00000000",
PLB_SLAVE2_ADDR_HI_1 => X"00000000",
PLB_SLAVE3_ADDR_LO_1 => X"00000000",
PLB_SLAVE3_ADDR_HI_1 => X"00000000",
PLB_SLAVE4_ADDR_LO_1 => X"00000000",
PLB_SLAVE4_ADDR_HI_1 => X"00000000",
PLB_SLAVE5_ADDR_LO_1 => X"00000000",
PLB_SLAVE5_ADDR_HI_1 => X"00000000",
PLB_SLAVE6_ADDR_LO_1 => X"00000000",
PLB_SLAVE6_ADDR_HI_1 => X"00000000",
PLB_SLAVE7_ADDR_LO_1 => X"00000000",
PLB_SLAVE7_ADDR_HI_1 => X"00000000",
C_MON_PLB_AWIDTH => 32,
C_MON_PLB_DWIDTH => 128,
C_MON_PLB_NUM_MASTERS => 2,
C_MON_PLB_NUM_SLAVES => 2,
C_MON_PLB_MID_WIDTH => 1
)
port map (
PLB_CLK => PLB_CLK,
PLB_RESET => PLB_RESET,
SYNCH_OUT => SYNCH_OUT,
SYNCH_IN => SYNCH_IN,
M_request => M_request,
M_priority => M_priority,
M_buslock => M_buslock,
M_RNW => M_RNW,
M_BE => M_BE,
M_msize => M_msize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_Mssize => PLB_Mssize,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_MasterID => PLB_MasterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_msize => PLB_msize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_UABus => PLB_UABus,
PLB_ABus => PLB_ABus,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_rdpendReq => PLB_rdpendReq,
PLB_wrpendReq => PLB_wrpendReq,
PLB_rdpendPri => PLB_rdpendPri,
PLB_wrpendPri => PLB_wrpendPri,
PLB_reqPri => PLB_reqPri,
Sl_addrAck => Sl_addrAck,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MIRQ => Sl_MIRQ,
Sl_ssize => Sl_ssize,
PLB_SaddrAck => PLB_SaddrAck,
PLB_Swait => PLB_Swait,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_SwrDAck => PLB_SwrDAck,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SMBusy => PLB_SMBusy,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMIRQ => PLB_SMIRQ,
PLB_Sssize => PLB_Sssize
);
end architecture STRUCTURE;
|
-------------------------------------------------------------------------------
-- bfm_monitor_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plbv46_monitor_bfm_v1_00_a;
use plbv46_monitor_bfm_v1_00_a.all;
entity bfm_monitor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
M_request : in std_logic_vector(0 to 1);
M_priority : in std_logic_vector(0 to 3);
M_buslock : in std_logic_vector(0 to 1);
M_RNW : in std_logic_vector(0 to 1);
M_BE : in std_logic_vector(0 to 31);
M_msize : in std_logic_vector(0 to 3);
M_size : in std_logic_vector(0 to 7);
M_type : in std_logic_vector(0 to 5);
M_TAttribute : in std_logic_vector(0 to 31);
M_lockErr : in std_logic_vector(0 to 1);
M_abort : in std_logic_vector(0 to 1);
M_UABus : in std_logic_vector(0 to 63);
M_ABus : in std_logic_vector(0 to 63);
M_wrDBus : in std_logic_vector(0 to 255);
M_wrBurst : in std_logic_vector(0 to 1);
M_rdBurst : in std_logic_vector(0 to 1);
PLB_MAddrAck : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic_vector(0 to 1);
PLB_MTimeout : in std_logic_vector(0 to 1);
PLB_MBusy : in std_logic_vector(0 to 1);
PLB_MRdErr : in std_logic_vector(0 to 1);
PLB_MWrErr : in std_logic_vector(0 to 1);
PLB_MIRQ : in std_logic_vector(0 to 1);
PLB_MWrDAck : in std_logic_vector(0 to 1);
PLB_MRdDBus : in std_logic_vector(0 to 255);
PLB_MRdWdAddr : in std_logic_vector(0 to 7);
PLB_MRdDAck : in std_logic_vector(0 to 1);
PLB_MRdBTerm : in std_logic_vector(0 to 1);
PLB_MWrBTerm : in std_logic_vector(0 to 1);
PLB_Mssize : in std_logic_vector(0 to 3);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic_vector(0 to 1);
PLB_wrPrim : in std_logic_vector(0 to 1);
PLB_MasterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_wait : in std_logic_vector(0 to 1);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 255);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_MBusy : in std_logic_vector(0 to 3);
Sl_MRdErr : in std_logic_vector(0 to 3);
Sl_MWrErr : in std_logic_vector(0 to 3);
Sl_MIRQ : in std_logic_vector(0 to 3);
Sl_ssize : in std_logic_vector(0 to 3);
PLB_SaddrAck : in std_logic;
PLB_Swait : in std_logic;
PLB_Srearbitrate : in std_logic;
PLB_SwrDAck : in std_logic;
PLB_SwrComp : in std_logic;
PLB_SwrBTerm : in std_logic;
PLB_SrdDBus : in std_logic_vector(0 to 127);
PLB_SrdWdAddr : in std_logic_vector(0 to 3);
PLB_SrdDAck : in std_logic;
PLB_SrdComp : in std_logic;
PLB_SrdBTerm : in std_logic;
PLB_SMBusy : in std_logic_vector(0 to 1);
PLB_SMRdErr : in std_logic_vector(0 to 1);
PLB_SMWrErr : in std_logic_vector(0 to 1);
PLB_SMIRQ : in std_logic_vector(0 to 1);
PLB_Sssize : in std_logic_vector(0 to 1)
);
end bfm_monitor_wrapper;
architecture STRUCTURE of bfm_monitor_wrapper is
component plbv46_monitor_bfm is
generic (
PLB_MONITOR_NUM : std_logic_vector(0 to 3);
PLB_SLAVE0_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE0_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE0_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE0_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_HI_1 : std_logic_vector(0 to 31);
C_MON_PLB_AWIDTH : integer;
C_MON_PLB_DWIDTH : integer;
C_MON_PLB_NUM_MASTERS : integer;
C_MON_PLB_NUM_SLAVES : integer;
C_MON_PLB_MID_WIDTH : integer
);
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
M_request : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_priority : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_MASTERS)-1));
M_buslock : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_RNW : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_BE : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_DWIDTH/8)-1));
M_msize : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_MASTERS)-1));
M_size : in std_logic_vector(0 to ((4*C_MON_PLB_NUM_MASTERS)-1));
M_type : in std_logic_vector(0 to ((3*C_MON_PLB_NUM_MASTERS)-1));
M_TAttribute : in std_logic_vector(0 to 16*C_MON_PLB_NUM_MASTERS-1);
M_lockErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_UABus : in std_logic_vector(0 to ((C_MON_PLB_AWIDTH*C_MON_PLB_NUM_MASTERS)-1));
M_ABus : in std_logic_vector(0 to ((C_MON_PLB_AWIDTH*C_MON_PLB_NUM_MASTERS)-1));
M_wrDBus : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH*C_MON_PLB_NUM_MASTERS)-1));
M_wrBurst : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_rdBurst : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MAddrAck : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRearbitrate : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MTimeout : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MBusy : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRdErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MWrErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MIRQ : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MWrDAck : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRdDBus : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH*C_MON_PLB_NUM_MASTERS)-1));
PLB_MRdWdAddr : in std_logic_vector(0 to ((4*C_MON_PLB_NUM_MASTERS)-1));
PLB_MRdDAck : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRdBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MWrBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_Mssize : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_MASTERS)-1));
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
PLB_wrPrim : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
PLB_MasterID : in std_logic_vector(0 to C_MON_PLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH/8)-1));
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to (C_MON_PLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wait : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rearbitrate : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH*C_MON_PLB_NUM_SLAVES)-1));
Sl_rdWdAddr : in std_logic_vector(0 to ((4*C_MON_PLB_NUM_SLAVES)-1));
Sl_rdDAck : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rdBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_MBusy : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_MRdErr : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_MWrErr : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_MIRQ : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_ssize : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_SLAVES)-1));
PLB_SaddrAck : in std_logic;
PLB_Swait : in std_logic;
PLB_Srearbitrate : in std_logic;
PLB_SwrDAck : in std_logic;
PLB_SwrComp : in std_logic;
PLB_SwrBTerm : in std_logic;
PLB_SrdDBus : in std_logic_vector(0 to C_MON_PLB_DWIDTH-1);
PLB_SrdWdAddr : in std_logic_vector(0 to 3);
PLB_SrdDAck : in std_logic;
PLB_SrdComp : in std_logic;
PLB_SrdBTerm : in std_logic;
PLB_SMBusy : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_SMRdErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_SMWrErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_SMIRQ : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_Sssize : in std_logic_vector(0 to 1)
);
end component;
begin
bfm_monitor : plbv46_monitor_bfm
generic map (
PLB_MONITOR_NUM => B"0000",
PLB_SLAVE0_ADDR_LO_0 => X"00000000",
PLB_SLAVE0_ADDR_HI_0 => X"00000000",
PLB_SLAVE1_ADDR_LO_0 => X"00000000",
PLB_SLAVE1_ADDR_HI_0 => X"00000000",
PLB_SLAVE2_ADDR_LO_0 => X"00000000",
PLB_SLAVE2_ADDR_HI_0 => X"00000000",
PLB_SLAVE3_ADDR_LO_0 => X"00000000",
PLB_SLAVE3_ADDR_HI_0 => X"00000000",
PLB_SLAVE4_ADDR_LO_0 => X"00000000",
PLB_SLAVE4_ADDR_HI_0 => X"00000000",
PLB_SLAVE5_ADDR_LO_0 => X"00000000",
PLB_SLAVE5_ADDR_HI_0 => X"00000000",
PLB_SLAVE6_ADDR_LO_0 => X"00000000",
PLB_SLAVE6_ADDR_HI_0 => X"00000000",
PLB_SLAVE7_ADDR_LO_0 => X"00000000",
PLB_SLAVE7_ADDR_HI_0 => X"00000000",
PLB_SLAVE0_ADDR_LO_1 => X"00000000",
PLB_SLAVE0_ADDR_HI_1 => X"00000000",
PLB_SLAVE1_ADDR_LO_1 => X"00000000",
PLB_SLAVE1_ADDR_HI_1 => X"00000000",
PLB_SLAVE2_ADDR_LO_1 => X"00000000",
PLB_SLAVE2_ADDR_HI_1 => X"00000000",
PLB_SLAVE3_ADDR_LO_1 => X"00000000",
PLB_SLAVE3_ADDR_HI_1 => X"00000000",
PLB_SLAVE4_ADDR_LO_1 => X"00000000",
PLB_SLAVE4_ADDR_HI_1 => X"00000000",
PLB_SLAVE5_ADDR_LO_1 => X"00000000",
PLB_SLAVE5_ADDR_HI_1 => X"00000000",
PLB_SLAVE6_ADDR_LO_1 => X"00000000",
PLB_SLAVE6_ADDR_HI_1 => X"00000000",
PLB_SLAVE7_ADDR_LO_1 => X"00000000",
PLB_SLAVE7_ADDR_HI_1 => X"00000000",
C_MON_PLB_AWIDTH => 32,
C_MON_PLB_DWIDTH => 128,
C_MON_PLB_NUM_MASTERS => 2,
C_MON_PLB_NUM_SLAVES => 2,
C_MON_PLB_MID_WIDTH => 1
)
port map (
PLB_CLK => PLB_CLK,
PLB_RESET => PLB_RESET,
SYNCH_OUT => SYNCH_OUT,
SYNCH_IN => SYNCH_IN,
M_request => M_request,
M_priority => M_priority,
M_buslock => M_buslock,
M_RNW => M_RNW,
M_BE => M_BE,
M_msize => M_msize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_Mssize => PLB_Mssize,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_MasterID => PLB_MasterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_msize => PLB_msize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_UABus => PLB_UABus,
PLB_ABus => PLB_ABus,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_rdpendReq => PLB_rdpendReq,
PLB_wrpendReq => PLB_wrpendReq,
PLB_rdpendPri => PLB_rdpendPri,
PLB_wrpendPri => PLB_wrpendPri,
PLB_reqPri => PLB_reqPri,
Sl_addrAck => Sl_addrAck,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MIRQ => Sl_MIRQ,
Sl_ssize => Sl_ssize,
PLB_SaddrAck => PLB_SaddrAck,
PLB_Swait => PLB_Swait,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_SwrDAck => PLB_SwrDAck,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SMBusy => PLB_SMBusy,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMIRQ => PLB_SMIRQ,
PLB_Sssize => PLB_Sssize
);
end architecture STRUCTURE;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file xsd_rom.vhd when simulating
-- the core, xsd_rom. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY xsd_rom IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END xsd_rom;
ARCHITECTURE xsd_rom_a OF xsd_rom IS
-- synthesis translate_off
COMPONENT wrapped_xsd_rom
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_xsd_rom USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 11,
c_addrb_width => 11,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "xsd_rom.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 2048,
c_read_depth_b => 2048,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 2048,
c_write_depth_b => 2048,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_xsd_rom
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END xsd_rom_a;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: sim_pll
-- File: sim_pll.vhd
-- Author: Magnus Hjorth, Aeroflex Gaisler
-- Description: Generic simulated PLL with input frequency checking
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity sim_pll is
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
-- Frequency limits in kHz, for checking only
minfreq: integer := 0;
maxfreq: integer := 10000000;
-- Lock tolerance in ps
locktol: integer := 2
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end;
architecture sim of sim_pll is
signal clkout1,clkout2,clkout3,clkout4: std_logic;
signal tp: time := 1 ns;
signal timeset: boolean := false;
signal fb: std_ulogic;
signal comp: time := 0 ns;
signal llock: std_logic;
begin
o1 <= transport clkout1 after tp + (tp*clkdiv1*(clkphase1 mod 360)) / (clkmul*360);
o2 <= transport clkout2 after tp + (tp*clkdiv2*(clkphase2 mod 360)) / (clkmul*360);
o3 <= transport clkout3 after tp + (tp*clkdiv3*(clkphase3 mod 360)) / (clkmul*360);
o4 <= transport clkout4 after tp + (tp*clkdiv4*(clkphase4 mod 360)) / (clkmul*360);
lock <= llock after tp*20; -- 20 cycle inertia on lock signal
freqmeas: process(i)
variable ts,te: time;
variable mf: integer;
variable warned: boolean := false;
variable first: boolean := true;
begin
if rising_edge(i) and (now /= (0 ps)) then
ts := te;
te := now;
if first then
first := false;
else
mf := (1 ms) / (te-ts);
assert (mf >= minfreq and mf <= maxfreq) or warned or rst='0' or llock/='1'
report "Input frequency out of range, " &
"measured: " & tost(mf) & ", min:" & tost(minfreq) & ", max:" & tost(maxfreq)
severity warning;
if (mf < minfreq or mf > maxfreq) and rst/='0' and llock='1' then warned := true; end if;
if llock='0' or te-ts-tp > locktol*(1 ps) or te-ts-tp < -locktol*(1 ps) then
tp <= te-ts;
timeset <= true;
end if;
end if;
end if;
end process;
genclk: process
variable divcount1,divcount2,divcount3,divcount4: integer;
variable compen: boolean;
variable t: time;
variable compps: integer;
begin
compen := false;
clkout1 <= '0';
clkout2 <= '0';
clkout3 <= '0';
clkout4 <= '0';
if not timeset or rst='0' then
wait until timeset and rst/='0';
end if;
divcount1 := 0;
divcount2 := 0;
divcount3 := 0;
divcount4 := 0;
fb <= '1';
clkout1 <= '1';
clkout2 <= '1';
clkout3 <= '1';
clkout4 <= '1';
oloop: loop
for x in 0 to 2*clkmul-1 loop
if x=0 then fb <= '1'; end if;
if x=clkmul then fb <= '0'; end if;
t := tp/(2*clkmul);
if compen and comp /= (0 ns) then
-- Handle compensation below resolution limit (1 ps assumed)
if comp < 2*clkmul*(1 ps) and comp > -2*clkmul*(1 ps) then
compps := abs(comp / (1 ps));
if x > 0 and x <= compps then
if comp > 0 ps then
t := t + 1 ps;
else
t := t - 1 ps;
end if;
end if;
else
t:=t+comp/(2*clkmul);
end if;
end if;
if t > (0 ns) then
wait on rst for t;
else
wait for 1 ns;
end if;
exit oloop when rst='0';
divcount1 := divcount1+1;
if divcount1 >= clkdiv1 then
clkout1 <= not clkout1;
divcount1 := 0;
end if;
divcount2 := divcount2+1;
if divcount2 >= clkdiv2 then
clkout2 <= not clkout2;
divcount2 := 0;
end if;
divcount3 := divcount3+1;
if divcount3 >= clkdiv3 then
clkout3 <= not clkout3;
divcount3 := 0;
end if;
divcount4 := divcount4+1;
if divcount4 >= clkdiv4 then
clkout4 <= not clkout4;
divcount4 := 0;
end if;
end loop;
compen := true;
end loop oloop;
end process;
fbchk: process(fb,i)
variable last_i,prev_i: time;
variable last_fb,prev_fb: time;
variable vlock: std_logic := '0';
begin
if falling_edge(i) then
prev_i := last_i;
last_i := now;
end if;
if falling_edge(fb) then
-- Update phase compensation
if last_i < last_fb+tp/2 then
comp <= (last_i - last_fb);
else
comp <= last_i - now;
end if;
prev_fb := last_fb;
last_fb := now;
end if;
if (last_i<=(last_fb+locktol*(1 ps)) and last_i>=(last_fb-locktol*(1 ps)) and
prev_i<=(prev_fb+locktol*(1 ps)) and prev_i>=(prev_fb-locktol*(1 ps))) then
vlock := '1';
end if;
if prev_fb > last_i+locktol*(1 ps) or prev_i>last_fb+locktol*(1 ps) then
vlock := '0';
end if;
llock <= vlock;
end process;
end;
|
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5600)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5600)
`protect data_block
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`protect end_protected
|
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
entity mux is
port ( clock : in std_logic;
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
Z : in std_logic;
prod : out std_logic_vector(31 downto 0));
end mux;
architecture behav of mux is
begin
process (z,a,b)
begin
if z = '0' then
prod <= a;
elsif z = '1' then
prod <= b;
end if;
end process;
end behav;
|
library verilog;
use verilog.vl_types.all;
entity Etapa1 is
port(
HEX0 : out vl_logic_vector(6 downto 0);
SW : in vl_logic_vector(4 downto 1)
);
end Etapa1;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
use work.wishbonepkg.all;
-- synthesis translate_off
use work.txt_util.all;
-- synthesis translate_on
entity icache is
generic (
ADDRESS_HIGH: integer := 31
);
port (
syscon: in wb_syscon_type;
valid: out std_logic;
data: out std_logic_vector(31 downto 0);
address: in std_logic_vector(31 downto 0);
strobe: in std_logic;
enable: in std_logic;
seq: in std_logic;
stall: out std_logic;
flush: in std_logic;
abort: in std_logic;
tag: in std_logic_vector(31 downto 0);
tagen: in std_logic;
-- Master wishbone interface
mwbo: out wb_mosi_type;
mwbi: in wb_miso_type
);
end icache;
architecture behave of icache is
constant ADDRESS_LOW: integer := 0;
constant CACHE_MAX_BITS: integer := 13; -- 8 Kb
constant CACHE_LINE_SIZE_BITS: integer := 6; -- 64 bytes
constant CACHE_LINE_SIZE: integer := 2**CACHE_LINE_SIZE_BITS;
constant CACHE_LINE_ID_BITS: integer := CACHE_MAX_BITS-CACHE_LINE_SIZE_BITS;
-- memory max width: 19 bits (18 downto 0)
-- cache line size: 64 bytes
-- cache lines: 128
alias line: std_logic_vector(CACHE_LINE_ID_BITS-1 downto 0)
is address(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS);
alias line_offset: std_logic_vector(CACHE_LINE_SIZE_BITS-1 downto 2)
is address(CACHE_LINE_SIZE_BITS-1 downto 2);
signal ctag: std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS+1 downto 0);
signal miss: std_logic;
signal ack: std_logic;
type state_type is (
flushing,
running,
filling,
--waitwrite,
ending
);
constant offcnt_zero: unsigned(line_offset'HIGH downto 2) := (others => '0');
signal tag_match: std_logic;
signal cache_addr_read,cache_addr_write: std_logic_vector(CACHE_MAX_BITS-1 downto 2);
signal access_i: std_logic;
signal stall_i, valid_i: std_logic;
signal hit: std_logic;
signal tag_mem_enable: std_logic;
signal cache_mem_enable: std_logic;
signal exttag_save: std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS downto 0);
signal tag_mem_data: std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS+1 downto 0);
signal tag_mem_addr: std_logic_vector(CACHE_LINE_ID_BITS-1 downto 0);
constant dignore: std_logic_vector(ctag'RANGE) := (others => DontCareValue);
constant dignore32: std_logic_vector(31 downto 0) := (others => DontCareValue);
signal valid_while_filling: std_logic;
type icache_regs_type is record
cyc, stb: std_logic;
busy: std_logic;
state: state_type;
fill_success: std_logic;
flushcnt: unsigned(line'RANGE);
tag_mem_wen: std_logic;
wbaddr: std_logic_vector(31 downto CACHE_MAX_BITS);
offcnt: unsigned(line_offset'HIGH downto 2);
offcnt_write: unsigned(line_offset'HIGH downto 2);
stbcount: unsigned(line_offset'HIGH downto 2);
access_q: std_logic;
queued_address: std_logic;
save_addr: std_logic_vector(address'RANGE);
line_save: std_logic_vector(CACHE_LINE_ID_BITS-1 downto 0);
tag_save: std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS downto 0);
enable_q: std_logic;
iwfready: std_logic;
fault: std_logic;
flush: std_logic;
end record;
signal r: icache_regs_type;
alias tag_save: std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS downto 0)
is r.save_addr(ADDRESS_HIGH downto CACHE_MAX_BITS);
alias address_tag: std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS downto 0)
is r.save_addr(ADDRESS_HIGH downto CACHE_MAX_BITS);
signal ctag_address: std_logic_vector(address_tag'RANGE);
signal wrcachea: std_logic;
signal cmem_enable: std_logic;
signal cmem_wren: std_logic;
signal access_to_same_line: std_logic;
begin
ctag_address<=ctag(address_tag'HIGH downto address_tag'LOW);
tagmem: entity work.generic_dp_ram_1r1w
generic map (
address_bits => CACHE_LINE_ID_BITS,
data_bits => ADDRESS_HIGH-CACHE_MAX_BITS+2
)
port map (
clka => syscon.clk,
ena => tag_mem_enable,
addra => cache_addr_read(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS),--line,
doa => ctag,
clkb => syscon.clk,
enb => '1',
web => r.tag_mem_wen,
addrb => tag_mem_addr,
dib => tag_mem_data,
dob => open
);
cachemem: entity work.generic_dp_ram_1r1w
generic map (
address_bits => cache_addr_read'LENGTH,
data_bits => 32
)
port map (
clka => syscon.clk,
ena => cache_mem_enable,
addra => cache_addr_read,
doa => data,
clkb => syscon.clk,
enb => cmem_enable,
web => cmem_wren,
addrb => cache_addr_write,
dib => mwbi.dat,
dob => open
);
cmem_enable <= '1';
cmem_wren <= mwbi.ack;
valid_i <= ctag(ctag'HIGH);
process(r.state, r.flushcnt, tagen, exttag_save)
variable wrtag: std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS downto 0);
begin
if tagen='1' then
wrtag := exttag_save;
else
wrtag := tag_save;
end if;
if r.state=flushing then
tag_mem_data <= '0' & wrtag;
tag_mem_addr <= std_logic_vector(r.flushcnt);
else
tag_mem_data <= '1' & wrtag;
tag_mem_addr <= r.line_save;
end if;
end process;
process(ctag_address, address_tag, tag, tagen)
begin
if tagen='0' then
if ctag_address=address_tag then
tag_match<='1';
else
tag_match<='0';
end if;
else
if ctag_address=tag(ADDRESS_HIGH downto CACHE_MAX_BITS) then
tag_match<='1';
else
tag_match<='0';
end if;
end if;
end process;
cache_addr_write <= r.line_save & mwbi.tag(CACHE_LINE_SIZE_BITS-3 downto 0);
access_to_same_line<='1' when r.line_save = r.save_addr(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS) and
r.tag_save = r.save_addr(ADDRESS_HIGH downto CACHE_MAX_BITS) else '0';
process(r,strobe,enable,miss,syscon,line,line_offset,hit,flush,mwbi,valid_while_filling,abort)
variable ett: std_logic_vector(exttag_save'RANGE);
variable w: icache_regs_type;
variable data_valid: std_logic;
variable stall_input: std_logic;
begin
w:=r;
w.busy := '0';
w.cyc := '0';
-- w.stb := 'X';
w.tag_mem_wen := '0';
w.fill_success :='0';
w.flushcnt := (others => 'X');
data_valid := '0';
tag_mem_enable <= enable and strobe;
cache_mem_enable <= enable and strobe;
cache_addr_read <= line & line_offset;
case r.state is
when flushing =>
w.busy := '1';
w.flushcnt := r.flushcnt - 1;
w.tag_mem_wen := '1';
w.wbaddr(31 downto CACHE_MAX_BITS) := (others => 'X');
w.offcnt := (others => 'X');
w.offcnt_write := (others => 'X');
w.iwfready := '0';
stall_input := '1';
if r.flushcnt=0 then
w.tag_mem_wen:='0';
--w.state := running;
if r.queued_address='1' and r.fault='1' then
w.state := filling;
w.wbaddr(31 downto CACHE_MAX_BITS) := r.save_addr(31 downto CACHE_MAX_BITS);
w.state := filling;
w.offcnt(CACHE_LINE_SIZE_BITS-1 downto 2) := unsigned(r.save_addr(CACHE_LINE_SIZE_BITS-1 downto 2));
w.offcnt_write := (others => '1');
w.stbcount := (others => '1');
w.cyc := '1';
w.stb := '1';
w.busy := '1';
w.queued_address:='0';
w.line_save := r.save_addr(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS);
w.tag_save := r.save_addr(ADDRESS_HIGH downto CACHE_MAX_BITS);
else
w.state := running;
end if;
end if;
when running =>
w.offcnt := (others => 'X');
w.offcnt_write := (others => 'X');
w.wbaddr(31 downto CACHE_MAX_BITS) := (others => 'X');
w.iwfready:='0';
stall_input := '0';
data_valid := hit;
w.stb := 'X';
if r.access_q='1' then
-- We had a cache access in last clock cycle.
if r.enable_q='1' then
if miss='1' and abort='0' then -- And it was a miss...
stall_input := '1';
data_valid := '0';
w.wbaddr(31 downto CACHE_MAX_BITS) := r.save_addr(31 downto CACHE_MAX_BITS);
w.state := filling;
w.offcnt(CACHE_LINE_SIZE_BITS-1 downto 2) := unsigned(r.save_addr(CACHE_LINE_SIZE_BITS-1 downto 2));
w.offcnt_write := (others => '1');
w.stbcount := (others => '1');
w.cyc := '1';
w.stb := '1';
w.busy := '1';
else
data_valid := '1';
end if;
end if;
end if;
if flush='1' then
w.state := flushing;
w.flushcnt := (others => '1');
w.tag_mem_wen := '1';
-- TODO: check if this is correct...
stall_input:='1';
end if;
w.queued_address := '0';
if r.access_q='1' and data_valid='0' then
w.queued_address:='1';
else
w.queued_address:='0';
end if;
w.fault := '0';
when filling =>
stall_input := '1';
w.busy:= '1';
w.cyc := '1';
tag_mem_enable <= '1';
cache_mem_enable <= enable and strobe;
if mwbi.ack='1' then
w.iwfready := enable;
w.offcnt_write := r.offcnt_write - 1;
-- This will go to 0, but we check before and switch state
if r.offcnt_write=offcnt_zero then
w.tag_mem_wen := '1';
w.state := ending;
end if;
end if;
if mwbi.stall='0' then
w.offcnt := r.offcnt + 1;
-- this needed ??
if r.stbcount/=offcnt_zero then
w.stbcount := w.stbcount - 1;
else
w.stb := '0';
end if;
end if;
if true then
if r.iwfready='0' then
cache_addr_read <= r.save_addr(CACHE_MAX_BITS-1 downto 2);
end if;
if enable='1' then
stall_input := not r.iwfready;
data_valid := r.iwfready;
if r.iwfready='1' and strobe='1' then
w.iwfready:='0';
end if;
if seq='0' and strobe='1' and stall_input='0' then
--stall_input := '1';
data_valid:='0';
w.fault :='1';
end if;
if r.access_q='1' and access_to_same_line='0' then
data_valid:='0';
stall_input:='1';
w.fault := '1';
end if;
end if;
if r.fault='1' then
stall_input:='1';
data_valid:='0';
end if;
if stall_input='0' then
if enable='1' and strobe='1' then
w.queued_address:='1';
else
w.queued_address:='0';
end if;
end if;
if flush='1' then
w.fault:='1';
data_valid:='0';
stall_input:='1';
w.flush:='1';
end if;
if stall_input='0' then
if enable='1' and strobe='1' then
w.queued_address:='1';
else
w.queued_address:='0';
end if;
end if;
if abort='1' then
w.fault:='1';
end if;
end if; -- IWF
when ending =>
w.busy :='0';
w.wbaddr(31 downto CACHE_MAX_BITS) := (others => 'X');
w.offcnt := (others => 'X');
w.offcnt_write := (others => 'X');
w.stbcount := (others => 'X');
w.line_save:= (others => 'X');
w.tag_save:= (others => 'X');
w.iwfready:='0';
tag_mem_enable <= '1';
cache_mem_enable <='1';
cache_addr_read <= r.save_addr(CACHE_MAX_BITS-1 downto 2);
stall_input := '1';
w.fault:='0';
if enable='1' then
w.fill_success := '1';
end if;
if r.queued_address='1' then--and r.fault='1' then
w.state := filling;
w.cyc := '1';
w.stb := '1';
w.busy := '1';
w.queued_address:='0';
w.wbaddr(31 downto CACHE_MAX_BITS) := r.save_addr(31 downto CACHE_MAX_BITS);
w.offcnt(CACHE_LINE_SIZE_BITS-1 downto 2) := unsigned(r.save_addr(CACHE_LINE_SIZE_BITS-1 downto 2));
w.offcnt_write := (others => '1');
w.stbcount := (others => '1');
w.line_save := r.save_addr(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS);
w.tag_save := r.save_addr(ADDRESS_HIGH downto CACHE_MAX_BITS);
else
w.state := running;
end if;
w.flush:='0';
if r.flush='1' then
w.state := flushing;
w.flushcnt := (others => '1');
w.tag_mem_wen := '1';
w.cyc :='0';
end if;
end case;
if strobe='1' and enable='1' then
if stall_input='0' then
w.save_addr := address;
w.access_q := '1';
if r.state=running then
w.line_save := address(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS);
w.tag_save := address(ADDRESS_HIGH downto CACHE_MAX_BITS);
end if;
end if;
else
if stall_input='0' then
w.access_q := '0';
end if;
end if;
if abort='1' then
w.access_q:='0';
w.queued_address:='0';
end if;
w.enable_q := enable;
valid <= data_valid;
stall <= stall_input;
if syscon.rst='1' then
w.state := flushing;
w.busy := '1';
w.fill_success :='0';
w.flushcnt := (others => '1');
w.tag_mem_wen := '1'; -- this needed ??
w.cyc := '0';
w.stb := 'X';
w.wbaddr(31 downto CACHE_MAX_BITS) := (others => 'X');
w.offcnt := (others => 'X');
w.offcnt_write := (others => 'X');
w.access_q := '0';
w.enable_q := '0';
w.queued_address:='0';
w.iwfready:='0';
w.flush := '0';
w.fault := '0';
w.stbcount := (others => 'X');
w.line_save:= (others => 'X');
w.tag_save:= (others => 'X');
end if;
if rising_edge(syscon.clk) then
r <= w;
end if;
end process;
hit <= '1' when tag_match='1' and valid_i='1' else '0';
miss <= not hit;
mwbo.cyc <= r.cyc;
mwbo.stb <= r.stb;
mwbo.we <= '0';
mwbo.dat <= (others => 'X');
mwbo.bte <= BTE_BURST_16BEATWRAP;
mwbo.cti <= CTI_CYCLE_INCRADDR; -- BUg: we need to signal eof
mwbo.adr(31 downto CACHE_MAX_BITS) <= r.wbaddr(31 downto CACHE_MAX_BITS);
mwbo.adr(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS) <= r.line_save;
mwbo.adr(CACHE_LINE_SIZE_BITS-1 downto 2) <= std_logic_vector(r.offcnt(CACHE_LINE_SIZE_BITS-1 downto 2));
mwbo.tag(CACHE_LINE_SIZE_BITS-3 downto 0) <= std_logic_vector(r.offcnt(CACHE_LINE_SIZE_BITS-1 downto 2));
mwbo.adr(1 downto 0) <= "00";
end behave;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2523.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p04n01i02523ent IS
END c07s03b05x00p04n01i02523ent;
ARCHITECTURE c07s03b05x00p04n01i02523arch OF c07s03b05x00p04n01i02523ent IS
BEGIN
TESTING: PROCESS
type Apples is range 0 to 75;
type Oranges is range 0 to 75;
variable Macintosh : Apples;
variable Seville : Oranges;
BEGIN
Macintosh := Apples (Seville) ;
Seville := Oranges (100) ;
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c07s03b05x00p04n01i02523 - Value does not belong to the subtype indicated by the type mark."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p04n01i02523arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2523.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p04n01i02523ent IS
END c07s03b05x00p04n01i02523ent;
ARCHITECTURE c07s03b05x00p04n01i02523arch OF c07s03b05x00p04n01i02523ent IS
BEGIN
TESTING: PROCESS
type Apples is range 0 to 75;
type Oranges is range 0 to 75;
variable Macintosh : Apples;
variable Seville : Oranges;
BEGIN
Macintosh := Apples (Seville) ;
Seville := Oranges (100) ;
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c07s03b05x00p04n01i02523 - Value does not belong to the subtype indicated by the type mark."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p04n01i02523arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2523.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p04n01i02523ent IS
END c07s03b05x00p04n01i02523ent;
ARCHITECTURE c07s03b05x00p04n01i02523arch OF c07s03b05x00p04n01i02523ent IS
BEGIN
TESTING: PROCESS
type Apples is range 0 to 75;
type Oranges is range 0 to 75;
variable Macintosh : Apples;
variable Seville : Oranges;
BEGIN
Macintosh := Apples (Seville) ;
Seville := Oranges (100) ;
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c07s03b05x00p04n01i02523 - Value does not belong to the subtype indicated by the type mark."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p04n01i02523arch;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.spi_bfm_pkg.all;
use work.vvc_methods_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_vvc_framework_common_methods_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
--=================================================================================================
entity spi_vvc is
generic (
GC_DATA_WIDTH : integer := 8;
GC_INSTANCE_IDX : natural := 1; -- Instance index for this SPI_VVCT instance
GC_MASTER_MODE : boolean := true;
GC_SPI_CONFIG : t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT; -- Behavior specification for BFM
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING
);
port (
spi_vvc_if : inout t_spi_if := init_spi_if_signals(GC_SPI_CONFIG, GC_MASTER_MODE)
);
end entity spi_vvc;
--=================================================================================================
--=================================================================================================
architecture behave of spi_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX);
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
-- Instantiation of the element dedicated Queue
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_spi_vvc_config(GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_spi_vvc_status(GC_INSTANCE_IDX);
alias transaction_info : t_transaction_info is shared_spi_transaction_info(GC_INSTANCE_IDX);
begin
--===============================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--===============================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, GC_SPI_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--===============================================================================================
--===============================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--===============================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := 0;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, shared_vvc_cmd, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- 2a. Put command on the queue if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed);
when AWAIT_ANY_COMPLETION =>
if not v_local_vvc_cmd.gen_boolean then
-- Called with lastness = NOT_LAST: Acknowledge immediately to let the sequencer continue
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
v_cmd_has_been_acked := true;
end if;
work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd);
when FETCH_RESULT =>
work.td_vvc_entity_support_pkg.interpreter_fetch_result(result_queue, v_local_vvc_cmd, vvc_config, C_VVC_LABELS, last_cmd_idx_executed, shared_vvc_response);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after runing or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
--uvvm_vvc_framework.ti_vvc_framework_support_pkg.acknowledge_cmd(global_vvc_ack);
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command executor
-- - Fetch and execute the commands
--===============================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_result : t_vvc_result; -- See vvc_cmd_pkg
variable v_timestamp_start_of_current_bfm_access : time := 0 ns;
variable v_timestamp_start_of_last_bfm_access : time := 0 ns;
variable v_timestamp_end_of_last_bfm_access : time := 0 ns;
variable v_command_is_bfm_access : boolean;
variable v_normalised_data : std_logic_vector(GC_DATA_WIDTH-1 downto 0) := (others => '0');
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
loop
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- Set the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
transaction_info.operation := v_cmd.operation;
transaction_info.msg := pad_string(to_string(v_cmd.msg), ' ', transaction_info.msg'length);
-- Check if command is a BFM access
if v_cmd.operation = MASTER_TRANSMIT_AND_RECEIVE or
v_cmd.operation = MASTER_TRANSMIT_AND_CHECK or
v_cmd.operation = MASTER_TRANSMIT_ONLY or
v_cmd.operation = MASTER_RECEIVE_ONLY or
v_cmd.operation = MASTER_CHECK_ONLY or
v_cmd.operation = SLAVE_TRANSMIT_AND_RECEIVE or
v_cmd.operation = SLAVE_TRANSMIT_AND_CHECK or
v_cmd.operation = SLAVE_TRANSMIT_ONLY or
v_cmd.operation = SLAVE_RECEIVE_ONLY or
v_cmd.operation = SLAVE_CHECK_ONLY
then
v_command_is_bfm_access := true;
else
v_command_is_bfm_access := false;
end if;
-- Insert delay if needed
work.td_vvc_entity_support_pkg.insert_inter_bfm_delay_if_requested(vvc_config => vvc_config,
command_is_bfm_access => v_command_is_bfm_access,
timestamp_start_of_last_bfm_access => v_timestamp_start_of_last_bfm_access,
timestamp_end_of_last_bfm_access => v_timestamp_end_of_last_bfm_access,
scope => C_SCOPE);
if v_command_is_bfm_access then
v_timestamp_start_of_current_bfm_access := now;
end if;
log(ID_BFM, "Running : " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd) & ".", C_SCOPE, vvc_config.msg_id_panel);
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is -- Only operations in the dedicated record are relevant
-- VVC dedicated operations
--===================================
when MASTER_TRANSMIT_AND_RECEIVE =>
transaction_info.tx_data(GC_DATA_WIDTH-1 downto 0) := v_cmd.data(GC_DATA_WIDTH-1 downto 0);
-- Normalise data
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "spi_master_transmit_and_receive() called with to wide data. " & v_cmd.msg);
if GC_MASTER_MODE then
spi_master_transmit_and_receive(tx_data => v_normalised_data,
rx_data => v_result,
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- Store the result
work.td_vvc_entity_support_pkg.store_result( result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_result );
else -- attempted master transmit and receive when in slave mode
alert(error, "Master transmit and receive called when VVC is in slave mode.", C_SCOPE);
end if;
when MASTER_TRANSMIT_AND_CHECK =>
transaction_info.tx_data(GC_DATA_WIDTH-1 downto 0) := v_cmd.data(GC_DATA_WIDTH-1 downto 0);
-- Normalise data
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "spi_master_transmit_and_check() called with to wide data. " & v_cmd.msg);
if GC_MASTER_MODE then
spi_master_transmit_and_check(tx_data => v_normalised_data,
data_exp => v_cmd.data_exp(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
else -- attempted master transmit and receive when in slave mode
alert(error, "Master transmit and check called when VVC is in slave mode.", C_SCOPE);
end if;
when MASTER_TRANSMIT_ONLY =>
transaction_info.tx_data(GC_DATA_WIDTH-1 downto 0) := v_cmd.data(GC_DATA_WIDTH-1 downto 0);
-- Normalise data
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "spi_master_transmit() called with to wide data. " & v_cmd.msg);
if GC_MASTER_MODE then -- master transmit
-- Call the corresponding procedure in the BFM package.
spi_master_transmit(tx_data => v_normalised_data,
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
else -- attempted master transmit when in slave mode
alert(error, "Master transmit called when VVC is in slave mode.", C_SCOPE);
end if;
when MASTER_RECEIVE_ONLY =>
if GC_MASTER_MODE then -- master receive
-- Call the corresponding procedure in the BFM package.
spi_master_receive(rx_data => v_result(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- Store the result
work.td_vvc_entity_support_pkg.store_result(result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_result);
else -- attempted master receive when in slave mode
alert(error, "Master receive called when VVC is in slave mode.", C_SCOPE);
end if;
when MASTER_CHECK_ONLY =>
-- Normalise data
v_normalised_data := normalize_and_check(v_cmd.data_exp, v_normalised_data, ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", "spi_master_check() called with to wide data. " & v_cmd.msg);
if GC_MASTER_MODE then -- master check
-- Call the corresponding procedure in the BFM package.
spi_master_check(data_exp => v_normalised_data,
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
else -- attempted master check when in slave mode
alert(error, "Master check called when VVC is in slave mode.", C_SCOPE);
end if;
when SLAVE_TRANSMIT_AND_RECEIVE =>
transaction_info.tx_data(GC_DATA_WIDTH-1 downto 0) := v_cmd.data(GC_DATA_WIDTH-1 downto 0);
-- Normalise data
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "spi_slave_transmit_and_receive() called with to wide data. " & v_cmd.msg);
if not GC_MASTER_MODE then
spi_slave_transmit_and_receive(tx_data => v_normalised_data,
rx_data => v_result,
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- Store the result
work.td_vvc_entity_support_pkg.store_result( result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_result );
else -- attempted slave transmit when in master mode
alert(note, "Slave transmit and receive called when VVC is in master mode.", C_SCOPE);
end if;
when SLAVE_TRANSMIT_AND_CHECK =>
transaction_info.tx_data(GC_DATA_WIDTH-1 downto 0) := v_cmd.data(GC_DATA_WIDTH-1 downto 0);
-- Normalise data
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "spi_slave_transmit_and_check() called with to wide data. " & v_cmd.msg);
if not GC_MASTER_MODE then
spi_slave_transmit_and_check(tx_data => v_normalised_data,
data_exp => v_cmd.data_exp(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
else -- attempted slave transmit when in master mode
alert(error, "Slave transmit and check called when VVC is in master mode.", C_SCOPE);
end if;
when SLAVE_TRANSMIT_ONLY =>
transaction_info.tx_data(GC_DATA_WIDTH-1 downto 0) := v_cmd.data(GC_DATA_WIDTH-1 downto 0);
-- Normalise data
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "spi_slave_transmit() called with to wide data. " & v_cmd.msg);
if not GC_MASTER_MODE then -- slave transmit
-- Call the corresponding procedure in the BFM package.
spi_slave_transmit(tx_data => v_normalised_data,
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
else -- attempted slave transmit when in master mode
alert(error, "Slave transmit called when VVC is in master mode.", C_SCOPE);
end if;
when SLAVE_RECEIVE_ONLY =>
if not GC_MASTER_MODE then -- slave receive
-- Call the corresponding procedure in the BFM package.
spi_slave_receive(rx_data => v_result(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- Store the result
work.td_vvc_entity_support_pkg.store_result(result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_result);
else -- attempted slave receive when in master mode
alert(error, "Slave receive called when VVC is in master mode.", C_SCOPE);
end if;
when SLAVE_CHECK_ONLY =>
-- Normalise data
v_normalised_data := normalize_and_check(v_cmd.data_exp, v_normalised_data, ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", "spi_slave_check() called with to wide data. " & v_cmd.msg);
if not GC_MASTER_MODE then -- slave check
-- Call the corresponding procedure in the BFM package.
spi_slave_check(data_exp => v_normalised_data,
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
else -- attempted slave check when in master mode
alert(error, "Slave check called when VVC is in master mode.", C_SCOPE);
end if;
-- UVVM common operations
--===================================
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, vvc_config.msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait for v_cmd.delay;
else
-- Delay specified using integer
wait for v_cmd.gen_integer_array(0) * vvc_config.bfm_config.spi_bit_time;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
if v_command_is_bfm_access then
v_timestamp_end_of_last_bfm_access := now;
v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access;
if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and
((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then
alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " &
to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE);
end if;
end if;
-- Reset terminate flag if any occurred
if (terminate_current_cmd.is_active = '1') then
log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, vvc_config.msg_id_panel);
uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd);
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Reset the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
end loop;
end process;
--========================================================================================================================
--===============================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--===============================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--===============================================================================================
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
entity CalculateG is
generic
(
width : integer := 8
);
port
(
-- Difference0 : in std_logic_vector( width + 3 downto 0 );
-- Difference01 : in std_logic_vector( width + 3 downto 0 );
Difference0 : in std_logic_vector( width downto 0 );
Difference01 : in std_logic_vector( width downto 0 );
IHorizontal : in std_logic_vector( width downto 0 );
IVertical : in std_logic_vector( width downto 0 );
Difference7 : in std_logic_vector( width downto 0 );
DifferenceDver : in std_logic_vector( width + 2 downto 0 );
DifferenceDhor : in std_logic_vector( width + 2 downto 0 );
ElementG : out std_logic_vector( width downto 0 )
);
end CalculateG;
architecture Behavioral of CalculateG is
signal PosThreshold : std_logic_vector( 10 downto 0 ) := "01111111111"; -- 1023
begin
process( Difference0, Difference01, IHorizontal, IVertical, Difference7, DifferenceDver, DifferenceDhor )
begin
if( Difference0( width ) /= '1' ) and ( Difference0>= PosThreshold ) then
ElementG <= IHorizontal;
elsif( Difference01( width ) /= '1' ) and ( Difference01 >= PosThreshold ) then
ElementG <= IVertical;
elsif DifferenceDhor < DifferenceDver then
ElementG <= IHorizontal;
elsif DifferenceDhor > DifferenceDver then
ElementG <= IVertical;
else
ElementG <= Difference7;
end if;
end process;
end Behavioral;
|
-----------------------------------------------------------
--------- AUTOGENERATED FILE, DO NOT EDIT -----------------
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
entity MySyncAdder is port(
addClk_clk, addClk_reset_n: in std_ulogic;
isAdd: in std_ulogic; -- WIRE
useOldZ_asX: in std_ulogic; -- WIRE
useOldZ_asY: in std_ulogic; -- WIRE
xx: in u8; -- Latch
yy: in u8; -- Latch
zz: out u8 -- reg
);
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
entity MySyncLOP is port(
lopClk_clk, lopClk_reset_n: in std_ulogic;
oper: in u4; -- reg
rx: in u8; -- reg
ry: in u8; -- reg
xorMaskIdx: in unsigned(2 downto 0); -- reg
result: out u8; -- reg
lastAND: out u8 -- Latch
);
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
entity Example1 is port(
clk_clk, clk_reset_n: in std_ulogic;
in_ry: in u8; -- WIRE
outa: out u8; -- WIRE
outb: out u8 -- WIRE
);
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
--#------- MySyncAdder ------------------------------------
architecture rtl of MySyncAdder is
----- internal regs/wires/etc --------
signal dg_c_zz: u8;
signal dg_o_zz: u8;
begin
MyMainProcess: process (all)
variable srcX: u8;
variable srcY: u8;
begin
dg_c_zz <= dg_o_zz; -- reg preload
srcX := X"00"; -- local-var zero-init
srcY := X"00"; -- local-var zero-init
if (useOldZ_asX = '1') then
srcX := dg_o_zz;
else
srcX := yy;
end if;
if (useOldZ_asY = '1') then
srcY := dg_o_zz;
else
srcY := xx;
end if;
if (isAdd = '1') then
dg_c_zz <= (srcX + srcY);
else
dg_c_zz <= (srcX - srcY);
end if;
end process;
----[ sync clock pump for addClk ]------
process begin
wait until rising_edge(addClk_clk);
dg_o_zz <= dg_c_zz;
end process;
------[ output registers/wires/latches ] --------------
zz <= dg_o_zz;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
--#------- MySyncLOP ------------------------------------
architecture rtl of MySyncLOP is
signal ClockCounter: u32; -- reg
----- internal regs/wires/etc --------
signal dg_c_oper: u4;
signal dg_c_rx: u8;
signal dg_c_ry: u8;
signal dg_c_xorMaskIdx: unsigned(2 downto 0);
signal dg_c_result: u8;
signal dg_o_result: u8;
signal dg_l_lastAND: u8;
signal dg_c_ClockCounter: u32;
begin
calcResult: process (all)
variable xorRemap: unsigned(2 downto 0);
variable xorMask: u8;
variable tmpRes: u8;
begin
dg_c_result <= dg_o_result; -- reg preload
dg_l_lastAND <= dg_l_lastAND; -- latch preload
dg_c_ClockCounter <= ClockCounter; -- reg preload
xorRemap := "000"; -- local-var zero-init
xorMask := X"00"; -- local-var zero-init
tmpRes := X"00"; -- local-var zero-init
case xorMaskIdx is
when "000" => xorRemap := "011";
when "001" => xorRemap := "010";
when "010" => xorRemap := "001";
when "011" => xorRemap := "000";
when "100" => xorRemap := "010";
when others => xorRemap := "001";
end case;
case xorRemap is
when "000" => xorMask := X"FF";
when "001" => xorMask := X"11";
when "010" | "100" | "111" => xorMask := X"33";
when others => xorMask := X"00";
end case;
case oper is
when X"0" =>
tmpRes := (rx and ry);
dg_l_lastAND <= tmpRes;
when X"1" =>
tmpRes := (rx or ry);
when X"2" =>
tmpRes := (rx xor ry);
when X"3" =>
tmpRes := (not (rx or ry));
when others => null;
end case;
dg_c_result <= (tmpRes xor xorMask);
dg_c_ClockCounter <= ClockCounter + X"00000001";
end process;
----[ sync clock pump for lopClk ]------
process begin
wait until rising_edge(lopClk_clk);
dg_o_result <= dg_c_result;
ClockCounter <= dg_c_ClockCounter;
if lopClk_reset_n = '0' then
dg_o_result <= X"99";
ClockCounter <= X"00000100";
end if;
end process;
------[ output registers/wires/latches ] --------------
result <= dg_o_result;
lastAND <= dg_l_lastAND;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
--#------- Example1 ------------------------------------
architecture rtl of Example1 is
type MyFSM is (
MyFSM_init,
MyFSM_adding,
MyFSM_add_oldx,
MyFSM_add_oldy,
MyFSM_lopping);
signal fsm: MyFSM; -- reg
signal count: u8; -- reg
----- internal regs/wires/etc --------
signal dg_w_outa: u8;
signal dg_w_outb: u8;
signal dg_c_fsm: MyFSM;
signal dg_c_count: u8;
----- unit signals -------------
signal adder_isAdd : std_ulogic;
signal adder_useOldZ_asX : std_ulogic;
signal adder_useOldZ_asY : std_ulogic;
signal adder_xx : u8;
signal adder_yy : u8;
signal adder_zz : u8;
signal lop_oper : u4;
signal dg_c_lop_oper : u4;
signal lop_rx : u8;
signal dg_c_lop_rx : u8;
signal lop_ry : u8;
signal dg_c_lop_ry : u8;
signal lop_xorMaskIdx : unsigned(2 downto 0);
signal dg_c_lop_xorMaskIdx : unsigned(2 downto 0);
signal lop_result : u8;
signal lop_lastAND : u8;
signal lop_lopClk_clk, lop_lopClk_reset_n : std_ulogic;
function ChooseLOPOperation (counter : u8) return u4 is
variable result: u4;
begin
result := X"0"; -- local-var zero-init
case counter(1 downto 0) is
when "00" => result := X"1";
when "01" => result := X"2";
when "10" => result := X"3";
when others => result := X"0";
end case;
return result;
end;
begin
dg_comb_proc1: process (all)
begin
dg_w_outa <= X"00"; -- wire pre-zero-init
dg_w_outb <= X"00"; -- wire pre-zero-init
dg_w_outa <= adder_zz;
dg_w_outb <= (lop_result + lop_lastAND);
end process;
main: process (all)
variable resetCount: std_ulogic;
begin
dg_c_fsm <= fsm; -- reg preload
dg_c_count <= count; -- reg preload
adder_isAdd <= '0'; -- wire pre-zero-init
adder_useOldZ_asX <= '0'; -- wire pre-zero-init
adder_useOldZ_asY <= '0'; -- wire pre-zero-init
adder_xx <= adder_xx; -- latch preload
adder_yy <= adder_yy; -- latch preload
dg_c_lop_oper <= lop_oper; -- reg preload
dg_c_lop_rx <= lop_rx; -- reg preload
dg_c_lop_xorMaskIdx <= lop_xorMaskIdx; -- reg preload
resetCount := '0'; -- local-var zero-init
case fsm is
when MyFSM_init =>
dg_c_fsm <= MyFSM_adding;
resetCount := '1';
adder_yy <= in_ry;
when MyFSM_adding =>
adder_isAdd <= '1';
adder_xx <= count;
if (dg_boolToBit(count = X"05") = '1') then
dg_c_fsm <= MyFSM_add_oldx;
resetCount := '1';
end if;
when MyFSM_add_oldx =>
adder_useOldZ_asX <= '1';
if (dg_boolToBit(count = X"03") = '1') then
dg_c_fsm <= MyFSM_add_oldy;
resetCount := '1';
end if;
when MyFSM_add_oldy =>
adder_useOldZ_asY <= '1';
adder_xx <= count;
dg_c_fsm <= MyFSM_lopping;
resetCount := '1';
when MyFSM_lopping =>
dg_c_lop_oper <= ChooseLOPOperation(count);
dg_c_lop_rx <= lop_rx + X"01";
dg_c_lop_xorMaskIdx <= lop_xorMaskIdx - "001";
when others => null;
end case;
if ((not clk_reset_n) = '1') then
dg_c_lop_oper <= X"2";
end if;
if (resetCount = '1') then
dg_c_count <= X"00";
else
dg_c_count <= (count + 1);
end if;
end process;
-------[ sub-units ]-----------
adder : entity work.MySyncAdder port map(
addClk_clk => clk_clk,
addClk_reset_n => clk_reset_n,
isAdd => adder_isAdd,
useOldZ_asX => adder_useOldZ_asX,
useOldZ_asY => adder_useOldZ_asY,
xx => adder_xx,
yy => adder_yy,
zz => adder_zz
);
lop : entity work.MySyncLOP port map(
lopClk_clk => lop_lopClk_clk,
lopClk_reset_n => lop_lopClk_reset_n,
oper => lop_oper,
rx => lop_rx,
ry => lop_ry,
xorMaskIdx => lop_xorMaskIdx,
result => lop_result,
lastAND => lop_lastAND
);
-------[ links ]----------
lop_lopClk_clk <= clk_clk;
lop_lopClk_reset_n <= clk_reset_n;
----[ sync clock pump for clk ]------
process begin
wait until rising_edge(clk_clk);
fsm <= dg_c_fsm;
count <= dg_c_count;
lop_oper <= dg_c_lop_oper;
lop_rx <= dg_c_lop_rx;
lop_ry <= dg_c_lop_ry;
lop_xorMaskIdx <= dg_c_lop_xorMaskIdx;
if clk_reset_n = '0' then
fsm <= MyFSM_init;
end if;
end process;
------[ output registers/wires/latches ] --------------
outa <= dg_w_outa;
outb <= dg_w_outb;
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity ula_tb is
end ula_tb;
architecture ula_tb of ula_tb is
signal ma, mb, ms: std_logic_vector(63 downto 0);
signal mw, mx, my, mz, mcout, mclk, mdo_op, mdone, mst: std_logic;
begin
vector: entity work.ula
port map (
a => ma,
b => mb,
s => ms,
x => mx,
y => my,
z => mz,
clk => mclk,
do_op => mdo_op,
done => mdone,
state => mst,
couterro => mcout
);
process
begin
ma <= "0011111111111110000000000000101000111111111111100000000000001010";
mb <= "0011111101010110101010010011101000111111111111100000000000000010";
mw <= '0';
mx <= '0';
my <= '0';
mz <= '0';
wait for 50 ns;
mx <= '0';
my <= '0';
mz <= '1';
wait for 50 ns;
mx <= '0';
my <= '1';
mz <= '0';
wait for 50 ns;
mx <= '0';
my <= '1';
mz <= '1';
wait for 50 ns;
mx <= '1';
my <= '0';
mz <= '0';
wait for 50 ns;
mx <= '1';
my <= '0';
mz <= '1';
wait for 50 ns;
mx <= '1';
my <= '1';
mz <= '0';
wait for 50 ns;
mx <= '1';
my <= '1';
mz <= '1';
wait for 50 ns;
wait;
end process;
end ula_tb;
|
-- NEED RESULT: ARCH00582: Attribute declarations - scalar static subtypes with dynamic initial values passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00582
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.4 (3)
-- 4.4 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00582)
-- ENT00582_Test_Bench(ARCH00582_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00582 of E00000 is
attribute at_boolean_1 : boolean ;
attribute at_bit_1 : bit ;
attribute at_severity_level_1 : severity_level ;
attribute at_character_1 : character ;
attribute at_t_enum1_1 : t_enum1 ;
attribute at_st_enum1_1 : st_enum1 ;
attribute at_integer_1 : integer ;
attribute at_t_int1_1 : t_int1 ;
attribute at_st_int1_1 : st_int1 ;
attribute at_time_1 : time ;
attribute at_t_phys1_1 : t_phys1 ;
attribute at_st_phys1_1 : st_phys1 ;
attribute at_real_1 : real ;
attribute at_t_real1_1 : t_real1 ;
attribute at_st_real1_1 : st_real1 ;
procedure p2
(
i_boolean_1, i_boolean_2 : boolean
:= c_boolean_1 ;
i_bit_1, i_bit_2 : bit
:= c_bit_1 ;
i_severity_level_1, i_severity_level_2 : severity_level
:= c_severity_level_1 ;
i_character_1, i_character_2 : character
:= c_character_1 ;
i_t_enum1_1, i_t_enum1_2 : t_enum1
:= c_t_enum1_1 ;
i_st_enum1_1, i_st_enum1_2 : st_enum1
:= c_st_enum1_1 ;
i_integer_1, i_integer_2 : integer
:= c_integer_1 ;
i_t_int1_1, i_t_int1_2 : t_int1
:= c_t_int1_1 ;
i_st_int1_1, i_st_int1_2 : st_int1
:= c_st_int1_1 ;
i_time_1, i_time_2 : time
:= c_time_1 ;
i_t_phys1_1, i_t_phys1_2 : t_phys1
:= c_t_phys1_1 ;
i_st_phys1_1, i_st_phys1_2 : st_phys1
:= c_st_phys1_1 ;
i_real_1, i_real_2 : real
:= c_real_1 ;
i_t_real1_1, i_t_real1_2 : t_real1
:= c_t_real1_1 ;
i_st_real1_1, i_st_real1_2 : st_real1
:= c_st_real1_1
) is
procedure p1 ;
attribute at_boolean_1 of p1 : procedure is
i_boolean_1 ;
attribute at_bit_1 of p1 : procedure is
i_bit_1 ;
attribute at_severity_level_1 of p1 : procedure is
i_severity_level_1 ;
attribute at_character_1 of p1 : procedure is
i_character_1 ;
attribute at_t_enum1_1 of p1 : procedure is
i_t_enum1_1 ;
attribute at_st_enum1_1 of p1 : procedure is
i_st_enum1_1 ;
attribute at_integer_1 of p1 : procedure is
i_integer_1 ;
attribute at_t_int1_1 of p1 : procedure is
i_t_int1_1 ;
attribute at_st_int1_1 of p1 : procedure is
i_st_int1_1 ;
attribute at_time_1 of p1 : procedure is
i_time_1 ;
attribute at_t_phys1_1 of p1 : procedure is
i_t_phys1_1 ;
attribute at_st_phys1_1 of p1 : procedure is
i_st_phys1_1 ;
attribute at_real_1 of p1 : procedure is
i_real_1 ;
attribute at_t_real1_1 of p1 : procedure is
i_t_real1_1 ;
attribute at_st_real1_1 of p1 : procedure is
i_st_real1_1 ;
procedure p1 is
variable correct : boolean := true ;
begin
correct := correct and p1'at_boolean_1
= c_boolean_1 ;
correct := correct and p1'at_bit_1
= c_bit_1 ;
correct := correct and p1'at_severity_level_1
= c_severity_level_1 ;
correct := correct and p1'at_character_1
= c_character_1 ;
correct := correct and p1'at_t_enum1_1
= c_t_enum1_1 ;
correct := correct and p1'at_st_enum1_1
= c_st_enum1_1 ;
correct := correct and p1'at_integer_1
= c_integer_1 ;
correct := correct and p1'at_t_int1_1
= c_t_int1_1 ;
correct := correct and p1'at_st_int1_1
= c_st_int1_1 ;
correct := correct and p1'at_time_1
= c_time_1 ;
correct := correct and p1'at_t_phys1_1
= c_t_phys1_1 ;
correct := correct and p1'at_st_phys1_1
= c_st_phys1_1 ;
correct := correct and p1'at_real_1
= c_real_1 ;
correct := correct and p1'at_t_real1_1
= c_t_real1_1 ;
correct := correct and p1'at_st_real1_1
= c_st_real1_1 ;
test_report ( "ARCH00582" ,
"Attribute declarations - scalar static subtypes"
& " with dynamic initial values" ,
correct) ;
end p1 ;
begin
p1 ;
end p2 ;
begin
process
begin
p2 ;
wait ;
end process ;
end ARCH00582 ;
--
entity ENT00582_Test_Bench is
end ENT00582_Test_Bench ;
--
architecture ARCH00582_Test_Bench of ENT00582_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00582 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00582_Test_Bench ;
|
library IEEE;
use IEEE.std_logic_1164.ALL;
entity static is
port(
clk_5hz : in std_logic;
clk_2hz : in std_logic;
clk_1hz : in std_logic;
leds : out std_logic_vector(2 downto 0)
);
end static;
architecture Behavioral of static is
begin
leds(0) <= clk_1hz;
leds(1) <= clk_2hz;
leds(2) <= clk_5hz;
end Behavioral;
|
----------------- structrual_HA -----------------------
-------------- Library statements -------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity declaration half_adder--
entity structural is
port (a, b : in std_logic;
sum, carry : out std_logic
);
end structural;
-- architecture structrual --
architecture struct of structural is
begin
u1: entity work.and_2 port map(a ,b , carry);
u2: entity work.xor_2 port map(a, b, sum);
end struct; |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity tb_05_06 is
end entity tb_05_06;
architecture test of tb_05_06 is
signal s, r : bit := '0';
signal q, q_n : bit;
begin
dut : entity work.S_R_flipflop(functional)
port map ( s => s, r => r, q => q, q_n => q_n );
stimulus : process is
begin
wait for 10 ns;
s <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '1'; wait for 10 ns;
r <= '0'; wait for 10 ns;
s <= '1'; wait for 10 ns;
r <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '0'; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity tb_05_06 is
end entity tb_05_06;
architecture test of tb_05_06 is
signal s, r : bit := '0';
signal q, q_n : bit;
begin
dut : entity work.S_R_flipflop(functional)
port map ( s => s, r => r, q => q, q_n => q_n );
stimulus : process is
begin
wait for 10 ns;
s <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '1'; wait for 10 ns;
r <= '0'; wait for 10 ns;
s <= '1'; wait for 10 ns;
r <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '0'; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity tb_05_06 is
end entity tb_05_06;
architecture test of tb_05_06 is
signal s, r : bit := '0';
signal q, q_n : bit;
begin
dut : entity work.S_R_flipflop(functional)
port map ( s => s, r => r, q => q, q_n => q_n );
stimulus : process is
begin
wait for 10 ns;
s <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '1'; wait for 10 ns;
r <= '0'; wait for 10 ns;
s <= '1'; wait for 10 ns;
r <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '0'; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
use work.uart_bfm_pkg.all;
use work.transaction_pkg.all;
--=================================================================================================
entity uart_vvc is
generic (
GC_DATA_WIDTH : natural := 8;
GC_INSTANCE_IDX : natural := 1;
GC_UART_CONFIG : t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING
);
port (
uart_vvc_rx : in std_logic;
uart_vvc_tx : inout std_logic
);
end entity uart_vvc;
--=================================================================================================
--=================================================================================================
architecture struct of uart_vvc is
begin
-- UART RX VVC
i1_uart_rx: entity work.uart_rx_vvc
generic map(
GC_DATA_WIDTH => GC_DATA_WIDTH,
GC_INSTANCE_IDX => GC_INSTANCE_IDX,
GC_CHANNEL => RX,
GC_UART_CONFIG => GC_UART_CONFIG,
GC_CMD_QUEUE_COUNT_MAX => GC_CMD_QUEUE_COUNT_MAX,
GC_CMD_QUEUE_COUNT_THRESHOLD => GC_CMD_QUEUE_COUNT_THRESHOLD,
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY => GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY
)
port map(
uart_vvc_rx => uart_vvc_rx
);
-- UART TX VVC
i1_uart_tx: entity work.uart_tx_vvc
generic map(
GC_DATA_WIDTH => GC_DATA_WIDTH,
GC_INSTANCE_IDX => GC_INSTANCE_IDX,
GC_CHANNEL => TX,
GC_UART_CONFIG => GC_UART_CONFIG,
GC_CMD_QUEUE_COUNT_MAX => GC_CMD_QUEUE_COUNT_MAX,
GC_CMD_QUEUE_COUNT_THRESHOLD => GC_CMD_QUEUE_COUNT_THRESHOLD,
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY => GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY
)
port map(
uart_vvc_tx => uart_vvc_tx
);
end struct;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config is
-- generate trace output or not.
constant Generate_Trace : boolean := true;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 22;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
-- Stack size
constant stackSize_bits: integer := 13;
constant Undefined: std_logic :='0';
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := true;
end zpu_config;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config is
-- generate trace output or not.
constant Generate_Trace : boolean := true;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 22;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
-- Stack size
constant stackSize_bits: integer := 13;
constant Undefined: std_logic :='0';
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := true;
end zpu_config;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config is
-- generate trace output or not.
constant Generate_Trace : boolean := true;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 22;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
-- Stack size
constant stackSize_bits: integer := 13;
constant Undefined: std_logic :='0';
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := true;
end zpu_config;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config is
-- generate trace output or not.
constant Generate_Trace : boolean := true;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 22;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
-- Stack size
constant stackSize_bits: integer := 13;
constant Undefined: std_logic :='0';
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := true;
end zpu_config;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config is
-- generate trace output or not.
constant Generate_Trace : boolean := true;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 22;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
-- Stack size
constant stackSize_bits: integer := 13;
constant Undefined: std_logic :='0';
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := true;
end zpu_config;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config is
-- generate trace output or not.
constant Generate_Trace : boolean := true;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 22;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
-- Stack size
constant stackSize_bits: integer := 13;
constant Undefined: std_logic :='0';
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := true;
end zpu_config;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config is
-- generate trace output or not.
constant Generate_Trace : boolean := true;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 22;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
-- Stack size
constant stackSize_bits: integer := 13;
constant Undefined: std_logic :='0';
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := true;
end zpu_config;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config is
-- generate trace output or not.
constant Generate_Trace : boolean := true;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 22;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
-- Stack size
constant stackSize_bits: integer := 13;
constant Undefined: std_logic :='0';
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := true;
end zpu_config;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config is
-- generate trace output or not.
constant Generate_Trace : boolean := true;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 22;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
-- Stack size
constant stackSize_bits: integer := 13;
constant Undefined: std_logic :='0';
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := true;
end zpu_config;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config is
-- generate trace output or not.
constant Generate_Trace : boolean := true;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 22;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
-- Stack size
constant stackSize_bits: integer := 13;
constant Undefined: std_logic :='0';
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := true;
end zpu_config;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config is
-- generate trace output or not.
constant Generate_Trace : boolean := true;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 22;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
-- Stack size
constant stackSize_bits: integer := 13;
constant Undefined: std_logic :='0';
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := true;
end zpu_config;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config is
-- generate trace output or not.
constant Generate_Trace : boolean := true;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 22;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
-- Stack size
constant stackSize_bits: integer := 13;
constant Undefined: std_logic :='0';
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := true;
end zpu_config;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config is
-- generate trace output or not.
constant Generate_Trace : boolean := true;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 22;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
-- Stack size
constant stackSize_bits: integer := 13;
constant Undefined: std_logic :='0';
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := true;
end zpu_config;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config is
-- generate trace output or not.
constant Generate_Trace : boolean := true;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 22;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
-- Stack size
constant stackSize_bits: integer := 13;
constant Undefined: std_logic :='0';
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := true;
end zpu_config;
|
-------------------------------------------------------------------------------
-- Title : Block-level Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
-- Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
-- File : v6_emac_v1_4_block.vhd
-- Version : 1.4
-------------------------------------------------------------------------------
--
-- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Description: This is the block-level wrapper for the Virtex-6 Embedded
-- Tri-Mode Ethernet MAC. It is intended that this example design
-- can be quickly adapted and downloaded onto an FPGA to provide
-- a hardware test environment.
--
-- The block-level wrapper:
--
-- * instantiates appropriate PHY interface modules (GMII, MII,
-- RGMII, SGMII or 1000BASE-X) as required per the user
-- configuration;
--
-- * instantiates some clocking and reset resources to operate
-- the EMAC and its example design.
--
-- Please refer to the Datasheet, Getting Started Guide, and
-- the Virtex-6 Embedded Tri-Mode Ethernet MAC User Gude for
-- further information.
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Entity declaration for the block-level wrapper
-------------------------------------------------------------------------------
entity v6_emac_v1_4_block is
port(
-- 125MHz clock output from transceiver
CLK125_OUT : out std_logic;
-- 125MHz clock input from BUFG
CLK125 : in std_logic;
-- Client receiver interface
EMACCLIENTRXD : out std_logic_vector(7 downto 0);
EMACCLIENTRXDVLD : out std_logic;
EMACCLIENTRXGOODFRAME : out std_logic;
EMACCLIENTRXBADFRAME : out std_logic;
EMACCLIENTRXFRAMEDROP : out std_logic;
EMACCLIENTRXSTATS : out std_logic_vector(6 downto 0);
EMACCLIENTRXSTATSVLD : out std_logic;
EMACCLIENTRXSTATSBYTEVLD : out std_logic;
-- Client transmitter interface
CLIENTEMACTXD : in std_logic_vector(7 downto 0);
CLIENTEMACTXDVLD : in std_logic;
EMACCLIENTTXACK : out std_logic;
CLIENTEMACTXFIRSTBYTE : in std_logic;
CLIENTEMACTXUNDERRUN : in std_logic;
EMACCLIENTTXCOLLISION : out std_logic;
EMACCLIENTTXRETRANSMIT : out std_logic;
CLIENTEMACTXIFGDELAY : in std_logic_vector(7 downto 0);
EMACCLIENTTXSTATS : out std_logic;
EMACCLIENTTXSTATSVLD : out std_logic;
EMACCLIENTTXSTATSBYTEVLD : out std_logic;
-- MAC control interface
CLIENTEMACPAUSEREQ : in std_logic;
CLIENTEMACPAUSEVAL : in std_logic_vector(15 downto 0);
-- EMAC-transceiver link status
EMACCLIENTSYNCACQSTATUS : out std_logic;
-- Auto-Negotiation interrupt
EMACANINTERRUPT : out std_logic;
-- SGMII interface
TXP : out std_logic;
TXN : out std_logic;
RXP : in std_logic;
RXN : in std_logic;
PHYAD : in std_logic_vector(4 downto 0);
RESETDONE : out std_logic;
-- SGMII transceiver clock buffer input
CLK_DS : in std_logic;
-- Asynchronous reset
RESET : in std_logic
);
end v6_emac_v1_4_block;
architecture TOP_LEVEL of v6_emac_v1_4_block is
-------------------------------------------------------------------------------
-- Component declarations for lower hierarchial level entities
-------------------------------------------------------------------------------
-- Component declaration for the primitive-level EMAC wrapper
component v6_emac_v1_4 is
port(
-- Client receiver interface
EMACCLIENTRXCLIENTCLKOUT : out std_logic;
CLIENTEMACRXCLIENTCLKIN : in std_logic;
EMACCLIENTRXD : out std_logic_vector(7 downto 0);
EMACCLIENTRXDVLD : out std_logic;
EMACCLIENTRXDVLDMSW : out std_logic;
EMACCLIENTRXGOODFRAME : out std_logic;
EMACCLIENTRXBADFRAME : out std_logic;
EMACCLIENTRXFRAMEDROP : out std_logic;
EMACCLIENTRXSTATS : out std_logic_vector(6 downto 0);
EMACCLIENTRXSTATSVLD : out std_logic;
EMACCLIENTRXSTATSBYTEVLD : out std_logic;
-- Client transmitter interface
EMACCLIENTTXCLIENTCLKOUT : out std_logic;
CLIENTEMACTXCLIENTCLKIN : in std_logic;
CLIENTEMACTXD : in std_logic_vector(7 downto 0);
CLIENTEMACTXDVLD : in std_logic;
CLIENTEMACTXDVLDMSW : in std_logic;
EMACCLIENTTXACK : out std_logic;
CLIENTEMACTXFIRSTBYTE : in std_logic;
CLIENTEMACTXUNDERRUN : in std_logic;
EMACCLIENTTXCOLLISION : out std_logic;
EMACCLIENTTXRETRANSMIT : out std_logic;
CLIENTEMACTXIFGDELAY : in std_logic_vector(7 downto 0);
EMACCLIENTTXSTATS : out std_logic;
EMACCLIENTTXSTATSVLD : out std_logic;
EMACCLIENTTXSTATSBYTEVLD : out std_logic;
-- MAC control interface
CLIENTEMACPAUSEREQ : in std_logic;
CLIENTEMACPAUSEVAL : in std_logic_vector(15 downto 0);
-- Clock signals
GTX_CLK : in std_logic;
PHYEMACTXGMIIMIICLKIN : in std_logic;
EMACPHYTXGMIIMIICLKOUT : out std_logic;
-- SGMII interface
RXDATA : in std_logic_vector(7 downto 0);
TXDATA : out std_logic_vector(7 downto 0);
MMCM_LOCKED : in std_logic;
AN_INTERRUPT : out std_logic;
SIGNAL_DETECT : in std_logic;
PHYAD : in std_logic_vector(4 downto 0);
ENCOMMAALIGN : out std_logic;
LOOPBACKMSB : out std_logic;
MGTRXRESET : out std_logic;
MGTTXRESET : out std_logic;
POWERDOWN : out std_logic;
SYNCACQSTATUS : out std_logic;
RXCLKCORCNT : in std_logic_vector(2 downto 0);
RXBUFSTATUS : in std_logic;
RXCHARISCOMMA : in std_logic;
RXCHARISK : in std_logic;
RXDISPERR : in std_logic;
RXNOTINTABLE : in std_logic;
RXREALIGN : in std_logic;
RXRUNDISP : in std_logic;
TXBUFERR : in std_logic;
TXCHARDISPMODE : out std_logic;
TXCHARDISPVAL : out std_logic;
TXCHARISK : out std_logic;
-- Asynchronous reset
RESET : in std_logic
);
end component;
-- Component declaration for the GTX wrapper
component v6_gtxwizard_top
port (
RESETDONE : out std_logic;
ENMCOMMAALIGN : in std_logic;
ENPCOMMAALIGN : in std_logic;
LOOPBACK : in std_logic;
POWERDOWN : in std_logic;
RXUSRCLK2 : in std_logic;
RXRESET : in std_logic;
TXCHARDISPMODE : in std_logic;
TXCHARDISPVAL : in std_logic;
TXCHARISK : in std_logic;
TXDATA : in std_logic_vector (7 downto 0);
TXUSRCLK2 : in std_logic;
TXRESET : in std_logic;
RXCHARISCOMMA : out std_logic;
RXCHARISK : out std_logic;
RXCLKCORCNT : out std_logic_vector (2 downto 0);
RXDATA : out std_logic_vector (7 downto 0);
RXDISPERR : out std_logic;
RXNOTINTABLE : out std_logic;
RXRUNDISP : out std_logic;
RXBUFERR : out std_logic;
TXBUFERR : out std_logic;
PLLLKDET : out std_logic;
TXOUTCLK : out std_logic;
RXELECIDLE : out std_logic;
TXN : out std_logic;
TXP : out std_logic;
RXN : in std_logic;
RXP : in std_logic;
CLK_DS : in std_logic;
PMARESET : in std_logic
);
end component;
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
-- Power and ground signals
signal gnd_i : std_logic;
signal vcc_i : std_logic;
-- Asynchronous reset signals
signal reset_ibuf_i : std_logic;
signal reset_i : std_logic;
signal reset_r : std_logic_vector(3 downto 0);
-- Client clocking signals
signal rx_client_clk_out_i : std_logic;
signal rx_client_clk_in_i : std_logic;
signal tx_client_clk_out_i : std_logic;
signal tx_client_clk_in_i : std_logic;
-- Physical interface signals
signal emac_locked_i : std_logic;
signal mgt_rx_data_i : std_logic_vector(7 downto 0);
signal mgt_tx_data_i : std_logic_vector(7 downto 0);
signal signal_detect_i : std_logic;
signal elecidle_i : std_logic;
signal resetdone_i : std_logic;
signal encommaalign_i : std_logic;
signal loopback_i : std_logic;
signal mgt_rx_reset_i : std_logic;
signal mgt_tx_reset_i : std_logic;
signal powerdown_i : std_logic;
signal rxclkcorcnt_i : std_logic_vector(2 downto 0);
signal rxchariscomma_i : std_logic;
signal rxcharisk_i : std_logic;
signal rxdisperr_i : std_logic;
signal rxnotintable_i : std_logic;
signal rxrundisp_i : std_logic;
signal txbuferr_i : std_logic;
signal txchardispmode_i : std_logic;
signal txchardispval_i : std_logic;
signal txcharisk_i : std_logic;
signal gtx_clk_ibufg_i : std_logic;
signal rxbufstatus_i : std_logic;
signal rxchariscomma_r : std_logic;
signal rxcharisk_r : std_logic;
signal rxclkcorcnt_r : std_logic_vector(2 downto 0);
signal mgt_rx_data_r : std_logic_vector(7 downto 0);
signal rxdisperr_r : std_logic;
signal rxnotintable_r : std_logic;
signal rxrundisp_r : std_logic;
signal txchardispmode_r : std_logic;
signal txchardispval_r : std_logic;
signal txcharisk_r : std_logic;
signal mgt_tx_data_r : std_logic_vector(7 downto 0);
-- Transceiver clocking signals
signal usrclk2 : std_logic;
signal txoutclk : std_logic;
signal plllock_i : std_logic;
-------------------------------------------------------------------------------
-- Attribute declarations
-------------------------------------------------------------------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of reset_r : signal is "TRUE";
-------------------------------------------------------------------------------
-- Main body of code
-------------------------------------------------------------------------------
begin
gnd_i <= '0';
vcc_i <= '1';
---------------------------------------------------------------------------
-- Main reset circuitry
---------------------------------------------------------------------------
reset_ibuf_i <= RESET;
-- Synchronize and extend the external reset signal
process(usrclk2, reset_ibuf_i)
begin
if (reset_ibuf_i = '1') then
reset_r <= "1111";
elsif usrclk2'event and usrclk2 = '1' then
if (plllock_i = '1') then
reset_r <= reset_r(2 downto 0) & reset_ibuf_i;
end if;
end if;
end process;
-- Apply the extended reset pulse to the EMAC
reset_i <= reset_r(3);
---------------------------------------------------------------------------
-- Instantiate GTX for SGMII or 1000BASE-X PCS/PMA physical interface
---------------------------------------------------------------------------
v6_gtxwizard_top_inst : v6_gtxwizard_top
PORT MAP (
RESETDONE => resetdone_i,
ENMCOMMAALIGN => encommaalign_i,
ENPCOMMAALIGN => encommaalign_i,
LOOPBACK => loopback_i,
POWERDOWN => powerdown_i,
RXUSRCLK2 => usrclk2,
RXRESET => mgt_rx_reset_i,
TXCHARDISPMODE => txchardispmode_r,
TXCHARDISPVAL => txchardispval_r,
TXCHARISK => txcharisk_r,
TXDATA => mgt_tx_data_r,
TXUSRCLK2 => usrclk2,
TXRESET => mgt_tx_reset_i,
RXCHARISCOMMA => rxchariscomma_i,
RXCHARISK => rxcharisk_i,
RXCLKCORCNT => rxclkcorcnt_i,
RXDATA => mgt_rx_data_i,
RXDISPERR => rxdisperr_i,
RXNOTINTABLE => rxnotintable_i,
RXRUNDISP => rxrundisp_i,
RXBUFERR => rxbufstatus_i,
TXBUFERR => txbuferr_i,
PLLLKDET => plllock_i,
TXOUTCLK => txoutclk,
RXELECIDLE => elecidle_i,
TXN => TXN,
TXP => TXP,
RXN => RXN,
RXP => RXP,
CLK_DS => CLK_DS,
PMARESET => reset_ibuf_i
);
RESETDONE <= resetdone_i;
--------------------------------------------------------------------------
-- Register the signals between EMAC and transceiver for timing purposes
--------------------------------------------------------------------------
regrx : process (usrclk2, reset_i)
begin
if reset_i = '1' then
rxchariscomma_r <= '0';
rxcharisk_r <= '0';
rxclkcorcnt_r <= (others => '0');
mgt_rx_data_r <= (others => '0');
rxdisperr_r <= '0';
rxnotintable_r <= '0';
rxrundisp_r <= '0';
txchardispmode_r <= '0';
txchardispval_r <= '0';
txcharisk_r <= '0';
mgt_tx_data_r <= (others => '0');
elsif usrclk2'event and usrclk2 = '1' then
rxchariscomma_r <= rxchariscomma_i;
rxcharisk_r <= rxcharisk_i;
rxclkcorcnt_r <= rxclkcorcnt_i;
mgt_rx_data_r <= mgt_rx_data_i;
rxdisperr_r <= rxdisperr_i;
rxnotintable_r <= rxnotintable_i;
rxrundisp_r <= rxrundisp_i;
txchardispmode_r <= txchardispmode_i after 1 ns;
txchardispval_r <= txchardispval_i after 1 ns;
txcharisk_r <= txcharisk_i after 1 ns;
mgt_tx_data_r <= mgt_tx_data_i after 1 ns;
end if;
end process regrx;
-- Detect when there has been a disconnect
signal_detect_i <= not(elecidle_i);
--------------------------------------------------------------------
-- GTX clock management
--------------------------------------------------------------------
-- 125MHz clock is used for GT user clocks and used
-- to clock all Ethernet core logic
usrclk2 <= CLK125;
-- GTX reference clock
gtx_clk_ibufg_i <= usrclk2;
-- PLL locks
emac_locked_i <= plllock_i;
-- SGMII client-side transmit clock
tx_client_clk_in_i <= usrclk2;
-- SGMII client-side receive clock
rx_client_clk_in_i <= usrclk2;
-- 125MHz clock output from transceiver
CLK125_OUT <= txoutclk;
--------------------------------------------------------------------------
-- Instantiate the primitive-level EMAC wrapper (v6_emac_v1_4.vhd)
--------------------------------------------------------------------------
v6_emac_v1_4_inst : v6_emac_v1_4
port map (
-- Client receiver interface
EMACCLIENTRXCLIENTCLKOUT => rx_client_clk_out_i,
CLIENTEMACRXCLIENTCLKIN => rx_client_clk_in_i,
EMACCLIENTRXD => EMACCLIENTRXD,
EMACCLIENTRXDVLD => EMACCLIENTRXDVLD,
EMACCLIENTRXDVLDMSW => open,
EMACCLIENTRXGOODFRAME => EMACCLIENTRXGOODFRAME,
EMACCLIENTRXBADFRAME => EMACCLIENTRXBADFRAME,
EMACCLIENTRXFRAMEDROP => EMACCLIENTRXFRAMEDROP,
EMACCLIENTRXSTATS => EMACCLIENTRXSTATS,
EMACCLIENTRXSTATSVLD => EMACCLIENTRXSTATSVLD,
EMACCLIENTRXSTATSBYTEVLD => EMACCLIENTRXSTATSBYTEVLD,
-- Client transmitter interface
EMACCLIENTTXCLIENTCLKOUT => tx_client_clk_out_i,
CLIENTEMACTXCLIENTCLKIN => tx_client_clk_in_i,
CLIENTEMACTXD => CLIENTEMACTXD,
CLIENTEMACTXDVLD => CLIENTEMACTXDVLD,
CLIENTEMACTXDVLDMSW => gnd_i,
EMACCLIENTTXACK => EMACCLIENTTXACK,
CLIENTEMACTXFIRSTBYTE => CLIENTEMACTXFIRSTBYTE,
CLIENTEMACTXUNDERRUN => CLIENTEMACTXUNDERRUN,
EMACCLIENTTXCOLLISION => EMACCLIENTTXCOLLISION,
EMACCLIENTTXRETRANSMIT => EMACCLIENTTXRETRANSMIT,
CLIENTEMACTXIFGDELAY => CLIENTEMACTXIFGDELAY,
EMACCLIENTTXSTATS => EMACCLIENTTXSTATS,
EMACCLIENTTXSTATSVLD => EMACCLIENTTXSTATSVLD,
EMACCLIENTTXSTATSBYTEVLD => EMACCLIENTTXSTATSBYTEVLD,
-- MAC control interface
CLIENTEMACPAUSEREQ => CLIENTEMACPAUSEREQ,
CLIENTEMACPAUSEVAL => CLIENTEMACPAUSEVAL,
-- Clock signals
GTX_CLK => usrclk2,
EMACPHYTXGMIIMIICLKOUT => open,
PHYEMACTXGMIIMIICLKIN => gnd_i,
-- SGMII interface
RXDATA => mgt_rx_data_r,
TXDATA => mgt_tx_data_i,
MMCM_LOCKED => emac_locked_i,
AN_INTERRUPT => EMACANINTERRUPT,
SIGNAL_DETECT => signal_detect_i,
PHYAD => PHYAD,
ENCOMMAALIGN => encommaalign_i,
LOOPBACKMSB => loopback_i,
MGTRXRESET => mgt_rx_reset_i,
MGTTXRESET => mgt_tx_reset_i,
POWERDOWN => powerdown_i,
SYNCACQSTATUS => EMACCLIENTSYNCACQSTATUS,
RXCLKCORCNT => rxclkcorcnt_r,
RXBUFSTATUS => rxbufstatus_i,
RXCHARISCOMMA => rxchariscomma_r,
RXCHARISK => rxcharisk_r,
RXDISPERR => rxdisperr_r,
RXNOTINTABLE => rxnotintable_r,
RXREALIGN => '0',
RXRUNDISP => rxrundisp_r,
TXBUFERR => txbuferr_i,
TXCHARDISPMODE => txchardispmode_i,
TXCHARDISPVAL => txchardispval_i,
TXCHARISK => txcharisk_i,
-- Asynchronous reset
RESET => reset_i
);
end TOP_LEVEL;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Simulation constants, functions and utilities.
--
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.physical.all;
package simulation is
-- predefined constants to ease testvector concatenation
constant U8 : T_SLV_8 := (others => 'U');
constant U16 : T_SLV_16 := (others => 'U');
constant U24 : T_SLV_24 := (others => 'U');
constant U32 : T_SLV_32 := (others => 'U');
constant D8 : T_SLV_8 := (others => '-');
constant D16 : T_SLV_16 := (others => '-');
constant D24 : T_SLV_24 := (others => '-');
constant D32 : T_SLV_32 := (others => '-');
-- Testbench Status Management
-- ===========================================================================
-- The testbench is marked as failed. If a message is provided, it is
-- reported as an error.
procedure tbFail(msg : in string := "");
-- If the passed condition has evaluated false, the testbench is marked
-- as failed. In this case, the optional message will be reported as an
-- error if one was provided.
procedure tbAssert(cond : in boolean; msg : in string := "");
-- Prints out the overall testbench result as defined by the automated
-- testbench process. Unless tbFail() or tbAssert() with a false condition
-- have been called before, a successful completion will be reported, a
-- failure otherwise.
procedure tbPrintResult;
-- clock generation
-- ===========================================================================
subtype T_DutyCycle is REAL range 0.0 to 1.0;
procedure simStop;
impure function simIsStopped return BOOLEAN;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5);
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5);
-- waveform generation
-- ===========================================================================
type T_SIM_WAVEFORM_TUPLE_SL is record
Delay : TIME;
Value : STD_LOGIC;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_8 is record
Delay : TIME;
Value : T_SLV_8;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_16 is record
Delay : TIME;
Value : T_SLV_16;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_24 is record
Delay : TIME;
Value : T_SLV_24;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_32 is record
Delay : TIME;
Value : T_SLV_32;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_48 is record
Delay : TIME;
Value : T_SLV_48;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_64 is record
Delay : TIME;
Value : T_SLV_64;
end record;
type T_SIM_WAVEFORM_SL is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SL;
type T_SIM_WAVEFORM_SLV_8 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8;
type T_SIM_WAVEFORM_SLV_16 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16;
type T_SIM_WAVEFORM_SLV_24 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24;
type T_SIM_WAVEFORM_SLV_32 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32;
type T_SIM_WAVEFORM_SLV_48 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48;
type T_SIM_WAVEFORM_SLV_64 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64;
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform: T_TIMEVEC; InitialValue : BOOLEAN);
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8);
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16);
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24);
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32);
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48);
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64);
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC;
-- TODO: integrate VCD simulation functions and procedures from sim_value_change_dump.vhdl here
-- checksum functions
-- ===========================================================================
-- TODO: move checksum functions here
end;
use std.TextIO.all;
package body simulation is
-- Testbench Status Management
-- ===========================================================================
-- Internal state variable to log a failure condition for final reporting.
-- Once de-asserted, this variable will never return to a value of true.
shared variable pass : boolean := true;
shared variable simStopped : BOOLEAN := FALSE;
procedure tbFail(msg : in string := "") is
begin
if (str_length(msg) > 0) then
report str_trim(msg) severity error;
end if;
pass := false;
end;
procedure tbAssert(cond : in boolean; msg : in string := "") is
begin
if not cond then
tbFail(msg);
end if;
end;
procedure tbPrintResult is
variable l : line;
begin
write(l, string'("SIMULATION RESULT = "));
if pass then
write(l, string'("PASSED"));
else
write(l, string'("FAILED"));
end if;
writeline(output, l);
end procedure;
-- clock generation
procedure simStop is
begin
simStopped := TRUE;
end procedure;
impure function simIsStopped return BOOLEAN is
begin
return simStopped;
end function;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5) is
constant Period : TIME := to_time(Frequency);
begin
simGenerateClock(Clock, Period, DutyCycle);
end procedure;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5) is
constant TIME_HIGH : TIME := Period * DutyCycle;
constant TIME_LOW : TIME := Period - TIME_HIGH;
begin
Clock <= '0';
while (not simStopped) loop
wait for TIME_LOW;
Clock <= '1';
wait for TIME_HIGH;
Clock <= '0';
end loop;
end procedure;
-- waveform generation
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform : T_TIMEVEC; InitialValue : BOOLEAN) is
variable State : BOOLEAN := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0') is
variable State : STD_LOGIC := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0') is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC is
begin
return (0 => Pause, 1 => ResetPulse);
end function;
-- checksum functions
-- ===========================================================================
-- TODO: move checksum functions here
end package body;
|
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