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---------------------------------------------------------------------------- ---- Create Date: 14:30:08 07/28/2010 ---- ---- Design Name: lfsr_pkg ---- ---- Project Name: lfsr_randgen ---- ---- Description: ---- ---- This is the package file used in the lfsr_randgen project.The ---- ---- package contain the function for XORing bits from various tap ---- ---- locations depending on the generic parameter(width of lfsr ) ---- ---- ---- ---------------------------------------------------------------------------- ---- ---- ---- This file is a part of the lfsr_randgen project at ---- ---- http://www.opencores.org/ ---- ---- ---- ---- Author(s): ---- ---- Vipin Lal, [email protected] ---- ---- ---- ---------------------------------------------------------------------------- ---- ---- ---- Copyright (C) 2010 Authors and OPENCORES.ORG ---- ---- ---- ---- This source file may be used and distributed without ---- ---- restriction provided that this copyright statement is not ---- ---- removed from the file and that any derivative work contains ---- ---- the original copyright notice and the associated disclaimer. ---- ---- ---- ---- This source file is free software; you can redistribute it ---- ---- and/or modify it under the terms of the GNU Lesser General ---- ---- Public License as published by the Free Software Foundation; ---- ---- either version 2.1 of the License, or (at your option) any ---- ---- later version. ---- ---- ---- ---- This source is distributed in the hope that it will be ---- ---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ---- PURPOSE. See the GNU Lesser General Public License for more ---- ---- details. ---- ---- ---- ---- You should have received a copy of the GNU Lesser General ---- ---- Public License along with this source; if not, download it ---- ---- from http://www.opencores.org/lgpl.shtml ---- ---- ---- ---------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; package lfsr_pkg is function xor_gates( random : std_logic_vector) return std_logic; end lfsr_pkg; --Package body starts from here. package body lfsr_pkg is --function for XORing from tap values. function xor_gates( random : std_logic_vector ) return std_logic is variable xor_out : std_logic:='0'; variable rand : std_logic_vector(random'length-1 downto 0):=random; begin if(rand'length = 3) then --3 xor_out := rand(2) xor rand(1); elsif(rand'length = 2) then --2 xor_out := rand(1) xor rand(0); elsif(rand'length = 4) then --4 xor_out := rand(3) xor rand(2); elsif(rand'length = 5) then --5 xor_out := rand(4) xor rand(2); elsif(rand'length = 6) then --6 xor_out := rand(5) xor rand(4); elsif(rand'length = 7) then --7 xor_out := rand(6) xor rand(5); elsif(rand'length = 8) then --8 xor_out := rand(7) xor rand(5) xor rand(4) xor rand(3); elsif(rand'length = 9) then --9 xor_out := rand(8) xor rand(4); elsif(rand'length = 10)then --10 xor_out := rand(9) xor rand(6); elsif(rand'length =11) then --11 xor_out := rand(10) xor rand(8); elsif(rand'length = 12) then --12 xor_out := rand(11) xor rand(5) xor rand(3) xor rand(0); elsif(rand'length = 13) then --13 xor_out := rand(12) xor rand(3) xor rand(2) xor rand(0); elsif(rand'length = 14) then --14 xor_out := rand(13) xor rand(4) xor rand(2) xor rand(0); elsif(rand'length = 15) then --15 xor_out := rand(14) xor rand(13); elsif(rand'length = 16) then --16 xor_out := rand(15) xor rand(14) xor rand(12) xor rand(3); elsif(rand'length = 17) then --17 xor_out := rand(16) xor rand(13); elsif(rand'length = 18) then --18 xor_out := rand(17) xor rand(10); elsif(rand'length = 19) then --19 xor_out := rand(18) xor rand(5) xor rand(1) xor rand(0); elsif(rand'length = 20) then --20 xor_out := rand(19) xor rand(16); elsif(rand'length = 21) then --21 xor_out := rand(20) xor rand(18); elsif(rand'length = 22) then --22 xor_out := rand(21) xor rand(20); elsif(rand'length = 23) then --23 xor_out := rand(22) xor rand(17); elsif(rand'length = 24) then --24 xor_out := rand(23) xor rand(22) xor rand(21) xor rand(16); elsif(rand'length = 25) then --25 xor_out := rand(24) xor rand(21); elsif(rand'length = 26) then --26 xor_out := rand(25) xor rand(5) xor rand(1) xor rand(0); elsif(rand'length = 27) then --27 xor_out := rand(26) xor rand(4) xor rand(1) xor rand(0); elsif(rand'length = 28) then --28 xor_out := rand(27) xor rand(24); elsif(rand'length = 29) then --29 xor_out := rand(28) xor rand(26); elsif(rand'length = 30) then --30 xor_out := rand(29) xor rand(5) xor rand(3) xor rand(0); elsif(rand'length = 31) then --31 xor_out := rand(30) xor rand(27); elsif(rand'length = 32) then --32 xor_out := rand(31) xor rand(21) xor rand(1) xor rand(0); elsif(rand'length = 33) then --33 xor_out := rand(32) xor rand(19); elsif(rand'length = 34) then --34 xor_out := rand(33) xor rand(26) xor rand(1) xor rand(0); elsif(rand'length = 35) then --35 xor_out := rand(34) xor rand(32); elsif(rand'length = 36) then --36 xor_out := rand(35) xor rand(24); elsif(rand'length = 37) then --37 xor_out := rand(36) xor rand(4) xor rand(3) xor rand(2) xor rand(1) xor rand(0); elsif(rand'length = 38) then --38 xor_out := rand(37) xor rand(5) xor rand(4) xor rand(0); elsif(rand'length = 39) then --39 xor_out := rand(38) xor rand(34); elsif(rand'length = 40) then --40 xor_out := rand(39) xor rand(37) xor rand(20) xor rand(18); elsif(rand'length = 41) then --41 xor_out := rand(40) xor rand(37); elsif(rand'length = 42) then --42 xor_out := rand(41) xor rand(40) xor rand(19) xor rand(18); elsif(rand'length = 43) then --43 xor_out := rand(42) xor rand(41) xor rand(37) xor rand(36); elsif(rand'length = 44) then --44 xor_out := rand(43) xor rand(42) xor rand(17) xor rand(16); elsif(rand'length = 45) then --45 xor_out := rand(44) xor rand(43) xor rand(41) xor rand(40); elsif(rand'length = 46) then --46 xor_out := rand(45) xor rand(44) xor rand(25) xor rand(24); elsif(rand'length = 47) then --47 xor_out := rand(46) xor rand(41); elsif(rand'length = 48) then --48 xor_out := rand(47) xor rand(46) xor rand(20) xor rand(19); elsif(rand'length = 49) then --49 xor_out := rand(48) xor rand(39); elsif(rand'length = 50) then --50 xor_out := rand(49) xor rand(48) xor rand(23) xor rand(22); elsif(rand'length = 51) then --51 xor_out := rand(50) xor rand(49) xor rand(35) xor rand(34); elsif(rand'length = 52) then --52 xor_out := rand(51) xor rand(48); elsif(rand'length = 53) then --53 xor_out := rand(52) xor rand(51) xor rand(37) xor rand(36); elsif(rand'length = 54) then --54 xor_out := rand(53) xor rand(52) xor rand(17) xor rand(16); elsif(rand'length = 55) then --55 xor_out := rand(54) xor rand(30); elsif(rand'length = 56) then --56 xor_out := rand(55) xor rand(54) xor rand(34) xor rand(33); elsif(rand'length = 57) then --57 xor_out := rand(56) xor rand(49); elsif(rand'length = 58) then --58 xor_out := rand(57) xor rand(38); elsif(rand'length = 59) then --59 xor_out := rand(58) xor rand(57) xor rand(37) xor rand(36); elsif(rand'length = 60) then --60 xor_out := rand(59) xor rand(58); elsif(rand'length = 61) then --61 xor_out := rand(60) xor rand(59) xor rand(45) xor rand(44); elsif(rand'length = 62) then --62 xor_out := rand(61) xor rand(60) xor rand(5) xor rand(4); elsif(rand'length = 63) then --63 xor_out := rand(62) xor rand(61); elsif(rand'length = 64) then --64 xor_out := rand(63) xor rand(62) xor rand(60) xor rand(59); elsif(rand'length = 65) then --65 xor_out := rand(64) xor rand(46); elsif(rand'length = 66) then --66 xor_out := rand(65) xor rand(64) xor rand(56) xor rand(55); elsif(rand'length = 67) then --67 xor_out := rand(66) xor rand(65) xor rand(57) xor rand(56); elsif(rand'length = 68) then --68 xor_out := rand(67) xor rand(58); elsif(rand'length = 69) then --69 xor_out := rand(68) xor rand(66) xor rand(41) xor rand(39); elsif(rand'length = 70) then --70 xor_out := rand(69) xor rand(68) xor rand(54) xor rand(53); elsif(rand'length = 71) then --71 xor_out := rand(70) xor rand(64); elsif(rand'length = 72) then --72 xor_out := rand(71) xor rand(65) xor rand(24) xor rand(18); elsif(rand'length = 73) then --73 xor_out := rand(72) xor rand(47); elsif(rand'length = 74) then --74 xor_out := rand(73) xor rand(72) xor rand(58) xor rand(57); elsif(rand'length = 75) then --75 xor_out := rand(74) xor rand(73) xor rand(64) xor rand(63); elsif(rand'length = 76) then --76 xor_out := rand(75) xor rand(74) xor rand(40) xor rand(39); elsif(rand'length = 77) then --77 xor_out := rand(76) xor rand(75) xor rand(46) xor rand(45); elsif(rand'length = 78) then --78 xor_out := rand(77) xor rand(76) xor rand(58) xor rand(57); elsif(rand'length = 79) then --79 xor_out := rand(78) xor rand(69); elsif(rand'length = 80) then --80 xor_out := rand(79) xor rand(78) xor rand(42) xor rand(41); elsif(rand'length = 81) then --81 xor_out := rand(80) xor rand(76); elsif(rand'length = 82) then --82 xor_out := rand(81) xor rand(78) xor rand(46) xor rand(43); elsif(rand'length = 83) then --83 xor_out := rand(82) xor rand(81) xor rand(37) xor rand(36); elsif(rand'length = 84) then --84 xor_out := rand(83) xor rand(70); elsif(rand'length = 85) then --85 xor_out := rand(84) xor rand(83) xor rand(57) xor rand(56); elsif(rand'length = 86) then --86 xor_out := rand(85) xor rand(84) xor rand(73) xor rand(72); elsif(rand'length = 87) then --87 xor_out := rand(86) xor rand(73); elsif(rand'length = 88) then --88 xor_out := rand(87) xor rand(86) xor rand(16) xor rand(15); elsif(rand'length = 89) then --89 xor_out := rand(88) xor rand(50); elsif(rand'length = 90) then --90 xor_out := rand(89) xor rand(88) xor rand(71) xor rand(70); elsif(rand'length = 91) then --91 xor_out := rand(90) xor rand(89) xor rand(7) xor rand(6); elsif(rand'length = 92) then --92 xor_out := rand(91) xor rand(90) xor rand(79) xor rand(78); elsif(rand'length = 93) then --93 xor_out := rand(92) xor rand(90); elsif(rand'length = 94) then --94 xor_out := rand(93) xor rand(72); elsif(rand'length = 95) then --95 xor_out := rand(94) xor rand(83); elsif(rand'length = 96) then --96 xor_out := rand(95) xor rand(93) xor rand(48) xor rand(46); elsif(rand'length = 97) then --97 xor_out := rand(96) xor rand(90); elsif(rand'length = 98) then --98 xor_out := rand(97) xor rand(86); elsif(rand'length = 99) then --99 xor_out := rand(98) xor rand(96) xor rand(53) xor rand(51); elsif(rand'length = 100) then --100 xor_out := rand(99) xor rand(62); elsif(rand'length = 101) then --101 xor_out := rand(100) xor rand(99) xor rand(94) xor rand(93); elsif(rand'length = 102) then --102 xor_out := rand(101) xor rand(100) xor rand(35) xor rand(34); elsif(rand'length = 103) then --103 xor_out := rand(102) xor rand(93); elsif(rand'length = 104) then --104 xor_out := rand(103) xor rand(102) xor rand(93) xor rand(92); elsif(rand'length = 105) then --105 xor_out := rand(104) xor rand(88); elsif(rand'length = 106) then --106 xor_out := rand(105) xor rand(90); elsif(rand'length = 107) then --107 xor_out := rand(106) xor rand(104) xor rand(43) xor rand(41); elsif(rand'length = 108) then --108 xor_out := rand(107) xor rand(76); elsif(rand'length = 109) then --109 xor_out := rand(108) xor rand(107) xor rand(102) xor rand(101); elsif(rand'length = 110)then --110 xor_out := rand(109) xor rand(108) xor rand(97) xor rand(96); elsif(rand'length = 111) then --111 xor_out := rand(110) xor rand(100); elsif(rand'length = 112) then --112 xor_out := rand(111) xor rand(109) xor rand(68) xor rand(66); elsif(rand'length = 113) then --113 xor_out := rand(112) xor rand(103); elsif(rand'length = 114) then --114 xor_out := rand(113) xor rand(112) xor rand(32) xor rand(31); elsif(rand'length = 115) then --115 xor_out := rand(114) xor rand(113) xor rand(100) xor rand(99); elsif(rand'length = 116) then --116 xor_out := rand(115) xor rand(114) xor rand(45) xor rand(44); elsif(rand'length = 117) then --117 xor_out := rand(116) xor rand(114) xor rand(98) xor rand(96); elsif(rand'length = 118) then --118 xor_out := rand(117) xor rand(84); elsif(rand'length = 119) then --119 xor_out := rand(118) xor rand(110); elsif(rand'length = 120) then --120 xor_out := rand(119) xor rand(112) xor rand(8) xor rand(1); elsif(rand'length = 121) then --121 xor_out := rand(120) xor rand(102); elsif(rand'length = 122) then --122 xor_out := rand(121) xor rand(120) xor rand(62) xor rand(61); elsif(rand'length = 123) then --123 xor_out := rand(122) xor rand(120); elsif(rand'length = 124) then --124 xor_out := rand(123) xor rand(86); elsif(rand'length = 125) then --125 xor_out := rand(124) xor rand(123) xor rand(17) xor rand(16); elsif(rand'length = 126) then --126 xor_out := rand(125) xor rand(124) xor rand(89) xor rand(88); elsif(rand'length = 127) then --127 xor_out := rand(126) xor rand(125); elsif(rand'length = 128) then --128 xor_out := rand(127) xor rand(125) xor rand(100) xor rand(98); elsif(rand'length = 129) then --129 xor_out := rand(128) xor rand(123); elsif(rand'length = 130) then --130 xor_out := rand(129) xor rand(126); elsif(rand'length = 131) then --131 xor_out := rand(130) xor rand(129) xor rand(83) xor rand(82); elsif(rand'length = 132) then --132 xor_out := rand(131) xor rand(102); elsif(rand'length = 133) then --133 xor_out := rand(132) xor rand(131) xor rand(81) xor rand(80); elsif(rand'length = 134) then --134 xor_out := rand(133) xor rand(76); elsif(rand'length = 135) then --135 xor_out := rand(134) xor rand(123); elsif(rand'length = 136) then --136 xor_out := rand(135) xor rand(134) xor rand(10) xor rand(9); elsif(rand'length = 137) then --137 xor_out := rand(136) xor rand(115); elsif(rand'length = 138) then --138 xor_out := rand(137) xor rand(136) xor rand(130) xor rand(129); elsif(rand'length = 139) then --139 xor_out := rand(138) xor rand(135) xor rand(133) xor rand(130); elsif(rand'length = 140) then --140 xor_out := rand(139) xor rand(110); elsif(rand'length = 141) then --141 xor_out := rand(140) xor rand(139) xor rand(109) xor rand(108); elsif(rand'length = 142) then --142 xor_out := rand(141) xor rand(120); elsif(rand'length = 143) then --143 xor_out := rand(142) xor rand(141) xor rand(122) xor rand(121); elsif(rand'length = 144) then --144 xor_out := rand(143) xor rand(142) xor rand(74) xor rand(73); elsif(rand'length = 145) then --145 xor_out := rand(144) xor rand(92); elsif(rand'length = 146) then --146 xor_out := rand(145) xor rand(144) xor rand(86) xor rand(85); elsif(rand'length = 147) then --147 xor_out := rand(146) xor rand(145) xor rand(109) xor rand(108); elsif(rand'length = 148) then --148 xor_out := rand(147) xor rand(120); elsif(rand'length = 149) then --149 xor_out := rand(148) xor rand(147) xor rand(39) xor rand(38); elsif(rand'length = 150) then --150 xor_out := rand(149) xor rand(96); elsif(rand'length = 151) then --151 xor_out := rand(150) xor rand(147); elsif(rand'length = 152) then --152 xor_out := rand(151) xor rand(150) xor rand(86) xor rand(85); elsif(rand'length = 153) then --153 xor_out := rand(152) xor rand(151); elsif(rand'length = 154) then --154 xor_out := rand(153) xor rand(151) xor rand(26) xor rand(24); elsif(rand'length = 155) then --155 xor_out := rand(154) xor rand(153) xor rand(123) xor rand(122); elsif(rand'length = 156) then --156 xor_out := rand(155) xor rand(154) xor rand(40) xor rand(39); elsif(rand'length = 157) then --157 xor_out := rand(156) xor rand(155) xor rand(130) xor rand(129); elsif(rand'length = 158) then --158 xor_out := rand(157) xor rand(156) xor rand(131) xor rand(130); elsif(rand'length = 159) then --159 xor_out := rand(158) xor rand(127); elsif(rand'length = 160) then --160 xor_out := rand(159) xor rand(158) xor rand(141) xor rand(140); elsif(rand'length = 161) then --161 xor_out := rand(160) xor rand(142); elsif(rand'length = 162) then --162 xor_out := rand(161) xor rand(160) xor rand(74) xor rand(73); elsif(rand'length = 163) then --163 xor_out := rand(162) xor rand(161) xor rand(103) xor rand(102); elsif(rand'length = 164) then --164 xor_out := rand(163) xor rand(162) xor rand(150) xor rand(149); elsif(rand'length = 165) then --165 xor_out := rand(164) xor rand(163) xor rand(134) xor rand(133); elsif(rand'length = 166) then --166 xor_out := rand(165) xor rand(164) xor rand(127) xor rand(126); elsif(rand'length = 167) then --167 xor_out := rand(166) xor rand(160); elsif(rand'length = 168) then --168 xor_out := rand(167) xor rand(165) xor rand(152) xor rand(150); end if; return xor_out; end xor_gates; --END function for XORing using tap values. end lfsr_pkg; --End of the package.
---------------------------------------------------------------------------- ---- Create Date: 14:30:08 07/28/2010 ---- ---- Design Name: lfsr_pkg ---- ---- Project Name: lfsr_randgen ---- ---- Description: ---- ---- This is the package file used in the lfsr_randgen project.The ---- ---- package contain the function for XORing bits from various tap ---- ---- locations depending on the generic parameter(width of lfsr ) ---- ---- ---- ---------------------------------------------------------------------------- ---- ---- ---- This file is a part of the lfsr_randgen project at ---- ---- http://www.opencores.org/ ---- ---- ---- ---- Author(s): ---- ---- Vipin Lal, [email protected] ---- ---- ---- ---------------------------------------------------------------------------- ---- ---- ---- Copyright (C) 2010 Authors and OPENCORES.ORG ---- ---- ---- ---- This source file may be used and distributed without ---- ---- restriction provided that this copyright statement is not ---- ---- removed from the file and that any derivative work contains ---- ---- the original copyright notice and the associated disclaimer. ---- ---- ---- ---- This source file is free software; you can redistribute it ---- ---- and/or modify it under the terms of the GNU Lesser General ---- ---- Public License as published by the Free Software Foundation; ---- ---- either version 2.1 of the License, or (at your option) any ---- ---- later version. ---- ---- ---- ---- This source is distributed in the hope that it will be ---- ---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ---- PURPOSE. See the GNU Lesser General Public License for more ---- ---- details. ---- ---- ---- ---- You should have received a copy of the GNU Lesser General ---- ---- Public License along with this source; if not, download it ---- ---- from http://www.opencores.org/lgpl.shtml ---- ---- ---- ---------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; package lfsr_pkg is function xor_gates( random : std_logic_vector) return std_logic; end lfsr_pkg; --Package body starts from here. package body lfsr_pkg is --function for XORing from tap values. function xor_gates( random : std_logic_vector ) return std_logic is variable xor_out : std_logic:='0'; variable rand : std_logic_vector(random'length-1 downto 0):=random; begin if(rand'length = 3) then --3 xor_out := rand(2) xor rand(1); elsif(rand'length = 2) then --2 xor_out := rand(1) xor rand(0); elsif(rand'length = 4) then --4 xor_out := rand(3) xor rand(2); elsif(rand'length = 5) then --5 xor_out := rand(4) xor rand(2); elsif(rand'length = 6) then --6 xor_out := rand(5) xor rand(4); elsif(rand'length = 7) then --7 xor_out := rand(6) xor rand(5); elsif(rand'length = 8) then --8 xor_out := rand(7) xor rand(5) xor rand(4) xor rand(3); elsif(rand'length = 9) then --9 xor_out := rand(8) xor rand(4); elsif(rand'length = 10)then --10 xor_out := rand(9) xor rand(6); elsif(rand'length =11) then --11 xor_out := rand(10) xor rand(8); elsif(rand'length = 12) then --12 xor_out := rand(11) xor rand(5) xor rand(3) xor rand(0); elsif(rand'length = 13) then --13 xor_out := rand(12) xor rand(3) xor rand(2) xor rand(0); elsif(rand'length = 14) then --14 xor_out := rand(13) xor rand(4) xor rand(2) xor rand(0); elsif(rand'length = 15) then --15 xor_out := rand(14) xor rand(13); elsif(rand'length = 16) then --16 xor_out := rand(15) xor rand(14) xor rand(12) xor rand(3); elsif(rand'length = 17) then --17 xor_out := rand(16) xor rand(13); elsif(rand'length = 18) then --18 xor_out := rand(17) xor rand(10); elsif(rand'length = 19) then --19 xor_out := rand(18) xor rand(5) xor rand(1) xor rand(0); elsif(rand'length = 20) then --20 xor_out := rand(19) xor rand(16); elsif(rand'length = 21) then --21 xor_out := rand(20) xor rand(18); elsif(rand'length = 22) then --22 xor_out := rand(21) xor rand(20); elsif(rand'length = 23) then --23 xor_out := rand(22) xor rand(17); elsif(rand'length = 24) then --24 xor_out := rand(23) xor rand(22) xor rand(21) xor rand(16); elsif(rand'length = 25) then --25 xor_out := rand(24) xor rand(21); elsif(rand'length = 26) then --26 xor_out := rand(25) xor rand(5) xor rand(1) xor rand(0); elsif(rand'length = 27) then --27 xor_out := rand(26) xor rand(4) xor rand(1) xor rand(0); elsif(rand'length = 28) then --28 xor_out := rand(27) xor rand(24); elsif(rand'length = 29) then --29 xor_out := rand(28) xor rand(26); elsif(rand'length = 30) then --30 xor_out := rand(29) xor rand(5) xor rand(3) xor rand(0); elsif(rand'length = 31) then --31 xor_out := rand(30) xor rand(27); elsif(rand'length = 32) then --32 xor_out := rand(31) xor rand(21) xor rand(1) xor rand(0); elsif(rand'length = 33) then --33 xor_out := rand(32) xor rand(19); elsif(rand'length = 34) then --34 xor_out := rand(33) xor rand(26) xor rand(1) xor rand(0); elsif(rand'length = 35) then --35 xor_out := rand(34) xor rand(32); elsif(rand'length = 36) then --36 xor_out := rand(35) xor rand(24); elsif(rand'length = 37) then --37 xor_out := rand(36) xor rand(4) xor rand(3) xor rand(2) xor rand(1) xor rand(0); elsif(rand'length = 38) then --38 xor_out := rand(37) xor rand(5) xor rand(4) xor rand(0); elsif(rand'length = 39) then --39 xor_out := rand(38) xor rand(34); elsif(rand'length = 40) then --40 xor_out := rand(39) xor rand(37) xor rand(20) xor rand(18); elsif(rand'length = 41) then --41 xor_out := rand(40) xor rand(37); elsif(rand'length = 42) then --42 xor_out := rand(41) xor rand(40) xor rand(19) xor rand(18); elsif(rand'length = 43) then --43 xor_out := rand(42) xor rand(41) xor rand(37) xor rand(36); elsif(rand'length = 44) then --44 xor_out := rand(43) xor rand(42) xor rand(17) xor rand(16); elsif(rand'length = 45) then --45 xor_out := rand(44) xor rand(43) xor rand(41) xor rand(40); elsif(rand'length = 46) then --46 xor_out := rand(45) xor rand(44) xor rand(25) xor rand(24); elsif(rand'length = 47) then --47 xor_out := rand(46) xor rand(41); elsif(rand'length = 48) then --48 xor_out := rand(47) xor rand(46) xor rand(20) xor rand(19); elsif(rand'length = 49) then --49 xor_out := rand(48) xor rand(39); elsif(rand'length = 50) then --50 xor_out := rand(49) xor rand(48) xor rand(23) xor rand(22); elsif(rand'length = 51) then --51 xor_out := rand(50) xor rand(49) xor rand(35) xor rand(34); elsif(rand'length = 52) then --52 xor_out := rand(51) xor rand(48); elsif(rand'length = 53) then --53 xor_out := rand(52) xor rand(51) xor rand(37) xor rand(36); elsif(rand'length = 54) then --54 xor_out := rand(53) xor rand(52) xor rand(17) xor rand(16); elsif(rand'length = 55) then --55 xor_out := rand(54) xor rand(30); elsif(rand'length = 56) then --56 xor_out := rand(55) xor rand(54) xor rand(34) xor rand(33); elsif(rand'length = 57) then --57 xor_out := rand(56) xor rand(49); elsif(rand'length = 58) then --58 xor_out := rand(57) xor rand(38); elsif(rand'length = 59) then --59 xor_out := rand(58) xor rand(57) xor rand(37) xor rand(36); elsif(rand'length = 60) then --60 xor_out := rand(59) xor rand(58); elsif(rand'length = 61) then --61 xor_out := rand(60) xor rand(59) xor rand(45) xor rand(44); elsif(rand'length = 62) then --62 xor_out := rand(61) xor rand(60) xor rand(5) xor rand(4); elsif(rand'length = 63) then --63 xor_out := rand(62) xor rand(61); elsif(rand'length = 64) then --64 xor_out := rand(63) xor rand(62) xor rand(60) xor rand(59); elsif(rand'length = 65) then --65 xor_out := rand(64) xor rand(46); elsif(rand'length = 66) then --66 xor_out := rand(65) xor rand(64) xor rand(56) xor rand(55); elsif(rand'length = 67) then --67 xor_out := rand(66) xor rand(65) xor rand(57) xor rand(56); elsif(rand'length = 68) then --68 xor_out := rand(67) xor rand(58); elsif(rand'length = 69) then --69 xor_out := rand(68) xor rand(66) xor rand(41) xor rand(39); elsif(rand'length = 70) then --70 xor_out := rand(69) xor rand(68) xor rand(54) xor rand(53); elsif(rand'length = 71) then --71 xor_out := rand(70) xor rand(64); elsif(rand'length = 72) then --72 xor_out := rand(71) xor rand(65) xor rand(24) xor rand(18); elsif(rand'length = 73) then --73 xor_out := rand(72) xor rand(47); elsif(rand'length = 74) then --74 xor_out := rand(73) xor rand(72) xor rand(58) xor rand(57); elsif(rand'length = 75) then --75 xor_out := rand(74) xor rand(73) xor rand(64) xor rand(63); elsif(rand'length = 76) then --76 xor_out := rand(75) xor rand(74) xor rand(40) xor rand(39); elsif(rand'length = 77) then --77 xor_out := rand(76) xor rand(75) xor rand(46) xor rand(45); elsif(rand'length = 78) then --78 xor_out := rand(77) xor rand(76) xor rand(58) xor rand(57); elsif(rand'length = 79) then --79 xor_out := rand(78) xor rand(69); elsif(rand'length = 80) then --80 xor_out := rand(79) xor rand(78) xor rand(42) xor rand(41); elsif(rand'length = 81) then --81 xor_out := rand(80) xor rand(76); elsif(rand'length = 82) then --82 xor_out := rand(81) xor rand(78) xor rand(46) xor rand(43); elsif(rand'length = 83) then --83 xor_out := rand(82) xor rand(81) xor rand(37) xor rand(36); elsif(rand'length = 84) then --84 xor_out := rand(83) xor rand(70); elsif(rand'length = 85) then --85 xor_out := rand(84) xor rand(83) xor rand(57) xor rand(56); elsif(rand'length = 86) then --86 xor_out := rand(85) xor rand(84) xor rand(73) xor rand(72); elsif(rand'length = 87) then --87 xor_out := rand(86) xor rand(73); elsif(rand'length = 88) then --88 xor_out := rand(87) xor rand(86) xor rand(16) xor rand(15); elsif(rand'length = 89) then --89 xor_out := rand(88) xor rand(50); elsif(rand'length = 90) then --90 xor_out := rand(89) xor rand(88) xor rand(71) xor rand(70); elsif(rand'length = 91) then --91 xor_out := rand(90) xor rand(89) xor rand(7) xor rand(6); elsif(rand'length = 92) then --92 xor_out := rand(91) xor rand(90) xor rand(79) xor rand(78); elsif(rand'length = 93) then --93 xor_out := rand(92) xor rand(90); elsif(rand'length = 94) then --94 xor_out := rand(93) xor rand(72); elsif(rand'length = 95) then --95 xor_out := rand(94) xor rand(83); elsif(rand'length = 96) then --96 xor_out := rand(95) xor rand(93) xor rand(48) xor rand(46); elsif(rand'length = 97) then --97 xor_out := rand(96) xor rand(90); elsif(rand'length = 98) then --98 xor_out := rand(97) xor rand(86); elsif(rand'length = 99) then --99 xor_out := rand(98) xor rand(96) xor rand(53) xor rand(51); elsif(rand'length = 100) then --100 xor_out := rand(99) xor rand(62); elsif(rand'length = 101) then --101 xor_out := rand(100) xor rand(99) xor rand(94) xor rand(93); elsif(rand'length = 102) then --102 xor_out := rand(101) xor rand(100) xor rand(35) xor rand(34); elsif(rand'length = 103) then --103 xor_out := rand(102) xor rand(93); elsif(rand'length = 104) then --104 xor_out := rand(103) xor rand(102) xor rand(93) xor rand(92); elsif(rand'length = 105) then --105 xor_out := rand(104) xor rand(88); elsif(rand'length = 106) then --106 xor_out := rand(105) xor rand(90); elsif(rand'length = 107) then --107 xor_out := rand(106) xor rand(104) xor rand(43) xor rand(41); elsif(rand'length = 108) then --108 xor_out := rand(107) xor rand(76); elsif(rand'length = 109) then --109 xor_out := rand(108) xor rand(107) xor rand(102) xor rand(101); elsif(rand'length = 110)then --110 xor_out := rand(109) xor rand(108) xor rand(97) xor rand(96); elsif(rand'length = 111) then --111 xor_out := rand(110) xor rand(100); elsif(rand'length = 112) then --112 xor_out := rand(111) xor rand(109) xor rand(68) xor rand(66); elsif(rand'length = 113) then --113 xor_out := rand(112) xor rand(103); elsif(rand'length = 114) then --114 xor_out := rand(113) xor rand(112) xor rand(32) xor rand(31); elsif(rand'length = 115) then --115 xor_out := rand(114) xor rand(113) xor rand(100) xor rand(99); elsif(rand'length = 116) then --116 xor_out := rand(115) xor rand(114) xor rand(45) xor rand(44); elsif(rand'length = 117) then --117 xor_out := rand(116) xor rand(114) xor rand(98) xor rand(96); elsif(rand'length = 118) then --118 xor_out := rand(117) xor rand(84); elsif(rand'length = 119) then --119 xor_out := rand(118) xor rand(110); elsif(rand'length = 120) then --120 xor_out := rand(119) xor rand(112) xor rand(8) xor rand(1); elsif(rand'length = 121) then --121 xor_out := rand(120) xor rand(102); elsif(rand'length = 122) then --122 xor_out := rand(121) xor rand(120) xor rand(62) xor rand(61); elsif(rand'length = 123) then --123 xor_out := rand(122) xor rand(120); elsif(rand'length = 124) then --124 xor_out := rand(123) xor rand(86); elsif(rand'length = 125) then --125 xor_out := rand(124) xor rand(123) xor rand(17) xor rand(16); elsif(rand'length = 126) then --126 xor_out := rand(125) xor rand(124) xor rand(89) xor rand(88); elsif(rand'length = 127) then --127 xor_out := rand(126) xor rand(125); elsif(rand'length = 128) then --128 xor_out := rand(127) xor rand(125) xor rand(100) xor rand(98); elsif(rand'length = 129) then --129 xor_out := rand(128) xor rand(123); elsif(rand'length = 130) then --130 xor_out := rand(129) xor rand(126); elsif(rand'length = 131) then --131 xor_out := rand(130) xor rand(129) xor rand(83) xor rand(82); elsif(rand'length = 132) then --132 xor_out := rand(131) xor rand(102); elsif(rand'length = 133) then --133 xor_out := rand(132) xor rand(131) xor rand(81) xor rand(80); elsif(rand'length = 134) then --134 xor_out := rand(133) xor rand(76); elsif(rand'length = 135) then --135 xor_out := rand(134) xor rand(123); elsif(rand'length = 136) then --136 xor_out := rand(135) xor rand(134) xor rand(10) xor rand(9); elsif(rand'length = 137) then --137 xor_out := rand(136) xor rand(115); elsif(rand'length = 138) then --138 xor_out := rand(137) xor rand(136) xor rand(130) xor rand(129); elsif(rand'length = 139) then --139 xor_out := rand(138) xor rand(135) xor rand(133) xor rand(130); elsif(rand'length = 140) then --140 xor_out := rand(139) xor rand(110); elsif(rand'length = 141) then --141 xor_out := rand(140) xor rand(139) xor rand(109) xor rand(108); elsif(rand'length = 142) then --142 xor_out := rand(141) xor rand(120); elsif(rand'length = 143) then --143 xor_out := rand(142) xor rand(141) xor rand(122) xor rand(121); elsif(rand'length = 144) then --144 xor_out := rand(143) xor rand(142) xor rand(74) xor rand(73); elsif(rand'length = 145) then --145 xor_out := rand(144) xor rand(92); elsif(rand'length = 146) then --146 xor_out := rand(145) xor rand(144) xor rand(86) xor rand(85); elsif(rand'length = 147) then --147 xor_out := rand(146) xor rand(145) xor rand(109) xor rand(108); elsif(rand'length = 148) then --148 xor_out := rand(147) xor rand(120); elsif(rand'length = 149) then --149 xor_out := rand(148) xor rand(147) xor rand(39) xor rand(38); elsif(rand'length = 150) then --150 xor_out := rand(149) xor rand(96); elsif(rand'length = 151) then --151 xor_out := rand(150) xor rand(147); elsif(rand'length = 152) then --152 xor_out := rand(151) xor rand(150) xor rand(86) xor rand(85); elsif(rand'length = 153) then --153 xor_out := rand(152) xor rand(151); elsif(rand'length = 154) then --154 xor_out := rand(153) xor rand(151) xor rand(26) xor rand(24); elsif(rand'length = 155) then --155 xor_out := rand(154) xor rand(153) xor rand(123) xor rand(122); elsif(rand'length = 156) then --156 xor_out := rand(155) xor rand(154) xor rand(40) xor rand(39); elsif(rand'length = 157) then --157 xor_out := rand(156) xor rand(155) xor rand(130) xor rand(129); elsif(rand'length = 158) then --158 xor_out := rand(157) xor rand(156) xor rand(131) xor rand(130); elsif(rand'length = 159) then --159 xor_out := rand(158) xor rand(127); elsif(rand'length = 160) then --160 xor_out := rand(159) xor rand(158) xor rand(141) xor rand(140); elsif(rand'length = 161) then --161 xor_out := rand(160) xor rand(142); elsif(rand'length = 162) then --162 xor_out := rand(161) xor rand(160) xor rand(74) xor rand(73); elsif(rand'length = 163) then --163 xor_out := rand(162) xor rand(161) xor rand(103) xor rand(102); elsif(rand'length = 164) then --164 xor_out := rand(163) xor rand(162) xor rand(150) xor rand(149); elsif(rand'length = 165) then --165 xor_out := rand(164) xor rand(163) xor rand(134) xor rand(133); elsif(rand'length = 166) then --166 xor_out := rand(165) xor rand(164) xor rand(127) xor rand(126); elsif(rand'length = 167) then --167 xor_out := rand(166) xor rand(160); elsif(rand'length = 168) then --168 xor_out := rand(167) xor rand(165) xor rand(152) xor rand(150); end if; return xor_out; end xor_gates; --END function for XORing using tap values. end lfsr_pkg; --End of the package.
---------------------------------------------------------------------------- ---- Create Date: 14:30:08 07/28/2010 ---- ---- Design Name: lfsr_pkg ---- ---- Project Name: lfsr_randgen ---- ---- Description: ---- ---- This is the package file used in the lfsr_randgen project.The ---- ---- package contain the function for XORing bits from various tap ---- ---- locations depending on the generic parameter(width of lfsr ) ---- ---- ---- ---------------------------------------------------------------------------- ---- ---- ---- This file is a part of the lfsr_randgen project at ---- ---- http://www.opencores.org/ ---- ---- ---- ---- Author(s): ---- ---- Vipin Lal, [email protected] ---- ---- ---- ---------------------------------------------------------------------------- ---- ---- ---- Copyright (C) 2010 Authors and OPENCORES.ORG ---- ---- ---- ---- This source file may be used and distributed without ---- ---- restriction provided that this copyright statement is not ---- ---- removed from the file and that any derivative work contains ---- ---- the original copyright notice and the associated disclaimer. ---- ---- ---- ---- This source file is free software; you can redistribute it ---- ---- and/or modify it under the terms of the GNU Lesser General ---- ---- Public License as published by the Free Software Foundation; ---- ---- either version 2.1 of the License, or (at your option) any ---- ---- later version. ---- ---- ---- ---- This source is distributed in the hope that it will be ---- ---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ---- PURPOSE. See the GNU Lesser General Public License for more ---- ---- details. ---- ---- ---- ---- You should have received a copy of the GNU Lesser General ---- ---- Public License along with this source; if not, download it ---- ---- from http://www.opencores.org/lgpl.shtml ---- ---- ---- ---------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; package lfsr_pkg is function xor_gates( random : std_logic_vector) return std_logic; end lfsr_pkg; --Package body starts from here. package body lfsr_pkg is --function for XORing from tap values. function xor_gates( random : std_logic_vector ) return std_logic is variable xor_out : std_logic:='0'; variable rand : std_logic_vector(random'length-1 downto 0):=random; begin if(rand'length = 3) then --3 xor_out := rand(2) xor rand(1); elsif(rand'length = 2) then --2 xor_out := rand(1) xor rand(0); elsif(rand'length = 4) then --4 xor_out := rand(3) xor rand(2); elsif(rand'length = 5) then --5 xor_out := rand(4) xor rand(2); elsif(rand'length = 6) then --6 xor_out := rand(5) xor rand(4); elsif(rand'length = 7) then --7 xor_out := rand(6) xor rand(5); elsif(rand'length = 8) then --8 xor_out := rand(7) xor rand(5) xor rand(4) xor rand(3); elsif(rand'length = 9) then --9 xor_out := rand(8) xor rand(4); elsif(rand'length = 10)then --10 xor_out := rand(9) xor rand(6); elsif(rand'length =11) then --11 xor_out := rand(10) xor rand(8); elsif(rand'length = 12) then --12 xor_out := rand(11) xor rand(5) xor rand(3) xor rand(0); elsif(rand'length = 13) then --13 xor_out := rand(12) xor rand(3) xor rand(2) xor rand(0); elsif(rand'length = 14) then --14 xor_out := rand(13) xor rand(4) xor rand(2) xor rand(0); elsif(rand'length = 15) then --15 xor_out := rand(14) xor rand(13); elsif(rand'length = 16) then --16 xor_out := rand(15) xor rand(14) xor rand(12) xor rand(3); elsif(rand'length = 17) then --17 xor_out := rand(16) xor rand(13); elsif(rand'length = 18) then --18 xor_out := rand(17) xor rand(10); elsif(rand'length = 19) then --19 xor_out := rand(18) xor rand(5) xor rand(1) xor rand(0); elsif(rand'length = 20) then --20 xor_out := rand(19) xor rand(16); elsif(rand'length = 21) then --21 xor_out := rand(20) xor rand(18); elsif(rand'length = 22) then --22 xor_out := rand(21) xor rand(20); elsif(rand'length = 23) then --23 xor_out := rand(22) xor rand(17); elsif(rand'length = 24) then --24 xor_out := rand(23) xor rand(22) xor rand(21) xor rand(16); elsif(rand'length = 25) then --25 xor_out := rand(24) xor rand(21); elsif(rand'length = 26) then --26 xor_out := rand(25) xor rand(5) xor rand(1) xor rand(0); elsif(rand'length = 27) then --27 xor_out := rand(26) xor rand(4) xor rand(1) xor rand(0); elsif(rand'length = 28) then --28 xor_out := rand(27) xor rand(24); elsif(rand'length = 29) then --29 xor_out := rand(28) xor rand(26); elsif(rand'length = 30) then --30 xor_out := rand(29) xor rand(5) xor rand(3) xor rand(0); elsif(rand'length = 31) then --31 xor_out := rand(30) xor rand(27); elsif(rand'length = 32) then --32 xor_out := rand(31) xor rand(21) xor rand(1) xor rand(0); elsif(rand'length = 33) then --33 xor_out := rand(32) xor rand(19); elsif(rand'length = 34) then --34 xor_out := rand(33) xor rand(26) xor rand(1) xor rand(0); elsif(rand'length = 35) then --35 xor_out := rand(34) xor rand(32); elsif(rand'length = 36) then --36 xor_out := rand(35) xor rand(24); elsif(rand'length = 37) then --37 xor_out := rand(36) xor rand(4) xor rand(3) xor rand(2) xor rand(1) xor rand(0); elsif(rand'length = 38) then --38 xor_out := rand(37) xor rand(5) xor rand(4) xor rand(0); elsif(rand'length = 39) then --39 xor_out := rand(38) xor rand(34); elsif(rand'length = 40) then --40 xor_out := rand(39) xor rand(37) xor rand(20) xor rand(18); elsif(rand'length = 41) then --41 xor_out := rand(40) xor rand(37); elsif(rand'length = 42) then --42 xor_out := rand(41) xor rand(40) xor rand(19) xor rand(18); elsif(rand'length = 43) then --43 xor_out := rand(42) xor rand(41) xor rand(37) xor rand(36); elsif(rand'length = 44) then --44 xor_out := rand(43) xor rand(42) xor rand(17) xor rand(16); elsif(rand'length = 45) then --45 xor_out := rand(44) xor rand(43) xor rand(41) xor rand(40); elsif(rand'length = 46) then --46 xor_out := rand(45) xor rand(44) xor rand(25) xor rand(24); elsif(rand'length = 47) then --47 xor_out := rand(46) xor rand(41); elsif(rand'length = 48) then --48 xor_out := rand(47) xor rand(46) xor rand(20) xor rand(19); elsif(rand'length = 49) then --49 xor_out := rand(48) xor rand(39); elsif(rand'length = 50) then --50 xor_out := rand(49) xor rand(48) xor rand(23) xor rand(22); elsif(rand'length = 51) then --51 xor_out := rand(50) xor rand(49) xor rand(35) xor rand(34); elsif(rand'length = 52) then --52 xor_out := rand(51) xor rand(48); elsif(rand'length = 53) then --53 xor_out := rand(52) xor rand(51) xor rand(37) xor rand(36); elsif(rand'length = 54) then --54 xor_out := rand(53) xor rand(52) xor rand(17) xor rand(16); elsif(rand'length = 55) then --55 xor_out := rand(54) xor rand(30); elsif(rand'length = 56) then --56 xor_out := rand(55) xor rand(54) xor rand(34) xor rand(33); elsif(rand'length = 57) then --57 xor_out := rand(56) xor rand(49); elsif(rand'length = 58) then --58 xor_out := rand(57) xor rand(38); elsif(rand'length = 59) then --59 xor_out := rand(58) xor rand(57) xor rand(37) xor rand(36); elsif(rand'length = 60) then --60 xor_out := rand(59) xor rand(58); elsif(rand'length = 61) then --61 xor_out := rand(60) xor rand(59) xor rand(45) xor rand(44); elsif(rand'length = 62) then --62 xor_out := rand(61) xor rand(60) xor rand(5) xor rand(4); elsif(rand'length = 63) then --63 xor_out := rand(62) xor rand(61); elsif(rand'length = 64) then --64 xor_out := rand(63) xor rand(62) xor rand(60) xor rand(59); elsif(rand'length = 65) then --65 xor_out := rand(64) xor rand(46); elsif(rand'length = 66) then --66 xor_out := rand(65) xor rand(64) xor rand(56) xor rand(55); elsif(rand'length = 67) then --67 xor_out := rand(66) xor rand(65) xor rand(57) xor rand(56); elsif(rand'length = 68) then --68 xor_out := rand(67) xor rand(58); elsif(rand'length = 69) then --69 xor_out := rand(68) xor rand(66) xor rand(41) xor rand(39); elsif(rand'length = 70) then --70 xor_out := rand(69) xor rand(68) xor rand(54) xor rand(53); elsif(rand'length = 71) then --71 xor_out := rand(70) xor rand(64); elsif(rand'length = 72) then --72 xor_out := rand(71) xor rand(65) xor rand(24) xor rand(18); elsif(rand'length = 73) then --73 xor_out := rand(72) xor rand(47); elsif(rand'length = 74) then --74 xor_out := rand(73) xor rand(72) xor rand(58) xor rand(57); elsif(rand'length = 75) then --75 xor_out := rand(74) xor rand(73) xor rand(64) xor rand(63); elsif(rand'length = 76) then --76 xor_out := rand(75) xor rand(74) xor rand(40) xor rand(39); elsif(rand'length = 77) then --77 xor_out := rand(76) xor rand(75) xor rand(46) xor rand(45); elsif(rand'length = 78) then --78 xor_out := rand(77) xor rand(76) xor rand(58) xor rand(57); elsif(rand'length = 79) then --79 xor_out := rand(78) xor rand(69); elsif(rand'length = 80) then --80 xor_out := rand(79) xor rand(78) xor rand(42) xor rand(41); elsif(rand'length = 81) then --81 xor_out := rand(80) xor rand(76); elsif(rand'length = 82) then --82 xor_out := rand(81) xor rand(78) xor rand(46) xor rand(43); elsif(rand'length = 83) then --83 xor_out := rand(82) xor rand(81) xor rand(37) xor rand(36); elsif(rand'length = 84) then --84 xor_out := rand(83) xor rand(70); elsif(rand'length = 85) then --85 xor_out := rand(84) xor rand(83) xor rand(57) xor rand(56); elsif(rand'length = 86) then --86 xor_out := rand(85) xor rand(84) xor rand(73) xor rand(72); elsif(rand'length = 87) then --87 xor_out := rand(86) xor rand(73); elsif(rand'length = 88) then --88 xor_out := rand(87) xor rand(86) xor rand(16) xor rand(15); elsif(rand'length = 89) then --89 xor_out := rand(88) xor rand(50); elsif(rand'length = 90) then --90 xor_out := rand(89) xor rand(88) xor rand(71) xor rand(70); elsif(rand'length = 91) then --91 xor_out := rand(90) xor rand(89) xor rand(7) xor rand(6); elsif(rand'length = 92) then --92 xor_out := rand(91) xor rand(90) xor rand(79) xor rand(78); elsif(rand'length = 93) then --93 xor_out := rand(92) xor rand(90); elsif(rand'length = 94) then --94 xor_out := rand(93) xor rand(72); elsif(rand'length = 95) then --95 xor_out := rand(94) xor rand(83); elsif(rand'length = 96) then --96 xor_out := rand(95) xor rand(93) xor rand(48) xor rand(46); elsif(rand'length = 97) then --97 xor_out := rand(96) xor rand(90); elsif(rand'length = 98) then --98 xor_out := rand(97) xor rand(86); elsif(rand'length = 99) then --99 xor_out := rand(98) xor rand(96) xor rand(53) xor rand(51); elsif(rand'length = 100) then --100 xor_out := rand(99) xor rand(62); elsif(rand'length = 101) then --101 xor_out := rand(100) xor rand(99) xor rand(94) xor rand(93); elsif(rand'length = 102) then --102 xor_out := rand(101) xor rand(100) xor rand(35) xor rand(34); elsif(rand'length = 103) then --103 xor_out := rand(102) xor rand(93); elsif(rand'length = 104) then --104 xor_out := rand(103) xor rand(102) xor rand(93) xor rand(92); elsif(rand'length = 105) then --105 xor_out := rand(104) xor rand(88); elsif(rand'length = 106) then --106 xor_out := rand(105) xor rand(90); elsif(rand'length = 107) then --107 xor_out := rand(106) xor rand(104) xor rand(43) xor rand(41); elsif(rand'length = 108) then --108 xor_out := rand(107) xor rand(76); elsif(rand'length = 109) then --109 xor_out := rand(108) xor rand(107) xor rand(102) xor rand(101); elsif(rand'length = 110)then --110 xor_out := rand(109) xor rand(108) xor rand(97) xor rand(96); elsif(rand'length = 111) then --111 xor_out := rand(110) xor rand(100); elsif(rand'length = 112) then --112 xor_out := rand(111) xor rand(109) xor rand(68) xor rand(66); elsif(rand'length = 113) then --113 xor_out := rand(112) xor rand(103); elsif(rand'length = 114) then --114 xor_out := rand(113) xor rand(112) xor rand(32) xor rand(31); elsif(rand'length = 115) then --115 xor_out := rand(114) xor rand(113) xor rand(100) xor rand(99); elsif(rand'length = 116) then --116 xor_out := rand(115) xor rand(114) xor rand(45) xor rand(44); elsif(rand'length = 117) then --117 xor_out := rand(116) xor rand(114) xor rand(98) xor rand(96); elsif(rand'length = 118) then --118 xor_out := rand(117) xor rand(84); elsif(rand'length = 119) then --119 xor_out := rand(118) xor rand(110); elsif(rand'length = 120) then --120 xor_out := rand(119) xor rand(112) xor rand(8) xor rand(1); elsif(rand'length = 121) then --121 xor_out := rand(120) xor rand(102); elsif(rand'length = 122) then --122 xor_out := rand(121) xor rand(120) xor rand(62) xor rand(61); elsif(rand'length = 123) then --123 xor_out := rand(122) xor rand(120); elsif(rand'length = 124) then --124 xor_out := rand(123) xor rand(86); elsif(rand'length = 125) then --125 xor_out := rand(124) xor rand(123) xor rand(17) xor rand(16); elsif(rand'length = 126) then --126 xor_out := rand(125) xor rand(124) xor rand(89) xor rand(88); elsif(rand'length = 127) then --127 xor_out := rand(126) xor rand(125); elsif(rand'length = 128) then --128 xor_out := rand(127) xor rand(125) xor rand(100) xor rand(98); elsif(rand'length = 129) then --129 xor_out := rand(128) xor rand(123); elsif(rand'length = 130) then --130 xor_out := rand(129) xor rand(126); elsif(rand'length = 131) then --131 xor_out := rand(130) xor rand(129) xor rand(83) xor rand(82); elsif(rand'length = 132) then --132 xor_out := rand(131) xor rand(102); elsif(rand'length = 133) then --133 xor_out := rand(132) xor rand(131) xor rand(81) xor rand(80); elsif(rand'length = 134) then --134 xor_out := rand(133) xor rand(76); elsif(rand'length = 135) then --135 xor_out := rand(134) xor rand(123); elsif(rand'length = 136) then --136 xor_out := rand(135) xor rand(134) xor rand(10) xor rand(9); elsif(rand'length = 137) then --137 xor_out := rand(136) xor rand(115); elsif(rand'length = 138) then --138 xor_out := rand(137) xor rand(136) xor rand(130) xor rand(129); elsif(rand'length = 139) then --139 xor_out := rand(138) xor rand(135) xor rand(133) xor rand(130); elsif(rand'length = 140) then --140 xor_out := rand(139) xor rand(110); elsif(rand'length = 141) then --141 xor_out := rand(140) xor rand(139) xor rand(109) xor rand(108); elsif(rand'length = 142) then --142 xor_out := rand(141) xor rand(120); elsif(rand'length = 143) then --143 xor_out := rand(142) xor rand(141) xor rand(122) xor rand(121); elsif(rand'length = 144) then --144 xor_out := rand(143) xor rand(142) xor rand(74) xor rand(73); elsif(rand'length = 145) then --145 xor_out := rand(144) xor rand(92); elsif(rand'length = 146) then --146 xor_out := rand(145) xor rand(144) xor rand(86) xor rand(85); elsif(rand'length = 147) then --147 xor_out := rand(146) xor rand(145) xor rand(109) xor rand(108); elsif(rand'length = 148) then --148 xor_out := rand(147) xor rand(120); elsif(rand'length = 149) then --149 xor_out := rand(148) xor rand(147) xor rand(39) xor rand(38); elsif(rand'length = 150) then --150 xor_out := rand(149) xor rand(96); elsif(rand'length = 151) then --151 xor_out := rand(150) xor rand(147); elsif(rand'length = 152) then --152 xor_out := rand(151) xor rand(150) xor rand(86) xor rand(85); elsif(rand'length = 153) then --153 xor_out := rand(152) xor rand(151); elsif(rand'length = 154) then --154 xor_out := rand(153) xor rand(151) xor rand(26) xor rand(24); elsif(rand'length = 155) then --155 xor_out := rand(154) xor rand(153) xor rand(123) xor rand(122); elsif(rand'length = 156) then --156 xor_out := rand(155) xor rand(154) xor rand(40) xor rand(39); elsif(rand'length = 157) then --157 xor_out := rand(156) xor rand(155) xor rand(130) xor rand(129); elsif(rand'length = 158) then --158 xor_out := rand(157) xor rand(156) xor rand(131) xor rand(130); elsif(rand'length = 159) then --159 xor_out := rand(158) xor rand(127); elsif(rand'length = 160) then --160 xor_out := rand(159) xor rand(158) xor rand(141) xor rand(140); elsif(rand'length = 161) then --161 xor_out := rand(160) xor rand(142); elsif(rand'length = 162) then --162 xor_out := rand(161) xor rand(160) xor rand(74) xor rand(73); elsif(rand'length = 163) then --163 xor_out := rand(162) xor rand(161) xor rand(103) xor rand(102); elsif(rand'length = 164) then --164 xor_out := rand(163) xor rand(162) xor rand(150) xor rand(149); elsif(rand'length = 165) then --165 xor_out := rand(164) xor rand(163) xor rand(134) xor rand(133); elsif(rand'length = 166) then --166 xor_out := rand(165) xor rand(164) xor rand(127) xor rand(126); elsif(rand'length = 167) then --167 xor_out := rand(166) xor rand(160); elsif(rand'length = 168) then --168 xor_out := rand(167) xor rand(165) xor rand(152) xor rand(150); end if; return xor_out; end xor_gates; --END function for XORing using tap values. end lfsr_pkg; --End of the package.
---------------------------------------------------------------------------- ---- Create Date: 14:30:08 07/28/2010 ---- ---- Design Name: lfsr_pkg ---- ---- Project Name: lfsr_randgen ---- ---- Description: ---- ---- This is the package file used in the lfsr_randgen project.The ---- ---- package contain the function for XORing bits from various tap ---- ---- locations depending on the generic parameter(width of lfsr ) ---- ---- ---- ---------------------------------------------------------------------------- ---- ---- ---- This file is a part of the lfsr_randgen project at ---- ---- http://www.opencores.org/ ---- ---- ---- ---- Author(s): ---- ---- Vipin Lal, [email protected] ---- ---- ---- ---------------------------------------------------------------------------- ---- ---- ---- Copyright (C) 2010 Authors and OPENCORES.ORG ---- ---- ---- ---- This source file may be used and distributed without ---- ---- restriction provided that this copyright statement is not ---- ---- removed from the file and that any derivative work contains ---- ---- the original copyright notice and the associated disclaimer. ---- ---- ---- ---- This source file is free software; you can redistribute it ---- ---- and/or modify it under the terms of the GNU Lesser General ---- ---- Public License as published by the Free Software Foundation; ---- ---- either version 2.1 of the License, or (at your option) any ---- ---- later version. ---- ---- ---- ---- This source is distributed in the hope that it will be ---- ---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ---- PURPOSE. See the GNU Lesser General Public License for more ---- ---- details. ---- ---- ---- ---- You should have received a copy of the GNU Lesser General ---- ---- Public License along with this source; if not, download it ---- ---- from http://www.opencores.org/lgpl.shtml ---- ---- ---- ---------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; package lfsr_pkg is function xor_gates( random : std_logic_vector) return std_logic; end lfsr_pkg; --Package body starts from here. package body lfsr_pkg is --function for XORing from tap values. function xor_gates( random : std_logic_vector ) return std_logic is variable xor_out : std_logic:='0'; variable rand : std_logic_vector(random'length-1 downto 0):=random; begin if(rand'length = 3) then --3 xor_out := rand(2) xor rand(1); elsif(rand'length = 2) then --2 xor_out := rand(1) xor rand(0); elsif(rand'length = 4) then --4 xor_out := rand(3) xor rand(2); elsif(rand'length = 5) then --5 xor_out := rand(4) xor rand(2); elsif(rand'length = 6) then --6 xor_out := rand(5) xor rand(4); elsif(rand'length = 7) then --7 xor_out := rand(6) xor rand(5); elsif(rand'length = 8) then --8 xor_out := rand(7) xor rand(5) xor rand(4) xor rand(3); elsif(rand'length = 9) then --9 xor_out := rand(8) xor rand(4); elsif(rand'length = 10)then --10 xor_out := rand(9) xor rand(6); elsif(rand'length =11) then --11 xor_out := rand(10) xor rand(8); elsif(rand'length = 12) then --12 xor_out := rand(11) xor rand(5) xor rand(3) xor rand(0); elsif(rand'length = 13) then --13 xor_out := rand(12) xor rand(3) xor rand(2) xor rand(0); elsif(rand'length = 14) then --14 xor_out := rand(13) xor rand(4) xor rand(2) xor rand(0); elsif(rand'length = 15) then --15 xor_out := rand(14) xor rand(13); elsif(rand'length = 16) then --16 xor_out := rand(15) xor rand(14) xor rand(12) xor rand(3); elsif(rand'length = 17) then --17 xor_out := rand(16) xor rand(13); elsif(rand'length = 18) then --18 xor_out := rand(17) xor rand(10); elsif(rand'length = 19) then --19 xor_out := rand(18) xor rand(5) xor rand(1) xor rand(0); elsif(rand'length = 20) then --20 xor_out := rand(19) xor rand(16); elsif(rand'length = 21) then --21 xor_out := rand(20) xor rand(18); elsif(rand'length = 22) then --22 xor_out := rand(21) xor rand(20); elsif(rand'length = 23) then --23 xor_out := rand(22) xor rand(17); elsif(rand'length = 24) then --24 xor_out := rand(23) xor rand(22) xor rand(21) xor rand(16); elsif(rand'length = 25) then --25 xor_out := rand(24) xor rand(21); elsif(rand'length = 26) then --26 xor_out := rand(25) xor rand(5) xor rand(1) xor rand(0); elsif(rand'length = 27) then --27 xor_out := rand(26) xor rand(4) xor rand(1) xor rand(0); elsif(rand'length = 28) then --28 xor_out := rand(27) xor rand(24); elsif(rand'length = 29) then --29 xor_out := rand(28) xor rand(26); elsif(rand'length = 30) then --30 xor_out := rand(29) xor rand(5) xor rand(3) xor rand(0); elsif(rand'length = 31) then --31 xor_out := rand(30) xor rand(27); elsif(rand'length = 32) then --32 xor_out := rand(31) xor rand(21) xor rand(1) xor rand(0); elsif(rand'length = 33) then --33 xor_out := rand(32) xor rand(19); elsif(rand'length = 34) then --34 xor_out := rand(33) xor rand(26) xor rand(1) xor rand(0); elsif(rand'length = 35) then --35 xor_out := rand(34) xor rand(32); elsif(rand'length = 36) then --36 xor_out := rand(35) xor rand(24); elsif(rand'length = 37) then --37 xor_out := rand(36) xor rand(4) xor rand(3) xor rand(2) xor rand(1) xor rand(0); elsif(rand'length = 38) then --38 xor_out := rand(37) xor rand(5) xor rand(4) xor rand(0); elsif(rand'length = 39) then --39 xor_out := rand(38) xor rand(34); elsif(rand'length = 40) then --40 xor_out := rand(39) xor rand(37) xor rand(20) xor rand(18); elsif(rand'length = 41) then --41 xor_out := rand(40) xor rand(37); elsif(rand'length = 42) then --42 xor_out := rand(41) xor rand(40) xor rand(19) xor rand(18); elsif(rand'length = 43) then --43 xor_out := rand(42) xor rand(41) xor rand(37) xor rand(36); elsif(rand'length = 44) then --44 xor_out := rand(43) xor rand(42) xor rand(17) xor rand(16); elsif(rand'length = 45) then --45 xor_out := rand(44) xor rand(43) xor rand(41) xor rand(40); elsif(rand'length = 46) then --46 xor_out := rand(45) xor rand(44) xor rand(25) xor rand(24); elsif(rand'length = 47) then --47 xor_out := rand(46) xor rand(41); elsif(rand'length = 48) then --48 xor_out := rand(47) xor rand(46) xor rand(20) xor rand(19); elsif(rand'length = 49) then --49 xor_out := rand(48) xor rand(39); elsif(rand'length = 50) then --50 xor_out := rand(49) xor rand(48) xor rand(23) xor rand(22); elsif(rand'length = 51) then --51 xor_out := rand(50) xor rand(49) xor rand(35) xor rand(34); elsif(rand'length = 52) then --52 xor_out := rand(51) xor rand(48); elsif(rand'length = 53) then --53 xor_out := rand(52) xor rand(51) xor rand(37) xor rand(36); elsif(rand'length = 54) then --54 xor_out := rand(53) xor rand(52) xor rand(17) xor rand(16); elsif(rand'length = 55) then --55 xor_out := rand(54) xor rand(30); elsif(rand'length = 56) then --56 xor_out := rand(55) xor rand(54) xor rand(34) xor rand(33); elsif(rand'length = 57) then --57 xor_out := rand(56) xor rand(49); elsif(rand'length = 58) then --58 xor_out := rand(57) xor rand(38); elsif(rand'length = 59) then --59 xor_out := rand(58) xor rand(57) xor rand(37) xor rand(36); elsif(rand'length = 60) then --60 xor_out := rand(59) xor rand(58); elsif(rand'length = 61) then --61 xor_out := rand(60) xor rand(59) xor rand(45) xor rand(44); elsif(rand'length = 62) then --62 xor_out := rand(61) xor rand(60) xor rand(5) xor rand(4); elsif(rand'length = 63) then --63 xor_out := rand(62) xor rand(61); elsif(rand'length = 64) then --64 xor_out := rand(63) xor rand(62) xor rand(60) xor rand(59); elsif(rand'length = 65) then --65 xor_out := rand(64) xor rand(46); elsif(rand'length = 66) then --66 xor_out := rand(65) xor rand(64) xor rand(56) xor rand(55); elsif(rand'length = 67) then --67 xor_out := rand(66) xor rand(65) xor rand(57) xor rand(56); elsif(rand'length = 68) then --68 xor_out := rand(67) xor rand(58); elsif(rand'length = 69) then --69 xor_out := rand(68) xor rand(66) xor rand(41) xor rand(39); elsif(rand'length = 70) then --70 xor_out := rand(69) xor rand(68) xor rand(54) xor rand(53); elsif(rand'length = 71) then --71 xor_out := rand(70) xor rand(64); elsif(rand'length = 72) then --72 xor_out := rand(71) xor rand(65) xor rand(24) xor rand(18); elsif(rand'length = 73) then --73 xor_out := rand(72) xor rand(47); elsif(rand'length = 74) then --74 xor_out := rand(73) xor rand(72) xor rand(58) xor rand(57); elsif(rand'length = 75) then --75 xor_out := rand(74) xor rand(73) xor rand(64) xor rand(63); elsif(rand'length = 76) then --76 xor_out := rand(75) xor rand(74) xor rand(40) xor rand(39); elsif(rand'length = 77) then --77 xor_out := rand(76) xor rand(75) xor rand(46) xor rand(45); elsif(rand'length = 78) then --78 xor_out := rand(77) xor rand(76) xor rand(58) xor rand(57); elsif(rand'length = 79) then --79 xor_out := rand(78) xor rand(69); elsif(rand'length = 80) then --80 xor_out := rand(79) xor rand(78) xor rand(42) xor rand(41); elsif(rand'length = 81) then --81 xor_out := rand(80) xor rand(76); elsif(rand'length = 82) then --82 xor_out := rand(81) xor rand(78) xor rand(46) xor rand(43); elsif(rand'length = 83) then --83 xor_out := rand(82) xor rand(81) xor rand(37) xor rand(36); elsif(rand'length = 84) then --84 xor_out := rand(83) xor rand(70); elsif(rand'length = 85) then --85 xor_out := rand(84) xor rand(83) xor rand(57) xor rand(56); elsif(rand'length = 86) then --86 xor_out := rand(85) xor rand(84) xor rand(73) xor rand(72); elsif(rand'length = 87) then --87 xor_out := rand(86) xor rand(73); elsif(rand'length = 88) then --88 xor_out := rand(87) xor rand(86) xor rand(16) xor rand(15); elsif(rand'length = 89) then --89 xor_out := rand(88) xor rand(50); elsif(rand'length = 90) then --90 xor_out := rand(89) xor rand(88) xor rand(71) xor rand(70); elsif(rand'length = 91) then --91 xor_out := rand(90) xor rand(89) xor rand(7) xor rand(6); elsif(rand'length = 92) then --92 xor_out := rand(91) xor rand(90) xor rand(79) xor rand(78); elsif(rand'length = 93) then --93 xor_out := rand(92) xor rand(90); elsif(rand'length = 94) then --94 xor_out := rand(93) xor rand(72); elsif(rand'length = 95) then --95 xor_out := rand(94) xor rand(83); elsif(rand'length = 96) then --96 xor_out := rand(95) xor rand(93) xor rand(48) xor rand(46); elsif(rand'length = 97) then --97 xor_out := rand(96) xor rand(90); elsif(rand'length = 98) then --98 xor_out := rand(97) xor rand(86); elsif(rand'length = 99) then --99 xor_out := rand(98) xor rand(96) xor rand(53) xor rand(51); elsif(rand'length = 100) then --100 xor_out := rand(99) xor rand(62); elsif(rand'length = 101) then --101 xor_out := rand(100) xor rand(99) xor rand(94) xor rand(93); elsif(rand'length = 102) then --102 xor_out := rand(101) xor rand(100) xor rand(35) xor rand(34); elsif(rand'length = 103) then --103 xor_out := rand(102) xor rand(93); elsif(rand'length = 104) then --104 xor_out := rand(103) xor rand(102) xor rand(93) xor rand(92); elsif(rand'length = 105) then --105 xor_out := rand(104) xor rand(88); elsif(rand'length = 106) then --106 xor_out := rand(105) xor rand(90); elsif(rand'length = 107) then --107 xor_out := rand(106) xor rand(104) xor rand(43) xor rand(41); elsif(rand'length = 108) then --108 xor_out := rand(107) xor rand(76); elsif(rand'length = 109) then --109 xor_out := rand(108) xor rand(107) xor rand(102) xor rand(101); elsif(rand'length = 110)then --110 xor_out := rand(109) xor rand(108) xor rand(97) xor rand(96); elsif(rand'length = 111) then --111 xor_out := rand(110) xor rand(100); elsif(rand'length = 112) then --112 xor_out := rand(111) xor rand(109) xor rand(68) xor rand(66); elsif(rand'length = 113) then --113 xor_out := rand(112) xor rand(103); elsif(rand'length = 114) then --114 xor_out := rand(113) xor rand(112) xor rand(32) xor rand(31); elsif(rand'length = 115) then --115 xor_out := rand(114) xor rand(113) xor rand(100) xor rand(99); elsif(rand'length = 116) then --116 xor_out := rand(115) xor rand(114) xor rand(45) xor rand(44); elsif(rand'length = 117) then --117 xor_out := rand(116) xor rand(114) xor rand(98) xor rand(96); elsif(rand'length = 118) then --118 xor_out := rand(117) xor rand(84); elsif(rand'length = 119) then --119 xor_out := rand(118) xor rand(110); elsif(rand'length = 120) then --120 xor_out := rand(119) xor rand(112) xor rand(8) xor rand(1); elsif(rand'length = 121) then --121 xor_out := rand(120) xor rand(102); elsif(rand'length = 122) then --122 xor_out := rand(121) xor rand(120) xor rand(62) xor rand(61); elsif(rand'length = 123) then --123 xor_out := rand(122) xor rand(120); elsif(rand'length = 124) then --124 xor_out := rand(123) xor rand(86); elsif(rand'length = 125) then --125 xor_out := rand(124) xor rand(123) xor rand(17) xor rand(16); elsif(rand'length = 126) then --126 xor_out := rand(125) xor rand(124) xor rand(89) xor rand(88); elsif(rand'length = 127) then --127 xor_out := rand(126) xor rand(125); elsif(rand'length = 128) then --128 xor_out := rand(127) xor rand(125) xor rand(100) xor rand(98); elsif(rand'length = 129) then --129 xor_out := rand(128) xor rand(123); elsif(rand'length = 130) then --130 xor_out := rand(129) xor rand(126); elsif(rand'length = 131) then --131 xor_out := rand(130) xor rand(129) xor rand(83) xor rand(82); elsif(rand'length = 132) then --132 xor_out := rand(131) xor rand(102); elsif(rand'length = 133) then --133 xor_out := rand(132) xor rand(131) xor rand(81) xor rand(80); elsif(rand'length = 134) then --134 xor_out := rand(133) xor rand(76); elsif(rand'length = 135) then --135 xor_out := rand(134) xor rand(123); elsif(rand'length = 136) then --136 xor_out := rand(135) xor rand(134) xor rand(10) xor rand(9); elsif(rand'length = 137) then --137 xor_out := rand(136) xor rand(115); elsif(rand'length = 138) then --138 xor_out := rand(137) xor rand(136) xor rand(130) xor rand(129); elsif(rand'length = 139) then --139 xor_out := rand(138) xor rand(135) xor rand(133) xor rand(130); elsif(rand'length = 140) then --140 xor_out := rand(139) xor rand(110); elsif(rand'length = 141) then --141 xor_out := rand(140) xor rand(139) xor rand(109) xor rand(108); elsif(rand'length = 142) then --142 xor_out := rand(141) xor rand(120); elsif(rand'length = 143) then --143 xor_out := rand(142) xor rand(141) xor rand(122) xor rand(121); elsif(rand'length = 144) then --144 xor_out := rand(143) xor rand(142) xor rand(74) xor rand(73); elsif(rand'length = 145) then --145 xor_out := rand(144) xor rand(92); elsif(rand'length = 146) then --146 xor_out := rand(145) xor rand(144) xor rand(86) xor rand(85); elsif(rand'length = 147) then --147 xor_out := rand(146) xor rand(145) xor rand(109) xor rand(108); elsif(rand'length = 148) then --148 xor_out := rand(147) xor rand(120); elsif(rand'length = 149) then --149 xor_out := rand(148) xor rand(147) xor rand(39) xor rand(38); elsif(rand'length = 150) then --150 xor_out := rand(149) xor rand(96); elsif(rand'length = 151) then --151 xor_out := rand(150) xor rand(147); elsif(rand'length = 152) then --152 xor_out := rand(151) xor rand(150) xor rand(86) xor rand(85); elsif(rand'length = 153) then --153 xor_out := rand(152) xor rand(151); elsif(rand'length = 154) then --154 xor_out := rand(153) xor rand(151) xor rand(26) xor rand(24); elsif(rand'length = 155) then --155 xor_out := rand(154) xor rand(153) xor rand(123) xor rand(122); elsif(rand'length = 156) then --156 xor_out := rand(155) xor rand(154) xor rand(40) xor rand(39); elsif(rand'length = 157) then --157 xor_out := rand(156) xor rand(155) xor rand(130) xor rand(129); elsif(rand'length = 158) then --158 xor_out := rand(157) xor rand(156) xor rand(131) xor rand(130); elsif(rand'length = 159) then --159 xor_out := rand(158) xor rand(127); elsif(rand'length = 160) then --160 xor_out := rand(159) xor rand(158) xor rand(141) xor rand(140); elsif(rand'length = 161) then --161 xor_out := rand(160) xor rand(142); elsif(rand'length = 162) then --162 xor_out := rand(161) xor rand(160) xor rand(74) xor rand(73); elsif(rand'length = 163) then --163 xor_out := rand(162) xor rand(161) xor rand(103) xor rand(102); elsif(rand'length = 164) then --164 xor_out := rand(163) xor rand(162) xor rand(150) xor rand(149); elsif(rand'length = 165) then --165 xor_out := rand(164) xor rand(163) xor rand(134) xor rand(133); elsif(rand'length = 166) then --166 xor_out := rand(165) xor rand(164) xor rand(127) xor rand(126); elsif(rand'length = 167) then --167 xor_out := rand(166) xor rand(160); elsif(rand'length = 168) then --168 xor_out := rand(167) xor rand(165) xor rand(152) xor rand(150); end if; return xor_out; end xor_gates; --END function for XORing using tap values. end lfsr_pkg; --End of the package.
---------------------------------------------------------------------------- ---- Create Date: 14:30:08 07/28/2010 ---- ---- Design Name: lfsr_pkg ---- ---- Project Name: lfsr_randgen ---- ---- Description: ---- ---- This is the package file used in the lfsr_randgen project.The ---- ---- package contain the function for XORing bits from various tap ---- ---- locations depending on the generic parameter(width of lfsr ) ---- ---- ---- ---------------------------------------------------------------------------- ---- ---- ---- This file is a part of the lfsr_randgen project at ---- ---- http://www.opencores.org/ ---- ---- ---- ---- Author(s): ---- ---- Vipin Lal, [email protected] ---- ---- ---- ---------------------------------------------------------------------------- ---- ---- ---- Copyright (C) 2010 Authors and OPENCORES.ORG ---- ---- ---- ---- This source file may be used and distributed without ---- ---- restriction provided that this copyright statement is not ---- ---- removed from the file and that any derivative work contains ---- ---- the original copyright notice and the associated disclaimer. ---- ---- ---- ---- This source file is free software; you can redistribute it ---- ---- and/or modify it under the terms of the GNU Lesser General ---- ---- Public License as published by the Free Software Foundation; ---- ---- either version 2.1 of the License, or (at your option) any ---- ---- later version. ---- ---- ---- ---- This source is distributed in the hope that it will be ---- ---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ---- PURPOSE. See the GNU Lesser General Public License for more ---- ---- details. ---- ---- ---- ---- You should have received a copy of the GNU Lesser General ---- ---- Public License along with this source; if not, download it ---- ---- from http://www.opencores.org/lgpl.shtml ---- ---- ---- ---------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; package lfsr_pkg is function xor_gates( random : std_logic_vector) return std_logic; end lfsr_pkg; --Package body starts from here. package body lfsr_pkg is --function for XORing from tap values. function xor_gates( random : std_logic_vector ) return std_logic is variable xor_out : std_logic:='0'; variable rand : std_logic_vector(random'length-1 downto 0):=random; begin if(rand'length = 3) then --3 xor_out := rand(2) xor rand(1); elsif(rand'length = 2) then --2 xor_out := rand(1) xor rand(0); elsif(rand'length = 4) then --4 xor_out := rand(3) xor rand(2); elsif(rand'length = 5) then --5 xor_out := rand(4) xor rand(2); elsif(rand'length = 6) then --6 xor_out := rand(5) xor rand(4); elsif(rand'length = 7) then --7 xor_out := rand(6) xor rand(5); elsif(rand'length = 8) then --8 xor_out := rand(7) xor rand(5) xor rand(4) xor rand(3); elsif(rand'length = 9) then --9 xor_out := rand(8) xor rand(4); elsif(rand'length = 10)then --10 xor_out := rand(9) xor rand(6); elsif(rand'length =11) then --11 xor_out := rand(10) xor rand(8); elsif(rand'length = 12) then --12 xor_out := rand(11) xor rand(5) xor rand(3) xor rand(0); elsif(rand'length = 13) then --13 xor_out := rand(12) xor rand(3) xor rand(2) xor rand(0); elsif(rand'length = 14) then --14 xor_out := rand(13) xor rand(4) xor rand(2) xor rand(0); elsif(rand'length = 15) then --15 xor_out := rand(14) xor rand(13); elsif(rand'length = 16) then --16 xor_out := rand(15) xor rand(14) xor rand(12) xor rand(3); elsif(rand'length = 17) then --17 xor_out := rand(16) xor rand(13); elsif(rand'length = 18) then --18 xor_out := rand(17) xor rand(10); elsif(rand'length = 19) then --19 xor_out := rand(18) xor rand(5) xor rand(1) xor rand(0); elsif(rand'length = 20) then --20 xor_out := rand(19) xor rand(16); elsif(rand'length = 21) then --21 xor_out := rand(20) xor rand(18); elsif(rand'length = 22) then --22 xor_out := rand(21) xor rand(20); elsif(rand'length = 23) then --23 xor_out := rand(22) xor rand(17); elsif(rand'length = 24) then --24 xor_out := rand(23) xor rand(22) xor rand(21) xor rand(16); elsif(rand'length = 25) then --25 xor_out := rand(24) xor rand(21); elsif(rand'length = 26) then --26 xor_out := rand(25) xor rand(5) xor rand(1) xor rand(0); elsif(rand'length = 27) then --27 xor_out := rand(26) xor rand(4) xor rand(1) xor rand(0); elsif(rand'length = 28) then --28 xor_out := rand(27) xor rand(24); elsif(rand'length = 29) then --29 xor_out := rand(28) xor rand(26); elsif(rand'length = 30) then --30 xor_out := rand(29) xor rand(5) xor rand(3) xor rand(0); elsif(rand'length = 31) then --31 xor_out := rand(30) xor rand(27); elsif(rand'length = 32) then --32 xor_out := rand(31) xor rand(21) xor rand(1) xor rand(0); elsif(rand'length = 33) then --33 xor_out := rand(32) xor rand(19); elsif(rand'length = 34) then --34 xor_out := rand(33) xor rand(26) xor rand(1) xor rand(0); elsif(rand'length = 35) then --35 xor_out := rand(34) xor rand(32); elsif(rand'length = 36) then --36 xor_out := rand(35) xor rand(24); elsif(rand'length = 37) then --37 xor_out := rand(36) xor rand(4) xor rand(3) xor rand(2) xor rand(1) xor rand(0); elsif(rand'length = 38) then --38 xor_out := rand(37) xor rand(5) xor rand(4) xor rand(0); elsif(rand'length = 39) then --39 xor_out := rand(38) xor rand(34); elsif(rand'length = 40) then --40 xor_out := rand(39) xor rand(37) xor rand(20) xor rand(18); elsif(rand'length = 41) then --41 xor_out := rand(40) xor rand(37); elsif(rand'length = 42) then --42 xor_out := rand(41) xor rand(40) xor rand(19) xor rand(18); elsif(rand'length = 43) then --43 xor_out := rand(42) xor rand(41) xor rand(37) xor rand(36); elsif(rand'length = 44) then --44 xor_out := rand(43) xor rand(42) xor rand(17) xor rand(16); elsif(rand'length = 45) then --45 xor_out := rand(44) xor rand(43) xor rand(41) xor rand(40); elsif(rand'length = 46) then --46 xor_out := rand(45) xor rand(44) xor rand(25) xor rand(24); elsif(rand'length = 47) then --47 xor_out := rand(46) xor rand(41); elsif(rand'length = 48) then --48 xor_out := rand(47) xor rand(46) xor rand(20) xor rand(19); elsif(rand'length = 49) then --49 xor_out := rand(48) xor rand(39); elsif(rand'length = 50) then --50 xor_out := rand(49) xor rand(48) xor rand(23) xor rand(22); elsif(rand'length = 51) then --51 xor_out := rand(50) xor rand(49) xor rand(35) xor rand(34); elsif(rand'length = 52) then --52 xor_out := rand(51) xor rand(48); elsif(rand'length = 53) then --53 xor_out := rand(52) xor rand(51) xor rand(37) xor rand(36); elsif(rand'length = 54) then --54 xor_out := rand(53) xor rand(52) xor rand(17) xor rand(16); elsif(rand'length = 55) then --55 xor_out := rand(54) xor rand(30); elsif(rand'length = 56) then --56 xor_out := rand(55) xor rand(54) xor rand(34) xor rand(33); elsif(rand'length = 57) then --57 xor_out := rand(56) xor rand(49); elsif(rand'length = 58) then --58 xor_out := rand(57) xor rand(38); elsif(rand'length = 59) then --59 xor_out := rand(58) xor rand(57) xor rand(37) xor rand(36); elsif(rand'length = 60) then --60 xor_out := rand(59) xor rand(58); elsif(rand'length = 61) then --61 xor_out := rand(60) xor rand(59) xor rand(45) xor rand(44); elsif(rand'length = 62) then --62 xor_out := rand(61) xor rand(60) xor rand(5) xor rand(4); elsif(rand'length = 63) then --63 xor_out := rand(62) xor rand(61); elsif(rand'length = 64) then --64 xor_out := rand(63) xor rand(62) xor rand(60) xor rand(59); elsif(rand'length = 65) then --65 xor_out := rand(64) xor rand(46); elsif(rand'length = 66) then --66 xor_out := rand(65) xor rand(64) xor rand(56) xor rand(55); elsif(rand'length = 67) then --67 xor_out := rand(66) xor rand(65) xor rand(57) xor rand(56); elsif(rand'length = 68) then --68 xor_out := rand(67) xor rand(58); elsif(rand'length = 69) then --69 xor_out := rand(68) xor rand(66) xor rand(41) xor rand(39); elsif(rand'length = 70) then --70 xor_out := rand(69) xor rand(68) xor rand(54) xor rand(53); elsif(rand'length = 71) then --71 xor_out := rand(70) xor rand(64); elsif(rand'length = 72) then --72 xor_out := rand(71) xor rand(65) xor rand(24) xor rand(18); elsif(rand'length = 73) then --73 xor_out := rand(72) xor rand(47); elsif(rand'length = 74) then --74 xor_out := rand(73) xor rand(72) xor rand(58) xor rand(57); elsif(rand'length = 75) then --75 xor_out := rand(74) xor rand(73) xor rand(64) xor rand(63); elsif(rand'length = 76) then --76 xor_out := rand(75) xor rand(74) xor rand(40) xor rand(39); elsif(rand'length = 77) then --77 xor_out := rand(76) xor rand(75) xor rand(46) xor rand(45); elsif(rand'length = 78) then --78 xor_out := rand(77) xor rand(76) xor rand(58) xor rand(57); elsif(rand'length = 79) then --79 xor_out := rand(78) xor rand(69); elsif(rand'length = 80) then --80 xor_out := rand(79) xor rand(78) xor rand(42) xor rand(41); elsif(rand'length = 81) then --81 xor_out := rand(80) xor rand(76); elsif(rand'length = 82) then --82 xor_out := rand(81) xor rand(78) xor rand(46) xor rand(43); elsif(rand'length = 83) then --83 xor_out := rand(82) xor rand(81) xor rand(37) xor rand(36); elsif(rand'length = 84) then --84 xor_out := rand(83) xor rand(70); elsif(rand'length = 85) then --85 xor_out := rand(84) xor rand(83) xor rand(57) xor rand(56); elsif(rand'length = 86) then --86 xor_out := rand(85) xor rand(84) xor rand(73) xor rand(72); elsif(rand'length = 87) then --87 xor_out := rand(86) xor rand(73); elsif(rand'length = 88) then --88 xor_out := rand(87) xor rand(86) xor rand(16) xor rand(15); elsif(rand'length = 89) then --89 xor_out := rand(88) xor rand(50); elsif(rand'length = 90) then --90 xor_out := rand(89) xor rand(88) xor rand(71) xor rand(70); elsif(rand'length = 91) then --91 xor_out := rand(90) xor rand(89) xor rand(7) xor rand(6); elsif(rand'length = 92) then --92 xor_out := rand(91) xor rand(90) xor rand(79) xor rand(78); elsif(rand'length = 93) then --93 xor_out := rand(92) xor rand(90); elsif(rand'length = 94) then --94 xor_out := rand(93) xor rand(72); elsif(rand'length = 95) then --95 xor_out := rand(94) xor rand(83); elsif(rand'length = 96) then --96 xor_out := rand(95) xor rand(93) xor rand(48) xor rand(46); elsif(rand'length = 97) then --97 xor_out := rand(96) xor rand(90); elsif(rand'length = 98) then --98 xor_out := rand(97) xor rand(86); elsif(rand'length = 99) then --99 xor_out := rand(98) xor rand(96) xor rand(53) xor rand(51); elsif(rand'length = 100) then --100 xor_out := rand(99) xor rand(62); elsif(rand'length = 101) then --101 xor_out := rand(100) xor rand(99) xor rand(94) xor rand(93); elsif(rand'length = 102) then --102 xor_out := rand(101) xor rand(100) xor rand(35) xor rand(34); elsif(rand'length = 103) then --103 xor_out := rand(102) xor rand(93); elsif(rand'length = 104) then --104 xor_out := rand(103) xor rand(102) xor rand(93) xor rand(92); elsif(rand'length = 105) then --105 xor_out := rand(104) xor rand(88); elsif(rand'length = 106) then --106 xor_out := rand(105) xor rand(90); elsif(rand'length = 107) then --107 xor_out := rand(106) xor rand(104) xor rand(43) xor rand(41); elsif(rand'length = 108) then --108 xor_out := rand(107) xor rand(76); elsif(rand'length = 109) then --109 xor_out := rand(108) xor rand(107) xor rand(102) xor rand(101); elsif(rand'length = 110)then --110 xor_out := rand(109) xor rand(108) xor rand(97) xor rand(96); elsif(rand'length = 111) then --111 xor_out := rand(110) xor rand(100); elsif(rand'length = 112) then --112 xor_out := rand(111) xor rand(109) xor rand(68) xor rand(66); elsif(rand'length = 113) then --113 xor_out := rand(112) xor rand(103); elsif(rand'length = 114) then --114 xor_out := rand(113) xor rand(112) xor rand(32) xor rand(31); elsif(rand'length = 115) then --115 xor_out := rand(114) xor rand(113) xor rand(100) xor rand(99); elsif(rand'length = 116) then --116 xor_out := rand(115) xor rand(114) xor rand(45) xor rand(44); elsif(rand'length = 117) then --117 xor_out := rand(116) xor rand(114) xor rand(98) xor rand(96); elsif(rand'length = 118) then --118 xor_out := rand(117) xor rand(84); elsif(rand'length = 119) then --119 xor_out := rand(118) xor rand(110); elsif(rand'length = 120) then --120 xor_out := rand(119) xor rand(112) xor rand(8) xor rand(1); elsif(rand'length = 121) then --121 xor_out := rand(120) xor rand(102); elsif(rand'length = 122) then --122 xor_out := rand(121) xor rand(120) xor rand(62) xor rand(61); elsif(rand'length = 123) then --123 xor_out := rand(122) xor rand(120); elsif(rand'length = 124) then --124 xor_out := rand(123) xor rand(86); elsif(rand'length = 125) then --125 xor_out := rand(124) xor rand(123) xor rand(17) xor rand(16); elsif(rand'length = 126) then --126 xor_out := rand(125) xor rand(124) xor rand(89) xor rand(88); elsif(rand'length = 127) then --127 xor_out := rand(126) xor rand(125); elsif(rand'length = 128) then --128 xor_out := rand(127) xor rand(125) xor rand(100) xor rand(98); elsif(rand'length = 129) then --129 xor_out := rand(128) xor rand(123); elsif(rand'length = 130) then --130 xor_out := rand(129) xor rand(126); elsif(rand'length = 131) then --131 xor_out := rand(130) xor rand(129) xor rand(83) xor rand(82); elsif(rand'length = 132) then --132 xor_out := rand(131) xor rand(102); elsif(rand'length = 133) then --133 xor_out := rand(132) xor rand(131) xor rand(81) xor rand(80); elsif(rand'length = 134) then --134 xor_out := rand(133) xor rand(76); elsif(rand'length = 135) then --135 xor_out := rand(134) xor rand(123); elsif(rand'length = 136) then --136 xor_out := rand(135) xor rand(134) xor rand(10) xor rand(9); elsif(rand'length = 137) then --137 xor_out := rand(136) xor rand(115); elsif(rand'length = 138) then --138 xor_out := rand(137) xor rand(136) xor rand(130) xor rand(129); elsif(rand'length = 139) then --139 xor_out := rand(138) xor rand(135) xor rand(133) xor rand(130); elsif(rand'length = 140) then --140 xor_out := rand(139) xor rand(110); elsif(rand'length = 141) then --141 xor_out := rand(140) xor rand(139) xor rand(109) xor rand(108); elsif(rand'length = 142) then --142 xor_out := rand(141) xor rand(120); elsif(rand'length = 143) then --143 xor_out := rand(142) xor rand(141) xor rand(122) xor rand(121); elsif(rand'length = 144) then --144 xor_out := rand(143) xor rand(142) xor rand(74) xor rand(73); elsif(rand'length = 145) then --145 xor_out := rand(144) xor rand(92); elsif(rand'length = 146) then --146 xor_out := rand(145) xor rand(144) xor rand(86) xor rand(85); elsif(rand'length = 147) then --147 xor_out := rand(146) xor rand(145) xor rand(109) xor rand(108); elsif(rand'length = 148) then --148 xor_out := rand(147) xor rand(120); elsif(rand'length = 149) then --149 xor_out := rand(148) xor rand(147) xor rand(39) xor rand(38); elsif(rand'length = 150) then --150 xor_out := rand(149) xor rand(96); elsif(rand'length = 151) then --151 xor_out := rand(150) xor rand(147); elsif(rand'length = 152) then --152 xor_out := rand(151) xor rand(150) xor rand(86) xor rand(85); elsif(rand'length = 153) then --153 xor_out := rand(152) xor rand(151); elsif(rand'length = 154) then --154 xor_out := rand(153) xor rand(151) xor rand(26) xor rand(24); elsif(rand'length = 155) then --155 xor_out := rand(154) xor rand(153) xor rand(123) xor rand(122); elsif(rand'length = 156) then --156 xor_out := rand(155) xor rand(154) xor rand(40) xor rand(39); elsif(rand'length = 157) then --157 xor_out := rand(156) xor rand(155) xor rand(130) xor rand(129); elsif(rand'length = 158) then --158 xor_out := rand(157) xor rand(156) xor rand(131) xor rand(130); elsif(rand'length = 159) then --159 xor_out := rand(158) xor rand(127); elsif(rand'length = 160) then --160 xor_out := rand(159) xor rand(158) xor rand(141) xor rand(140); elsif(rand'length = 161) then --161 xor_out := rand(160) xor rand(142); elsif(rand'length = 162) then --162 xor_out := rand(161) xor rand(160) xor rand(74) xor rand(73); elsif(rand'length = 163) then --163 xor_out := rand(162) xor rand(161) xor rand(103) xor rand(102); elsif(rand'length = 164) then --164 xor_out := rand(163) xor rand(162) xor rand(150) xor rand(149); elsif(rand'length = 165) then --165 xor_out := rand(164) xor rand(163) xor rand(134) xor rand(133); elsif(rand'length = 166) then --166 xor_out := rand(165) xor rand(164) xor rand(127) xor rand(126); elsif(rand'length = 167) then --167 xor_out := rand(166) xor rand(160); elsif(rand'length = 168) then --168 xor_out := rand(167) xor rand(165) xor rand(152) xor rand(150); end if; return xor_out; end xor_gates; --END function for XORing using tap values. end lfsr_pkg; --End of the package.
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity SignalShorter_16x1 is Port ( input : in STD_LOGIC_VECTOR (15 downto 0); output : out STD_LOGIC); end SignalShorter_16x1; architecture skeleton of SignalShorter_16x1 is begin process(input) is variable verifier : STD_LOGIC; begin verifier := '0'; for i in 15 downto 0 loop if(input(i) = '1') then verifier := '1'; end if; end loop; output <= verifier; end process; end skeleton;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_NORMFP1X.VHD *** --*** *** --*** Function: Normalize single precision *** --*** number *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** 28/12/07 - divider target uses all of *** --*** mantissa width *** --*** 06/02/08 - fix divider norm *** --*** 21/03/08 - fix add tree output norm *** --*** *** --*************************************************** -- normalize signed numbers (x input format) - for 1x multipliers -- format signed32/36 bit mantissa, 10 bit exponent -- unsigned numbers for divider (S,1,23 bit mantissa for divider) -- divider packed into 32/36bit mantissa + exponent ENTITY hcc_normfp1x IS GENERIC ( mantissa : positive := 32; -- 32 or 36 inputnormalize : integer := 1; -- 0 = scale, 1 = normalize roundnormalize : integer := 1; normspeed : positive := 2; -- 1 or 2 target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); END hcc_normfp1x; ARCHITECTURE rtl OF hcc_normfp1x IS type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal ccnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); -- scale signal aasatff, aazipff : STD_LOGIC; signal countaa : STD_LOGIC_VECTOR (3 DOWNTO 1); -- normalize signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1); signal normfracnode, normnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal normfracff, normff : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal countadjust : STD_LOGIC_VECTOR (10 DOWNTO 1); signal exptopff, expbotff : expfftype; signal aasatdelff, aazipdelff : STD_LOGIC_VECTOR (5 DOWNTO 1); signal countsign : STD_LOGIC_VECTOR (6 DOWNTO 1); signal normsignnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal aaexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1); component hcc_normsgn3236 GENERIC ( mantissa : positive := 32; normspeed : positive := 1 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1) ); end component; component hcc_scmul3236 GENERIC (mantissa : positive := 32); PORT ( frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1); count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1) ); end component; BEGIN --******************************************************** --*** scale multiplier *** --*** multiplier format [S][1][mantissa....] *** --*** one clock latency *** --******************************************************** -- make sure right format & adjust exponent gsa: IF (inputnormalize = 0) GENERATE psa: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; END LOOP; aasatff <= '0'; aazipff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; aasatff <= aasat; aazipff <= aazip; END IF; END IF; END PROCESS; -- no rounding when scaling sma: hcc_scmul3236 GENERIC MAP (mantissa=>mantissa) PORT MAP (frac=>aaff(mantissa+10 DOWNTO 11), scaled=>ccnode(mantissa+10 DOWNTO 11),count=>countaa); ccnode(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + ("0000000" & countaa); cc <= ccnode; ccsat <= aasatff; cczip <= aazipff; END GENERATE; --******************************************************** --*** full normalization of input - 4 stages *** --*** unlike double, no round required on output, as *** --*** no information lost *** --******************************************************** gna: IF (inputnormalize = 1) GENERATE -- normalize gza: FOR k IN 1 TO mantissa-1 GENERATE zerovec(k) <= '0'; END GENERATE; -- if multiplier, "1" which is nominally in position 27, is shifted to position 31 -- add 4 to exponent when multiplier, 0 for adder gxa: IF (target < 2) GENERATE countadjust <= conv_std_logic_vector (4,10); END GENERATE; gxb: IF (target = 2) GENERATE countadjust <= conv_std_logic_vector (4,10); END GENERATE; pna: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; END LOOP; FOR k IN 1 TO mantissa LOOP normfracff(k) <= '0'; normff(k) <= '0'; END LOOP; FOR k IN 1 TO 10 LOOP exptopff(1)(k) <= '0'; exptopff(2)(k) <= '0'; expbotff(1)(k) <= '0'; expbotff(2)(k) <= '0'; END LOOP; FOR k IN 1 TO 5 LOOP aasatdelff(k) <= '0'; aazipdelff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; normfracff <= normfracnode; --might not get used normff <= normnode; exptopff(1)(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + countadjust; exptopff(2)(10 DOWNTO 1) <= exptopff(1)(10 DOWNTO 1) - ("0000" & countsign); --might not get used expbotff(1)(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); expbotff(2)(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); aasatdelff(1) <= aasat; aazipdelff(1) <= aazip; FOR k IN 2 TO 5 LOOP -- 4&5 might not get used aasatdelff(k) <= aasatdelff(k-1); aazipdelff(k) <= aazipdelff(k-1); END LOOP; END IF; END IF; END PROCESS; nrmc: hcc_normsgn3236 GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, fracin=>aaff(mantissa+10 DOWNTO 11), countout=>countsign, -- stage 1 or 2 fracout=>normfracnode); -- stage 2 or 3 gnb: IF (target = 1) GENERATE gnc: FOR k IN 1 TO mantissa GENERATE normsignnode(k) <= normfracff(k) XOR normfracff(mantissa); END GENERATE; normnode(mantissa-1 DOWNTO 1) <= normsignnode(mantissa-1 DOWNTO 1) + (zerovec(mantissa-2 DOWNTO 1) & normfracff(mantissa)); -- 06/02/08 make sure signbit is packed with the mantissa normnode(mantissa) <= normfracff(mantissa); --*** OUTPUTS *** ccnode(mantissa+10 DOWNTO 11) <= normff; ccnode(10 DOWNTO 1) <= expbotff(normspeed)(10 DOWNTO 1); ccsat <= aasatdelff(3+normspeed); cczip <= aazipdelff(3+normspeed); END GENERATE; gnc: IF (target = 0) GENERATE --*** OUTPUTS *** ccnode(mantissa+10 DOWNTO 11) <= normfracff; gma: IF (normspeed = 1) GENERATE ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); END GENERATE; gmb: IF (normspeed > 1) GENERATE ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); END GENERATE; ccsat <= aasatdelff(2+normspeed); cczip <= aazipdelff(2+normspeed); END GENERATE; gnd: IF (target = 2) GENERATE gaa: IF (roundnormalize = 1) GENERATE normnode <= (normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa DOWNTO 5)) + (zerovec(mantissa-1 DOWNTO 1) & normfracff(4)); END GENERATE; --*** OUTPUTS *** gab: IF (roundnormalize = 0) GENERATE -- 21/03/08 fixed this to SSSSS1XXXXX ccnode(mantissa+10 DOWNTO 11) <= normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa DOWNTO 5); END GENERATE; gac: IF (roundnormalize = 1) GENERATE ccnode(mantissa+10 DOWNTO 11) <= normff; END GENERATE; gad: IF (normspeed = 1 AND roundnormalize = 0) GENERATE ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); END GENERATE; gae: IF ((normspeed = 2 AND roundnormalize = 0) OR (normspeed = 1 AND roundnormalize = 1)) GENERATE ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); END GENERATE; gaf: IF (normspeed = 2 AND roundnormalize = 1) GENERATE ccnode(10 DOWNTO 1) <= expbotff(2)(10 DOWNTO 1); END GENERATE; ccsat <= aasatdelff(2+normspeed+roundnormalize); cczip <= aazipdelff(2+normspeed+roundnormalize); END GENERATE; cc <= ccnode; END GENERATE; --*** DEBUG *** aaexp <= aa(10 DOWNTO 1); aaman <= aa(mantissa+10 DOWNTO 11); ccexp <= ccnode(10 DOWNTO 1); ccman <= ccnode(mantissa+10 DOWNTO 11); END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_NORMFP1X.VHD *** --*** *** --*** Function: Normalize single precision *** --*** number *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** 28/12/07 - divider target uses all of *** --*** mantissa width *** --*** 06/02/08 - fix divider norm *** --*** 21/03/08 - fix add tree output norm *** --*** *** --*************************************************** -- normalize signed numbers (x input format) - for 1x multipliers -- format signed32/36 bit mantissa, 10 bit exponent -- unsigned numbers for divider (S,1,23 bit mantissa for divider) -- divider packed into 32/36bit mantissa + exponent ENTITY hcc_normfp1x IS GENERIC ( mantissa : positive := 32; -- 32 or 36 inputnormalize : integer := 1; -- 0 = scale, 1 = normalize roundnormalize : integer := 1; normspeed : positive := 2; -- 1 or 2 target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); END hcc_normfp1x; ARCHITECTURE rtl OF hcc_normfp1x IS type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal ccnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); -- scale signal aasatff, aazipff : STD_LOGIC; signal countaa : STD_LOGIC_VECTOR (3 DOWNTO 1); -- normalize signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1); signal normfracnode, normnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal normfracff, normff : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal countadjust : STD_LOGIC_VECTOR (10 DOWNTO 1); signal exptopff, expbotff : expfftype; signal aasatdelff, aazipdelff : STD_LOGIC_VECTOR (5 DOWNTO 1); signal countsign : STD_LOGIC_VECTOR (6 DOWNTO 1); signal normsignnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal aaexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1); component hcc_normsgn3236 GENERIC ( mantissa : positive := 32; normspeed : positive := 1 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1) ); end component; component hcc_scmul3236 GENERIC (mantissa : positive := 32); PORT ( frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1); count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1) ); end component; BEGIN --******************************************************** --*** scale multiplier *** --*** multiplier format [S][1][mantissa....] *** --*** one clock latency *** --******************************************************** -- make sure right format & adjust exponent gsa: IF (inputnormalize = 0) GENERATE psa: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; END LOOP; aasatff <= '0'; aazipff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; aasatff <= aasat; aazipff <= aazip; END IF; END IF; END PROCESS; -- no rounding when scaling sma: hcc_scmul3236 GENERIC MAP (mantissa=>mantissa) PORT MAP (frac=>aaff(mantissa+10 DOWNTO 11), scaled=>ccnode(mantissa+10 DOWNTO 11),count=>countaa); ccnode(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + ("0000000" & countaa); cc <= ccnode; ccsat <= aasatff; cczip <= aazipff; END GENERATE; --******************************************************** --*** full normalization of input - 4 stages *** --*** unlike double, no round required on output, as *** --*** no information lost *** --******************************************************** gna: IF (inputnormalize = 1) GENERATE -- normalize gza: FOR k IN 1 TO mantissa-1 GENERATE zerovec(k) <= '0'; END GENERATE; -- if multiplier, "1" which is nominally in position 27, is shifted to position 31 -- add 4 to exponent when multiplier, 0 for adder gxa: IF (target < 2) GENERATE countadjust <= conv_std_logic_vector (4,10); END GENERATE; gxb: IF (target = 2) GENERATE countadjust <= conv_std_logic_vector (4,10); END GENERATE; pna: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; END LOOP; FOR k IN 1 TO mantissa LOOP normfracff(k) <= '0'; normff(k) <= '0'; END LOOP; FOR k IN 1 TO 10 LOOP exptopff(1)(k) <= '0'; exptopff(2)(k) <= '0'; expbotff(1)(k) <= '0'; expbotff(2)(k) <= '0'; END LOOP; FOR k IN 1 TO 5 LOOP aasatdelff(k) <= '0'; aazipdelff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; normfracff <= normfracnode; --might not get used normff <= normnode; exptopff(1)(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + countadjust; exptopff(2)(10 DOWNTO 1) <= exptopff(1)(10 DOWNTO 1) - ("0000" & countsign); --might not get used expbotff(1)(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); expbotff(2)(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); aasatdelff(1) <= aasat; aazipdelff(1) <= aazip; FOR k IN 2 TO 5 LOOP -- 4&5 might not get used aasatdelff(k) <= aasatdelff(k-1); aazipdelff(k) <= aazipdelff(k-1); END LOOP; END IF; END IF; END PROCESS; nrmc: hcc_normsgn3236 GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, fracin=>aaff(mantissa+10 DOWNTO 11), countout=>countsign, -- stage 1 or 2 fracout=>normfracnode); -- stage 2 or 3 gnb: IF (target = 1) GENERATE gnc: FOR k IN 1 TO mantissa GENERATE normsignnode(k) <= normfracff(k) XOR normfracff(mantissa); END GENERATE; normnode(mantissa-1 DOWNTO 1) <= normsignnode(mantissa-1 DOWNTO 1) + (zerovec(mantissa-2 DOWNTO 1) & normfracff(mantissa)); -- 06/02/08 make sure signbit is packed with the mantissa normnode(mantissa) <= normfracff(mantissa); --*** OUTPUTS *** ccnode(mantissa+10 DOWNTO 11) <= normff; ccnode(10 DOWNTO 1) <= expbotff(normspeed)(10 DOWNTO 1); ccsat <= aasatdelff(3+normspeed); cczip <= aazipdelff(3+normspeed); END GENERATE; gnc: IF (target = 0) GENERATE --*** OUTPUTS *** ccnode(mantissa+10 DOWNTO 11) <= normfracff; gma: IF (normspeed = 1) GENERATE ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); END GENERATE; gmb: IF (normspeed > 1) GENERATE ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); END GENERATE; ccsat <= aasatdelff(2+normspeed); cczip <= aazipdelff(2+normspeed); END GENERATE; gnd: IF (target = 2) GENERATE gaa: IF (roundnormalize = 1) GENERATE normnode <= (normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa DOWNTO 5)) + (zerovec(mantissa-1 DOWNTO 1) & normfracff(4)); END GENERATE; --*** OUTPUTS *** gab: IF (roundnormalize = 0) GENERATE -- 21/03/08 fixed this to SSSSS1XXXXX ccnode(mantissa+10 DOWNTO 11) <= normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa DOWNTO 5); END GENERATE; gac: IF (roundnormalize = 1) GENERATE ccnode(mantissa+10 DOWNTO 11) <= normff; END GENERATE; gad: IF (normspeed = 1 AND roundnormalize = 0) GENERATE ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); END GENERATE; gae: IF ((normspeed = 2 AND roundnormalize = 0) OR (normspeed = 1 AND roundnormalize = 1)) GENERATE ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); END GENERATE; gaf: IF (normspeed = 2 AND roundnormalize = 1) GENERATE ccnode(10 DOWNTO 1) <= expbotff(2)(10 DOWNTO 1); END GENERATE; ccsat <= aasatdelff(2+normspeed+roundnormalize); cczip <= aazipdelff(2+normspeed+roundnormalize); END GENERATE; cc <= ccnode; END GENERATE; --*** DEBUG *** aaexp <= aa(10 DOWNTO 1); aaman <= aa(mantissa+10 DOWNTO 11); ccexp <= ccnode(10 DOWNTO 1); ccman <= ccnode(mantissa+10 DOWNTO 11); END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_NORMFP1X.VHD *** --*** *** --*** Function: Normalize single precision *** --*** number *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** 28/12/07 - divider target uses all of *** --*** mantissa width *** --*** 06/02/08 - fix divider norm *** --*** 21/03/08 - fix add tree output norm *** --*** *** --*************************************************** -- normalize signed numbers (x input format) - for 1x multipliers -- format signed32/36 bit mantissa, 10 bit exponent -- unsigned numbers for divider (S,1,23 bit mantissa for divider) -- divider packed into 32/36bit mantissa + exponent ENTITY hcc_normfp1x IS GENERIC ( mantissa : positive := 32; -- 32 or 36 inputnormalize : integer := 1; -- 0 = scale, 1 = normalize roundnormalize : integer := 1; normspeed : positive := 2; -- 1 or 2 target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); END hcc_normfp1x; ARCHITECTURE rtl OF hcc_normfp1x IS type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal ccnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); -- scale signal aasatff, aazipff : STD_LOGIC; signal countaa : STD_LOGIC_VECTOR (3 DOWNTO 1); -- normalize signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1); signal normfracnode, normnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal normfracff, normff : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal countadjust : STD_LOGIC_VECTOR (10 DOWNTO 1); signal exptopff, expbotff : expfftype; signal aasatdelff, aazipdelff : STD_LOGIC_VECTOR (5 DOWNTO 1); signal countsign : STD_LOGIC_VECTOR (6 DOWNTO 1); signal normsignnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal aaexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1); component hcc_normsgn3236 GENERIC ( mantissa : positive := 32; normspeed : positive := 1 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1) ); end component; component hcc_scmul3236 GENERIC (mantissa : positive := 32); PORT ( frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1); count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1) ); end component; BEGIN --******************************************************** --*** scale multiplier *** --*** multiplier format [S][1][mantissa....] *** --*** one clock latency *** --******************************************************** -- make sure right format & adjust exponent gsa: IF (inputnormalize = 0) GENERATE psa: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; END LOOP; aasatff <= '0'; aazipff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; aasatff <= aasat; aazipff <= aazip; END IF; END IF; END PROCESS; -- no rounding when scaling sma: hcc_scmul3236 GENERIC MAP (mantissa=>mantissa) PORT MAP (frac=>aaff(mantissa+10 DOWNTO 11), scaled=>ccnode(mantissa+10 DOWNTO 11),count=>countaa); ccnode(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + ("0000000" & countaa); cc <= ccnode; ccsat <= aasatff; cczip <= aazipff; END GENERATE; --******************************************************** --*** full normalization of input - 4 stages *** --*** unlike double, no round required on output, as *** --*** no information lost *** --******************************************************** gna: IF (inputnormalize = 1) GENERATE -- normalize gza: FOR k IN 1 TO mantissa-1 GENERATE zerovec(k) <= '0'; END GENERATE; -- if multiplier, "1" which is nominally in position 27, is shifted to position 31 -- add 4 to exponent when multiplier, 0 for adder gxa: IF (target < 2) GENERATE countadjust <= conv_std_logic_vector (4,10); END GENERATE; gxb: IF (target = 2) GENERATE countadjust <= conv_std_logic_vector (4,10); END GENERATE; pna: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; END LOOP; FOR k IN 1 TO mantissa LOOP normfracff(k) <= '0'; normff(k) <= '0'; END LOOP; FOR k IN 1 TO 10 LOOP exptopff(1)(k) <= '0'; exptopff(2)(k) <= '0'; expbotff(1)(k) <= '0'; expbotff(2)(k) <= '0'; END LOOP; FOR k IN 1 TO 5 LOOP aasatdelff(k) <= '0'; aazipdelff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; normfracff <= normfracnode; --might not get used normff <= normnode; exptopff(1)(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + countadjust; exptopff(2)(10 DOWNTO 1) <= exptopff(1)(10 DOWNTO 1) - ("0000" & countsign); --might not get used expbotff(1)(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); expbotff(2)(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); aasatdelff(1) <= aasat; aazipdelff(1) <= aazip; FOR k IN 2 TO 5 LOOP -- 4&5 might not get used aasatdelff(k) <= aasatdelff(k-1); aazipdelff(k) <= aazipdelff(k-1); END LOOP; END IF; END IF; END PROCESS; nrmc: hcc_normsgn3236 GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, fracin=>aaff(mantissa+10 DOWNTO 11), countout=>countsign, -- stage 1 or 2 fracout=>normfracnode); -- stage 2 or 3 gnb: IF (target = 1) GENERATE gnc: FOR k IN 1 TO mantissa GENERATE normsignnode(k) <= normfracff(k) XOR normfracff(mantissa); END GENERATE; normnode(mantissa-1 DOWNTO 1) <= normsignnode(mantissa-1 DOWNTO 1) + (zerovec(mantissa-2 DOWNTO 1) & normfracff(mantissa)); -- 06/02/08 make sure signbit is packed with the mantissa normnode(mantissa) <= normfracff(mantissa); --*** OUTPUTS *** ccnode(mantissa+10 DOWNTO 11) <= normff; ccnode(10 DOWNTO 1) <= expbotff(normspeed)(10 DOWNTO 1); ccsat <= aasatdelff(3+normspeed); cczip <= aazipdelff(3+normspeed); END GENERATE; gnc: IF (target = 0) GENERATE --*** OUTPUTS *** ccnode(mantissa+10 DOWNTO 11) <= normfracff; gma: IF (normspeed = 1) GENERATE ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); END GENERATE; gmb: IF (normspeed > 1) GENERATE ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); END GENERATE; ccsat <= aasatdelff(2+normspeed); cczip <= aazipdelff(2+normspeed); END GENERATE; gnd: IF (target = 2) GENERATE gaa: IF (roundnormalize = 1) GENERATE normnode <= (normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa DOWNTO 5)) + (zerovec(mantissa-1 DOWNTO 1) & normfracff(4)); END GENERATE; --*** OUTPUTS *** gab: IF (roundnormalize = 0) GENERATE -- 21/03/08 fixed this to SSSSS1XXXXX ccnode(mantissa+10 DOWNTO 11) <= normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa DOWNTO 5); END GENERATE; gac: IF (roundnormalize = 1) GENERATE ccnode(mantissa+10 DOWNTO 11) <= normff; END GENERATE; gad: IF (normspeed = 1 AND roundnormalize = 0) GENERATE ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); END GENERATE; gae: IF ((normspeed = 2 AND roundnormalize = 0) OR (normspeed = 1 AND roundnormalize = 1)) GENERATE ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); END GENERATE; gaf: IF (normspeed = 2 AND roundnormalize = 1) GENERATE ccnode(10 DOWNTO 1) <= expbotff(2)(10 DOWNTO 1); END GENERATE; ccsat <= aasatdelff(2+normspeed+roundnormalize); cczip <= aazipdelff(2+normspeed+roundnormalize); END GENERATE; cc <= ccnode; END GENERATE; --*** DEBUG *** aaexp <= aa(10 DOWNTO 1); aaman <= aa(mantissa+10 DOWNTO 11); ccexp <= ccnode(10 DOWNTO 1); ccman <= ccnode(mantissa+10 DOWNTO 11); END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_NORMFP1X.VHD *** --*** *** --*** Function: Normalize single precision *** --*** number *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** 28/12/07 - divider target uses all of *** --*** mantissa width *** --*** 06/02/08 - fix divider norm *** --*** 21/03/08 - fix add tree output norm *** --*** *** --*************************************************** -- normalize signed numbers (x input format) - for 1x multipliers -- format signed32/36 bit mantissa, 10 bit exponent -- unsigned numbers for divider (S,1,23 bit mantissa for divider) -- divider packed into 32/36bit mantissa + exponent ENTITY hcc_normfp1x IS GENERIC ( mantissa : positive := 32; -- 32 or 36 inputnormalize : integer := 1; -- 0 = scale, 1 = normalize roundnormalize : integer := 1; normspeed : positive := 2; -- 1 or 2 target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); END hcc_normfp1x; ARCHITECTURE rtl OF hcc_normfp1x IS type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal ccnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); -- scale signal aasatff, aazipff : STD_LOGIC; signal countaa : STD_LOGIC_VECTOR (3 DOWNTO 1); -- normalize signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1); signal normfracnode, normnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal normfracff, normff : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal countadjust : STD_LOGIC_VECTOR (10 DOWNTO 1); signal exptopff, expbotff : expfftype; signal aasatdelff, aazipdelff : STD_LOGIC_VECTOR (5 DOWNTO 1); signal countsign : STD_LOGIC_VECTOR (6 DOWNTO 1); signal normsignnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal aaexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1); component hcc_normsgn3236 GENERIC ( mantissa : positive := 32; normspeed : positive := 1 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1) ); end component; component hcc_scmul3236 GENERIC (mantissa : positive := 32); PORT ( frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1); count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1) ); end component; BEGIN --******************************************************** --*** scale multiplier *** --*** multiplier format [S][1][mantissa....] *** --*** one clock latency *** --******************************************************** -- make sure right format & adjust exponent gsa: IF (inputnormalize = 0) GENERATE psa: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; END LOOP; aasatff <= '0'; aazipff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; aasatff <= aasat; aazipff <= aazip; END IF; END IF; END PROCESS; -- no rounding when scaling sma: hcc_scmul3236 GENERIC MAP (mantissa=>mantissa) PORT MAP (frac=>aaff(mantissa+10 DOWNTO 11), scaled=>ccnode(mantissa+10 DOWNTO 11),count=>countaa); ccnode(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + ("0000000" & countaa); cc <= ccnode; ccsat <= aasatff; cczip <= aazipff; END GENERATE; --******************************************************** --*** full normalization of input - 4 stages *** --*** unlike double, no round required on output, as *** --*** no information lost *** --******************************************************** gna: IF (inputnormalize = 1) GENERATE -- normalize gza: FOR k IN 1 TO mantissa-1 GENERATE zerovec(k) <= '0'; END GENERATE; -- if multiplier, "1" which is nominally in position 27, is shifted to position 31 -- add 4 to exponent when multiplier, 0 for adder gxa: IF (target < 2) GENERATE countadjust <= conv_std_logic_vector (4,10); END GENERATE; gxb: IF (target = 2) GENERATE countadjust <= conv_std_logic_vector (4,10); END GENERATE; pna: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; END LOOP; FOR k IN 1 TO mantissa LOOP normfracff(k) <= '0'; normff(k) <= '0'; END LOOP; FOR k IN 1 TO 10 LOOP exptopff(1)(k) <= '0'; exptopff(2)(k) <= '0'; expbotff(1)(k) <= '0'; expbotff(2)(k) <= '0'; END LOOP; FOR k IN 1 TO 5 LOOP aasatdelff(k) <= '0'; aazipdelff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; normfracff <= normfracnode; --might not get used normff <= normnode; exptopff(1)(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + countadjust; exptopff(2)(10 DOWNTO 1) <= exptopff(1)(10 DOWNTO 1) - ("0000" & countsign); --might not get used expbotff(1)(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); expbotff(2)(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); aasatdelff(1) <= aasat; aazipdelff(1) <= aazip; FOR k IN 2 TO 5 LOOP -- 4&5 might not get used aasatdelff(k) <= aasatdelff(k-1); aazipdelff(k) <= aazipdelff(k-1); END LOOP; END IF; END IF; END PROCESS; nrmc: hcc_normsgn3236 GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, fracin=>aaff(mantissa+10 DOWNTO 11), countout=>countsign, -- stage 1 or 2 fracout=>normfracnode); -- stage 2 or 3 gnb: IF (target = 1) GENERATE gnc: FOR k IN 1 TO mantissa GENERATE normsignnode(k) <= normfracff(k) XOR normfracff(mantissa); END GENERATE; normnode(mantissa-1 DOWNTO 1) <= normsignnode(mantissa-1 DOWNTO 1) + (zerovec(mantissa-2 DOWNTO 1) & normfracff(mantissa)); -- 06/02/08 make sure signbit is packed with the mantissa normnode(mantissa) <= normfracff(mantissa); --*** OUTPUTS *** ccnode(mantissa+10 DOWNTO 11) <= normff; ccnode(10 DOWNTO 1) <= expbotff(normspeed)(10 DOWNTO 1); ccsat <= aasatdelff(3+normspeed); cczip <= aazipdelff(3+normspeed); END GENERATE; gnc: IF (target = 0) GENERATE --*** OUTPUTS *** ccnode(mantissa+10 DOWNTO 11) <= normfracff; gma: IF (normspeed = 1) GENERATE ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); END GENERATE; gmb: IF (normspeed > 1) GENERATE ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); END GENERATE; ccsat <= aasatdelff(2+normspeed); cczip <= aazipdelff(2+normspeed); END GENERATE; gnd: IF (target = 2) GENERATE gaa: IF (roundnormalize = 1) GENERATE normnode <= (normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa DOWNTO 5)) + (zerovec(mantissa-1 DOWNTO 1) & normfracff(4)); END GENERATE; --*** OUTPUTS *** gab: IF (roundnormalize = 0) GENERATE -- 21/03/08 fixed this to SSSSS1XXXXX ccnode(mantissa+10 DOWNTO 11) <= normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa DOWNTO 5); END GENERATE; gac: IF (roundnormalize = 1) GENERATE ccnode(mantissa+10 DOWNTO 11) <= normff; END GENERATE; gad: IF (normspeed = 1 AND roundnormalize = 0) GENERATE ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); END GENERATE; gae: IF ((normspeed = 2 AND roundnormalize = 0) OR (normspeed = 1 AND roundnormalize = 1)) GENERATE ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); END GENERATE; gaf: IF (normspeed = 2 AND roundnormalize = 1) GENERATE ccnode(10 DOWNTO 1) <= expbotff(2)(10 DOWNTO 1); END GENERATE; ccsat <= aasatdelff(2+normspeed+roundnormalize); cczip <= aazipdelff(2+normspeed+roundnormalize); END GENERATE; cc <= ccnode; END GENERATE; --*** DEBUG *** aaexp <= aa(10 DOWNTO 1); aaman <= aa(mantissa+10 DOWNTO 11); ccexp <= ccnode(10 DOWNTO 1); ccman <= ccnode(mantissa+10 DOWNTO 11); END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_NORMFP1X.VHD *** --*** *** --*** Function: Normalize single precision *** --*** number *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** 28/12/07 - divider target uses all of *** --*** mantissa width *** --*** 06/02/08 - fix divider norm *** --*** 21/03/08 - fix add tree output norm *** --*** *** --*************************************************** -- normalize signed numbers (x input format) - for 1x multipliers -- format signed32/36 bit mantissa, 10 bit exponent -- unsigned numbers for divider (S,1,23 bit mantissa for divider) -- divider packed into 32/36bit mantissa + exponent ENTITY hcc_normfp1x IS GENERIC ( mantissa : positive := 32; -- 32 or 36 inputnormalize : integer := 1; -- 0 = scale, 1 = normalize roundnormalize : integer := 1; normspeed : positive := 2; -- 1 or 2 target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); END hcc_normfp1x; ARCHITECTURE rtl OF hcc_normfp1x IS type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal ccnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); -- scale signal aasatff, aazipff : STD_LOGIC; signal countaa : STD_LOGIC_VECTOR (3 DOWNTO 1); -- normalize signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1); signal normfracnode, normnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal normfracff, normff : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal countadjust : STD_LOGIC_VECTOR (10 DOWNTO 1); signal exptopff, expbotff : expfftype; signal aasatdelff, aazipdelff : STD_LOGIC_VECTOR (5 DOWNTO 1); signal countsign : STD_LOGIC_VECTOR (6 DOWNTO 1); signal normsignnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal aaexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1); component hcc_normsgn3236 GENERIC ( mantissa : positive := 32; normspeed : positive := 1 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1) ); end component; component hcc_scmul3236 GENERIC (mantissa : positive := 32); PORT ( frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1); count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1) ); end component; BEGIN --******************************************************** --*** scale multiplier *** --*** multiplier format [S][1][mantissa....] *** --*** one clock latency *** --******************************************************** -- make sure right format & adjust exponent gsa: IF (inputnormalize = 0) GENERATE psa: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; END LOOP; aasatff <= '0'; aazipff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; aasatff <= aasat; aazipff <= aazip; END IF; END IF; END PROCESS; -- no rounding when scaling sma: hcc_scmul3236 GENERIC MAP (mantissa=>mantissa) PORT MAP (frac=>aaff(mantissa+10 DOWNTO 11), scaled=>ccnode(mantissa+10 DOWNTO 11),count=>countaa); ccnode(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + ("0000000" & countaa); cc <= ccnode; ccsat <= aasatff; cczip <= aazipff; END GENERATE; --******************************************************** --*** full normalization of input - 4 stages *** --*** unlike double, no round required on output, as *** --*** no information lost *** --******************************************************** gna: IF (inputnormalize = 1) GENERATE -- normalize gza: FOR k IN 1 TO mantissa-1 GENERATE zerovec(k) <= '0'; END GENERATE; -- if multiplier, "1" which is nominally in position 27, is shifted to position 31 -- add 4 to exponent when multiplier, 0 for adder gxa: IF (target < 2) GENERATE countadjust <= conv_std_logic_vector (4,10); END GENERATE; gxb: IF (target = 2) GENERATE countadjust <= conv_std_logic_vector (4,10); END GENERATE; pna: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; END LOOP; FOR k IN 1 TO mantissa LOOP normfracff(k) <= '0'; normff(k) <= '0'; END LOOP; FOR k IN 1 TO 10 LOOP exptopff(1)(k) <= '0'; exptopff(2)(k) <= '0'; expbotff(1)(k) <= '0'; expbotff(2)(k) <= '0'; END LOOP; FOR k IN 1 TO 5 LOOP aasatdelff(k) <= '0'; aazipdelff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; normfracff <= normfracnode; --might not get used normff <= normnode; exptopff(1)(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + countadjust; exptopff(2)(10 DOWNTO 1) <= exptopff(1)(10 DOWNTO 1) - ("0000" & countsign); --might not get used expbotff(1)(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); expbotff(2)(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); aasatdelff(1) <= aasat; aazipdelff(1) <= aazip; FOR k IN 2 TO 5 LOOP -- 4&5 might not get used aasatdelff(k) <= aasatdelff(k-1); aazipdelff(k) <= aazipdelff(k-1); END LOOP; END IF; END IF; END PROCESS; nrmc: hcc_normsgn3236 GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, fracin=>aaff(mantissa+10 DOWNTO 11), countout=>countsign, -- stage 1 or 2 fracout=>normfracnode); -- stage 2 or 3 gnb: IF (target = 1) GENERATE gnc: FOR k IN 1 TO mantissa GENERATE normsignnode(k) <= normfracff(k) XOR normfracff(mantissa); END GENERATE; normnode(mantissa-1 DOWNTO 1) <= normsignnode(mantissa-1 DOWNTO 1) + (zerovec(mantissa-2 DOWNTO 1) & normfracff(mantissa)); -- 06/02/08 make sure signbit is packed with the mantissa normnode(mantissa) <= normfracff(mantissa); --*** OUTPUTS *** ccnode(mantissa+10 DOWNTO 11) <= normff; ccnode(10 DOWNTO 1) <= expbotff(normspeed)(10 DOWNTO 1); ccsat <= aasatdelff(3+normspeed); cczip <= aazipdelff(3+normspeed); END GENERATE; gnc: IF (target = 0) GENERATE --*** OUTPUTS *** ccnode(mantissa+10 DOWNTO 11) <= normfracff; gma: IF (normspeed = 1) GENERATE ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); END GENERATE; gmb: IF (normspeed > 1) GENERATE ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); END GENERATE; ccsat <= aasatdelff(2+normspeed); cczip <= aazipdelff(2+normspeed); END GENERATE; gnd: IF (target = 2) GENERATE gaa: IF (roundnormalize = 1) GENERATE normnode <= (normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa DOWNTO 5)) + (zerovec(mantissa-1 DOWNTO 1) & normfracff(4)); END GENERATE; --*** OUTPUTS *** gab: IF (roundnormalize = 0) GENERATE -- 21/03/08 fixed this to SSSSS1XXXXX ccnode(mantissa+10 DOWNTO 11) <= normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa DOWNTO 5); END GENERATE; gac: IF (roundnormalize = 1) GENERATE ccnode(mantissa+10 DOWNTO 11) <= normff; END GENERATE; gad: IF (normspeed = 1 AND roundnormalize = 0) GENERATE ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); END GENERATE; gae: IF ((normspeed = 2 AND roundnormalize = 0) OR (normspeed = 1 AND roundnormalize = 1)) GENERATE ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); END GENERATE; gaf: IF (normspeed = 2 AND roundnormalize = 1) GENERATE ccnode(10 DOWNTO 1) <= expbotff(2)(10 DOWNTO 1); END GENERATE; ccsat <= aasatdelff(2+normspeed+roundnormalize); cczip <= aazipdelff(2+normspeed+roundnormalize); END GENERATE; cc <= ccnode; END GENERATE; --*** DEBUG *** aaexp <= aa(10 DOWNTO 1); aaman <= aa(mantissa+10 DOWNTO 11); ccexp <= ccnode(10 DOWNTO 1); ccman <= ccnode(mantissa+10 DOWNTO 11); END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_NORMFP1X.VHD *** --*** *** --*** Function: Normalize single precision *** --*** number *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** 28/12/07 - divider target uses all of *** --*** mantissa width *** --*** 06/02/08 - fix divider norm *** --*** 21/03/08 - fix add tree output norm *** --*** *** --*************************************************** -- normalize signed numbers (x input format) - for 1x multipliers -- format signed32/36 bit mantissa, 10 bit exponent -- unsigned numbers for divider (S,1,23 bit mantissa for divider) -- divider packed into 32/36bit mantissa + exponent ENTITY hcc_normfp1x IS GENERIC ( mantissa : positive := 32; -- 32 or 36 inputnormalize : integer := 1; -- 0 = scale, 1 = normalize roundnormalize : integer := 1; normspeed : positive := 2; -- 1 or 2 target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); END hcc_normfp1x; ARCHITECTURE rtl OF hcc_normfp1x IS type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal ccnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); -- scale signal aasatff, aazipff : STD_LOGIC; signal countaa : STD_LOGIC_VECTOR (3 DOWNTO 1); -- normalize signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1); signal normfracnode, normnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal normfracff, normff : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal countadjust : STD_LOGIC_VECTOR (10 DOWNTO 1); signal exptopff, expbotff : expfftype; signal aasatdelff, aazipdelff : STD_LOGIC_VECTOR (5 DOWNTO 1); signal countsign : STD_LOGIC_VECTOR (6 DOWNTO 1); signal normsignnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal aaexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1); component hcc_normsgn3236 GENERIC ( mantissa : positive := 32; normspeed : positive := 1 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1) ); end component; component hcc_scmul3236 GENERIC (mantissa : positive := 32); PORT ( frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1); count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1) ); end component; BEGIN --******************************************************** --*** scale multiplier *** --*** multiplier format [S][1][mantissa....] *** --*** one clock latency *** --******************************************************** -- make sure right format & adjust exponent gsa: IF (inputnormalize = 0) GENERATE psa: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; END LOOP; aasatff <= '0'; aazipff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; aasatff <= aasat; aazipff <= aazip; END IF; END IF; END PROCESS; -- no rounding when scaling sma: hcc_scmul3236 GENERIC MAP (mantissa=>mantissa) PORT MAP (frac=>aaff(mantissa+10 DOWNTO 11), scaled=>ccnode(mantissa+10 DOWNTO 11),count=>countaa); ccnode(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + ("0000000" & countaa); cc <= ccnode; ccsat <= aasatff; cczip <= aazipff; END GENERATE; --******************************************************** --*** full normalization of input - 4 stages *** --*** unlike double, no round required on output, as *** --*** no information lost *** --******************************************************** gna: IF (inputnormalize = 1) GENERATE -- normalize gza: FOR k IN 1 TO mantissa-1 GENERATE zerovec(k) <= '0'; END GENERATE; -- if multiplier, "1" which is nominally in position 27, is shifted to position 31 -- add 4 to exponent when multiplier, 0 for adder gxa: IF (target < 2) GENERATE countadjust <= conv_std_logic_vector (4,10); END GENERATE; gxb: IF (target = 2) GENERATE countadjust <= conv_std_logic_vector (4,10); END GENERATE; pna: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; END LOOP; FOR k IN 1 TO mantissa LOOP normfracff(k) <= '0'; normff(k) <= '0'; END LOOP; FOR k IN 1 TO 10 LOOP exptopff(1)(k) <= '0'; exptopff(2)(k) <= '0'; expbotff(1)(k) <= '0'; expbotff(2)(k) <= '0'; END LOOP; FOR k IN 1 TO 5 LOOP aasatdelff(k) <= '0'; aazipdelff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; normfracff <= normfracnode; --might not get used normff <= normnode; exptopff(1)(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + countadjust; exptopff(2)(10 DOWNTO 1) <= exptopff(1)(10 DOWNTO 1) - ("0000" & countsign); --might not get used expbotff(1)(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); expbotff(2)(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); aasatdelff(1) <= aasat; aazipdelff(1) <= aazip; FOR k IN 2 TO 5 LOOP -- 4&5 might not get used aasatdelff(k) <= aasatdelff(k-1); aazipdelff(k) <= aazipdelff(k-1); END LOOP; END IF; END IF; END PROCESS; nrmc: hcc_normsgn3236 GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, fracin=>aaff(mantissa+10 DOWNTO 11), countout=>countsign, -- stage 1 or 2 fracout=>normfracnode); -- stage 2 or 3 gnb: IF (target = 1) GENERATE gnc: FOR k IN 1 TO mantissa GENERATE normsignnode(k) <= normfracff(k) XOR normfracff(mantissa); END GENERATE; normnode(mantissa-1 DOWNTO 1) <= normsignnode(mantissa-1 DOWNTO 1) + (zerovec(mantissa-2 DOWNTO 1) & normfracff(mantissa)); -- 06/02/08 make sure signbit is packed with the mantissa normnode(mantissa) <= normfracff(mantissa); --*** OUTPUTS *** ccnode(mantissa+10 DOWNTO 11) <= normff; ccnode(10 DOWNTO 1) <= expbotff(normspeed)(10 DOWNTO 1); ccsat <= aasatdelff(3+normspeed); cczip <= aazipdelff(3+normspeed); END GENERATE; gnc: IF (target = 0) GENERATE --*** OUTPUTS *** ccnode(mantissa+10 DOWNTO 11) <= normfracff; gma: IF (normspeed = 1) GENERATE ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); END GENERATE; gmb: IF (normspeed > 1) GENERATE ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); END GENERATE; ccsat <= aasatdelff(2+normspeed); cczip <= aazipdelff(2+normspeed); END GENERATE; gnd: IF (target = 2) GENERATE gaa: IF (roundnormalize = 1) GENERATE normnode <= (normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa DOWNTO 5)) + (zerovec(mantissa-1 DOWNTO 1) & normfracff(4)); END GENERATE; --*** OUTPUTS *** gab: IF (roundnormalize = 0) GENERATE -- 21/03/08 fixed this to SSSSS1XXXXX ccnode(mantissa+10 DOWNTO 11) <= normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa DOWNTO 5); END GENERATE; gac: IF (roundnormalize = 1) GENERATE ccnode(mantissa+10 DOWNTO 11) <= normff; END GENERATE; gad: IF (normspeed = 1 AND roundnormalize = 0) GENERATE ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); END GENERATE; gae: IF ((normspeed = 2 AND roundnormalize = 0) OR (normspeed = 1 AND roundnormalize = 1)) GENERATE ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); END GENERATE; gaf: IF (normspeed = 2 AND roundnormalize = 1) GENERATE ccnode(10 DOWNTO 1) <= expbotff(2)(10 DOWNTO 1); END GENERATE; ccsat <= aasatdelff(2+normspeed+roundnormalize); cczip <= aazipdelff(2+normspeed+roundnormalize); END GENERATE; cc <= ccnode; END GENERATE; --*** DEBUG *** aaexp <= aa(10 DOWNTO 1); aaman <= aa(mantissa+10 DOWNTO 11); ccexp <= ccnode(10 DOWNTO 1); ccman <= ccnode(mantissa+10 DOWNTO 11); END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_NORMFP1X.VHD *** --*** *** --*** Function: Normalize single precision *** --*** number *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** 28/12/07 - divider target uses all of *** --*** mantissa width *** --*** 06/02/08 - fix divider norm *** --*** 21/03/08 - fix add tree output norm *** --*** *** --*************************************************** -- normalize signed numbers (x input format) - for 1x multipliers -- format signed32/36 bit mantissa, 10 bit exponent -- unsigned numbers for divider (S,1,23 bit mantissa for divider) -- divider packed into 32/36bit mantissa + exponent ENTITY hcc_normfp1x IS GENERIC ( mantissa : positive := 32; -- 32 or 36 inputnormalize : integer := 1; -- 0 = scale, 1 = normalize roundnormalize : integer := 1; normspeed : positive := 2; -- 1 or 2 target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); END hcc_normfp1x; ARCHITECTURE rtl OF hcc_normfp1x IS type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal ccnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); -- scale signal aasatff, aazipff : STD_LOGIC; signal countaa : STD_LOGIC_VECTOR (3 DOWNTO 1); -- normalize signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1); signal normfracnode, normnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal normfracff, normff : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal countadjust : STD_LOGIC_VECTOR (10 DOWNTO 1); signal exptopff, expbotff : expfftype; signal aasatdelff, aazipdelff : STD_LOGIC_VECTOR (5 DOWNTO 1); signal countsign : STD_LOGIC_VECTOR (6 DOWNTO 1); signal normsignnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal aaexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1); component hcc_normsgn3236 GENERIC ( mantissa : positive := 32; normspeed : positive := 1 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1) ); end component; component hcc_scmul3236 GENERIC (mantissa : positive := 32); PORT ( frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1); count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1) ); end component; BEGIN --******************************************************** --*** scale multiplier *** --*** multiplier format [S][1][mantissa....] *** --*** one clock latency *** --******************************************************** -- make sure right format & adjust exponent gsa: IF (inputnormalize = 0) GENERATE psa: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; END LOOP; aasatff <= '0'; aazipff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; aasatff <= aasat; aazipff <= aazip; END IF; END IF; END PROCESS; -- no rounding when scaling sma: hcc_scmul3236 GENERIC MAP (mantissa=>mantissa) PORT MAP (frac=>aaff(mantissa+10 DOWNTO 11), scaled=>ccnode(mantissa+10 DOWNTO 11),count=>countaa); ccnode(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + ("0000000" & countaa); cc <= ccnode; ccsat <= aasatff; cczip <= aazipff; END GENERATE; --******************************************************** --*** full normalization of input - 4 stages *** --*** unlike double, no round required on output, as *** --*** no information lost *** --******************************************************** gna: IF (inputnormalize = 1) GENERATE -- normalize gza: FOR k IN 1 TO mantissa-1 GENERATE zerovec(k) <= '0'; END GENERATE; -- if multiplier, "1" which is nominally in position 27, is shifted to position 31 -- add 4 to exponent when multiplier, 0 for adder gxa: IF (target < 2) GENERATE countadjust <= conv_std_logic_vector (4,10); END GENERATE; gxb: IF (target = 2) GENERATE countadjust <= conv_std_logic_vector (4,10); END GENERATE; pna: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; END LOOP; FOR k IN 1 TO mantissa LOOP normfracff(k) <= '0'; normff(k) <= '0'; END LOOP; FOR k IN 1 TO 10 LOOP exptopff(1)(k) <= '0'; exptopff(2)(k) <= '0'; expbotff(1)(k) <= '0'; expbotff(2)(k) <= '0'; END LOOP; FOR k IN 1 TO 5 LOOP aasatdelff(k) <= '0'; aazipdelff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; normfracff <= normfracnode; --might not get used normff <= normnode; exptopff(1)(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + countadjust; exptopff(2)(10 DOWNTO 1) <= exptopff(1)(10 DOWNTO 1) - ("0000" & countsign); --might not get used expbotff(1)(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); expbotff(2)(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); aasatdelff(1) <= aasat; aazipdelff(1) <= aazip; FOR k IN 2 TO 5 LOOP -- 4&5 might not get used aasatdelff(k) <= aasatdelff(k-1); aazipdelff(k) <= aazipdelff(k-1); END LOOP; END IF; END IF; END PROCESS; nrmc: hcc_normsgn3236 GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, fracin=>aaff(mantissa+10 DOWNTO 11), countout=>countsign, -- stage 1 or 2 fracout=>normfracnode); -- stage 2 or 3 gnb: IF (target = 1) GENERATE gnc: FOR k IN 1 TO mantissa GENERATE normsignnode(k) <= normfracff(k) XOR normfracff(mantissa); END GENERATE; normnode(mantissa-1 DOWNTO 1) <= normsignnode(mantissa-1 DOWNTO 1) + (zerovec(mantissa-2 DOWNTO 1) & normfracff(mantissa)); -- 06/02/08 make sure signbit is packed with the mantissa normnode(mantissa) <= normfracff(mantissa); --*** OUTPUTS *** ccnode(mantissa+10 DOWNTO 11) <= normff; ccnode(10 DOWNTO 1) <= expbotff(normspeed)(10 DOWNTO 1); ccsat <= aasatdelff(3+normspeed); cczip <= aazipdelff(3+normspeed); END GENERATE; gnc: IF (target = 0) GENERATE --*** OUTPUTS *** ccnode(mantissa+10 DOWNTO 11) <= normfracff; gma: IF (normspeed = 1) GENERATE ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); END GENERATE; gmb: IF (normspeed > 1) GENERATE ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); END GENERATE; ccsat <= aasatdelff(2+normspeed); cczip <= aazipdelff(2+normspeed); END GENERATE; gnd: IF (target = 2) GENERATE gaa: IF (roundnormalize = 1) GENERATE normnode <= (normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa DOWNTO 5)) + (zerovec(mantissa-1 DOWNTO 1) & normfracff(4)); END GENERATE; --*** OUTPUTS *** gab: IF (roundnormalize = 0) GENERATE -- 21/03/08 fixed this to SSSSS1XXXXX ccnode(mantissa+10 DOWNTO 11) <= normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa DOWNTO 5); END GENERATE; gac: IF (roundnormalize = 1) GENERATE ccnode(mantissa+10 DOWNTO 11) <= normff; END GENERATE; gad: IF (normspeed = 1 AND roundnormalize = 0) GENERATE ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); END GENERATE; gae: IF ((normspeed = 2 AND roundnormalize = 0) OR (normspeed = 1 AND roundnormalize = 1)) GENERATE ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); END GENERATE; gaf: IF (normspeed = 2 AND roundnormalize = 1) GENERATE ccnode(10 DOWNTO 1) <= expbotff(2)(10 DOWNTO 1); END GENERATE; ccsat <= aasatdelff(2+normspeed+roundnormalize); cczip <= aazipdelff(2+normspeed+roundnormalize); END GENERATE; cc <= ccnode; END GENERATE; --*** DEBUG *** aaexp <= aa(10 DOWNTO 1); aaman <= aa(mantissa+10 DOWNTO 11); ccexp <= ccnode(10 DOWNTO 1); ccman <= ccnode(mantissa+10 DOWNTO 11); END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_NORMFP1X.VHD *** --*** *** --*** Function: Normalize single precision *** --*** number *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** 28/12/07 - divider target uses all of *** --*** mantissa width *** --*** 06/02/08 - fix divider norm *** --*** 21/03/08 - fix add tree output norm *** --*** *** --*************************************************** -- normalize signed numbers (x input format) - for 1x multipliers -- format signed32/36 bit mantissa, 10 bit exponent -- unsigned numbers for divider (S,1,23 bit mantissa for divider) -- divider packed into 32/36bit mantissa + exponent ENTITY hcc_normfp1x IS GENERIC ( mantissa : positive := 32; -- 32 or 36 inputnormalize : integer := 1; -- 0 = scale, 1 = normalize roundnormalize : integer := 1; normspeed : positive := 2; -- 1 or 2 target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); END hcc_normfp1x; ARCHITECTURE rtl OF hcc_normfp1x IS type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal ccnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); -- scale signal aasatff, aazipff : STD_LOGIC; signal countaa : STD_LOGIC_VECTOR (3 DOWNTO 1); -- normalize signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1); signal normfracnode, normnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal normfracff, normff : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal countadjust : STD_LOGIC_VECTOR (10 DOWNTO 1); signal exptopff, expbotff : expfftype; signal aasatdelff, aazipdelff : STD_LOGIC_VECTOR (5 DOWNTO 1); signal countsign : STD_LOGIC_VECTOR (6 DOWNTO 1); signal normsignnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal aaexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1); component hcc_normsgn3236 GENERIC ( mantissa : positive := 32; normspeed : positive := 1 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1) ); end component; component hcc_scmul3236 GENERIC (mantissa : positive := 32); PORT ( frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1); count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1) ); end component; BEGIN --******************************************************** --*** scale multiplier *** --*** multiplier format [S][1][mantissa....] *** --*** one clock latency *** --******************************************************** -- make sure right format & adjust exponent gsa: IF (inputnormalize = 0) GENERATE psa: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; END LOOP; aasatff <= '0'; aazipff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; aasatff <= aasat; aazipff <= aazip; END IF; END IF; END PROCESS; -- no rounding when scaling sma: hcc_scmul3236 GENERIC MAP (mantissa=>mantissa) PORT MAP (frac=>aaff(mantissa+10 DOWNTO 11), scaled=>ccnode(mantissa+10 DOWNTO 11),count=>countaa); ccnode(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + ("0000000" & countaa); cc <= ccnode; ccsat <= aasatff; cczip <= aazipff; END GENERATE; --******************************************************** --*** full normalization of input - 4 stages *** --*** unlike double, no round required on output, as *** --*** no information lost *** --******************************************************** gna: IF (inputnormalize = 1) GENERATE -- normalize gza: FOR k IN 1 TO mantissa-1 GENERATE zerovec(k) <= '0'; END GENERATE; -- if multiplier, "1" which is nominally in position 27, is shifted to position 31 -- add 4 to exponent when multiplier, 0 for adder gxa: IF (target < 2) GENERATE countadjust <= conv_std_logic_vector (4,10); END GENERATE; gxb: IF (target = 2) GENERATE countadjust <= conv_std_logic_vector (4,10); END GENERATE; pna: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; END LOOP; FOR k IN 1 TO mantissa LOOP normfracff(k) <= '0'; normff(k) <= '0'; END LOOP; FOR k IN 1 TO 10 LOOP exptopff(1)(k) <= '0'; exptopff(2)(k) <= '0'; expbotff(1)(k) <= '0'; expbotff(2)(k) <= '0'; END LOOP; FOR k IN 1 TO 5 LOOP aasatdelff(k) <= '0'; aazipdelff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; normfracff <= normfracnode; --might not get used normff <= normnode; exptopff(1)(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + countadjust; exptopff(2)(10 DOWNTO 1) <= exptopff(1)(10 DOWNTO 1) - ("0000" & countsign); --might not get used expbotff(1)(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); expbotff(2)(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); aasatdelff(1) <= aasat; aazipdelff(1) <= aazip; FOR k IN 2 TO 5 LOOP -- 4&5 might not get used aasatdelff(k) <= aasatdelff(k-1); aazipdelff(k) <= aazipdelff(k-1); END LOOP; END IF; END IF; END PROCESS; nrmc: hcc_normsgn3236 GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, fracin=>aaff(mantissa+10 DOWNTO 11), countout=>countsign, -- stage 1 or 2 fracout=>normfracnode); -- stage 2 or 3 gnb: IF (target = 1) GENERATE gnc: FOR k IN 1 TO mantissa GENERATE normsignnode(k) <= normfracff(k) XOR normfracff(mantissa); END GENERATE; normnode(mantissa-1 DOWNTO 1) <= normsignnode(mantissa-1 DOWNTO 1) + (zerovec(mantissa-2 DOWNTO 1) & normfracff(mantissa)); -- 06/02/08 make sure signbit is packed with the mantissa normnode(mantissa) <= normfracff(mantissa); --*** OUTPUTS *** ccnode(mantissa+10 DOWNTO 11) <= normff; ccnode(10 DOWNTO 1) <= expbotff(normspeed)(10 DOWNTO 1); ccsat <= aasatdelff(3+normspeed); cczip <= aazipdelff(3+normspeed); END GENERATE; gnc: IF (target = 0) GENERATE --*** OUTPUTS *** ccnode(mantissa+10 DOWNTO 11) <= normfracff; gma: IF (normspeed = 1) GENERATE ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); END GENERATE; gmb: IF (normspeed > 1) GENERATE ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); END GENERATE; ccsat <= aasatdelff(2+normspeed); cczip <= aazipdelff(2+normspeed); END GENERATE; gnd: IF (target = 2) GENERATE gaa: IF (roundnormalize = 1) GENERATE normnode <= (normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa DOWNTO 5)) + (zerovec(mantissa-1 DOWNTO 1) & normfracff(4)); END GENERATE; --*** OUTPUTS *** gab: IF (roundnormalize = 0) GENERATE -- 21/03/08 fixed this to SSSSS1XXXXX ccnode(mantissa+10 DOWNTO 11) <= normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa DOWNTO 5); END GENERATE; gac: IF (roundnormalize = 1) GENERATE ccnode(mantissa+10 DOWNTO 11) <= normff; END GENERATE; gad: IF (normspeed = 1 AND roundnormalize = 0) GENERATE ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); END GENERATE; gae: IF ((normspeed = 2 AND roundnormalize = 0) OR (normspeed = 1 AND roundnormalize = 1)) GENERATE ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); END GENERATE; gaf: IF (normspeed = 2 AND roundnormalize = 1) GENERATE ccnode(10 DOWNTO 1) <= expbotff(2)(10 DOWNTO 1); END GENERATE; ccsat <= aasatdelff(2+normspeed+roundnormalize); cczip <= aazipdelff(2+normspeed+roundnormalize); END GENERATE; cc <= ccnode; END GENERATE; --*** DEBUG *** aaexp <= aa(10 DOWNTO 1); aaman <= aa(mantissa+10 DOWNTO 11); ccexp <= ccnode(10 DOWNTO 1); ccman <= ccnode(mantissa+10 DOWNTO 11); END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_NORMFP1X.VHD *** --*** *** --*** Function: Normalize single precision *** --*** number *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** 28/12/07 - divider target uses all of *** --*** mantissa width *** --*** 06/02/08 - fix divider norm *** --*** 21/03/08 - fix add tree output norm *** --*** *** --*************************************************** -- normalize signed numbers (x input format) - for 1x multipliers -- format signed32/36 bit mantissa, 10 bit exponent -- unsigned numbers for divider (S,1,23 bit mantissa for divider) -- divider packed into 32/36bit mantissa + exponent ENTITY hcc_normfp1x IS GENERIC ( mantissa : positive := 32; -- 32 or 36 inputnormalize : integer := 1; -- 0 = scale, 1 = normalize roundnormalize : integer := 1; normspeed : positive := 2; -- 1 or 2 target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); END hcc_normfp1x; ARCHITECTURE rtl OF hcc_normfp1x IS type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal ccnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); -- scale signal aasatff, aazipff : STD_LOGIC; signal countaa : STD_LOGIC_VECTOR (3 DOWNTO 1); -- normalize signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1); signal normfracnode, normnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal normfracff, normff : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal countadjust : STD_LOGIC_VECTOR (10 DOWNTO 1); signal exptopff, expbotff : expfftype; signal aasatdelff, aazipdelff : STD_LOGIC_VECTOR (5 DOWNTO 1); signal countsign : STD_LOGIC_VECTOR (6 DOWNTO 1); signal normsignnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal aaexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1); component hcc_normsgn3236 GENERIC ( mantissa : positive := 32; normspeed : positive := 1 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1) ); end component; component hcc_scmul3236 GENERIC (mantissa : positive := 32); PORT ( frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1); count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1) ); end component; BEGIN --******************************************************** --*** scale multiplier *** --*** multiplier format [S][1][mantissa....] *** --*** one clock latency *** --******************************************************** -- make sure right format & adjust exponent gsa: IF (inputnormalize = 0) GENERATE psa: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; END LOOP; aasatff <= '0'; aazipff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; aasatff <= aasat; aazipff <= aazip; END IF; END IF; END PROCESS; -- no rounding when scaling sma: hcc_scmul3236 GENERIC MAP (mantissa=>mantissa) PORT MAP (frac=>aaff(mantissa+10 DOWNTO 11), scaled=>ccnode(mantissa+10 DOWNTO 11),count=>countaa); ccnode(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + ("0000000" & countaa); cc <= ccnode; ccsat <= aasatff; cczip <= aazipff; END GENERATE; --******************************************************** --*** full normalization of input - 4 stages *** --*** unlike double, no round required on output, as *** --*** no information lost *** --******************************************************** gna: IF (inputnormalize = 1) GENERATE -- normalize gza: FOR k IN 1 TO mantissa-1 GENERATE zerovec(k) <= '0'; END GENERATE; -- if multiplier, "1" which is nominally in position 27, is shifted to position 31 -- add 4 to exponent when multiplier, 0 for adder gxa: IF (target < 2) GENERATE countadjust <= conv_std_logic_vector (4,10); END GENERATE; gxb: IF (target = 2) GENERATE countadjust <= conv_std_logic_vector (4,10); END GENERATE; pna: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; END LOOP; FOR k IN 1 TO mantissa LOOP normfracff(k) <= '0'; normff(k) <= '0'; END LOOP; FOR k IN 1 TO 10 LOOP exptopff(1)(k) <= '0'; exptopff(2)(k) <= '0'; expbotff(1)(k) <= '0'; expbotff(2)(k) <= '0'; END LOOP; FOR k IN 1 TO 5 LOOP aasatdelff(k) <= '0'; aazipdelff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; normfracff <= normfracnode; --might not get used normff <= normnode; exptopff(1)(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + countadjust; exptopff(2)(10 DOWNTO 1) <= exptopff(1)(10 DOWNTO 1) - ("0000" & countsign); --might not get used expbotff(1)(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); expbotff(2)(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); aasatdelff(1) <= aasat; aazipdelff(1) <= aazip; FOR k IN 2 TO 5 LOOP -- 4&5 might not get used aasatdelff(k) <= aasatdelff(k-1); aazipdelff(k) <= aazipdelff(k-1); END LOOP; END IF; END IF; END PROCESS; nrmc: hcc_normsgn3236 GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, fracin=>aaff(mantissa+10 DOWNTO 11), countout=>countsign, -- stage 1 or 2 fracout=>normfracnode); -- stage 2 or 3 gnb: IF (target = 1) GENERATE gnc: FOR k IN 1 TO mantissa GENERATE normsignnode(k) <= normfracff(k) XOR normfracff(mantissa); END GENERATE; normnode(mantissa-1 DOWNTO 1) <= normsignnode(mantissa-1 DOWNTO 1) + (zerovec(mantissa-2 DOWNTO 1) & normfracff(mantissa)); -- 06/02/08 make sure signbit is packed with the mantissa normnode(mantissa) <= normfracff(mantissa); --*** OUTPUTS *** ccnode(mantissa+10 DOWNTO 11) <= normff; ccnode(10 DOWNTO 1) <= expbotff(normspeed)(10 DOWNTO 1); ccsat <= aasatdelff(3+normspeed); cczip <= aazipdelff(3+normspeed); END GENERATE; gnc: IF (target = 0) GENERATE --*** OUTPUTS *** ccnode(mantissa+10 DOWNTO 11) <= normfracff; gma: IF (normspeed = 1) GENERATE ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); END GENERATE; gmb: IF (normspeed > 1) GENERATE ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); END GENERATE; ccsat <= aasatdelff(2+normspeed); cczip <= aazipdelff(2+normspeed); END GENERATE; gnd: IF (target = 2) GENERATE gaa: IF (roundnormalize = 1) GENERATE normnode <= (normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa DOWNTO 5)) + (zerovec(mantissa-1 DOWNTO 1) & normfracff(4)); END GENERATE; --*** OUTPUTS *** gab: IF (roundnormalize = 0) GENERATE -- 21/03/08 fixed this to SSSSS1XXXXX ccnode(mantissa+10 DOWNTO 11) <= normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa DOWNTO 5); END GENERATE; gac: IF (roundnormalize = 1) GENERATE ccnode(mantissa+10 DOWNTO 11) <= normff; END GENERATE; gad: IF (normspeed = 1 AND roundnormalize = 0) GENERATE ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); END GENERATE; gae: IF ((normspeed = 2 AND roundnormalize = 0) OR (normspeed = 1 AND roundnormalize = 1)) GENERATE ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); END GENERATE; gaf: IF (normspeed = 2 AND roundnormalize = 1) GENERATE ccnode(10 DOWNTO 1) <= expbotff(2)(10 DOWNTO 1); END GENERATE; ccsat <= aasatdelff(2+normspeed+roundnormalize); cczip <= aazipdelff(2+normspeed+roundnormalize); END GENERATE; cc <= ccnode; END GENERATE; --*** DEBUG *** aaexp <= aa(10 DOWNTO 1); aaman <= aa(mantissa+10 DOWNTO 11); ccexp <= ccnode(10 DOWNTO 1); ccman <= ccnode(mantissa+10 DOWNTO 11); END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_NORMFP1X.VHD *** --*** *** --*** Function: Normalize single precision *** --*** number *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** 28/12/07 - divider target uses all of *** --*** mantissa width *** --*** 06/02/08 - fix divider norm *** --*** 21/03/08 - fix add tree output norm *** --*** *** --*************************************************** -- normalize signed numbers (x input format) - for 1x multipliers -- format signed32/36 bit mantissa, 10 bit exponent -- unsigned numbers for divider (S,1,23 bit mantissa for divider) -- divider packed into 32/36bit mantissa + exponent ENTITY hcc_normfp1x IS GENERIC ( mantissa : positive := 32; -- 32 or 36 inputnormalize : integer := 1; -- 0 = scale, 1 = normalize roundnormalize : integer := 1; normspeed : positive := 2; -- 1 or 2 target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); END hcc_normfp1x; ARCHITECTURE rtl OF hcc_normfp1x IS type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal ccnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); -- scale signal aasatff, aazipff : STD_LOGIC; signal countaa : STD_LOGIC_VECTOR (3 DOWNTO 1); -- normalize signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1); signal normfracnode, normnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal normfracff, normff : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal countadjust : STD_LOGIC_VECTOR (10 DOWNTO 1); signal exptopff, expbotff : expfftype; signal aasatdelff, aazipdelff : STD_LOGIC_VECTOR (5 DOWNTO 1); signal countsign : STD_LOGIC_VECTOR (6 DOWNTO 1); signal normsignnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal aaexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1); component hcc_normsgn3236 GENERIC ( mantissa : positive := 32; normspeed : positive := 1 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1) ); end component; component hcc_scmul3236 GENERIC (mantissa : positive := 32); PORT ( frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1); count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1) ); end component; BEGIN --******************************************************** --*** scale multiplier *** --*** multiplier format [S][1][mantissa....] *** --*** one clock latency *** --******************************************************** -- make sure right format & adjust exponent gsa: IF (inputnormalize = 0) GENERATE psa: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; END LOOP; aasatff <= '0'; aazipff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; aasatff <= aasat; aazipff <= aazip; END IF; END IF; END PROCESS; -- no rounding when scaling sma: hcc_scmul3236 GENERIC MAP (mantissa=>mantissa) PORT MAP (frac=>aaff(mantissa+10 DOWNTO 11), scaled=>ccnode(mantissa+10 DOWNTO 11),count=>countaa); ccnode(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + ("0000000" & countaa); cc <= ccnode; ccsat <= aasatff; cczip <= aazipff; END GENERATE; --******************************************************** --*** full normalization of input - 4 stages *** --*** unlike double, no round required on output, as *** --*** no information lost *** --******************************************************** gna: IF (inputnormalize = 1) GENERATE -- normalize gza: FOR k IN 1 TO mantissa-1 GENERATE zerovec(k) <= '0'; END GENERATE; -- if multiplier, "1" which is nominally in position 27, is shifted to position 31 -- add 4 to exponent when multiplier, 0 for adder gxa: IF (target < 2) GENERATE countadjust <= conv_std_logic_vector (4,10); END GENERATE; gxb: IF (target = 2) GENERATE countadjust <= conv_std_logic_vector (4,10); END GENERATE; pna: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; END LOOP; FOR k IN 1 TO mantissa LOOP normfracff(k) <= '0'; normff(k) <= '0'; END LOOP; FOR k IN 1 TO 10 LOOP exptopff(1)(k) <= '0'; exptopff(2)(k) <= '0'; expbotff(1)(k) <= '0'; expbotff(2)(k) <= '0'; END LOOP; FOR k IN 1 TO 5 LOOP aasatdelff(k) <= '0'; aazipdelff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; normfracff <= normfracnode; --might not get used normff <= normnode; exptopff(1)(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + countadjust; exptopff(2)(10 DOWNTO 1) <= exptopff(1)(10 DOWNTO 1) - ("0000" & countsign); --might not get used expbotff(1)(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); expbotff(2)(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); aasatdelff(1) <= aasat; aazipdelff(1) <= aazip; FOR k IN 2 TO 5 LOOP -- 4&5 might not get used aasatdelff(k) <= aasatdelff(k-1); aazipdelff(k) <= aazipdelff(k-1); END LOOP; END IF; END IF; END PROCESS; nrmc: hcc_normsgn3236 GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, fracin=>aaff(mantissa+10 DOWNTO 11), countout=>countsign, -- stage 1 or 2 fracout=>normfracnode); -- stage 2 or 3 gnb: IF (target = 1) GENERATE gnc: FOR k IN 1 TO mantissa GENERATE normsignnode(k) <= normfracff(k) XOR normfracff(mantissa); END GENERATE; normnode(mantissa-1 DOWNTO 1) <= normsignnode(mantissa-1 DOWNTO 1) + (zerovec(mantissa-2 DOWNTO 1) & normfracff(mantissa)); -- 06/02/08 make sure signbit is packed with the mantissa normnode(mantissa) <= normfracff(mantissa); --*** OUTPUTS *** ccnode(mantissa+10 DOWNTO 11) <= normff; ccnode(10 DOWNTO 1) <= expbotff(normspeed)(10 DOWNTO 1); ccsat <= aasatdelff(3+normspeed); cczip <= aazipdelff(3+normspeed); END GENERATE; gnc: IF (target = 0) GENERATE --*** OUTPUTS *** ccnode(mantissa+10 DOWNTO 11) <= normfracff; gma: IF (normspeed = 1) GENERATE ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); END GENERATE; gmb: IF (normspeed > 1) GENERATE ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); END GENERATE; ccsat <= aasatdelff(2+normspeed); cczip <= aazipdelff(2+normspeed); END GENERATE; gnd: IF (target = 2) GENERATE gaa: IF (roundnormalize = 1) GENERATE normnode <= (normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa DOWNTO 5)) + (zerovec(mantissa-1 DOWNTO 1) & normfracff(4)); END GENERATE; --*** OUTPUTS *** gab: IF (roundnormalize = 0) GENERATE -- 21/03/08 fixed this to SSSSS1XXXXX ccnode(mantissa+10 DOWNTO 11) <= normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa DOWNTO 5); END GENERATE; gac: IF (roundnormalize = 1) GENERATE ccnode(mantissa+10 DOWNTO 11) <= normff; END GENERATE; gad: IF (normspeed = 1 AND roundnormalize = 0) GENERATE ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1); END GENERATE; gae: IF ((normspeed = 2 AND roundnormalize = 0) OR (normspeed = 1 AND roundnormalize = 1)) GENERATE ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); END GENERATE; gaf: IF (normspeed = 2 AND roundnormalize = 1) GENERATE ccnode(10 DOWNTO 1) <= expbotff(2)(10 DOWNTO 1); END GENERATE; ccsat <= aasatdelff(2+normspeed+roundnormalize); cczip <= aazipdelff(2+normspeed+roundnormalize); END GENERATE; cc <= ccnode; END GENERATE; --*** DEBUG *** aaexp <= aa(10 DOWNTO 1); aaman <= aa(mantissa+10 DOWNTO 11); ccexp <= ccnode(10 DOWNTO 1); ccman <= ccnode(mantissa+10 DOWNTO 11); END rtl;
-- --ROMsUsingBlockRAMResources. --VHDLcodeforaROMwithregisteredoutput(template2) -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity os16 is port( clock:in std_logic; address:in std_logic_vector(13 downto 0); q:out std_logic_vector(7 downto 0) ); end os16; architecture syn of os16 is type rom_type is array(0 to 16383) of std_logic_vector(7 downto 0); signal ROM:rom_type:= ( X"11", X"92", X"10", X"05", X"83", X"00", X"42", X"42", X"00", X"00", X"01", X"02", X"a9", X"40", X"8d", X"0e", X"d4", X"ad", X"13", X"d0", X"8d", X"fa", X"03", X"60", X"2c", X"0f", X"d4", X"10", X"03", X"6c", X"00", X"02", X"d8", X"48", X"8a", X"48", X"98", X"48", X"8d", X"0f", X"d4", X"6c", X"22", X"02", X"d8", X"6c", X"16", X"02", X"48", X"ad", X"0e", X"d2", X"29", X"20", X"d0", X"0d", X"a9", X"df", X"8d", X"0e", X"d2", X"a5", X"10", X"8d", X"0e", X"d2", X"6c", X"0a", X"02", X"8a", X"48", X"ad", X"ff", X"d1", X"2d", X"49", X"02", X"f0", X"03", X"6c", X"38", X"02", X"a2", X"06", X"bd", X"cf", X"c0", X"e0", X"05", X"d0", X"04", X"25", X"10", X"f0", X"05", X"2c", X"0e", X"d2", X"f0", X"06", X"ca", X"10", X"ed", X"4c", X"a0", X"c0", X"49", X"ff", X"8d", X"0e", X"d2", X"a5", X"10", X"8d", X"0e", X"d2", X"e0", X"00", X"d0", X"05", X"ad", X"6d", X"02", X"d0", X"23", X"bd", X"d7", X"c0", X"aa", X"bd", X"00", X"02", X"8d", X"8c", X"02", X"bd", X"01", X"02", X"8d", X"8d", X"02", X"68", X"aa", X"6c", X"8c", X"02", X"a9", X"00", X"85", X"11", X"8d", X"ff", X"02", X"8d", X"f0", X"02", X"85", X"4d", X"68", X"40", X"68", X"aa", X"2c", X"02", X"d3", X"10", X"06", X"ad", X"00", X"d3", X"6c", X"02", X"02", X"2c", X"03", X"d3", X"10", X"06", X"ad", X"01", X"d3", X"6c", X"04", X"02", X"68", X"8d", X"8c", X"02", X"68", X"48", X"29", X"10", X"f0", X"07", X"ad", X"8c", X"02", X"48", X"6c", X"06", X"02", X"ad", X"8c", X"02", X"48", X"68", X"40", X"80", X"40", X"04", X"02", X"01", X"08", X"10", X"20", X"36", X"08", X"14", X"12", X"10", X"0e", X"0c", X"0a", X"4c", X"df", X"c0", X"e6", X"14", X"d0", X"08", X"e6", X"4d", X"e6", X"13", X"d0", X"02", X"e6", X"12", X"a9", X"fe", X"a2", X"00", X"a4", X"4d", X"10", X"06", X"85", X"4d", X"a6", X"13", X"a9", X"f6", X"85", X"4e", X"86", X"4f", X"ad", X"c5", X"02", X"45", X"4f", X"25", X"4e", X"8d", X"17", X"d0", X"a2", X"00", X"20", X"55", X"c2", X"d0", X"03", X"20", X"4f", X"c2", X"a5", X"42", X"d0", X"08", X"ba", X"bd", X"04", X"01", X"29", X"04", X"f0", X"03", X"4c", X"8a", X"c2", X"ad", X"13", X"d0", X"cd", X"fa", X"03", X"d0", X"b4", X"ad", X"0d", X"d4", X"8d", X"35", X"02", X"ad", X"0c", X"d4", X"8d", X"34", X"02", X"ad", X"31", X"02", X"8d", X"03", X"d4", X"ad", X"30", X"02", X"8d", X"02", X"d4", X"ad", X"2f", X"02", X"8d", X"00", X"d4", X"ad", X"6f", X"02", X"8d", X"1b", X"d0", X"ad", X"6c", X"02", X"f0", X"0e", X"ce", X"6c", X"02", X"a9", X"08", X"38", X"ed", X"6c", X"02", X"29", X"07", X"8d", X"05", X"d4", X"a2", X"08", X"8e", X"1f", X"d0", X"58", X"bd", X"c0", X"02", X"45", X"4f", X"25", X"4e", X"9d", X"12", X"d0", X"ca", X"10", X"f2", X"ad", X"f4", X"02", X"8d", X"09", X"d4", X"ad", X"f3", X"02", X"8d", X"01", X"d4", X"a2", X"02", X"20", X"55", X"c2", X"d0", X"03", X"20", X"52", X"c2", X"a2", X"02", X"e8", X"e8", X"bd", X"18", X"02", X"1d", X"19", X"02", X"f0", X"06", X"20", X"55", X"c2", X"9d", X"26", X"02", X"e0", X"08", X"d0", X"ec", X"ad", X"0f", X"d2", X"29", X"04", X"f0", X"08", X"ad", X"f1", X"02", X"f0", X"03", X"ce", X"f1", X"02", X"ad", X"2b", X"02", X"f0", X"3e", X"ad", X"0f", X"d2", X"29", X"04", X"d0", X"32", X"ce", X"2b", X"02", X"d0", X"32", X"ad", X"6d", X"02", X"d0", X"2d", X"ad", X"da", X"02", X"8d", X"2b", X"02", X"ad", X"09", X"d2", X"c9", X"9f", X"f0", X"20", X"c9", X"83", X"f0", X"1c", X"c9", X"84", X"f0", X"18", X"c9", X"94", X"f0", X"14", X"29", X"3f", X"c9", X"11", X"f0", X"0e", X"ad", X"09", X"d2", X"8d", X"fc", X"02", X"4c", X"f3", X"c1", X"a9", X"00", X"8d", X"2b", X"02", X"ad", X"00", X"d3", X"4a", X"4a", X"4a", X"4a", X"8d", X"79", X"02", X"8d", X"7b", X"02", X"ad", X"00", X"d3", X"29", X"0f", X"8d", X"78", X"02", X"8d", X"7a", X"02", X"ad", X"10", X"d0", X"8d", X"84", X"02", X"8d", X"86", X"02", X"ad", X"11", X"d0", X"8d", X"85", X"02", X"8d", X"87", X"02", X"a2", X"03", X"bd", X"00", X"d2", X"9d", X"70", X"02", X"9d", X"74", X"02", X"ca", X"10", X"f4", X"8d", X"0b", X"d2", X"a2", X"02", X"a0", X"01", X"b9", X"78", X"02", X"4a", X"4a", X"4a", X"9d", X"7d", X"02", X"9d", X"81", X"02", X"a9", X"00", X"2a", X"9d", X"7c", X"02", X"9d", X"80", X"02", X"ca", X"ca", X"88", X"10", X"e6", X"6c", X"24", X"02", X"6c", X"26", X"02", X"6c", X"28", X"02", X"bc", X"18", X"02", X"d0", X"08", X"bc", X"19", X"02", X"f0", X"10", X"de", X"19", X"02", X"de", X"18", X"02", X"d0", X"08", X"bc", X"19", X"02", X"d0", X"03", X"a9", X"00", X"60", X"a9", X"ff", X"60", X"0a", X"8d", X"2d", X"02", X"8a", X"a2", X"05", X"8d", X"0a", X"d4", X"ca", X"d0", X"fd", X"ae", X"2d", X"02", X"9d", X"17", X"02", X"98", X"9d", X"16", X"02", X"60", X"68", X"a8", X"68", X"aa", X"68", X"40", X"78", X"ad", X"13", X"d0", X"cd", X"fa", X"03", X"d0", X"2f", X"6a", X"90", X"05", X"20", X"c9", X"c4", X"d0", X"27", X"ad", X"44", X"02", X"d0", X"22", X"a9", X"ff", X"d0", X"20", X"78", X"a2", X"8c", X"88", X"d0", X"fd", X"ca", X"d0", X"fa", X"ad", X"3d", X"03", X"c9", X"5c", X"d0", X"0e", X"ad", X"3e", X"03", X"c9", X"93", X"d0", X"07", X"ad", X"3f", X"03", X"c9", X"25", X"f0", X"c8", X"a9", X"00", X"85", X"08", X"78", X"d8", X"a2", X"ff", X"9a", X"20", X"71", X"c4", X"a9", X"01", X"85", X"01", X"a5", X"08", X"d0", X"52", X"a9", X"00", X"a0", X"08", X"85", X"04", X"85", X"05", X"a9", X"ff", X"91", X"04", X"d1", X"04", X"f0", X"02", X"46", X"01", X"a9", X"00", X"91", X"04", X"d1", X"04", X"f0", X"02", X"46", X"01", X"c8", X"d0", X"e9", X"e6", X"05", X"a6", X"05", X"e4", X"06", X"d0", X"e1", X"a9", X"23", X"85", X"0a", X"a9", X"f2", X"85", X"0b", X"ad", X"01", X"d3", X"29", X"7f", X"8d", X"01", X"d3", X"20", X"73", X"ff", X"b0", X"05", X"20", X"92", X"ff", X"90", X"02", X"46", X"01", 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X"03", X"a9", X"60", X"8d", X"00", X"03", X"a9", X"00", X"8d", X"01", X"03", X"a9", X"23", X"8d", X"06", X"03", X"ad", X"02", X"03", X"a0", X"40", X"c9", X"52", X"f0", X"02", X"a0", X"80", X"8c", X"03", X"03", X"a5", X"3e", X"8d", X"0b", X"03", X"20", X"59", X"e4", X"60", X"8d", X"ff", X"03", X"a9", X"55", X"8d", X"fd", X"03", X"8d", X"fe", X"03", X"a9", X"57", X"20", X"3f", X"fe", X"60", X"04", X"03", X"80", X"c0", X"02", X"01", X"40", X"e0", X"1e", X"19", X"0a", X"08", X"a9", X"1e", X"8d", X"14", X"03", X"60", X"ea", X"02", X"c0", X"03", X"a9", X"04", X"8d", X"df", X"02", X"ae", X"9f", X"fe", X"ac", X"a0", X"fe", X"a9", X"53", X"8d", X"02", X"03", X"8d", X"0a", X"03", X"20", X"14", X"ff", X"20", X"59", X"e4", X"30", X"03", X"20", X"44", X"ff", X"60", X"20", X"a3", X"fe", X"a9", X"00", X"8d", X"de", X"02", X"60", X"48", X"bd", X"41", X"03", X"85", X"21", X"20", X"4b", X"ff", X"ae", X"de", X"02", X"68", X"9d", X"c0", X"03", X"e8", X"ec", X"df", X"02", X"f0", X"15", X"8e", X"de", X"02", X"c9", X"9b", X"f0", X"03", X"a0", X"01", X"60", X"a9", X"20", X"9d", X"c0", X"03", X"e8", X"ec", X"df", X"02", X"d0", X"f7", X"a9", X"00", X"8d", X"de", X"02", X"ae", X"a1", X"fe", X"ac", X"a2", X"fe", X"20", X"14", X"ff", X"4c", X"59", X"e4", X"20", X"4b", X"ff", X"a9", X"9b", X"ae", X"de", X"02", X"d0", X"dc", X"a0", X"01", X"60", X"8e", X"04", X"03", X"8c", X"05", X"03", X"a9", X"40", X"8d", X"00", X"03", X"a5", X"21", X"8d", X"01", X"03", X"a9", X"80", X"ae", X"02", X"03", X"e0", X"53", X"d0", X"02", X"a9", X"40", X"8d", X"03", X"03", X"ad", X"df", X"02", X"8d", X"08", X"03", X"a9", X"00", X"8d", X"09", X"03", X"ad", X"14", X"03", X"8d", X"06", X"03", X"60", X"ad", X"ec", X"02", X"8d", X"14", X"03", X"60", X"a0", X"57", X"a5", X"2b", X"c9", X"4e", X"d0", X"04", X"a2", X"28", X"d0", X"0e", X"c9", X"44", X"d0", X"04", X"a2", X"14", X"d0", X"06", X"c9", X"53", X"d0", X"0c", X"a2", X"1d", X"8e", X"df", X"02", X"8c", X"02", X"03", X"8d", X"0a", X"03", X"60", X"a9", X"4e", X"d0", X"dc", X"a2", X"00", X"86", X"8b", X"86", X"8c", X"20", X"a9", X"ff", X"e0", X"0c", X"d0", X"f9", X"ad", X"00", X"c0", X"ae", X"01", X"c0", X"c5", X"8b", X"d0", X"06", X"e4", X"8c", X"d0", X"02", X"18", X"60", X"38", X"60", X"a2", X"00", X"86", X"8b", X"86", X"8c", X"a2", X"0c", X"20", X"a9", X"ff", X"20", X"a9", X"ff", X"ad", X"f8", X"ff", X"ae", X"f9", X"ff", X"4c", X"86", X"ff", X"a0", X"00", X"bd", X"d7", X"ff", X"99", X"9e", X"00", X"e8", X"c8", X"c0", X"04", X"d0", X"f4", X"a0", X"00", X"18", X"b1", X"9e", X"65", X"8b", X"85", X"8b", X"90", X"02", X"e6", X"8c", X"e6", X"9e", X"d0", X"02", X"e6", X"9f", X"a5", X"9e", X"c5", X"a0", X"d0", X"e9", X"a5", X"9f", X"c5", X"a1", X"d0", X"e3", X"60", X"02", X"c0", X"00", X"d0", X"00", X"50", X"00", X"58", X"00", X"d8", X"00", X"e0", X"00", X"e0", X"f8", X"ff", X"fa", X"ff", X"00", X"00", X"00", X"00", X"00", X"10", X"05", X"83", X"02", X"42", X"42", X"00", X"00", X"01", X"02", X"8c", X"6c", X"18", X"c0", X"aa", X"c2", X"2c", X"c0" ); signal rdata:std_logic_vector(7 downto 0); begin rdata<=ROM(conv_integer(address)); process(clock) begin if(clock'event and clock='1')then q<=rdata; end if; end process; end syn;
entity something is end entity; architecture arch of something is begin end architecture; configuration testbench of something is for arch end for; end; entity c01s03b01x00p12n01i00863ent is end entity; architecture c01s03b01x00p12n01i00863arch of c01s03b01x00p12n01i00863ent is begin K:block component test port( sigin1 : in boolean := false; sigout1 : out boolean ; sigin2 : in bit := '0'; sigout2 : out bit ; sigin4 : in severity_level := note ; sigout4 : out severity_level ; sigin5 : in integer := 0 ; sigout5 : out integer ; sigin6 : in real := 0.0; sigout6 : out real ; sigin7 : in time := 0 fs; sigout7 : out time ; sigin8 : in natural := 0 ; sigout8 : out natural ; sigin9 : in positive := 0 ; sigout9 : out positive ); end component; BEGIN T5: component test; G: for i in 0 to 3 generate T1: component test; end generate; end block; end architecture; configuration c01s03b01x00p12n01i00863cfg of c01s03b01x00p12n01i00863ent is for c01s03b01x00p12n01i00863arch for K for T5:test use configuration work.testbench; end for; for G(3) for T1:test use configuration work.testbench; end for; end for; for G(0 to 2) for all:test use configuration work.testbench; end for; end for; end for; end for; end;
--***************************************************************************** -- (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 1.5 -- \ \ Application : MIG -- / / Filename : ddr_phy_top.vhd -- /___/ /\ Date Last Modified : $date$ -- \ \ / \ Date Created : Jan 31 2012 -- \___\/\___\ -- --Device : 7 Series --Design Name : DDR3 SDRAM --Purpose : Top level memory interface block. Instantiates a clock -- and reset generator, the memory controller, the phy and -- the user interface blocks. --Reference : --Revision History : --***************************************************************************** library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity mig_7series_v1_8_ddr_phy_top is generic ( TCQ : integer := 100; -- Register delay (simulation only) AL : string := "0"; -- Additive Latency option BANK_WIDTH : integer := 3; -- # of bank bits BURST_MODE : string := "8"; -- Burst length BURST_TYPE : string := "SEQ"; -- Burst type CA_MIRROR : string := "OFF"; -- C/A mirror opt for DDR3 dual rank CK_WIDTH : integer := 1; -- # of CK/CK# outputs to memory CL : integer := 5; COL_WIDTH : integer := 12; -- column address width CS_WIDTH : integer := 1; -- # of unique CS outputs CKE_WIDTH : integer := 1; -- # of cke outputs CWL : integer := 5; DM_WIDTH : integer := 8; -- # of DM (data mask) DQ_WIDTH : integer := 64; -- # of DQ (data) DQS_CNT_WIDTH : integer := 3; -- = ceil(log2(DQS_WIDTH)) DQS_WIDTH : integer := 8; -- # of DQS (strobe) DRAM_TYPE : string := "DDR3"; DRAM_WIDTH : integer := 8; -- # of DQ per DQS MASTER_PHY_CTL : integer := 0; -- The bank number where master PHY_CONTROL resides LP_DDR_CK_WIDTH : integer := 2; DATA_IO_IDLE_PWRDWN : string := "ON"; -- "ON" or "OFF" -- Hard PHY parameters PHYCTL_CMD_FIFO : string := "FALSE"; -- five fields, one per possible I/O bank, 4 bits in each field, -- 1 per lane data=1/ctl=0 DATA_CTL_B0 : std_logic_vector(3 downto 0) := X"c"; DATA_CTL_B1 : std_logic_vector(3 downto 0) := X"f"; DATA_CTL_B2 : std_logic_vector(3 downto 0) := X"f"; DATA_CTL_B3 : std_logic_vector(3 downto 0) := X"f"; DATA_CTL_B4 : std_logic_vector(3 downto 0) := X"f"; -- defines the byte lanes in I/O banks being used in the interface -- 1- Used, 0- Unused BYTE_LANES_B0 : std_logic_vector(3 downto 0) := "1111"; BYTE_LANES_B1 : std_logic_vector(3 downto 0) := "0000"; BYTE_LANES_B2 : std_logic_vector(3 downto 0) := "0000"; BYTE_LANES_B3 : std_logic_vector(3 downto 0) := "0000"; BYTE_LANES_B4 : std_logic_vector(3 downto 0) := "0000"; -- defines the bit lanes in I/O banks being used in the interface. Each -- = 1 I/O bank = 4 byte lanes = 48 bit lanes. 1-Used, 0-Unused PHY_0_BITLANES : std_logic_vector(47 downto 0) := X"000000000000"; PHY_1_BITLANES : std_logic_vector(47 downto 0) := X"000000000000"; PHY_2_BITLANES : std_logic_vector(47 downto 0) := X"000000000000"; -- control/address/data pin mapping parameters CK_BYTE_MAP : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000"; ADDR_MAP : std_logic_vector(191 downto 0) := X"000000000000000000000000000000000000000000000000"; BANK_MAP : std_logic_vector(35 downto 0) := X"000000000"; CAS_MAP : std_logic_vector(11 downto 0) := X"000"; CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0) := X"00"; CKE_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000"; ODT_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000"; CKE_ODT_AUX : string := "FALSE"; CS_MAP : std_logic_vector(119 downto 0) := X"000000000000000000000000000000"; PARITY_MAP : std_logic_vector(11 downto 0) := X"000"; RAS_MAP : std_logic_vector(11 downto 0) := X"000"; WE_MAP : std_logic_vector(11 downto 0) := X"000"; DQS_BYTE_MAP : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000"; DATA0_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000"; DATA1_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000"; DATA2_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000"; DATA3_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000"; DATA4_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000"; DATA5_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000"; DATA6_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000"; DATA7_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000"; DATA8_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000"; DATA9_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000"; DATA10_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000"; DATA11_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000"; DATA12_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000"; DATA13_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000"; DATA14_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000"; DATA15_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000"; DATA16_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000"; DATA17_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000"; MASK0_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000000000"; MASK1_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000000000"; -- This parameter must be set based on memory clock frequency -- It must be set to 4 for frequencies above 533 MHz?? (undecided) -- and set to 2 for 533 MHz and below PRE_REV3ES : string := "OFF"; -- Delay O/Ps using Phaser_Out fine dly nCK_PER_CLK : integer := 2; -- # of memory CKs per fabric CLK nCS_PER_RANK : integer := 1; -- # of unique CS outputs per rank ADDR_CMD_MODE : string := "1T"; -- ADDR/CTRL timing: "2T", "1T" IODELAY_HP_MODE : string := "ON"; BANK_TYPE : string := "HP_IO"; -- # = "HP_LP", "HR_LP", "DEFAULT" DATA_IO_PRIM_TYPE : string := "DEFAULT"; -- # = "HP_LP", "HR_LP", "DEFAULT" IODELAY_GRP : string := "IODELAY_MIG"; IBUF_LPWR_MODE : string := "OFF"; -- input buffer low power option OUTPUT_DRV : string := "HIGH"; -- to calib_top REG_CTRL : string := "OFF"; -- to calib_top RTT_NOM : string := "60"; -- to calib_top RTT_WR : string := "120"; -- to calib_top tCK : integer := 2500; -- pS tRFC : integer := 110000; -- pS DDR2_DQSN_ENABLE : string := "YES"; -- Enable differential DQS for DDR2 WRLVL : string := "OFF"; -- to calib_top DEBUG_PORT : string := "OFF"; -- to calib_top RANKS : integer := 4; ODT_WIDTH : integer := 1; ROW_WIDTH : integer := 16; -- DRAM address bus width SLOT_1_CONFIG : std_logic_vector(7 downto 0) := "00000000"; -- calibration Address. The address given below will be used for calibration -- read and write operations. CALIB_ROW_ADD : std_logic_vector(15 downto 0) := X"0000"; -- Calibration row address CALIB_COL_ADD : std_logic_vector(11 downto 0) := X"000"; -- Calibration column address CALIB_BA_ADD : std_logic_vector(2 downto 0) := "000"; -- Calibration bank address -- Simulation /debug options SIM_BYPASS_INIT_CAL : string := "OFF"; -- Parameter used to force skipping -- or abbreviation of initialization -- and calibration. Overrides -- SIM_INIT_OPTION, SIM_CAL_OPTION, -- and disables various other blocks --parameter SIM_INIT_OPTION = "SKIP_PU_DLY", -- Skip various init steps --parameter SIM_CAL_OPTION = "NONE", -- Skip various calib steps REFCLK_FREQ : real := 200.0; -- IODELAY ref clock freq (MHz) USE_CS_PORT : integer := 1; -- Support chip select output USE_DM_PORT : integer := 1; -- Support data mask output USE_ODT_PORT : integer := 1; -- Support ODT output RD_PATH_REG : integer := 0 -- optional registers in the read path -- to MC for timing improvement. -- =1 enabled, = 0 disabled ); port ( clk : in std_logic; -- Fabric logic clock -- To MC, calib_top, hard PHY clk_ref : in std_logic; -- Idelay_ctrl reference clock -- To hard PHY (external source) freq_refclk : in std_logic; -- To hard PHY for Phasers mem_refclk : in std_logic; -- Memory clock to hard PHY pll_lock : in std_logic; -- System PLL lock signal sync_pulse : in std_logic; -- 1/N sync pulse used to -- synchronize all PHASERS error : in std_logic; -- Support for TG error detect rst_tg_mc : out std_logic; -- Support for TG error detect device_temp : in std_logic_vector(11 downto 0); tempmon_sample_en : in std_logic; dbg_sel_pi_incdec : in std_logic; dbg_sel_po_incdec : in std_logic; dbg_byte_sel : in std_logic_vector(DQS_CNT_WIDTH downto 0); dbg_pi_f_inc : in std_logic; dbg_pi_f_dec : in std_logic; dbg_po_f_inc : in std_logic; dbg_po_f_stg23_sel : in std_logic; dbg_po_f_dec : in std_logic; dbg_idel_down_all : in std_logic; dbg_idel_down_cpt : in std_logic; dbg_idel_up_all : in std_logic; dbg_idel_up_cpt : in std_logic; dbg_sel_all_idel_cpt : in std_logic; dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH-1 downto 0); rst : in std_logic; slot_0_present : in std_logic_vector(7 downto 0); slot_1_present : in std_logic_vector(7 downto 0); -- From MC mc_ras_n : in std_logic_vector(nCK_PER_CLK-1 downto 0); mc_cas_n : in std_logic_vector(nCK_PER_CLK-1 downto 0); mc_we_n : in std_logic_vector(nCK_PER_CLK-1 downto 0); mc_address : in std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0); mc_bank : in std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0); mc_cs_n : in std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0); mc_reset_n : in std_logic; mc_odt : in std_logic_vector(1 downto 0); mc_cke : in std_logic_vector(nCK_PER_CLK-1 downto 0); -- AUX - For ODT and CKE assertion during reads and writes mc_aux_out0 : in std_logic_vector(3 downto 0); mc_aux_out1 : in std_logic_vector(3 downto 0); mc_cmd_wren : in std_logic; mc_ctl_wren : in std_logic; mc_cmd : in std_logic_vector(2 downto 0); mc_cas_slot : in std_logic_vector(1 downto 0); mc_data_offset : in std_logic_vector(5 downto 0); mc_data_offset_1 : in std_logic_vector(5 downto 0); mc_data_offset_2 : in std_logic_vector(5 downto 0); mc_rank_cnt : in std_logic_vector(1 downto 0); -- Write mc_wrdata_en : in std_logic; mc_wrdata : in std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0); mc_wrdata_mask : in std_logic_vector((2*nCK_PER_CLK*(DQ_WIDTH/8))-1 downto 0); idle : in std_logic; -- DDR bus signals ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0); ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0); ddr_cas_n : out std_logic; ddr_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0); ddr_ck : out std_logic_vector(CK_WIDTH-1 downto 0); ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0); ddr_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0); ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0); ddr_odt : out std_logic_vector(ODT_WIDTH-1 downto 0); ddr_ras_n : out std_logic; ddr_reset_n : out std_logic; ddr_parity : out std_logic; ddr_we_n : out std_logic; ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0); ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0); ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0); dbg_calib_top : out std_logic_vector(255 downto 0); dbg_cpt_first_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0); dbg_cpt_second_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0); dbg_cpt_tap_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0); dbg_dq_idelay_tap_cnt : out std_logic_vector(5*DQS_WIDTH*RANKS-1 downto 0); dbg_phy_rdlvl : out std_logic_vector(255 downto 0); dbg_phy_wrcal : out std_logic_vector(99 downto 0); dbg_final_po_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0); dbg_final_po_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0); dbg_rd_data_edge_detect : out std_logic_vector(DQS_WIDTH-1 downto 0); dbg_rddata : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0); dbg_rddata_valid : out std_logic; dbg_rdlvl_done : out std_logic_vector(1 downto 0); dbg_rdlvl_err : out std_logic_vector(1 downto 0); dbg_rdlvl_start : out std_logic_vector(1 downto 0); dbg_tap_cnt_during_wrlvl : out std_logic_vector(5 downto 0); dbg_wl_edge_detect_valid : out std_logic; dbg_wrlvl_done : out std_logic; dbg_wrlvl_err : out std_logic; dbg_wrlvl_start : out std_logic; dbg_wrlvl_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0); dbg_wrlvl_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0); dbg_phy_wrlvl : out std_logic_vector(255 downto 0); dbg_pi_phaselock_start : out std_logic; dbg_pi_phaselocked_done : out std_logic; dbg_pi_phaselock_err : out std_logic; dbg_pi_phase_locked_phy4lanes : out std_logic_vector(11 downto 0); dbg_pi_dqsfound_start : out std_logic; dbg_pi_dqsfound_done : out std_logic; dbg_pi_dqsfound_err : out std_logic; dbg_pi_dqs_found_lanes_phy4lanes : out std_logic_vector(11 downto 0); dbg_wrcal_start : out std_logic; dbg_wrcal_done : out std_logic; dbg_wrcal_err : out std_logic; -- FIFO status flags phy_mc_ctl_full : out std_logic; phy_mc_cmd_full : out std_logic; phy_mc_data_full : out std_logic; -- Calibration status and resultant outputs init_calib_complete : out std_logic; init_wrcal_complete : out std_logic; calib_rd_data_offset_0 : out std_logic_vector(6*RANKS-1 downto 0); calib_rd_data_offset_1 : out std_logic_vector(6*RANKS-1 downto 0); calib_rd_data_offset_2 : out std_logic_vector(6*RANKS-1 downto 0); phy_rddata_valid : out std_logic; phy_rd_data : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0); ref_dll_lock : out std_logic; rst_phaser_ref : in std_logic; dbg_rd_data_offset : out std_logic_vector(6*RANKS-1 downto 0); dbg_phy_init : out std_logic_vector(255 downto 0); dbg_prbs_rdlvl : out std_logic_vector(255 downto 0); dbg_dqs_found_cal : out std_logic_vector(255 downto 0); dbg_pi_counter_read_val : out std_logic_vector(5 downto 0); dbg_po_counter_read_val : out std_logic_vector(8 downto 0); dbg_oclkdelay_calib_start : out std_logic; dbg_oclkdelay_calib_done : out std_logic; dbg_phy_oclkdelay_cal : out std_logic_vector(255 downto 0); dbg_oclkdelay_rd_data : out std_logic_vector(DRAM_WIDTH*16-1 downto 0) ); end entity; architecture arch_ddr_phy_top of mig_7series_v1_8_ddr_phy_top is -- function to OR the bits in a vectored signal function OR_BR (inp_var: std_logic_vector) return std_logic is variable temp: std_logic := '0'; begin for idx in inp_var'range loop temp := temp or inp_var(idx); end loop; return temp; end function; -- Calculate number of slots in the system function CALC_nSLOTS return integer is begin if (OR_BR(SLOT_1_CONFIG) = '1') then return (2); else return (1); end if; end function; function SIM_INIT_OPTION_W return string is begin if (SIM_BYPASS_INIT_CAL = "SKIP") then return ("SKIP_INIT"); elsif (SIM_BYPASS_INIT_CAL = "FAST" or SIM_BYPASS_INIT_CAL = "SIM_FULL") then return ("SKIP_PU_DLY"); else return ("NONE"); end if; end function; function SIM_CAL_OPTION_W return string is begin if (SIM_BYPASS_INIT_CAL = "SKIP") then return ("SKIP_CAL"); elsif (SIM_BYPASS_INIT_CAL = "FAST") then return ("FAST_CAL"); elsif (SIM_BYPASS_INIT_CAL = "SIM_FULL" or SIM_BYPASS_INIT_CAL = "SIM_INIT_CAL_FULL") then return ("FAST_WIN_DETECT"); else return ("NONE"); end if; end function; function CALC_WRLVL_W return string is begin if (SIM_BYPASS_INIT_CAL = "SKIP") then return ("OFF"); else return (WRLVL); end if; end function; function HIGHEST_BANK_W return integer is begin if (BYTE_LANES_B4 /= "0000") then return (5); elsif (BYTE_LANES_B3 /= "0000") then return (4); elsif (BYTE_LANES_B2 /= "0000") then return (3); elsif (BYTE_LANES_B1 /= "0000") then return (2); else return (1); end if; end function; function HIGHEST_LANE_B0_W return integer is begin if (BYTE_LANES_B0(3) = '1') then return (4); elsif (BYTE_LANES_B0(2) = '1') then return (3); elsif (BYTE_LANES_B0(1) = '1') then return (2); elsif (BYTE_LANES_B0(0) = '1') then return (1); else return (0); end if; end function; function HIGHEST_LANE_B1_W return integer is begin if (BYTE_LANES_B1(3) = '1') then return (4); elsif (BYTE_LANES_B1(2) = '1') then return (3); elsif (BYTE_LANES_B1(1) = '1') then return (2); elsif (BYTE_LANES_B1(0) = '1') then return (1); else return (0); end if; end function; function HIGHEST_LANE_B2_W return integer is begin if (BYTE_LANES_B2(3) = '1') then return (4); elsif (BYTE_LANES_B2(2) = '1') then return (3); elsif (BYTE_LANES_B2(1) = '1') then return (2); elsif (BYTE_LANES_B2(0) = '1') then return (1); else return (0); end if; end function; function HIGHEST_LANE_B3_W return integer is begin if (BYTE_LANES_B3(3) = '1') then return (4); elsif (BYTE_LANES_B3(2) = '1') then return (3); elsif (BYTE_LANES_B3(1) = '1') then return (2); elsif (BYTE_LANES_B3(0) = '1') then return (1); else return (0); end if; end function; function HIGHEST_LANE_B4_W return integer is begin if (BYTE_LANES_B4(3) = '1') then return (4); elsif (BYTE_LANES_B4(2) = '1') then return (3); elsif (BYTE_LANES_B4(1) = '1') then return (2); elsif (BYTE_LANES_B4(0) = '1') then return (1); else return (0); end if; end function; function HIGHEST_LANE_W return integer is begin if (HIGHEST_LANE_B4_W /= 0) then return (HIGHEST_LANE_B4_W+16); elsif (HIGHEST_LANE_B3_W /= 0) then return (HIGHEST_LANE_B3_W+12); elsif (HIGHEST_LANE_B2_W /= 0) then return (HIGHEST_LANE_B2_W+8); elsif (HIGHEST_LANE_B1_W /= 0) then return (HIGHEST_LANE_B1_W+4); else return (HIGHEST_LANE_B0_W); end if; end function; function N_CTL_LANES_B0 return integer is variable temp: integer := 0; begin for idx in 0 to 3 loop if (not(DATA_CTL_B0(idx)) = '1' and BYTE_LANES_B0(idx) = '1') then temp := temp + 1; else temp := temp; end if; end loop; return temp; end function; function N_CTL_LANES_B1 return integer is variable temp: integer := 0; begin for idx in 0 to 3 loop if (not(DATA_CTL_B1(idx)) = '1' and BYTE_LANES_B1(idx) = '1') then temp := temp + 1; else temp := temp; end if; end loop; return temp; end function; function N_CTL_LANES_B2 return integer is variable temp: integer := 0; begin for idx in 0 to 3 loop if (not(DATA_CTL_B2(idx)) = '1' and BYTE_LANES_B2(idx) = '1') then temp := temp + 1; else temp := temp; end if; end loop; return temp; end function; function N_CTL_LANES_B3 return integer is variable temp: integer := 0; begin for idx in 0 to 3 loop if (not(DATA_CTL_B3(idx)) = '1' and BYTE_LANES_B3(idx) = '1') then temp := temp + 1; else temp := temp; end if; end loop; return temp; end function; function N_CTL_LANES_B4 return integer is variable temp: integer := 0; begin for idx in 0 to 3 loop if (not(DATA_CTL_B4(idx)) = '1' and BYTE_LANES_B4(idx) = '1') then temp := temp + 1; else temp := temp; end if; end loop; return temp; end function; function CTL_BANK_B0 return std_logic is begin if ((not(DATA_CTL_B0(0)) = '1' and BYTE_LANES_B0(0) = '1') or (not(DATA_CTL_B0(1)) = '1' and BYTE_LANES_B0(1) = '1') or (not(DATA_CTL_B0(2)) = '1' and BYTE_LANES_B0(2) = '1') or (not(DATA_CTL_B0(3)) = '1' and BYTE_LANES_B0(3) = '1')) then return ('1') ; else return ('0') ; end if; end function; function CTL_BANK_B1 return std_logic is begin if ((not(DATA_CTL_B1(0)) = '1' and BYTE_LANES_B1(0) = '1') or (not(DATA_CTL_B1(1)) = '1' and BYTE_LANES_B1(1) = '1') or (not(DATA_CTL_B1(2)) = '1' and BYTE_LANES_B1(2) = '1') or (not(DATA_CTL_B1(3)) = '1' and BYTE_LANES_B1(3) = '1')) then return ('1') ; else return ('0') ; end if; end function; function CTL_BANK_B2 return std_logic is begin if ((not(DATA_CTL_B2(0)) = '1' and BYTE_LANES_B2(0) = '1') or (not(DATA_CTL_B2(1)) = '1' and BYTE_LANES_B2(1) = '1') or (not(DATA_CTL_B2(2)) = '1' and BYTE_LANES_B2(2) = '1') or (not(DATA_CTL_B2(3)) = '1' and BYTE_LANES_B2(3) = '1')) then return ('1') ; else return ('0') ; end if; end function; function CTL_BANK_B3 return std_logic is begin if ((not(DATA_CTL_B3(0)) = '1' and BYTE_LANES_B3(0) = '1') or (not(DATA_CTL_B3(1)) = '1' and BYTE_LANES_B3(1) = '1') or (not(DATA_CTL_B3(2)) = '1' and BYTE_LANES_B3(2) = '1') or (not(DATA_CTL_B3(3)) = '1' and BYTE_LANES_B3(3) = '1')) then return ('1') ; else return ('0') ; end if; end function; function CTL_BANK_B4 return std_logic is begin if ((not(DATA_CTL_B4(0)) = '1' and BYTE_LANES_B4(0) = '1') or (not(DATA_CTL_B4(1)) = '1' and BYTE_LANES_B4(1) = '1') or (not(DATA_CTL_B4(2)) = '1' and BYTE_LANES_B4(2) = '1') or (not(DATA_CTL_B4(3)) = '1' and BYTE_LANES_B4(3) = '1')) then return ('1') ; else return ('0') ; end if; end function; function CTL_BANK_W return std_logic_vector is variable ctl_bank_var : std_logic_vector(2 downto 0); begin if (CTL_BANK_B0 = '1') then ctl_bank_var := "000"; elsif (CTL_BANK_B1 = '1') then ctl_bank_var := "001"; elsif (CTL_BANK_B2 = '1') then ctl_bank_var := "010"; elsif (CTL_BANK_B3 = '1') then ctl_bank_var := "011"; elsif (CTL_BANK_B4 = '1') then ctl_bank_var := "100"; else ctl_bank_var := "000"; end if; return (ctl_bank_var); end function; function ODD_PARITY (inp_var : std_logic_vector) return std_logic is variable tmp : std_logic := '0'; begin for idx in inp_var'range loop tmp := tmp XOR inp_var(idx); end loop; return tmp; end ODD_PARITY; -- Calculate number of slots in the system constant nSLOTS : integer := CALC_nSLOTS; constant CLK_PERIOD : integer := tCK * nCK_PER_CLK; -- Parameter used to force skipping or abbreviation of initialization -- and calibration. Overrides SIM_INIT_OPTION, SIM_CAL_OPTION, and -- disables various other blocks depending on the option selected -- This option should only be used during simulation. In the case of -- the "SKIP" option, the testbench used should also not be modeling -- propagation delays. -- Allowable options = {"NONE", "SIM_FULL", "SKIP", "FAST"} -- "NONE" = options determined by the individual parameter settings -- "SIM_FULL" = skip power-up delay. FULL calibration performed without -- averaging algorithm turned ON during window detection. -- "SKIP" = skip power-up delay. Skip calibration not yet supported. -- "FAST" = skip power-up delay, and calibrate (read leveling, write -- leveling, and phase detector) only using one DQS group, and -- apply the results to all other DQS groups. constant SIM_INIT_OPTION : string := SIM_INIT_OPTION_W; constant SIM_CAL_OPTION : string := SIM_CAL_OPTION_W; constant WRLVL_W : string := CALC_WRLVL_W; constant HIGHEST_BANK : integer := HIGHEST_BANK_W; -- constant HIGHEST_LANE_B0 = HIGHEST_LANE_B0_W; -- constant HIGHEST_LANE_B1 = HIGHEST_LANE_B1_W; -- constant HIGHEST_LANE_B2 = HIGHEST_LANE_B2_W; -- constant HIGHEST_LANE_B3 = HIGHEST_LANE_B3_W; -- constant HIGHEST_LANE_B4 = HIGHEST_LANE_B4_W; constant HIGHEST_LANE : integer := HIGHEST_LANE_W; constant N_CTL_LANES : integer := N_CTL_LANES_B0 + N_CTL_LANES_B1 + N_CTL_LANES_B2 + N_CTL_LANES_B3 + N_CTL_LANES_B4; -- Assuming Ck/Addr/Cmd and Control are placed in a single IO Bank -- This should be the case since the PLL should be placed adjacent -- to the same IO Bank as Ck/Addr/Cmd and Control constant CTL_BANK : std_logic_vector(2 downto 0):= CTL_BANK_W; function CTL_BYTE_LANE_W return std_logic_vector is variable ctl_byte_lane_var: std_logic_vector(7 downto 0); begin if (N_CTL_LANES = 4) then ctl_byte_lane_var := "11100100"; elsif (N_CTL_LANES = 3 and (((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and (not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and (not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1') or ((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and (not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and (not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1') or ((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and (not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and (not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1') or ((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and (not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and (not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1') or ((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and (not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and (not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1'))) then ctl_byte_lane_var := "00100100"; elsif (N_CTL_LANES = 3 and (((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and (not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and (not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or ((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and (not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and (not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or ((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and (not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and (not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or ((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and (not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and (not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or ((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and (not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and (not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then ctl_byte_lane_var := "00110100"; elsif (N_CTL_LANES = 3 and (((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and (not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1' and (not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or ((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and (not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1' and (not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or ((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and (not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1' and (not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or ((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and (not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1' and (not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or ((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and (not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1' and (not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then ctl_byte_lane_var := "00111000"; elsif (N_CTL_LANES = 3 and (((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and (not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1' and (not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or ((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and (not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1' and (not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or ((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and (not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1' and (not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or ((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and (not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1' and (not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or ((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and (not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1' and (not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then ctl_byte_lane_var := "00111001"; elsif (N_CTL_LANES = 2 and (((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and (not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1') or ((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and (not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1') or ((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and (not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1') or ((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and (not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1') or ((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and (not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1'))) then ctl_byte_lane_var := "00000100"; elsif (N_CTL_LANES = 2 and (((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and (not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or ((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and (not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or ((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and (not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or ((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and (not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or ((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and (not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then ctl_byte_lane_var := "00001100"; elsif (N_CTL_LANES = 2 and (((not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1' and (not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or ((not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1' and (not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or ((not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1' and (not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or ((not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1' and (not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or ((not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1' and (not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then ctl_byte_lane_var := "00001110"; elsif (N_CTL_LANES = 2 and (((not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and (not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1') or ((not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and (not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1') or ((not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and (not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1') or ((not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and (not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1') or ((not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and (not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1'))) then ctl_byte_lane_var := "00001001"; elsif (N_CTL_LANES = 2 and (((not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and (not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or ((not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and (not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or ((not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and (not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or ((not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and (not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or ((not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and (not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then ctl_byte_lane_var := "00001101"; elsif (N_CTL_LANES = 2 and (((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and (not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1') or ((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and (not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1') or ((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and (not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1') or ((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and (not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1') or ((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and (not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1'))) then ctl_byte_lane_var := "00001000"; else ctl_byte_lane_var := "11100100"; end if; return (ctl_byte_lane_var); end function; constant CTL_BYTE_LANE : std_logic_vector(7 downto 0):= CTL_BYTE_LANE_W; component mig_7series_v1_8_ddr_mc_phy_wrapper is generic ( TCQ : integer; tCK : integer; BANK_TYPE : string; DATA_IO_PRIM_TYPE : string; DATA_IO_IDLE_PWRDWN :string; IODELAY_GRP : string; nCK_PER_CLK : integer; nCS_PER_RANK : integer; BANK_WIDTH : integer; CKE_WIDTH : integer; CS_WIDTH : integer; CK_WIDTH : integer; CWL : integer; DDR2_DQSN_ENABLE : string; DM_WIDTH : integer; DQ_WIDTH : integer; DQS_CNT_WIDTH : integer; DQS_WIDTH : integer; DRAM_TYPE : string; RANKS : integer; ODT_WIDTH : integer; REG_CTRL : string; ROW_WIDTH : integer; USE_CS_PORT : integer; USE_DM_PORT : integer; USE_ODT_PORT : integer; IBUF_LPWR_MODE : string; LP_DDR_CK_WIDTH : integer; PHYCTL_CMD_FIFO : string; DATA_CTL_B0 : std_logic_vector(3 downto 0); DATA_CTL_B1 : std_logic_vector(3 downto 0); DATA_CTL_B2 : std_logic_vector(3 downto 0); DATA_CTL_B3 : std_logic_vector(3 downto 0); DATA_CTL_B4 : std_logic_vector(3 downto 0); BYTE_LANES_B0 : std_logic_vector(3 downto 0); BYTE_LANES_B1 : std_logic_vector(3 downto 0); BYTE_LANES_B2 : std_logic_vector(3 downto 0); BYTE_LANES_B3 : std_logic_vector(3 downto 0); BYTE_LANES_B4 : std_logic_vector(3 downto 0); PHY_0_BITLANES : std_logic_vector(47 downto 0); PHY_1_BITLANES : std_logic_vector(47 downto 0); PHY_2_BITLANES : std_logic_vector(47 downto 0); HIGHEST_BANK : integer; HIGHEST_LANE : integer; CK_BYTE_MAP : std_logic_vector(143 downto 0); ADDR_MAP : std_logic_vector(191 downto 0); BANK_MAP : std_logic_vector(35 downto 0); CAS_MAP : std_logic_vector(11 downto 0); CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0); CKE_MAP : std_logic_vector(95 downto 0); ODT_MAP : std_logic_vector(95 downto 0); CKE_ODT_AUX : string; CS_MAP : std_logic_vector(119 downto 0); PARITY_MAP : std_logic_vector(11 downto 0); RAS_MAP : std_logic_vector(11 downto 0); WE_MAP : std_logic_vector(11 downto 0); DQS_BYTE_MAP : std_logic_vector(143 downto 0); DATA0_MAP : std_logic_vector(95 downto 0); DATA1_MAP : std_logic_vector(95 downto 0); DATA2_MAP : std_logic_vector(95 downto 0); DATA3_MAP : std_logic_vector(95 downto 0); DATA4_MAP : std_logic_vector(95 downto 0); DATA5_MAP : std_logic_vector(95 downto 0); DATA6_MAP : std_logic_vector(95 downto 0); DATA7_MAP : std_logic_vector(95 downto 0); DATA8_MAP : std_logic_vector(95 downto 0); DATA9_MAP : std_logic_vector(95 downto 0); DATA10_MAP : std_logic_vector(95 downto 0); DATA11_MAP : std_logic_vector(95 downto 0); DATA12_MAP : std_logic_vector(95 downto 0); DATA13_MAP : std_logic_vector(95 downto 0); DATA14_MAP : std_logic_vector(95 downto 0); DATA15_MAP : std_logic_vector(95 downto 0); DATA16_MAP : std_logic_vector(95 downto 0); DATA17_MAP : std_logic_vector(95 downto 0); MASK0_MAP : std_logic_vector(107 downto 0); MASK1_MAP : std_logic_vector(107 downto 0); SIM_CAL_OPTION : string; MASTER_PHY_CTL : integer ); port ( rst : in std_logic; clk : in std_logic; freq_refclk : in std_logic; mem_refclk : in std_logic; pll_lock : in std_logic; sync_pulse : in std_logic; idelayctrl_refclk : in std_logic; phy_cmd_wr_en : in std_logic; phy_data_wr_en : in std_logic; phy_ctl_wd : in std_logic_vector(31 downto 0); phy_ctl_wr : in std_logic; phy_if_empty_def : in std_logic; phy_if_reset : in std_logic; data_offset_1 : in std_logic_vector(5 downto 0); data_offset_2 : in std_logic_vector(5 downto 0); aux_in_1 : in std_logic_vector(3 downto 0); aux_in_2 : in std_logic_vector(3 downto 0); idelaye2_init_val : out std_logic_vector(4 downto 0); oclkdelay_init_val : out std_logic_vector(5 downto 0); if_empty : out std_logic; phy_ctl_full : out std_logic; phy_cmd_full : out std_logic; phy_data_full : out std_logic; phy_pre_data_a_full : out std_logic; ddr_clk : out std_logic_vector(CK_WIDTH*LP_DDR_CK_WIDTH-1 downto 0); phy_mc_go : out std_logic; phy_write_calib : in std_logic; phy_read_calib : in std_logic; calib_in_common : in std_logic; calib_sel : in std_logic_vector(5 downto 0); calib_zero_inputs : in std_logic_vector(HIGHEST_BANK-1 downto 0); calib_zero_ctrl : in std_logic_vector(HIGHEST_BANK-1 downto 0); po_fine_enable : in std_logic_vector(2 downto 0); po_coarse_enable : in std_logic_vector(2 downto 0); po_fine_inc : in std_logic_vector(2 downto 0); po_coarse_inc : in std_logic_vector(2 downto 0); po_counter_load_en : in std_logic; po_counter_read_en : in std_logic; po_sel_fine_oclk_delay : in std_logic_vector(2 downto 0); po_counter_load_val : in std_logic_vector(8 downto 0); po_counter_read_val : out std_logic_vector(8 downto 0); pi_counter_read_val : out std_logic_vector(5 downto 0); pi_rst_dqs_find : in std_logic_vector(HIGHEST_BANK-1 downto 0); pi_fine_enable : in std_logic; pi_fine_inc : in std_logic; pi_counter_load_en : in std_logic; pi_counter_load_val : in std_logic_vector(5 downto 0); idelay_ce : in std_logic; idelay_inc : in std_logic; idelay_ld : in std_logic; idle : in std_logic; pi_phase_locked : out std_logic; pi_phase_locked_all : out std_logic; pi_dqs_found : out std_logic; pi_dqs_found_all : out std_logic; pi_dqs_out_of_range : out std_logic; phy_init_data_sel : in std_logic; mux_address : in std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0); mux_bank : in std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0); mux_cas_n : in std_logic_vector(nCK_PER_CLK-1 downto 0); mux_cs_n : in std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0); mux_ras_n : in std_logic_vector(nCK_PER_CLK-1 downto 0); mux_odt : in std_logic_vector(1 downto 0); mux_cke : in std_logic_vector(nCK_PER_CLK-1 downto 0); mux_we_n : in std_logic_vector(nCK_PER_CLK-1 downto 0); parity_in : in std_logic_vector(nCK_PER_CLK-1 downto 0); mux_wrdata : in std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0); mux_wrdata_mask : in std_logic_vector(2*nCK_PER_CLK*(DQ_WIDTH/8)-1 downto 0); mux_reset_n : in std_logic; rd_data : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0); ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0); ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0); ddr_cas_n : out std_logic; ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0); ddr_cs_n : out std_logic_vector(CS_WIDTH*nCS_PER_RANK-1 downto 0); ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0); ddr_odt : out std_logic_vector(ODT_WIDTH-1 downto 0); ddr_parity : out std_logic; ddr_ras_n : out std_logic; ddr_we_n : out std_logic; ddr_reset_n : out std_logic; ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0); ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0); ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0); dbg_pi_counter_read_en : in std_logic; ref_dll_lock : out std_logic; rst_phaser_ref : in std_logic; dbg_pi_phase_locked_phy4lanes : out std_logic_vector(11 downto 0); dbg_pi_dqs_found_lanes_phy4lanes : out std_logic_vector(11 downto 0) ); end component mig_7series_v1_8_ddr_mc_phy_wrapper; component mig_7series_v1_8_ddr_calib_top is generic ( TCQ : integer; nCK_PER_CLK : integer; tCK : integer; CLK_PERIOD : integer; N_CTL_LANES : integer; DRAM_TYPE : string; PRBS_WIDTH : integer; HIGHEST_LANE : integer; HIGHEST_BANK : integer; BANK_TYPE : string; BYTE_LANES_B0 : std_logic_vector(3 downto 0); BYTE_LANES_B1 : std_logic_vector(3 downto 0); BYTE_LANES_B2 : std_logic_vector(3 downto 0); BYTE_LANES_B3 : std_logic_vector(3 downto 0); BYTE_LANES_B4 : std_logic_vector(3 downto 0); DATA_CTL_B0 : std_logic_vector(3 downto 0); DATA_CTL_B1 : std_logic_vector(3 downto 0); DATA_CTL_B2 : std_logic_vector(3 downto 0); DATA_CTL_B3 : std_logic_vector(3 downto 0); DATA_CTL_B4 : std_logic_vector(3 downto 0); DQS_BYTE_MAP : std_logic_vector(143 downto 0); CTL_BYTE_LANE : std_logic_vector(7 downto 0); CTL_BANK : std_logic_vector(2 downto 0); SLOT_1_CONFIG : std_logic_vector(7 downto 0); BANK_WIDTH : integer; CA_MIRROR : string; COL_WIDTH : integer; nCS_PER_RANK : integer; DQ_WIDTH : integer; DQS_CNT_WIDTH : integer; DQS_WIDTH : integer; DRAM_WIDTH : integer; ROW_WIDTH : integer; RANKS : integer; CS_WIDTH : integer; CKE_WIDTH : integer; DDR2_DQSN_ENABLE : string; PER_BIT_DESKEW : string; CALIB_ROW_ADD : std_logic_vector(15 downto 0); CALIB_COL_ADD : std_logic_vector(11 downto 0); CALIB_BA_ADD : std_logic_vector(2 downto 0); AL : string; ADDR_CMD_MODE : string; BURST_MODE : string; BURST_TYPE : string; nCL : integer; nCWL : integer; tRFC : integer; OUTPUT_DRV : string; REG_CTRL : string; RTT_NOM : string; RTT_WR : string; USE_ODT_PORT : integer; WRLVL : string; PRE_REV3ES : string; SIM_INIT_OPTION : string; SIM_CAL_OPTION : string; CKE_ODT_AUX : string; DEBUG_PORT : string ); port ( clk : in std_logic; rst : in std_logic; slot_0_present : in std_logic_vector(7 downto 0); slot_1_present : in std_logic_vector(7 downto 0); phy_ctl_ready : in std_logic; phy_ctl_full : in std_logic; phy_cmd_full : in std_logic; phy_data_full : in std_logic; write_calib : out std_logic; read_calib : out std_logic; calib_ctl_wren : out std_logic; calib_cmd_wren : out std_logic; calib_seq : out std_logic_vector(1 downto 0); calib_aux_out : out std_logic_vector(3 downto 0); calib_cke : out std_logic_vector(nCK_PER_CLK-1 downto 0); calib_odt : out std_logic_vector(1 downto 0); calib_cmd : out std_logic_vector(2 downto 0); calib_wrdata_en : out std_logic; calib_rank_cnt : out std_logic_vector(1 downto 0); calib_cas_slot : out std_logic_vector(1 downto 0); calib_data_offset_0 : out std_logic_vector(5 downto 0); calib_data_offset_1 : out std_logic_vector(5 downto 0); calib_data_offset_2 : out std_logic_vector(5 downto 0); phy_address : out std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0); phy_bank : out std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0); phy_cs_n : out std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0); phy_ras_n : out std_logic_vector(nCK_PER_CLK-1 downto 0); phy_cas_n : out std_logic_vector(nCK_PER_CLK-1 downto 0); phy_we_n : out std_logic_vector(nCK_PER_CLK-1 downto 0); phy_reset_n : out std_logic; calib_sel : out std_logic_vector(5 downto 0); calib_in_common : out std_logic; calib_zero_inputs : out std_logic_vector(HIGHEST_BANK-1 downto 0); calib_zero_ctrl : out std_logic_vector(HIGHEST_BANK-1 downto 0); phy_if_empty_def : out std_logic; phy_if_reset : out std_logic; pi_phaselocked : in std_logic; pi_phase_locked_all : in std_logic; pi_found_dqs : in std_logic; pi_dqs_found_all : in std_logic; pi_dqs_found_lanes : in std_logic_vector(HIGHEST_LANE-1 downto 0); pi_counter_read_val : in std_logic_vector(5 downto 0); pi_rst_stg1_cal : out std_logic_vector(HIGHEST_BANK-1 downto 0); pi_en_stg2_f : out std_logic; pi_stg2_f_incdec : out std_logic; pi_stg2_load : out std_logic; pi_stg2_reg_l : out std_logic_vector(5 downto 0); idelay_ce : out std_logic; idelay_inc : out std_logic; idelay_ld : out std_logic; po_sel_stg2stg3 : out std_logic_vector(2 downto 0); po_stg2_c_incdec : out std_logic_vector(2 downto 0); po_en_stg2_c : out std_logic_vector(2 downto 0); po_stg2_f_incdec : out std_logic_vector(2 downto 0); po_en_stg2_f : out std_logic_vector(2 downto 0); po_counter_load_en : out std_logic; po_counter_read_val : in std_logic_vector(8 downto 0); device_temp : in std_logic_vector(11 downto 0); tempmon_sample_en : in std_logic; phy_if_empty : in std_logic; idelaye2_init_val : in std_logic_vector(4 downto 0); oclkdelay_init_val : in std_logic_vector(5 downto 0); tg_err : in std_logic; rst_tg_mc : out std_logic; phy_wrdata : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0); dlyval_dq : out std_logic_vector(5*RANKS*DQ_WIDTH-1 downto 0); phy_rddata : in std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0); calib_rd_data_offset_0 : out std_logic_vector(6*RANKS-1 downto 0); calib_rd_data_offset_1 : out std_logic_vector(6*RANKS-1 downto 0); calib_rd_data_offset_2 : out std_logic_vector(6*RANKS-1 downto 0); phy_rddata_valid : out std_logic; calib_writes : out std_logic; init_calib_complete : out std_logic; init_wrcal_complete : out std_logic; pi_phase_locked_err : out std_logic; pi_dqsfound_err : out std_logic; wrcal_err : out std_logic; dbg_pi_phaselock_start : out std_logic; dbg_pi_dqsfound_start : out std_logic; dbg_pi_dqsfound_done : out std_logic; dbg_wrcal_start : out std_logic; dbg_wrcal_done : out std_logic; dbg_wrlvl_start : out std_logic; dbg_wrlvl_done : out std_logic; dbg_wrlvl_err : out std_logic; dbg_wrlvl_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0); dbg_wrlvl_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0); dbg_phy_wrlvl : out std_logic_vector(255 downto 0); dbg_tap_cnt_during_wrlvl : out std_logic_vector(5 downto 0); dbg_wl_edge_detect_valid : out std_logic; dbg_rd_data_edge_detect : out std_logic_vector(DQS_WIDTH-1 downto 0); dbg_final_po_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0); dbg_final_po_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0); dbg_phy_wrcal : out std_logic_vector(99 downto 0); dbg_rdlvl_start : out std_logic_vector(1 downto 0); dbg_rdlvl_done : out std_logic_vector(1 downto 0); dbg_rdlvl_err : out std_logic_vector(1 downto 0); dbg_cpt_first_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0); dbg_cpt_second_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0); dbg_cpt_tap_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0); dbg_dq_idelay_tap_cnt : out std_logic_vector(5*DQS_WIDTH*RANKS-1 downto 0); dbg_sel_pi_incdec : in std_logic; dbg_sel_po_incdec : in std_logic; dbg_byte_sel : in std_logic_vector(DQS_CNT_WIDTH downto 0); dbg_pi_f_inc : in std_logic; dbg_pi_f_dec : in std_logic; dbg_po_f_inc : in std_logic; dbg_po_f_stg23_sel : in std_logic; dbg_po_f_dec : in std_logic; dbg_idel_up_all : in std_logic; dbg_idel_down_all : in std_logic; dbg_idel_up_cpt : in std_logic; dbg_idel_down_cpt : in std_logic; dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH-1 downto 0); dbg_sel_all_idel_cpt : in std_logic; dbg_phy_rdlvl : out std_logic_vector(255 downto 0); dbg_calib_top : out std_logic_vector(255 downto 0); dbg_phy_init : out std_logic_vector(255 downto 0); dbg_prbs_rdlvl : out std_logic_vector(255 downto 0); dbg_dqs_found_cal : out std_logic_vector(255 downto 0); dbg_phy_oclkdelay_cal : out std_logic_vector(255 downto 0); dbg_oclkdelay_rd_data : out std_logic_vector(DRAM_WIDTH*16-1 downto 0); dbg_oclkdelay_calib_start : out std_logic; dbg_oclkdelay_calib_done : out std_logic ); end component mig_7series_v1_8_ddr_calib_top; signal phy_din : std_logic_vector(HIGHEST_LANE*80-1 downto 0); signal phy_dout : std_logic_vector(HIGHEST_LANE*80-1 downto 0); signal ddr_cmd_ctl_data : std_logic_vector(HIGHEST_LANE*12-1 downto 0); signal aux_out : std_logic_vector((((HIGHEST_LANE+3)/4)*4)-1 downto 0); signal ddr_clk : std_logic_vector(CK_WIDTH * LP_DDR_CK_WIDTH-1 downto 0); signal phy_mc_go : std_logic; signal phy_ctl_full : std_logic; signal phy_cmd_full : std_logic; signal phy_data_full : std_logic; signal phy_pre_data_a_full : std_logic; signal if_empty : std_logic; signal phy_write_calib : std_logic; signal phy_read_calib : std_logic; signal rst_stg1_cal : std_logic_vector(HIGHEST_BANK-1 downto 0); signal calib_sel : std_logic_vector(5 downto 0); signal calib_in_common : std_logic; signal calib_zero_inputs : std_logic_vector(HIGHEST_BANK-1 downto 0); signal calib_zero_ctrl : std_logic_vector(HIGHEST_BANK-1 downto 0); signal pi_phase_locked : std_logic; signal pi_phase_locked_all : std_logic; signal pi_found_dqs : std_logic; signal pi_dqs_found_all : std_logic; signal pi_dqs_out_of_range : std_logic; signal pi_enstg2_f : std_logic; signal pi_stg2_fincdec : std_logic; signal pi_stg2_load : std_logic; signal pi_stg2_reg_l : std_logic_vector(5 downto 0); signal idelay_ce : std_logic; signal idelay_inc : std_logic; signal idelay_ld : std_logic; signal po_sel_stg2stg3 : std_logic_vector(2 downto 0); signal po_stg2_cincdec : std_logic_vector(2 downto 0); signal po_enstg2_c : std_logic_vector(2 downto 0); signal po_stg2_fincdec : std_logic_vector(2 downto 0); signal po_enstg2_f : std_logic_vector(2 downto 0); signal po_counter_read_val : std_logic_vector(8 downto 0); signal pi_counter_read_val : std_logic_vector(5 downto 0); signal phy_wrdata : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0); signal parity : std_logic_vector(nCK_PER_CLK-1 downto 0); signal phy_address : std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0); signal phy_bank : std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0); signal phy_cs_n : std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0); signal phy_ras_n : std_logic_vector(nCK_PER_CLK-1 downto 0); signal phy_cas_n : std_logic_vector(nCK_PER_CLK-1 downto 0); signal phy_we_n : std_logic_vector(nCK_PER_CLK-1 downto 0); signal phy_reset_n : std_logic; signal calib_aux_out : std_logic_vector(3 downto 0); signal calib_cke : std_logic_vector(nCK_PER_CLK-1 downto 0); signal calib_odt : std_logic_vector(1 downto 0); signal calib_ctl_wren : std_logic; signal calib_cmd_wren : std_logic; signal calib_wrdata_en : std_logic; signal calib_cmd : std_logic_vector(2 downto 0); signal calib_seq : std_logic_vector(1 downto 0); signal calib_data_offset_0 : std_logic_vector(5 downto 0); signal calib_data_offset_1 : std_logic_vector(5 downto 0); signal calib_data_offset_2 : std_logic_vector(5 downto 0); signal calib_rank_cnt : std_logic_vector(1 downto 0); signal calib_cas_slot : std_logic_vector(1 downto 0); signal mux_address : std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0); signal mux_aux_out : std_logic_vector(3 downto 0); signal aux_out_map : std_logic_vector(3 downto 0); signal mux_bank : std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0); signal mux_cmd : std_logic_vector(2 downto 0); signal mux_cmd_wren : std_logic; signal mux_cs_n : std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0); signal mux_ctl_wren : std_logic; signal mux_cas_slot : std_logic_vector(1 downto 0); signal mux_data_offset : std_logic_vector(5 downto 0); signal mux_data_offset_1 : std_logic_vector(5 downto 0); signal mux_data_offset_2 : std_logic_vector(5 downto 0); signal mux_ras_n : std_logic_vector(nCK_PER_CLK-1 downto 0); signal mux_cas_n : std_logic_vector(nCK_PER_CLK-1 downto 0); signal mux_rank_cnt : std_logic_vector(1 downto 0); signal mux_reset_n : std_logic; signal mux_we_n : std_logic_vector(nCK_PER_CLK-1 downto 0); signal mux_wrdata : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0); signal mux_wrdata_mask : std_logic_vector(2*nCK_PER_CLK*(DQ_WIDTH/8)-1 downto 0); signal mux_wrdata_en : std_logic; signal mux_cke : std_logic_vector(nCK_PER_CLK-1 downto 0); signal mux_odt : std_logic_vector(1 downto 0); signal phy_if_empty_def : std_logic; signal phy_if_reset : std_logic; signal phy_init_data_sel : std_logic; signal rd_data_map : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0); signal phy_rddata_valid_w : std_logic; signal rddata_valid_reg : std_logic; signal rd_data_reg : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0); signal idelaye2_init_val : std_logic_vector(4 downto 0); signal oclkdelay_init_val : std_logic_vector(5 downto 0); signal mc_cs_n_temp : std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0); signal calib_rd_data_offset_i0 : std_logic_vector(6*RANKS-1 downto 0); signal init_wrcal_complete_i : std_logic; signal phy_ctl_wd_i : std_logic_vector(31 downto 0); signal po_counter_load_en : std_logic; signal parity_0_wire : std_logic_vector((ROW_WIDTH+BANK_WIDTH+3)-1 downto 0); signal parity_1_wire : std_logic_vector((ROW_WIDTH+BANK_WIDTH+3)-1 downto 0); signal parity_2_wire : std_logic_vector((ROW_WIDTH+BANK_WIDTH+3)-1 downto 0); signal parity_3_wire : std_logic_vector((ROW_WIDTH+BANK_WIDTH+3)-1 downto 0); signal dbg_pi_dqs_found_lanes_phy4lanes_i : std_logic_vector(11 downto 0); signal all_zeros : std_logic_vector(8 downto 0):= (others => '0'); attribute keep : string; attribute max_fanout : integer; attribute keep of phy_rddata_valid_w : signal is "true"; attribute max_fanout of phy_rddata_valid_w : signal is 3; begin --*************************************************************************** dbg_rddata_valid <= rddata_valid_reg; dbg_rddata <= rd_data_reg; dbg_rd_data_offset <= calib_rd_data_offset_i0; calib_rd_data_offset_0 <= calib_rd_data_offset_i0; dbg_pi_phaselocked_done <= pi_phase_locked_all; dbg_po_counter_read_val <= po_counter_read_val; dbg_pi_counter_read_val <= pi_counter_read_val; dbg_pi_dqs_found_lanes_phy4lanes <= dbg_pi_dqs_found_lanes_phy4lanes_i; init_wrcal_complete <= init_wrcal_complete_i; --*************************************************************************** clock_gen : for i in 0 to (CK_WIDTH-1) generate ddr_ck(i) <= ddr_clk(LP_DDR_CK_WIDTH * i); ddr_ck_n(i) <= ddr_clk((LP_DDR_CK_WIDTH * i) + 1); end generate; --*************************************************************************** -- During memory initialization and calibration the calibration logic drives -- the memory signals. After calibration is complete the memory controller -- drives the memory signals. -- Do not expect timing issues in 4:1 mode at 800 MHz/1600 Mbps --*************************************************************************** cs_rdimm : if((REG_CTRL = "ON") and (DRAM_TYPE = "DDR3") and (RANKS = 1) and (nCS_PER_RANK = 2)) generate cs_rdimm_gen: for v in 0 to (CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK)-1 generate cs_rdimm_gen_i : if((v mod (CS_WIDTH*nCS_PER_RANK)) = 0) generate mc_cs_n_temp(v) <= mc_cs_n(v) ; end generate; cs_rdimm_gen_j : if(not((v mod (CS_WIDTH*nCS_PER_RANK)) = 0)) generate mc_cs_n_temp(v) <= '1' ; end generate; end generate; end generate; cs_others : if(not(REG_CTRL = "ON") or not(DRAM_TYPE = "DDR3") or not(RANKS = 1) or not(nCS_PER_RANK = 2)) generate mc_cs_n_temp <= mc_cs_n ; end generate; mux_wrdata <= mc_wrdata when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_wrdata; mux_wrdata_mask <= mc_wrdata_mask when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else (others => '0'); mux_address <= mc_address when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_address; mux_bank <= mc_bank when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_bank; mux_cs_n <= mc_cs_n_temp when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_cs_n; mux_ras_n <= mc_ras_n when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_ras_n; mux_cas_n <= mc_cas_n when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_cas_n; mux_we_n <= mc_we_n when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_we_n; mux_reset_n <= mc_reset_n when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_reset_n; mux_aux_out <= mc_aux_out0 when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_aux_out; mux_odt <= mc_odt when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_odt; mux_cke <= mc_cke when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_cke; mux_cmd_wren <= mc_cmd_wren when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_cmd_wren; mux_ctl_wren <= mc_ctl_wren when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_ctl_wren; mux_wrdata_en <= mc_wrdata_en when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_wrdata_en; mux_cmd <= mc_cmd when (phy_init_data_sel ='1' or init_wrcal_complete_i ='1') else calib_cmd; mux_cas_slot <= mc_cas_slot when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_cas_slot; mux_data_offset <= mc_data_offset when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_data_offset_0; mux_data_offset_1 <= mc_data_offset_1 when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_data_offset_1; mux_data_offset_2 <= mc_data_offset_2 when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_data_offset_2; -- Reserved field. Hard coded to 2'b00 irrespective of the number of ranks. CR 643601 mux_rank_cnt <= "00"; -- Assigning cke & odt for DDR2 & DDR3 -- No changes for DDR3 & DDR2 dual rank -- DDR2 single rank systems might potentially need 3 odt signals. -- Aux_out[2] will have the odt toggled by phy and controller -- wiring aux_out[2] to 0 & 3. Depending upon the odt parameter -- all of the three odt bits or some of them might be used. -- mapping done in mc_phy_wrapper module aux_out_gen : if(CKE_ODT_AUX = "TRUE") generate aux_out_map <= (mux_aux_out(1) & mux_aux_out(1) & mux_aux_out(1) & mux_aux_out(0)) when ((DRAM_TYPE = "DDR2") and (RANKS = 1)) else mux_aux_out; end generate; wo_aux_out_gen : if(not(CKE_ODT_AUX = "TRUE")) generate aux_out_map <= "0000"; end generate; init_calib_complete <= phy_init_data_sel; phy_mc_ctl_full <= phy_ctl_full; phy_mc_cmd_full <= phy_cmd_full; phy_mc_data_full <= phy_pre_data_a_full; --*************************************************************************** -- Generate parity for DDR3 RDIMM. --*************************************************************************** gen_ddr3_parity : if ((DRAM_TYPE = "DDR3") and (REG_CTRL = "ON")) generate gen_ddr3_parity_4by1: if (nCK_PER_CLK = 4) generate parity_0_wire <= (mux_address((ROW_WIDTH*4)-1 downto ROW_WIDTH*3) & mux_bank((BANK_WIDTH*4)-1 downto BANK_WIDTH*3) & mux_cas_n(3) & mux_ras_n(3) & mux_we_n(3)); parity_1_wire <= (mux_address(ROW_WIDTH-1 downto 0) & mux_bank(BANK_WIDTH-1 downto 0) & mux_cas_n(0) & mux_ras_n(0) & mux_we_n(0)); parity_2_wire <= (mux_address((ROW_WIDTH*2)-1 downto ROW_WIDTH) & mux_bank((BANK_WIDTH*2)-1 downto BANK_WIDTH) & mux_cas_n(1) & mux_ras_n(1) & mux_we_n(1)); parity_3_wire <= (mux_address((ROW_WIDTH*3)-1 downto ROW_WIDTH*2) & mux_bank((BANK_WIDTH*3)-1 downto BANK_WIDTH*2) & mux_cas_n(2) & mux_ras_n(2) & mux_we_n(2)); process (clk) begin if (clk'event and clk = '1') then parity(0) <= ODD_PARITY(parity_0_wire) after (TCQ) * 1 ps; end if; end process; process (mux_address, mux_bank, mux_cas_n, mux_ras_n, mux_we_n) begin parity(1) <= ODD_PARITY(parity_1_wire) after (TCQ) * 1 ps; parity(2) <= ODD_PARITY(parity_2_wire) after (TCQ) * 1 ps; parity(3) <= ODD_PARITY(parity_3_wire) after (TCQ) * 1 ps; end process; end generate; gen_ddr3_parity_2by1: if ( not(nCK_PER_CLK = 4)) generate parity_1_wire <= (mux_address(ROW_WIDTH-1 downto 0) & mux_bank(BANK_WIDTH-1 downto 0) & mux_cas_n(0) & mux_ras_n(0) & mux_we_n(0)); parity_2_wire <= (mux_address((ROW_WIDTH*2)-1 downto ROW_WIDTH) & mux_bank((BANK_WIDTH*2)-1 downto BANK_WIDTH) & mux_cas_n(1) & mux_ras_n(1) & mux_we_n(1)); process (clk) begin if (clk'event and clk='1') then parity(0) <= ODD_PARITY(parity_2_wire) after (TCQ) * 1 ps; end if; end process; process(mux_address, mux_bank, mux_cas_n, mux_ras_n, mux_we_n) begin parity(1) <= ODD_PARITY(parity_1_wire) after (TCQ) * 1 ps; end process; end generate; end generate; gen_ddr3_noparity : if (not(DRAM_TYPE = "DDR3") or not(REG_CTRL = "ON")) generate gen_ddr3_noparity_4by1 : if (nCK_PER_CLK = 4) generate process (clk) begin if (clk'event and clk='1') then parity(0) <= '0' after (TCQ)*1 ps; parity(1) <= '0' after (TCQ)*1 ps; parity(2) <= '0' after (TCQ)*1 ps; parity(3) <= '0' after (TCQ)*1 ps; end if; end process; end generate; gen_ddr3_noparity_2by1 : if (not(nCK_PER_CLK = 4)) generate process (clk) begin if (clk'event and clk='1') then parity(0) <= '0' after (TCQ)*1 ps; parity(1) <= '0' after (TCQ)*1 ps; end if; end process; end generate; end generate; --*************************************************************************** -- Code for optional register stage in read path to MC for timing --*************************************************************************** RD_REG_TIMING : if(RD_PATH_REG = 1) generate process (clk) begin if (clk'event and clk='1') then rddata_valid_reg <= phy_rddata_valid_w after (TCQ)*1 ps; rd_data_reg <= rd_data_map after (TCQ)*1 ps; end if; end process; end generate; RD_REG_NO_TIMING : if( not(RD_PATH_REG = 1)) generate process (phy_rddata_valid_w, rd_data_map) begin rddata_valid_reg <= phy_rddata_valid_w; rd_data_reg <= rd_data_map; end process; end generate; phy_rddata_valid <= rddata_valid_reg; phy_rd_data <= rd_data_reg; --*************************************************************************** -- Hard PHY and accompanying bit mapping logic --*************************************************************************** phy_ctl_wd_i <= ("00000" & mux_cas_slot & calib_seq & mux_data_offset & mux_rank_cnt & "000" & aux_out_map & "00000" & mux_cmd); u_ddr_mc_phy_wrapper : mig_7series_v1_8_ddr_mc_phy_wrapper generic map ( TCQ => TCQ, tCK => tCK, BANK_TYPE => BANK_TYPE, DATA_IO_PRIM_TYPE => DATA_IO_PRIM_TYPE, IODELAY_GRP => IODELAY_GRP, DATA_IO_IDLE_PWRDWN=> DATA_IO_IDLE_PWRDWN, nCK_PER_CLK => nCK_PER_CLK, nCS_PER_RANK => nCS_PER_RANK, BANK_WIDTH => BANK_WIDTH, CKE_WIDTH => CKE_WIDTH, CS_WIDTH => CS_WIDTH, CK_WIDTH => CK_WIDTH, CWL => CWL, DDR2_DQSN_ENABLE => DDR2_DQSN_ENABLE, DM_WIDTH => DM_WIDTH, DQ_WIDTH => DQ_WIDTH, DQS_CNT_WIDTH => DQS_CNT_WIDTH, DQS_WIDTH => DQS_WIDTH, DRAM_TYPE => DRAM_TYPE, RANKS => RANKS, ODT_WIDTH => ODT_WIDTH, REG_CTRL => REG_CTRL, ROW_WIDTH => ROW_WIDTH, USE_CS_PORT => USE_CS_PORT, USE_DM_PORT => USE_DM_PORT, USE_ODT_PORT => USE_ODT_PORT, IBUF_LPWR_MODE => IBUF_LPWR_MODE, LP_DDR_CK_WIDTH => LP_DDR_CK_WIDTH, PHYCTL_CMD_FIFO => PHYCTL_CMD_FIFO, DATA_CTL_B0 => DATA_CTL_B0, DATA_CTL_B1 => DATA_CTL_B1, DATA_CTL_B2 => DATA_CTL_B2, DATA_CTL_B3 => DATA_CTL_B3, DATA_CTL_B4 => DATA_CTL_B4, BYTE_LANES_B0 => BYTE_LANES_B0, BYTE_LANES_B1 => BYTE_LANES_B1, BYTE_LANES_B2 => BYTE_LANES_B2, BYTE_LANES_B3 => BYTE_LANES_B3, BYTE_LANES_B4 => BYTE_LANES_B4, PHY_0_BITLANES => PHY_0_BITLANES, PHY_1_BITLANES => PHY_1_BITLANES, PHY_2_BITLANES => PHY_2_BITLANES, HIGHEST_BANK => HIGHEST_BANK, HIGHEST_LANE => HIGHEST_LANE, CK_BYTE_MAP => CK_BYTE_MAP, ADDR_MAP => ADDR_MAP, BANK_MAP => BANK_MAP, CAS_MAP => CAS_MAP, CKE_ODT_BYTE_MAP => CKE_ODT_BYTE_MAP, CKE_MAP => CKE_MAP, ODT_MAP => ODT_MAP, CKE_ODT_AUX => CKE_ODT_AUX, CS_MAP => CS_MAP, PARITY_MAP => PARITY_MAP, RAS_MAP => RAS_MAP, WE_MAP => WE_MAP, DQS_BYTE_MAP => DQS_BYTE_MAP, DATA0_MAP => DATA0_MAP, DATA1_MAP => DATA1_MAP, DATA2_MAP => DATA2_MAP, DATA3_MAP => DATA3_MAP, DATA4_MAP => DATA4_MAP, DATA5_MAP => DATA5_MAP, DATA6_MAP => DATA6_MAP, DATA7_MAP => DATA7_MAP, DATA8_MAP => DATA8_MAP, DATA9_MAP => DATA9_MAP, DATA10_MAP => DATA10_MAP, DATA11_MAP => DATA11_MAP, DATA12_MAP => DATA12_MAP, DATA13_MAP => DATA13_MAP, DATA14_MAP => DATA14_MAP, DATA15_MAP => DATA15_MAP, DATA16_MAP => DATA16_MAP, DATA17_MAP => DATA17_MAP, MASK0_MAP => MASK0_MAP, MASK1_MAP => MASK1_MAP, SIM_CAL_OPTION => SIM_CAL_OPTION, MASTER_PHY_CTL => MASTER_PHY_CTL ) port map ( rst => rst, clk => clk, -- For memory frequencies between 400~1066 MHz freq_refclk = mem_refclk -- For memory frequencies below 400 MHz mem_refclk = mem_refclk and -- freq_refclk = 2x or 4x mem_refclk such that it remains in the -- 400~1066 MHz range freq_refclk => freq_refclk, mem_refclk => mem_refclk, pll_lock => pll_lock, sync_pulse => sync_pulse, idelayctrl_refclk => clk_ref, phy_cmd_wr_en => mux_cmd_wren, phy_data_wr_en => mux_wrdata_en, -- phy_ctl_wd = {ACTPRE[31:30],EventDelay[29:25],seq[24:23], -- DataOffset[22:17],HiIndex[16:15],LowIndex[14:12], -- AuxOut[11:8],ControlOffset[7:3],PHYCmd[2:0]} -- The fields ACTPRE, and BankCount are only used -- when the hard PHY counters are used by the MC. phy_ctl_wd => phy_ctl_wd_i, phy_ctl_wr => mux_ctl_wren, phy_if_empty_def => phy_if_empty_def, phy_if_reset => phy_if_reset, data_offset_1 => mux_data_offset_1, data_offset_2 => mux_data_offset_2, aux_in_1 => aux_out_map, aux_in_2 => aux_out_map, idelaye2_init_val => idelaye2_init_val, oclkdelay_init_val => oclkdelay_init_val, if_empty => if_empty, phy_ctl_full => phy_ctl_full, phy_cmd_full => phy_cmd_full, phy_data_full => phy_data_full, phy_pre_data_a_full => phy_pre_data_a_full, ddr_clk => ddr_clk, phy_mc_go => phy_mc_go, phy_write_calib => phy_write_calib, phy_read_calib => phy_read_calib, calib_in_common => calib_in_common, calib_sel => calib_sel, calib_zero_inputs => calib_zero_inputs, calib_zero_ctrl => calib_zero_ctrl, po_fine_enable => po_enstg2_f, po_coarse_enable => po_enstg2_c, po_fine_inc => po_stg2_fincdec, po_coarse_inc => po_stg2_cincdec, po_counter_load_en => po_counter_load_en, po_counter_read_en => '1', po_sel_fine_oclk_delay => po_sel_stg2stg3, po_counter_load_val => all_zeros, po_counter_read_val => po_counter_read_val, pi_counter_read_val => pi_counter_read_val, pi_rst_dqs_find => rst_stg1_cal, pi_fine_enable => pi_enstg2_f, pi_fine_inc => pi_stg2_fincdec, pi_counter_load_en => pi_stg2_load, pi_counter_load_val => pi_stg2_reg_l, idelay_ce => idelay_ce, idelay_inc => idelay_inc, idelay_ld => idelay_ld, idle => idle, pi_phase_locked => pi_phase_locked, pi_phase_locked_all => pi_phase_locked_all, pi_dqs_found => pi_found_dqs, pi_dqs_found_all => pi_dqs_found_all, -- Currently not being used. May be used in future if periodic reads -- become a requirement. This output could also be used to signal a -- catastrophic failure in read capture and the need for re-cal pi_dqs_out_of_range => pi_dqs_out_of_range, phy_init_data_sel => phy_init_data_sel, mux_address => mux_address, mux_bank => mux_bank, mux_cas_n => mux_cas_n, mux_cs_n => mux_cs_n, mux_ras_n => mux_ras_n, mux_odt => mux_odt, mux_cke => mux_cke, mux_we_n => mux_we_n, parity_in => parity, mux_wrdata => mux_wrdata, mux_wrdata_mask => mux_wrdata_mask, mux_reset_n => mux_reset_n, rd_data => rd_data_map, ddr_addr => ddr_addr, ddr_ba => ddr_ba, ddr_cas_n => ddr_cas_n, ddr_cke => ddr_cke, ddr_cs_n => ddr_cs_n, ddr_dm => ddr_dm, ddr_odt => ddr_odt, ddr_parity => ddr_parity, ddr_ras_n => ddr_ras_n, ddr_we_n => ddr_we_n, ddr_reset_n => ddr_reset_n, ddr_dq => ddr_dq, ddr_dqs => ddr_dqs, ddr_dqs_n => ddr_dqs_n, dbg_pi_counter_read_en => '1', ref_dll_lock => ref_dll_lock, rst_phaser_ref => rst_phaser_ref, dbg_pi_phase_locked_phy4lanes => dbg_pi_phase_locked_phy4lanes, dbg_pi_dqs_found_lanes_phy4lanes => dbg_pi_dqs_found_lanes_phy4lanes_i ); --*************************************************************************** -- Soft memory initialization and calibration logic --*************************************************************************** u_ddr_calib_top : mig_7series_v1_8_ddr_calib_top generic map ( TCQ => TCQ, nCK_PER_CLK => nCK_PER_CLK, tCK => tCK, CLK_PERIOD => CLK_PERIOD, N_CTL_LANES => N_CTL_LANES, DRAM_TYPE => DRAM_TYPE, PRBS_WIDTH => 8, HIGHEST_LANE => HIGHEST_LANE, HIGHEST_BANK => HIGHEST_BANK, BANK_TYPE => BANK_TYPE, BYTE_LANES_B0 => BYTE_LANES_B0, BYTE_LANES_B1 => BYTE_LANES_B1, BYTE_LANES_B2 => BYTE_LANES_B2, BYTE_LANES_B3 => BYTE_LANES_B3, BYTE_LANES_B4 => BYTE_LANES_B4, DATA_CTL_B0 => DATA_CTL_B0, DATA_CTL_B1 => DATA_CTL_B1, DATA_CTL_B2 => DATA_CTL_B2, DATA_CTL_B3 => DATA_CTL_B3, DATA_CTL_B4 => DATA_CTL_B4, DQS_BYTE_MAP => DQS_BYTE_MAP, CTL_BYTE_LANE => CTL_BYTE_LANE, CTL_BANK => CTL_BANK, SLOT_1_CONFIG => SLOT_1_CONFIG, BANK_WIDTH => BANK_WIDTH, CA_MIRROR => CA_MIRROR, COL_WIDTH => COL_WIDTH, nCS_PER_RANK => nCS_PER_RANK, DQ_WIDTH => DQ_WIDTH, DQS_CNT_WIDTH => DQS_CNT_WIDTH, DQS_WIDTH => DQS_WIDTH, DRAM_WIDTH => DRAM_WIDTH, ROW_WIDTH => ROW_WIDTH, RANKS => RANKS, CS_WIDTH => CS_WIDTH, CKE_WIDTH => CKE_WIDTH, DDR2_DQSN_ENABLE => DDR2_DQSN_ENABLE, PER_BIT_DESKEW => "OFF", CALIB_ROW_ADD => CALIB_ROW_ADD, CALIB_COL_ADD => CALIB_COL_ADD, CALIB_BA_ADD => CALIB_BA_ADD, AL => AL, ADDR_CMD_MODE => ADDR_CMD_MODE, BURST_MODE => BURST_MODE, BURST_TYPE => BURST_TYPE, nCL => CL, nCWL => CWL, tRFC => tRFC, OUTPUT_DRV => OUTPUT_DRV, REG_CTRL => REG_CTRL, RTT_NOM => RTT_NOM, RTT_WR => RTT_WR, USE_ODT_PORT => USE_ODT_PORT, WRLVL => WRLVL_W, PRE_REV3ES => PRE_REV3ES, SIM_INIT_OPTION => SIM_INIT_OPTION, SIM_CAL_OPTION => SIM_CAL_OPTION, CKE_ODT_AUX => CKE_ODT_AUX, DEBUG_PORT => DEBUG_PORT ) port map ( clk => clk, rst => rst, slot_0_present => slot_0_present, slot_1_present => slot_1_present, -- PHY Control Block and IN_FIFO status phy_ctl_ready => phy_mc_go, phy_ctl_full => '0', phy_cmd_full => '0', phy_data_full => '0', -- hard PHY calibration modes write_calib => phy_write_calib, read_calib => phy_read_calib, -- Signals from calib logic to be MUXED with MC -- signals before sending to hard PHY calib_ctl_wren => calib_ctl_wren, calib_cmd_wren => calib_cmd_wren, calib_seq => calib_seq, calib_aux_out => calib_aux_out, calib_odt => calib_odt, calib_cke => calib_cke, calib_cmd => calib_cmd, calib_wrdata_en => calib_wrdata_en, calib_rank_cnt => calib_rank_cnt, calib_cas_slot => calib_cas_slot, calib_data_offset_0 => calib_data_offset_0, calib_data_offset_1 => calib_data_offset_1, calib_data_offset_2 => calib_data_offset_2, phy_address => phy_address, phy_bank => phy_bank, phy_cs_n => phy_cs_n, phy_ras_n => phy_ras_n, phy_cas_n => phy_cas_n, phy_we_n => phy_we_n, phy_reset_n => phy_reset_n, -- DQS count and ck/addr/cmd to be mapped to calib_sel -- based on parameter that defines placement of ctl lanes -- and DQS byte groups in each bank. When phy_write_calib -- is de-asserted calib_sel should select CK/addr/cmd/ctl. calib_sel => calib_sel, calib_in_common => calib_in_common, calib_zero_inputs => calib_zero_inputs, calib_zero_ctrl => calib_zero_ctrl, phy_if_empty_def => phy_if_empty_def, phy_if_reset => phy_if_reset, -- DQS Phaser_IN calibration/status signals pi_phaselocked => pi_phase_locked, pi_phase_locked_all => pi_phase_locked_all, pi_found_dqs => pi_found_dqs, pi_dqs_found_all => pi_dqs_found_all, pi_dqs_found_lanes => dbg_pi_dqs_found_lanes_phy4lanes_i(HIGHEST_LANE-1 downto 0), pi_rst_stg1_cal => rst_stg1_cal, pi_en_stg2_f => pi_enstg2_f, pi_stg2_f_incdec => pi_stg2_fincdec, pi_stg2_load => pi_stg2_load, pi_stg2_reg_l => pi_stg2_reg_l, pi_counter_read_val => pi_counter_read_val, device_temp => device_temp, tempmon_sample_en => tempmon_sample_en, -- IDELAY tap enable and inc signals idelay_ce => idelay_ce, idelay_inc => idelay_inc, idelay_ld => idelay_ld, -- DQS Phaser_OUT calibration/status signals po_sel_stg2stg3 => po_sel_stg2stg3, po_stg2_c_incdec => po_stg2_cincdec, po_en_stg2_c => po_enstg2_c, po_stg2_f_incdec => po_stg2_fincdec, po_en_stg2_f => po_enstg2_f, po_counter_load_en => po_counter_load_en, po_counter_read_val => po_counter_read_val, phy_if_empty => if_empty, idelaye2_init_val => idelaye2_init_val, oclkdelay_init_val => oclkdelay_init_val, tg_err => error, rst_tg_mc => rst_tg_mc, phy_wrdata => phy_wrdata, -- From calib logic To data IN_FIFO -- DQ IDELAY tap value from Calib logic -- port to be added to mc_phy by Gary dlyval_dq => open, -- From data IN_FIFO To Calib logic and MC/UI phy_rddata => rd_data_map, -- From calib logic To MC phy_rddata_valid => phy_rddata_valid_w, calib_rd_data_offset_0 => calib_rd_data_offset_i0, calib_rd_data_offset_1 => calib_rd_data_offset_1, calib_rd_data_offset_2 => calib_rd_data_offset_2, calib_writes => open, -- Mem Init and Calibration status To MC init_calib_complete => phy_init_data_sel, init_wrcal_complete => init_wrcal_complete_i, -- Debug Error signals pi_phase_locked_err => dbg_pi_phaselock_err, pi_dqsfound_err => dbg_pi_dqsfound_err, wrcal_err => dbg_wrcal_err, -- Debug Signals dbg_pi_phaselock_start => dbg_pi_phaselock_start, dbg_pi_dqsfound_start => dbg_pi_dqsfound_start, dbg_pi_dqsfound_done => dbg_pi_dqsfound_done, dbg_wrcal_start => dbg_wrcal_start, dbg_wrcal_done => dbg_wrcal_done, dbg_wrlvl_start => dbg_wrlvl_start, dbg_wrlvl_done => dbg_wrlvl_done, dbg_wrlvl_err => dbg_wrlvl_err, dbg_wrlvl_fine_tap_cnt => dbg_wrlvl_fine_tap_cnt, dbg_wrlvl_coarse_tap_cnt => dbg_wrlvl_coarse_tap_cnt, dbg_phy_wrlvl => dbg_phy_wrlvl, dbg_tap_cnt_during_wrlvl => dbg_tap_cnt_during_wrlvl, dbg_wl_edge_detect_valid => dbg_wl_edge_detect_valid, dbg_rd_data_edge_detect => dbg_rd_data_edge_detect, dbg_final_po_fine_tap_cnt => dbg_final_po_fine_tap_cnt, dbg_final_po_coarse_tap_cnt => dbg_final_po_coarse_tap_cnt, dbg_phy_wrcal => dbg_phy_wrcal, dbg_rdlvl_start => dbg_rdlvl_start, dbg_rdlvl_done => dbg_rdlvl_done, dbg_rdlvl_err => dbg_rdlvl_err, dbg_cpt_first_edge_cnt => dbg_cpt_first_edge_cnt, dbg_cpt_second_edge_cnt => dbg_cpt_second_edge_cnt, dbg_cpt_tap_cnt => dbg_cpt_tap_cnt, dbg_dq_idelay_tap_cnt => dbg_dq_idelay_tap_cnt, dbg_sel_pi_incdec => dbg_sel_pi_incdec, dbg_sel_po_incdec => dbg_sel_po_incdec, dbg_byte_sel => dbg_byte_sel, dbg_pi_f_inc => dbg_pi_f_inc, dbg_pi_f_dec => dbg_pi_f_dec, dbg_po_f_inc => dbg_po_f_inc, dbg_po_f_stg23_sel => dbg_po_f_stg23_sel, dbg_po_f_dec => dbg_po_f_dec, dbg_idel_up_all => dbg_idel_up_all, dbg_idel_down_all => dbg_idel_down_all, dbg_idel_up_cpt => dbg_idel_up_cpt, dbg_idel_down_cpt => dbg_idel_down_cpt, dbg_sel_idel_cpt => dbg_sel_idel_cpt, dbg_sel_all_idel_cpt => dbg_sel_all_idel_cpt, dbg_phy_rdlvl => dbg_phy_rdlvl, dbg_calib_top => dbg_calib_top, dbg_phy_init => dbg_phy_init, dbg_prbs_rdlvl => dbg_prbs_rdlvl, dbg_dqs_found_cal => dbg_dqs_found_cal, dbg_phy_oclkdelay_cal => dbg_phy_oclkdelay_cal, dbg_oclkdelay_rd_data => dbg_oclkdelay_rd_data, dbg_oclkdelay_calib_start => dbg_oclkdelay_calib_start, dbg_oclkdelay_calib_done => dbg_oclkdelay_calib_done ); end architecture arch_ddr_phy_top;
-- Implementation of Filter H_a3(z) -- using Complex Frequency sampling filer (FSF) as Hilbert transformer -- -- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License -- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License along with this program; -- if not, see <http://www.gnu.org/licenses/>. library ieee; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_signed.all; package analytic_filter_h_a3_pkg is component analytic_filter_h_a3 generic( data_width : integer ); port( clk_i : in std_logic; rst_i : in std_logic; data_i : in std_logic_vector(data_width-1 downto 0); data_str_i : in std_logic; data_i_o : out std_logic_vector(data_width-1 downto 0); data_q_o : out std_logic_vector(data_width-1 downto 0); data_str_o : out std_logic ); end component; end analytic_filter_h_a3_pkg; package body analytic_filter_h_a3_pkg is end analytic_filter_h_a3_pkg; -- Entity Definition library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; use work.fsf_comb_filter_pkg.all; use work.fsf_pole_filter_pkg.all; use work.fsf_pole_filter_coeff_def_pkg.all; use work.complex_fsf_filter_c_90_pkg.all; use work.complex_fsf_filter_inv_c_m30_m150_pkg.all; use work.resize_tools_pkg.all; entity analytic_filter_h_a3 is generic( data_width : integer := 16 ); port( clk_i : in std_logic; rst_i : in std_logic; data_i : in std_logic_vector(data_width-1 downto 0); data_str_i : in std_logic; data_i_o : out std_logic_vector(data_width-1 downto 0); data_q_o : out std_logic_vector(data_width-1 downto 0); data_str_o : out std_logic ); end analytic_filter_h_a3; architecture analytic_filter_h_a3_arch of analytic_filter_h_a3 is --signal y : std_logic_vector (data_width-1 downto 0); --signal x : std_logic_vector (data_width-1 downto 0); signal data_i_res : std_logic_vector (data_width-1 downto 0); signal t1 : std_logic_vector (data_width-1 downto 0); signal t1_res : std_logic_vector (data_width-1 downto 0); signal t2 : std_logic_vector (data_width-1 downto 0); signal t3 : std_logic_vector (data_width-1 downto 0); signal t4 : std_logic_vector (data_width-1 downto 0); signal c1_i : std_logic_vector (data_width-1 downto 0); signal c1_q : std_logic_vector (data_width-1 downto 0); signal c2_i : std_logic_vector (data_width-1 downto 0); signal c2_q : std_logic_vector (data_width-1 downto 0); signal c2_i_res : std_logic_vector (data_width-1 downto 0); signal c2_q_res : std_logic_vector (data_width-1 downto 0); signal c3_i : std_logic_vector (data_width-1 downto 0); signal c3_q : std_logic_vector (data_width-1 downto 0); signal c3_i_res : std_logic_vector (data_width-1 downto 0); signal c3_q_res : std_logic_vector (data_width-1 downto 0); signal c4_i : std_logic_vector (data_width-1 downto 0); signal c4_q : std_logic_vector (data_width-1 downto 0); signal t1_str : std_logic; signal t2_str : std_logic; signal t3_str : std_logic; signal t4_str : std_logic; signal c1_str : std_logic; signal c2_str : std_logic; signal c3_str : std_logic; signal c4_str : std_logic; begin data_i_res <= resize_to_msb_round(std_logic_vector(shift_right(signed(data_i),1)),data_width); comb_stage1 : fsf_comb_filter generic map ( data_width => data_width, comb_delay => 4 ) port map( clk_i => clk_i, rst_i => rst_i, data_i => data_i_res, data_str_i => data_str_i, data_o => t1, data_str_o => t1_str ); t1_res <= resize_to_msb_round(std_logic_vector(shift_right(signed(t1),1)),data_width); comb_stage2 : fsf_comb_filter generic map ( data_width => data_width, comb_delay => 4 ) port map( clk_i => clk_i, rst_i => rst_i, data_i => t1_res, data_str_i => t1_str, data_o => t2, data_str_o => t2_str ); c_0_180_filter1 : fsf_pole_filter generic map ( data_width => data_width, coeff => c_0_180_coeff, no_of_coefficients => 2 ) port map( clk_i => clk_i, rst_i => rst_i, data_i => t2, data_str_i => t2_str, data_o => t3, data_str_o => t3_str ); c_0_180_filter2 : fsf_pole_filter generic map ( data_width => data_width, coeff => c_0_180_coeff, no_of_coefficients => 2 ) port map( clk_i => clk_i, rst_i => rst_i, data_i => t3, data_str_i => t3_str, data_o => t4, data_str_o => t4_str ); complex_fsf_filter_c_90_1 : complex_fsf_filter_c_90 generic map ( data_width => data_width ) port map( clk_i => clk_i, rst_i => rst_i, data_i_i => t4, data_q_i => (others => '0'), data_str_i => t4_str, data_i_o => c1_i, data_q_o => c1_q, data_str_o => c1_str ); complex_fsf_filter_c_90_2 : complex_fsf_filter_c_90 generic map ( data_width => data_width ) port map( clk_i => clk_i, rst_i => rst_i, data_i_i => c1_i, data_q_i => c1_q, data_str_i => c1_str, data_i_o => c2_i, data_q_o => c2_q, data_str_o => c2_str ); c2_i_res <= resize_to_msb_round(std_logic_vector(shift_right(signed(c2_i),1)),data_width); c2_q_res <= resize_to_msb_round(std_logic_vector(shift_right(signed(c2_q),1)),data_width); complex_fsf_filter_inv_c_m30_m150_1 : complex_fsf_filter_inv_c_m30_m150 generic map ( data_width => data_width ) port map( clk_i => clk_i, rst_i => rst_i, data_i_i => c2_i_res, data_q_i => c2_q_res, data_str_i => c2_str, data_i_o => c3_i, data_q_o => c3_q, data_str_o => c3_str ); c3_i_res <= resize_to_msb_round(std_logic_vector(shift_right(signed(c3_i),2)),data_width); c3_q_res <= resize_to_msb_round(std_logic_vector(shift_right(signed(c3_q),2)),data_width); complex_fsf_filter_inv_c_m30_m150_2 : complex_fsf_filter_inv_c_m30_m150 generic map ( data_width => data_width ) port map( clk_i => clk_i, rst_i => rst_i, data_i_i => c3_i_res, data_q_i => c3_q_res, data_str_i => c3_str, data_i_o => c4_i, data_q_o => c4_q, data_str_o => c4_str ); data_i_o <= c4_i; data_q_o <= c4_q; data_str_o <= c4_str; end analytic_filter_h_a3_arch;
------------------------------------------------------------------------------------------------------------------------ -- POWERLINK IP-Core -- -- Copyright (C) 2010 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------------------------------------------------ -- Version History ------------------------------------------------------------------------------------------------------------------------ -- 2010-08-23 V0.01 zelenkaj First version -- 2010-09-13 V0.02 zelenkaj added selection Rmii / Mii -- 2010-10-18 V0.03 zelenkaj added selection Big/Little Endian (pdi_par) -- use bidirectional bus (pdi_par) -- 2010-11-23 V0.04 zelenkaj Added 2 GPIO signals to parallel interface -- Added Operational Flag to simple I/O interface -- Omitted T/RPDO descriptor sections in DPR -- Added generic to set duration of valid assertion (portio) -- 2010-11-29 V0.05 zelenkaj Added Big/Little Endian (pdi_spi) -- 2010-12-06 V0.06 zelenkaj Bugfix: ap_irq was not driven in SPI configuration -- 2011-01-10 V0.07 zelenkaj Added 2-stage sync to SPI input pins -- 2011-02-24 V0.08 zelenkaj minor changes (naming conventions Mii->SMI) -- 2011-03-14 V0.09 zelenkaj minor change, added generic for rx packet buffer location -- 2011-03-21 V0.10 zelenkaj clean up -- 2011-03-28 V0.20 zelenkaj Changed: Structure of Control/Status Register -- Added: LED -- Added: Events -- Added/Changed: Asynchronous buffer 2x Ping-Pong -- 2011-04-04 V0.21 zelenkaj parallel interface, sync moved to pdi_par -- minor: led_status is the official name -- 2011-04-26 V0.22 zelenkaj generic for clock domain selection -- 2011-04-28 V0.23 zelenkaj second cmp timer of openMAC is optinal by generic -- generic for second phy port of openMAC -- 2011-05-06 V0.24 zelenkaj some naming convention changes -- bug fix: use the RX_ER signal, it has important meaning! -- 2011-05-09 V0.25 zelenkaj Hardware Acceleration (HW ACC) added. -- 2011-07-23 V0.26 zelenkaj openFILTER enhanced by RxErr signal -- 2011-07-25 V0.27 zelenkaj LED gadget and asynchronous buffer optional -- 2011-08-08 V0.28 zelenkaj LED gadget enhancement -> added 8 general purpose outputs -- 2011-08-02 V1.00 zelenkaj exchanged Avalon interface with entity openMAC_Ethernet -- 2011-09-05 V1.01 zelenkaj SPI PDI missed to connect async irq to toplevel -- 2011-10-20 V1.02 zelenkaj SMI export of in, out and tristate, endian generic -- 2011-11-07 V1.03 zelenkaj dma generic for PLB/AXI support necessary -- 2011-11-21 V1.04 zelenkaj added time synchronization feature -- 2011-11-28 V1.05 zelenkaj added waitrequest signals to pdi pcp/ap -- 2011-11-29 V1.06 zelenkaj event is optional -- 2011-11-30 V1.07 zelenkaj Added generic for DMA observer -- 2011-12-02 V1.08 zelenkaj Added I, O and T instead of IO ports -- 2012-01-09 V1.09 zelenkaj Added ap_syncIrq for external AP -- 2012-01-26 V1.10 zelenkaj Added generic for SMI generation and one SMI ports -- Omit hwacc options, since we are fast enough! ------------------------------------------------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity powerlink is generic( -- GENERAL GENERICS -- endian_g : string := "little"; genOnePdiClkDomain_g : boolean := false; genPdi_g : boolean := true; genInternalAp_g : boolean := true; genSimpleIO_g : boolean := false; genSpiAp_g : boolean := false; -- OPENMAC GENERICS Simulate : boolean := false; iBufSize_g : integer := 1024; iBufSizeLOG2_g : integer := 10; useRmii_g : boolean := true; --use Rmii useIntPacketBuf_g : boolean := true; --internal packet buffer useRxIntPacketBuf_g : boolean := true; --rx buffer located in internal packet buffer use2ndCmpTimer_g : boolean := true; --use second cmp timer (used in PDI) use2ndPhy_g : boolean := true; --use second phy (introduces openHUB) m_burstcount_width_g : integer := 4; m_burstcount_const_g : boolean := true; --hold burst value during transfer m_tx_burst_size_g : integer := 16; --0 < x =< 2**m_burstcount_width_g m_rx_burst_size_g : integer := 16; --0 < x =< 2**m_burstcount_width_g m_tx_fifo_size_g : integer := 16; m_rx_fifo_size_g : integer := 16; m_data_width_g : integer := 16; gen_dma_observer_g : boolean := true; genSmiIO : boolean := true; --drive SMI IO if true gNumSmi : integer range 1 to 2 := 2; --number of SMI used -- PDI GENERICS iRpdos_g : integer := 3; iTpdos_g : integer := 1; genABuf1_g : boolean := true; --if false iABuf1_g must be set to 0! genABuf2_g : boolean := true; --if false iABuf2_g must be set to 0! genLedGadget_g : boolean := false; genTimeSync_g : boolean := false; genEvent_g : boolean := false; --PDO buffer size *3 iTpdoBufSize_g : integer := 100; iRpdo0BufSize_g : integer := 100; iRpdo1BufSize_g : integer := 100; iRpdo2BufSize_g : integer := 100; --asynchronous buffer size iAsyBuf1Size_g : integer := 100; iAsyBuf2Size_g : integer := 100; iPdiRev_g : integer := 16#55AA#; -- 8/16bit PARALLEL PDI GENERICS papDataWidth_g : integer := 8; papLowAct_g : boolean := false; papBigEnd_g : boolean := false; -- SPI GENERICS spiCPOL_g : boolean := false; spiCPHA_g : boolean := false; spiBigEnd_g : boolean := false; -- PORTIO pioValLen_g : integer := 50; --clock ticks of pcp_clk -- GENERAL TARGET DEPENDINGS genIoBuf_g : boolean := true --generates IO buffers ); port( -- CLOCK / RESET PORTS clk50 : in std_logic; --RMII clk rst : in std_logic; --general reset clkEth : in std_logic; --Tx Reg clk m_clk : in std_logic; --openMAC DMA master clock pkt_clk : in std_logic; --openMAC packet buffer clock (don't use pcp..) clkPcp : in std_logic; --pcp clk clkAp : in std_logic; --ap clk rstPcp : in std_logic; --rst from pcp side rstAp : in std_logic; --rst ap -- OPENMAC --- OPENMAC PORTS mac_chipselect : in std_logic; mac_read : in std_logic; mac_write : in std_logic; mac_byteenable : in std_logic_vector(1 downto 0); mac_address : in std_logic_vector(11 downto 0); mac_writedata : in std_logic_vector(15 downto 0); mac_readdata : out std_logic_vector(15 downto 0) := (others => '0'); mac_waitrequest : out std_logic; mac_irq : out std_logic := '0'; --- TIMER COMPARE PORTS tcp_chipselect : in std_logic; tcp_read : in std_logic; tcp_write : in std_logic; tcp_byteenable : in std_logic_vector(3 downto 0); tcp_address : in std_logic_vector(1 downto 0); tcp_writedata : in std_logic_vector(31 downto 0); tcp_readdata : out std_logic_vector(31 downto 0) := (others => '0'); tcp_waitrequest : out std_logic; tcp_irq : out std_logic := '0'; --- MAC BUFFER PORTS mbf_chipselect : in std_logic; mbf_read : in std_logic; mbf_write : in std_logic; mbf_byteenable : in std_logic_vector(3 downto 0); mbf_address : in std_logic_vector(ibufsizelog2_g-3 downto 0); mbf_writedata : in std_logic_vector(31 downto 0); mbf_readdata : out std_logic_vector(31 downto 0) := (others => '0'); mbf_waitrequest : out std_logic; --- OPENMAC DMA PORTS m_read : OUT STD_LOGIC := '0'; m_write : OUT STD_LOGIC := '0'; m_byteenable : OUT STD_LOGIC_VECTOR(m_data_width_g/8-1 DOWNTO 0) := (others => '0'); m_address : OUT STD_LOGIC_VECTOR(29 DOWNTO 0) := (others => '0'); m_writedata : OUT STD_LOGIC_VECTOR(m_data_width_g-1 DOWNTO 0) := (others => '0'); m_readdata : IN STD_LOGIC_VECTOR(m_data_width_g-1 DOWNTO 0) := (others => '0'); m_waitrequest : IN STD_LOGIC; m_readdatavalid : in STD_LOGIC := '0'; m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0); m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0); -- PDI --- PCP PORTS pcp_chipselect : in std_logic; pcp_read : in std_logic; pcp_write : in std_logic; pcp_byteenable : in std_logic_vector(3 downto 0); pcp_address : in std_logic_vector(12 downto 0); pcp_writedata : in std_logic_vector(31 downto 0); pcp_readdata : out std_logic_vector(31 downto 0) := (others => '0'); pcp_waitrequest : out std_logic; --- AP PORTS ap_irq : out std_logic := '0'; ap_irq_n : out std_logic := '1'; ap_syncIrq : out std_logic := '0'; ap_syncIrq_n : out std_logic := '1'; ap_asyncIrq : out std_logic := '0'; ap_asyncIrq_n : out std_logic := '1'; ---- AVALON ap_chipselect : in std_logic; ap_read : in std_logic; ap_write : in std_logic; ap_byteenable : in std_logic_vector(3 downto 0); ap_address : in std_logic_vector(12 downto 0); ap_writedata : in std_logic_vector(31 downto 0); ap_readdata : out std_logic_vector(31 downto 0) := (others => '0'); ap_waitrequest : out std_logic; ---- 8/16bit parallel pap_cs : in std_logic; pap_rd : in std_logic; pap_wr : in std_logic; pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0); pap_cs_n : in std_logic; pap_rd_n : in std_logic; pap_wr_n : in std_logic; pap_be_n : in std_logic_vector(papDataWidth_g/8-1 downto 0); pap_addr : in std_logic_vector(15 downto 0); pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0'); pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0'); pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0); pap_data_T : out std_logic; pap_ack : out std_logic := '0'; pap_ack_n : out std_logic := '1'; pap_gpio : inout std_logic_vector(1 downto 0) := (others => '0'); pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0'); pap_gpio_O : out std_logic_vector(1 downto 0); pap_gpio_T : out std_logic_vector(1 downto 0); ---- SPI spi_clk : in std_logic; spi_sel_n : in std_logic; spi_mosi : in std_logic; spi_miso : out std_logic := '0'; ---- simple I/O smp_address : in std_logic; smp_read : in std_logic; smp_readdata : out std_logic_vector(31 downto 0) := (others => '0'); smp_write : in std_logic; smp_writedata : in std_logic_vector(31 downto 0); smp_byteenable : in std_logic_vector(3 downto 0); smp_waitrequest : out std_logic; pio_pconfig : in std_logic_vector(3 downto 0); pio_portInLatch : in std_logic_vector(3 downto 0); pio_portOutValid : out std_logic_vector(3 downto 0) := (others => '0'); pio_portio : inout std_logic_vector(31 downto 0) := (others => '0'); pio_portio_I : in std_logic_vector(31 downto 0) := (others => '0'); pio_portio_O : out std_logic_vector(31 downto 0); pio_portio_T : out std_logic_vector(31 downto 0); pio_operational : out std_logic := '0'; -- EXTERNAL --- PHY MANAGEMENT ---- shared (valid if gNumSmi = 1) phy_SMIClk : out std_logic := '0'; phy_SMIDat : inout std_logic := '1'; phy_SMIDat_I : in std_logic := '1'; phy_SMIDat_O : out std_logic; phy_SMIDat_T : out std_logic; phy_Rst_n : out std_logic := '1'; ---- PHY0 (valid if gNumSmi = 2) phy0_SMIClk : out std_logic := '0'; phy0_SMIDat : inout std_logic := '1'; phy0_SMIDat_I : in std_logic := '1'; phy0_SMIDat_O : out std_logic; phy0_SMIDat_T : out std_logic; phy0_Rst_n : out std_logic := '1'; phy0_link : in std_logic := '0'; ---- PHY1 (valid if gNumSmi = 2) phy1_SMIClk : out std_logic := '0'; phy1_SMIDat : inout std_logic := '1'; phy1_SMIDat_I : in std_logic := '1'; phy1_SMIDat_O : out std_logic; phy1_SMIDat_T : out std_logic; phy1_Rst_n : out std_logic := '1'; phy1_link : in std_logic := '0'; --- RMII PORTS phy0_RxDat : in std_logic_vector(1 downto 0); phy0_RxDv : in std_logic; phy0_RxErr : in std_logic; phy0_TxDat : out std_logic_vector(1 downto 0) := (others => '0'); phy0_TxEn : out std_logic := '0'; phy1_RxDat : in std_logic_vector(1 downto 0) := (others => '0'); phy1_RxDv : in std_logic; phy1_RxErr : in std_logic; phy1_TxDat : out std_logic_vector(1 downto 0) := (others => '0'); phy1_TxEn : out std_logic := '0'; --- MII PORTS phyMii0_RxClk : in std_logic; phyMii0_RxDat : in std_logic_vector(3 downto 0) := (others => '0'); phyMii0_RxDv : in std_logic; phyMii0_RxEr : in std_logic; phyMii0_TxClk : in std_logic; phyMii0_TxDat : out std_logic_vector(3 downto 0) := (others => '0'); phyMii0_TxEn : out std_logic := '0'; phyMii0_TxEr : out std_logic := '0'; phyMii1_RxClk : in std_logic; phyMii1_RxDat : in std_logic_vector(3 downto 0) := (others => '0'); phyMii1_RxDv : in std_logic; phyMii1_RxEr : in std_logic; phyMii1_TxClk : in std_logic; phyMii1_TxDat : out std_logic_vector(3 downto 0) := (others => '0'); phyMii1_TxEn : out std_logic := '0'; phyMii1_TxEr : out std_logic := '0'; --- LEDs led_error : out std_logic := '0'; led_status : out std_logic := '0'; led_phyLink : out std_logic_vector(1 downto 0) := (others => '0'); led_phyAct : out std_logic_vector(1 downto 0) := (others => '0'); led_opt : out std_logic_vector(1 downto 0) := (others => '0'); led_gpo : out std_logic_vector(7 downto 0) := (others => '0') ); end powerlink; architecture rtl of powerlink is signal smi_Clk : std_logic := '0'; signal smi_Di : std_logic := '0'; signal smi_Do : std_logic := '0'; signal smi_Doe : std_logic := '0'; signal phy_nResetOut : std_logic := '0'; signal irqToggle : std_logic := '0'; signal ap_chipselect_s : std_logic := '0'; signal ap_read_s : std_logic := '0'; signal ap_write_s : std_logic := '0'; signal ap_byteenable_s : std_logic_vector(ap_byteenable'range) := (others => '0'); signal ap_address_s : std_logic_vector(ap_address'range) := (others => '0'); signal ap_writedata_s : std_logic_vector(ap_writedata'range):= (others => '0'); signal ap_readdata_s : std_logic_vector(ap_readdata'range) := (others => '0'); signal pap_cs_s : std_logic; signal pap_rd_s : std_logic; signal pap_wr_s : std_logic; signal pap_be_s : std_logic_vector(pap_be'range); signal pap_ack_s : std_logic; signal ap_irq_s : std_logic; signal ap_asyncIrq_s : std_logic; signal spi_sel_s : std_logic; signal spi_sel_s1 : std_logic; signal spi_sel_s2 : std_logic; signal spi_clk_s : std_logic; signal spi_clk_s1 : std_logic; signal spi_clk_s2 : std_logic; signal spi_mosi_s : std_logic; signal spi_mosi_s1 : std_logic; signal spi_mosi_s2 : std_logic; signal phyLink, phyAct : std_logic_vector(1 downto 0); signal led_s : std_logic_vector(15 downto 0); signal clkAp_s, rstAp_s : std_logic; --PDI change buffer triggers for hw acc to pdi signal rpdo_change_tog : std_logic_vector(2 downto 0); signal tpdo_change_tog : std_logic; begin --general signals clkAp_s <= clkAp when genOnePdiClkDomain_g = FALSE else clkPcp; rstAp_s <= rstAp when genOnePdiClkDomain_g = FALSE else rstPcp; phyLink <= phy1_link & phy0_link; --LEDs: GPO7, ..., GPO0, O1, O0, PA1, PL1, PA0, PL0, E, S led_error <= led_s(1); led_status <= led_s(0); led_phyLink <= led_s(4) & led_s(2); led_phyAct <= led_s(5) & led_s(3); led_opt <= led_s(7) & led_s(6); led_gpo <= led_s(15 downto 8); ------------------------------------------------------------------------------------------------------------------------ --PCP + AP genPdi : if genPdi_g and genInternalAp_g and not genSpiAp_g generate --sync and async interrupt are driven by only one line -- this gives some effort for Nios II AP ;) ap_irq <= ap_irq_s or ap_asyncIrq_s; theAvalonPdi : entity work.pdi generic map ( genOnePdiClkDomain_g => genOnePdiClkDomain_g, iPdiRev_g => iPdiRev_g, iRpdos_g => iRpdos_g, iTpdos_g => iTpdos_g, genABuf1_g => genABuf1_g, genABuf2_g => genABuf2_g, genLedGadget_g => genLedGadget_g, genTimeSync_g => genTimeSync_g, genEvent_g => genEvent_g, --PDO buffer size *3 iTpdoBufSize_g => iTpdoBufSize_g, iRpdo0BufSize_g => iRpdo0BufSize_g, iRpdo1BufSize_g => iRpdo1BufSize_g, iRpdo2BufSize_g => iRpdo2BufSize_g, --asynchronous buffer size iABuf1_g => iAsyBuf1Size_g, iABuf2_g => iAsyBuf2Size_g ) port map ( pcp_reset => rstPcp, pcp_clk => clkPcp, ap_reset => rstAp_s, ap_clk => clkAp_s, -- Avalon Slave Interface for PCP pcp_chipselect => pcp_chipselect, pcp_read => pcp_read, pcp_write => pcp_write, pcp_byteenable => pcp_byteenable, pcp_address => pcp_address, pcp_writedata => pcp_writedata, pcp_readdata => pcp_readdata, pcp_waitrequest => pcp_waitrequest, pcp_irq => irqToggle, -- Avalon Slave Interface for AP ap_chipselect => ap_chipselect, ap_read => ap_read, ap_write => ap_write, ap_byteenable => ap_byteenable, ap_address => ap_address, ap_writedata => ap_writedata, ap_readdata => ap_readdata, ap_waitrequest => ap_waitrequest, ap_irq => ap_irq_s, -- async interrupt ap_asyncIrq => ap_asyncIrq_s, -- LED ledsOut => led_s, phyLink => phyLink, phyAct => phyAct, --PDI change buffer triggers rpdo_change_tog => rpdo_change_tog, tpdo_change_tog => tpdo_change_tog ); end generate genPdi; --AP is external connected via parallel interface genPdiPar : if genPdi_g and not genInternalAp_g and not genSpiAp_g generate --only 8 or 16bit data width is allowed ASSERT ( papDataWidth_g = 8 or papDataWidth_g = 16 ) REPORT "External parallel port only allows 8 or 16bit data width!" severity failure; ------------------------------------------------------------------------------------- --convert active low signals to active high - respectively assign active high signals theActiveLowGen : if papLowAct_g generate pap_wr_s <= not pap_wr_n; pap_rd_s <= not pap_rd_n; pap_cs_s <= not pap_cs_n; pap_be_s <= not pap_be_n; end generate; theActiveHighGen : if not papLowAct_g generate pap_wr_s <= pap_wr; pap_rd_s <= pap_rd; pap_cs_s <= pap_cs; pap_be_s <= pap_be; end generate; ap_syncIrq <= ap_irq_s; ap_syncIrq_n <= not ap_irq_s; ap_asyncIrq <= ap_asyncIrq_s; ap_asyncIrq_n <= not ap_asyncIrq_s; pap_ack <= pap_ack_s; pap_ack_n <= not pap_ack_s; -- ------------------------------------------------------------------------------------- theParPort : entity work.pdi_par generic map ( papDataWidth_g => papDataWidth_g, papBigEnd_g => papBigEnd_g, papGenIoBuf_g => genIoBuf_g ) port map ( -- 8/16bit parallel pap_cs => pap_cs_s, pap_rd => pap_rd_s, pap_wr => pap_wr_s, pap_be => pap_be_s, pap_addr => pap_addr, pap_data => pap_data, pap_data_I => pap_data_I, pap_data_O => pap_data_O, pap_data_T => pap_data_T, pap_ack => pap_ack_s, pap_gpio => pap_gpio, pap_gpio_I => pap_gpio_I, pap_gpio_O => pap_gpio_O, pap_gpio_T => pap_gpio_T, -- clock for AP side ap_reset => rstPcp, ap_clk => clk50, -- Avalon Slave Interface for AP ap_chipselect => ap_chipselect_s, ap_read => ap_read_s, ap_write => ap_write_s, ap_byteenable => ap_byteenable_s, ap_address => ap_address_s, ap_writedata => ap_writedata_s, ap_readdata => ap_readdata_s ); thePdi : entity work.pdi generic map ( genOnePdiClkDomain_g => genOnePdiClkDomain_g, iPdiRev_g => iPdiRev_g, iRpdos_g => iRpdos_g, iTpdos_g => iTpdos_g, genABuf1_g => genABuf1_g, genABuf2_g => genABuf2_g, genLedGadget_g => genLedGadget_g, genTimeSync_g => genTimeSync_g, genEvent_g => genEvent_g, --PDO buffer size *3 iTpdoBufSize_g => iTpdoBufSize_g, iRpdo0BufSize_g => iRpdo0BufSize_g, iRpdo1BufSize_g => iRpdo1BufSize_g, iRpdo2BufSize_g => iRpdo2BufSize_g, --asynchronous buffer size iABuf1_g => iAsyBuf1Size_g, iABuf2_g => iAsyBuf2Size_g ) port map ( pcp_reset => rstPcp, pcp_clk => clkPcp, ap_reset => rst, ap_clk => clk50, -- Avalon Slave Interface for PCP pcp_chipselect => pcp_chipselect, pcp_read => pcp_read, pcp_write => pcp_write, pcp_byteenable => pcp_byteenable, pcp_address => pcp_address, pcp_writedata => pcp_writedata, pcp_readdata => pcp_readdata, pcp_waitrequest => pcp_waitrequest, pcp_irq => irqToggle, -- Avalon Slave Interface for AP ap_chipselect => ap_chipselect_s, ap_read => ap_read_s, ap_write => ap_write_s, ap_byteenable => ap_byteenable_s, ap_address => ap_address_s, ap_writedata => ap_writedata_s, ap_readdata => ap_readdata_s, ap_waitrequest => open, ap_irq => ap_irq_s, -- async interrupt ap_asyncIrq => ap_asyncIrq_s, -- LED ledsOut => led_s, phyLink => phyLink, phyAct => phyAct, --PDI change buffer triggers rpdo_change_tog => rpdo_change_tog, tpdo_change_tog => tpdo_change_tog ); end generate genPdiPar; --AP is extern connected via SPI genPdiSpi : if genPdi_g and genSpiAp_g generate ap_syncIrq <= ap_irq_s; ap_syncIrq_n <= not ap_irq_s; ap_asyncIrq <= ap_asyncIrq_s; ap_asyncIrq_n <= not ap_asyncIrq_s; spi_clk_s <= spi_clk; spi_sel_s <= not spi_sel_n; spi_mosi_s <= spi_mosi; theSyncProc : process(clk50, rst) begin if rst = '1' then spi_sel_s1 <= '0'; spi_sel_s2 <= '0'; spi_clk_s1 <= '0'; spi_clk_s2 <= '0'; spi_mosi_s1 <= '0'; spi_mosi_s2 <= '0'; elsif clk50 = '1' and clk50'event then spi_sel_s1 <= spi_sel_s; spi_sel_s2 <= spi_sel_s1; spi_clk_s1 <= spi_clk_s; spi_clk_s2 <= spi_clk_s1; spi_mosi_s1 <= spi_mosi_s; spi_mosi_s2 <= spi_mosi_s1; end if; end process; ------------------------------------------------------------------------------------------------------------------------ thePdiSpi : entity work.pdi_spi generic map ( spiSize_g => 8, --fixed value! cpol_g => spiCPOL_g, cpha_g => spiCPHA_g, spiBigEnd_g => spiBigEnd_g ) port map ( -- SPI spi_clk => spi_clk_s2, spi_sel => spi_sel_s2, spi_miso => spi_miso, spi_mosi => spi_mosi_s2, -- clock for AP side ap_reset => rstPcp, ap_clk => clk50, -- Avalon Slave Interface for AP ap_chipselect => ap_chipselect_s, ap_read => ap_read_s, ap_write => ap_write_s, ap_byteenable => ap_byteenable_s, ap_address => ap_address_s, ap_writedata => ap_writedata_s, ap_readdata => ap_readdata_s ); thePdi : entity work.pdi generic map ( genOnePdiClkDomain_g => genOnePdiClkDomain_g, iPdiRev_g => iPdiRev_g, iRpdos_g => iRpdos_g, iTpdos_g => iTpdos_g, genABuf1_g => genABuf1_g, genABuf2_g => genABuf2_g, genLedGadget_g => genLedGadget_g, genTimeSync_g => genTimeSync_g, genEvent_g => genEvent_g, --PDO buffer size *3 iTpdoBufSize_g => iTpdoBufSize_g, iRpdo0BufSize_g => iRpdo0BufSize_g, iRpdo1BufSize_g => iRpdo1BufSize_g, iRpdo2BufSize_g => iRpdo2BufSize_g, --asynchronous buffer size iABuf1_g => iAsyBuf1Size_g, iABuf2_g => iAsyBuf2Size_g ) port map ( pcp_reset => rstPcp, pcp_clk => clkPcp, ap_reset => rst, ap_clk => clk50, -- Avalon Slave Interface for PCP pcp_chipselect => pcp_chipselect, pcp_read => pcp_read, pcp_write => pcp_write, pcp_byteenable => pcp_byteenable, pcp_address => pcp_address, pcp_writedata => pcp_writedata, pcp_readdata => pcp_readdata, pcp_waitrequest => pcp_waitrequest, pcp_irq => irqToggle, -- Avalon Slave Interface for AP ap_chipselect => ap_chipselect_s, ap_read => ap_read_s, ap_write => ap_write_s, ap_byteenable => ap_byteenable_s, ap_address => ap_address_s, ap_writedata => ap_writedata_s, ap_readdata => ap_readdata_s, ap_waitrequest => open, ap_irq => ap_irq_s, -- async interrupt ap_asyncIrq => ap_asyncIrq_s, -- LED ledsOut => led_s, phyLink => phyLink, phyAct => phyAct, --PDI change buffer triggers rpdo_change_tog => rpdo_change_tog, tpdo_change_tog => tpdo_change_tog ); end generate genPdiSpi; -- ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ --SIMPLE I/O CN genSimpleIO : if genSimpleIO_g generate thePortIO : entity work.portio generic map ( pioValLen_g => pioValLen_g, pioGenIoBuf_g => genIoBuf_g ) port map ( s0_address => smp_address, s0_read => smp_read, s0_readdata => smp_readdata, s0_write => smp_write, s0_writedata => smp_writedata, s0_byteenable => smp_byteenable, s0_waitrequest => smp_waitrequest, clk => clkPcp, reset => rstPcp, x_pconfig => pio_pconfig, x_portInLatch => pio_portInLatch, x_portOutValid => pio_portOutValid, x_portio => pio_portio, x_portio_I => pio_portio_I, x_portio_O => pio_portio_O, x_portio_T => pio_portio_T, x_operational => pio_operational ); end generate genSimpleIO; -- ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ --OPENMAC (OPENHUB, OPENFILTER, PHY MANAGEMENT) theOpenMac : entity work.openMAC_Ethernet generic map ( endian_g => endian_g, dma_highadr_g => m_address'high, gen2ndCmpTimer_g => use2ndCmpTimer_g, genHub_g => use2ndPhy_g, iPktBufSizeLog2_g => iBufSizeLOG2_g, iPktBufSize_g => iBufSize_g, simulate => false, useIntPktBuf_g => useIntPacketBuf_g, useRmii_g => useRmii_g, useRxIntPktBuf_g => useRxIntPacketBuf_g, m_burstcount_width_g => m_burstcount_width_g, m_burstcount_const_g => m_burstcount_const_g, m_data_width_g => m_data_width_g, m_tx_fifo_size_g => m_tx_fifo_size_g, m_rx_fifo_size_g => m_rx_fifo_size_g, m_tx_burst_size_g => m_tx_burst_size_g, m_rx_burst_size_g => m_rx_burst_size_g, genSmiIO => genSmiIO, gNumSmi => gNumSmi, genPhyActLed_g => genLedGadget_g, gen_dma_observer_g => gen_dma_observer_g ) port map( clk => clk50, clkx2 => clkEth, pkt_clk => pkt_clk, m_clk => m_clk, rst => rst, m_address => m_address, m_burstcount => m_burstcount, m_burstcounter => m_burstcounter, m_byteenable => m_byteenable, m_read => m_read, m_readdata => m_readdata, m_readdatavalid => m_readdatavalid, m_write => m_write, m_writedata => m_writedata, m_waitrequest => m_waitrequest, mac_rx_irq => open, mac_tx_irq => open, act_led => phyAct(0), phy0_rst_n => phy0_Rst_n, phy0_rx_dat => phy0_RxDat, phy0_rx_dv => phy0_RxDv, phy0_rx_err => phy0_RxErr, phy0_smi_clk => phy0_SMICLK, phy0_smi_dio => phy0_SMIDat, phy0_smi_dio_I => phy0_SMIDat_I, phy0_smi_dio_O => phy0_SMIDat_O, phy0_smi_dio_T => phy0_SMIDat_T, phy0_tx_dat => phy0_TxDat, phy0_tx_en => phy0_TxEn, phy1_rst_n => phy1_Rst_n, phy1_rx_dat => phy1_RxDat, phy1_rx_dv => phy1_RxDv, phy1_rx_err => phy1_RxErr, phy1_smi_clk => phy1_SMICLK, phy1_smi_dio => phy1_SMIDat, phy1_smi_dio_I => phy1_SMIDat_I, phy1_smi_dio_O => phy1_SMIDat_O, phy1_smi_dio_T => phy1_SMIDat_T, phy1_tx_dat => phy1_TxDat, phy1_tx_en => phy1_TxEn, phyMii0_rx_clk => phyMii0_RxClk, phyMii0_rx_dat => phyMii0_RxDat, phyMii0_rx_dv => phyMii0_RxDv, phyMii0_rx_err => phyMii0_RxEr, phyMii0_tx_clk => phyMii0_TxClk, phyMii0_tx_dat => phyMii0_TxDat, phyMii0_tx_en => phyMii0_TxEn, phyMii1_rx_clk => phyMii1_RxClk, phyMii1_rx_dat => phyMii1_RxDat, phyMii1_rx_dv => phyMii1_RxDv, phyMii1_rx_err => phyMii1_RxEr, phyMii1_tx_clk => phyMii1_TxClk, phyMii1_tx_dat => phyMii1_TxDat, phyMii1_tx_en => phyMii1_TxEn, phy_rst_n => phy_Rst_n, phy_smi_clk => phy_SMIClk, phy_smi_dio_I => phy_SMIDat_I, phy_smi_dio_O => phy_SMIDat_O, phy_smi_dio_T => phy_SMIDat_T, phy_smi_dio => phy_SMIDat, pkt_address => mbf_address, pkt_byteenable => mbf_byteenable, pkt_chipselect => mbf_chipselect, pkt_read => mbf_read, pkt_readdata => mbf_readdata, pkt_waitrequest => mbf_waitrequest, pkt_write => mbf_write, pkt_writedata => mbf_writedata, s_address => mac_address, s_byteenable => mac_byteenable, s_chipselect => mac_chipselect, s_irq => mac_irq, s_read => mac_read, s_readdata => mac_readdata, s_waitrequest => mac_waitrequest, s_write => mac_write, s_writedata => mac_writedata, t_address => tcp_address, t_byteenable => tcp_byteenable, t_chipselect => tcp_chipselect, t_irq => tcp_irq, t_read => tcp_read, t_readdata => tcp_readdata, t_tog => irqToggle, t_waitrequest => tcp_waitrequest, t_write => tcp_write, t_writedata => tcp_writedata ); phyAct(1) <= phyAct(0); -- ------------------------------------------------------------------------------------------------------------------------ end rtl;
------------------------------------------------------------------------------------------------------------------------ -- POWERLINK IP-Core -- -- Copyright (C) 2010 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------------------------------------------------ -- Version History ------------------------------------------------------------------------------------------------------------------------ -- 2010-08-23 V0.01 zelenkaj First version -- 2010-09-13 V0.02 zelenkaj added selection Rmii / Mii -- 2010-10-18 V0.03 zelenkaj added selection Big/Little Endian (pdi_par) -- use bidirectional bus (pdi_par) -- 2010-11-23 V0.04 zelenkaj Added 2 GPIO signals to parallel interface -- Added Operational Flag to simple I/O interface -- Omitted T/RPDO descriptor sections in DPR -- Added generic to set duration of valid assertion (portio) -- 2010-11-29 V0.05 zelenkaj Added Big/Little Endian (pdi_spi) -- 2010-12-06 V0.06 zelenkaj Bugfix: ap_irq was not driven in SPI configuration -- 2011-01-10 V0.07 zelenkaj Added 2-stage sync to SPI input pins -- 2011-02-24 V0.08 zelenkaj minor changes (naming conventions Mii->SMI) -- 2011-03-14 V0.09 zelenkaj minor change, added generic for rx packet buffer location -- 2011-03-21 V0.10 zelenkaj clean up -- 2011-03-28 V0.20 zelenkaj Changed: Structure of Control/Status Register -- Added: LED -- Added: Events -- Added/Changed: Asynchronous buffer 2x Ping-Pong -- 2011-04-04 V0.21 zelenkaj parallel interface, sync moved to pdi_par -- minor: led_status is the official name -- 2011-04-26 V0.22 zelenkaj generic for clock domain selection -- 2011-04-28 V0.23 zelenkaj second cmp timer of openMAC is optinal by generic -- generic for second phy port of openMAC -- 2011-05-06 V0.24 zelenkaj some naming convention changes -- bug fix: use the RX_ER signal, it has important meaning! -- 2011-05-09 V0.25 zelenkaj Hardware Acceleration (HW ACC) added. -- 2011-07-23 V0.26 zelenkaj openFILTER enhanced by RxErr signal -- 2011-07-25 V0.27 zelenkaj LED gadget and asynchronous buffer optional -- 2011-08-08 V0.28 zelenkaj LED gadget enhancement -> added 8 general purpose outputs -- 2011-08-02 V1.00 zelenkaj exchanged Avalon interface with entity openMAC_Ethernet -- 2011-09-05 V1.01 zelenkaj SPI PDI missed to connect async irq to toplevel -- 2011-10-20 V1.02 zelenkaj SMI export of in, out and tristate, endian generic -- 2011-11-07 V1.03 zelenkaj dma generic for PLB/AXI support necessary -- 2011-11-21 V1.04 zelenkaj added time synchronization feature -- 2011-11-28 V1.05 zelenkaj added waitrequest signals to pdi pcp/ap -- 2011-11-29 V1.06 zelenkaj event is optional -- 2011-11-30 V1.07 zelenkaj Added generic for DMA observer -- 2011-12-02 V1.08 zelenkaj Added I, O and T instead of IO ports -- 2012-01-09 V1.09 zelenkaj Added ap_syncIrq for external AP -- 2012-01-26 V1.10 zelenkaj Added generic for SMI generation and one SMI ports -- Omit hwacc options, since we are fast enough! ------------------------------------------------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity powerlink is generic( -- GENERAL GENERICS -- endian_g : string := "little"; genOnePdiClkDomain_g : boolean := false; genPdi_g : boolean := true; genInternalAp_g : boolean := true; genSimpleIO_g : boolean := false; genSpiAp_g : boolean := false; -- OPENMAC GENERICS Simulate : boolean := false; iBufSize_g : integer := 1024; iBufSizeLOG2_g : integer := 10; useRmii_g : boolean := true; --use Rmii useIntPacketBuf_g : boolean := true; --internal packet buffer useRxIntPacketBuf_g : boolean := true; --rx buffer located in internal packet buffer use2ndCmpTimer_g : boolean := true; --use second cmp timer (used in PDI) use2ndPhy_g : boolean := true; --use second phy (introduces openHUB) m_burstcount_width_g : integer := 4; m_burstcount_const_g : boolean := true; --hold burst value during transfer m_tx_burst_size_g : integer := 16; --0 < x =< 2**m_burstcount_width_g m_rx_burst_size_g : integer := 16; --0 < x =< 2**m_burstcount_width_g m_tx_fifo_size_g : integer := 16; m_rx_fifo_size_g : integer := 16; m_data_width_g : integer := 16; gen_dma_observer_g : boolean := true; genSmiIO : boolean := true; --drive SMI IO if true gNumSmi : integer range 1 to 2 := 2; --number of SMI used -- PDI GENERICS iRpdos_g : integer := 3; iTpdos_g : integer := 1; genABuf1_g : boolean := true; --if false iABuf1_g must be set to 0! genABuf2_g : boolean := true; --if false iABuf2_g must be set to 0! genLedGadget_g : boolean := false; genTimeSync_g : boolean := false; genEvent_g : boolean := false; --PDO buffer size *3 iTpdoBufSize_g : integer := 100; iRpdo0BufSize_g : integer := 100; iRpdo1BufSize_g : integer := 100; iRpdo2BufSize_g : integer := 100; --asynchronous buffer size iAsyBuf1Size_g : integer := 100; iAsyBuf2Size_g : integer := 100; iPdiRev_g : integer := 16#55AA#; -- 8/16bit PARALLEL PDI GENERICS papDataWidth_g : integer := 8; papLowAct_g : boolean := false; papBigEnd_g : boolean := false; -- SPI GENERICS spiCPOL_g : boolean := false; spiCPHA_g : boolean := false; spiBigEnd_g : boolean := false; -- PORTIO pioValLen_g : integer := 50; --clock ticks of pcp_clk -- GENERAL TARGET DEPENDINGS genIoBuf_g : boolean := true --generates IO buffers ); port( -- CLOCK / RESET PORTS clk50 : in std_logic; --RMII clk rst : in std_logic; --general reset clkEth : in std_logic; --Tx Reg clk m_clk : in std_logic; --openMAC DMA master clock pkt_clk : in std_logic; --openMAC packet buffer clock (don't use pcp..) clkPcp : in std_logic; --pcp clk clkAp : in std_logic; --ap clk rstPcp : in std_logic; --rst from pcp side rstAp : in std_logic; --rst ap -- OPENMAC --- OPENMAC PORTS mac_chipselect : in std_logic; mac_read : in std_logic; mac_write : in std_logic; mac_byteenable : in std_logic_vector(1 downto 0); mac_address : in std_logic_vector(11 downto 0); mac_writedata : in std_logic_vector(15 downto 0); mac_readdata : out std_logic_vector(15 downto 0) := (others => '0'); mac_waitrequest : out std_logic; mac_irq : out std_logic := '0'; --- TIMER COMPARE PORTS tcp_chipselect : in std_logic; tcp_read : in std_logic; tcp_write : in std_logic; tcp_byteenable : in std_logic_vector(3 downto 0); tcp_address : in std_logic_vector(1 downto 0); tcp_writedata : in std_logic_vector(31 downto 0); tcp_readdata : out std_logic_vector(31 downto 0) := (others => '0'); tcp_waitrequest : out std_logic; tcp_irq : out std_logic := '0'; --- MAC BUFFER PORTS mbf_chipselect : in std_logic; mbf_read : in std_logic; mbf_write : in std_logic; mbf_byteenable : in std_logic_vector(3 downto 0); mbf_address : in std_logic_vector(ibufsizelog2_g-3 downto 0); mbf_writedata : in std_logic_vector(31 downto 0); mbf_readdata : out std_logic_vector(31 downto 0) := (others => '0'); mbf_waitrequest : out std_logic; --- OPENMAC DMA PORTS m_read : OUT STD_LOGIC := '0'; m_write : OUT STD_LOGIC := '0'; m_byteenable : OUT STD_LOGIC_VECTOR(m_data_width_g/8-1 DOWNTO 0) := (others => '0'); m_address : OUT STD_LOGIC_VECTOR(29 DOWNTO 0) := (others => '0'); m_writedata : OUT STD_LOGIC_VECTOR(m_data_width_g-1 DOWNTO 0) := (others => '0'); m_readdata : IN STD_LOGIC_VECTOR(m_data_width_g-1 DOWNTO 0) := (others => '0'); m_waitrequest : IN STD_LOGIC; m_readdatavalid : in STD_LOGIC := '0'; m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0); m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0); -- PDI --- PCP PORTS pcp_chipselect : in std_logic; pcp_read : in std_logic; pcp_write : in std_logic; pcp_byteenable : in std_logic_vector(3 downto 0); pcp_address : in std_logic_vector(12 downto 0); pcp_writedata : in std_logic_vector(31 downto 0); pcp_readdata : out std_logic_vector(31 downto 0) := (others => '0'); pcp_waitrequest : out std_logic; --- AP PORTS ap_irq : out std_logic := '0'; ap_irq_n : out std_logic := '1'; ap_syncIrq : out std_logic := '0'; ap_syncIrq_n : out std_logic := '1'; ap_asyncIrq : out std_logic := '0'; ap_asyncIrq_n : out std_logic := '1'; ---- AVALON ap_chipselect : in std_logic; ap_read : in std_logic; ap_write : in std_logic; ap_byteenable : in std_logic_vector(3 downto 0); ap_address : in std_logic_vector(12 downto 0); ap_writedata : in std_logic_vector(31 downto 0); ap_readdata : out std_logic_vector(31 downto 0) := (others => '0'); ap_waitrequest : out std_logic; ---- 8/16bit parallel pap_cs : in std_logic; pap_rd : in std_logic; pap_wr : in std_logic; pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0); pap_cs_n : in std_logic; pap_rd_n : in std_logic; pap_wr_n : in std_logic; pap_be_n : in std_logic_vector(papDataWidth_g/8-1 downto 0); pap_addr : in std_logic_vector(15 downto 0); pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0'); pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0'); pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0); pap_data_T : out std_logic; pap_ack : out std_logic := '0'; pap_ack_n : out std_logic := '1'; pap_gpio : inout std_logic_vector(1 downto 0) := (others => '0'); pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0'); pap_gpio_O : out std_logic_vector(1 downto 0); pap_gpio_T : out std_logic_vector(1 downto 0); ---- SPI spi_clk : in std_logic; spi_sel_n : in std_logic; spi_mosi : in std_logic; spi_miso : out std_logic := '0'; ---- simple I/O smp_address : in std_logic; smp_read : in std_logic; smp_readdata : out std_logic_vector(31 downto 0) := (others => '0'); smp_write : in std_logic; smp_writedata : in std_logic_vector(31 downto 0); smp_byteenable : in std_logic_vector(3 downto 0); smp_waitrequest : out std_logic; pio_pconfig : in std_logic_vector(3 downto 0); pio_portInLatch : in std_logic_vector(3 downto 0); pio_portOutValid : out std_logic_vector(3 downto 0) := (others => '0'); pio_portio : inout std_logic_vector(31 downto 0) := (others => '0'); pio_portio_I : in std_logic_vector(31 downto 0) := (others => '0'); pio_portio_O : out std_logic_vector(31 downto 0); pio_portio_T : out std_logic_vector(31 downto 0); pio_operational : out std_logic := '0'; -- EXTERNAL --- PHY MANAGEMENT ---- shared (valid if gNumSmi = 1) phy_SMIClk : out std_logic := '0'; phy_SMIDat : inout std_logic := '1'; phy_SMIDat_I : in std_logic := '1'; phy_SMIDat_O : out std_logic; phy_SMIDat_T : out std_logic; phy_Rst_n : out std_logic := '1'; ---- PHY0 (valid if gNumSmi = 2) phy0_SMIClk : out std_logic := '0'; phy0_SMIDat : inout std_logic := '1'; phy0_SMIDat_I : in std_logic := '1'; phy0_SMIDat_O : out std_logic; phy0_SMIDat_T : out std_logic; phy0_Rst_n : out std_logic := '1'; phy0_link : in std_logic := '0'; ---- PHY1 (valid if gNumSmi = 2) phy1_SMIClk : out std_logic := '0'; phy1_SMIDat : inout std_logic := '1'; phy1_SMIDat_I : in std_logic := '1'; phy1_SMIDat_O : out std_logic; phy1_SMIDat_T : out std_logic; phy1_Rst_n : out std_logic := '1'; phy1_link : in std_logic := '0'; --- RMII PORTS phy0_RxDat : in std_logic_vector(1 downto 0); phy0_RxDv : in std_logic; phy0_RxErr : in std_logic; phy0_TxDat : out std_logic_vector(1 downto 0) := (others => '0'); phy0_TxEn : out std_logic := '0'; phy1_RxDat : in std_logic_vector(1 downto 0) := (others => '0'); phy1_RxDv : in std_logic; phy1_RxErr : in std_logic; phy1_TxDat : out std_logic_vector(1 downto 0) := (others => '0'); phy1_TxEn : out std_logic := '0'; --- MII PORTS phyMii0_RxClk : in std_logic; phyMii0_RxDat : in std_logic_vector(3 downto 0) := (others => '0'); phyMii0_RxDv : in std_logic; phyMii0_RxEr : in std_logic; phyMii0_TxClk : in std_logic; phyMii0_TxDat : out std_logic_vector(3 downto 0) := (others => '0'); phyMii0_TxEn : out std_logic := '0'; phyMii0_TxEr : out std_logic := '0'; phyMii1_RxClk : in std_logic; phyMii1_RxDat : in std_logic_vector(3 downto 0) := (others => '0'); phyMii1_RxDv : in std_logic; phyMii1_RxEr : in std_logic; phyMii1_TxClk : in std_logic; phyMii1_TxDat : out std_logic_vector(3 downto 0) := (others => '0'); phyMii1_TxEn : out std_logic := '0'; phyMii1_TxEr : out std_logic := '0'; --- LEDs led_error : out std_logic := '0'; led_status : out std_logic := '0'; led_phyLink : out std_logic_vector(1 downto 0) := (others => '0'); led_phyAct : out std_logic_vector(1 downto 0) := (others => '0'); led_opt : out std_logic_vector(1 downto 0) := (others => '0'); led_gpo : out std_logic_vector(7 downto 0) := (others => '0') ); end powerlink; architecture rtl of powerlink is signal smi_Clk : std_logic := '0'; signal smi_Di : std_logic := '0'; signal smi_Do : std_logic := '0'; signal smi_Doe : std_logic := '0'; signal phy_nResetOut : std_logic := '0'; signal irqToggle : std_logic := '0'; signal ap_chipselect_s : std_logic := '0'; signal ap_read_s : std_logic := '0'; signal ap_write_s : std_logic := '0'; signal ap_byteenable_s : std_logic_vector(ap_byteenable'range) := (others => '0'); signal ap_address_s : std_logic_vector(ap_address'range) := (others => '0'); signal ap_writedata_s : std_logic_vector(ap_writedata'range):= (others => '0'); signal ap_readdata_s : std_logic_vector(ap_readdata'range) := (others => '0'); signal pap_cs_s : std_logic; signal pap_rd_s : std_logic; signal pap_wr_s : std_logic; signal pap_be_s : std_logic_vector(pap_be'range); signal pap_ack_s : std_logic; signal ap_irq_s : std_logic; signal ap_asyncIrq_s : std_logic; signal spi_sel_s : std_logic; signal spi_sel_s1 : std_logic; signal spi_sel_s2 : std_logic; signal spi_clk_s : std_logic; signal spi_clk_s1 : std_logic; signal spi_clk_s2 : std_logic; signal spi_mosi_s : std_logic; signal spi_mosi_s1 : std_logic; signal spi_mosi_s2 : std_logic; signal phyLink, phyAct : std_logic_vector(1 downto 0); signal led_s : std_logic_vector(15 downto 0); signal clkAp_s, rstAp_s : std_logic; --PDI change buffer triggers for hw acc to pdi signal rpdo_change_tog : std_logic_vector(2 downto 0); signal tpdo_change_tog : std_logic; begin --general signals clkAp_s <= clkAp when genOnePdiClkDomain_g = FALSE else clkPcp; rstAp_s <= rstAp when genOnePdiClkDomain_g = FALSE else rstPcp; phyLink <= phy1_link & phy0_link; --LEDs: GPO7, ..., GPO0, O1, O0, PA1, PL1, PA0, PL0, E, S led_error <= led_s(1); led_status <= led_s(0); led_phyLink <= led_s(4) & led_s(2); led_phyAct <= led_s(5) & led_s(3); led_opt <= led_s(7) & led_s(6); led_gpo <= led_s(15 downto 8); ------------------------------------------------------------------------------------------------------------------------ --PCP + AP genPdi : if genPdi_g and genInternalAp_g and not genSpiAp_g generate --sync and async interrupt are driven by only one line -- this gives some effort for Nios II AP ;) ap_irq <= ap_irq_s or ap_asyncIrq_s; theAvalonPdi : entity work.pdi generic map ( genOnePdiClkDomain_g => genOnePdiClkDomain_g, iPdiRev_g => iPdiRev_g, iRpdos_g => iRpdos_g, iTpdos_g => iTpdos_g, genABuf1_g => genABuf1_g, genABuf2_g => genABuf2_g, genLedGadget_g => genLedGadget_g, genTimeSync_g => genTimeSync_g, genEvent_g => genEvent_g, --PDO buffer size *3 iTpdoBufSize_g => iTpdoBufSize_g, iRpdo0BufSize_g => iRpdo0BufSize_g, iRpdo1BufSize_g => iRpdo1BufSize_g, iRpdo2BufSize_g => iRpdo2BufSize_g, --asynchronous buffer size iABuf1_g => iAsyBuf1Size_g, iABuf2_g => iAsyBuf2Size_g ) port map ( pcp_reset => rstPcp, pcp_clk => clkPcp, ap_reset => rstAp_s, ap_clk => clkAp_s, -- Avalon Slave Interface for PCP pcp_chipselect => pcp_chipselect, pcp_read => pcp_read, pcp_write => pcp_write, pcp_byteenable => pcp_byteenable, pcp_address => pcp_address, pcp_writedata => pcp_writedata, pcp_readdata => pcp_readdata, pcp_waitrequest => pcp_waitrequest, pcp_irq => irqToggle, -- Avalon Slave Interface for AP ap_chipselect => ap_chipselect, ap_read => ap_read, ap_write => ap_write, ap_byteenable => ap_byteenable, ap_address => ap_address, ap_writedata => ap_writedata, ap_readdata => ap_readdata, ap_waitrequest => ap_waitrequest, ap_irq => ap_irq_s, -- async interrupt ap_asyncIrq => ap_asyncIrq_s, -- LED ledsOut => led_s, phyLink => phyLink, phyAct => phyAct, --PDI change buffer triggers rpdo_change_tog => rpdo_change_tog, tpdo_change_tog => tpdo_change_tog ); end generate genPdi; --AP is external connected via parallel interface genPdiPar : if genPdi_g and not genInternalAp_g and not genSpiAp_g generate --only 8 or 16bit data width is allowed ASSERT ( papDataWidth_g = 8 or papDataWidth_g = 16 ) REPORT "External parallel port only allows 8 or 16bit data width!" severity failure; ------------------------------------------------------------------------------------- --convert active low signals to active high - respectively assign active high signals theActiveLowGen : if papLowAct_g generate pap_wr_s <= not pap_wr_n; pap_rd_s <= not pap_rd_n; pap_cs_s <= not pap_cs_n; pap_be_s <= not pap_be_n; end generate; theActiveHighGen : if not papLowAct_g generate pap_wr_s <= pap_wr; pap_rd_s <= pap_rd; pap_cs_s <= pap_cs; pap_be_s <= pap_be; end generate; ap_syncIrq <= ap_irq_s; ap_syncIrq_n <= not ap_irq_s; ap_asyncIrq <= ap_asyncIrq_s; ap_asyncIrq_n <= not ap_asyncIrq_s; pap_ack <= pap_ack_s; pap_ack_n <= not pap_ack_s; -- ------------------------------------------------------------------------------------- theParPort : entity work.pdi_par generic map ( papDataWidth_g => papDataWidth_g, papBigEnd_g => papBigEnd_g, papGenIoBuf_g => genIoBuf_g ) port map ( -- 8/16bit parallel pap_cs => pap_cs_s, pap_rd => pap_rd_s, pap_wr => pap_wr_s, pap_be => pap_be_s, pap_addr => pap_addr, pap_data => pap_data, pap_data_I => pap_data_I, pap_data_O => pap_data_O, pap_data_T => pap_data_T, pap_ack => pap_ack_s, pap_gpio => pap_gpio, pap_gpio_I => pap_gpio_I, pap_gpio_O => pap_gpio_O, pap_gpio_T => pap_gpio_T, -- clock for AP side ap_reset => rstPcp, ap_clk => clk50, -- Avalon Slave Interface for AP ap_chipselect => ap_chipselect_s, ap_read => ap_read_s, ap_write => ap_write_s, ap_byteenable => ap_byteenable_s, ap_address => ap_address_s, ap_writedata => ap_writedata_s, ap_readdata => ap_readdata_s ); thePdi : entity work.pdi generic map ( genOnePdiClkDomain_g => genOnePdiClkDomain_g, iPdiRev_g => iPdiRev_g, iRpdos_g => iRpdos_g, iTpdos_g => iTpdos_g, genABuf1_g => genABuf1_g, genABuf2_g => genABuf2_g, genLedGadget_g => genLedGadget_g, genTimeSync_g => genTimeSync_g, genEvent_g => genEvent_g, --PDO buffer size *3 iTpdoBufSize_g => iTpdoBufSize_g, iRpdo0BufSize_g => iRpdo0BufSize_g, iRpdo1BufSize_g => iRpdo1BufSize_g, iRpdo2BufSize_g => iRpdo2BufSize_g, --asynchronous buffer size iABuf1_g => iAsyBuf1Size_g, iABuf2_g => iAsyBuf2Size_g ) port map ( pcp_reset => rstPcp, pcp_clk => clkPcp, ap_reset => rst, ap_clk => clk50, -- Avalon Slave Interface for PCP pcp_chipselect => pcp_chipselect, pcp_read => pcp_read, pcp_write => pcp_write, pcp_byteenable => pcp_byteenable, pcp_address => pcp_address, pcp_writedata => pcp_writedata, pcp_readdata => pcp_readdata, pcp_waitrequest => pcp_waitrequest, pcp_irq => irqToggle, -- Avalon Slave Interface for AP ap_chipselect => ap_chipselect_s, ap_read => ap_read_s, ap_write => ap_write_s, ap_byteenable => ap_byteenable_s, ap_address => ap_address_s, ap_writedata => ap_writedata_s, ap_readdata => ap_readdata_s, ap_waitrequest => open, ap_irq => ap_irq_s, -- async interrupt ap_asyncIrq => ap_asyncIrq_s, -- LED ledsOut => led_s, phyLink => phyLink, phyAct => phyAct, --PDI change buffer triggers rpdo_change_tog => rpdo_change_tog, tpdo_change_tog => tpdo_change_tog ); end generate genPdiPar; --AP is extern connected via SPI genPdiSpi : if genPdi_g and genSpiAp_g generate ap_syncIrq <= ap_irq_s; ap_syncIrq_n <= not ap_irq_s; ap_asyncIrq <= ap_asyncIrq_s; ap_asyncIrq_n <= not ap_asyncIrq_s; spi_clk_s <= spi_clk; spi_sel_s <= not spi_sel_n; spi_mosi_s <= spi_mosi; theSyncProc : process(clk50, rst) begin if rst = '1' then spi_sel_s1 <= '0'; spi_sel_s2 <= '0'; spi_clk_s1 <= '0'; spi_clk_s2 <= '0'; spi_mosi_s1 <= '0'; spi_mosi_s2 <= '0'; elsif clk50 = '1' and clk50'event then spi_sel_s1 <= spi_sel_s; spi_sel_s2 <= spi_sel_s1; spi_clk_s1 <= spi_clk_s; spi_clk_s2 <= spi_clk_s1; spi_mosi_s1 <= spi_mosi_s; spi_mosi_s2 <= spi_mosi_s1; end if; end process; ------------------------------------------------------------------------------------------------------------------------ thePdiSpi : entity work.pdi_spi generic map ( spiSize_g => 8, --fixed value! cpol_g => spiCPOL_g, cpha_g => spiCPHA_g, spiBigEnd_g => spiBigEnd_g ) port map ( -- SPI spi_clk => spi_clk_s2, spi_sel => spi_sel_s2, spi_miso => spi_miso, spi_mosi => spi_mosi_s2, -- clock for AP side ap_reset => rstPcp, ap_clk => clk50, -- Avalon Slave Interface for AP ap_chipselect => ap_chipselect_s, ap_read => ap_read_s, ap_write => ap_write_s, ap_byteenable => ap_byteenable_s, ap_address => ap_address_s, ap_writedata => ap_writedata_s, ap_readdata => ap_readdata_s ); thePdi : entity work.pdi generic map ( genOnePdiClkDomain_g => genOnePdiClkDomain_g, iPdiRev_g => iPdiRev_g, iRpdos_g => iRpdos_g, iTpdos_g => iTpdos_g, genABuf1_g => genABuf1_g, genABuf2_g => genABuf2_g, genLedGadget_g => genLedGadget_g, genTimeSync_g => genTimeSync_g, genEvent_g => genEvent_g, --PDO buffer size *3 iTpdoBufSize_g => iTpdoBufSize_g, iRpdo0BufSize_g => iRpdo0BufSize_g, iRpdo1BufSize_g => iRpdo1BufSize_g, iRpdo2BufSize_g => iRpdo2BufSize_g, --asynchronous buffer size iABuf1_g => iAsyBuf1Size_g, iABuf2_g => iAsyBuf2Size_g ) port map ( pcp_reset => rstPcp, pcp_clk => clkPcp, ap_reset => rst, ap_clk => clk50, -- Avalon Slave Interface for PCP pcp_chipselect => pcp_chipselect, pcp_read => pcp_read, pcp_write => pcp_write, pcp_byteenable => pcp_byteenable, pcp_address => pcp_address, pcp_writedata => pcp_writedata, pcp_readdata => pcp_readdata, pcp_waitrequest => pcp_waitrequest, pcp_irq => irqToggle, -- Avalon Slave Interface for AP ap_chipselect => ap_chipselect_s, ap_read => ap_read_s, ap_write => ap_write_s, ap_byteenable => ap_byteenable_s, ap_address => ap_address_s, ap_writedata => ap_writedata_s, ap_readdata => ap_readdata_s, ap_waitrequest => open, ap_irq => ap_irq_s, -- async interrupt ap_asyncIrq => ap_asyncIrq_s, -- LED ledsOut => led_s, phyLink => phyLink, phyAct => phyAct, --PDI change buffer triggers rpdo_change_tog => rpdo_change_tog, tpdo_change_tog => tpdo_change_tog ); end generate genPdiSpi; -- ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ --SIMPLE I/O CN genSimpleIO : if genSimpleIO_g generate thePortIO : entity work.portio generic map ( pioValLen_g => pioValLen_g, pioGenIoBuf_g => genIoBuf_g ) port map ( s0_address => smp_address, s0_read => smp_read, s0_readdata => smp_readdata, s0_write => smp_write, s0_writedata => smp_writedata, s0_byteenable => smp_byteenable, s0_waitrequest => smp_waitrequest, clk => clkPcp, reset => rstPcp, x_pconfig => pio_pconfig, x_portInLatch => pio_portInLatch, x_portOutValid => pio_portOutValid, x_portio => pio_portio, x_portio_I => pio_portio_I, x_portio_O => pio_portio_O, x_portio_T => pio_portio_T, x_operational => pio_operational ); end generate genSimpleIO; -- ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ --OPENMAC (OPENHUB, OPENFILTER, PHY MANAGEMENT) theOpenMac : entity work.openMAC_Ethernet generic map ( endian_g => endian_g, dma_highadr_g => m_address'high, gen2ndCmpTimer_g => use2ndCmpTimer_g, genHub_g => use2ndPhy_g, iPktBufSizeLog2_g => iBufSizeLOG2_g, iPktBufSize_g => iBufSize_g, simulate => false, useIntPktBuf_g => useIntPacketBuf_g, useRmii_g => useRmii_g, useRxIntPktBuf_g => useRxIntPacketBuf_g, m_burstcount_width_g => m_burstcount_width_g, m_burstcount_const_g => m_burstcount_const_g, m_data_width_g => m_data_width_g, m_tx_fifo_size_g => m_tx_fifo_size_g, m_rx_fifo_size_g => m_rx_fifo_size_g, m_tx_burst_size_g => m_tx_burst_size_g, m_rx_burst_size_g => m_rx_burst_size_g, genSmiIO => genSmiIO, gNumSmi => gNumSmi, genPhyActLed_g => genLedGadget_g, gen_dma_observer_g => gen_dma_observer_g ) port map( clk => clk50, clkx2 => clkEth, pkt_clk => pkt_clk, m_clk => m_clk, rst => rst, m_address => m_address, m_burstcount => m_burstcount, m_burstcounter => m_burstcounter, m_byteenable => m_byteenable, m_read => m_read, m_readdata => m_readdata, m_readdatavalid => m_readdatavalid, m_write => m_write, m_writedata => m_writedata, m_waitrequest => m_waitrequest, mac_rx_irq => open, mac_tx_irq => open, act_led => phyAct(0), phy0_rst_n => phy0_Rst_n, phy0_rx_dat => phy0_RxDat, phy0_rx_dv => phy0_RxDv, phy0_rx_err => phy0_RxErr, phy0_smi_clk => phy0_SMICLK, phy0_smi_dio => phy0_SMIDat, phy0_smi_dio_I => phy0_SMIDat_I, phy0_smi_dio_O => phy0_SMIDat_O, phy0_smi_dio_T => phy0_SMIDat_T, phy0_tx_dat => phy0_TxDat, phy0_tx_en => phy0_TxEn, phy1_rst_n => phy1_Rst_n, phy1_rx_dat => phy1_RxDat, phy1_rx_dv => phy1_RxDv, phy1_rx_err => phy1_RxErr, phy1_smi_clk => phy1_SMICLK, phy1_smi_dio => phy1_SMIDat, phy1_smi_dio_I => phy1_SMIDat_I, phy1_smi_dio_O => phy1_SMIDat_O, phy1_smi_dio_T => phy1_SMIDat_T, phy1_tx_dat => phy1_TxDat, phy1_tx_en => phy1_TxEn, phyMii0_rx_clk => phyMii0_RxClk, phyMii0_rx_dat => phyMii0_RxDat, phyMii0_rx_dv => phyMii0_RxDv, phyMii0_rx_err => phyMii0_RxEr, phyMii0_tx_clk => phyMii0_TxClk, phyMii0_tx_dat => phyMii0_TxDat, phyMii0_tx_en => phyMii0_TxEn, phyMii1_rx_clk => phyMii1_RxClk, phyMii1_rx_dat => phyMii1_RxDat, phyMii1_rx_dv => phyMii1_RxDv, phyMii1_rx_err => phyMii1_RxEr, phyMii1_tx_clk => phyMii1_TxClk, phyMii1_tx_dat => phyMii1_TxDat, phyMii1_tx_en => phyMii1_TxEn, phy_rst_n => phy_Rst_n, phy_smi_clk => phy_SMIClk, phy_smi_dio_I => phy_SMIDat_I, phy_smi_dio_O => phy_SMIDat_O, phy_smi_dio_T => phy_SMIDat_T, phy_smi_dio => phy_SMIDat, pkt_address => mbf_address, pkt_byteenable => mbf_byteenable, pkt_chipselect => mbf_chipselect, pkt_read => mbf_read, pkt_readdata => mbf_readdata, pkt_waitrequest => mbf_waitrequest, pkt_write => mbf_write, pkt_writedata => mbf_writedata, s_address => mac_address, s_byteenable => mac_byteenable, s_chipselect => mac_chipselect, s_irq => mac_irq, s_read => mac_read, s_readdata => mac_readdata, s_waitrequest => mac_waitrequest, s_write => mac_write, s_writedata => mac_writedata, t_address => tcp_address, t_byteenable => tcp_byteenable, t_chipselect => tcp_chipselect, t_irq => tcp_irq, t_read => tcp_read, t_readdata => tcp_readdata, t_tog => irqToggle, t_waitrequest => tcp_waitrequest, t_write => tcp_write, t_writedata => tcp_writedata ); phyAct(1) <= phyAct(0); -- ------------------------------------------------------------------------------------------------------------------------ end rtl;
------------------------------------------------------------------------------------------------------------------------ -- POWERLINK IP-Core -- -- Copyright (C) 2010 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------------------------------------------------ -- Version History ------------------------------------------------------------------------------------------------------------------------ -- 2010-08-23 V0.01 zelenkaj First version -- 2010-09-13 V0.02 zelenkaj added selection Rmii / Mii -- 2010-10-18 V0.03 zelenkaj added selection Big/Little Endian (pdi_par) -- use bidirectional bus (pdi_par) -- 2010-11-23 V0.04 zelenkaj Added 2 GPIO signals to parallel interface -- Added Operational Flag to simple I/O interface -- Omitted T/RPDO descriptor sections in DPR -- Added generic to set duration of valid assertion (portio) -- 2010-11-29 V0.05 zelenkaj Added Big/Little Endian (pdi_spi) -- 2010-12-06 V0.06 zelenkaj Bugfix: ap_irq was not driven in SPI configuration -- 2011-01-10 V0.07 zelenkaj Added 2-stage sync to SPI input pins -- 2011-02-24 V0.08 zelenkaj minor changes (naming conventions Mii->SMI) -- 2011-03-14 V0.09 zelenkaj minor change, added generic for rx packet buffer location -- 2011-03-21 V0.10 zelenkaj clean up -- 2011-03-28 V0.20 zelenkaj Changed: Structure of Control/Status Register -- Added: LED -- Added: Events -- Added/Changed: Asynchronous buffer 2x Ping-Pong -- 2011-04-04 V0.21 zelenkaj parallel interface, sync moved to pdi_par -- minor: led_status is the official name -- 2011-04-26 V0.22 zelenkaj generic for clock domain selection -- 2011-04-28 V0.23 zelenkaj second cmp timer of openMAC is optinal by generic -- generic for second phy port of openMAC -- 2011-05-06 V0.24 zelenkaj some naming convention changes -- bug fix: use the RX_ER signal, it has important meaning! -- 2011-05-09 V0.25 zelenkaj Hardware Acceleration (HW ACC) added. -- 2011-07-23 V0.26 zelenkaj openFILTER enhanced by RxErr signal -- 2011-07-25 V0.27 zelenkaj LED gadget and asynchronous buffer optional -- 2011-08-08 V0.28 zelenkaj LED gadget enhancement -> added 8 general purpose outputs -- 2011-08-02 V1.00 zelenkaj exchanged Avalon interface with entity openMAC_Ethernet -- 2011-09-05 V1.01 zelenkaj SPI PDI missed to connect async irq to toplevel -- 2011-10-20 V1.02 zelenkaj SMI export of in, out and tristate, endian generic -- 2011-11-07 V1.03 zelenkaj dma generic for PLB/AXI support necessary -- 2011-11-21 V1.04 zelenkaj added time synchronization feature -- 2011-11-28 V1.05 zelenkaj added waitrequest signals to pdi pcp/ap -- 2011-11-29 V1.06 zelenkaj event is optional -- 2011-11-30 V1.07 zelenkaj Added generic for DMA observer -- 2011-12-02 V1.08 zelenkaj Added I, O and T instead of IO ports -- 2012-01-09 V1.09 zelenkaj Added ap_syncIrq for external AP -- 2012-01-26 V1.10 zelenkaj Added generic for SMI generation and one SMI ports -- Omit hwacc options, since we are fast enough! ------------------------------------------------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity powerlink is generic( -- GENERAL GENERICS -- endian_g : string := "little"; genOnePdiClkDomain_g : boolean := false; genPdi_g : boolean := true; genInternalAp_g : boolean := true; genSimpleIO_g : boolean := false; genSpiAp_g : boolean := false; -- OPENMAC GENERICS Simulate : boolean := false; iBufSize_g : integer := 1024; iBufSizeLOG2_g : integer := 10; useRmii_g : boolean := true; --use Rmii useIntPacketBuf_g : boolean := true; --internal packet buffer useRxIntPacketBuf_g : boolean := true; --rx buffer located in internal packet buffer use2ndCmpTimer_g : boolean := true; --use second cmp timer (used in PDI) use2ndPhy_g : boolean := true; --use second phy (introduces openHUB) m_burstcount_width_g : integer := 4; m_burstcount_const_g : boolean := true; --hold burst value during transfer m_tx_burst_size_g : integer := 16; --0 < x =< 2**m_burstcount_width_g m_rx_burst_size_g : integer := 16; --0 < x =< 2**m_burstcount_width_g m_tx_fifo_size_g : integer := 16; m_rx_fifo_size_g : integer := 16; m_data_width_g : integer := 16; gen_dma_observer_g : boolean := true; genSmiIO : boolean := true; --drive SMI IO if true gNumSmi : integer range 1 to 2 := 2; --number of SMI used -- PDI GENERICS iRpdos_g : integer := 3; iTpdos_g : integer := 1; genABuf1_g : boolean := true; --if false iABuf1_g must be set to 0! genABuf2_g : boolean := true; --if false iABuf2_g must be set to 0! genLedGadget_g : boolean := false; genTimeSync_g : boolean := false; genEvent_g : boolean := false; --PDO buffer size *3 iTpdoBufSize_g : integer := 100; iRpdo0BufSize_g : integer := 100; iRpdo1BufSize_g : integer := 100; iRpdo2BufSize_g : integer := 100; --asynchronous buffer size iAsyBuf1Size_g : integer := 100; iAsyBuf2Size_g : integer := 100; iPdiRev_g : integer := 16#55AA#; -- 8/16bit PARALLEL PDI GENERICS papDataWidth_g : integer := 8; papLowAct_g : boolean := false; papBigEnd_g : boolean := false; -- SPI GENERICS spiCPOL_g : boolean := false; spiCPHA_g : boolean := false; spiBigEnd_g : boolean := false; -- PORTIO pioValLen_g : integer := 50; --clock ticks of pcp_clk -- GENERAL TARGET DEPENDINGS genIoBuf_g : boolean := true --generates IO buffers ); port( -- CLOCK / RESET PORTS clk50 : in std_logic; --RMII clk rst : in std_logic; --general reset clkEth : in std_logic; --Tx Reg clk m_clk : in std_logic; --openMAC DMA master clock pkt_clk : in std_logic; --openMAC packet buffer clock (don't use pcp..) clkPcp : in std_logic; --pcp clk clkAp : in std_logic; --ap clk rstPcp : in std_logic; --rst from pcp side rstAp : in std_logic; --rst ap -- OPENMAC --- OPENMAC PORTS mac_chipselect : in std_logic; mac_read : in std_logic; mac_write : in std_logic; mac_byteenable : in std_logic_vector(1 downto 0); mac_address : in std_logic_vector(11 downto 0); mac_writedata : in std_logic_vector(15 downto 0); mac_readdata : out std_logic_vector(15 downto 0) := (others => '0'); mac_waitrequest : out std_logic; mac_irq : out std_logic := '0'; --- TIMER COMPARE PORTS tcp_chipselect : in std_logic; tcp_read : in std_logic; tcp_write : in std_logic; tcp_byteenable : in std_logic_vector(3 downto 0); tcp_address : in std_logic_vector(1 downto 0); tcp_writedata : in std_logic_vector(31 downto 0); tcp_readdata : out std_logic_vector(31 downto 0) := (others => '0'); tcp_waitrequest : out std_logic; tcp_irq : out std_logic := '0'; --- MAC BUFFER PORTS mbf_chipselect : in std_logic; mbf_read : in std_logic; mbf_write : in std_logic; mbf_byteenable : in std_logic_vector(3 downto 0); mbf_address : in std_logic_vector(ibufsizelog2_g-3 downto 0); mbf_writedata : in std_logic_vector(31 downto 0); mbf_readdata : out std_logic_vector(31 downto 0) := (others => '0'); mbf_waitrequest : out std_logic; --- OPENMAC DMA PORTS m_read : OUT STD_LOGIC := '0'; m_write : OUT STD_LOGIC := '0'; m_byteenable : OUT STD_LOGIC_VECTOR(m_data_width_g/8-1 DOWNTO 0) := (others => '0'); m_address : OUT STD_LOGIC_VECTOR(29 DOWNTO 0) := (others => '0'); m_writedata : OUT STD_LOGIC_VECTOR(m_data_width_g-1 DOWNTO 0) := (others => '0'); m_readdata : IN STD_LOGIC_VECTOR(m_data_width_g-1 DOWNTO 0) := (others => '0'); m_waitrequest : IN STD_LOGIC; m_readdatavalid : in STD_LOGIC := '0'; m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0); m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0); -- PDI --- PCP PORTS pcp_chipselect : in std_logic; pcp_read : in std_logic; pcp_write : in std_logic; pcp_byteenable : in std_logic_vector(3 downto 0); pcp_address : in std_logic_vector(12 downto 0); pcp_writedata : in std_logic_vector(31 downto 0); pcp_readdata : out std_logic_vector(31 downto 0) := (others => '0'); pcp_waitrequest : out std_logic; --- AP PORTS ap_irq : out std_logic := '0'; ap_irq_n : out std_logic := '1'; ap_syncIrq : out std_logic := '0'; ap_syncIrq_n : out std_logic := '1'; ap_asyncIrq : out std_logic := '0'; ap_asyncIrq_n : out std_logic := '1'; ---- AVALON ap_chipselect : in std_logic; ap_read : in std_logic; ap_write : in std_logic; ap_byteenable : in std_logic_vector(3 downto 0); ap_address : in std_logic_vector(12 downto 0); ap_writedata : in std_logic_vector(31 downto 0); ap_readdata : out std_logic_vector(31 downto 0) := (others => '0'); ap_waitrequest : out std_logic; ---- 8/16bit parallel pap_cs : in std_logic; pap_rd : in std_logic; pap_wr : in std_logic; pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0); pap_cs_n : in std_logic; pap_rd_n : in std_logic; pap_wr_n : in std_logic; pap_be_n : in std_logic_vector(papDataWidth_g/8-1 downto 0); pap_addr : in std_logic_vector(15 downto 0); pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0'); pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0'); pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0); pap_data_T : out std_logic; pap_ack : out std_logic := '0'; pap_ack_n : out std_logic := '1'; pap_gpio : inout std_logic_vector(1 downto 0) := (others => '0'); pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0'); pap_gpio_O : out std_logic_vector(1 downto 0); pap_gpio_T : out std_logic_vector(1 downto 0); ---- SPI spi_clk : in std_logic; spi_sel_n : in std_logic; spi_mosi : in std_logic; spi_miso : out std_logic := '0'; ---- simple I/O smp_address : in std_logic; smp_read : in std_logic; smp_readdata : out std_logic_vector(31 downto 0) := (others => '0'); smp_write : in std_logic; smp_writedata : in std_logic_vector(31 downto 0); smp_byteenable : in std_logic_vector(3 downto 0); smp_waitrequest : out std_logic; pio_pconfig : in std_logic_vector(3 downto 0); pio_portInLatch : in std_logic_vector(3 downto 0); pio_portOutValid : out std_logic_vector(3 downto 0) := (others => '0'); pio_portio : inout std_logic_vector(31 downto 0) := (others => '0'); pio_portio_I : in std_logic_vector(31 downto 0) := (others => '0'); pio_portio_O : out std_logic_vector(31 downto 0); pio_portio_T : out std_logic_vector(31 downto 0); pio_operational : out std_logic := '0'; -- EXTERNAL --- PHY MANAGEMENT ---- shared (valid if gNumSmi = 1) phy_SMIClk : out std_logic := '0'; phy_SMIDat : inout std_logic := '1'; phy_SMIDat_I : in std_logic := '1'; phy_SMIDat_O : out std_logic; phy_SMIDat_T : out std_logic; phy_Rst_n : out std_logic := '1'; ---- PHY0 (valid if gNumSmi = 2) phy0_SMIClk : out std_logic := '0'; phy0_SMIDat : inout std_logic := '1'; phy0_SMIDat_I : in std_logic := '1'; phy0_SMIDat_O : out std_logic; phy0_SMIDat_T : out std_logic; phy0_Rst_n : out std_logic := '1'; phy0_link : in std_logic := '0'; ---- PHY1 (valid if gNumSmi = 2) phy1_SMIClk : out std_logic := '0'; phy1_SMIDat : inout std_logic := '1'; phy1_SMIDat_I : in std_logic := '1'; phy1_SMIDat_O : out std_logic; phy1_SMIDat_T : out std_logic; phy1_Rst_n : out std_logic := '1'; phy1_link : in std_logic := '0'; --- RMII PORTS phy0_RxDat : in std_logic_vector(1 downto 0); phy0_RxDv : in std_logic; phy0_RxErr : in std_logic; phy0_TxDat : out std_logic_vector(1 downto 0) := (others => '0'); phy0_TxEn : out std_logic := '0'; phy1_RxDat : in std_logic_vector(1 downto 0) := (others => '0'); phy1_RxDv : in std_logic; phy1_RxErr : in std_logic; phy1_TxDat : out std_logic_vector(1 downto 0) := (others => '0'); phy1_TxEn : out std_logic := '0'; --- MII PORTS phyMii0_RxClk : in std_logic; phyMii0_RxDat : in std_logic_vector(3 downto 0) := (others => '0'); phyMii0_RxDv : in std_logic; phyMii0_RxEr : in std_logic; phyMii0_TxClk : in std_logic; phyMii0_TxDat : out std_logic_vector(3 downto 0) := (others => '0'); phyMii0_TxEn : out std_logic := '0'; phyMii0_TxEr : out std_logic := '0'; phyMii1_RxClk : in std_logic; phyMii1_RxDat : in std_logic_vector(3 downto 0) := (others => '0'); phyMii1_RxDv : in std_logic; phyMii1_RxEr : in std_logic; phyMii1_TxClk : in std_logic; phyMii1_TxDat : out std_logic_vector(3 downto 0) := (others => '0'); phyMii1_TxEn : out std_logic := '0'; phyMii1_TxEr : out std_logic := '0'; --- LEDs led_error : out std_logic := '0'; led_status : out std_logic := '0'; led_phyLink : out std_logic_vector(1 downto 0) := (others => '0'); led_phyAct : out std_logic_vector(1 downto 0) := (others => '0'); led_opt : out std_logic_vector(1 downto 0) := (others => '0'); led_gpo : out std_logic_vector(7 downto 0) := (others => '0') ); end powerlink; architecture rtl of powerlink is signal smi_Clk : std_logic := '0'; signal smi_Di : std_logic := '0'; signal smi_Do : std_logic := '0'; signal smi_Doe : std_logic := '0'; signal phy_nResetOut : std_logic := '0'; signal irqToggle : std_logic := '0'; signal ap_chipselect_s : std_logic := '0'; signal ap_read_s : std_logic := '0'; signal ap_write_s : std_logic := '0'; signal ap_byteenable_s : std_logic_vector(ap_byteenable'range) := (others => '0'); signal ap_address_s : std_logic_vector(ap_address'range) := (others => '0'); signal ap_writedata_s : std_logic_vector(ap_writedata'range):= (others => '0'); signal ap_readdata_s : std_logic_vector(ap_readdata'range) := (others => '0'); signal pap_cs_s : std_logic; signal pap_rd_s : std_logic; signal pap_wr_s : std_logic; signal pap_be_s : std_logic_vector(pap_be'range); signal pap_ack_s : std_logic; signal ap_irq_s : std_logic; signal ap_asyncIrq_s : std_logic; signal spi_sel_s : std_logic; signal spi_sel_s1 : std_logic; signal spi_sel_s2 : std_logic; signal spi_clk_s : std_logic; signal spi_clk_s1 : std_logic; signal spi_clk_s2 : std_logic; signal spi_mosi_s : std_logic; signal spi_mosi_s1 : std_logic; signal spi_mosi_s2 : std_logic; signal phyLink, phyAct : std_logic_vector(1 downto 0); signal led_s : std_logic_vector(15 downto 0); signal clkAp_s, rstAp_s : std_logic; --PDI change buffer triggers for hw acc to pdi signal rpdo_change_tog : std_logic_vector(2 downto 0); signal tpdo_change_tog : std_logic; begin --general signals clkAp_s <= clkAp when genOnePdiClkDomain_g = FALSE else clkPcp; rstAp_s <= rstAp when genOnePdiClkDomain_g = FALSE else rstPcp; phyLink <= phy1_link & phy0_link; --LEDs: GPO7, ..., GPO0, O1, O0, PA1, PL1, PA0, PL0, E, S led_error <= led_s(1); led_status <= led_s(0); led_phyLink <= led_s(4) & led_s(2); led_phyAct <= led_s(5) & led_s(3); led_opt <= led_s(7) & led_s(6); led_gpo <= led_s(15 downto 8); ------------------------------------------------------------------------------------------------------------------------ --PCP + AP genPdi : if genPdi_g and genInternalAp_g and not genSpiAp_g generate --sync and async interrupt are driven by only one line -- this gives some effort for Nios II AP ;) ap_irq <= ap_irq_s or ap_asyncIrq_s; theAvalonPdi : entity work.pdi generic map ( genOnePdiClkDomain_g => genOnePdiClkDomain_g, iPdiRev_g => iPdiRev_g, iRpdos_g => iRpdos_g, iTpdos_g => iTpdos_g, genABuf1_g => genABuf1_g, genABuf2_g => genABuf2_g, genLedGadget_g => genLedGadget_g, genTimeSync_g => genTimeSync_g, genEvent_g => genEvent_g, --PDO buffer size *3 iTpdoBufSize_g => iTpdoBufSize_g, iRpdo0BufSize_g => iRpdo0BufSize_g, iRpdo1BufSize_g => iRpdo1BufSize_g, iRpdo2BufSize_g => iRpdo2BufSize_g, --asynchronous buffer size iABuf1_g => iAsyBuf1Size_g, iABuf2_g => iAsyBuf2Size_g ) port map ( pcp_reset => rstPcp, pcp_clk => clkPcp, ap_reset => rstAp_s, ap_clk => clkAp_s, -- Avalon Slave Interface for PCP pcp_chipselect => pcp_chipselect, pcp_read => pcp_read, pcp_write => pcp_write, pcp_byteenable => pcp_byteenable, pcp_address => pcp_address, pcp_writedata => pcp_writedata, pcp_readdata => pcp_readdata, pcp_waitrequest => pcp_waitrequest, pcp_irq => irqToggle, -- Avalon Slave Interface for AP ap_chipselect => ap_chipselect, ap_read => ap_read, ap_write => ap_write, ap_byteenable => ap_byteenable, ap_address => ap_address, ap_writedata => ap_writedata, ap_readdata => ap_readdata, ap_waitrequest => ap_waitrequest, ap_irq => ap_irq_s, -- async interrupt ap_asyncIrq => ap_asyncIrq_s, -- LED ledsOut => led_s, phyLink => phyLink, phyAct => phyAct, --PDI change buffer triggers rpdo_change_tog => rpdo_change_tog, tpdo_change_tog => tpdo_change_tog ); end generate genPdi; --AP is external connected via parallel interface genPdiPar : if genPdi_g and not genInternalAp_g and not genSpiAp_g generate --only 8 or 16bit data width is allowed ASSERT ( papDataWidth_g = 8 or papDataWidth_g = 16 ) REPORT "External parallel port only allows 8 or 16bit data width!" severity failure; ------------------------------------------------------------------------------------- --convert active low signals to active high - respectively assign active high signals theActiveLowGen : if papLowAct_g generate pap_wr_s <= not pap_wr_n; pap_rd_s <= not pap_rd_n; pap_cs_s <= not pap_cs_n; pap_be_s <= not pap_be_n; end generate; theActiveHighGen : if not papLowAct_g generate pap_wr_s <= pap_wr; pap_rd_s <= pap_rd; pap_cs_s <= pap_cs; pap_be_s <= pap_be; end generate; ap_syncIrq <= ap_irq_s; ap_syncIrq_n <= not ap_irq_s; ap_asyncIrq <= ap_asyncIrq_s; ap_asyncIrq_n <= not ap_asyncIrq_s; pap_ack <= pap_ack_s; pap_ack_n <= not pap_ack_s; -- ------------------------------------------------------------------------------------- theParPort : entity work.pdi_par generic map ( papDataWidth_g => papDataWidth_g, papBigEnd_g => papBigEnd_g, papGenIoBuf_g => genIoBuf_g ) port map ( -- 8/16bit parallel pap_cs => pap_cs_s, pap_rd => pap_rd_s, pap_wr => pap_wr_s, pap_be => pap_be_s, pap_addr => pap_addr, pap_data => pap_data, pap_data_I => pap_data_I, pap_data_O => pap_data_O, pap_data_T => pap_data_T, pap_ack => pap_ack_s, pap_gpio => pap_gpio, pap_gpio_I => pap_gpio_I, pap_gpio_O => pap_gpio_O, pap_gpio_T => pap_gpio_T, -- clock for AP side ap_reset => rstPcp, ap_clk => clk50, -- Avalon Slave Interface for AP ap_chipselect => ap_chipselect_s, ap_read => ap_read_s, ap_write => ap_write_s, ap_byteenable => ap_byteenable_s, ap_address => ap_address_s, ap_writedata => ap_writedata_s, ap_readdata => ap_readdata_s ); thePdi : entity work.pdi generic map ( genOnePdiClkDomain_g => genOnePdiClkDomain_g, iPdiRev_g => iPdiRev_g, iRpdos_g => iRpdos_g, iTpdos_g => iTpdos_g, genABuf1_g => genABuf1_g, genABuf2_g => genABuf2_g, genLedGadget_g => genLedGadget_g, genTimeSync_g => genTimeSync_g, genEvent_g => genEvent_g, --PDO buffer size *3 iTpdoBufSize_g => iTpdoBufSize_g, iRpdo0BufSize_g => iRpdo0BufSize_g, iRpdo1BufSize_g => iRpdo1BufSize_g, iRpdo2BufSize_g => iRpdo2BufSize_g, --asynchronous buffer size iABuf1_g => iAsyBuf1Size_g, iABuf2_g => iAsyBuf2Size_g ) port map ( pcp_reset => rstPcp, pcp_clk => clkPcp, ap_reset => rst, ap_clk => clk50, -- Avalon Slave Interface for PCP pcp_chipselect => pcp_chipselect, pcp_read => pcp_read, pcp_write => pcp_write, pcp_byteenable => pcp_byteenable, pcp_address => pcp_address, pcp_writedata => pcp_writedata, pcp_readdata => pcp_readdata, pcp_waitrequest => pcp_waitrequest, pcp_irq => irqToggle, -- Avalon Slave Interface for AP ap_chipselect => ap_chipselect_s, ap_read => ap_read_s, ap_write => ap_write_s, ap_byteenable => ap_byteenable_s, ap_address => ap_address_s, ap_writedata => ap_writedata_s, ap_readdata => ap_readdata_s, ap_waitrequest => open, ap_irq => ap_irq_s, -- async interrupt ap_asyncIrq => ap_asyncIrq_s, -- LED ledsOut => led_s, phyLink => phyLink, phyAct => phyAct, --PDI change buffer triggers rpdo_change_tog => rpdo_change_tog, tpdo_change_tog => tpdo_change_tog ); end generate genPdiPar; --AP is extern connected via SPI genPdiSpi : if genPdi_g and genSpiAp_g generate ap_syncIrq <= ap_irq_s; ap_syncIrq_n <= not ap_irq_s; ap_asyncIrq <= ap_asyncIrq_s; ap_asyncIrq_n <= not ap_asyncIrq_s; spi_clk_s <= spi_clk; spi_sel_s <= not spi_sel_n; spi_mosi_s <= spi_mosi; theSyncProc : process(clk50, rst) begin if rst = '1' then spi_sel_s1 <= '0'; spi_sel_s2 <= '0'; spi_clk_s1 <= '0'; spi_clk_s2 <= '0'; spi_mosi_s1 <= '0'; spi_mosi_s2 <= '0'; elsif clk50 = '1' and clk50'event then spi_sel_s1 <= spi_sel_s; spi_sel_s2 <= spi_sel_s1; spi_clk_s1 <= spi_clk_s; spi_clk_s2 <= spi_clk_s1; spi_mosi_s1 <= spi_mosi_s; spi_mosi_s2 <= spi_mosi_s1; end if; end process; ------------------------------------------------------------------------------------------------------------------------ thePdiSpi : entity work.pdi_spi generic map ( spiSize_g => 8, --fixed value! cpol_g => spiCPOL_g, cpha_g => spiCPHA_g, spiBigEnd_g => spiBigEnd_g ) port map ( -- SPI spi_clk => spi_clk_s2, spi_sel => spi_sel_s2, spi_miso => spi_miso, spi_mosi => spi_mosi_s2, -- clock for AP side ap_reset => rstPcp, ap_clk => clk50, -- Avalon Slave Interface for AP ap_chipselect => ap_chipselect_s, ap_read => ap_read_s, ap_write => ap_write_s, ap_byteenable => ap_byteenable_s, ap_address => ap_address_s, ap_writedata => ap_writedata_s, ap_readdata => ap_readdata_s ); thePdi : entity work.pdi generic map ( genOnePdiClkDomain_g => genOnePdiClkDomain_g, iPdiRev_g => iPdiRev_g, iRpdos_g => iRpdos_g, iTpdos_g => iTpdos_g, genABuf1_g => genABuf1_g, genABuf2_g => genABuf2_g, genLedGadget_g => genLedGadget_g, genTimeSync_g => genTimeSync_g, genEvent_g => genEvent_g, --PDO buffer size *3 iTpdoBufSize_g => iTpdoBufSize_g, iRpdo0BufSize_g => iRpdo0BufSize_g, iRpdo1BufSize_g => iRpdo1BufSize_g, iRpdo2BufSize_g => iRpdo2BufSize_g, --asynchronous buffer size iABuf1_g => iAsyBuf1Size_g, iABuf2_g => iAsyBuf2Size_g ) port map ( pcp_reset => rstPcp, pcp_clk => clkPcp, ap_reset => rst, ap_clk => clk50, -- Avalon Slave Interface for PCP pcp_chipselect => pcp_chipselect, pcp_read => pcp_read, pcp_write => pcp_write, pcp_byteenable => pcp_byteenable, pcp_address => pcp_address, pcp_writedata => pcp_writedata, pcp_readdata => pcp_readdata, pcp_waitrequest => pcp_waitrequest, pcp_irq => irqToggle, -- Avalon Slave Interface for AP ap_chipselect => ap_chipselect_s, ap_read => ap_read_s, ap_write => ap_write_s, ap_byteenable => ap_byteenable_s, ap_address => ap_address_s, ap_writedata => ap_writedata_s, ap_readdata => ap_readdata_s, ap_waitrequest => open, ap_irq => ap_irq_s, -- async interrupt ap_asyncIrq => ap_asyncIrq_s, -- LED ledsOut => led_s, phyLink => phyLink, phyAct => phyAct, --PDI change buffer triggers rpdo_change_tog => rpdo_change_tog, tpdo_change_tog => tpdo_change_tog ); end generate genPdiSpi; -- ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ --SIMPLE I/O CN genSimpleIO : if genSimpleIO_g generate thePortIO : entity work.portio generic map ( pioValLen_g => pioValLen_g, pioGenIoBuf_g => genIoBuf_g ) port map ( s0_address => smp_address, s0_read => smp_read, s0_readdata => smp_readdata, s0_write => smp_write, s0_writedata => smp_writedata, s0_byteenable => smp_byteenable, s0_waitrequest => smp_waitrequest, clk => clkPcp, reset => rstPcp, x_pconfig => pio_pconfig, x_portInLatch => pio_portInLatch, x_portOutValid => pio_portOutValid, x_portio => pio_portio, x_portio_I => pio_portio_I, x_portio_O => pio_portio_O, x_portio_T => pio_portio_T, x_operational => pio_operational ); end generate genSimpleIO; -- ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ --OPENMAC (OPENHUB, OPENFILTER, PHY MANAGEMENT) theOpenMac : entity work.openMAC_Ethernet generic map ( endian_g => endian_g, dma_highadr_g => m_address'high, gen2ndCmpTimer_g => use2ndCmpTimer_g, genHub_g => use2ndPhy_g, iPktBufSizeLog2_g => iBufSizeLOG2_g, iPktBufSize_g => iBufSize_g, simulate => false, useIntPktBuf_g => useIntPacketBuf_g, useRmii_g => useRmii_g, useRxIntPktBuf_g => useRxIntPacketBuf_g, m_burstcount_width_g => m_burstcount_width_g, m_burstcount_const_g => m_burstcount_const_g, m_data_width_g => m_data_width_g, m_tx_fifo_size_g => m_tx_fifo_size_g, m_rx_fifo_size_g => m_rx_fifo_size_g, m_tx_burst_size_g => m_tx_burst_size_g, m_rx_burst_size_g => m_rx_burst_size_g, genSmiIO => genSmiIO, gNumSmi => gNumSmi, genPhyActLed_g => genLedGadget_g, gen_dma_observer_g => gen_dma_observer_g ) port map( clk => clk50, clkx2 => clkEth, pkt_clk => pkt_clk, m_clk => m_clk, rst => rst, m_address => m_address, m_burstcount => m_burstcount, m_burstcounter => m_burstcounter, m_byteenable => m_byteenable, m_read => m_read, m_readdata => m_readdata, m_readdatavalid => m_readdatavalid, m_write => m_write, m_writedata => m_writedata, m_waitrequest => m_waitrequest, mac_rx_irq => open, mac_tx_irq => open, act_led => phyAct(0), phy0_rst_n => phy0_Rst_n, phy0_rx_dat => phy0_RxDat, phy0_rx_dv => phy0_RxDv, phy0_rx_err => phy0_RxErr, phy0_smi_clk => phy0_SMICLK, phy0_smi_dio => phy0_SMIDat, phy0_smi_dio_I => phy0_SMIDat_I, phy0_smi_dio_O => phy0_SMIDat_O, phy0_smi_dio_T => phy0_SMIDat_T, phy0_tx_dat => phy0_TxDat, phy0_tx_en => phy0_TxEn, phy1_rst_n => phy1_Rst_n, phy1_rx_dat => phy1_RxDat, phy1_rx_dv => phy1_RxDv, phy1_rx_err => phy1_RxErr, phy1_smi_clk => phy1_SMICLK, phy1_smi_dio => phy1_SMIDat, phy1_smi_dio_I => phy1_SMIDat_I, phy1_smi_dio_O => phy1_SMIDat_O, phy1_smi_dio_T => phy1_SMIDat_T, phy1_tx_dat => phy1_TxDat, phy1_tx_en => phy1_TxEn, phyMii0_rx_clk => phyMii0_RxClk, phyMii0_rx_dat => phyMii0_RxDat, phyMii0_rx_dv => phyMii0_RxDv, phyMii0_rx_err => phyMii0_RxEr, phyMii0_tx_clk => phyMii0_TxClk, phyMii0_tx_dat => phyMii0_TxDat, phyMii0_tx_en => phyMii0_TxEn, phyMii1_rx_clk => phyMii1_RxClk, phyMii1_rx_dat => phyMii1_RxDat, phyMii1_rx_dv => phyMii1_RxDv, phyMii1_rx_err => phyMii1_RxEr, phyMii1_tx_clk => phyMii1_TxClk, phyMii1_tx_dat => phyMii1_TxDat, phyMii1_tx_en => phyMii1_TxEn, phy_rst_n => phy_Rst_n, phy_smi_clk => phy_SMIClk, phy_smi_dio_I => phy_SMIDat_I, phy_smi_dio_O => phy_SMIDat_O, phy_smi_dio_T => phy_SMIDat_T, phy_smi_dio => phy_SMIDat, pkt_address => mbf_address, pkt_byteenable => mbf_byteenable, pkt_chipselect => mbf_chipselect, pkt_read => mbf_read, pkt_readdata => mbf_readdata, pkt_waitrequest => mbf_waitrequest, pkt_write => mbf_write, pkt_writedata => mbf_writedata, s_address => mac_address, s_byteenable => mac_byteenable, s_chipselect => mac_chipselect, s_irq => mac_irq, s_read => mac_read, s_readdata => mac_readdata, s_waitrequest => mac_waitrequest, s_write => mac_write, s_writedata => mac_writedata, t_address => tcp_address, t_byteenable => tcp_byteenable, t_chipselect => tcp_chipselect, t_irq => tcp_irq, t_read => tcp_read, t_readdata => tcp_readdata, t_tog => irqToggle, t_waitrequest => tcp_waitrequest, t_write => tcp_write, t_writedata => tcp_writedata ); phyAct(1) <= phyAct(0); -- ------------------------------------------------------------------------------------------------------------------------ end rtl;
------------------------------------------------------------------------------------------------------------------------ -- POWERLINK IP-Core -- -- Copyright (C) 2010 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------------------------------------------------ -- Version History ------------------------------------------------------------------------------------------------------------------------ -- 2010-08-23 V0.01 zelenkaj First version -- 2010-09-13 V0.02 zelenkaj added selection Rmii / Mii -- 2010-10-18 V0.03 zelenkaj added selection Big/Little Endian (pdi_par) -- use bidirectional bus (pdi_par) -- 2010-11-23 V0.04 zelenkaj Added 2 GPIO signals to parallel interface -- Added Operational Flag to simple I/O interface -- Omitted T/RPDO descriptor sections in DPR -- Added generic to set duration of valid assertion (portio) -- 2010-11-29 V0.05 zelenkaj Added Big/Little Endian (pdi_spi) -- 2010-12-06 V0.06 zelenkaj Bugfix: ap_irq was not driven in SPI configuration -- 2011-01-10 V0.07 zelenkaj Added 2-stage sync to SPI input pins -- 2011-02-24 V0.08 zelenkaj minor changes (naming conventions Mii->SMI) -- 2011-03-14 V0.09 zelenkaj minor change, added generic for rx packet buffer location -- 2011-03-21 V0.10 zelenkaj clean up -- 2011-03-28 V0.20 zelenkaj Changed: Structure of Control/Status Register -- Added: LED -- Added: Events -- Added/Changed: Asynchronous buffer 2x Ping-Pong -- 2011-04-04 V0.21 zelenkaj parallel interface, sync moved to pdi_par -- minor: led_status is the official name -- 2011-04-26 V0.22 zelenkaj generic for clock domain selection -- 2011-04-28 V0.23 zelenkaj second cmp timer of openMAC is optinal by generic -- generic for second phy port of openMAC -- 2011-05-06 V0.24 zelenkaj some naming convention changes -- bug fix: use the RX_ER signal, it has important meaning! -- 2011-05-09 V0.25 zelenkaj Hardware Acceleration (HW ACC) added. -- 2011-07-23 V0.26 zelenkaj openFILTER enhanced by RxErr signal -- 2011-07-25 V0.27 zelenkaj LED gadget and asynchronous buffer optional -- 2011-08-08 V0.28 zelenkaj LED gadget enhancement -> added 8 general purpose outputs -- 2011-08-02 V1.00 zelenkaj exchanged Avalon interface with entity openMAC_Ethernet -- 2011-09-05 V1.01 zelenkaj SPI PDI missed to connect async irq to toplevel -- 2011-10-20 V1.02 zelenkaj SMI export of in, out and tristate, endian generic -- 2011-11-07 V1.03 zelenkaj dma generic for PLB/AXI support necessary -- 2011-11-21 V1.04 zelenkaj added time synchronization feature -- 2011-11-28 V1.05 zelenkaj added waitrequest signals to pdi pcp/ap -- 2011-11-29 V1.06 zelenkaj event is optional -- 2011-11-30 V1.07 zelenkaj Added generic for DMA observer -- 2011-12-02 V1.08 zelenkaj Added I, O and T instead of IO ports -- 2012-01-09 V1.09 zelenkaj Added ap_syncIrq for external AP -- 2012-01-26 V1.10 zelenkaj Added generic for SMI generation and one SMI ports -- Omit hwacc options, since we are fast enough! ------------------------------------------------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity powerlink is generic( -- GENERAL GENERICS -- endian_g : string := "little"; genOnePdiClkDomain_g : boolean := false; genPdi_g : boolean := true; genInternalAp_g : boolean := true; genSimpleIO_g : boolean := false; genSpiAp_g : boolean := false; -- OPENMAC GENERICS Simulate : boolean := false; iBufSize_g : integer := 1024; iBufSizeLOG2_g : integer := 10; useRmii_g : boolean := true; --use Rmii useIntPacketBuf_g : boolean := true; --internal packet buffer useRxIntPacketBuf_g : boolean := true; --rx buffer located in internal packet buffer use2ndCmpTimer_g : boolean := true; --use second cmp timer (used in PDI) use2ndPhy_g : boolean := true; --use second phy (introduces openHUB) m_burstcount_width_g : integer := 4; m_burstcount_const_g : boolean := true; --hold burst value during transfer m_tx_burst_size_g : integer := 16; --0 < x =< 2**m_burstcount_width_g m_rx_burst_size_g : integer := 16; --0 < x =< 2**m_burstcount_width_g m_tx_fifo_size_g : integer := 16; m_rx_fifo_size_g : integer := 16; m_data_width_g : integer := 16; gen_dma_observer_g : boolean := true; genSmiIO : boolean := true; --drive SMI IO if true gNumSmi : integer range 1 to 2 := 2; --number of SMI used -- PDI GENERICS iRpdos_g : integer := 3; iTpdos_g : integer := 1; genABuf1_g : boolean := true; --if false iABuf1_g must be set to 0! genABuf2_g : boolean := true; --if false iABuf2_g must be set to 0! genLedGadget_g : boolean := false; genTimeSync_g : boolean := false; genEvent_g : boolean := false; --PDO buffer size *3 iTpdoBufSize_g : integer := 100; iRpdo0BufSize_g : integer := 100; iRpdo1BufSize_g : integer := 100; iRpdo2BufSize_g : integer := 100; --asynchronous buffer size iAsyBuf1Size_g : integer := 100; iAsyBuf2Size_g : integer := 100; iPdiRev_g : integer := 16#55AA#; -- 8/16bit PARALLEL PDI GENERICS papDataWidth_g : integer := 8; papLowAct_g : boolean := false; papBigEnd_g : boolean := false; -- SPI GENERICS spiCPOL_g : boolean := false; spiCPHA_g : boolean := false; spiBigEnd_g : boolean := false; -- PORTIO pioValLen_g : integer := 50; --clock ticks of pcp_clk -- GENERAL TARGET DEPENDINGS genIoBuf_g : boolean := true --generates IO buffers ); port( -- CLOCK / RESET PORTS clk50 : in std_logic; --RMII clk rst : in std_logic; --general reset clkEth : in std_logic; --Tx Reg clk m_clk : in std_logic; --openMAC DMA master clock pkt_clk : in std_logic; --openMAC packet buffer clock (don't use pcp..) clkPcp : in std_logic; --pcp clk clkAp : in std_logic; --ap clk rstPcp : in std_logic; --rst from pcp side rstAp : in std_logic; --rst ap -- OPENMAC --- OPENMAC PORTS mac_chipselect : in std_logic; mac_read : in std_logic; mac_write : in std_logic; mac_byteenable : in std_logic_vector(1 downto 0); mac_address : in std_logic_vector(11 downto 0); mac_writedata : in std_logic_vector(15 downto 0); mac_readdata : out std_logic_vector(15 downto 0) := (others => '0'); mac_waitrequest : out std_logic; mac_irq : out std_logic := '0'; --- TIMER COMPARE PORTS tcp_chipselect : in std_logic; tcp_read : in std_logic; tcp_write : in std_logic; tcp_byteenable : in std_logic_vector(3 downto 0); tcp_address : in std_logic_vector(1 downto 0); tcp_writedata : in std_logic_vector(31 downto 0); tcp_readdata : out std_logic_vector(31 downto 0) := (others => '0'); tcp_waitrequest : out std_logic; tcp_irq : out std_logic := '0'; --- MAC BUFFER PORTS mbf_chipselect : in std_logic; mbf_read : in std_logic; mbf_write : in std_logic; mbf_byteenable : in std_logic_vector(3 downto 0); mbf_address : in std_logic_vector(ibufsizelog2_g-3 downto 0); mbf_writedata : in std_logic_vector(31 downto 0); mbf_readdata : out std_logic_vector(31 downto 0) := (others => '0'); mbf_waitrequest : out std_logic; --- OPENMAC DMA PORTS m_read : OUT STD_LOGIC := '0'; m_write : OUT STD_LOGIC := '0'; m_byteenable : OUT STD_LOGIC_VECTOR(m_data_width_g/8-1 DOWNTO 0) := (others => '0'); m_address : OUT STD_LOGIC_VECTOR(29 DOWNTO 0) := (others => '0'); m_writedata : OUT STD_LOGIC_VECTOR(m_data_width_g-1 DOWNTO 0) := (others => '0'); m_readdata : IN STD_LOGIC_VECTOR(m_data_width_g-1 DOWNTO 0) := (others => '0'); m_waitrequest : IN STD_LOGIC; m_readdatavalid : in STD_LOGIC := '0'; m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0); m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0); -- PDI --- PCP PORTS pcp_chipselect : in std_logic; pcp_read : in std_logic; pcp_write : in std_logic; pcp_byteenable : in std_logic_vector(3 downto 0); pcp_address : in std_logic_vector(12 downto 0); pcp_writedata : in std_logic_vector(31 downto 0); pcp_readdata : out std_logic_vector(31 downto 0) := (others => '0'); pcp_waitrequest : out std_logic; --- AP PORTS ap_irq : out std_logic := '0'; ap_irq_n : out std_logic := '1'; ap_syncIrq : out std_logic := '0'; ap_syncIrq_n : out std_logic := '1'; ap_asyncIrq : out std_logic := '0'; ap_asyncIrq_n : out std_logic := '1'; ---- AVALON ap_chipselect : in std_logic; ap_read : in std_logic; ap_write : in std_logic; ap_byteenable : in std_logic_vector(3 downto 0); ap_address : in std_logic_vector(12 downto 0); ap_writedata : in std_logic_vector(31 downto 0); ap_readdata : out std_logic_vector(31 downto 0) := (others => '0'); ap_waitrequest : out std_logic; ---- 8/16bit parallel pap_cs : in std_logic; pap_rd : in std_logic; pap_wr : in std_logic; pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0); pap_cs_n : in std_logic; pap_rd_n : in std_logic; pap_wr_n : in std_logic; pap_be_n : in std_logic_vector(papDataWidth_g/8-1 downto 0); pap_addr : in std_logic_vector(15 downto 0); pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0'); pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0'); pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0); pap_data_T : out std_logic; pap_ack : out std_logic := '0'; pap_ack_n : out std_logic := '1'; pap_gpio : inout std_logic_vector(1 downto 0) := (others => '0'); pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0'); pap_gpio_O : out std_logic_vector(1 downto 0); pap_gpio_T : out std_logic_vector(1 downto 0); ---- SPI spi_clk : in std_logic; spi_sel_n : in std_logic; spi_mosi : in std_logic; spi_miso : out std_logic := '0'; ---- simple I/O smp_address : in std_logic; smp_read : in std_logic; smp_readdata : out std_logic_vector(31 downto 0) := (others => '0'); smp_write : in std_logic; smp_writedata : in std_logic_vector(31 downto 0); smp_byteenable : in std_logic_vector(3 downto 0); smp_waitrequest : out std_logic; pio_pconfig : in std_logic_vector(3 downto 0); pio_portInLatch : in std_logic_vector(3 downto 0); pio_portOutValid : out std_logic_vector(3 downto 0) := (others => '0'); pio_portio : inout std_logic_vector(31 downto 0) := (others => '0'); pio_portio_I : in std_logic_vector(31 downto 0) := (others => '0'); pio_portio_O : out std_logic_vector(31 downto 0); pio_portio_T : out std_logic_vector(31 downto 0); pio_operational : out std_logic := '0'; -- EXTERNAL --- PHY MANAGEMENT ---- shared (valid if gNumSmi = 1) phy_SMIClk : out std_logic := '0'; phy_SMIDat : inout std_logic := '1'; phy_SMIDat_I : in std_logic := '1'; phy_SMIDat_O : out std_logic; phy_SMIDat_T : out std_logic; phy_Rst_n : out std_logic := '1'; ---- PHY0 (valid if gNumSmi = 2) phy0_SMIClk : out std_logic := '0'; phy0_SMIDat : inout std_logic := '1'; phy0_SMIDat_I : in std_logic := '1'; phy0_SMIDat_O : out std_logic; phy0_SMIDat_T : out std_logic; phy0_Rst_n : out std_logic := '1'; phy0_link : in std_logic := '0'; ---- PHY1 (valid if gNumSmi = 2) phy1_SMIClk : out std_logic := '0'; phy1_SMIDat : inout std_logic := '1'; phy1_SMIDat_I : in std_logic := '1'; phy1_SMIDat_O : out std_logic; phy1_SMIDat_T : out std_logic; phy1_Rst_n : out std_logic := '1'; phy1_link : in std_logic := '0'; --- RMII PORTS phy0_RxDat : in std_logic_vector(1 downto 0); phy0_RxDv : in std_logic; phy0_RxErr : in std_logic; phy0_TxDat : out std_logic_vector(1 downto 0) := (others => '0'); phy0_TxEn : out std_logic := '0'; phy1_RxDat : in std_logic_vector(1 downto 0) := (others => '0'); phy1_RxDv : in std_logic; phy1_RxErr : in std_logic; phy1_TxDat : out std_logic_vector(1 downto 0) := (others => '0'); phy1_TxEn : out std_logic := '0'; --- MII PORTS phyMii0_RxClk : in std_logic; phyMii0_RxDat : in std_logic_vector(3 downto 0) := (others => '0'); phyMii0_RxDv : in std_logic; phyMii0_RxEr : in std_logic; phyMii0_TxClk : in std_logic; phyMii0_TxDat : out std_logic_vector(3 downto 0) := (others => '0'); phyMii0_TxEn : out std_logic := '0'; phyMii0_TxEr : out std_logic := '0'; phyMii1_RxClk : in std_logic; phyMii1_RxDat : in std_logic_vector(3 downto 0) := (others => '0'); phyMii1_RxDv : in std_logic; phyMii1_RxEr : in std_logic; phyMii1_TxClk : in std_logic; phyMii1_TxDat : out std_logic_vector(3 downto 0) := (others => '0'); phyMii1_TxEn : out std_logic := '0'; phyMii1_TxEr : out std_logic := '0'; --- LEDs led_error : out std_logic := '0'; led_status : out std_logic := '0'; led_phyLink : out std_logic_vector(1 downto 0) := (others => '0'); led_phyAct : out std_logic_vector(1 downto 0) := (others => '0'); led_opt : out std_logic_vector(1 downto 0) := (others => '0'); led_gpo : out std_logic_vector(7 downto 0) := (others => '0') ); end powerlink; architecture rtl of powerlink is signal smi_Clk : std_logic := '0'; signal smi_Di : std_logic := '0'; signal smi_Do : std_logic := '0'; signal smi_Doe : std_logic := '0'; signal phy_nResetOut : std_logic := '0'; signal irqToggle : std_logic := '0'; signal ap_chipselect_s : std_logic := '0'; signal ap_read_s : std_logic := '0'; signal ap_write_s : std_logic := '0'; signal ap_byteenable_s : std_logic_vector(ap_byteenable'range) := (others => '0'); signal ap_address_s : std_logic_vector(ap_address'range) := (others => '0'); signal ap_writedata_s : std_logic_vector(ap_writedata'range):= (others => '0'); signal ap_readdata_s : std_logic_vector(ap_readdata'range) := (others => '0'); signal pap_cs_s : std_logic; signal pap_rd_s : std_logic; signal pap_wr_s : std_logic; signal pap_be_s : std_logic_vector(pap_be'range); signal pap_ack_s : std_logic; signal ap_irq_s : std_logic; signal ap_asyncIrq_s : std_logic; signal spi_sel_s : std_logic; signal spi_sel_s1 : std_logic; signal spi_sel_s2 : std_logic; signal spi_clk_s : std_logic; signal spi_clk_s1 : std_logic; signal spi_clk_s2 : std_logic; signal spi_mosi_s : std_logic; signal spi_mosi_s1 : std_logic; signal spi_mosi_s2 : std_logic; signal phyLink, phyAct : std_logic_vector(1 downto 0); signal led_s : std_logic_vector(15 downto 0); signal clkAp_s, rstAp_s : std_logic; --PDI change buffer triggers for hw acc to pdi signal rpdo_change_tog : std_logic_vector(2 downto 0); signal tpdo_change_tog : std_logic; begin --general signals clkAp_s <= clkAp when genOnePdiClkDomain_g = FALSE else clkPcp; rstAp_s <= rstAp when genOnePdiClkDomain_g = FALSE else rstPcp; phyLink <= phy1_link & phy0_link; --LEDs: GPO7, ..., GPO0, O1, O0, PA1, PL1, PA0, PL0, E, S led_error <= led_s(1); led_status <= led_s(0); led_phyLink <= led_s(4) & led_s(2); led_phyAct <= led_s(5) & led_s(3); led_opt <= led_s(7) & led_s(6); led_gpo <= led_s(15 downto 8); ------------------------------------------------------------------------------------------------------------------------ --PCP + AP genPdi : if genPdi_g and genInternalAp_g and not genSpiAp_g generate --sync and async interrupt are driven by only one line -- this gives some effort for Nios II AP ;) ap_irq <= ap_irq_s or ap_asyncIrq_s; theAvalonPdi : entity work.pdi generic map ( genOnePdiClkDomain_g => genOnePdiClkDomain_g, iPdiRev_g => iPdiRev_g, iRpdos_g => iRpdos_g, iTpdos_g => iTpdos_g, genABuf1_g => genABuf1_g, genABuf2_g => genABuf2_g, genLedGadget_g => genLedGadget_g, genTimeSync_g => genTimeSync_g, genEvent_g => genEvent_g, --PDO buffer size *3 iTpdoBufSize_g => iTpdoBufSize_g, iRpdo0BufSize_g => iRpdo0BufSize_g, iRpdo1BufSize_g => iRpdo1BufSize_g, iRpdo2BufSize_g => iRpdo2BufSize_g, --asynchronous buffer size iABuf1_g => iAsyBuf1Size_g, iABuf2_g => iAsyBuf2Size_g ) port map ( pcp_reset => rstPcp, pcp_clk => clkPcp, ap_reset => rstAp_s, ap_clk => clkAp_s, -- Avalon Slave Interface for PCP pcp_chipselect => pcp_chipselect, pcp_read => pcp_read, pcp_write => pcp_write, pcp_byteenable => pcp_byteenable, pcp_address => pcp_address, pcp_writedata => pcp_writedata, pcp_readdata => pcp_readdata, pcp_waitrequest => pcp_waitrequest, pcp_irq => irqToggle, -- Avalon Slave Interface for AP ap_chipselect => ap_chipselect, ap_read => ap_read, ap_write => ap_write, ap_byteenable => ap_byteenable, ap_address => ap_address, ap_writedata => ap_writedata, ap_readdata => ap_readdata, ap_waitrequest => ap_waitrequest, ap_irq => ap_irq_s, -- async interrupt ap_asyncIrq => ap_asyncIrq_s, -- LED ledsOut => led_s, phyLink => phyLink, phyAct => phyAct, --PDI change buffer triggers rpdo_change_tog => rpdo_change_tog, tpdo_change_tog => tpdo_change_tog ); end generate genPdi; --AP is external connected via parallel interface genPdiPar : if genPdi_g and not genInternalAp_g and not genSpiAp_g generate --only 8 or 16bit data width is allowed ASSERT ( papDataWidth_g = 8 or papDataWidth_g = 16 ) REPORT "External parallel port only allows 8 or 16bit data width!" severity failure; ------------------------------------------------------------------------------------- --convert active low signals to active high - respectively assign active high signals theActiveLowGen : if papLowAct_g generate pap_wr_s <= not pap_wr_n; pap_rd_s <= not pap_rd_n; pap_cs_s <= not pap_cs_n; pap_be_s <= not pap_be_n; end generate; theActiveHighGen : if not papLowAct_g generate pap_wr_s <= pap_wr; pap_rd_s <= pap_rd; pap_cs_s <= pap_cs; pap_be_s <= pap_be; end generate; ap_syncIrq <= ap_irq_s; ap_syncIrq_n <= not ap_irq_s; ap_asyncIrq <= ap_asyncIrq_s; ap_asyncIrq_n <= not ap_asyncIrq_s; pap_ack <= pap_ack_s; pap_ack_n <= not pap_ack_s; -- ------------------------------------------------------------------------------------- theParPort : entity work.pdi_par generic map ( papDataWidth_g => papDataWidth_g, papBigEnd_g => papBigEnd_g, papGenIoBuf_g => genIoBuf_g ) port map ( -- 8/16bit parallel pap_cs => pap_cs_s, pap_rd => pap_rd_s, pap_wr => pap_wr_s, pap_be => pap_be_s, pap_addr => pap_addr, pap_data => pap_data, pap_data_I => pap_data_I, pap_data_O => pap_data_O, pap_data_T => pap_data_T, pap_ack => pap_ack_s, pap_gpio => pap_gpio, pap_gpio_I => pap_gpio_I, pap_gpio_O => pap_gpio_O, pap_gpio_T => pap_gpio_T, -- clock for AP side ap_reset => rstPcp, ap_clk => clk50, -- Avalon Slave Interface for AP ap_chipselect => ap_chipselect_s, ap_read => ap_read_s, ap_write => ap_write_s, ap_byteenable => ap_byteenable_s, ap_address => ap_address_s, ap_writedata => ap_writedata_s, ap_readdata => ap_readdata_s ); thePdi : entity work.pdi generic map ( genOnePdiClkDomain_g => genOnePdiClkDomain_g, iPdiRev_g => iPdiRev_g, iRpdos_g => iRpdos_g, iTpdos_g => iTpdos_g, genABuf1_g => genABuf1_g, genABuf2_g => genABuf2_g, genLedGadget_g => genLedGadget_g, genTimeSync_g => genTimeSync_g, genEvent_g => genEvent_g, --PDO buffer size *3 iTpdoBufSize_g => iTpdoBufSize_g, iRpdo0BufSize_g => iRpdo0BufSize_g, iRpdo1BufSize_g => iRpdo1BufSize_g, iRpdo2BufSize_g => iRpdo2BufSize_g, --asynchronous buffer size iABuf1_g => iAsyBuf1Size_g, iABuf2_g => iAsyBuf2Size_g ) port map ( pcp_reset => rstPcp, pcp_clk => clkPcp, ap_reset => rst, ap_clk => clk50, -- Avalon Slave Interface for PCP pcp_chipselect => pcp_chipselect, pcp_read => pcp_read, pcp_write => pcp_write, pcp_byteenable => pcp_byteenable, pcp_address => pcp_address, pcp_writedata => pcp_writedata, pcp_readdata => pcp_readdata, pcp_waitrequest => pcp_waitrequest, pcp_irq => irqToggle, -- Avalon Slave Interface for AP ap_chipselect => ap_chipselect_s, ap_read => ap_read_s, ap_write => ap_write_s, ap_byteenable => ap_byteenable_s, ap_address => ap_address_s, ap_writedata => ap_writedata_s, ap_readdata => ap_readdata_s, ap_waitrequest => open, ap_irq => ap_irq_s, -- async interrupt ap_asyncIrq => ap_asyncIrq_s, -- LED ledsOut => led_s, phyLink => phyLink, phyAct => phyAct, --PDI change buffer triggers rpdo_change_tog => rpdo_change_tog, tpdo_change_tog => tpdo_change_tog ); end generate genPdiPar; --AP is extern connected via SPI genPdiSpi : if genPdi_g and genSpiAp_g generate ap_syncIrq <= ap_irq_s; ap_syncIrq_n <= not ap_irq_s; ap_asyncIrq <= ap_asyncIrq_s; ap_asyncIrq_n <= not ap_asyncIrq_s; spi_clk_s <= spi_clk; spi_sel_s <= not spi_sel_n; spi_mosi_s <= spi_mosi; theSyncProc : process(clk50, rst) begin if rst = '1' then spi_sel_s1 <= '0'; spi_sel_s2 <= '0'; spi_clk_s1 <= '0'; spi_clk_s2 <= '0'; spi_mosi_s1 <= '0'; spi_mosi_s2 <= '0'; elsif clk50 = '1' and clk50'event then spi_sel_s1 <= spi_sel_s; spi_sel_s2 <= spi_sel_s1; spi_clk_s1 <= spi_clk_s; spi_clk_s2 <= spi_clk_s1; spi_mosi_s1 <= spi_mosi_s; spi_mosi_s2 <= spi_mosi_s1; end if; end process; ------------------------------------------------------------------------------------------------------------------------ thePdiSpi : entity work.pdi_spi generic map ( spiSize_g => 8, --fixed value! cpol_g => spiCPOL_g, cpha_g => spiCPHA_g, spiBigEnd_g => spiBigEnd_g ) port map ( -- SPI spi_clk => spi_clk_s2, spi_sel => spi_sel_s2, spi_miso => spi_miso, spi_mosi => spi_mosi_s2, -- clock for AP side ap_reset => rstPcp, ap_clk => clk50, -- Avalon Slave Interface for AP ap_chipselect => ap_chipselect_s, ap_read => ap_read_s, ap_write => ap_write_s, ap_byteenable => ap_byteenable_s, ap_address => ap_address_s, ap_writedata => ap_writedata_s, ap_readdata => ap_readdata_s ); thePdi : entity work.pdi generic map ( genOnePdiClkDomain_g => genOnePdiClkDomain_g, iPdiRev_g => iPdiRev_g, iRpdos_g => iRpdos_g, iTpdos_g => iTpdos_g, genABuf1_g => genABuf1_g, genABuf2_g => genABuf2_g, genLedGadget_g => genLedGadget_g, genTimeSync_g => genTimeSync_g, genEvent_g => genEvent_g, --PDO buffer size *3 iTpdoBufSize_g => iTpdoBufSize_g, iRpdo0BufSize_g => iRpdo0BufSize_g, iRpdo1BufSize_g => iRpdo1BufSize_g, iRpdo2BufSize_g => iRpdo2BufSize_g, --asynchronous buffer size iABuf1_g => iAsyBuf1Size_g, iABuf2_g => iAsyBuf2Size_g ) port map ( pcp_reset => rstPcp, pcp_clk => clkPcp, ap_reset => rst, ap_clk => clk50, -- Avalon Slave Interface for PCP pcp_chipselect => pcp_chipselect, pcp_read => pcp_read, pcp_write => pcp_write, pcp_byteenable => pcp_byteenable, pcp_address => pcp_address, pcp_writedata => pcp_writedata, pcp_readdata => pcp_readdata, pcp_waitrequest => pcp_waitrequest, pcp_irq => irqToggle, -- Avalon Slave Interface for AP ap_chipselect => ap_chipselect_s, ap_read => ap_read_s, ap_write => ap_write_s, ap_byteenable => ap_byteenable_s, ap_address => ap_address_s, ap_writedata => ap_writedata_s, ap_readdata => ap_readdata_s, ap_waitrequest => open, ap_irq => ap_irq_s, -- async interrupt ap_asyncIrq => ap_asyncIrq_s, -- LED ledsOut => led_s, phyLink => phyLink, phyAct => phyAct, --PDI change buffer triggers rpdo_change_tog => rpdo_change_tog, tpdo_change_tog => tpdo_change_tog ); end generate genPdiSpi; -- ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ --SIMPLE I/O CN genSimpleIO : if genSimpleIO_g generate thePortIO : entity work.portio generic map ( pioValLen_g => pioValLen_g, pioGenIoBuf_g => genIoBuf_g ) port map ( s0_address => smp_address, s0_read => smp_read, s0_readdata => smp_readdata, s0_write => smp_write, s0_writedata => smp_writedata, s0_byteenable => smp_byteenable, s0_waitrequest => smp_waitrequest, clk => clkPcp, reset => rstPcp, x_pconfig => pio_pconfig, x_portInLatch => pio_portInLatch, x_portOutValid => pio_portOutValid, x_portio => pio_portio, x_portio_I => pio_portio_I, x_portio_O => pio_portio_O, x_portio_T => pio_portio_T, x_operational => pio_operational ); end generate genSimpleIO; -- ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ --OPENMAC (OPENHUB, OPENFILTER, PHY MANAGEMENT) theOpenMac : entity work.openMAC_Ethernet generic map ( endian_g => endian_g, dma_highadr_g => m_address'high, gen2ndCmpTimer_g => use2ndCmpTimer_g, genHub_g => use2ndPhy_g, iPktBufSizeLog2_g => iBufSizeLOG2_g, iPktBufSize_g => iBufSize_g, simulate => false, useIntPktBuf_g => useIntPacketBuf_g, useRmii_g => useRmii_g, useRxIntPktBuf_g => useRxIntPacketBuf_g, m_burstcount_width_g => m_burstcount_width_g, m_burstcount_const_g => m_burstcount_const_g, m_data_width_g => m_data_width_g, m_tx_fifo_size_g => m_tx_fifo_size_g, m_rx_fifo_size_g => m_rx_fifo_size_g, m_tx_burst_size_g => m_tx_burst_size_g, m_rx_burst_size_g => m_rx_burst_size_g, genSmiIO => genSmiIO, gNumSmi => gNumSmi, genPhyActLed_g => genLedGadget_g, gen_dma_observer_g => gen_dma_observer_g ) port map( clk => clk50, clkx2 => clkEth, pkt_clk => pkt_clk, m_clk => m_clk, rst => rst, m_address => m_address, m_burstcount => m_burstcount, m_burstcounter => m_burstcounter, m_byteenable => m_byteenable, m_read => m_read, m_readdata => m_readdata, m_readdatavalid => m_readdatavalid, m_write => m_write, m_writedata => m_writedata, m_waitrequest => m_waitrequest, mac_rx_irq => open, mac_tx_irq => open, act_led => phyAct(0), phy0_rst_n => phy0_Rst_n, phy0_rx_dat => phy0_RxDat, phy0_rx_dv => phy0_RxDv, phy0_rx_err => phy0_RxErr, phy0_smi_clk => phy0_SMICLK, phy0_smi_dio => phy0_SMIDat, phy0_smi_dio_I => phy0_SMIDat_I, phy0_smi_dio_O => phy0_SMIDat_O, phy0_smi_dio_T => phy0_SMIDat_T, phy0_tx_dat => phy0_TxDat, phy0_tx_en => phy0_TxEn, phy1_rst_n => phy1_Rst_n, phy1_rx_dat => phy1_RxDat, phy1_rx_dv => phy1_RxDv, phy1_rx_err => phy1_RxErr, phy1_smi_clk => phy1_SMICLK, phy1_smi_dio => phy1_SMIDat, phy1_smi_dio_I => phy1_SMIDat_I, phy1_smi_dio_O => phy1_SMIDat_O, phy1_smi_dio_T => phy1_SMIDat_T, phy1_tx_dat => phy1_TxDat, phy1_tx_en => phy1_TxEn, phyMii0_rx_clk => phyMii0_RxClk, phyMii0_rx_dat => phyMii0_RxDat, phyMii0_rx_dv => phyMii0_RxDv, phyMii0_rx_err => phyMii0_RxEr, phyMii0_tx_clk => phyMii0_TxClk, phyMii0_tx_dat => phyMii0_TxDat, phyMii0_tx_en => phyMii0_TxEn, phyMii1_rx_clk => phyMii1_RxClk, phyMii1_rx_dat => phyMii1_RxDat, phyMii1_rx_dv => phyMii1_RxDv, phyMii1_rx_err => phyMii1_RxEr, phyMii1_tx_clk => phyMii1_TxClk, phyMii1_tx_dat => phyMii1_TxDat, phyMii1_tx_en => phyMii1_TxEn, phy_rst_n => phy_Rst_n, phy_smi_clk => phy_SMIClk, phy_smi_dio_I => phy_SMIDat_I, phy_smi_dio_O => phy_SMIDat_O, phy_smi_dio_T => phy_SMIDat_T, phy_smi_dio => phy_SMIDat, pkt_address => mbf_address, pkt_byteenable => mbf_byteenable, pkt_chipselect => mbf_chipselect, pkt_read => mbf_read, pkt_readdata => mbf_readdata, pkt_waitrequest => mbf_waitrequest, pkt_write => mbf_write, pkt_writedata => mbf_writedata, s_address => mac_address, s_byteenable => mac_byteenable, s_chipselect => mac_chipselect, s_irq => mac_irq, s_read => mac_read, s_readdata => mac_readdata, s_waitrequest => mac_waitrequest, s_write => mac_write, s_writedata => mac_writedata, t_address => tcp_address, t_byteenable => tcp_byteenable, t_chipselect => tcp_chipselect, t_irq => tcp_irq, t_read => tcp_read, t_readdata => tcp_readdata, t_tog => irqToggle, t_waitrequest => tcp_waitrequest, t_write => tcp_write, t_writedata => tcp_writedata ); phyAct(1) <= phyAct(0); -- ------------------------------------------------------------------------------------------------------------------------ end rtl;
------------------------------------------------------------------------------------------------------------------------ -- POWERLINK IP-Core -- -- Copyright (C) 2010 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------------------------------------------------ -- Version History ------------------------------------------------------------------------------------------------------------------------ -- 2010-08-23 V0.01 zelenkaj First version -- 2010-09-13 V0.02 zelenkaj added selection Rmii / Mii -- 2010-10-18 V0.03 zelenkaj added selection Big/Little Endian (pdi_par) -- use bidirectional bus (pdi_par) -- 2010-11-23 V0.04 zelenkaj Added 2 GPIO signals to parallel interface -- Added Operational Flag to simple I/O interface -- Omitted T/RPDO descriptor sections in DPR -- Added generic to set duration of valid assertion (portio) -- 2010-11-29 V0.05 zelenkaj Added Big/Little Endian (pdi_spi) -- 2010-12-06 V0.06 zelenkaj Bugfix: ap_irq was not driven in SPI configuration -- 2011-01-10 V0.07 zelenkaj Added 2-stage sync to SPI input pins -- 2011-02-24 V0.08 zelenkaj minor changes (naming conventions Mii->SMI) -- 2011-03-14 V0.09 zelenkaj minor change, added generic for rx packet buffer location -- 2011-03-21 V0.10 zelenkaj clean up -- 2011-03-28 V0.20 zelenkaj Changed: Structure of Control/Status Register -- Added: LED -- Added: Events -- Added/Changed: Asynchronous buffer 2x Ping-Pong -- 2011-04-04 V0.21 zelenkaj parallel interface, sync moved to pdi_par -- minor: led_status is the official name -- 2011-04-26 V0.22 zelenkaj generic for clock domain selection -- 2011-04-28 V0.23 zelenkaj second cmp timer of openMAC is optinal by generic -- generic for second phy port of openMAC -- 2011-05-06 V0.24 zelenkaj some naming convention changes -- bug fix: use the RX_ER signal, it has important meaning! -- 2011-05-09 V0.25 zelenkaj Hardware Acceleration (HW ACC) added. -- 2011-07-23 V0.26 zelenkaj openFILTER enhanced by RxErr signal -- 2011-07-25 V0.27 zelenkaj LED gadget and asynchronous buffer optional -- 2011-08-08 V0.28 zelenkaj LED gadget enhancement -> added 8 general purpose outputs -- 2011-08-02 V1.00 zelenkaj exchanged Avalon interface with entity openMAC_Ethernet -- 2011-09-05 V1.01 zelenkaj SPI PDI missed to connect async irq to toplevel -- 2011-10-20 V1.02 zelenkaj SMI export of in, out and tristate, endian generic -- 2011-11-07 V1.03 zelenkaj dma generic for PLB/AXI support necessary -- 2011-11-21 V1.04 zelenkaj added time synchronization feature -- 2011-11-28 V1.05 zelenkaj added waitrequest signals to pdi pcp/ap -- 2011-11-29 V1.06 zelenkaj event is optional -- 2011-11-30 V1.07 zelenkaj Added generic for DMA observer -- 2011-12-02 V1.08 zelenkaj Added I, O and T instead of IO ports -- 2012-01-09 V1.09 zelenkaj Added ap_syncIrq for external AP -- 2012-01-26 V1.10 zelenkaj Added generic for SMI generation and one SMI ports -- Omit hwacc options, since we are fast enough! ------------------------------------------------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity powerlink is generic( -- GENERAL GENERICS -- endian_g : string := "little"; genOnePdiClkDomain_g : boolean := false; genPdi_g : boolean := true; genInternalAp_g : boolean := true; genSimpleIO_g : boolean := false; genSpiAp_g : boolean := false; -- OPENMAC GENERICS Simulate : boolean := false; iBufSize_g : integer := 1024; iBufSizeLOG2_g : integer := 10; useRmii_g : boolean := true; --use Rmii useIntPacketBuf_g : boolean := true; --internal packet buffer useRxIntPacketBuf_g : boolean := true; --rx buffer located in internal packet buffer use2ndCmpTimer_g : boolean := true; --use second cmp timer (used in PDI) use2ndPhy_g : boolean := true; --use second phy (introduces openHUB) m_burstcount_width_g : integer := 4; m_burstcount_const_g : boolean := true; --hold burst value during transfer m_tx_burst_size_g : integer := 16; --0 < x =< 2**m_burstcount_width_g m_rx_burst_size_g : integer := 16; --0 < x =< 2**m_burstcount_width_g m_tx_fifo_size_g : integer := 16; m_rx_fifo_size_g : integer := 16; m_data_width_g : integer := 16; gen_dma_observer_g : boolean := true; genSmiIO : boolean := true; --drive SMI IO if true gNumSmi : integer range 1 to 2 := 2; --number of SMI used -- PDI GENERICS iRpdos_g : integer := 3; iTpdos_g : integer := 1; genABuf1_g : boolean := true; --if false iABuf1_g must be set to 0! genABuf2_g : boolean := true; --if false iABuf2_g must be set to 0! genLedGadget_g : boolean := false; genTimeSync_g : boolean := false; genEvent_g : boolean := false; --PDO buffer size *3 iTpdoBufSize_g : integer := 100; iRpdo0BufSize_g : integer := 100; iRpdo1BufSize_g : integer := 100; iRpdo2BufSize_g : integer := 100; --asynchronous buffer size iAsyBuf1Size_g : integer := 100; iAsyBuf2Size_g : integer := 100; iPdiRev_g : integer := 16#55AA#; -- 8/16bit PARALLEL PDI GENERICS papDataWidth_g : integer := 8; papLowAct_g : boolean := false; papBigEnd_g : boolean := false; -- SPI GENERICS spiCPOL_g : boolean := false; spiCPHA_g : boolean := false; spiBigEnd_g : boolean := false; -- PORTIO pioValLen_g : integer := 50; --clock ticks of pcp_clk -- GENERAL TARGET DEPENDINGS genIoBuf_g : boolean := true --generates IO buffers ); port( -- CLOCK / RESET PORTS clk50 : in std_logic; --RMII clk rst : in std_logic; --general reset clkEth : in std_logic; --Tx Reg clk m_clk : in std_logic; --openMAC DMA master clock pkt_clk : in std_logic; --openMAC packet buffer clock (don't use pcp..) clkPcp : in std_logic; --pcp clk clkAp : in std_logic; --ap clk rstPcp : in std_logic; --rst from pcp side rstAp : in std_logic; --rst ap -- OPENMAC --- OPENMAC PORTS mac_chipselect : in std_logic; mac_read : in std_logic; mac_write : in std_logic; mac_byteenable : in std_logic_vector(1 downto 0); mac_address : in std_logic_vector(11 downto 0); mac_writedata : in std_logic_vector(15 downto 0); mac_readdata : out std_logic_vector(15 downto 0) := (others => '0'); mac_waitrequest : out std_logic; mac_irq : out std_logic := '0'; --- TIMER COMPARE PORTS tcp_chipselect : in std_logic; tcp_read : in std_logic; tcp_write : in std_logic; tcp_byteenable : in std_logic_vector(3 downto 0); tcp_address : in std_logic_vector(1 downto 0); tcp_writedata : in std_logic_vector(31 downto 0); tcp_readdata : out std_logic_vector(31 downto 0) := (others => '0'); tcp_waitrequest : out std_logic; tcp_irq : out std_logic := '0'; --- MAC BUFFER PORTS mbf_chipselect : in std_logic; mbf_read : in std_logic; mbf_write : in std_logic; mbf_byteenable : in std_logic_vector(3 downto 0); mbf_address : in std_logic_vector(ibufsizelog2_g-3 downto 0); mbf_writedata : in std_logic_vector(31 downto 0); mbf_readdata : out std_logic_vector(31 downto 0) := (others => '0'); mbf_waitrequest : out std_logic; --- OPENMAC DMA PORTS m_read : OUT STD_LOGIC := '0'; m_write : OUT STD_LOGIC := '0'; m_byteenable : OUT STD_LOGIC_VECTOR(m_data_width_g/8-1 DOWNTO 0) := (others => '0'); m_address : OUT STD_LOGIC_VECTOR(29 DOWNTO 0) := (others => '0'); m_writedata : OUT STD_LOGIC_VECTOR(m_data_width_g-1 DOWNTO 0) := (others => '0'); m_readdata : IN STD_LOGIC_VECTOR(m_data_width_g-1 DOWNTO 0) := (others => '0'); m_waitrequest : IN STD_LOGIC; m_readdatavalid : in STD_LOGIC := '0'; m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0); m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0); -- PDI --- PCP PORTS pcp_chipselect : in std_logic; pcp_read : in std_logic; pcp_write : in std_logic; pcp_byteenable : in std_logic_vector(3 downto 0); pcp_address : in std_logic_vector(12 downto 0); pcp_writedata : in std_logic_vector(31 downto 0); pcp_readdata : out std_logic_vector(31 downto 0) := (others => '0'); pcp_waitrequest : out std_logic; --- AP PORTS ap_irq : out std_logic := '0'; ap_irq_n : out std_logic := '1'; ap_syncIrq : out std_logic := '0'; ap_syncIrq_n : out std_logic := '1'; ap_asyncIrq : out std_logic := '0'; ap_asyncIrq_n : out std_logic := '1'; ---- AVALON ap_chipselect : in std_logic; ap_read : in std_logic; ap_write : in std_logic; ap_byteenable : in std_logic_vector(3 downto 0); ap_address : in std_logic_vector(12 downto 0); ap_writedata : in std_logic_vector(31 downto 0); ap_readdata : out std_logic_vector(31 downto 0) := (others => '0'); ap_waitrequest : out std_logic; ---- 8/16bit parallel pap_cs : in std_logic; pap_rd : in std_logic; pap_wr : in std_logic; pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0); pap_cs_n : in std_logic; pap_rd_n : in std_logic; pap_wr_n : in std_logic; pap_be_n : in std_logic_vector(papDataWidth_g/8-1 downto 0); pap_addr : in std_logic_vector(15 downto 0); pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0'); pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0'); pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0); pap_data_T : out std_logic; pap_ack : out std_logic := '0'; pap_ack_n : out std_logic := '1'; pap_gpio : inout std_logic_vector(1 downto 0) := (others => '0'); pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0'); pap_gpio_O : out std_logic_vector(1 downto 0); pap_gpio_T : out std_logic_vector(1 downto 0); ---- SPI spi_clk : in std_logic; spi_sel_n : in std_logic; spi_mosi : in std_logic; spi_miso : out std_logic := '0'; ---- simple I/O smp_address : in std_logic; smp_read : in std_logic; smp_readdata : out std_logic_vector(31 downto 0) := (others => '0'); smp_write : in std_logic; smp_writedata : in std_logic_vector(31 downto 0); smp_byteenable : in std_logic_vector(3 downto 0); smp_waitrequest : out std_logic; pio_pconfig : in std_logic_vector(3 downto 0); pio_portInLatch : in std_logic_vector(3 downto 0); pio_portOutValid : out std_logic_vector(3 downto 0) := (others => '0'); pio_portio : inout std_logic_vector(31 downto 0) := (others => '0'); pio_portio_I : in std_logic_vector(31 downto 0) := (others => '0'); pio_portio_O : out std_logic_vector(31 downto 0); pio_portio_T : out std_logic_vector(31 downto 0); pio_operational : out std_logic := '0'; -- EXTERNAL --- PHY MANAGEMENT ---- shared (valid if gNumSmi = 1) phy_SMIClk : out std_logic := '0'; phy_SMIDat : inout std_logic := '1'; phy_SMIDat_I : in std_logic := '1'; phy_SMIDat_O : out std_logic; phy_SMIDat_T : out std_logic; phy_Rst_n : out std_logic := '1'; ---- PHY0 (valid if gNumSmi = 2) phy0_SMIClk : out std_logic := '0'; phy0_SMIDat : inout std_logic := '1'; phy0_SMIDat_I : in std_logic := '1'; phy0_SMIDat_O : out std_logic; phy0_SMIDat_T : out std_logic; phy0_Rst_n : out std_logic := '1'; phy0_link : in std_logic := '0'; ---- PHY1 (valid if gNumSmi = 2) phy1_SMIClk : out std_logic := '0'; phy1_SMIDat : inout std_logic := '1'; phy1_SMIDat_I : in std_logic := '1'; phy1_SMIDat_O : out std_logic; phy1_SMIDat_T : out std_logic; phy1_Rst_n : out std_logic := '1'; phy1_link : in std_logic := '0'; --- RMII PORTS phy0_RxDat : in std_logic_vector(1 downto 0); phy0_RxDv : in std_logic; phy0_RxErr : in std_logic; phy0_TxDat : out std_logic_vector(1 downto 0) := (others => '0'); phy0_TxEn : out std_logic := '0'; phy1_RxDat : in std_logic_vector(1 downto 0) := (others => '0'); phy1_RxDv : in std_logic; phy1_RxErr : in std_logic; phy1_TxDat : out std_logic_vector(1 downto 0) := (others => '0'); phy1_TxEn : out std_logic := '0'; --- MII PORTS phyMii0_RxClk : in std_logic; phyMii0_RxDat : in std_logic_vector(3 downto 0) := (others => '0'); phyMii0_RxDv : in std_logic; phyMii0_RxEr : in std_logic; phyMii0_TxClk : in std_logic; phyMii0_TxDat : out std_logic_vector(3 downto 0) := (others => '0'); phyMii0_TxEn : out std_logic := '0'; phyMii0_TxEr : out std_logic := '0'; phyMii1_RxClk : in std_logic; phyMii1_RxDat : in std_logic_vector(3 downto 0) := (others => '0'); phyMii1_RxDv : in std_logic; phyMii1_RxEr : in std_logic; phyMii1_TxClk : in std_logic; phyMii1_TxDat : out std_logic_vector(3 downto 0) := (others => '0'); phyMii1_TxEn : out std_logic := '0'; phyMii1_TxEr : out std_logic := '0'; --- LEDs led_error : out std_logic := '0'; led_status : out std_logic := '0'; led_phyLink : out std_logic_vector(1 downto 0) := (others => '0'); led_phyAct : out std_logic_vector(1 downto 0) := (others => '0'); led_opt : out std_logic_vector(1 downto 0) := (others => '0'); led_gpo : out std_logic_vector(7 downto 0) := (others => '0') ); end powerlink; architecture rtl of powerlink is signal smi_Clk : std_logic := '0'; signal smi_Di : std_logic := '0'; signal smi_Do : std_logic := '0'; signal smi_Doe : std_logic := '0'; signal phy_nResetOut : std_logic := '0'; signal irqToggle : std_logic := '0'; signal ap_chipselect_s : std_logic := '0'; signal ap_read_s : std_logic := '0'; signal ap_write_s : std_logic := '0'; signal ap_byteenable_s : std_logic_vector(ap_byteenable'range) := (others => '0'); signal ap_address_s : std_logic_vector(ap_address'range) := (others => '0'); signal ap_writedata_s : std_logic_vector(ap_writedata'range):= (others => '0'); signal ap_readdata_s : std_logic_vector(ap_readdata'range) := (others => '0'); signal pap_cs_s : std_logic; signal pap_rd_s : std_logic; signal pap_wr_s : std_logic; signal pap_be_s : std_logic_vector(pap_be'range); signal pap_ack_s : std_logic; signal ap_irq_s : std_logic; signal ap_asyncIrq_s : std_logic; signal spi_sel_s : std_logic; signal spi_sel_s1 : std_logic; signal spi_sel_s2 : std_logic; signal spi_clk_s : std_logic; signal spi_clk_s1 : std_logic; signal spi_clk_s2 : std_logic; signal spi_mosi_s : std_logic; signal spi_mosi_s1 : std_logic; signal spi_mosi_s2 : std_logic; signal phyLink, phyAct : std_logic_vector(1 downto 0); signal led_s : std_logic_vector(15 downto 0); signal clkAp_s, rstAp_s : std_logic; --PDI change buffer triggers for hw acc to pdi signal rpdo_change_tog : std_logic_vector(2 downto 0); signal tpdo_change_tog : std_logic; begin --general signals clkAp_s <= clkAp when genOnePdiClkDomain_g = FALSE else clkPcp; rstAp_s <= rstAp when genOnePdiClkDomain_g = FALSE else rstPcp; phyLink <= phy1_link & phy0_link; --LEDs: GPO7, ..., GPO0, O1, O0, PA1, PL1, PA0, PL0, E, S led_error <= led_s(1); led_status <= led_s(0); led_phyLink <= led_s(4) & led_s(2); led_phyAct <= led_s(5) & led_s(3); led_opt <= led_s(7) & led_s(6); led_gpo <= led_s(15 downto 8); ------------------------------------------------------------------------------------------------------------------------ --PCP + AP genPdi : if genPdi_g and genInternalAp_g and not genSpiAp_g generate --sync and async interrupt are driven by only one line -- this gives some effort for Nios II AP ;) ap_irq <= ap_irq_s or ap_asyncIrq_s; theAvalonPdi : entity work.pdi generic map ( genOnePdiClkDomain_g => genOnePdiClkDomain_g, iPdiRev_g => iPdiRev_g, iRpdos_g => iRpdos_g, iTpdos_g => iTpdos_g, genABuf1_g => genABuf1_g, genABuf2_g => genABuf2_g, genLedGadget_g => genLedGadget_g, genTimeSync_g => genTimeSync_g, genEvent_g => genEvent_g, --PDO buffer size *3 iTpdoBufSize_g => iTpdoBufSize_g, iRpdo0BufSize_g => iRpdo0BufSize_g, iRpdo1BufSize_g => iRpdo1BufSize_g, iRpdo2BufSize_g => iRpdo2BufSize_g, --asynchronous buffer size iABuf1_g => iAsyBuf1Size_g, iABuf2_g => iAsyBuf2Size_g ) port map ( pcp_reset => rstPcp, pcp_clk => clkPcp, ap_reset => rstAp_s, ap_clk => clkAp_s, -- Avalon Slave Interface for PCP pcp_chipselect => pcp_chipselect, pcp_read => pcp_read, pcp_write => pcp_write, pcp_byteenable => pcp_byteenable, pcp_address => pcp_address, pcp_writedata => pcp_writedata, pcp_readdata => pcp_readdata, pcp_waitrequest => pcp_waitrequest, pcp_irq => irqToggle, -- Avalon Slave Interface for AP ap_chipselect => ap_chipselect, ap_read => ap_read, ap_write => ap_write, ap_byteenable => ap_byteenable, ap_address => ap_address, ap_writedata => ap_writedata, ap_readdata => ap_readdata, ap_waitrequest => ap_waitrequest, ap_irq => ap_irq_s, -- async interrupt ap_asyncIrq => ap_asyncIrq_s, -- LED ledsOut => led_s, phyLink => phyLink, phyAct => phyAct, --PDI change buffer triggers rpdo_change_tog => rpdo_change_tog, tpdo_change_tog => tpdo_change_tog ); end generate genPdi; --AP is external connected via parallel interface genPdiPar : if genPdi_g and not genInternalAp_g and not genSpiAp_g generate --only 8 or 16bit data width is allowed ASSERT ( papDataWidth_g = 8 or papDataWidth_g = 16 ) REPORT "External parallel port only allows 8 or 16bit data width!" severity failure; ------------------------------------------------------------------------------------- --convert active low signals to active high - respectively assign active high signals theActiveLowGen : if papLowAct_g generate pap_wr_s <= not pap_wr_n; pap_rd_s <= not pap_rd_n; pap_cs_s <= not pap_cs_n; pap_be_s <= not pap_be_n; end generate; theActiveHighGen : if not papLowAct_g generate pap_wr_s <= pap_wr; pap_rd_s <= pap_rd; pap_cs_s <= pap_cs; pap_be_s <= pap_be; end generate; ap_syncIrq <= ap_irq_s; ap_syncIrq_n <= not ap_irq_s; ap_asyncIrq <= ap_asyncIrq_s; ap_asyncIrq_n <= not ap_asyncIrq_s; pap_ack <= pap_ack_s; pap_ack_n <= not pap_ack_s; -- ------------------------------------------------------------------------------------- theParPort : entity work.pdi_par generic map ( papDataWidth_g => papDataWidth_g, papBigEnd_g => papBigEnd_g, papGenIoBuf_g => genIoBuf_g ) port map ( -- 8/16bit parallel pap_cs => pap_cs_s, pap_rd => pap_rd_s, pap_wr => pap_wr_s, pap_be => pap_be_s, pap_addr => pap_addr, pap_data => pap_data, pap_data_I => pap_data_I, pap_data_O => pap_data_O, pap_data_T => pap_data_T, pap_ack => pap_ack_s, pap_gpio => pap_gpio, pap_gpio_I => pap_gpio_I, pap_gpio_O => pap_gpio_O, pap_gpio_T => pap_gpio_T, -- clock for AP side ap_reset => rstPcp, ap_clk => clk50, -- Avalon Slave Interface for AP ap_chipselect => ap_chipselect_s, ap_read => ap_read_s, ap_write => ap_write_s, ap_byteenable => ap_byteenable_s, ap_address => ap_address_s, ap_writedata => ap_writedata_s, ap_readdata => ap_readdata_s ); thePdi : entity work.pdi generic map ( genOnePdiClkDomain_g => genOnePdiClkDomain_g, iPdiRev_g => iPdiRev_g, iRpdos_g => iRpdos_g, iTpdos_g => iTpdos_g, genABuf1_g => genABuf1_g, genABuf2_g => genABuf2_g, genLedGadget_g => genLedGadget_g, genTimeSync_g => genTimeSync_g, genEvent_g => genEvent_g, --PDO buffer size *3 iTpdoBufSize_g => iTpdoBufSize_g, iRpdo0BufSize_g => iRpdo0BufSize_g, iRpdo1BufSize_g => iRpdo1BufSize_g, iRpdo2BufSize_g => iRpdo2BufSize_g, --asynchronous buffer size iABuf1_g => iAsyBuf1Size_g, iABuf2_g => iAsyBuf2Size_g ) port map ( pcp_reset => rstPcp, pcp_clk => clkPcp, ap_reset => rst, ap_clk => clk50, -- Avalon Slave Interface for PCP pcp_chipselect => pcp_chipselect, pcp_read => pcp_read, pcp_write => pcp_write, pcp_byteenable => pcp_byteenable, pcp_address => pcp_address, pcp_writedata => pcp_writedata, pcp_readdata => pcp_readdata, pcp_waitrequest => pcp_waitrequest, pcp_irq => irqToggle, -- Avalon Slave Interface for AP ap_chipselect => ap_chipselect_s, ap_read => ap_read_s, ap_write => ap_write_s, ap_byteenable => ap_byteenable_s, ap_address => ap_address_s, ap_writedata => ap_writedata_s, ap_readdata => ap_readdata_s, ap_waitrequest => open, ap_irq => ap_irq_s, -- async interrupt ap_asyncIrq => ap_asyncIrq_s, -- LED ledsOut => led_s, phyLink => phyLink, phyAct => phyAct, --PDI change buffer triggers rpdo_change_tog => rpdo_change_tog, tpdo_change_tog => tpdo_change_tog ); end generate genPdiPar; --AP is extern connected via SPI genPdiSpi : if genPdi_g and genSpiAp_g generate ap_syncIrq <= ap_irq_s; ap_syncIrq_n <= not ap_irq_s; ap_asyncIrq <= ap_asyncIrq_s; ap_asyncIrq_n <= not ap_asyncIrq_s; spi_clk_s <= spi_clk; spi_sel_s <= not spi_sel_n; spi_mosi_s <= spi_mosi; theSyncProc : process(clk50, rst) begin if rst = '1' then spi_sel_s1 <= '0'; spi_sel_s2 <= '0'; spi_clk_s1 <= '0'; spi_clk_s2 <= '0'; spi_mosi_s1 <= '0'; spi_mosi_s2 <= '0'; elsif clk50 = '1' and clk50'event then spi_sel_s1 <= spi_sel_s; spi_sel_s2 <= spi_sel_s1; spi_clk_s1 <= spi_clk_s; spi_clk_s2 <= spi_clk_s1; spi_mosi_s1 <= spi_mosi_s; spi_mosi_s2 <= spi_mosi_s1; end if; end process; ------------------------------------------------------------------------------------------------------------------------ thePdiSpi : entity work.pdi_spi generic map ( spiSize_g => 8, --fixed value! cpol_g => spiCPOL_g, cpha_g => spiCPHA_g, spiBigEnd_g => spiBigEnd_g ) port map ( -- SPI spi_clk => spi_clk_s2, spi_sel => spi_sel_s2, spi_miso => spi_miso, spi_mosi => spi_mosi_s2, -- clock for AP side ap_reset => rstPcp, ap_clk => clk50, -- Avalon Slave Interface for AP ap_chipselect => ap_chipselect_s, ap_read => ap_read_s, ap_write => ap_write_s, ap_byteenable => ap_byteenable_s, ap_address => ap_address_s, ap_writedata => ap_writedata_s, ap_readdata => ap_readdata_s ); thePdi : entity work.pdi generic map ( genOnePdiClkDomain_g => genOnePdiClkDomain_g, iPdiRev_g => iPdiRev_g, iRpdos_g => iRpdos_g, iTpdos_g => iTpdos_g, genABuf1_g => genABuf1_g, genABuf2_g => genABuf2_g, genLedGadget_g => genLedGadget_g, genTimeSync_g => genTimeSync_g, genEvent_g => genEvent_g, --PDO buffer size *3 iTpdoBufSize_g => iTpdoBufSize_g, iRpdo0BufSize_g => iRpdo0BufSize_g, iRpdo1BufSize_g => iRpdo1BufSize_g, iRpdo2BufSize_g => iRpdo2BufSize_g, --asynchronous buffer size iABuf1_g => iAsyBuf1Size_g, iABuf2_g => iAsyBuf2Size_g ) port map ( pcp_reset => rstPcp, pcp_clk => clkPcp, ap_reset => rst, ap_clk => clk50, -- Avalon Slave Interface for PCP pcp_chipselect => pcp_chipselect, pcp_read => pcp_read, pcp_write => pcp_write, pcp_byteenable => pcp_byteenable, pcp_address => pcp_address, pcp_writedata => pcp_writedata, pcp_readdata => pcp_readdata, pcp_waitrequest => pcp_waitrequest, pcp_irq => irqToggle, -- Avalon Slave Interface for AP ap_chipselect => ap_chipselect_s, ap_read => ap_read_s, ap_write => ap_write_s, ap_byteenable => ap_byteenable_s, ap_address => ap_address_s, ap_writedata => ap_writedata_s, ap_readdata => ap_readdata_s, ap_waitrequest => open, ap_irq => ap_irq_s, -- async interrupt ap_asyncIrq => ap_asyncIrq_s, -- LED ledsOut => led_s, phyLink => phyLink, phyAct => phyAct, --PDI change buffer triggers rpdo_change_tog => rpdo_change_tog, tpdo_change_tog => tpdo_change_tog ); end generate genPdiSpi; -- ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ --SIMPLE I/O CN genSimpleIO : if genSimpleIO_g generate thePortIO : entity work.portio generic map ( pioValLen_g => pioValLen_g, pioGenIoBuf_g => genIoBuf_g ) port map ( s0_address => smp_address, s0_read => smp_read, s0_readdata => smp_readdata, s0_write => smp_write, s0_writedata => smp_writedata, s0_byteenable => smp_byteenable, s0_waitrequest => smp_waitrequest, clk => clkPcp, reset => rstPcp, x_pconfig => pio_pconfig, x_portInLatch => pio_portInLatch, x_portOutValid => pio_portOutValid, x_portio => pio_portio, x_portio_I => pio_portio_I, x_portio_O => pio_portio_O, x_portio_T => pio_portio_T, x_operational => pio_operational ); end generate genSimpleIO; -- ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ --OPENMAC (OPENHUB, OPENFILTER, PHY MANAGEMENT) theOpenMac : entity work.openMAC_Ethernet generic map ( endian_g => endian_g, dma_highadr_g => m_address'high, gen2ndCmpTimer_g => use2ndCmpTimer_g, genHub_g => use2ndPhy_g, iPktBufSizeLog2_g => iBufSizeLOG2_g, iPktBufSize_g => iBufSize_g, simulate => false, useIntPktBuf_g => useIntPacketBuf_g, useRmii_g => useRmii_g, useRxIntPktBuf_g => useRxIntPacketBuf_g, m_burstcount_width_g => m_burstcount_width_g, m_burstcount_const_g => m_burstcount_const_g, m_data_width_g => m_data_width_g, m_tx_fifo_size_g => m_tx_fifo_size_g, m_rx_fifo_size_g => m_rx_fifo_size_g, m_tx_burst_size_g => m_tx_burst_size_g, m_rx_burst_size_g => m_rx_burst_size_g, genSmiIO => genSmiIO, gNumSmi => gNumSmi, genPhyActLed_g => genLedGadget_g, gen_dma_observer_g => gen_dma_observer_g ) port map( clk => clk50, clkx2 => clkEth, pkt_clk => pkt_clk, m_clk => m_clk, rst => rst, m_address => m_address, m_burstcount => m_burstcount, m_burstcounter => m_burstcounter, m_byteenable => m_byteenable, m_read => m_read, m_readdata => m_readdata, m_readdatavalid => m_readdatavalid, m_write => m_write, m_writedata => m_writedata, m_waitrequest => m_waitrequest, mac_rx_irq => open, mac_tx_irq => open, act_led => phyAct(0), phy0_rst_n => phy0_Rst_n, phy0_rx_dat => phy0_RxDat, phy0_rx_dv => phy0_RxDv, phy0_rx_err => phy0_RxErr, phy0_smi_clk => phy0_SMICLK, phy0_smi_dio => phy0_SMIDat, phy0_smi_dio_I => phy0_SMIDat_I, phy0_smi_dio_O => phy0_SMIDat_O, phy0_smi_dio_T => phy0_SMIDat_T, phy0_tx_dat => phy0_TxDat, phy0_tx_en => phy0_TxEn, phy1_rst_n => phy1_Rst_n, phy1_rx_dat => phy1_RxDat, phy1_rx_dv => phy1_RxDv, phy1_rx_err => phy1_RxErr, phy1_smi_clk => phy1_SMICLK, phy1_smi_dio => phy1_SMIDat, phy1_smi_dio_I => phy1_SMIDat_I, phy1_smi_dio_O => phy1_SMIDat_O, phy1_smi_dio_T => phy1_SMIDat_T, phy1_tx_dat => phy1_TxDat, phy1_tx_en => phy1_TxEn, phyMii0_rx_clk => phyMii0_RxClk, phyMii0_rx_dat => phyMii0_RxDat, phyMii0_rx_dv => phyMii0_RxDv, phyMii0_rx_err => phyMii0_RxEr, phyMii0_tx_clk => phyMii0_TxClk, phyMii0_tx_dat => phyMii0_TxDat, phyMii0_tx_en => phyMii0_TxEn, phyMii1_rx_clk => phyMii1_RxClk, phyMii1_rx_dat => phyMii1_RxDat, phyMii1_rx_dv => phyMii1_RxDv, phyMii1_rx_err => phyMii1_RxEr, phyMii1_tx_clk => phyMii1_TxClk, phyMii1_tx_dat => phyMii1_TxDat, phyMii1_tx_en => phyMii1_TxEn, phy_rst_n => phy_Rst_n, phy_smi_clk => phy_SMIClk, phy_smi_dio_I => phy_SMIDat_I, phy_smi_dio_O => phy_SMIDat_O, phy_smi_dio_T => phy_SMIDat_T, phy_smi_dio => phy_SMIDat, pkt_address => mbf_address, pkt_byteenable => mbf_byteenable, pkt_chipselect => mbf_chipselect, pkt_read => mbf_read, pkt_readdata => mbf_readdata, pkt_waitrequest => mbf_waitrequest, pkt_write => mbf_write, pkt_writedata => mbf_writedata, s_address => mac_address, s_byteenable => mac_byteenable, s_chipselect => mac_chipselect, s_irq => mac_irq, s_read => mac_read, s_readdata => mac_readdata, s_waitrequest => mac_waitrequest, s_write => mac_write, s_writedata => mac_writedata, t_address => tcp_address, t_byteenable => tcp_byteenable, t_chipselect => tcp_chipselect, t_irq => tcp_irq, t_read => tcp_read, t_readdata => tcp_readdata, t_tog => irqToggle, t_waitrequest => tcp_waitrequest, t_write => tcp_write, t_writedata => tcp_writedata ); phyAct(1) <= phyAct(0); -- ------------------------------------------------------------------------------------------------------------------------ end rtl;
-- median_filter.vhd -- Jan Viktorin <[email protected]> -- Copyright (C) 2011, 2012 Jan Viktorin library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library utils_v1_00_a; use utils_v1_00_a.ctl_bypass; --- -- Performs median filtering on RGB window bus. The window -- must be create by another unit. Median filter sorts the -- values in the window and outputs its median. --- entity median_filter is generic ( MATRIX_SIZE : integer := 3 ); port ( CLK : in std_logic; CE : in std_logic; WIN_R : in std_logic_vector((MATRIX_SIZE ** 2) * 8 - 1 downto 0); WIN_G : in std_logic_vector((MATRIX_SIZE ** 2) * 8 - 1 downto 0); WIN_B : in std_logic_vector((MATRIX_SIZE ** 2) * 8 - 1 downto 0); WIN_DE : in std_logic_vector((MATRIX_SIZE ** 2) - 1 downto 0); WIN_HS : in std_logic_vector((MATRIX_SIZE ** 2) - 1 downto 0); WIN_VS : in std_logic_vector((MATRIX_SIZE ** 2) - 1 downto 0); OUT_R : out std_logic_vector(7 downto 0); OUT_G : out std_logic_vector(7 downto 0); OUT_B : out std_logic_vector(7 downto 0); OUT_DE : out std_logic; OUT_HS : out std_logic; OUT_VS : out std_logic ); end entity; --- -- Implementation uses unit median9 with bitonic sorter. -- It does not care about the borders it just uses the -- incoming values. Thus the unit can be improved by -- using eg. zero values on window fields with DE = '0'. -- -- This implementation is for 3x3 windows only. --- architecture median9_filter of median_filter is signal median_r : std_logic_vector(7 downto 0); signal median_g : std_logic_vector(7 downto 0); signal median_b : std_logic_vector(7 downto 0); begin median_r_i : entity work.median9 port map ( CLK => CLK, CE => CE, DI => WIN_R, DO => median_r ); median_g_i : entity work.median9 port map ( CLK => CLK, CE => CE, DI => WIN_G, DO => median_g ); median_b_i : entity work.median9 port map ( CLK => CLK, CE => CE, DI => WIN_B, DO => median_b ); ctl_bypass_i : entity utils_v1_00_a.ctl_bypass generic map ( DWIDTH => 3, DEPTH => 8 ) port map ( CLK => CLK, CE => CE, DI(0) => WIN_DE(4), DI(1) => WIN_HS(4), DI(2) => WIN_VS(4), DO(0) => OUT_DE, DO(1) => OUT_HS, DO(2) => OUT_VS ); OUT_R <= median_r; OUT_G <= median_g; OUT_B <= median_b; end architecture;
entity array1 is end entity; architecture test of array1 is type matrix_t is array (integer range <>, integer range <>) of integer; constant c : matrix_t(0 to 1, 0 to 1) := ( ( 1, 2 ), ( 3, 4 ) ); begin process is variable m : matrix_t(1 to 3, 1 to 3) := ( ( 1, 2, 3 ), ( 4, 5, 6 ), ( 7, 8, 9 ) ); begin report integer'image(m(1, 3)); report integer'image(m(2, 2)); assert m(2, 2) = 5; assert m(3, 1) = 7; report integer'image(c(1, 0)); assert c(1, 0) = 3; wait; end process; end architecture;
entity array1 is end entity; architecture test of array1 is type matrix_t is array (integer range <>, integer range <>) of integer; constant c : matrix_t(0 to 1, 0 to 1) := ( ( 1, 2 ), ( 3, 4 ) ); begin process is variable m : matrix_t(1 to 3, 1 to 3) := ( ( 1, 2, 3 ), ( 4, 5, 6 ), ( 7, 8, 9 ) ); begin report integer'image(m(1, 3)); report integer'image(m(2, 2)); assert m(2, 2) = 5; assert m(3, 1) = 7; report integer'image(c(1, 0)); assert c(1, 0) = 3; wait; end process; end architecture;
entity array1 is end entity; architecture test of array1 is type matrix_t is array (integer range <>, integer range <>) of integer; constant c : matrix_t(0 to 1, 0 to 1) := ( ( 1, 2 ), ( 3, 4 ) ); begin process is variable m : matrix_t(1 to 3, 1 to 3) := ( ( 1, 2, 3 ), ( 4, 5, 6 ), ( 7, 8, 9 ) ); begin report integer'image(m(1, 3)); report integer'image(m(2, 2)); assert m(2, 2) = 5; assert m(3, 1) = 7; report integer'image(c(1, 0)); assert c(1, 0) = 3; wait; end process; end architecture;
entity array1 is end entity; architecture test of array1 is type matrix_t is array (integer range <>, integer range <>) of integer; constant c : matrix_t(0 to 1, 0 to 1) := ( ( 1, 2 ), ( 3, 4 ) ); begin process is variable m : matrix_t(1 to 3, 1 to 3) := ( ( 1, 2, 3 ), ( 4, 5, 6 ), ( 7, 8, 9 ) ); begin report integer'image(m(1, 3)); report integer'image(m(2, 2)); assert m(2, 2) = 5; assert m(3, 1) = 7; report integer'image(c(1, 0)); assert c(1, 0) = 3; wait; end process; end architecture;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1348.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s04b01x00p07n01i01348ent IS END c08s04b01x00p07n01i01348ent; ARCHITECTURE c08s04b01x00p07n01i01348arch OF c08s04b01x00p07n01i01348ent IS -- Local signals. signal S : BIT := '0'; BEGIN TESTING: PROCESS -- local variables. variable S_INITIAL : BIT; variable ShouldBeTime : TIME; variable k : integer := 0; BEGIN -- 0. Keep around the initial value of S. S_INITIAL := S; -- 1. When no preemption necessary, verify the results. S <= transport (not S) after 10 ns, (S) after 20 ns; -- a. Wait for first transaction. ShouldBeTime := NOW + 10 ns; wait on S; if (ShouldBeTime /= now or S /= not S_INITIAL) then k := 1; end if; assert (ShouldBeTime = NOW); assert (S = (not S_INITIAL)); -- b. Wait for second transaction. ShouldBeTime := NOW + 10 ns; wait on S; assert (ShouldBeTime = NOW); assert (S = S_INITIAL); -- 2. Preempt a transaction which is to occur at the same time as second one. S_INITIAL := S; S <= transport (S) after 10 ns; S <= transport (not S) after 10 ns; -- Should preempt first transaction. -- a. Verify that the second transaction comes as expected. ShouldBeTime := NOW + 10 ns; wait on S; if (ShouldBeTime /= now or S /= not S_INITIAL) then k := 1; end if; assert (ShouldBeTime = NOW); assert (S = (not S_INITIAL)); -- b. Verify that the first transaction has been preempted. ShouldBeTime := NOW + 10 ns; wait on S for 10 ns; if (ShouldBeTime /= now) then k := 1; end if; assert (ShouldBeTime = NOW); -- 3. Preempt a transaction which is to occur at a later time than second one. S_INITIAL := S; S <= transport (S) after 15 ns; S <= transport (not S) after 10 ns; -- Should preempt first transaction. -- a. Verify that the second transaction comes as expected. ShouldBeTime := NOW + 10 ns; wait on S; if (ShouldBeTime /= now or S /= not S_INITIAL) then k := 1; end if; assert (ShouldBeTime = NOW); assert (S = (not S_INITIAL)); -- b. Verify that the first transaction has been preempted. ShouldBeTime := NOW + 10 ns; wait on S for 10 ns; if (ShouldBeTime /= now) then k := 1; end if; assert (ShouldBeTime = NOW); -- 4. Preempt multiple transactions. S_INITIAL := S; S <= transport (S) after 15 ns, (not S) after 30 ns; S <= transport (not S) after 10 ns, (S) after 20 ns; -- a. Verify that the second transactions come as expected. ShouldBeTime := NOW + 10 ns; wait on S; if (ShouldBeTime /= now or S /= not S_INITIAL) then k := 1; end if; assert (ShouldBeTime = NOW); assert (S = (not S_INITIAL)); ShouldBeTime := NOW + 10 ns; wait on S; if (ShouldBeTime /= now or S /= S_INITIAL) then k := 1; end if; assert (ShouldBeTime = NOW); assert (S = S_INITIAL); -- b. Verify that the first transactions have been preempted. ShouldBeTime := NOW + 40 ns; wait on S for 40 ns; if (ShouldBeTime /= now) then k := 1; end if; assert (ShouldBeTime = NOW); assert NOT( k=0 ) report "***PASSED TEST: c08s04b01x00p07n01i01348" severity NOTE; assert ( k=0 ) report "***FAILED TEST: c08s04b01x00p07n01i01348 - The sequence of transactions is used to update the projected output waveform representing the current and future values of the driver associated with the signal assignment statement." severity ERROR; wait; END PROCESS TESTING; END c08s04b01x00p07n01i01348arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1348.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s04b01x00p07n01i01348ent IS END c08s04b01x00p07n01i01348ent; ARCHITECTURE c08s04b01x00p07n01i01348arch OF c08s04b01x00p07n01i01348ent IS -- Local signals. signal S : BIT := '0'; BEGIN TESTING: PROCESS -- local variables. variable S_INITIAL : BIT; variable ShouldBeTime : TIME; variable k : integer := 0; BEGIN -- 0. Keep around the initial value of S. S_INITIAL := S; -- 1. When no preemption necessary, verify the results. S <= transport (not S) after 10 ns, (S) after 20 ns; -- a. Wait for first transaction. ShouldBeTime := NOW + 10 ns; wait on S; if (ShouldBeTime /= now or S /= not S_INITIAL) then k := 1; end if; assert (ShouldBeTime = NOW); assert (S = (not S_INITIAL)); -- b. Wait for second transaction. ShouldBeTime := NOW + 10 ns; wait on S; assert (ShouldBeTime = NOW); assert (S = S_INITIAL); -- 2. Preempt a transaction which is to occur at the same time as second one. S_INITIAL := S; S <= transport (S) after 10 ns; S <= transport (not S) after 10 ns; -- Should preempt first transaction. -- a. Verify that the second transaction comes as expected. ShouldBeTime := NOW + 10 ns; wait on S; if (ShouldBeTime /= now or S /= not S_INITIAL) then k := 1; end if; assert (ShouldBeTime = NOW); assert (S = (not S_INITIAL)); -- b. Verify that the first transaction has been preempted. ShouldBeTime := NOW + 10 ns; wait on S for 10 ns; if (ShouldBeTime /= now) then k := 1; end if; assert (ShouldBeTime = NOW); -- 3. Preempt a transaction which is to occur at a later time than second one. S_INITIAL := S; S <= transport (S) after 15 ns; S <= transport (not S) after 10 ns; -- Should preempt first transaction. -- a. Verify that the second transaction comes as expected. ShouldBeTime := NOW + 10 ns; wait on S; if (ShouldBeTime /= now or S /= not S_INITIAL) then k := 1; end if; assert (ShouldBeTime = NOW); assert (S = (not S_INITIAL)); -- b. Verify that the first transaction has been preempted. ShouldBeTime := NOW + 10 ns; wait on S for 10 ns; if (ShouldBeTime /= now) then k := 1; end if; assert (ShouldBeTime = NOW); -- 4. Preempt multiple transactions. S_INITIAL := S; S <= transport (S) after 15 ns, (not S) after 30 ns; S <= transport (not S) after 10 ns, (S) after 20 ns; -- a. Verify that the second transactions come as expected. ShouldBeTime := NOW + 10 ns; wait on S; if (ShouldBeTime /= now or S /= not S_INITIAL) then k := 1; end if; assert (ShouldBeTime = NOW); assert (S = (not S_INITIAL)); ShouldBeTime := NOW + 10 ns; wait on S; if (ShouldBeTime /= now or S /= S_INITIAL) then k := 1; end if; assert (ShouldBeTime = NOW); assert (S = S_INITIAL); -- b. Verify that the first transactions have been preempted. ShouldBeTime := NOW + 40 ns; wait on S for 40 ns; if (ShouldBeTime /= now) then k := 1; end if; assert (ShouldBeTime = NOW); assert NOT( k=0 ) report "***PASSED TEST: c08s04b01x00p07n01i01348" severity NOTE; assert ( k=0 ) report "***FAILED TEST: c08s04b01x00p07n01i01348 - The sequence of transactions is used to update the projected output waveform representing the current and future values of the driver associated with the signal assignment statement." severity ERROR; wait; END PROCESS TESTING; END c08s04b01x00p07n01i01348arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1348.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s04b01x00p07n01i01348ent IS END c08s04b01x00p07n01i01348ent; ARCHITECTURE c08s04b01x00p07n01i01348arch OF c08s04b01x00p07n01i01348ent IS -- Local signals. signal S : BIT := '0'; BEGIN TESTING: PROCESS -- local variables. variable S_INITIAL : BIT; variable ShouldBeTime : TIME; variable k : integer := 0; BEGIN -- 0. Keep around the initial value of S. S_INITIAL := S; -- 1. When no preemption necessary, verify the results. S <= transport (not S) after 10 ns, (S) after 20 ns; -- a. Wait for first transaction. ShouldBeTime := NOW + 10 ns; wait on S; if (ShouldBeTime /= now or S /= not S_INITIAL) then k := 1; end if; assert (ShouldBeTime = NOW); assert (S = (not S_INITIAL)); -- b. Wait for second transaction. ShouldBeTime := NOW + 10 ns; wait on S; assert (ShouldBeTime = NOW); assert (S = S_INITIAL); -- 2. Preempt a transaction which is to occur at the same time as second one. S_INITIAL := S; S <= transport (S) after 10 ns; S <= transport (not S) after 10 ns; -- Should preempt first transaction. -- a. Verify that the second transaction comes as expected. ShouldBeTime := NOW + 10 ns; wait on S; if (ShouldBeTime /= now or S /= not S_INITIAL) then k := 1; end if; assert (ShouldBeTime = NOW); assert (S = (not S_INITIAL)); -- b. Verify that the first transaction has been preempted. ShouldBeTime := NOW + 10 ns; wait on S for 10 ns; if (ShouldBeTime /= now) then k := 1; end if; assert (ShouldBeTime = NOW); -- 3. Preempt a transaction which is to occur at a later time than second one. S_INITIAL := S; S <= transport (S) after 15 ns; S <= transport (not S) after 10 ns; -- Should preempt first transaction. -- a. Verify that the second transaction comes as expected. ShouldBeTime := NOW + 10 ns; wait on S; if (ShouldBeTime /= now or S /= not S_INITIAL) then k := 1; end if; assert (ShouldBeTime = NOW); assert (S = (not S_INITIAL)); -- b. Verify that the first transaction has been preempted. ShouldBeTime := NOW + 10 ns; wait on S for 10 ns; if (ShouldBeTime /= now) then k := 1; end if; assert (ShouldBeTime = NOW); -- 4. Preempt multiple transactions. S_INITIAL := S; S <= transport (S) after 15 ns, (not S) after 30 ns; S <= transport (not S) after 10 ns, (S) after 20 ns; -- a. Verify that the second transactions come as expected. ShouldBeTime := NOW + 10 ns; wait on S; if (ShouldBeTime /= now or S /= not S_INITIAL) then k := 1; end if; assert (ShouldBeTime = NOW); assert (S = (not S_INITIAL)); ShouldBeTime := NOW + 10 ns; wait on S; if (ShouldBeTime /= now or S /= S_INITIAL) then k := 1; end if; assert (ShouldBeTime = NOW); assert (S = S_INITIAL); -- b. Verify that the first transactions have been preempted. ShouldBeTime := NOW + 40 ns; wait on S for 40 ns; if (ShouldBeTime /= now) then k := 1; end if; assert (ShouldBeTime = NOW); assert NOT( k=0 ) report "***PASSED TEST: c08s04b01x00p07n01i01348" severity NOTE; assert ( k=0 ) report "***FAILED TEST: c08s04b01x00p07n01i01348 - The sequence of transactions is used to update the projected output waveform representing the current and future values of the driver associated with the signal assignment statement." severity ERROR; wait; END PROCESS TESTING; END c08s04b01x00p07n01i01348arch;
-- Projeto gerado via script. -- Data: Sex,30/12/2011-23:36:18 -- Autor: rogerio -- Comentario: Descrição da Entidade: inversor. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity inversor is port (a: in std_logic; y: out std_logic); end inversor; architecture logica of inversor is begin -- Comandos. y <= not a; end logica;
----------------------------------------------------------------------------- -- LEON3 Demonstration design test bench -- Copyright (C) 2013 Gaisler Research ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2013, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library gaisler; use gaisler.libdcom.all; use gaisler.sim.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; use grlib.devices.all; library micron; use micron.all; library techmap; use techmap.gencomp.all; use work.debug.all; use work.config.all; entity testbench is generic ( fabtech : integer := CFG_FABTECH; memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; clktech : integer := CFG_CLKTECH; disas : integer := CFG_DISAS; -- Enable disassembly to console dbguart : integer := CFG_DUART; -- Print UART on console pclow : integer := CFG_PCLOW; testahb : boolean := true; USE_MIG_INTERFACE_MODEL : boolean := false ); end; architecture behav of testbench is -- DDR3 Simulation parameters constant SIM_BYPASS_INIT_CAL : string := "FAST"; -- # = "OFF" - Complete memory init & -- calibration sequence -- # = "SKIP" - Not supported -- # = "FAST" - Complete memory init & use -- abbreviated calib sequence constant SIMULATION : string := "TRUE"; -- Should be TRUE during design simulations and -- FALSE during implementations constant promfile : string := "prom.srec"; -- rom contents constant sramfile : string := "ram.srec"; -- ram contents constant sdramfile : string := "ram.srec"; -- sdram contents signal clk : std_logic := '0'; signal Rst : std_logic := '0'; signal address : std_logic_vector(25 downto 0); signal data : std_logic_vector(15 downto 0); signal button : std_logic_vector(3 downto 0) := "0000"; signal genio : std_logic_vector(59 downto 0); signal romsn : std_logic; signal oen : std_ulogic; signal writen : std_ulogic; signal adv : std_logic; signal GND : std_ulogic := '0'; signal VCC : std_ulogic := '1'; signal NC : std_ulogic := 'Z'; signal txd1 , rxd1 , dsurx : std_logic; signal txd2 , rxd2 , dsutx : std_logic; signal ctsn1 , rtsn1 , dsuctsn : std_ulogic; signal ctsn2 , rtsn2 , dsurtsn : std_ulogic; signal phy_gtxclk : std_logic := '0'; signal phy_txer : std_ulogic; signal phy_txd : std_logic_vector(7 downto 0); signal phy_txctl_txen : std_ulogic; signal phy_txclk : std_ulogic; signal phy_rxer : std_ulogic; signal phy_rxd : std_logic_vector(7 downto 0); signal phy_rxctl_rxdv : std_ulogic; signal phy_rxclk : std_ulogic; signal phy_reset : std_ulogic; signal phy_mdio : std_logic; signal phy_mdc : std_ulogic; signal phy_crs : std_ulogic; signal phy_col : std_ulogic; signal phy_int : std_ulogic; signal phy_rxdl : std_logic_vector(7 downto 0); signal phy_txdl : std_logic_vector(7 downto 0); signal clk27 : std_ulogic := '0'; signal clk200p : std_ulogic := '0'; signal clk200n : std_ulogic := '1'; signal clk33 : std_ulogic := '0'; signal clkethp : std_ulogic := '0'; signal clkethn : std_ulogic := '1'; signal txp1 : std_logic; signal txn : std_logic; signal rxp : std_logic := '1'; signal rxn : std_logic := '0'; signal iic_scl : std_ulogic; signal iic_sda : std_ulogic; signal ddc_scl : std_ulogic; signal ddc_sda : std_ulogic; signal dvi_iic_scl : std_logic; signal dvi_iic_sda : std_logic; signal tft_lcd_data : std_logic_vector(11 downto 0); signal tft_lcd_clk_p : std_ulogic; signal tft_lcd_clk_n : std_ulogic; signal tft_lcd_hsync : std_ulogic; signal tft_lcd_vsync : std_ulogic; signal tft_lcd_de : std_ulogic; signal tft_lcd_reset_b : std_ulogic; -- DDR3 memory signal ddr3_dq : std_logic_vector(63 downto 0); signal ddr3_dqs_p : std_logic_vector(7 downto 0); signal ddr3_dqs_n : std_logic_vector(7 downto 0); signal ddr3_addr : std_logic_vector(13 downto 0); signal ddr3_ba : std_logic_vector(2 downto 0); signal ddr3_ras_n : std_logic; signal ddr3_cas_n : std_logic; signal ddr3_we_n : std_logic; signal ddr3_reset_n : std_logic; signal ddr3_ck_p : std_logic_vector(0 downto 0); signal ddr3_ck_n : std_logic_vector(0 downto 0); signal ddr3_cke : std_logic_vector(0 downto 0); signal ddr3_cs_n : std_logic_vector(0 downto 0); signal ddr3_dm : std_logic_vector(7 downto 0); signal ddr3_odt : std_logic_vector(0 downto 0); -- SPI flash signal spi_sel_n : std_ulogic; signal spi_clk : std_ulogic; signal spi_mosi : std_ulogic; signal dsurst : std_ulogic; signal errorn : std_logic; signal switch : std_logic_vector(3 downto 0); -- I/O port signal led : std_logic_vector(6 downto 0); -- I/O port constant lresp : boolean := false; signal tdqs_n : std_logic; signal gmii_tx_clk : std_logic; signal gmii_rx_clk : std_logic; signal gmii_txd : std_logic_vector(7 downto 0); signal gmii_tx_en : std_logic; signal gmii_tx_er : std_logic; signal gmii_rxd : std_logic_vector(7 downto 0); signal gmii_rx_dv : std_logic; signal gmii_rx_er : std_logic; component leon3mp is generic ( fabtech : integer := CFG_FABTECH; memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; clktech : integer := CFG_CLKTECH; disas : integer := CFG_DISAS; -- Enable disassembly to console dbguart : integer := CFG_DUART; -- Print UART on console pclow : integer := CFG_PCLOW; testahb : boolean := false; SIM_BYPASS_INIT_CAL : string := "OFF"; SIMULATION : string := "FALSE"; USE_MIG_INTERFACE_MODEL : boolean := false ); port ( reset : in std_ulogic; clk200p : in std_ulogic; -- 200 MHz clock clk200n : in std_ulogic; -- 200 MHz clock address : out std_logic_vector(25 downto 0); data : inout std_logic_vector(15 downto 0); oen : out std_ulogic; writen : out std_ulogic; romsn : out std_logic; adv : out std_logic; ddr3_dq : inout std_logic_vector(63 downto 0); ddr3_dqs_p : inout std_logic_vector(7 downto 0); ddr3_dqs_n : inout std_logic_vector(7 downto 0); ddr3_addr : out std_logic_vector(13 downto 0); ddr3_ba : out std_logic_vector(2 downto 0); ddr3_ras_n : out std_logic; ddr3_cas_n : out std_logic; ddr3_we_n : out std_logic; ddr3_reset_n : out std_logic; ddr3_ck_p : out std_logic_vector(0 downto 0); ddr3_ck_n : out std_logic_vector(0 downto 0); ddr3_cke : out std_logic_vector(0 downto 0); ddr3_cs_n : out std_logic_vector(0 downto 0); ddr3_dm : out std_logic_vector(7 downto 0); ddr3_odt : out std_logic_vector(0 downto 0); dsurx : in std_ulogic; dsutx : out std_ulogic; dsuctsn : in std_ulogic; dsurtsn : out std_ulogic; button : in std_logic_vector(3 downto 0); switch : inout std_logic_vector(3 downto 0); led : out std_logic_vector(6 downto 0); iic_scl : inout std_ulogic; iic_sda : inout std_ulogic; gtrefclk_p : in std_logic; gtrefclk_n : in std_logic; phy_gtxclk : out std_logic; --phy_txer : out std_ulogic; phy_txd : out std_logic_vector(3 downto 0); phy_txctl_txen : out std_ulogic; --phy_txclk : in std_ulogic; --phy_rxer : in std_ulogic; phy_rxd : in std_logic_vector(3 downto 0); phy_rxctl_rxdv : in std_ulogic; phy_rxclk : in std_ulogic; phy_reset : out std_ulogic; phy_mdio : inout std_logic; phy_mdc : out std_ulogic; phy_int : in std_ulogic ); end component; component ddr3_model generic( ADDR_BITS : integer := 14; BA_BITS : integer := 3; DM_BITS : integer := 1; DQ_BITS : integer := 8; DQS_BITS : integer := 1 ); port( rst_n : in std_logic; ck : in std_logic; ck_n : in std_logic; cke : in std_logic; cs_n : in std_logic; ras_n : in std_logic; cas_n : in std_logic; we_n : in std_logic; dm_tdqs : inout std_logic; ba : in std_logic_vector(2 downto 0); addr : in std_logic_vector(13 downto 0); dq : inout std_logic_vector(7 downto 0); dqs : inout std_logic; dqs_n : inout std_logic; tdqs_n : out std_logic_vector(0 to 0); odt : in std_logic ); end component; begin -- clock and reset clk200p <= not clk200p after 2.5 ns; clk200n <= not clk200n after 2.5 ns; clkethp <= not clkethp after 4 ns; clkethn <= not clkethp after 4 ns; rst <= not dsurst; rxd1 <= 'H'; ctsn1 <= '0'; rxd2 <= 'H'; ctsn2 <= '0'; button <= "0000"; switch(2 downto 0) <= "000"; cpu : leon3mp generic map ( fabtech => fabtech, memtech => memtech, padtech => padtech, clktech => clktech, disas => disas, dbguart => dbguart, pclow => pclow, testahb => testahb, SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL, SIMULATION => SIMULATION, USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL ) port map ( reset => rst, clk200p => clk200p, clk200n => clk200n, address => address, data => data, oen => oen, writen => writen, romsn => romsn, adv => adv, ddr3_dq => ddr3_dq, ddr3_dqs_p => ddr3_dqs_p, ddr3_dqs_n => ddr3_dqs_n, ddr3_addr => ddr3_addr, ddr3_ba => ddr3_ba, ddr3_ras_n => ddr3_ras_n, ddr3_cas_n => ddr3_cas_n, ddr3_we_n => ddr3_we_n, ddr3_reset_n => ddr3_reset_n, ddr3_ck_p => ddr3_ck_p, ddr3_ck_n => ddr3_ck_n, ddr3_cke => ddr3_cke, ddr3_cs_n => ddr3_cs_n, ddr3_dm => ddr3_dm, ddr3_odt => ddr3_odt, dsurx => dsurx, dsutx => dsutx, dsuctsn => dsuctsn, dsurtsn => dsurtsn, button => button, switch => switch, led => led, iic_scl => iic_scl, iic_sda => iic_sda, gtrefclk_p => clkethp, gtrefclk_n => clkethn, phy_gtxclk => phy_gtxclk, --phy_txer => phy_txer, phy_txd => phy_txd(3 downto 0), phy_txctl_txen => phy_txctl_txen, --phy_txclk => phy_txclk, --phy_rxer => phy_rxer, phy_rxd => phy_rxd(3 downto 0), phy_rxctl_rxdv => phy_rxctl_rxdv, phy_rxclk => phy_rxclk'delayed(1 ns), phy_reset => phy_reset, phy_mdio => phy_mdio, phy_mdc => phy_mdc, phy_int => phy_int ); prom0 : for i in 0 to 1 generate sr0 : sram generic map (index => i+4, abits => 22, fname => promfile) port map (address(21 downto 0), data(15-i*8 downto 8-i*8), romsn, writen, oen); end generate; -- Memory Models instantiations gen_mem_model : if (USE_MIG_INTERFACE_MODEL /= true) generate ddr3mem : if (CFG_MIG_SERIES7 = 1) generate gen_mem: for i in 0 to 7 generate u1: ddr3_model generic map( ADDR_BITS => 14, BA_BITS => 3, DM_BITS => 1, DQ_BITS => 8, DQS_BITS => 1 ) port map ( rst_n => ddr3_reset_n, ck => ddr3_ck_p(0), ck_n => ddr3_ck_n(0), cke => ddr3_cke(0), cs_n => ddr3_cs_n(0), ras_n => ddr3_ras_n, cas_n => ddr3_cas_n, we_n => ddr3_we_n, dm_tdqs => ddr3_dm(i), ba => ddr3_ba, addr => ddr3_addr, dq => ddr3_dq((8*i+7) downto (8*i)), dqs => ddr3_dqs_p(i), dqs_n => ddr3_dqs_n(i), tdqs_n => open, odt => ddr3_odt(0) ); end generate gen_mem; end generate ddr3mem; end generate gen_mem_model; mig_mem_model : if (USE_MIG_INTERFACE_MODEL = true) generate ddr3_dq <= (others => 'Z'); ddr3_dqs_p <= (others => 'Z'); ddr3_dqs_n <= (others => 'Z'); end generate mig_mem_model; errorn <= led(1); errorn <= 'H'; -- ERROR pull-up phy0 : if (CFG_GRETH = 1) generate phy_mdio <= 'H'; phy_int <= '0'; p0: phy generic map (address => 7) port map(phy_reset, phy_mdio, phy_txclk, phy_rxclk, phy_rxd, phy_rxctl_rxdv, phy_rxer, phy_col, phy_crs, phy_txd, phy_txctl_txen, phy_txer, phy_mdc, phy_gtxclk); end generate; iuerr : process begin wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation wait on led(3); -- DDR3 Memory Init ready wait for 5000 ns; if to_x01(errorn) = '1' then wait on errorn; end if; assert (to_x01(errorn) = '1') report "*** IU in error mode, simulation halted ***" severity failure ; -- this should be a failure end process; data <= buskeep(data) after 5 ns; dsucom : process procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is variable w32 : std_logic_vector(31 downto 0); variable c8 : std_logic_vector(7 downto 0); constant txp : time := 320 * 1 ns; begin dsutx <= '1'; dsurst <= '0'; switch(3) <= '0'; wait for 2500 ns; wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation dsurst <= '1'; switch(3) <= '1'; if (USE_MIG_INTERFACE_MODEL /= true) then wait on led(3); -- Wait for DDR3 Memory Init ready end if; report "Start DSU transfer"; wait for 5000 ns; txc(dsutx, 16#55#, txp); -- sync uart -- Reads from memory and DSU register to mimic GRMON during simulation l1 : loop txc(dsutx, 16#80#, txp); txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp); rxi(dsurx, w32, txp, lresp); --report "DSU read memory " & tost(w32); txc(dsutx, 16#80#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp); rxi(dsurx, w32, txp, lresp); --report "DSU Break and Single Step register" & tost(w32); end loop l1; wait; -- ** This is only kept for reference -- -- do test read and writes to DDR3 to check status -- Write txc(dsutx, 16#c0#, txp); txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp); txa(dsutx, 16#01#, 16#23#, 16#45#, 16#67#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp); txa(dsutx, 16#89#, 16#AB#, 16#CD#, 16#EF#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp); txa(dsutx, 16#08#, 16#19#, 16#2A#, 16#3B#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp); txa(dsutx, 16#4C#, 16#5D#, 16#6E#, 16#7F#, txp); txc(dsutx, 16#80#, txp); txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp); rxi(dsurx, w32, txp, lresp); txc(dsutx, 16#80#, txp); txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp); rxi(dsurx, w32, txp, lresp); report "* Read " & tost(w32); txc(dsutx, 16#a0#, txp); txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp); rxi(dsurx, w32, txp, lresp); txc(dsutx, 16#a0#, txp); txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp); rxi(dsurx, w32, txp, lresp); wait; -- Register 0x90000000 (DSU Control Register) -- Data 0x0000202e (b0010 0000 0010 1110) -- [0] - Trace Enable -- [1] - Break On Error -- [2] - Break on IU watchpoint -- [3] - Break on s/w break points -- -- [4] - (Break on trap) -- [5] - Break on error traps -- [6] - Debug mode (Read mode only) -- [7] - DSUEN (read mode) -- -- [8] - DSUBRE (read mode) -- [9] - Processor mode error (clears error) -- [10] - processor halt (returns 1 if processor halted) -- [11] - power down mode (return 1 if processor in power down mode) txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); txa(dsutx, 16#00#, 16#00#, 16#80#, 16#02#, txp); wait; txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp); wait for 25000 ns; txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp); txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp); txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp); txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp); txc(dsutx, 16#80#, txp); txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp); wait; end; begin dsuctsn <= '0'; dsucfg(dsutx, dsurx); wait; end process; end ;
library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Volume_Pregain_Top_Module is generic( INTBIT_WIDTH : integer; FRACBIT_WIDTH : integer ); port( OUT_VOLCTRL_L : out signed((INTBIT_WIDTH - 1) downto 0) := (others => '0'); -- 24 bit signed output OUT_VOLCTRL_R : out signed((INTBIT_WIDTH - 1) downto 0) := (others => '0'); -- 24 bit signed output OUT_RDY : out STD_LOGIC; IN_SIG_L : in signed((INTBIT_WIDTH - 1) downto 0); --amplifier input signal 24-bit IN_SIG_R : in signed((INTBIT_WIDTH - 1) downto 0); --amplifier input signal 24-bit IN_COEF_L : in signed(((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0); -- 32 bit COEF from a register. Last 8 bits are fractional for volume control 0<-->1 IN_COEF_R : in signed(((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0); -- 32 bit COEF from a register. Last 8 bits are fractional for volume control 0<-->1 CLK_100mhz : in STD_LOGIC; RESET : in STD_LOGIC ); end Volume_Pregain_Top_Module; architecture Behavioral of Volume_Pregain_Top_Module is component AmplifierFP generic ( INTBIT_WIDTH : integer; FRACBIT_WIDTH : integer); port( CLK : in std_logic; RESET : in std_logic; IN_SIG : in signed((INTBIT_WIDTH - 1) downto 0); --amplifier input signal 24-bit IN_COEF : in signed(((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0); -- 32 bit COEF from a register. Last 8 bits are fractional for volume control 0<-->1 OUT_AMP : out signed((INTBIT_WIDTH - 1) downto 0) := (others => '0'); --amplifier output OUT_RDY : out std_logic ); end component; signal AMP_OUT_L, AMP_OUT_R : signed((INTBIT_WIDTH - 1) downto 0) := (others => '0'); signal VOLCTRL_L, VOLCTRL_R : signed((INTBIT_WIDTH - 1) downto 0) := (others => '0'); signal volctrl_ready_l : std_logic := '0'; signal volctrl_ready_r : std_logic := '0'; begin AmplifierFP_L : AmplifierFP generic map( INTBIT_WIDTH => INTBIT_WIDTH, FRACBIT_WIDTH => FRACBIT_WIDTH )port map( CLK => CLK_100mhz, RESET => RESET, IN_SIG => IN_SIG_L, IN_COEF => IN_COEF_L, OUT_AMP => AMP_OUT_L, OUT_RDY => volctrl_ready_l ); AmplifierFP_R : AmplifierFP generic map( INTBIT_WIDTH => INTBIT_WIDTH, FRACBIT_WIDTH => FRACBIT_WIDTH )port map( CLK => CLK_100mhz, RESET => RESET, IN_SIG => IN_SIG_R, IN_COEF => IN_COEF_R, OUT_AMP => AMP_OUT_R, OUT_RDY => volctrl_ready_r ); seq_proc : process(CLK_100mhz) begin if (CLK_100mhz'event and CLK_100mhz = '1') then -- update the ready signal when new values gets written to the buffer if (volctrl_ready_l = '1') then VOLCTRL_L <= AMP_OUT_L; end if; if (volctrl_ready_r = '1') then VOLCTRL_R <= AMP_OUT_R; end if; end if; end process; OUT_RDY <= volctrl_ready_l or volctrl_ready_r; OUT_VOLCTRL_L <= VOLCTRL_L; OUT_VOLCTRL_R <= VOLCTRL_R; end Behavioral;
library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Volume_Pregain_Top_Module is generic( INTBIT_WIDTH : integer; FRACBIT_WIDTH : integer ); port( OUT_VOLCTRL_L : out signed((INTBIT_WIDTH - 1) downto 0) := (others => '0'); -- 24 bit signed output OUT_VOLCTRL_R : out signed((INTBIT_WIDTH - 1) downto 0) := (others => '0'); -- 24 bit signed output OUT_RDY : out STD_LOGIC; IN_SIG_L : in signed((INTBIT_WIDTH - 1) downto 0); --amplifier input signal 24-bit IN_SIG_R : in signed((INTBIT_WIDTH - 1) downto 0); --amplifier input signal 24-bit IN_COEF_L : in signed(((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0); -- 32 bit COEF from a register. Last 8 bits are fractional for volume control 0<-->1 IN_COEF_R : in signed(((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0); -- 32 bit COEF from a register. Last 8 bits are fractional for volume control 0<-->1 CLK_100mhz : in STD_LOGIC; RESET : in STD_LOGIC ); end Volume_Pregain_Top_Module; architecture Behavioral of Volume_Pregain_Top_Module is component AmplifierFP generic ( INTBIT_WIDTH : integer; FRACBIT_WIDTH : integer); port( CLK : in std_logic; RESET : in std_logic; IN_SIG : in signed((INTBIT_WIDTH - 1) downto 0); --amplifier input signal 24-bit IN_COEF : in signed(((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0); -- 32 bit COEF from a register. Last 8 bits are fractional for volume control 0<-->1 OUT_AMP : out signed((INTBIT_WIDTH - 1) downto 0) := (others => '0'); --amplifier output OUT_RDY : out std_logic ); end component; signal AMP_OUT_L, AMP_OUT_R : signed((INTBIT_WIDTH - 1) downto 0) := (others => '0'); signal VOLCTRL_L, VOLCTRL_R : signed((INTBIT_WIDTH - 1) downto 0) := (others => '0'); signal volctrl_ready_l : std_logic := '0'; signal volctrl_ready_r : std_logic := '0'; begin AmplifierFP_L : AmplifierFP generic map( INTBIT_WIDTH => INTBIT_WIDTH, FRACBIT_WIDTH => FRACBIT_WIDTH )port map( CLK => CLK_100mhz, RESET => RESET, IN_SIG => IN_SIG_L, IN_COEF => IN_COEF_L, OUT_AMP => AMP_OUT_L, OUT_RDY => volctrl_ready_l ); AmplifierFP_R : AmplifierFP generic map( INTBIT_WIDTH => INTBIT_WIDTH, FRACBIT_WIDTH => FRACBIT_WIDTH )port map( CLK => CLK_100mhz, RESET => RESET, IN_SIG => IN_SIG_R, IN_COEF => IN_COEF_R, OUT_AMP => AMP_OUT_R, OUT_RDY => volctrl_ready_r ); seq_proc : process(CLK_100mhz) begin if (CLK_100mhz'event and CLK_100mhz = '1') then -- update the ready signal when new values gets written to the buffer if (volctrl_ready_l = '1') then VOLCTRL_L <= AMP_OUT_L; end if; if (volctrl_ready_r = '1') then VOLCTRL_R <= AMP_OUT_R; end if; end if; end process; OUT_RDY <= volctrl_ready_l or volctrl_ready_r; OUT_VOLCTRL_L <= VOLCTRL_L; OUT_VOLCTRL_R <= VOLCTRL_R; end Behavioral;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.mem_bus_pkg.all; use work.cart_slot_pkg.all; use work.io_bus_pkg.all; use work.io_bus_bfm_pkg.all; use work.command_if_pkg.all; library std; use std.textio.all; entity harness_logic_32 is end entity; architecture tb of harness_logic_32 is constant c_uart_divisor : natural := 50; signal PHI2 : std_logic := '0'; signal RSTn : std_logic := 'H'; signal DOTCLK : std_logic := '1'; signal BUFFER_ENn : std_logic := '1'; signal BA : std_logic := '0'; signal DMAn : std_logic := '1'; signal EXROMn : std_logic; signal GAMEn : std_logic; signal ROMHn : std_logic := '1'; signal ROMLn : std_logic := '1'; signal IO1n : std_logic := '1'; signal IO2n : std_logic := '1'; signal IRQn : std_logic := '1'; signal NMIn : std_logic := '1'; signal PWM_OUT : std_logic_vector(1 downto 0); signal IEC_ATN : std_logic := '1'; signal IEC_DATA : std_logic := '1'; signal IEC_CLOCK : std_logic := '1'; signal IEC_RESET : std_logic := '1'; signal IEC_SRQ_IN : std_logic := '1'; signal iec_atn_o : std_logic := '1'; signal iec_data_o : std_logic := '1'; signal iec_clock_o : std_logic := '1'; signal iec_reset_o : std_logic := '1'; signal iec_srq_o : std_logic := '1'; signal DISK_ACTn : std_logic; -- activity LED signal CART_LEDn : std_logic; signal SDACT_LEDn : std_logic; signal MOTOR_LEDn : std_logic; signal UART_TXD : std_logic; signal UART_RXD : std_logic := '1'; signal SD_SSn : std_logic; signal SD_CLK : std_logic; signal SD_MOSI : std_logic; signal SD_MISO : std_logic := '1'; signal SD_WP : std_logic := '1'; signal SD_CARDDETn : std_logic := '1'; signal SD_DATA : std_logic_vector(2 downto 1) := "HH"; signal BUTTON : std_logic_vector(2 downto 0) := "000"; signal SLOT_ADDR : std_logic_vector(15 downto 0); signal SLOT_DATA : std_logic_vector(7 downto 0); signal RWn : std_logic := '1'; signal CAS_MOTOR : std_logic := '1'; signal CAS_SENSE : std_logic := '0'; signal CAS_READ : std_logic := '0'; signal CAS_WRITE : std_logic := '0'; signal RTC_CS : std_logic; signal RTC_SCK : std_logic; signal RTC_MOSI : std_logic; signal RTC_MISO : std_logic := '1'; signal FLASH_CSn : std_logic; signal FLASH_SCK : std_logic; signal FLASH_MOSI : std_logic; signal FLASH_MISO : std_logic := '1'; signal ULPI_CLOCK : std_logic := '0'; signal ULPI_RESET : std_logic := '0'; signal ULPI_NXT : std_logic := '0'; signal ULPI_STP : std_logic; signal ULPI_DIR : std_logic := '0'; signal ULPI_DATA : std_logic_vector(7 downto 0) := (others => 'H'); signal sys_clock : std_logic := '1'; signal sys_reset : std_logic := '1'; signal sys_clock_2x : std_logic := '1'; signal rx_char : std_logic_vector(7 downto 0); signal rx_char_d : std_logic_vector(7 downto 0); signal rx_ack : std_logic; signal tx_char : std_logic_vector(7 downto 0) := X"00"; signal tx_done : std_logic; signal do_tx : std_logic := '0'; -- memory controller interconnect signal mem_inhibit : std_logic := '0'; signal mem_req : t_mem_req_32; signal mem_resp : t_mem_resp_32; signal io_req : t_io_req; signal io_resp : t_io_resp; signal CLOCK_50 : std_logic := '0'; signal SDRAM_CLK : std_logic; signal SDRAM_CKE : std_logic; signal SDRAM_CSn : std_logic := '1'; signal SDRAM_RASn : std_logic := '1'; signal SDRAM_CASn : std_logic := '1'; signal SDRAM_WEn : std_logic := '1'; signal SDRAM_DQM : std_logic := '0'; signal SDRAM_A : std_logic_vector(12 downto 0); signal SDRAM_BA : std_logic_vector(1 downto 0); signal SDRAM_DQ : std_logic_vector(7 downto 0) := (others => 'Z'); begin sys_clock <= not sys_clock after 10 ns; sys_clock_2x <= not sys_clock_2x after 5 ns; sys_reset <= '1', '0' after 100 ns; mut: entity work.ultimate_logic_32 generic map ( g_version => X"02", g_simulation => true, g_clock_freq => 50_000_000, g_baud_rate => 1_000_000, g_timer_rate => 200_000, g_boot_rom => false, g_video_overlay => false, g_icap => false, g_uart => true, g_drive_1541 => true, g_drive_1541_2 => false, g_hardware_gcr => true, g_cartridge => true, g_command_intf => true, g_stereo_sid => false, g_ram_expansion => true, g_extended_reu => false, g_hardware_iec => false, g_iec_prog_tim => false, g_c2n_streamer => false, g_c2n_recorder => false, g_drive_sound => true, g_rtc_chip => false, g_rtc_timer => false, g_usb_host => false, g_usb_host2 => true, g_spi_flash => true, g_vic_copper => false, g_sampler => false, g_profiler => true, g_analyzer => false ) port map ( sys_clock => sys_clock, sys_reset => sys_reset, ulpi_clock => ulpi_clock, ulpi_reset => ulpi_reset, PHI2 => PHI2, DOTCLK => DOTCLK, RSTn => RSTn, BUFFER_ENn => BUFFER_ENn, SLOT_ADDR => SLOT_ADDR, SLOT_DATA => SLOT_DATA, RWn => RWn, BA => BA, DMAn => DMAn, EXROMn => EXROMn, GAMEn => GAMEn, ROMHn => ROMHn, ROMLn => ROMLn, IO1n => IO1n, IO2n => IO2n, IRQn => IRQn, NMIn => NMIn, mem_inhibit => mem_inhibit, mem_req => mem_req, mem_resp => mem_resp, PWM_OUT => PWM_OUT, iec_reset_i => IEC_RESET, iec_atn_i => IEC_ATN, iec_data_i => IEC_DATA, iec_clock_i => IEC_CLOCK, iec_srq_i => IEC_SRQ_IN, iec_reset_o => iec_reset_o, iec_atn_o => iec_atn_o, iec_data_o => iec_data_o, iec_clock_o => iec_clock_o, iec_srq_o => iec_srq_o, BUTTON => BUTTON, DISK_ACTn => DISK_ACTn, CART_LEDn => CART_LEDn, SDACT_LEDn => SDACT_LEDn, MOTOR_LEDn => MOTOR_LEDn, UART_TXD => UART_TXD, UART_RXD => UART_RXD, SD_SSn => SD_SSn, SD_CLK => SD_CLK, SD_MOSI => SD_MOSI, SD_MISO => SD_MISO, SD_CARDDETn => SD_CARDDETn, SD_DATA => SD_DATA, RTC_CS => RTC_CS, RTC_SCK => RTC_SCK, RTC_MOSI => RTC_MOSI, RTC_MISO => RTC_MISO, FLASH_CSn => FLASH_CSn, FLASH_SCK => FLASH_SCK, FLASH_MOSI => FLASH_MOSI, FLASH_MISO => FLASH_MISO, ULPI_NXT => ULPI_NXT, ULPI_STP => ULPI_STP, ULPI_DIR => ULPI_DIR, ULPI_DATA => ULPI_DATA, CAS_MOTOR => CAS_MOTOR, CAS_SENSE => CAS_SENSE, CAS_READ => CAS_READ, CAS_WRITE => CAS_WRITE, sim_io_req => io_req, sim_io_resp => io_resp ); i_mem_ctrl: entity work.ext_mem_ctrl_v5 generic map ( g_simulation => false ) port map ( clock => sys_clock, clk_2x => sys_clock_2x, reset => sys_reset, inhibit => mem_inhibit, is_idle => open, req => mem_req, resp => mem_resp, SDRAM_CLK => SDRAM_CLK, SDRAM_CKE => SDRAM_CKE, SDRAM_CSn => SDRAM_CSn, SDRAM_RASn => SDRAM_RASn, SDRAM_CASn => SDRAM_CASn, SDRAM_WEn => SDRAM_WEn, SDRAM_DQM => SDRAM_DQM, SDRAM_BA => SDRAM_BA, SDRAM_A => SDRAM_A, SDRAM_DQ => SDRAM_DQ ); ULPI_CLOCK <= not ULPI_CLOCK after 8.333 ns; -- 60 MHz ULPI_RESET <= '1', '0' after 100 ns; PHI2 <= not PHI2 after 507.5 ns; -- 0.98525 MHz RSTn <= '0', 'H' after 6 us, '0' after 100 us, 'H' after 105 us; i_io_bfm: entity work.io_bus_bfm generic map ( g_name => "io_bfm" ) port map ( clock => sys_clock, req => io_req, resp => io_resp ); SLOT_DATA <= (others => 'H'); ROMHn <= '1'; ROMLn <= not PHI2 after 50 ns; IO1n <= '1'; IO2n <= '1'; process begin SLOT_ADDR <= X"7F00"; RWn <= '1'; while true loop wait until PHI2 = '0'; --SLOT_ADDR(8 downto 0) <= std_logic_vector(unsigned(SLOT_ADDR(8 downto 0)) + 1); SLOT_ADDR <= std_logic_vector(unsigned(SLOT_ADDR) + 1); RWn <= '1'; wait until PHI2 = '0'; RWn <= '0'; end loop; end process; process begin BA <= '1'; for i in 0 to 100 loop wait until PHI2='0'; end loop; BA <= '0'; for i in 0 to 10 loop wait until PHI2='0'; end loop; end process; ram: entity work.dram_8 generic map( g_cas_latency => 3, g_burst_len_r => 4, g_burst_len_w => 4, g_column_bits => 10, g_row_bits => 13, g_bank_bits => 2 ) port map( CLK => SDRAM_CLK, CKE => SDRAM_CKE, A => SDRAM_A, BA => SDRAM_BA, CSn => SDRAM_CSn, RASn => SDRAM_RASn, CASn => SDRAM_CASn, WEn => SDRAM_WEn, DQM => SDRAM_DQM, DQ => SDRAM_DQ ); -- i_ulpi_phy: entity work.ulpi_master_bfm -- generic map ( -- g_given_name => "device" ) -- -- port map ( -- clock => ULPI_CLOCK, -- reset => ULPI_RESET, -- ulpi_nxt => ulpi_nxt, -- ulpi_stp => ulpi_stp, -- ulpi_dir => ulpi_dir, -- ulpi_data => ulpi_data ); -- -- i_device: entity work.usb_device_model; i_rx: entity work.rx generic map (c_uart_divisor) port map ( clk => sys_clock, reset => sys_reset, rxd => UART_TXD, rxchar => rx_char, rx_ack => rx_ack ); i_tx: entity work.tx generic map (c_uart_divisor) port map ( clk => sys_clock, reset => sys_reset, dotx => do_tx, txchar => tx_char, done => tx_done, txd => UART_RXD ); process(sys_clock) variable s : line; variable char : character; begin if rising_edge(sys_clock) then if rx_ack='1' then rx_char_d <= rx_char; char := character'val(to_integer(unsigned(rx_char))); if rx_char = X"0D" then -- Ignore character 13 elsif rx_char = X"0A" then -- Writeline on character 10 (newline) writeline(output, s); else -- Write to buffer write(s, char); end if; end if; if mem_resp.rack = '1' and mem_req.address < 16 then report "Access to address " & integer'image(to_integer(mem_req.address)) severity error; end if; end if; end process; process variable io : p_io_bus_bfm_object; begin wait until sys_reset='0'; wait until sys_clock='1'; bind_io_bus_bfm("io_bfm", io); io_write(io, X"40000" + c_cart_c64_mode, X"04"); -- reset io_write(io, X"40000" + c_cart_cartridge_type, X"06"); -- retro io_write(io, X"40000" + c_cart_c64_mode, X"08"); -- unreset io_write(io, X"44000" + c_cif_io_slot_base, X"7E"); io_write(io, X"44000" + c_cif_io_slot_enable, X"01"); wait for 6 us; wait until sys_clock='1'; --io_write(io, X"42002", X"42"); wait; end process; process procedure send_char(i: std_logic_vector(7 downto 0)) is begin if tx_done /= '1' then wait until tx_done = '1'; end if; wait until sys_clock='1'; tx_char <= i; do_tx <= '1'; wait until tx_done = '0'; wait until sys_clock='1'; do_tx <= '0'; end procedure; procedure send_string(i : string) is variable b : std_logic_vector(7 downto 0); begin for n in i'range loop b := std_logic_vector(to_unsigned(character'pos(i(n)), 8)); send_char(b); end loop; send_char(X"0d"); send_char(X"0a"); end procedure; begin wait for 2 ms; --send_string("wd 4005000 12345678"); send_string("run"); -- send_string("m 100000"); -- send_string("w 400000F 4"); wait; end process; -- check timing data process(PHI2) begin if falling_edge(PHI2) then assert SLOT_DATA'last_event >= 189 ns report "Timing error on C64 bus." severity error; end if; end process; end tb;
architecture rtl of fifo is begin process begin var1 := '0' when rd_en = '1' else '1'; var2 := '0' when rd_en = '1' else '1'; wr_en_a <= force '0' when rd_en = '1' else '1'; wr_en_b <= force '0' when rd_en = '1' else '1'; end process; concurrent_wr_en_a <= '0'when rd_en = '1' else '1'; concurrent_wr_en_b <= '0' when rd_en = '1' else '1'; end architecture rtl;
--------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:42:09 02/09/2013 -- Design Name: -- Module Name: Top - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.all; use IEEE.STD_LOGIC_UNSIGNED.all; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity TopRoland is port ( -- Standard 6847 signals -- -- expept DA which is now input only -- except nRP which re-purposed as a nWR DD : inout std_logic_vector (7 downto 0); DA : in std_logic_vector (12 downto 0); nMS : in std_logic; CSS : in std_logic; nFS : out std_logic; nWR : in std_logic; -- Was nRP AG : in std_logic; GM : in std_logic_vector (2 downto 0); -- 5 bit VGA Output R : out std_logic_vector (0 downto 0); G : out std_logic_vector (1 downto 0); B : out std_logic_vector (0 downto 0); HSYNC : out std_logic; VSYNC : out std_logic; -- 1 bit AUDIO Output AUDIO : out std_logic; -- Other GODIL specific pins clock49 : in std_logic; nRST : in std_logic; nBXXX : in std_logic; -- Jumpers -- Enabled SID Audio SIDEN : in std_logic; -- Moves SID from 9FE0 to BDC0 nSIDD : in std_logic; -- charSet charSet : in std_logic; -- Active low version of the SID Select Signal for disabling the external bus buffers -- nSIDSEL : out std_logic; -- PS/2 Mouse PS2_CLK : inout std_logic; PS2_DATA : inout std_logic; -- UART uart_TxD : out std_logic; uart_RxD : in std_logic; -- LEDs led8 : out std_logic; -- MISC CSO_B : out std_logic ); end TopRoland; architecture BEHAVIORAL of TopRoland is -- clock32 is the main clock signal clock32 : std_logic; -- clock25 is a full speed VGA clock signal clock25 : std_logic; -- clock15 is just used between two DCMs signal clock15 : std_logic; -- clock59 is just used between two DCMs signal clock59 : std_logic; -- Reset signal (active high) signal reset : std_logic; -- Reset signal to 6847 (active high), not currently used signal reset_vid : std_logic; -- pipelined versions of the address/data/write signals signal nWR1 : std_logic; signal nWR2 : std_logic; signal nMS1 : std_logic; signal nMS2 : std_logic; signal nWRMS1 : std_logic; signal nWRMS2 : std_logic; signal nBXXX1 : std_logic; signal nBXXX2 : std_logic; signal DA1 : std_logic_vector (12 downto 0); signal DA2 : std_logic_vector (12 downto 0); signal DD1 : std_logic_vector (7 downto 0); signal DD2 : std_logic_vector (7 downto 0); signal DD3 : std_logic_vector (7 downto 0); signal ram_we : std_logic; signal addr : std_logic_vector (12 downto 0); signal din : std_logic_vector (7 downto 0); -- Dout back to the Atom, that is either VRAM or SID signal dout : std_logic_vector (7 downto 0); -- SID sigmals signal sid_cs : std_logic; signal sid_we : std_logic; signal sid_audio : std_logic; -- UART sigmals signal uart_cs : std_logic; signal uart_we : std_logic; -- Atom extension register signals signal reg_cs : std_logic; signal reg_we : std_logic; signal final_red : std_logic; signal final_green1 : std_logic; signal final_green0 : std_logic; signal final_blue : std_logic; signal final_vsync : std_logic; signal final_hsync : std_logic; signal final_blank : std_logic; signal final_char_a : std_logic_vector (10 downto 0); signal locked1 : std_logic; signal locked2 : std_logic; signal locked3 : std_logic; signal locked4 : std_logic; -- Palette Signals signal palette_cs : std_logic; -- enable for #BD0x -- Colour palette registers signal palette_data : std_logic_vector(7 downto 0); signal logical_colour : std_logic_vector(3 downto 0); signal physical_colour : std_logic_vector(5 downto 0); type palette_type is array (0 to 15) of std_logic_vector(5 downto 0); signal palette : palette_type := ( 0 => "000000", 1 => "000011", 2 => "000100", 3 => "000111", 4 => "001000", 5 => "001011", 6 => "001100", 7 => "001111", 8 => "110000", 9 => "110011", 10 => "110100", 11 => "110111", 12 => "111000", 13 => "111011", 14 => "111100", 15 => "111111" ); begin reset <= not nRST; reset_vid <= '0'; -- Currently set at 49.152 * (31/26) * (3/7) = 25.1161318637MHz Inst_DCM1 : entity work.DCM1 port map ( CLKIN_IN => clock49, RST => '0', CLK0_OUT => clock59, CLK0_OUT1 => open, CLK2X_OUT => open, LOCKED => locked1 ); Inst_DCM2 : entity work.DCM2 port map ( CLKIN_IN => clock59, RST => not locked1, CLK0_OUT => clock25, CLK0_OUT1 => open, CLK2X_OUT => open, LOCKED => locked2 ); Inst_DCM3 : entity work.DCMSID0 port map ( CLKIN_IN => clock49, RST => '0', CLK0_OUT => clock15, CLK0_OUT1 => open, CLK2X_OUT => open, LOCKED => locked3 ); Inst_DCM4 : entity work.DCMSID1 port map ( CLKIN_IN => clock15, RST => not locked3, CLK0_OUT => clock32, CLK0_OUT1 => open, CLK2X_OUT => open, LOCKED => locked4 ); led8 <= not (locked1 and locked2 and locked3 and locked4); Inst_AtomGodilVideo : entity work.AtomGodilVideo generic map ( CImplGraphicsExt => true, CImplSoftChar => true, CImplSID => true, CImplVGA80x40 => true, CImplHWScrolling => true, CImplMouse => true, CImplUart => true, CImplDoubleVideo => true, MainClockSpeed => 32000000, DefaultBaud => 115200 ) port map ( clock_vga => clock25, clock_main => clock32, clock_sid_32Mhz => clock32, clock_sid_dac => clock49, reset => reset, reset_vid => reset_vid, din => din, dout => dout, addr => addr, CSS => CSS, AG => AG, GM => GM, nFS => nFS, ram_we => ram_we, reg_cs => reg_cs, reg_we => reg_we, sid_cs => sid_cs, sid_we => sid_we, sid_audio => sid_audio, sid_audio_d => open, PS2_CLK => PS2_CLK, PS2_DATA => PS2_DATA, uart_cs => uart_cs, uart_we => uart_we, uart_RxD => uart_RxD, uart_TxD => uart_TxD, uart_escape => open, uart_break => open, final_red => final_red, final_green1 => final_green1, final_green0 => final_green0, final_blue => final_blue, final_vsync => final_vsync, final_hsync => final_hsync, final_blank => final_blank, charSet => charSet ); -- Pipelined version of address/data/write signals process (clock32) begin if rising_edge(clock32) then nBXXX2 <= nBXXX1; nBXXX1 <= nBXXX; nMS2 <= nMS1; nMS1 <= nMS; nWRMS2 <= nWRMS1; nWRMS1 <= nWR or nMS; nWR2 <= nWR1; nWR1 <= nWR; DD3 <= DD2; DD2 <= DD1; DD1 <= DD; DA2 <= DA1; DA1 <= DA; end if; end process; -- Signals driving the VRAM -- Write just before the rising edge of nWR ram_we <= '1' when (nWRMS1 = '1' and nWRMS2 = '0' and nBXXX2 = '1') else '0'; din <= DD2; addr <= DA2; -- Signals driving the internal registers -- When nSIDD=0 the registers are mapped to BDE0-BDFF -- When nSIDD=1 the registers are mapped to 9FE0-9FFF reg_cs <= '1' when (nSIDD = '1' and nMS2 = '0' and DA2(12 downto 5) = "11111111") or (nSIDD = '0' and nBXXX2 = '0' and DA2(11 downto 5) = "1101111") else '0'; reg_we <= '1' when (nSIDD = '1' and nWRMS1 = '1' and nWRMS2 = '0') or (nSIDD = '0' and nWR1 = '1' and nWR2 = '0') else '0'; -- Signals driving the SID -- When nSIDD=0 the SID is mapped to BDC0-BDDF -- When nSIDD=1 the SID is mapped to 9FC0-9FDF sid_cs <= '1' when (nSIDD = '1' and nMS2 = '0' and DA2(12 downto 5) = "11111110") or (nSIDD = '0' and nBXXX2 = '0' and DA2(11 downto 5) = "1101110") else '0'; sid_we <= '1' when (nSIDD = '1' and nWRMS1 = '1' and nWRMS2 = '0') or (nSIDD = '0' and nWR1 = '1' and nWR2 = '0') else '0'; -- Signals driving the UART -- When nSIDD=0 the UART is mapped to BDB0-BDBF -- When nSIDD=1 the UART is mapped to 9FB0-9FBF uart_cs <= '1' when (nSIDD = '1' and nMS2 = '0' and DA2(12 downto 4) = "111111011") or (nSIDD = '0' and nBXXX2 = '0' and DA2(11 downto 4) = "11011011") else '0'; uart_we <= '1' when (nSIDD = '1' and nWRMS1 = '1' and nWRMS2 = '0') or (nSIDD = '0' and nWR1 = '1' and nWR2 = '0') else '0'; AUDIO <= sid_audio when SIDEN = '1' else '0'; -- Output the SID Select Signal so it can be used to disable the bus buffers -- TODO: this looks incorrect -- nSIDSEL <= not sid_cs; -- Tri-state data back to the Atom DD <= palette_data when nMS = '0' and nWR = '1' and palette_cs = '1' else dout when nMS = '0' and nWR = '1' and palette_cs = '0' else (others => 'Z'); CSO_B <= '1'; -------------------------------------------------------- -- Colour palette control -------------------------------------------------------- palette_cs <= '1' when nBXXX2 = '0' and DA2(11 downto 4) = x"D0" else '0'; process (clock32) begin if rising_edge(clock32) then if nRST = '0' then -- initializing like this mean the palette will be -- implemented with LUTs rather than as a block RAM palette(0) <= "000000"; palette(1) <= "000011"; palette(2) <= "000100"; palette(3) <= "000111"; palette(4) <= "001000"; palette(5) <= "001011"; palette(6) <= "001100"; palette(7) <= "001111"; palette(8) <= "110000"; palette(9) <= "110011"; palette(10) <= "110100"; palette(11) <= "110111"; palette(12) <= "111000"; palette(13) <= "111011"; palette(14) <= "111100"; palette(15) <= "111111"; else -- write colour palette registers if palette_cs = '1' and nWR1 = '1' and nWR2 = '0' then palette(conv_integer(DA2(3 downto 0))) <= DD2(7 downto 2); end if; end if; end if; end process; logical_colour <= final_red & final_green1 & final_green0 & final_blue; -- Making this a synchronous process should improve the timing -- and potentially make the pixels more defined process (clock25) begin if rising_edge(clock25) then if final_blank = '1' then physical_colour <= (others => '0'); else physical_colour <= palette(conv_integer(logical_colour)); end if; -- Also register hsync/vsync so they are correctly -- aligned with the colour changes HSYNC <= final_hsync; VSYNC <= final_vsync; end if; end process; -- Use the same bits as AtomFpga_Atom2K18, ignoring bits 4 and 0 R(0) <= physical_colour(5); G(1) <= physical_colour(3); G(0) <= physical_colour(2); B(0) <= physical_colour(1); palette_data <= palette(conv_integer(DA2(3 downto 0))) & "00"; end BEHAVIORAL;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity FA is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; Sout : out STD_LOGIC; Cout : out STD_LOGIC); end FA; architecture FA_arch of FA is component HA port(A,B: in STD_LOGIC; Sout,Cout: out STD_LOGIC); end component; signal S1,C1,C2: STD_LOGIC; begin H1: HA port map(A,B,S1,C1); H2: HA port map(S1,Cin,Sout,C2); Cout <= C1 OR C2; end FA_arch;
entity attr10 is end entity; architecture test of attr10 is begin process is constant s : string := "1234"; constant n : integer := 1234; begin for i in 1 to 4 loop report character'image(integer'image(n)(i)); assert integer'image(n)(i) = s(i); end loop; wait; end process; end architecture;
entity attr10 is end entity; architecture test of attr10 is begin process is constant s : string := "1234"; constant n : integer := 1234; begin for i in 1 to 4 loop report character'image(integer'image(n)(i)); assert integer'image(n)(i) = s(i); end loop; wait; end process; end architecture;
entity attr10 is end entity; architecture test of attr10 is begin process is constant s : string := "1234"; constant n : integer := 1234; begin for i in 1 to 4 loop report character'image(integer'image(n)(i)); assert integer'image(n)(i) = s(i); end loop; wait; end process; end architecture;
entity attr10 is end entity; architecture test of attr10 is begin process is constant s : string := "1234"; constant n : integer := 1234; begin for i in 1 to 4 loop report character'image(integer'image(n)(i)); assert integer'image(n)(i) = s(i); end loop; wait; end process; end architecture;
entity attr10 is end entity; architecture test of attr10 is begin process is constant s : string := "1234"; constant n : integer := 1234; begin for i in 1 to 4 loop report character'image(integer'image(n)(i)); assert integer'image(n)(i) = s(i); end loop; wait; end process; end architecture;
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016 -- Date : Mon Jun 05 11:21:36 2017 -- Host : GILAMONSTER running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -rename_top system_util_ds_buf_0_0 -prefix -- system_util_ds_buf_0_0_ system_util_ds_buf_0_0_sim_netlist.vhdl -- Design : system_util_ds_buf_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_util_ds_buf_0_0_util_ds_buf is port ( IBUF_DS_P : in STD_LOGIC_VECTOR ( 0 to 0 ); IBUF_DS_N : in STD_LOGIC_VECTOR ( 0 to 0 ); IBUF_OUT : out STD_LOGIC_VECTOR ( 0 to 0 ); IBUF_DS_ODIV2 : out STD_LOGIC_VECTOR ( 0 to 0 ); OBUF_IN : in STD_LOGIC_VECTOR ( 0 to 0 ); OBUF_DS_P : out STD_LOGIC_VECTOR ( 0 to 0 ); OBUF_DS_N : out STD_LOGIC_VECTOR ( 0 to 0 ); IOBUF_DS_P : inout STD_LOGIC_VECTOR ( 0 to 0 ); IOBUF_DS_N : inout STD_LOGIC_VECTOR ( 0 to 0 ); IOBUF_IO_T : in STD_LOGIC_VECTOR ( 0 to 0 ); IOBUF_IO_I : in STD_LOGIC_VECTOR ( 0 to 0 ); IOBUF_IO_O : out STD_LOGIC_VECTOR ( 0 to 0 ); BUFG_I : in STD_LOGIC_VECTOR ( 0 to 0 ); BUFG_O : out STD_LOGIC_VECTOR ( 0 to 0 ); BUFGCE_I : in STD_LOGIC_VECTOR ( 0 to 0 ); BUFGCE_CE : in STD_LOGIC_VECTOR ( 0 to 0 ); BUFGCE_O : out STD_LOGIC_VECTOR ( 0 to 0 ); BUFH_I : in STD_LOGIC_VECTOR ( 0 to 0 ); BUFH_O : out STD_LOGIC_VECTOR ( 0 to 0 ); BUFHCE_I : in STD_LOGIC_VECTOR ( 0 to 0 ); BUFHCE_CE : in STD_LOGIC_VECTOR ( 0 to 0 ); BUFHCE_O : out STD_LOGIC_VECTOR ( 0 to 0 ); BUFG_GT_I : in STD_LOGIC_VECTOR ( 0 to 0 ); BUFG_GT_CE : in STD_LOGIC_VECTOR ( 0 to 0 ); BUFG_GT_CEMASK : in STD_LOGIC_VECTOR ( 0 to 0 ); BUFG_GT_CLR : in STD_LOGIC_VECTOR ( 0 to 0 ); BUFG_GT_CLRMASK : in STD_LOGIC_VECTOR ( 0 to 0 ); BUFG_GT_DIV : in STD_LOGIC_VECTOR ( 2 downto 0 ); BUFG_GT_O : out STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute C_BUF_TYPE : string; attribute C_BUF_TYPE of system_util_ds_buf_0_0_util_ds_buf : entity is "BUFG"; attribute C_SIZE : integer; attribute C_SIZE of system_util_ds_buf_0_0_util_ds_buf : entity is 1; end system_util_ds_buf_0_0_util_ds_buf; architecture STRUCTURE of system_util_ds_buf_0_0_util_ds_buf is signal \<const0>\ : STD_LOGIC; attribute box_type : string; attribute box_type of \USE_BUFG.GEN_BUFG[0].BUFG_U\ : label is "PRIMITIVE"; begin BUFGCE_O(0) <= \<const0>\; BUFG_GT_O(0) <= \<const0>\; BUFHCE_O(0) <= \<const0>\; BUFH_O(0) <= \<const0>\; IBUF_DS_ODIV2(0) <= \<const0>\; IBUF_OUT(0) <= \<const0>\; IOBUF_IO_O(0) <= \<const0>\; OBUF_DS_N(0) <= \<const0>\; OBUF_DS_P(0) <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); \USE_BUFG.GEN_BUFG[0].BUFG_U\: unisim.vcomponents.BUFG port map ( I => BUFG_I(0), O => BUFG_O(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_util_ds_buf_0_0 is port ( BUFG_I : in STD_LOGIC_VECTOR ( 0 to 0 ); BUFG_O : out STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of system_util_ds_buf_0_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of system_util_ds_buf_0_0 : entity is "system_util_ds_buf_0_0,util_ds_buf,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of system_util_ds_buf_0_0 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of system_util_ds_buf_0_0 : entity is "util_ds_buf,Vivado 2016.4"; end system_util_ds_buf_0_0; architecture STRUCTURE of system_util_ds_buf_0_0 is signal NLW_U0_BUFGCE_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_BUFG_GT_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_BUFHCE_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_BUFH_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_IBUF_DS_ODIV2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_IBUF_OUT_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_IOBUF_DS_N_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_IOBUF_DS_P_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_IOBUF_IO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_OBUF_DS_N_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_OBUF_DS_P_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); attribute C_BUF_TYPE : string; attribute C_BUF_TYPE of U0 : label is "BUFG"; attribute C_SIZE : integer; attribute C_SIZE of U0 : label is 1; begin U0: entity work.system_util_ds_buf_0_0_util_ds_buf port map ( BUFGCE_CE(0) => '0', BUFGCE_I(0) => '0', BUFGCE_O(0) => NLW_U0_BUFGCE_O_UNCONNECTED(0), BUFG_GT_CE(0) => '0', BUFG_GT_CEMASK(0) => '0', BUFG_GT_CLR(0) => '0', BUFG_GT_CLRMASK(0) => '0', BUFG_GT_DIV(2 downto 0) => B"000", BUFG_GT_I(0) => '0', BUFG_GT_O(0) => NLW_U0_BUFG_GT_O_UNCONNECTED(0), BUFG_I(0) => BUFG_I(0), BUFG_O(0) => BUFG_O(0), BUFHCE_CE(0) => '0', BUFHCE_I(0) => '0', BUFHCE_O(0) => NLW_U0_BUFHCE_O_UNCONNECTED(0), BUFH_I(0) => '0', BUFH_O(0) => NLW_U0_BUFH_O_UNCONNECTED(0), IBUF_DS_N(0) => '0', IBUF_DS_ODIV2(0) => NLW_U0_IBUF_DS_ODIV2_UNCONNECTED(0), IBUF_DS_P(0) => '0', IBUF_OUT(0) => NLW_U0_IBUF_OUT_UNCONNECTED(0), IOBUF_DS_N(0) => NLW_U0_IOBUF_DS_N_UNCONNECTED(0), IOBUF_DS_P(0) => NLW_U0_IOBUF_DS_P_UNCONNECTED(0), IOBUF_IO_I(0) => '0', IOBUF_IO_O(0) => NLW_U0_IOBUF_IO_O_UNCONNECTED(0), IOBUF_IO_T(0) => '0', OBUF_DS_N(0) => NLW_U0_OBUF_DS_N_UNCONNECTED(0), OBUF_DS_P(0) => NLW_U0_OBUF_DS_P_UNCONNECTED(0), OBUF_IN(0) => '0' ); end STRUCTURE;
library IEEE; library UNISIM; use IEEE.STD_LOGIC_1164.all; use UNISIM.vcomponents.all; entity eightdiv is port( clk : in std_logic; clk_out : out std_logic; clkdiv_out : out std_logic ); end eightdiv; architecture Behavioral of eightdiv is constant low : std_logic := '0'; constant high : std_logic := '1'; begin -- DCM_CLKGEN: Frequency Aligned Digital Clock Manager -- Spartan-6 -- Xilinx HDL Libraries Guide, version 13.1 DCM_CLKGEN_inst : DCM_CLKGEN generic map ( CLKFXDV_DIVIDE => 8, -- CLKFXDV divide value (2, 4, 8, 16, 32) CLKFX_DIVIDE => 2, -- Divide value - D - (1-256) --CLKFX_MD_MAX => 0.0, -- Specify maximum M/D ratio for timing anlysis CLKFX_MULTIPLY => 2, -- Multiply value - M - (2-256) CLKIN_PERIOD => 10.0, -- Input clock period specified in nS SPREAD_SPECTRUM => "NONE", -- Spread Spectrum mode "NONE", "CENTER_LOW_SPREAD", "CENTER_HIGH_SPREAD", -- "VIDEO_LINK_M0", "VIDEO_LINK_M1" or "VIDEO_LINK_M2" STARTUP_WAIT => FALSE -- Delay config DONE until DCM_CLKGEN LOCKED (TRUE/FALSE) ) port map ( CLKFX => clk_out, -- 1-bit output: Generated clock output --CLKFX180 => CLKFX180, -- 1-bit output: Generated clock output 180 degree out of phase from CLKFX. CLKFXDV => clkdiv_out, -- 1-bit output: Divided clock output --LOCKED => LOCKED, -- 1-bit output: Locked output --PROGDONE => PROGDONE, -- 1-bit output: Active high output to indicate the successful re-programming --STATUS => STATUS, -- 2-bit output: DCM_CLKGEN status CLKIN => clk, -- 1-bit input: Input clock FREEZEDCM => low, -- 1-bit input: Prevents frequency adjustments to input clock PROGCLK => low, -- 1-bit input: Clock input for M/D reconfiguration PROGDATA => low, -- 1-bit input: Serial data input for M/D reconfiguration PROGEN => low, -- 1-bit input: Active high program enable RST => low -- 1-bit input: Reset input pin ); end Behavioral;
-- Simple sin/cos LUT -- Register input/output to allow usual quarter-wave symmetry -- -- Original author Colm Ryan -- Copyright 2015, Raytheon BBN Technologies library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; entity SinCosLUT is generic ( PHASE_WIDTH : natural := 14; OUTPUT_WIDTH : natural := 14 ); port ( clk : in std_logic; rst : in std_logic; phase_tdata : in std_logic_vector(PHASE_WIDTH-1 downto 0); phase_tvalid : in std_logic; sin_tdata : out std_logic_vector(OUTPUT_WIDTH-1 downto 0); cos_tdata : out std_logic_vector(OUTPUT_WIDTH-1 downto 0); sincos_tvalid : out std_logic ); end entity; architecture arch of SinCosLUT is --0 to pi/2 sin look up table constant LUT_SIZE : natural := 2**(PHASE_WIDTH-2); type lut_array is array(LUT_SIZE-1 downto 0) of signed(OUTPUT_WIDTH-1 downto 0); function fill_lut return lut_array is variable lut : lut_array; variable tmp : integer; constant SCALE : real := real(2**(OUTPUT_WIDTH-1)) - 1.0; begin for ct in 0 to LUT_SIZE-1 loop tmp := integer( SCALE * sin((MATH_PI/2.0)*real(ct)/real(LUT_SIZE)) ); lut(ct) := to_signed(tmp, OUTPUT_WIDTH); end loop; return lut; end function; --seems this should be constant but then rom_style requires signal signal lut : lut_array := fill_lut; attribute rom_style : string; attribute rom_style of lut : signal is "block"; signal sin_addr, cos_addr : natural range 0 to 2**(PHASE_WIDTH-2)-1; subtype ADDR_SLICE is natural range PHASE_WIDTH-3 downto 0; signal sin_tdata_reg, cos_tdata_reg : signed(OUTPUT_WIDTH-1 downto 0); signal sign_bit : std_logic; signal ones_complement_addr_bit : std_logic; signal sin_sign_bit_d : std_logic := '0'; signal cos_sign_bit, cos_sign_bit_d : std_logic := '0'; begin sign_bit <= phase_tdata(phase_tdata'high); ones_complement_addr_bit <= phase_tdata(phase_tdata'high - 1); sin_port : process(clk) variable lut_data : signed(OUTPUT_WIDTH-1 downto 0); begin if rising_edge(clk) then --register addr with possible ones complement if ones_complement_addr_bit = '0' then sin_addr <= to_integer(unsigned(phase_tdata(ADDR_SLICE))); else sin_addr <= to_integer(unsigned(not phase_tdata(ADDR_SLICE))); end if; --Register output data from BRAM sin_tdata_reg <= lut_data; lut_data := lut(sin_addr); end if; end process; sin_sign_bit_delay : entity work.DelayLine generic map ( DELAY_TAPS => 3) port map( clk => clk, rst => rst, data_in(0) => sign_bit, data_out(0) => sin_sign_bit_d); -- should be sin_tdata <= std_logic_vector(sin_tdata_reg) when sin_sign_bit_d = '0' else std_logic_vector(-sin_tdata_reg); -- instead sign inversion as one's complement -- could be off by 1 bit but just make OUTPUT_WIDTH wider to compensate -- TODO: investigate skewing phase and LUT by 1/2 LSB see sin_tdata <= std_logic_vector(sin_tdata_reg) when sin_sign_bit_d = '0' else not std_logic_vector(sin_tdata_reg); -- cos(\theta) = sin(\pi/2 - \theta) = sin(\pi/2 + \theta) -- pi/2 shift just adds 01 to sign/address inversion bits 00 -> 01; 01 -> 10; 10 -> 11; 11 -> 11 -- cos address inversion = not sin address inversion and cos sign inversion = sin sign inversion xor sin address inversion cos_port : process(clk) variable lut_data : signed(OUTPUT_WIDTH-1 downto 0); begin if rising_edge(clk) then --register addr with possible ones complement if ones_complement_addr_bit = '1' then cos_addr <= to_integer(unsigned(phase_tdata(ADDR_SLICE))); else cos_addr <= to_integer(unsigned(not phase_tdata(ADDR_SLICE))); end if; --Register output data from BRAM cos_tdata_reg <= lut_data; lut_data := lut(cos_addr); end if; end process; --sign inversion as ones complement cos_sign_bit <= sign_bit xor ones_complement_addr_bit; cos_sign_bit_delay : entity work.DelayLine generic map ( DELAY_TAPS => 3) port map( clk => clk, rst => rst, data_in(0) => cos_sign_bit, data_out(0) => cos_sign_bit_d); cos_tdata <= std_logic_vector(cos_tdata_reg) when cos_sign_bit_d = '0' else not std_logic_vector(cos_tdata_reg); end architecture;
-- niosii_system_width_adapter.vhd -- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:30 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity niosii_system_width_adapter is generic ( IN_PKT_ADDR_H : integer := 60; IN_PKT_ADDR_L : integer := 36; IN_PKT_DATA_H : integer := 31; IN_PKT_DATA_L : integer := 0; IN_PKT_BYTEEN_H : integer := 35; IN_PKT_BYTEEN_L : integer := 32; IN_PKT_BYTE_CNT_H : integer := 69; IN_PKT_BYTE_CNT_L : integer := 67; IN_PKT_TRANS_COMPRESSED_READ : integer := 61; IN_PKT_BURSTWRAP_H : integer := 72; IN_PKT_BURSTWRAP_L : integer := 70; IN_PKT_BURST_SIZE_H : integer := 75; IN_PKT_BURST_SIZE_L : integer := 73; IN_PKT_RESPONSE_STATUS_H : integer := 99; IN_PKT_RESPONSE_STATUS_L : integer := 98; IN_PKT_TRANS_EXCLUSIVE : integer := 66; IN_PKT_BURST_TYPE_H : integer := 77; IN_PKT_BURST_TYPE_L : integer := 76; IN_ST_DATA_W : integer := 100; OUT_PKT_ADDR_H : integer := 42; OUT_PKT_ADDR_L : integer := 18; OUT_PKT_DATA_H : integer := 15; OUT_PKT_DATA_L : integer := 0; OUT_PKT_BYTEEN_H : integer := 17; OUT_PKT_BYTEEN_L : integer := 16; OUT_PKT_BYTE_CNT_H : integer := 51; OUT_PKT_BYTE_CNT_L : integer := 49; OUT_PKT_TRANS_COMPRESSED_READ : integer := 43; OUT_PKT_BURST_SIZE_H : integer := 57; OUT_PKT_BURST_SIZE_L : integer := 55; OUT_PKT_RESPONSE_STATUS_H : integer := 81; OUT_PKT_RESPONSE_STATUS_L : integer := 80; OUT_PKT_TRANS_EXCLUSIVE : integer := 48; OUT_PKT_BURST_TYPE_H : integer := 59; OUT_PKT_BURST_TYPE_L : integer := 58; OUT_ST_DATA_W : integer := 82; ST_CHANNEL_W : integer := 13; OPTIMIZE_FOR_RSP : integer := 0; RESPONSE_PATH : integer := 0 ); port ( clk : in std_logic := '0'; -- clk.clk reset : in std_logic := '0'; -- clk_reset.reset in_valid : in std_logic := '0'; -- sink.valid in_channel : in std_logic_vector(12 downto 0) := (others => '0'); -- .channel in_startofpacket : in std_logic := '0'; -- .startofpacket in_endofpacket : in std_logic := '0'; -- .endofpacket in_ready : out std_logic; -- .ready in_data : in std_logic_vector(99 downto 0) := (others => '0'); -- .data out_endofpacket : out std_logic; -- src.endofpacket out_data : out std_logic_vector(81 downto 0); -- .data out_channel : out std_logic_vector(12 downto 0); -- .channel out_valid : out std_logic; -- .valid out_ready : in std_logic := '0'; -- .ready out_startofpacket : out std_logic; -- .startofpacket in_command_size_data : in std_logic_vector(2 downto 0) := (others => '0') ); end entity niosii_system_width_adapter; architecture rtl of niosii_system_width_adapter is component altera_merlin_width_adapter is generic ( IN_PKT_ADDR_H : integer := 60; IN_PKT_ADDR_L : integer := 36; IN_PKT_DATA_H : integer := 31; IN_PKT_DATA_L : integer := 0; IN_PKT_BYTEEN_H : integer := 35; IN_PKT_BYTEEN_L : integer := 32; IN_PKT_BYTE_CNT_H : integer := 63; IN_PKT_BYTE_CNT_L : integer := 61; IN_PKT_TRANS_COMPRESSED_READ : integer := 65; IN_PKT_BURSTWRAP_H : integer := 67; IN_PKT_BURSTWRAP_L : integer := 66; IN_PKT_BURST_SIZE_H : integer := 70; IN_PKT_BURST_SIZE_L : integer := 68; IN_PKT_RESPONSE_STATUS_H : integer := 72; IN_PKT_RESPONSE_STATUS_L : integer := 71; IN_PKT_TRANS_EXCLUSIVE : integer := 73; IN_PKT_BURST_TYPE_H : integer := 75; IN_PKT_BURST_TYPE_L : integer := 74; IN_ST_DATA_W : integer := 76; OUT_PKT_ADDR_H : integer := 60; OUT_PKT_ADDR_L : integer := 36; OUT_PKT_DATA_H : integer := 31; OUT_PKT_DATA_L : integer := 0; OUT_PKT_BYTEEN_H : integer := 35; OUT_PKT_BYTEEN_L : integer := 32; OUT_PKT_BYTE_CNT_H : integer := 63; OUT_PKT_BYTE_CNT_L : integer := 61; OUT_PKT_TRANS_COMPRESSED_READ : integer := 65; OUT_PKT_BURST_SIZE_H : integer := 68; OUT_PKT_BURST_SIZE_L : integer := 66; OUT_PKT_RESPONSE_STATUS_H : integer := 70; OUT_PKT_RESPONSE_STATUS_L : integer := 69; OUT_PKT_TRANS_EXCLUSIVE : integer := 71; OUT_PKT_BURST_TYPE_H : integer := 73; OUT_PKT_BURST_TYPE_L : integer := 72; OUT_ST_DATA_W : integer := 74; ST_CHANNEL_W : integer := 32; OPTIMIZE_FOR_RSP : integer := 0; RESPONSE_PATH : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset in_valid : in std_logic := 'X'; -- valid in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel in_startofpacket : in std_logic := 'X'; -- startofpacket in_endofpacket : in std_logic := 'X'; -- endofpacket in_ready : out std_logic; -- ready in_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data out_endofpacket : out std_logic; -- endofpacket out_data : out std_logic_vector(81 downto 0); -- data out_channel : out std_logic_vector(12 downto 0); -- channel out_valid : out std_logic; -- valid out_ready : in std_logic := 'X'; -- ready out_startofpacket : out std_logic; -- startofpacket in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data ); end component altera_merlin_width_adapter; begin width_adapter : component altera_merlin_width_adapter generic map ( IN_PKT_ADDR_H => IN_PKT_ADDR_H, IN_PKT_ADDR_L => IN_PKT_ADDR_L, IN_PKT_DATA_H => IN_PKT_DATA_H, IN_PKT_DATA_L => IN_PKT_DATA_L, IN_PKT_BYTEEN_H => IN_PKT_BYTEEN_H, IN_PKT_BYTEEN_L => IN_PKT_BYTEEN_L, IN_PKT_BYTE_CNT_H => IN_PKT_BYTE_CNT_H, IN_PKT_BYTE_CNT_L => IN_PKT_BYTE_CNT_L, IN_PKT_TRANS_COMPRESSED_READ => IN_PKT_TRANS_COMPRESSED_READ, IN_PKT_BURSTWRAP_H => IN_PKT_BURSTWRAP_H, IN_PKT_BURSTWRAP_L => IN_PKT_BURSTWRAP_L, IN_PKT_BURST_SIZE_H => IN_PKT_BURST_SIZE_H, IN_PKT_BURST_SIZE_L => IN_PKT_BURST_SIZE_L, IN_PKT_RESPONSE_STATUS_H => IN_PKT_RESPONSE_STATUS_H, IN_PKT_RESPONSE_STATUS_L => IN_PKT_RESPONSE_STATUS_L, IN_PKT_TRANS_EXCLUSIVE => IN_PKT_TRANS_EXCLUSIVE, IN_PKT_BURST_TYPE_H => IN_PKT_BURST_TYPE_H, IN_PKT_BURST_TYPE_L => IN_PKT_BURST_TYPE_L, IN_ST_DATA_W => IN_ST_DATA_W, OUT_PKT_ADDR_H => OUT_PKT_ADDR_H, OUT_PKT_ADDR_L => OUT_PKT_ADDR_L, OUT_PKT_DATA_H => OUT_PKT_DATA_H, OUT_PKT_DATA_L => OUT_PKT_DATA_L, OUT_PKT_BYTEEN_H => OUT_PKT_BYTEEN_H, OUT_PKT_BYTEEN_L => OUT_PKT_BYTEEN_L, OUT_PKT_BYTE_CNT_H => OUT_PKT_BYTE_CNT_H, OUT_PKT_BYTE_CNT_L => OUT_PKT_BYTE_CNT_L, OUT_PKT_TRANS_COMPRESSED_READ => OUT_PKT_TRANS_COMPRESSED_READ, OUT_PKT_BURST_SIZE_H => OUT_PKT_BURST_SIZE_H, OUT_PKT_BURST_SIZE_L => OUT_PKT_BURST_SIZE_L, OUT_PKT_RESPONSE_STATUS_H => OUT_PKT_RESPONSE_STATUS_H, OUT_PKT_RESPONSE_STATUS_L => OUT_PKT_RESPONSE_STATUS_L, OUT_PKT_TRANS_EXCLUSIVE => OUT_PKT_TRANS_EXCLUSIVE, OUT_PKT_BURST_TYPE_H => OUT_PKT_BURST_TYPE_H, OUT_PKT_BURST_TYPE_L => OUT_PKT_BURST_TYPE_L, OUT_ST_DATA_W => OUT_ST_DATA_W, ST_CHANNEL_W => ST_CHANNEL_W, OPTIMIZE_FOR_RSP => OPTIMIZE_FOR_RSP, RESPONSE_PATH => RESPONSE_PATH ) port map ( clk => clk, -- clk.clk reset => reset, -- clk_reset.reset in_valid => in_valid, -- sink.valid in_channel => in_channel, -- .channel in_startofpacket => in_startofpacket, -- .startofpacket in_endofpacket => in_endofpacket, -- .endofpacket in_ready => in_ready, -- .ready in_data => in_data, -- .data out_endofpacket => out_endofpacket, -- src.endofpacket out_data => out_data, -- .data out_channel => out_channel, -- .channel out_valid => out_valid, -- .valid out_ready => out_ready, -- .ready out_startofpacket => out_startofpacket, -- .startofpacket in_command_size_data => "000" -- (terminated) ); end architecture rtl; -- of niosii_system_width_adapter
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block EEpkeRyv68cmXBgNTfLO+mYJ25WVbrEwBbppOaWeK6RMl/IG7L6/LrSP7dIMRjhs3qnRYnrzNKmk bEBa7SYyCg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block YbGVmcB5GmKAD/Csxzgliw3PWPy264E7kJSrLM/qBD9S/D49iIvSOD7joJDCqmp+kE2WKcpITB7/ Z86b6JKBRfhlVUKKopSqb1JCVKjO2fVJ78YD5Y+gDNqdxsrvTpbGNnopF2Hcjohs/xa41filVhEb 3IU4w1bxbZsXoHvcwws= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block V0DB/xii2yFJNDHw4f5cdmh55yNtA0H3hcacj+N9zuyvBG5Y6Kl8wsK+MftB5Nc0Y4dmjfuYCXyA bw/Kf9d3oy63o2aU6nJkpFX9sjmcqDx/C0GvQZCpKYchsaljXxKm09D6m6Rl6NAepkTkNhvOA6FB D3aMCBKVcTMb3raMRB1jVuaBmII1fOPeDjwHkraoaJNDWWnTRvoJ+ooM5YM3zytBCO7T6QW1MhZF 11svYlkRaCljZPoxBB3SSf/OsQfJ930WVQaTnXoezl+cDy0QggBF4z1RTcR5arXzU8KSOJrOSURM nN9dsQCrpAsn4azbGoN50/DFM+bgPLFKhII5Yw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block dCuFS27q8ROwMaO3SWXnCgs3XZXadA0pZTO5QXcce1j35xhabMOgpTvOzvBraB3mlKS6f6FJPm8C 14G+6depgIyjv7V2GXfXGAkF9fOGGXLbwahWdCN9SwNTFBUGJO4O3CmdCP0MA1nLxoZf3d1Ca/F7 B4sPu5L0CbKc2DaeM40= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block iK1uLuoWHgfibO2O7nsPODcTxmxxRrAKbpWmTAgnUO7tyIS6cnDsN1SM/TgBHFBRytsawhOj+jyY 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block EEpkeRyv68cmXBgNTfLO+mYJ25WVbrEwBbppOaWeK6RMl/IG7L6/LrSP7dIMRjhs3qnRYnrzNKmk bEBa7SYyCg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block YbGVmcB5GmKAD/Csxzgliw3PWPy264E7kJSrLM/qBD9S/D49iIvSOD7joJDCqmp+kE2WKcpITB7/ Z86b6JKBRfhlVUKKopSqb1JCVKjO2fVJ78YD5Y+gDNqdxsrvTpbGNnopF2Hcjohs/xa41filVhEb 3IU4w1bxbZsXoHvcwws= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block EEpkeRyv68cmXBgNTfLO+mYJ25WVbrEwBbppOaWeK6RMl/IG7L6/LrSP7dIMRjhs3qnRYnrzNKmk bEBa7SYyCg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block YbGVmcB5GmKAD/Csxzgliw3PWPy264E7kJSrLM/qBD9S/D49iIvSOD7joJDCqmp+kE2WKcpITB7/ Z86b6JKBRfhlVUKKopSqb1JCVKjO2fVJ78YD5Y+gDNqdxsrvTpbGNnopF2Hcjohs/xa41filVhEb 3IU4w1bxbZsXoHvcwws= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block EEpkeRyv68cmXBgNTfLO+mYJ25WVbrEwBbppOaWeK6RMl/IG7L6/LrSP7dIMRjhs3qnRYnrzNKmk bEBa7SYyCg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block YbGVmcB5GmKAD/Csxzgliw3PWPy264E7kJSrLM/qBD9S/D49iIvSOD7joJDCqmp+kE2WKcpITB7/ Z86b6JKBRfhlVUKKopSqb1JCVKjO2fVJ78YD5Y+gDNqdxsrvTpbGNnopF2Hcjohs/xa41filVhEb 3IU4w1bxbZsXoHvcwws= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block EEpkeRyv68cmXBgNTfLO+mYJ25WVbrEwBbppOaWeK6RMl/IG7L6/LrSP7dIMRjhs3qnRYnrzNKmk bEBa7SYyCg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block YbGVmcB5GmKAD/Csxzgliw3PWPy264E7kJSrLM/qBD9S/D49iIvSOD7joJDCqmp+kE2WKcpITB7/ Z86b6JKBRfhlVUKKopSqb1JCVKjO2fVJ78YD5Y+gDNqdxsrvTpbGNnopF2Hcjohs/xa41filVhEb 3IU4w1bxbZsXoHvcwws= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block EEpkeRyv68cmXBgNTfLO+mYJ25WVbrEwBbppOaWeK6RMl/IG7L6/LrSP7dIMRjhs3qnRYnrzNKmk bEBa7SYyCg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block YbGVmcB5GmKAD/Csxzgliw3PWPy264E7kJSrLM/qBD9S/D49iIvSOD7joJDCqmp+kE2WKcpITB7/ Z86b6JKBRfhlVUKKopSqb1JCVKjO2fVJ78YD5Y+gDNqdxsrvTpbGNnopF2Hcjohs/xa41filVhEb 3IU4w1bxbZsXoHvcwws= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block EEpkeRyv68cmXBgNTfLO+mYJ25WVbrEwBbppOaWeK6RMl/IG7L6/LrSP7dIMRjhs3qnRYnrzNKmk bEBa7SYyCg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block YbGVmcB5GmKAD/Csxzgliw3PWPy264E7kJSrLM/qBD9S/D49iIvSOD7joJDCqmp+kE2WKcpITB7/ Z86b6JKBRfhlVUKKopSqb1JCVKjO2fVJ78YD5Y+gDNqdxsrvTpbGNnopF2Hcjohs/xa41filVhEb 3IU4w1bxbZsXoHvcwws= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block EEpkeRyv68cmXBgNTfLO+mYJ25WVbrEwBbppOaWeK6RMl/IG7L6/LrSP7dIMRjhs3qnRYnrzNKmk bEBa7SYyCg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block YbGVmcB5GmKAD/Csxzgliw3PWPy264E7kJSrLM/qBD9S/D49iIvSOD7joJDCqmp+kE2WKcpITB7/ Z86b6JKBRfhlVUKKopSqb1JCVKjO2fVJ78YD5Y+gDNqdxsrvTpbGNnopF2Hcjohs/xa41filVhEb 3IU4w1bxbZsXoHvcwws= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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-- ============================================== -- Copyright © 2014 Ali M. Al-Bayaty -- -- Video-Game-Engine is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- any later version. -- -- Video-Game-Engine is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- ============================================== -- -- Video Game Engine Project -- ( EDK: VGA 40x30 Resolution, Timer Helper VHDL ) -- -- MSEE student: Ali M. Al-Bayaty -- EE659: System-On-Chip -- Personal website: <http://albayaty.github.io/> -- Source code link: <https://github.com/albayaty/Video-Game-Engine.git> -- -- ============================================== -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity vgatimehelper is port( clk, reset: in std_logic; --send in 50mhz clock hsync, vsync: out std_logic; video_on, p_tick: out std_logic; --p_tick is the 25mhz clock you will --not need to use, video_on is when you --can display a pixel pixel_x, pixel_y: out std_logic_vector (9 downto 0) ); end vgatimehelper; architecture arch of vgatimehelper is -- VGA 640-by-480 sync parameters constant HD: integer:=640; --horizontal display area constant HF: integer:=16 ; --h. front porch constant HB: integer:=48 ; --h. back porch constant HR: integer:=96 ; --h. retrace constant VD: integer:=480; --vertical display area constant VF: integer:=10; --v. front porch constant VB: integer:=33; --v. back porch constant VR: integer:=2; --v. retrace -- mod-2 counter signal mod2_reg, mod2_next: std_logic; -- sync counters signal v_count_reg, v_count_next: unsigned(9 downto 0); signal h_count_reg, h_count_next: unsigned(9 downto 0); -- output buffer signal v_sync_reg, h_sync_reg: std_logic; signal v_sync_next, h_sync_next: std_logic; -- status signal signal h_end, v_end, pixel_tick: std_logic; begin -- registers process (clk,reset) begin if reset='1' then mod2_reg <= '0'; v_count_reg <= (others=>'0'); h_count_reg <= (others=>'0'); v_sync_reg <= '0'; h_sync_reg <= '0'; elsif (clk'event and clk='1') then mod2_reg <= mod2_next; v_count_reg <= v_count_next; h_count_reg <= h_count_next; v_sync_reg <= v_sync_next; h_sync_reg <= h_sync_next; end if; end process; -- mod-2 circuit to generate 25 MHz enable tick mod2_next <= not mod2_reg; -- 25 MHz pixel tick pixel_tick <= '1' when mod2_reg='1' else '0'; -- status h_end <= -- end of horizontal counter '1' when h_count_reg=(HD+HF+HB+HR-1) else --799 '0'; v_end <= -- end of vertical counter '1' when v_count_reg=(VD+VF+VB+VR-1) else --524 '0'; -- mod-800 horizontal sync counter process (h_count_reg,h_end,pixel_tick) begin if pixel_tick='1' then -- 25 MHz tick if h_end='1' then h_count_next <= (others=>'0'); else h_count_next <= h_count_reg + 1; end if; else h_count_next <= h_count_reg; end if; end process; -- mod-525 vertical sync counter process (v_count_reg,h_end,v_end,pixel_tick) begin if pixel_tick='1' and h_end='1' then if (v_end='1') then v_count_next <= (others=>'0'); else v_count_next <= v_count_reg + 1; end if; else v_count_next <= v_count_reg; end if; end process; -- horizontal and vertical sync, buffered to avoid glitch h_sync_next <= '1' when (h_count_reg>=(HD+HF)) --656 and (h_count_reg<=(HD+HF+HR-1)) else --751 '0'; v_sync_next <= '1' when (v_count_reg>=(VD+VF)) --490 and (v_count_reg<=(VD+VF+VR-1)) else --491 '0'; -- video on/off video_on <= '1' when (h_count_reg<HD) and (v_count_reg<VD) else '0'; -- output signal hsync <= h_sync_reg; vsync <= v_sync_reg; pixel_x <= std_logic_vector(h_count_reg); pixel_y <= std_logic_vector(v_count_reg); p_tick <= pixel_tick; end arch;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity myguarded is Port ( i1 : in std_logic; i2 : in std_logic; con : in std_logic; o1 : out std_logic; o2 : out std_logic); end myguarded; architecture Behavioral of myguarded is begin b: block( con = '1' ) begin o1 <= guarded i1; o2 <= i2; end block b; end Behavioral;
library verilog; use verilog.vl_types.all; entity nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2_MAC2S_0 is port( clk : in vl_logic; ce : in vl_logic; a : in vl_logic_vector(15 downto 0); b : in vl_logic_vector(7 downto 0); p : out vl_logic_vector(23 downto 0) ); end nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2_MAC2S_0;
-- ------------------------------------------------------------------------------------------- -- Copyright © 2010-2011, Xilinx, Inc. -- This file contains confidential and proprietary information of Xilinx, Inc. and is -- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------- -- -- Disclaimer: -- This disclaimer is not a license and does not grant any rights to the materials -- distributed herewith. Except as otherwise provided in a valid license issued to -- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE -- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY -- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, -- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, -- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable -- (whether in contract or tort, including negligence, or under any other theory -- of liability) for any loss or damage of any kind or nature related to, arising -- under or in connection with these materials, including for any direct, or any -- indirect, special, incidental, or consequential loss or damage (including loss -- of data, profits, goodwill, or any type of loss or damage suffered as a result -- of any action brought by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail-safe, or for use in any -- application requiring fail-safe performance, such as life-support or safety -- devices or systems, Class III medical devices, nuclear facilities, applications -- related to the deployment of airbags, or any other applications that could lead -- to death, personal injury, or severe property or environmental damage -- (individually and collectively, "Critical Applications"). Customer assumes the -- sole risk and liability of any use of Xilinx products in Critical Applications, -- subject only to applicable laws and regulations governing limitations on product -- liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------------------- -- -- -- Definition of a program memory for KCPSM6 including generic parameters for the -- convenient selection of device family, program memory size and the ability to include -- the JTAG Loader hardware for rapid software development. -- -- This file is primarily for use during code development and it is recommended that the -- appropriate simplified program memory definition be used in a final production design. -- -- Generic Values Comments -- Parameter Supported -- -- C_FAMILY "S6" Spartan-6 device -- "V6" Virtex-6 device -- "7S" 7-Series device -- (Artix-7, Kintex-7 or Virtex-7) -- -- C_RAM_SIZE_KWORDS 1, 2 or 4 Size of program memory in K-instructions -- '4' is not supported for 'S6'. -- -- C_JTAG_LOADER_ENABLE 0 or 1 Set to '1' to include JTAG Loader -- -- Notes -- -- If your design contains MULTIPLE KCPSM6 instances then only one should have the -- JTAG Loader enabled at a time (i.e. make sure that C_JTAG_LOADER_ENABLE is only set to -- '1' on one instance of the program memory). Advanced users may be interested to know -- that it is possible to connect JTAG Loader to multiple memories and then to use the -- JTAG Loader utility to specify which memory contents are to be modified. However, -- this scheme does require some effort to set up and the additional connectivity of the -- multiple BRAMs can impact the placement, routing and performance of the complete -- design. Please contact the author at Xilinx for more detailed information. -- -- Regardless of the size of program memory specified by C_RAM_SIZE_KWORDS, the complete -- 12-bit address bus is connected to KCPSM6. This enables the generic to be modified -- without requiring changes to the fundamental hardware definition. However, when the -- program memory is 1K then only the lower 10-bits of the address are actually used and -- the valid address range is 000 to 3FF hex. Likewise, for a 2K program only the lower -- 11-bits of the address are actually used and the valid address range is 000 to 7FF hex. -- -- Programs are stored in Block Memory (BRAM) and the number of BRAM used depends on the -- size of the program and the device family. -- -- In a Spartan-6 device a BRAM is capable of holding 1K instructions. Hence a 2K program -- will require 2 BRAMs to be used. Whilst it is possible to implement a 4K program in a -- Spartan-6 device this is a less natural fit within the architecture and either requires -- 4 BRAMs and a small amount of logic resulting in a lower performance or 5 BRAMs when -- performance is a critical factor. Due to these additional considerations this file -- does not support the selection of 4K when using Spartan-6. If one of these special -- cases is required then please contact the author at Xilinx to discuss and request a -- specific 'ROM_form' template that will meet your requirements. Note that whilst it -- it is possible to divide a Spartan-6 BRAM into 2 smaller memories which would each hold -- a program up to only 512 instructions there is a silicon errata which makes unsuitable. -- -- In a Virtex-6 or any 7-Series device a BRAM is capable of holding 2K instructions so -- obviously a 2K program requires only a single BRAM. Each BRAM can also be divided into -- 2 smaller memories supporting programs of 1K in half of a 36k-bit BRAM (generally reported -- as being an 18k-bit BRAM). For a program of 4K instructions 2 BRAMs are required. -- -- -- Program defined by 'U:\althouse\xcs_dev\groups\paeg_comm\xt_connectivity_trd\design_vc709_phase2\source\clock_control\utils\clock_control_program.psm'. -- -- Generated by KCPSM6 Assembler: 18 Sep 2012 - 15:22:35. -- -- Assembler used ROM_form template: 16th August 2011 -- -- Standard IEEE libraries -- -- package jtag_loader_pkg is function addr_width_calc (size_in_k: integer) return integer; end jtag_loader_pkg; -- package body jtag_loader_pkg is function addr_width_calc (size_in_k: integer) return integer is begin if (size_in_k = 1) then return 10; elsif (size_in_k = 2) then return 11; elsif (size_in_k = 4) then return 12; else report "Invalid BlockRAM size. Please set to 1, 2 or 4 K words." severity FAILURE; end if; return 0; end function addr_width_calc; end package body; -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.jtag_loader_pkg.ALL; -- -- The Unisim Library is used to define Xilinx primitives. It is also used during -- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd -- library unisim; use unisim.vcomponents.all; -- -- entity clock_control_program is generic( C_FAMILY : string := "S6"; C_RAM_SIZE_KWORDS : integer := 1; C_JTAG_LOADER_ENABLE : integer := 0); Port ( address : in std_logic_vector(11 downto 0); instruction : out std_logic_vector(17 downto 0); enable : in std_logic; rdl : out std_logic; clk : in std_logic); end clock_control_program; -- architecture low_level_definition of clock_control_program is -- signal address_a : std_logic_vector(15 downto 0); signal data_in_a : std_logic_vector(35 downto 0); signal data_out_a : std_logic_vector(35 downto 0); signal data_out_a_l : std_logic_vector(35 downto 0); signal data_out_a_h : std_logic_vector(35 downto 0); signal address_b : std_logic_vector(15 downto 0); signal data_in_b : std_logic_vector(35 downto 0); signal data_in_b_l : std_logic_vector(35 downto 0); signal data_out_b : std_logic_vector(35 downto 0); signal data_out_b_l : std_logic_vector(35 downto 0); signal data_in_b_h : std_logic_vector(35 downto 0); signal data_out_b_h : std_logic_vector(35 downto 0); signal enable_b : std_logic; signal clk_b : std_logic; signal we_b : std_logic_vector(7 downto 0); -- signal jtag_addr : std_logic_vector(11 downto 0); signal jtag_we : std_logic; signal jtag_clk : std_logic; signal jtag_din : std_logic_vector(17 downto 0); signal jtag_dout : std_logic_vector(17 downto 0); signal jtag_dout_1 : std_logic_vector(17 downto 0); signal jtag_en : std_logic_vector(0 downto 0); -- signal picoblaze_reset : std_logic_vector(0 downto 0); signal rdl_bus : std_logic_vector(0 downto 0); -- constant BRAM_ADDRESS_WIDTH : integer := addr_width_calc(C_RAM_SIZE_KWORDS); -- -- component jtag_loader_6 generic( C_JTAG_LOADER_ENABLE : integer := 1; C_FAMILY : string := "V6"; C_NUM_PICOBLAZE : integer := 1; C_BRAM_MAX_ADDR_WIDTH : integer := 10; C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18; C_JTAG_CHAIN : integer := 2; C_ADDR_WIDTH_0 : integer := 10; C_ADDR_WIDTH_1 : integer := 10; C_ADDR_WIDTH_2 : integer := 10; C_ADDR_WIDTH_3 : integer := 10; C_ADDR_WIDTH_4 : integer := 10; C_ADDR_WIDTH_5 : integer := 10; C_ADDR_WIDTH_6 : integer := 10; C_ADDR_WIDTH_7 : integer := 10); port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); jtag_din : out STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_addr : out STD_LOGIC_VECTOR(C_BRAM_MAX_ADDR_WIDTH-1 downto 0); jtag_clk : out std_logic; jtag_we : out std_logic; jtag_dout_0 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_1 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_2 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_3 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_4 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_5 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_6 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_7 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0)); end component; -- begin -- -- ram_1k_generate : if (C_RAM_SIZE_KWORDS = 1) generate s6: if (C_FAMILY = "S6") generate -- address_a(13 downto 0) <= address(9 downto 0) & "0000"; instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0); data_in_a <= "0000000000000000000000000000000000" & address(11 downto 10); jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0); -- no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0); address_b(13 downto 0) <= "00000000000000"; we_b(3 downto 0) <= "0000"; enable_b <= '0'; rdl <= '0'; clk_b <= '0'; end generate no_loader; -- loader : if (C_JTAG_LOADER_ENABLE = 1) generate data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0); address_b(13 downto 0) <= jtag_addr(9 downto 0) & "0000"; we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we; enable_b <= jtag_en(0); rdl <= rdl_bus(0); clk_b <= jtag_clk; end generate loader; -- kcpsm6_rom: RAMB16BWER generic map ( DATA_WIDTH_A => 18, DOA_REG => 0, EN_RSTRAM_A => FALSE, INIT_A => X"000000000", RST_PRIORITY_A => "CE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", DATA_WIDTH_B => 18, DOB_REG => 0, EN_RSTRAM_B => FALSE, INIT_B => X"000000000", RST_PRIORITY_B => "CE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", RSTTYPE => "SYNC", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "SPARTAN6", INIT_00 => X"1B03008D1D121B02008D1DE41B01008D1D541B00004D1D8000B40049004616FF", INIT_01 => X"1D001B1F008D1DA01B19008D1D401B0B008D1D081B0A008D1D921B04008D1D15", INIT_02 => X"008D1DEF1B2A008D1D491B29008D1DC21B28008D1D031B21008D1D001B20008D", INIT_03 => X"1B30008D1D771B2F008D1D001B2E008D1D0B1B2D008D1D771B2C008D1D001B2B", INIT_04 => X"157400B800B4204C5000D60416FF5000D6041600204C008D1D401B88008D1D0B", INIT_05 => X"00DC00C54507157400B800B4500000BF900000DC00C505D0900000DC00C54506", INIT_06 => X"00DC00C505B0900000DC00C54506155D00B800B4500000BF00DA0D5000CF9000", INIT_07 => X"00C505B0900000DC00C54506155D00B800B4500000BF900000DC00C505D09000", INIT_08 => X"156800B800B4500000BF00DA0D5000CF900000DC00C54507155D00B8900000DC", INIT_09 => X"00B800B4500000BF900000DC00C505D0900000DC00C505B0900000DC00C54506", INIT_0A => X"00CF900000DC00C54507156800B8900000DC00C505B0900000DC00C545061568", INIT_0B => X"00EA500000DF00FC00EA00FB00E400EE5000DF085F021F01500000BF00DA0D50", INIT_0C => X"110820C69000410E00D500EE20CB00EA60CAC5101180500000EE00FC00E400FB", INIT_0D => X"10FE5000D50100F120D500EE500000DF00FC00E400FB00EA500060D0910100F1", INIT_0E => X"DF085F025000DF082F0010FD500020E6D0019006DF085F01500000FBDF082F00", INIT_0F => X"01010101010101010101500000DF00FE4500D002900600FE00E400FB00EE5000", INIT_10 => X"00000000000000000000000000000000000000000000500061029001100B5000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_00 => X"8E92ABA3A3A4AA8BA4AAE8E92AA28A08208208208208208208208208208208A8", INITP_01 => X"AAAA42AA8A0B08A822AAAAB62DAAC2AAAAAAA0A8BA4BA3A4AAE8E8E92AA2E92E", INITP_02 => X"00000000000000000000000000000000000000000000000000000000000002D2", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000") port map( ADDRA => address_a(13 downto 0), ENA => enable, CLKA => clk, DOA => data_out_a(31 downto 0), DOPA => data_out_a(35 downto 32), DIA => data_in_a(31 downto 0), DIPA => data_in_a(35 downto 32), WEA => "0000", REGCEA => '0', RSTA => '0', ADDRB => address_b(13 downto 0), ENB => enable_b, CLKB => clk_b, DOB => data_out_b(31 downto 0), DOPB => data_out_b(35 downto 32), DIB => data_in_b(31 downto 0), DIPB => data_in_b(35 downto 32), WEB => we_b(3 downto 0), REGCEB => '0', RSTB => '0'); -- end generate s6; -- -- v6 : if (C_FAMILY = "V6") generate -- address_a(13 downto 0) <= address(9 downto 0) & "0000"; instruction <= data_out_a(17 downto 0); data_in_a(17 downto 0) <= "0000000000000000" & address(11 downto 10); jtag_dout <= data_out_b(17 downto 0); -- no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate data_in_b(17 downto 0) <= data_out_b(17 downto 0); address_b(13 downto 0) <= "00000000000000"; we_b(3 downto 0) <= "0000"; enable_b <= '0'; rdl <= '0'; clk_b <= '0'; end generate no_loader; -- loader : if (C_JTAG_LOADER_ENABLE = 1) generate data_in_b(17 downto 0) <= jtag_din(17 downto 0); address_b(13 downto 0) <= jtag_addr(9 downto 0) & "0000"; we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we; enable_b <= jtag_en(0); rdl <= rdl_bus(0); clk_b <= jtag_clk; end generate loader; -- kcpsm6_rom: RAMB18E1 generic map ( READ_WIDTH_A => 18, WRITE_WIDTH_A => 18, DOA_REG => 0, INIT_A => "000000000000000000", RSTREG_PRIORITY_A => "REGCE", SRVAL_A => X"000000000000000000", WRITE_MODE_A => "WRITE_FIRST", READ_WIDTH_B => 18, WRITE_WIDTH_B => 18, DOB_REG => 0, INIT_B => X"000000000000000000", RSTREG_PRIORITY_B => "REGCE", SRVAL_B => X"000000000000000000", WRITE_MODE_B => "WRITE_FIRST", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", SIM_DEVICE => "VIRTEX6", INIT_00 => X"1B03008D1D121B02008D1DE41B01008D1D541B00004D1D8000B40049004616FF", INIT_01 => X"1D001B1F008D1DA01B19008D1D401B0B008D1D081B0A008D1D921B04008D1D15", INIT_02 => X"008D1DEF1B2A008D1D491B29008D1DC21B28008D1D031B21008D1D001B20008D", INIT_03 => X"1B30008D1D771B2F008D1D001B2E008D1D0B1B2D008D1D771B2C008D1D001B2B", INIT_04 => X"157400B800B4204C5000D60416FF5000D6041600204C008D1D401B88008D1D0B", INIT_05 => X"00DC00C54507157400B800B4500000BF900000DC00C505D0900000DC00C54506", INIT_06 => X"00DC00C505B0900000DC00C54506155D00B800B4500000BF00DA0D5000CF9000", INIT_07 => X"00C505B0900000DC00C54506155D00B800B4500000BF900000DC00C505D09000", INIT_08 => X"156800B800B4500000BF00DA0D5000CF900000DC00C54507155D00B8900000DC", INIT_09 => X"00B800B4500000BF900000DC00C505D0900000DC00C505B0900000DC00C54506", INIT_0A => X"00CF900000DC00C54507156800B8900000DC00C505B0900000DC00C545061568", INIT_0B => X"00EA500000DF00FC00EA00FB00E400EE5000DF085F021F01500000BF00DA0D50", INIT_0C => X"110820C69000410E00D500EE20CB00EA60CAC5101180500000EE00FC00E400FB", INIT_0D => X"10FE5000D50100F120D500EE500000DF00FC00E400FB00EA500060D0910100F1", INIT_0E => X"DF085F025000DF082F0010FD500020E6D0019006DF085F01500000FBDF082F00", INIT_0F => X"01010101010101010101500000DF00FE4500D002900600FE00E400FB00EE5000", INIT_10 => X"00000000000000000000000000000000000000000000500061029001100B5000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_00 => X"8E92ABA3A3A4AA8BA4AAE8E92AA28A08208208208208208208208208208208A8", INITP_01 => X"AAAA42AA8A0B08A822AAAAB62DAAC2AAAAAAA0A8BA4BA3A4AAE8E8E92AA2E92E", INITP_02 => X"00000000000000000000000000000000000000000000000000000000000002D2", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000") port map( ADDRARDADDR => address_a(13 downto 0), ENARDEN => enable, CLKARDCLK => clk, DOADO => data_out_a(15 downto 0), DOPADOP => data_out_a(17 downto 16), DIADI => data_in_a(15 downto 0), DIPADIP => data_in_a(17 downto 16), WEA => "00", REGCEAREGCE => '0', RSTRAMARSTRAM => '0', RSTREGARSTREG => '0', ADDRBWRADDR => address_b(13 downto 0), ENBWREN => enable_b, CLKBWRCLK => clk_b, DOBDO => data_out_b(15 downto 0), DOPBDOP => data_out_b(17 downto 16), DIBDI => data_in_b(15 downto 0), DIPBDIP => data_in_b(17 downto 16), WEBWE => we_b(3 downto 0), REGCEB => '0', RSTRAMB => '0', RSTREGB => '0'); -- end generate v6; -- -- akv7 : if (C_FAMILY = "7S") generate -- address_a(13 downto 0) <= address(9 downto 0) & "0000"; instruction <= data_out_a(17 downto 0); data_in_a(17 downto 0) <= "0000000000000000" & address(11 downto 10); jtag_dout <= data_out_b(17 downto 0); -- no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate data_in_b(17 downto 0) <= data_out_b(17 downto 0); address_b(13 downto 0) <= "00000000000000"; we_b(3 downto 0) <= "0000"; enable_b <= '0'; rdl <= '0'; clk_b <= '0'; end generate no_loader; -- loader : if (C_JTAG_LOADER_ENABLE = 1) generate data_in_b(17 downto 0) <= jtag_din(17 downto 0); address_b(13 downto 0) <= jtag_addr(9 downto 0) & "0000"; we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we; enable_b <= jtag_en(0); rdl <= rdl_bus(0); clk_b <= jtag_clk; end generate loader; -- kcpsm6_rom: RAMB18E1 generic map ( READ_WIDTH_A => 18, WRITE_WIDTH_A => 18, DOA_REG => 0, INIT_A => "000000000000000000", RSTREG_PRIORITY_A => "REGCE", SRVAL_A => X"000000000000000000", WRITE_MODE_A => "WRITE_FIRST", READ_WIDTH_B => 18, WRITE_WIDTH_B => 18, DOB_REG => 0, INIT_B => X"000000000000000000", RSTREG_PRIORITY_B => "REGCE", SRVAL_B => X"000000000000000000", WRITE_MODE_B => "WRITE_FIRST", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", SIM_DEVICE => "7SERIES", INIT_00 => X"1B03008D1D121B02008D1DE41B01008D1D541B00004D1D8000B40049004616FF", INIT_01 => X"1D001B1F008D1DA01B19008D1D401B0B008D1D081B0A008D1D921B04008D1D15", INIT_02 => X"008D1DEF1B2A008D1D491B29008D1DC21B28008D1D031B21008D1D001B20008D", INIT_03 => X"1B30008D1D771B2F008D1D001B2E008D1D0B1B2D008D1D771B2C008D1D001B2B", INIT_04 => X"157400B800B4204C5000D60416FF5000D6041600204C008D1D401B88008D1D0B", INIT_05 => X"00DC00C54507157400B800B4500000BF900000DC00C505D0900000DC00C54506", INIT_06 => X"00DC00C505B0900000DC00C54506155D00B800B4500000BF00DA0D5000CF9000", INIT_07 => X"00C505B0900000DC00C54506155D00B800B4500000BF900000DC00C505D09000", INIT_08 => X"156800B800B4500000BF00DA0D5000CF900000DC00C54507155D00B8900000DC", INIT_09 => X"00B800B4500000BF900000DC00C505D0900000DC00C505B0900000DC00C54506", INIT_0A => X"00CF900000DC00C54507156800B8900000DC00C505B0900000DC00C545061568", INIT_0B => X"00EA500000DF00FC00EA00FB00E400EE5000DF085F021F01500000BF00DA0D50", INIT_0C => X"110820C69000410E00D500EE20CB00EA60CAC5101180500000EE00FC00E400FB", INIT_0D => X"10FE5000D50100F120D500EE500000DF00FC00E400FB00EA500060D0910100F1", INIT_0E => X"DF085F025000DF082F0010FD500020E6D0019006DF085F01500000FBDF082F00", INIT_0F => X"01010101010101010101500000DF00FE4500D002900600FE00E400FB00EE5000", INIT_10 => X"00000000000000000000000000000000000000000000500061029001100B5000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_00 => X"8E92ABA3A3A4AA8BA4AAE8E92AA28A08208208208208208208208208208208A8", INITP_01 => X"AAAA42AA8A0B08A822AAAAB62DAAC2AAAAAAA0A8BA4BA3A4AAE8E8E92AA2E92E", INITP_02 => X"00000000000000000000000000000000000000000000000000000000000002D2", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000") port map( ADDRARDADDR => address_a(13 downto 0), ENARDEN => enable, CLKARDCLK => clk, DOADO => data_out_a(15 downto 0), DOPADOP => data_out_a(17 downto 16), DIADI => data_in_a(15 downto 0), DIPADIP => data_in_a(17 downto 16), WEA => "00", REGCEAREGCE => '0', RSTRAMARSTRAM => '0', RSTREGARSTREG => '0', ADDRBWRADDR => address_b(13 downto 0), ENBWREN => enable_b, CLKBWRCLK => clk_b, DOBDO => data_out_b(15 downto 0), DOPBDOP => data_out_b(17 downto 16), DIBDI => data_in_b(15 downto 0), DIPBDIP => data_in_b(17 downto 16), WEBWE => we_b(3 downto 0), REGCEB => '0', RSTRAMB => '0', RSTREGB => '0'); -- end generate akv7; -- end generate ram_1k_generate; -- -- -- ram_2k_generate : if (C_RAM_SIZE_KWORDS = 2) generate -- -- s6: if (C_FAMILY = "S6") generate -- address_a(13 downto 0) <= address(10 downto 0) & "000"; instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0); data_in_a <= "00000000000000000000000000000000000" & address(11); jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0); -- no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0); data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0); address_b(13 downto 0) <= "00000000000000"; we_b(3 downto 0) <= "0000"; enable_b <= '0'; rdl <= '0'; clk_b <= '0'; end generate no_loader; -- loader : if (C_JTAG_LOADER_ENABLE = 1) generate data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9); data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0); address_b(13 downto 0) <= jtag_addr(10 downto 0) & "000"; we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we; enable_b <= jtag_en(0); rdl <= rdl_bus(0); clk_b <= jtag_clk; end generate loader; -- kcpsm6_rom_l: RAMB16BWER generic map ( DATA_WIDTH_A => 9, DOA_REG => 0, EN_RSTRAM_A => FALSE, INIT_A => X"000000000", RST_PRIORITY_A => "CE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", DATA_WIDTH_B => 9, DOB_REG => 0, EN_RSTRAM_B => FALSE, INIT_B => X"000000000", RST_PRIORITY_B => "CE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", RSTTYPE => "SYNC", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "SPARTAN6", INIT_00 => X"001F8DA0198D400B8D080A8D92048D15038D12028DE4018D54004D80B44946FF", INIT_01 => X"308D772F8D002E8D0B2D8D772C8D002B8DEF2A8D49298DC2288D03218D00208D", INIT_02 => X"DCC50774B8B400BF00DCC5D000DCC50674B8B44C0004FF0004004C8D40888D0B", INIT_03 => X"C5B000DCC5065DB8B400BF00DCC5D000DCC5B000DCC5065DB8B400BFDA50CF00", INIT_04 => X"B8B400BF00DCC5D000DCC5B000DCC50668B8B400BFDA50CF00DCC5075DB800DC", INIT_05 => X"EA00DFFCEAFBE4EE0008020100BFDA50CF00DCC50768B800DCC5B000DCC50668", INIT_06 => X"FE0001F1D5EE00DFFCE4FBEA00D001F108C6000ED5EECBEACA108000EEFCE4FB", INIT_07 => X"010101010100DFFE000206FEE4FBEE000802000800FD00E60106080100FB0800", INIT_08 => X"0000000000000000000000000000000000000000000000000000000002010B00", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_00 => X"F880D8332002906000710C2301118218460223043011800DB6DB6DB6DB6DB6D0", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000008", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000") port map( ADDRA => address_a(13 downto 0), ENA => enable, CLKA => clk, DOA => data_out_a_l(31 downto 0), DOPA => data_out_a_l(35 downto 32), DIA => data_in_a(31 downto 0), DIPA => data_in_a(35 downto 32), WEA => "0000", REGCEA => '0', RSTA => '0', ADDRB => address_b(13 downto 0), ENB => enable_b, CLKB => clk_b, DOB => data_out_b_l(31 downto 0), DOPB => data_out_b_l(35 downto 32), DIB => data_in_b_l(31 downto 0), DIPB => data_in_b_l(35 downto 32), WEB => we_b(3 downto 0), REGCEB => '0', RSTB => '0'); -- kcpsm6_rom_h: RAMB16BWER generic map ( DATA_WIDTH_A => 9, DOA_REG => 0, EN_RSTRAM_A => FALSE, INIT_A => X"000000000", RST_PRIORITY_A => "CE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", DATA_WIDTH_B => 9, DOB_REG => 0, EN_RSTRAM_B => FALSE, INIT_B => X"000000000", RST_PRIORITY_B => "CE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", RSTTYPE => "SYNC", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "SPARTAN6", INIT_00 => X"0E0D000E0D000E0D000E0D000E0D000E0D000E0D000E0D000E0D000E0000000B", INIT_01 => X"0D000E0D000E0D000E0D000E0D000E0D000E0D000E0D000E0D000E0D000E0D00", INIT_02 => X"0000A20A00002800C8000002C80000A20A000010286B0B286B0B10000E0D000E", INIT_03 => X"0002C80000A20A00002800C8000002C8000002C80000A20A00002800000600C8", INIT_04 => X"00002800C8000002C8000002C80000A20A00002800000600C80000A20A00C800", INIT_05 => X"0028000000000000286F2F0F2800000600C80000A20A00C8000002C80000A20A", INIT_06 => X"08286A00100028000000000028B0C8000810C8A000001000B062082800000000", INIT_07 => X"0000000000280000A2684800000000286F2F286F1708289068486F2F28006F17", INIT_08 => X"00000000000000000000000000000000000000000000000000000028B0C80828", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_00 => X"FF1FB32E5FFD6F9FFFCEF3DCFEEE7DE7B9FDDCFBCFEE7DB2492492492492492E", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000019", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000") port map( ADDRA => address_a(13 downto 0), ENA => enable, CLKA => clk, DOA => data_out_a_h(31 downto 0), DOPA => data_out_a_h(35 downto 32), DIA => data_in_a(31 downto 0), DIPA => data_in_a(35 downto 32), WEA => "0000", REGCEA => '0', RSTA => '0', ADDRB => address_b(13 downto 0), ENB => enable_b, CLKB => clk_b, DOB => data_out_b_h(31 downto 0), DOPB => data_out_b_h(35 downto 32), DIB => data_in_b_h(31 downto 0), DIPB => data_in_b_h(35 downto 32), WEB => we_b(3 downto 0), REGCEB => '0', RSTB => '0'); -- end generate s6; -- -- v6 : if (C_FAMILY = "V6") generate -- address_a <= '0' & address(10 downto 0) & "0000"; instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0); data_in_a <= "00000000000000000000000000000000000" & address(11); jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0); -- no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0); address_b <= "0000000000000000"; we_b <= "00000000"; enable_b <= '0'; rdl <= '0'; clk_b <= '0'; end generate no_loader; -- loader : if (C_JTAG_LOADER_ENABLE = 1) generate data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0); address_b <= '0' & jtag_addr(10 downto 0) & "0000"; we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we; enable_b <= jtag_en(0); rdl <= rdl_bus(0); clk_b <= jtag_clk; end generate loader; -- kcpsm6_rom: RAMB36E1 generic map ( READ_WIDTH_A => 18, WRITE_WIDTH_A => 18, DOA_REG => 0, INIT_A => X"000000000", RSTREG_PRIORITY_A => "REGCE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", READ_WIDTH_B => 18, WRITE_WIDTH_B => 18, DOB_REG => 0, INIT_B => X"000000000", RSTREG_PRIORITY_B => "REGCE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", EN_ECC_READ => FALSE, EN_ECC_WRITE => FALSE, RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", SIM_DEVICE => "VIRTEX6", INIT_00 => X"1B03008D1D121B02008D1DE41B01008D1D541B00004D1D8000B40049004616FF", INIT_01 => X"1D001B1F008D1DA01B19008D1D401B0B008D1D081B0A008D1D921B04008D1D15", INIT_02 => X"008D1DEF1B2A008D1D491B29008D1DC21B28008D1D031B21008D1D001B20008D", INIT_03 => X"1B30008D1D771B2F008D1D001B2E008D1D0B1B2D008D1D771B2C008D1D001B2B", INIT_04 => X"157400B800B4204C5000D60416FF5000D6041600204C008D1D401B88008D1D0B", INIT_05 => X"00DC00C54507157400B800B4500000BF900000DC00C505D0900000DC00C54506", INIT_06 => X"00DC00C505B0900000DC00C54506155D00B800B4500000BF00DA0D5000CF9000", INIT_07 => X"00C505B0900000DC00C54506155D00B800B4500000BF900000DC00C505D09000", INIT_08 => X"156800B800B4500000BF00DA0D5000CF900000DC00C54507155D00B8900000DC", INIT_09 => X"00B800B4500000BF900000DC00C505D0900000DC00C505B0900000DC00C54506", INIT_0A => X"00CF900000DC00C54507156800B8900000DC00C505B0900000DC00C545061568", INIT_0B => X"00EA500000DF00FC00EA00FB00E400EE5000DF085F021F01500000BF00DA0D50", INIT_0C => X"110820C69000410E00D500EE20CB00EA60CAC5101180500000EE00FC00E400FB", INIT_0D => X"10FE5000D50100F120D500EE500000DF00FC00E400FB00EA500060D0910100F1", INIT_0E => X"DF085F025000DF082F0010FD500020E6D0019006DF085F01500000FBDF082F00", INIT_0F => X"01010101010101010101500000DF00FE4500D002900600FE00E400FB00EE5000", INIT_10 => X"00000000000000000000000000000000000000000000500061029001100B5000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_00 => X"8E92ABA3A3A4AA8BA4AAE8E92AA28A08208208208208208208208208208208A8", INITP_01 => X"AAAA42AA8A0B08A822AAAAB62DAAC2AAAAAAA0A8BA4BA3A4AAE8E8E92AA2E92E", INITP_02 => X"00000000000000000000000000000000000000000000000000000000000002D2", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000") port map( ADDRARDADDR => address_a, ENARDEN => enable, CLKARDCLK => clk, DOADO => data_out_a(31 downto 0), DOPADOP => data_out_a(35 downto 32), DIADI => data_in_a(31 downto 0), DIPADIP => data_in_a(35 downto 32), WEA => "0000", REGCEAREGCE => '0', RSTRAMARSTRAM => '0', RSTREGARSTREG => '0', ADDRBWRADDR => address_b, ENBWREN => enable_b, CLKBWRCLK => clk_b, DOBDO => data_out_b(31 downto 0), DOPBDOP => data_out_b(35 downto 32), DIBDI => data_in_b(31 downto 0), DIPBDIP => data_in_b(35 downto 32), WEBWE => we_b, REGCEB => '0', RSTRAMB => '0', RSTREGB => '0', CASCADEINA => '0', CASCADEINB => '0', INJECTDBITERR => '0', INJECTSBITERR => '0'); -- end generate v6; -- -- akv7 : if (C_FAMILY = "7S") generate -- address_a <= '0' & address(10 downto 0) & "0000"; instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0); data_in_a <= "00000000000000000000000000000000000" & address(11); jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0); -- no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0); address_b <= "0000000000000000"; we_b <= "00000000"; enable_b <= '0'; rdl <= '0'; clk_b <= '0'; end generate no_loader; -- loader : if (C_JTAG_LOADER_ENABLE = 1) generate data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0); address_b <= '0' & jtag_addr(10 downto 0) & "0000"; we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we; enable_b <= jtag_en(0); rdl <= rdl_bus(0); clk_b <= jtag_clk; end generate loader; -- kcpsm6_rom: RAMB36E1 generic map ( READ_WIDTH_A => 18, WRITE_WIDTH_A => 18, DOA_REG => 0, INIT_A => X"000000000", RSTREG_PRIORITY_A => "REGCE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", READ_WIDTH_B => 18, WRITE_WIDTH_B => 18, DOB_REG => 0, INIT_B => X"000000000", RSTREG_PRIORITY_B => "REGCE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", EN_ECC_READ => FALSE, EN_ECC_WRITE => FALSE, RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", SIM_DEVICE => "7SERIES", INIT_00 => X"1B03008D1D121B02008D1DE41B01008D1D541B00004D1D8000B40049004616FF", INIT_01 => X"1D001B1F008D1DA01B19008D1D401B0B008D1D081B0A008D1D921B04008D1D15", INIT_02 => X"008D1DEF1B2A008D1D491B29008D1DC21B28008D1D031B21008D1D001B20008D", INIT_03 => X"1B30008D1D771B2F008D1D001B2E008D1D0B1B2D008D1D771B2C008D1D001B2B", INIT_04 => X"157400B800B4204C5000D60416FF5000D6041600204C008D1D401B88008D1D0B", INIT_05 => X"00DC00C54507157400B800B4500000BF900000DC00C505D0900000DC00C54506", INIT_06 => X"00DC00C505B0900000DC00C54506155D00B800B4500000BF00DA0D5000CF9000", INIT_07 => X"00C505B0900000DC00C54506155D00B800B4500000BF900000DC00C505D09000", INIT_08 => X"156800B800B4500000BF00DA0D5000CF900000DC00C54507155D00B8900000DC", INIT_09 => X"00B800B4500000BF900000DC00C505D0900000DC00C505B0900000DC00C54506", INIT_0A => X"00CF900000DC00C54507156800B8900000DC00C505B0900000DC00C545061568", INIT_0B => X"00EA500000DF00FC00EA00FB00E400EE5000DF085F021F01500000BF00DA0D50", INIT_0C => X"110820C69000410E00D500EE20CB00EA60CAC5101180500000EE00FC00E400FB", INIT_0D => X"10FE5000D50100F120D500EE500000DF00FC00E400FB00EA500060D0910100F1", INIT_0E => X"DF085F025000DF082F0010FD500020E6D0019006DF085F01500000FBDF082F00", INIT_0F => X"01010101010101010101500000DF00FE4500D002900600FE00E400FB00EE5000", INIT_10 => X"00000000000000000000000000000000000000000000500061029001100B5000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_00 => X"8E92ABA3A3A4AA8BA4AAE8E92AA28A08208208208208208208208208208208A8", INITP_01 => X"AAAA42AA8A0B08A822AAAAB62DAAC2AAAAAAA0A8BA4BA3A4AAE8E8E92AA2E92E", INITP_02 => X"00000000000000000000000000000000000000000000000000000000000002D2", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000") port map( ADDRARDADDR => address_a, ENARDEN => enable, CLKARDCLK => clk, DOADO => data_out_a(31 downto 0), DOPADOP => data_out_a(35 downto 32), DIADI => data_in_a(31 downto 0), DIPADIP => data_in_a(35 downto 32), WEA => "0000", REGCEAREGCE => '0', RSTRAMARSTRAM => '0', RSTREGARSTREG => '0', ADDRBWRADDR => address_b, ENBWREN => enable_b, CLKBWRCLK => clk_b, DOBDO => data_out_b(31 downto 0), DOPBDOP => data_out_b(35 downto 32), DIBDI => data_in_b(31 downto 0), DIPBDIP => data_in_b(35 downto 32), WEBWE => we_b, REGCEB => '0', RSTRAMB => '0', RSTREGB => '0', CASCADEINA => '0', CASCADEINB => '0', INJECTDBITERR => '0', INJECTSBITERR => '0'); -- end generate akv7; -- end generate ram_2k_generate; -- -- ram_4k_generate : if (C_RAM_SIZE_KWORDS = 4) generate s6: if (C_FAMILY = "S6") generate assert(1=0) report "4K BRAM in Spartan-6 is a special case not supported by this template." severity FAILURE; end generate s6; -- -- v6 : if (C_FAMILY = "V6") generate -- address_a <= '0' & address(11 downto 0) & "000"; instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0); data_in_a <= "000000000000000000000000000000000000"; jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0); -- no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0); data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0); address_b <= "0000000000000000"; we_b <= "00000000"; enable_b <= '0'; rdl <= '0'; clk_b <= '0'; end generate no_loader; -- loader : if (C_JTAG_LOADER_ENABLE = 1) generate data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9); data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0); address_b <= '0' & jtag_addr(11 downto 0) & "000"; we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we; enable_b <= jtag_en(0); rdl <= rdl_bus(0); clk_b <= jtag_clk; end generate loader; -- kcpsm6_rom_l: RAMB36E1 generic map ( READ_WIDTH_A => 9, WRITE_WIDTH_A => 9, DOA_REG => 0, INIT_A => X"000000000", RSTREG_PRIORITY_A => "REGCE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", READ_WIDTH_B => 9, WRITE_WIDTH_B => 9, DOB_REG => 0, INIT_B => X"000000000", RSTREG_PRIORITY_B => "REGCE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", EN_ECC_READ => FALSE, EN_ECC_WRITE => FALSE, RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", SIM_DEVICE => "VIRTEX6", INIT_00 => X"001F8DA0198D400B8D080A8D92048D15038D12028DE4018D54004D80B44946FF", INIT_01 => X"308D772F8D002E8D0B2D8D772C8D002B8DEF2A8D49298DC2288D03218D00208D", INIT_02 => X"DCC50774B8B400BF00DCC5D000DCC50674B8B44C0004FF0004004C8D40888D0B", INIT_03 => X"C5B000DCC5065DB8B400BF00DCC5D000DCC5B000DCC5065DB8B400BFDA50CF00", INIT_04 => X"B8B400BF00DCC5D000DCC5B000DCC50668B8B400BFDA50CF00DCC5075DB800DC", INIT_05 => X"EA00DFFCEAFBE4EE0008020100BFDA50CF00DCC50768B800DCC5B000DCC50668", INIT_06 => X"FE0001F1D5EE00DFFCE4FBEA00D001F108C6000ED5EECBEACA108000EEFCE4FB", INIT_07 => X"010101010100DFFE000206FEE4FBEE000802000800FD00E60106080100FB0800", INIT_08 => X"0000000000000000000000000000000000000000000000000000000002010B00", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_00 => X"F880D8332002906000710C2301118218460223043011800DB6DB6DB6DB6DB6D0", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000008", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000") port map( ADDRARDADDR => address_a, ENARDEN => enable, CLKARDCLK => clk, DOADO => data_out_a_l(31 downto 0), DOPADOP => data_out_a_l(35 downto 32), DIADI => data_in_a(31 downto 0), DIPADIP => data_in_a(35 downto 32), WEA => "0000", REGCEAREGCE => '0', RSTRAMARSTRAM => '0', RSTREGARSTREG => '0', ADDRBWRADDR => address_b, ENBWREN => enable_b, CLKBWRCLK => clk_b, DOBDO => data_out_b_l(31 downto 0), DOPBDOP => data_out_b_l(35 downto 32), DIBDI => data_in_b_l(31 downto 0), DIPBDIP => data_in_b_l(35 downto 32), WEBWE => we_b, REGCEB => '0', RSTRAMB => '0', RSTREGB => '0', CASCADEINA => '0', CASCADEINB => '0', INJECTDBITERR => '0', INJECTSBITERR => '0'); -- kcpsm6_rom_h: RAMB36E1 generic map ( READ_WIDTH_A => 9, WRITE_WIDTH_A => 9, DOA_REG => 0, INIT_A => X"000000000", RSTREG_PRIORITY_A => "REGCE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", READ_WIDTH_B => 9, WRITE_WIDTH_B => 9, DOB_REG => 0, INIT_B => X"000000000", RSTREG_PRIORITY_B => "REGCE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", EN_ECC_READ => FALSE, EN_ECC_WRITE => FALSE, RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", SIM_DEVICE => "VIRTEX6", INIT_00 => X"0E0D000E0D000E0D000E0D000E0D000E0D000E0D000E0D000E0D000E0000000B", INIT_01 => X"0D000E0D000E0D000E0D000E0D000E0D000E0D000E0D000E0D000E0D000E0D00", INIT_02 => X"0000A20A00002800C8000002C80000A20A000010286B0B286B0B10000E0D000E", INIT_03 => X"0002C80000A20A00002800C8000002C8000002C80000A20A00002800000600C8", INIT_04 => X"00002800C8000002C8000002C80000A20A00002800000600C80000A20A00C800", INIT_05 => X"0028000000000000286F2F0F2800000600C80000A20A00C8000002C80000A20A", INIT_06 => X"08286A00100028000000000028B0C8000810C8A000001000B062082800000000", INIT_07 => X"0000000000280000A2684800000000286F2F286F1708289068486F2F28006F17", INIT_08 => X"00000000000000000000000000000000000000000000000000000028B0C80828", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_00 => X"FF1FB32E5FFD6F9FFFCEF3DCFEEE7DE7B9FDDCFBCFEE7DB2492492492492492E", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000019", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000") port map( ADDRARDADDR => address_a, ENARDEN => enable, CLKARDCLK => clk, DOADO => data_out_a_h(31 downto 0), DOPADOP => data_out_a_h(35 downto 32), DIADI => data_in_a(31 downto 0), DIPADIP => data_in_a(35 downto 32), WEA => "0000", REGCEAREGCE => '0', RSTRAMARSTRAM => '0', RSTREGARSTREG => '0', ADDRBWRADDR => address_b, ENBWREN => enable_b, CLKBWRCLK => clk_b, DOBDO => data_out_b_h(31 downto 0), DOPBDOP => data_out_b_h(35 downto 32), DIBDI => data_in_b_h(31 downto 0), DIPBDIP => data_in_b_h(35 downto 32), WEBWE => we_b, REGCEB => '0', RSTRAMB => '0', RSTREGB => '0', CASCADEINA => '0', CASCADEINB => '0', INJECTDBITERR => '0', INJECTSBITERR => '0'); -- end generate v6; -- -- akv7 : if (C_FAMILY = "7S") generate -- address_a <= '0' & address(11 downto 0) & "000"; instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0); data_in_a <= "000000000000000000000000000000000000"; jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0); -- no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0); data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0); address_b <= "0000000000000000"; we_b <= "00000000"; enable_b <= '0'; rdl <= '0'; clk_b <= '0'; end generate no_loader; -- loader : if (C_JTAG_LOADER_ENABLE = 1) generate data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9); data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0); address_b <= '0' & jtag_addr(11 downto 0) & "000"; we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we; enable_b <= jtag_en(0); rdl <= rdl_bus(0); clk_b <= jtag_clk; end generate loader; -- kcpsm6_rom_l: RAMB36E1 generic map ( READ_WIDTH_A => 9, WRITE_WIDTH_A => 9, DOA_REG => 0, INIT_A => X"000000000", RSTREG_PRIORITY_A => "REGCE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", READ_WIDTH_B => 9, WRITE_WIDTH_B => 9, DOB_REG => 0, INIT_B => X"000000000", RSTREG_PRIORITY_B => "REGCE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", EN_ECC_READ => FALSE, EN_ECC_WRITE => FALSE, RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", SIM_DEVICE => "7SERIES", INIT_00 => X"001F8DA0198D400B8D080A8D92048D15038D12028DE4018D54004D80B44946FF", INIT_01 => X"308D772F8D002E8D0B2D8D772C8D002B8DEF2A8D49298DC2288D03218D00208D", INIT_02 => X"DCC50774B8B400BF00DCC5D000DCC50674B8B44C0004FF0004004C8D40888D0B", INIT_03 => X"C5B000DCC5065DB8B400BF00DCC5D000DCC5B000DCC5065DB8B400BFDA50CF00", INIT_04 => X"B8B400BF00DCC5D000DCC5B000DCC50668B8B400BFDA50CF00DCC5075DB800DC", INIT_05 => X"EA00DFFCEAFBE4EE0008020100BFDA50CF00DCC50768B800DCC5B000DCC50668", INIT_06 => X"FE0001F1D5EE00DFFCE4FBEA00D001F108C6000ED5EECBEACA108000EEFCE4FB", INIT_07 => X"010101010100DFFE000206FEE4FBEE000802000800FD00E60106080100FB0800", INIT_08 => X"0000000000000000000000000000000000000000000000000000000002010B00", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_00 => X"F880D8332002906000710C2301118218460223043011800DB6DB6DB6DB6DB6D0", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000008", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000") port map( ADDRARDADDR => address_a, ENARDEN => enable, CLKARDCLK => clk, DOADO => data_out_a_l(31 downto 0), DOPADOP => data_out_a_l(35 downto 32), DIADI => data_in_a(31 downto 0), DIPADIP => data_in_a(35 downto 32), WEA => "0000", REGCEAREGCE => '0', RSTRAMARSTRAM => '0', RSTREGARSTREG => '0', ADDRBWRADDR => address_b, ENBWREN => enable_b, CLKBWRCLK => clk_b, DOBDO => data_out_b_l(31 downto 0), DOPBDOP => data_out_b_l(35 downto 32), DIBDI => data_in_b_l(31 downto 0), DIPBDIP => data_in_b_l(35 downto 32), WEBWE => we_b, REGCEB => '0', RSTRAMB => '0', RSTREGB => '0', CASCADEINA => '0', CASCADEINB => '0', INJECTDBITERR => '0', INJECTSBITERR => '0'); -- kcpsm6_rom_h: RAMB36E1 generic map ( READ_WIDTH_A => 9, WRITE_WIDTH_A => 9, DOA_REG => 0, INIT_A => X"000000000", RSTREG_PRIORITY_A => "REGCE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", READ_WIDTH_B => 9, WRITE_WIDTH_B => 9, DOB_REG => 0, INIT_B => X"000000000", RSTREG_PRIORITY_B => "REGCE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", EN_ECC_READ => FALSE, EN_ECC_WRITE => FALSE, RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", SIM_DEVICE => "7SERIES", INIT_00 => X"0E0D000E0D000E0D000E0D000E0D000E0D000E0D000E0D000E0D000E0000000B", INIT_01 => X"0D000E0D000E0D000E0D000E0D000E0D000E0D000E0D000E0D000E0D000E0D00", INIT_02 => X"0000A20A00002800C8000002C80000A20A000010286B0B286B0B10000E0D000E", INIT_03 => X"0002C80000A20A00002800C8000002C8000002C80000A20A00002800000600C8", INIT_04 => X"00002800C8000002C8000002C80000A20A00002800000600C80000A20A00C800", INIT_05 => X"0028000000000000286F2F0F2800000600C80000A20A00C8000002C80000A20A", INIT_06 => X"08286A00100028000000000028B0C8000810C8A000001000B062082800000000", INIT_07 => X"0000000000280000A2684800000000286F2F286F1708289068486F2F28006F17", INIT_08 => X"00000000000000000000000000000000000000000000000000000028B0C80828", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_00 => X"FF1FB32E5FFD6F9FFFCEF3DCFEEE7DE7B9FDDCFBCFEE7DB2492492492492492E", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000019", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000") port map( ADDRARDADDR => address_a, ENARDEN => enable, CLKARDCLK => clk, DOADO => data_out_a_h(31 downto 0), DOPADOP => data_out_a_h(35 downto 32), DIADI => data_in_a(31 downto 0), DIPADIP => data_in_a(35 downto 32), WEA => "0000", REGCEAREGCE => '0', RSTRAMARSTRAM => '0', RSTREGARSTREG => '0', ADDRBWRADDR => address_b, ENBWREN => enable_b, CLKBWRCLK => clk_b, DOBDO => data_out_b_h(31 downto 0), DOPBDOP => data_out_b_h(35 downto 32), DIBDI => data_in_b_h(31 downto 0), DIPBDIP => data_in_b_h(35 downto 32), WEBWE => we_b, REGCEB => '0', RSTRAMB => '0', RSTREGB => '0', CASCADEINA => '0', CASCADEINB => '0', INJECTDBITERR => '0', INJECTSBITERR => '0'); -- end generate akv7; -- end generate ram_4k_generate; -- -- -- -- -- JTAG Loader -- instantiate_loader : if (C_JTAG_LOADER_ENABLE = 1) generate -- jtag_loader_6_inst : jtag_loader_6 generic map( C_FAMILY => C_FAMILY, C_NUM_PICOBLAZE => 1, C_JTAG_LOADER_ENABLE => C_JTAG_LOADER_ENABLE, C_BRAM_MAX_ADDR_WIDTH => BRAM_ADDRESS_WIDTH, C_ADDR_WIDTH_0 => BRAM_ADDRESS_WIDTH) port map( picoblaze_reset => rdl_bus, jtag_en => jtag_en, jtag_din => jtag_din, jtag_addr => jtag_addr(BRAM_ADDRESS_WIDTH-1 downto 0), jtag_clk => jtag_clk, jtag_we => jtag_we, jtag_dout_0 => jtag_dout, jtag_dout_1 => jtag_dout, -- ports 1-7 are not used jtag_dout_2 => jtag_dout, -- in a 1 device debug jtag_dout_3 => jtag_dout, -- session. However, Synplify jtag_dout_4 => jtag_dout, -- etc require all ports to jtag_dout_5 => jtag_dout, -- be connected jtag_dout_6 => jtag_dout, jtag_dout_7 => jtag_dout); -- end generate instantiate_loader; -- end low_level_definition; -- -- ------------------------------------------------------------------------------------------- -- -- JTAG Loader -- ------------------------------------------------------------------------------------------- -- -- -- JTAG Loader 6 - Version 6.00 -- Kris Chaplin 4 February 2010 -- Ken Chapman 15 August 2011 - Revised coding style -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- library unisim; use unisim.vcomponents.all; -- entity jtag_loader_6 is generic( C_JTAG_LOADER_ENABLE : integer := 1; C_FAMILY : string := "V6"; C_NUM_PICOBLAZE : integer := 1; C_BRAM_MAX_ADDR_WIDTH : integer := 10; C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18; C_JTAG_CHAIN : integer := 2; C_ADDR_WIDTH_0 : integer := 10; C_ADDR_WIDTH_1 : integer := 10; C_ADDR_WIDTH_2 : integer := 10; C_ADDR_WIDTH_3 : integer := 10; C_ADDR_WIDTH_4 : integer := 10; C_ADDR_WIDTH_5 : integer := 10; C_ADDR_WIDTH_6 : integer := 10; C_ADDR_WIDTH_7 : integer := 10); port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0'); jtag_din : out std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0'); jtag_addr : out std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0) := (others => '0'); jtag_clk : out std_logic := '0'; jtag_we : out std_logic := '0'; jtag_dout_0 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_1 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_2 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_3 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_4 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_5 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_6 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_7 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0)); end jtag_loader_6; -- architecture Behavioral of jtag_loader_6 is -- signal num_picoblaze : std_logic_vector(2 downto 0); signal picoblaze_instruction_data_width : std_logic_vector(4 downto 0); -- signal drck : std_logic; signal shift_clk : std_logic; signal shift_din : std_logic; signal shift_dout : std_logic; signal shift : std_logic; signal capture : std_logic; -- signal control_reg_ce : std_logic; signal bram_ce : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); signal bus_zero : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0'); signal jtag_en_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); signal jtag_en_expanded : std_logic_vector(7 downto 0) := (others => '0'); signal jtag_addr_int : std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0); signal jtag_din_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal control_din : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0'); signal control_dout : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0'); signal control_dout_int : std_logic_vector(7 downto 0):= (others => '0'); signal bram_dout_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0'); signal jtag_we_int : std_logic; signal jtag_clk_int : std_logic; signal bram_ce_valid : std_logic; signal din_load : std_logic; -- signal jtag_dout_0_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_1_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_2_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_3_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_4_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_5_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_6_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_7_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal picoblaze_reset_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0'); -- begin bus_zero <= (others => '0'); -- jtag_loader_gen: if (C_JTAG_LOADER_ENABLE = 1) generate -- -- Insert BSCAN primitive for target device architecture. -- BSCAN_SPARTAN6_gen: if (C_FAMILY="S6") generate begin BSCAN_BLOCK_inst : BSCAN_SPARTAN6 generic map ( JTAG_CHAIN => C_JTAG_CHAIN) port map( CAPTURE => capture, DRCK => drck, RESET => open, RUNTEST => open, SEL => bram_ce_valid, SHIFT => shift, TCK => open, TDI => shift_din, TMS => open, UPDATE => jtag_clk_int, TDO => shift_dout); end generate BSCAN_SPARTAN6_gen; -- BSCAN_VIRTEX6_gen: if (C_FAMILY="V6") generate begin BSCAN_BLOCK_inst: BSCAN_VIRTEX6 generic map( JTAG_CHAIN => C_JTAG_CHAIN, DISABLE_JTAG => FALSE) port map( CAPTURE => capture, DRCK => drck, RESET => open, RUNTEST => open, SEL => bram_ce_valid, SHIFT => shift, TCK => open, TDI => shift_din, TMS => open, UPDATE => jtag_clk_int, TDO => shift_dout); end generate BSCAN_VIRTEX6_gen; -- BSCAN_7SERIES_gen: if (C_FAMILY="7S") generate begin BSCAN_BLOCK_inst: BSCANE2 generic map( JTAG_CHAIN => C_JTAG_CHAIN, DISABLE_JTAG => "FALSE") port map( CAPTURE => capture, DRCK => drck, RESET => open, RUNTEST => open, SEL => bram_ce_valid, SHIFT => shift, TCK => open, TDI => shift_din, TMS => open, UPDATE => jtag_clk_int, TDO => shift_dout); end generate BSCAN_7SERIES_gen; -- -- -- Insert clock buffer to ensure reliable shift operations. -- upload_clock: BUFG port map( I => drck, O => shift_clk); -- -- -- Shift Register -- -- control_reg_ce_shift: process (shift_clk) begin if shift_clk'event and shift_clk = '1' then if (shift = '1') then control_reg_ce <= shift_din; end if; end if; end process control_reg_ce_shift; -- bram_ce_shift: process (shift_clk) begin if shift_clk'event and shift_clk='1' then if (shift = '1') then if(C_NUM_PICOBLAZE > 1) then for i in 0 to C_NUM_PICOBLAZE-2 loop bram_ce(i+1) <= bram_ce(i); end loop; end if; bram_ce(0) <= control_reg_ce; end if; end if; end process bram_ce_shift; -- bram_we_shift: process (shift_clk) begin if shift_clk'event and shift_clk='1' then if (shift = '1') then jtag_we_int <= bram_ce(C_NUM_PICOBLAZE-1); end if; end if; end process bram_we_shift; -- bram_a_shift: process (shift_clk) begin if shift_clk'event and shift_clk='1' then if (shift = '1') then for i in 0 to C_BRAM_MAX_ADDR_WIDTH-2 loop jtag_addr_int(i+1) <= jtag_addr_int(i); end loop; jtag_addr_int(0) <= jtag_we_int; end if; end if; end process bram_a_shift; -- bram_d_shift: process (shift_clk) begin if shift_clk'event and shift_clk='1' then if (din_load = '1') then jtag_din_int <= bram_dout_int; elsif (shift = '1') then for i in 0 to C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-2 loop jtag_din_int(i+1) <= jtag_din_int(i); end loop; jtag_din_int(0) <= jtag_addr_int(C_BRAM_MAX_ADDR_WIDTH-1); end if; end if; end process bram_d_shift; -- shift_dout <= jtag_din_int(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1); -- -- din_load_select:process (bram_ce, din_load, capture, bus_zero, control_reg_ce) begin if ( bram_ce = bus_zero ) then din_load <= capture and control_reg_ce; else din_load <= capture; end if; end process din_load_select; -- -- -- Control Registers -- num_picoblaze <= conv_std_logic_vector(C_NUM_PICOBLAZE-1,3); picoblaze_instruction_data_width <= conv_std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1,5); -- control_registers: process(jtag_clk_int) begin if (jtag_clk_int'event and jtag_clk_int = '1') then if (bram_ce_valid = '1') and (jtag_we_int = '0') and (control_reg_ce = '1') then case (jtag_addr_int(3 downto 0)) is when "0000" => -- 0 = version - returns (7 downto 4) illustrating number of PB -- and (3 downto 0) picoblaze instruction data width control_dout_int <= num_picoblaze & picoblaze_instruction_data_width; when "0001" => -- 1 = PicoBlaze 0 reset / status if (C_NUM_PICOBLAZE >= 1) then control_dout_int <= picoblaze_reset_int(0) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_0-1,5) ); else control_dout_int <= (others => '0'); end if; when "0010" => -- 2 = PicoBlaze 1 reset / status if (C_NUM_PICOBLAZE >= 2) then control_dout_int <= picoblaze_reset_int(1) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_1-1,5) ); else control_dout_int <= (others => '0'); end if; when "0011" => -- 3 = PicoBlaze 2 reset / status if (C_NUM_PICOBLAZE >= 3) then control_dout_int <= picoblaze_reset_int(2) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_2-1,5) ); else control_dout_int <= (others => '0'); end if; when "0100" => -- 4 = PicoBlaze 3 reset / status if (C_NUM_PICOBLAZE >= 4) then control_dout_int <= picoblaze_reset_int(3) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_3-1,5) ); else control_dout_int <= (others => '0'); end if; when "0101" => -- 5 = PicoBlaze 4 reset / status if (C_NUM_PICOBLAZE >= 5) then control_dout_int <= picoblaze_reset_int(4) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_4-1,5) ); else control_dout_int <= (others => '0'); end if; when "0110" => -- 6 = PicoBlaze 5 reset / status if (C_NUM_PICOBLAZE >= 6) then control_dout_int <= picoblaze_reset_int(5) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_5-1,5) ); else control_dout_int <= (others => '0'); end if; when "0111" => -- 7 = PicoBlaze 6 reset / status if (C_NUM_PICOBLAZE >= 7) then control_dout_int <= picoblaze_reset_int(6) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_6-1,5) ); else control_dout_int <= (others => '0'); end if; when "1000" => -- 8 = PicoBlaze 7 reset / status if (C_NUM_PICOBLAZE >= 8) then control_dout_int <= picoblaze_reset_int(7) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_7-1,5) ); else control_dout_int <= (others => '0'); end if; when "1111" => control_dout_int <= conv_std_logic_vector(C_BRAM_MAX_ADDR_WIDTH -1,8); when others => control_dout_int <= (others => '1'); end case; else control_dout_int <= (others => '0'); end if; end if; end process control_registers; -- control_dout(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-8) <= control_dout_int; -- pb_reset: process(jtag_clk_int) begin if (jtag_clk_int'event and jtag_clk_int = '1') then if (bram_ce_valid = '1') and (jtag_we_int = '1') and (control_reg_ce = '1') then picoblaze_reset_int(C_NUM_PICOBLAZE-1 downto 0) <= control_din(C_NUM_PICOBLAZE-1 downto 0); end if; end if; end process pb_reset; -- -- -- Assignments -- control_dout (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-9 downto 0) <= (others => '0') when (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH > 8); -- -- Qualify the blockram CS signal with bscan select output jtag_en_int <= bram_ce when bram_ce_valid = '1' else (others => '0'); -- jtag_en_expanded(C_NUM_PICOBLAZE-1 downto 0) <= jtag_en_int; jtag_en_expanded(7 downto C_NUM_PICOBLAZE) <= (others => '0') when (C_NUM_PICOBLAZE < 8); -- bram_dout_int <= control_dout or jtag_dout_0_masked or jtag_dout_1_masked or jtag_dout_2_masked or jtag_dout_3_masked or jtag_dout_4_masked or jtag_dout_5_masked or jtag_dout_6_masked or jtag_dout_7_masked; -- control_din <= jtag_din_int; -- jtag_dout_0_masked <= jtag_dout_0 when jtag_en_expanded(0) = '1' else (others => '0'); jtag_dout_1_masked <= jtag_dout_1 when jtag_en_expanded(1) = '1' else (others => '0'); jtag_dout_2_masked <= jtag_dout_2 when jtag_en_expanded(2) = '1' else (others => '0'); jtag_dout_3_masked <= jtag_dout_3 when jtag_en_expanded(3) = '1' else (others => '0'); jtag_dout_4_masked <= jtag_dout_4 when jtag_en_expanded(4) = '1' else (others => '0'); jtag_dout_5_masked <= jtag_dout_5 when jtag_en_expanded(5) = '1' else (others => '0'); jtag_dout_6_masked <= jtag_dout_6 when jtag_en_expanded(6) = '1' else (others => '0'); jtag_dout_7_masked <= jtag_dout_7 when jtag_en_expanded(7) = '1' else (others => '0'); -- jtag_en <= jtag_en_int; jtag_din <= jtag_din_int; jtag_addr <= jtag_addr_int; jtag_clk <= jtag_clk_int; jtag_we <= jtag_we_int; picoblaze_reset <= picoblaze_reset_int; -- end generate jtag_loader_gen; -- end Behavioral; -- -- ------------------------------------------------------------------------------------ -- -- END OF FILE clock_control_program.vhd -- ------------------------------------------------------------------------------------
architecture RTL of FIFO is begin process begin sig1 <= sig2; sig2 <= sig3; end process; -- Violations below process begin sig1 <=sig2; sig2 <= sig3; end process; end architecture RTL;
library verilog; use verilog.vl_types.all; entity usb_system_clocks_stdsync_sv6 is port( clk : in vl_logic; din : in vl_logic; dout : out vl_logic; reset_n : in vl_logic ); end usb_system_clocks_stdsync_sv6;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc582.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- -- **************************** -- -- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:36 1996 -- -- **************************** -- -- **************************** -- -- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:50 1996 -- -- **************************** -- -- **************************** -- -- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:14 1996 -- -- **************************** -- ENTITY c03s04b01x00p01n01i00582ent IS END c03s04b01x00p01n01i00582ent; ARCHITECTURE c03s04b01x00p01n01i00582arch OF c03s04b01x00p01n01i00582ent IS type string_file is file of string; signal k : integer := 0; BEGIN TESTING: PROCESS file filein : string_file open read_mode is "iofile.21"; variable v : string(1 to 7); variable len : natural; BEGIN for i in 1 to 100 loop assert(endfile(filein) = false) report"end of file reached before expected"; read(filein,v,len); assert(len = 7) report "wrong length passed during read operation"; if (v /= "shishir" or len /= 7) then k <= 1; end if; end loop; wait for 1 ns; assert NOT(k = 0) report "***PASSED TEST: c03s04b01x00p01n01i00582" severity NOTE; assert (k = 0) report "***FAILED TEST: c03s04b01x00p01n01i00582 - File reading operation failed." severity ERROR; wait; END PROCESS TESTING; END c03s04b01x00p01n01i00582arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc582.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- -- **************************** -- -- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:36 1996 -- -- **************************** -- -- **************************** -- -- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:50 1996 -- -- **************************** -- -- **************************** -- -- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:14 1996 -- -- **************************** -- ENTITY c03s04b01x00p01n01i00582ent IS END c03s04b01x00p01n01i00582ent; ARCHITECTURE c03s04b01x00p01n01i00582arch OF c03s04b01x00p01n01i00582ent IS type string_file is file of string; signal k : integer := 0; BEGIN TESTING: PROCESS file filein : string_file open read_mode is "iofile.21"; variable v : string(1 to 7); variable len : natural; BEGIN for i in 1 to 100 loop assert(endfile(filein) = false) report"end of file reached before expected"; read(filein,v,len); assert(len = 7) report "wrong length passed during read operation"; if (v /= "shishir" or len /= 7) then k <= 1; end if; end loop; wait for 1 ns; assert NOT(k = 0) report "***PASSED TEST: c03s04b01x00p01n01i00582" severity NOTE; assert (k = 0) report "***FAILED TEST: c03s04b01x00p01n01i00582 - File reading operation failed." severity ERROR; wait; END PROCESS TESTING; END c03s04b01x00p01n01i00582arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc582.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- -- **************************** -- -- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:36 1996 -- -- **************************** -- -- **************************** -- -- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:50 1996 -- -- **************************** -- -- **************************** -- -- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:14 1996 -- -- **************************** -- ENTITY c03s04b01x00p01n01i00582ent IS END c03s04b01x00p01n01i00582ent; ARCHITECTURE c03s04b01x00p01n01i00582arch OF c03s04b01x00p01n01i00582ent IS type string_file is file of string; signal k : integer := 0; BEGIN TESTING: PROCESS file filein : string_file open read_mode is "iofile.21"; variable v : string(1 to 7); variable len : natural; BEGIN for i in 1 to 100 loop assert(endfile(filein) = false) report"end of file reached before expected"; read(filein,v,len); assert(len = 7) report "wrong length passed during read operation"; if (v /= "shishir" or len /= 7) then k <= 1; end if; end loop; wait for 1 ns; assert NOT(k = 0) report "***PASSED TEST: c03s04b01x00p01n01i00582" severity NOTE; assert (k = 0) report "***FAILED TEST: c03s04b01x00p01n01i00582 - File reading operation failed." severity ERROR; wait; END PROCESS TESTING; END c03s04b01x00p01n01i00582arch;
---------------------------------------------------------------------------------- -- Felix Winterstein, Imperial College London -- -- Module Name: divider_top - Behavioral -- -- Revision 1.01 -- Additional Comments: distributed under a BSD license, see LICENSE.txt -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use ieee.math_real.all; use work.lloyds_algorithm_pkg.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity divider_top is generic ( ROUND : boolean := false ); port ( clk : in std_logic; sclr : in std_logic; nd : in std_logic; dividend : in data_type_ext; divisor : in coord_type; rdy : out std_logic; quotient : out data_type; divide_by_zero : out std_logic ); end divider_top; architecture Behavioral of divider_top is constant QUOTIENT_BITWIDTH : integer := COORD_BITWIDTH_EXT; constant FRACTIONAL_BITWIDTH : integer := COORD_BITWIDTH_EXT-COORD_BITWIDTH; type divider_result_type is array(0 to D-1) of std_logic_vector(QUOTIENT_BITWIDTH+FRACTIONAL_BITWIDTH-1 downto 0); type quotient_type is array(0 to D-1) of std_logic_vector(QUOTIENT_BITWIDTH-1 downto 0); component divider port ( aclk : IN std_logic; s_axis_divisor_tvalid : IN std_logic; --s_axis_divisor_tready : OUT std_logic; s_axis_divisor_tdata : IN std_logic_vector(COORD_BITWIDTH-1 DOWNTO 0); s_axis_dividend_tvalid : IN std_logic; --s_axis_dividend_tready : OUT std_logic; s_axis_dividend_tdata : IN std_logic_vector(COORD_BITWIDTH_EXT-1 DOWNTO 0); m_axis_dout_tvalid : OUT std_logic; m_axis_dout_tdata : OUT std_logic_vector(QUOTIENT_BITWIDTH+FRACTIONAL_BITWIDTH-1 DOWNTO 0) --m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); end component; component divider_v3_0 port ( clk : IN std_logic; sclr : IN std_logic; s_axis_divisor_tvalid : IN std_logic; divisor : IN std_logic_vector(COORD_BITWIDTH-1 DOWNTO 0); dividend : IN std_logic_vector(COORD_BITWIDTH_EXT-1 DOWNTO 0); quotient: OUT std_logic_vector(QUOTIENT_BITWIDTH-1 DOWNTO 0); fractional : OUT std_logic_vector(FRACTIONAL_BITWIDTH-1 downto 0) ); end component; component dsp_round generic ( BITWIDTH_IN : integer := 32; BITWIDTH_OUT : integer := 32 ); port ( sclr : in std_logic; nd : in std_logic; AB_IN : in std_logic_vector (BITWIDTH_IN-1 downto 0); CARRYIN_IN : in std_logic; CLK_IN : in std_logic; C_IN : in std_logic_vector (BITWIDTH_IN-1 downto 0); P_OUT : out std_logic_vector (BITWIDTH_OUT-1 downto 0); rdy : out std_logic ); end component; signal tmp_divisor : coord_type; signal divider_result : divider_result_type; signal tmp_quotient : quotient_type; signal divider_valid : std_logic_vector(0 to D-1); signal tmp_divide_by_zero : std_logic_vector(0 to D-1); signal round_valid : std_logic_vector(0 to D-1); signal c_in_const : std_logic_vector(COORD_BITWIDTH_EXT-1 downto 0); begin c_in_const(QUOTIENT_BITWIDTH-1 downto QUOTIENT_BITWIDTH-FRACTIONAL_BITWIDTH-1) <= (others => '0'); c_in_const(QUOTIENT_BITWIDTH-FRACTIONAL_BITWIDTH-2 downto 0) <= (others => '1'); tmp_divisor <= std_logic_vector(to_unsigned(1,COORD_BITWIDTH)) WHEN divisor = std_logic_vector(to_unsigned(0,COORD_BITWIDTH)) ELSE divisor; G_DIV : for I in 0 to D-1 generate divider_inst : divider port map ( aclk => clk, s_axis_divisor_tvalid => nd, --s_axis_divisor_tready => open, s_axis_divisor_tdata => tmp_divisor, s_axis_dividend_tvalid => nd, --s_axis_dividend_tready => open, s_axis_dividend_tdata => dividend(I), m_axis_dout_tvalid => divider_valid(I), m_axis_dout_tdata => divider_result(I) --m_axis_dout_tuser(0) => tmp_divide_by_zero(I) ); tmp_quotient(I) <= divider_result(I)(QUOTIENT_BITWIDTH+FRACTIONAL_BITWIDTH-1 downto FRACTIONAL_BITWIDTH); G_ROUND : if ROUND = true generate dsp_round_inst : dsp_round generic map ( BITWIDTH_IN => COORD_BITWIDTH_EXT, BITWIDTH_OUT => COORD_BITWIDTH ) port map ( sclr => sclr, nd => divider_valid(I), AB_IN => divider_result(I)(COORD_BITWIDTH_EXT-1 downto 0), CARRYIN_IN => divider_result(I)(COORD_BITWIDTH_EXT-1), -- round towards zero CLK_IN => clk, C_IN => c_in_const, P_OUT => quotient(I), rdy => round_valid(I) ); end generate G_ROUND; G_NO_ROUND : if ROUND = false generate quotient(I) <= divider_result(I)(QUOTIENT_BITWIDTH-1 downto FRACTIONAL_BITWIDTH); end generate G_NO_ROUND; end generate G_DIV; G_NO_ROUND_1 : if ROUND = false generate rdy <= divider_valid(0); end generate G_NO_ROUND_1; G_ROUND_1 : if ROUND = true generate rdy <= round_valid(0); end generate G_ROUND_1; divide_by_zero <= '0';--tmp_divide_by_zero(0); end Behavioral;
------------------------------------------------------------------------------- --! @file nShiftRegRtl.vhd -- --! @brief Shift register with n-bit-width -- --! @details This shift register implementation provides a configurable width. ------------------------------------------------------------------------------- -- -- (c) B&R, 2014 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --! Common library library libcommon; --! Use common library global package use libcommon.global.all; entity nShiftReg is generic ( --! Data width gWidth : natural := 8; --! Number of tabs gTabs : natural := 4; --! Shift direction ("left" or "right") gShiftDir : string := "left" ); port ( --! Asynchronous reset iArst : in std_logic; --! Clock iClk : in std_logic; --! Parallel Load iLoad : in std_logic; --! Shift Enable iShift : in std_logic; --! Load Data (gTabs x gWidth) iLoadData : in std_logic_vector(gWidth*gTabs-1 downto 0); --! Parallel Output Data oParData : out std_logic_vector(gWidth*gTabs-1 downto 0); --! Input Shift Data iData : in std_logic_vector(gWidth-1 downto 0); --! Ouptut Shift Data oData : out std_logic_vector(gWidth-1 downto 0) ); end nShiftReg; architecture rtl of nShiftReg is --! Shift register type type tShiftReg is array (gTabs-1 downto 0) of std_logic_vector(gWidth-1 downto 0); --! Function to convert std_logic_vector into tShiftReg function convStdLogicToShiftReg (din : std_logic_vector) return tShiftReg is variable vTmp : tShiftReg; begin --default vTmp := (others => (others => cInactivated)); --loop tab-wise for i in gTabs-1 downto 0 loop vTmp(i) := din((i+1)*gWidth-1 downto i*gWidth); end loop; return vTmp; end function; --! Function to convert tShiftReg into std_logic_vector function convShiftRegToStdLogic (din : tShiftReg) return std_logic_vector is variable vTmp : std_logic_vector(gWidth*gTabs-1 downto 0); begin --default vTmp := (others => cInactivated); --loop tab-wise for i in gTabs-1 downto 0 loop vTmp((i+1)*gWidth-1 downto i*gWidth) := din(i); end loop; return vTmp; end function; --! Shift register signal reg, reg_next : tShiftReg; begin assert (gShiftDir = "left" or gShiftDir = "right") report "Set either left or right for shift direction!" severity failure; --serial output oData <= reg(reg'right) when gShiftDir = "right" else reg(reg'left); --parallel output oParData <= convShiftRegToStdLogic(reg); --! Process doing loading and shifting comb : process ( reg, iLoad, iShift, iLoadData, iData ) begin --default reg_next <= reg; if iLoad = cActivated then reg_next <= convStdLogicToShiftReg(iLoadData); elsif iShift = cActivated then if gShiftDir = "right" then reg_next <= iData & reg(reg'left downto 1); else reg_next <= reg(reg'left-1 downto 0) & iData; end if; end if; end process; --! Register process regClk : process(iArst, iClk) begin if iArst = cActivated then reg <= (others => (others => cInactivated)); elsif rising_edge(iClk) then reg <= reg_next; end if; end process; end rtl;
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Package: Common functions and types -- -- Authors: Thomas B. Preusser -- Martin Zabel -- Patrick Lehmann -- -- Description: -- ------------------------------------ -- For detailed documentation see below. -- -- License: -- ============================================================================ -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library PoC; use PoC.my_config.all; package utils is -- PoC settings -- ========================================================================== constant POC_VERBOSE : BOOLEAN := MY_VERBOSE; -- Environment -- ========================================================================== -- Distinguishes simulation from synthesis constant SIMULATION : BOOLEAN; -- deferred constant declaration -- Type declarations -- ========================================================================== --+ Vectors of primitive standard types +++++++++++++++++++++++++++++++++++++ type T_BOOLVEC is array(NATURAL range <>) of BOOLEAN; type T_INTVEC is array(NATURAL range <>) of INTEGER; type T_NATVEC is array(NATURAL range <>) of NATURAL; type T_POSVEC is array(NATURAL range <>) of POSITIVE; type T_REALVEC is array(NATURAL range <>) of REAL; --+ Integer subranges sometimes useful for speeding up simulation ++++++++++ subtype T_INT_8 is INTEGER range -128 to 127; subtype T_INT_16 is INTEGER range -32768 to 32767; subtype T_UINT_8 is INTEGER range 0 to 255; subtype T_UINT_16 is INTEGER range 0 to 65535; --+ Enums ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- Intellectual Property (IP) type type T_IPSTYLE is (IPSTYLE_HARD, IPSTYLE_SOFT); -- Bit Order type T_BIT_ORDER is (LSB_FIRST, MSB_FIRST); -- Byte Order (Endian) type T_BYTE_ORDER is (LITTLE_ENDIAN, BIG_ENDIAN); -- rounding style type T_ROUNDING_STYLE is (ROUND_TO_NEAREST, ROUND_TO_ZERO, ROUND_TO_INF, ROUND_UP, ROUND_DOWN); type T_BCD is array(3 downto 0) of std_logic; type T_BCD_VECTOR is array(NATURAL range <>) of T_BCD; constant C_BCD_MINUS : T_BCD := "1010"; constant C_BCD_OFF : T_BCD := "1011"; -- Function declarations -- ========================================================================== --+ Division ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- Calculates: ceil(a / b) function div_ceil(a : NATURAL; b : POSITIVE) return NATURAL; --+ Power +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- is input a power of 2? function is_pow2(int : NATURAL) return BOOLEAN; -- round to next power of 2 function ceil_pow2(int : NATURAL) return POSITIVE; -- round to previous power of 2 function floor_pow2(int : NATURAL) return NATURAL; --+ Logarithm ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- Calculates: ceil(ld(arg)) function log2ceil(arg : positive) return natural; -- Calculates: max(1, ceil(ld(arg))) function log2ceilnz(arg : positive) return positive; -- Calculates: ceil(lg(arg)) function log10ceil(arg : POSITIVE) return NATURAL; -- Calculates: max(1, ceil(lg(arg))) function log10ceilnz(arg : POSITIVE) return POSITIVE; --+ if-then-else (ite) +++++++++++++++++++++++++++++++++++++++++++++++++++++ function ite(cond : BOOLEAN; value1 : BOOLEAN; value2 : BOOLEAN) return BOOLEAN; function ite(cond : BOOLEAN; value1 : INTEGER; value2 : INTEGER) return INTEGER; function ite(cond : BOOLEAN; value1 : REAL; value2 : REAL) return REAL; function ite(cond : BOOLEAN; value1 : STD_LOGIC; value2 : STD_LOGIC) return STD_LOGIC; function ite(cond : BOOLEAN; value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function ite(cond : BOOLEAN; value1 : BIT_VECTOR; value2 : BIT_VECTOR) return BIT_VECTOR; function ite(cond : BOOLEAN; value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED; function ite(cond : BOOLEAN; value1 : CHARACTER; value2 : CHARACTER) return CHARACTER; function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING; --+ Max / Min / Sum ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ function imin(arg1 : integer; arg2 : integer) return integer; -- Calculates: min(arg1, arg2) for integers function rmin(arg1 : real; arg2 : real) return real; -- Calculates: min(arg1, arg2) for reals function imin(vec : T_INTVEC) return INTEGER; -- Calculates: min(vec) for a integer vector function imin(vec : T_NATVEC) return NATURAL; -- Calculates: min(vec) for a natural vector function imin(vec : T_POSVEC) return POSITIVE; -- Calculates: min(vec) for a positive vector function rmin(vec : T_REALVEC) return real; -- Calculates: min(vec) of real vector function imax(arg1 : integer; arg2 : integer) return integer; -- Calculates: max(arg1, arg2) for integers function rmax(arg1 : real; arg2 : real) return real; -- Calculates: max(arg1, arg2) for reals function imax(vec : T_INTVEC) return INTEGER; -- Calculates: max(vec) for a integer vector function imax(vec : T_NATVEC) return NATURAL; -- Calculates: max(vec) for a natural vector function imax(vec : T_POSVEC) return POSITIVE; -- Calculates: max(vec) for a positive vector function rmax(vec : T_REALVEC) return real; -- Calculates: max(vec) of real vector function isum(vec : T_NATVEC) return NATURAL; -- Calculates: sum(vec) for a natural vector function isum(vec : T_POSVEC) return natural; -- Calculates: sum(vec) for a positive vector function isum(vec : T_INTVEC) return integer; -- Calculates: sum(vec) of integer vector function rsum(vec : T_REALVEC) return real; -- Calculates: sum(vec) of real vector --+ Conversions ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- to integer: to_int function to_int(bool : BOOLEAN; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER; function to_int(sl : STD_LOGIC; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER; -- to std_logic: to_sl function to_sl(Value : BOOLEAN) return STD_LOGIC; function to_sl(Value : CHARACTER) return STD_LOGIC; -- to std_logic_vector: to_slv function to_slv(Value : NATURAL; Size : POSITIVE) return STD_LOGIC_VECTOR; -- short for std_logic_vector(to_unsigned(Value, Size)) -- TODO: comment function to_index(slv : UNSIGNED; max : NATURAL := 0) return INTEGER; function to_index(slv : STD_LOGIC_VECTOR; max : NATURAL := 0) return INTEGER; -- is_* function is_sl(c : CHARACTER) return BOOLEAN; --+ Basic Vector Utilities +++++++++++++++++++++++++++++++++++++++++++++++++ -- Aggregate functions function slv_or (vec : STD_LOGIC_VECTOR) return STD_LOGIC; function slv_nor (vec : STD_LOGIC_VECTOR) return STD_LOGIC; function slv_and (vec : STD_LOGIC_VECTOR) return STD_LOGIC; function slv_nand(vec : STD_LOGIC_VECTOR) return STD_LOGIC; function slv_xor (vec : std_logic_vector) return std_logic; -- NO slv_xnor! This operation would not be well-defined as -- not xor(vec) /= vec_{n-1} xnor ... xnor vec_1 xnor vec_0 iff n is odd. -- Reverses the elements of the passed Vector. -- -- @synthesis supported -- function reverse(vec : std_logic_vector) return std_logic_vector; function reverse(vec : bit_vector) return bit_vector; function reverse(vec : unsigned) return unsigned; -- Resizes the vector to the specified length. The adjustment is make on -- on the 'high end of the vector. The 'low index remains as in the argument. -- If the result vector is larger, the extension uses the provided fill value -- (default: '0'). -- Use the resize functions of the numeric_std package for value-preserving -- resizes of the signed and unsigned data types. -- -- @synthesis supported -- function resize(vec : bit_vector; length : natural; fill : bit := '0') return bit_vector; function resize(vec : std_logic_vector; length : natural; fill : std_logic := '0') return std_logic_vector; -- Shift the index range of a vector by the specified offset. function move(vec : std_logic_vector; ofs : integer) return std_logic_vector; -- Shift the index range of a vector making vec'low = 0. function movez(vec : std_logic_vector) return std_logic_vector; function ascend(vec : std_logic_vector) return std_logic_vector; function descend(vec : std_logic_vector) return std_logic_vector; -- Least-Significant Set Bit (lssb): -- Computes a vector of the same length as the argument with -- at most one bit set at the rightmost '1' found in arg. -- -- @synthesis supported -- function lssb(arg : std_logic_vector) return std_logic_vector; function lssb(arg : bit_vector) return bit_vector; -- Returns the index of the least-significant set bit. -- -- @synthesis supported -- function lssb_idx(arg : std_logic_vector) return integer; function lssb_idx(arg : bit_vector) return integer; -- Most-Significant Set Bit (mssb): computes a vector of the same length -- with at most one bit set at the leftmost '1' found in arg. function mssb(arg : std_logic_vector) return std_logic_vector; function mssb(arg : bit_vector) return bit_vector; function mssb_idx(arg : std_logic_vector) return integer; function mssb_idx(arg : bit_vector) return integer; -- Swap sub vectors in vector (endian reversal) function swap(slv : STD_LOGIC_VECTOR; Size : POSITIVE) return STD_LOGIC_VECTOR; -- generate bit masks function genmask_high(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR; function genmask_low(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR; --+ Encodings ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- One-Hot-Code to Binary-Code. function onehot2bin(onehot : std_logic_vector) return unsigned; -- Converts Gray-Code into Binary-Code. -- -- @synthesis supported -- function gray2bin (gray_val : std_logic_vector) return std_logic_vector; -- Binary-Code to One-Hot-Code function bin2onehot(value : std_logic_vector) return std_logic_vector; -- Binary-Code to Gray-Code function bin2gray(value : std_logic_vector) return std_logic_vector; end package; package body utils is -- Environment -- ========================================================================== function is_simulation return boolean is variable ret : boolean; begin ret := false; --synthesis translate_off if Is_X('X') then ret := true; end if; --synthesis translate_on return ret; end function; -- deferred constant assignment constant SIMULATION : BOOLEAN := is_simulation; -- Divisions: div_* function div_ceil(a : NATURAL; b : POSITIVE) return NATURAL is -- calculates: ceil(a / b) begin return (a + (b - 1)) / b; end function; -- Power functions: *_pow2 -- ========================================================================== -- is input a power of 2? function is_pow2(int : NATURAL) return BOOLEAN is begin return ceil_pow2(int) = int; end function; -- round to next power of 2 function ceil_pow2(int : NATURAL) return POSITIVE is begin return 2 ** log2ceil(int); end function; -- round to previous power of 2 function floor_pow2(int : NATURAL) return NATURAL is variable temp : UNSIGNED(30 downto 0); begin temp := to_unsigned(int, 31); for i in temp'range loop if (temp(i) = '1') then return 2 ** i; end if; end loop; return 0; end function; -- Logarithms: log*ceil* -- ========================================================================== function log2ceil(arg : positive) return natural is variable tmp : positive; variable log : natural; begin if arg = 1 then return 0; end if; tmp := 1; log := 0; while arg > tmp loop tmp := tmp * 2; log := log + 1; end loop; return log; end function; function log2ceilnz(arg : positive) return positive is begin return imax(1, log2ceil(arg)); end function; function log10ceil(arg : positive) return natural is variable tmp : positive; variable log : natural; begin if arg = 1 then return 0; end if; tmp := 1; log := 0; while arg > tmp loop tmp := tmp * 10; log := log + 1; end loop; return log; end function; function log10ceilnz(arg : positive) return positive is begin return imax(1, log10ceil(arg)); end function; -- if-then-else (ite) -- ========================================================================== function ite(cond : BOOLEAN; value1 : BOOLEAN; value2 : BOOLEAN) return BOOLEAN is begin if cond then return value1; else return value2; end if; end function; function ite(cond : BOOLEAN; value1 : INTEGER; value2 : INTEGER) return INTEGER is begin if cond then return value1; else return value2; end if; end function; function ite(cond : BOOLEAN; value1 : REAL; value2 : REAL) return REAL is begin if cond then return value1; else return value2; end if; end function; function ite(cond : BOOLEAN; value1 : STD_LOGIC; value2 : STD_LOGIC) return STD_LOGIC is begin if cond then return value1; else return value2; end if; end function; function ite(cond : BOOLEAN; value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is begin if cond then return value1; else return value2; end if; end function; function ite(cond : BOOLEAN; value1 : BIT_VECTOR; value2 : BIT_VECTOR) return BIT_VECTOR is begin if cond then return value1; else return value2; end if; end function; function ite(cond : BOOLEAN; value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED is begin if cond then return value1; else return value2; end if; end function; function ite(cond : BOOLEAN; value1 : CHARACTER; value2 : CHARACTER) return CHARACTER is begin if cond then return value1; else return value2; end if; end function; function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING is begin if cond then return value1; else return value2; end if; end function; -- *min / *max / *sum -- ========================================================================== function imin(arg1 : integer; arg2 : integer) return integer is begin if arg1 < arg2 then return arg1; end if; return arg2; end function; function rmin(arg1 : real; arg2 : real) return real is begin if arg1 < arg2 then return arg1; end if; return arg2; end function; function imin(vec : T_INTVEC) return INTEGER is variable Result : INTEGER; begin Result := INTEGER'high; for i in vec'range loop if (vec(I) < Result) then Result := vec(I); end if; end loop; return Result; end function; function imin(vec : T_NATVEC) return NATURAL is variable Result : NATURAL; begin Result := NATURAL'high; for i in vec'range loop if (vec(I) < Result) then Result := vec(I); end if; end loop; return Result; end function; function imin(vec : T_POSVEC) return POSITIVE is variable Result : POSITIVE; begin Result := POSITIVE'high; for i in vec'range loop if (vec(I) < Result) then Result := vec(I); end if; end loop; return Result; end function; function rmin(vec : T_REALVEC) return REAL is variable Result : REAL; begin Result := REAL'high; for i in vec'range loop if vec(i) < Result then Result := vec(i); end if; end loop; return Result; end function; function imax(arg1 : integer; arg2 : integer) return integer is begin if arg1 > arg2 then return arg1; end if; return arg2; end function; function rmax(arg1 : real; arg2 : real) return real is begin if arg1 > arg2 then return arg1; end if; return arg2; end function; function imax(vec : T_INTVEC) return INTEGER is variable Result : INTEGER; begin Result := INTEGER'low; for i in vec'range loop if (vec(I) > Result) then Result := vec(I); end if; end loop; return Result; end function; function imax(vec : T_NATVEC) return NATURAL is variable Result : NATURAL; begin Result := NATURAL'low; for i in vec'range loop if (vec(I) > Result) then Result := vec(I); end if; end loop; return Result; end function; function imax(vec : T_POSVEC) return POSITIVE is variable Result : POSITIVE; begin Result := POSITIVE'low; for i in vec'range loop if (vec(I) > Result) then Result := vec(I); end if; end loop; return Result; end function; function rmax(vec : T_REALVEC) return REAL is variable Result : REAL; begin Result := REAL'low; for i in vec'range loop if vec(i) > Result then Result := vec(i); end if; end loop; return Result; end function; function isum(vec : T_INTVEC) return INTEGER is variable Result : INTEGER; begin Result := 0; for i in vec'range loop Result := Result + vec(i); end loop; return Result; end function; function isum(vec : T_NATVEC) return NATURAL is variable Result : NATURAL; begin Result := 0; for i in vec'range loop Result := Result + vec(I); end loop; return Result; end function; function isum(vec : T_POSVEC) return natural is variable Result : natural; begin Result := 0; for i in vec'range loop Result := Result + vec(I); end loop; return Result; end function; function rsum(vec : T_REALVEC) return REAL is variable Result : REAL; begin Result := 0.0; for i in vec'range loop Result := Result + vec(i); end loop; return Result; end function; -- Vector aggregate functions: slv_* -- ========================================================================== function slv_or(vec : STD_LOGIC_VECTOR) return STD_LOGIC is variable Result : STD_LOGIC; begin Result := '0'; for i in vec'range loop Result := Result or vec(i); end loop; return Result; end function; function slv_nor(vec : STD_LOGIC_VECTOR) return STD_LOGIC is begin return not slv_or(vec); end function; function slv_and(vec : STD_LOGIC_VECTOR) return STD_LOGIC is variable Result : STD_LOGIC; begin Result := '1'; for i in vec'range loop Result := Result and vec(i); end loop; return Result; end function; function slv_nand(vec : STD_LOGIC_VECTOR) return STD_LOGIC is begin return not slv_and(vec); end function; function slv_xor(vec : std_logic_vector) return std_logic is variable res : std_logic; begin res := '0'; for i in vec'range loop res := res xor vec(i); end loop; return res; end slv_xor; -- Convert to integer: to_int function to_int(bool : BOOLEAN; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER is begin return ite(bool, one, zero); end function; function to_int(sl : STD_LOGIC; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER is begin if (sl = '1') then return one; end if; return zero; end function; -- Convert to bit: to_sl -- ========================================================================== function to_sl(Value : BOOLEAN) return STD_LOGIC is begin return ite(Value, '1', '0'); end function; function to_sl(Value : CHARACTER) return STD_LOGIC is begin case Value is when 'U' => return 'U'; when '0' => return '0'; when '1' => return '1'; when 'Z' => return 'Z'; when 'W' => return 'W'; when 'L' => return 'L'; when 'H' => return 'H'; when '-' => return '-'; when OTHERS => return 'X'; end case; end function; -- Convert to vector: to_slv -- ========================================================================== -- short for std_logic_vector(to_unsigned(Value, Size)) -- the return value is guaranteed to have the range (Size-1 downto 0) function to_slv(Value : NATURAL; Size : POSITIVE) return STD_LOGIC_VECTOR is constant res : std_logic_vector(Size-1 downto 0) := std_logic_vector(to_unsigned(Value, Size)); begin return res; end function; function to_index(slv : UNSIGNED; max : NATURAL := 0) return INTEGER is variable res : integer; begin if (slv'length = 0) then return 0; end if; res := to_integer(slv); if SIMULATION and max > 0 then res := imin(res, max); end if; return res; end function; function to_index(slv : STD_LOGIC_VECTOR; max : NATURAL := 0) return INTEGER is begin return to_index(unsigned(slv), max); end function; -- is_* -- ========================================================================== function is_sl(c : CHARACTER) return BOOLEAN is begin case c is when 'U'|'X'|'0'|'1'|'Z'|'W'|'L'|'H'|'-' => return true; when OTHERS => return false; end case; end function; -- Reverse vector elements function reverse(vec : std_logic_vector) return std_logic_vector is variable res : std_logic_vector(vec'range); begin for i in vec'low to vec'high loop res(vec'low + (vec'high-i)) := vec(i); end loop; return res; end function; function reverse(vec : bit_vector) return bit_vector is variable res : bit_vector(vec'range); begin res := to_bitvector(reverse(to_stdlogicvector(vec))); return res; end reverse; function reverse(vec : unsigned) return unsigned is begin return unsigned(reverse(std_logic_vector(vec))); end function; -- Swap sub vectors in vector -- ========================================================================== function swap(slv : STD_LOGIC_VECTOR; Size : POSITIVE) return STD_LOGIC_VECTOR IS CONSTANT SegmentCount : NATURAL := slv'length / Size; variable FromH : NATURAL; variable FromL : NATURAL; variable ToH : NATURAL; variable ToL : NATURAL; variable Result : STD_LOGIC_VECTOR(slv'length - 1 DOWNTO 0); begin for i in 0 TO SegmentCount - 1 loop FromH := ((I + 1) * Size) - 1; FromL := I * Size; ToH := ((SegmentCount - I) * Size) - 1; ToL := (SegmentCount - I - 1) * Size; Result(ToH DOWNTO ToL) := slv(FromH DOWNTO FromL); end loop; return Result; end function; -- generate bit masks -- ========================================================================== function genmask_high(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR IS begin if (Bits = 0) then return (MaskLength - 1 DOWNTO 0 => '0'); else return (MaskLength - 1 DOWNTO MaskLength - Bits + 1 => '1') & (MaskLength - Bits DOWNTO 0 => '0'); end if; end function; function genmask_low(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR is begin if (Bits = 0) then return (MaskLength - 1 DOWNTO 0 => '0'); else return (MaskLength - 1 DOWNTO Bits => '0') & (Bits - 1 DOWNTO 0 => '1'); end if; end function; -- binary encoding conversion functions -- ========================================================================== -- One-Hot-Code to Binary-Code function onehot2bin(onehot : std_logic_vector) return unsigned is variable res : unsigned(log2ceilnz(onehot'high+1)-1 downto 0); variable chk : natural; begin res := (others => '0'); chk := 0; for i in onehot'range loop if onehot(i) = '1' then res := res or to_unsigned(i, res'length); chk := chk + 1; end if; end loop; if SIMULATION and chk /= 1 then report "Broken 1-Hot-Code with "&integer'image(chk)&" bits set." severity error; end if; return res; end onehot2bin; -- Gray-Code to Binary-Code function gray2bin(gray_val : std_logic_vector) return std_logic_vector is variable res : std_logic_vector(gray_val'range); begin -- gray2bin res(res'left) := gray_val(gray_val'left); for i in res'left-1 downto res'right loop res(i) := res(i+1) xor gray_val(i); end loop; return res; end gray2bin; -- Binary-Code to One-Hot-Code function bin2onehot(value : std_logic_vector) return std_logic_vector is variable result : std_logic_vector(2**value'length - 1 downto 0); begin result := (others => '0'); result(to_index(value, 0)) := '1'; return result; end function; -- Binary-Code to Gray-Code function bin2gray(value : std_logic_vector) return std_logic_vector is variable result : std_logic_vector(value'range); begin result(result'left) := value(value'left); for i in (result'left - 1) downto result'right loop result(i) := value(i) xor value(i + 1); end loop; return result; end function; -- bit searching / bit indices -- ========================================================================== -- Least-Significant Set Bit (lssb): computes a vector of the same length with at most one bit set at the rightmost '1' found in arg. function lssb(arg : std_logic_vector) return std_logic_vector is variable res : std_logic_vector(arg'range); begin res := arg and std_logic_vector(unsigned(not arg)+1); return res; end function; function lssb(arg : bit_vector) return bit_vector is variable res : bit_vector(arg'range); begin res := to_bitvector(lssb(to_stdlogicvector(arg))); return res; end lssb; -- Most-Significant Set Bit (mssb): computes a vector of the same length with at most one bit set at the leftmost '1' found in arg. function mssb(arg : std_logic_vector) return std_logic_vector is begin return reverse(lssb(reverse(arg))); end function; function mssb(arg : bit_vector) return bit_vector is begin return reverse(lssb(reverse(arg))); end mssb; -- Index of lssb function lssb_idx(arg : std_logic_vector) return integer is begin return to_integer(onehot2bin(lssb(arg))); end function; function lssb_idx(arg : bit_vector) return integer is variable slv : std_logic_vector(arg'range); begin slv := to_stdlogicvector(arg); return lssb_idx(slv); end lssb_idx; -- Index of mssb function mssb_idx(arg : std_logic_vector) return integer is begin return to_integer(onehot2bin(mssb(arg))); end function; function mssb_idx(arg : bit_vector) return integer is variable slv : std_logic_vector(arg'range); begin slv := to_stdlogicvector(arg); return mssb_idx(slv); end mssb_idx; function resize(vec : bit_vector; length : natural; fill : bit := '0') return bit_vector is constant high2b : natural := vec'low+length-1; constant highcp : natural := imin(vec'high, high2b); variable res_up : bit_vector(vec'low to high2b); variable res_dn : bit_vector(high2b downto vec'low); begin if vec'ascending then res_up := (others => fill); res_up(vec'low to highcp) := vec(vec'low to highcp); return res_up; else res_dn := (others => fill); res_dn(highcp downto vec'low) := vec(highcp downto vec'low); return res_dn; end if; end resize; function resize(vec : std_logic_vector; length : natural; fill : std_logic := '0') return std_logic_vector is constant high2b : natural := vec'low+length-1; constant highcp : natural := imin(vec'high, high2b); variable res_up : std_logic_vector(vec'low to high2b); variable res_dn : std_logic_vector(high2b downto vec'low); begin if vec'ascending then res_up := (others => fill); res_up(vec'low to highcp) := vec(vec'low to highcp); return res_up; else res_dn := (others => fill); res_dn(highcp downto vec'low) := vec(highcp downto vec'low); return res_dn; end if; end resize; -- Move vector boundaries -- ========================================================================== function move(vec : std_logic_vector; ofs : integer) return std_logic_vector is variable res_up : std_logic_vector(vec'low +ofs to vec'high+ofs); variable res_dn : std_logic_vector(vec'high+ofs downto vec'low +ofs); begin if vec'ascending then res_up := vec; return res_up; else res_dn := vec; return res_dn; end if; end move; function movez(vec : std_logic_vector) return std_logic_vector is begin return move(vec, -vec'low); end movez; function ascend(vec : std_logic_vector) return std_logic_vector is variable res : std_logic_vector(vec'low to vec'high); begin res := vec; return res; end ascend; function descend(vec : std_logic_vector) return std_logic_vector is variable res : std_logic_vector(vec'high downto vec'low); begin res := vec; return res; end descend; end package body;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Synthesizable Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: weight_hid_synth.vhd -- -- Description: -- Synthesizable Testbench -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.NUMERIC_STD.ALL; USE IEEE.STD_LOGIC_MISC.ALL; LIBRARY STD; USE STD.TEXTIO.ALL; --LIBRARY unisim; --USE unisim.vcomponents.ALL; LIBRARY work; USE work.ALL; USE work.BMG_TB_PKG.ALL; ENTITY weight_hid_synth IS PORT( CLK_IN : IN STD_LOGIC; RESET_IN : IN STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA ); END ENTITY; ARCHITECTURE weight_hid_synth_ARCH OF weight_hid_synth IS COMPONENT weight_hid_exdes PORT ( --Inputs - Port A WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(319 DOWNTO 0); DOUTA : OUT STD_LOGIC_VECTOR(319 DOWNTO 0); CLKA : IN STD_LOGIC ); END COMPONENT; SIGNAL CLKA: STD_LOGIC := '0'; SIGNAL RSTA: STD_LOGIC := '0'; SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA: STD_LOGIC_VECTOR(319 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA_R: STD_LOGIC_VECTOR(319 DOWNTO 0) := (OTHERS => '0'); SIGNAL DOUTA: STD_LOGIC_VECTOR(319 DOWNTO 0); SIGNAL CHECKER_EN : STD_LOGIC:='0'; SIGNAL CHECKER_EN_R : STD_LOGIC:='0'; SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0'); SIGNAL clk_in_i: STD_LOGIC; SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1'; SIGNAL ITER_R0 : STD_LOGIC := '0'; SIGNAL ITER_R1 : STD_LOGIC := '0'; SIGNAL ITER_R2 : STD_LOGIC := '0'; SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); BEGIN -- clk_buf: bufg -- PORT map( -- i => CLK_IN, -- o => clk_in_i -- ); clk_in_i <= CLK_IN; CLKA <= clk_in_i; RSTA <= RESET_SYNC_R3 AFTER 50 ns; PROCESS(clk_in_i) BEGIN IF(RISING_EDGE(clk_in_i)) THEN RESET_SYNC_R1 <= RESET_IN; RESET_SYNC_R2 <= RESET_SYNC_R1; RESET_SYNC_R3 <= RESET_SYNC_R2; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ISSUE_FLAG_STATUS<= (OTHERS => '0'); ELSE ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG; END IF; END IF; END PROCESS; STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS; BMG_DATA_CHECKER_INST: ENTITY work.CHECKER GENERIC MAP ( WRITE_WIDTH => 320, READ_WIDTH => 320 ) PORT MAP ( CLK => CLKA, RST => RSTA, EN => CHECKER_EN_R, DATA_IN => DOUTA, STATUS => ISSUE_FLAG(0) ); PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RSTA='1') THEN CHECKER_EN_R <= '0'; ELSE CHECKER_EN_R <= CHECKER_EN AFTER 50 ns; END IF; END IF; END PROCESS; BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN PORT MAP( CLK => clk_in_i, RST => RSTA, ADDRA => ADDRA, DINA => DINA, WEA => WEA, CHECK_DATA => CHECKER_EN ); PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STATUS(8) <= '0'; iter_r2 <= '0'; iter_r1 <= '0'; iter_r0 <= '0'; ELSE STATUS(8) <= iter_r2; iter_r2 <= iter_r1; iter_r1 <= iter_r0; iter_r0 <= STIMULUS_FLOW(8); END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STIMULUS_FLOW <= (OTHERS => '0'); ELSIF(WEA(0)='1') THEN STIMULUS_FLOW <= STIMULUS_FLOW+1; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN WEA_R <= (OTHERS=>'0') AFTER 50 ns; DINA_R <= (OTHERS=>'0') AFTER 50 ns; ELSE WEA_R <= WEA AFTER 50 ns; DINA_R <= DINA AFTER 50 ns; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ADDRA_R <= (OTHERS=> '0') AFTER 50 ns; ELSE ADDRA_R <= ADDRA AFTER 50 ns; END IF; END IF; END PROCESS; BMG_PORT: weight_hid_exdes PORT MAP ( --Port A WEA => WEA_R, ADDRA => ADDRA_R, DINA => DINA_R, DOUTA => DOUTA, CLKA => CLKA ); END ARCHITECTURE;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: iodrp_mcb_controller.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for IODRP controller for v0.9 device -- --Reference: -- -- Revision: Date: Comment -- 1.0: 03/19/09: Initial version for IODRP_MCB read operations. -- 1.1: 04/03/09: SLH - Added left shift for certain IOI's -- 1.2: 02/14/11: Change FSM encoding from one-hot to gray to match Verilog version. -- End Revision --******************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity iodrp_mcb_controller is --output to IODRP SDI pin --input from IODRP SDO pin -- Register where memcell_address is captured during the READY state -- Register which stores the write data until it is ready to be shifted out -- The shift register which shifts out SDO and shifts in SDI. -- This register is loaded before the address or data phase, but continues to shift for a writeback of read data -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO -- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg -- The counter for which bit is being shifted during address or data phase -- This is set after the first address phase has executed -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg --added so that DRP_SDI output is only active when DRP_CS is active port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end entity iodrp_mcb_controller; architecture trans of iodrp_mcb_controller is type StType is ( READY, DECIDE , ADDR_PHASE , ADDR_TO_DATA_GAP , ADDR_TO_DATA_GAP2, ADDR_TO_DATA_GAP3, DATA_PHASE , ALMOST_READY , ALMOST_READY2 , ALMOST_READY3 ); constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001"; constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000"; constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011"; constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010"; constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101"; constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100"; constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111"; constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110"; constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001"; constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000"; constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011"; constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010"; constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101"; constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100"; constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111"; constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110"; constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101"; constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100"; constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111"; constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110"; signal memcell_addr_reg : std_logic_vector(7 downto 0); signal data_reg : std_logic_vector(7 downto 0); signal shift_through_reg : std_logic_vector(8 downto 0); signal load_shift_n : std_logic; signal addr_data_sel_n : std_logic; signal bit_cnt : std_logic_vector(2 downto 0); signal rd_not_write_reg : std_logic; signal AddressPhase : std_logic; signal DRP_CS_pre : std_logic; signal extra_cs : std_logic; signal state,nextstate : StType; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "gray"; attribute fsm_encoding of nextstate : signal is "gray"; signal data_out : std_logic_vector(8 downto 0); signal data_out_mux : std_logic_vector(8 downto 0); signal DRP_SDI_pre : std_logic; --synthesis translate_off signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0); -- case(state) --synthesis translate_on -- The changes below are to compensate for an issue with 1.0 silicon. -- It may still be necessary to add a clock cycle to the ADD and CS signals --`define DRP_v1_0_FIX // Uncomment out this line for synthesis procedure shift_n_expand( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(8 downto 0)) is variable data_out_xilinx2 : std_logic_vector(8 downto 0); begin if ((data_in(0)) = '1') then data_out_xilinx2(1 downto 0) := "11"; else data_out_xilinx2(1 downto 0) := "00"; end if; if (data_in(1 downto 0) = "10") then data_out_xilinx2(2 downto 1) := "11"; else data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1)); end if; if (data_in(2 downto 1) = "10") then data_out_xilinx2(3 downto 2) := "11"; else data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2)); end if; if (data_in(3 downto 2) = "10") then data_out_xilinx2(4 downto 3) := "11"; else data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3)); end if; if (data_in(4 downto 3) = "10") then data_out_xilinx2(5 downto 4) := "11"; else data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4)); end if; if (data_in(5 downto 4) = "10") then data_out_xilinx2(6 downto 5) := "11"; else data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5)); end if; if (data_in(6 downto 5) = "10") then data_out_xilinx2(7 downto 6) := "11"; else data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6)); end if; if (data_in(7 downto 6) = "10") then data_out_xilinx2(8 downto 7) := "11"; else data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7)); end if; end shift_n_expand; -- Declare intermediate signals for referenced outputs signal DRP_CS_xilinx1 : std_logic; signal DRP_ADD_xilinx0 : std_logic; signal ALMOST_READY2_ST : std_logic; signal ADDR_PHASE_ST : std_logic; signal BIT_CNT7 : std_logic; signal ADDR_PHASE_ST1 : std_logic; signal DATA_PHASE_ST : std_logic; begin -- Drive referenced outputs DRP_CS <= DRP_CS_xilinx1; DRP_ADD <= DRP_ADD_xilinx0; -- process (state) -- begin -- case state is -- when READY => -- state_ascii <= "READY"; -- when DECIDE => -- state_ascii <= "DECIDE"; -- when ADDR_PHASE => -- state_ascii <= "ADDR_PHASE"; -- when ADDR_TO_DATA_GAP => -- state_ascii <= "ADDR_TO_DATA_GAP"; -- when ADDR_TO_DATA_GAP2 => -- state_ascii <= "ADDR_TO_DATA_GAP2"; -- when ADDR_TO_DATA_GAP3 => -- state_ascii <= "ADDR_TO_DATA_GAP3"; -- when DATA_PHASE => -- state_ascii <= "DATA_PHASE"; -- when ALMOST_READY => -- state_ascii <= "ALMOST_READY"; -- when ALMOST_READY2 => -- state_ascii <= "ALMOST_READY2"; -- when ALMOST_READY3 => -- state_ascii <= "ALMOST_READY3"; -- when others => -- null; -- end case; -- end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (state = READY) then memcell_addr_reg <= memcell_address; data_reg <= write_data; rd_not_write_reg <= rd_not_write; end if; end if; end process; rdy_busy_n <= '1' when state = READY else '0'; process (drp_ioi_addr, data_out) begin case drp_ioi_addr is when IOI_DQ0 => data_out_mux <= data_out; when IOI_DQ1 => data_out_mux <= data_out; when IOI_DQ2 => data_out_mux <= data_out; when IOI_DQ3 => data_out_mux <= data_out; when IOI_DQ4 => data_out_mux <= data_out; when IOI_DQ5 => data_out_mux <= data_out; when IOI_DQ6 => data_out_mux <= data_out; when IOI_DQ7 => data_out_mux <= data_out; when IOI_DQ8 => data_out_mux <= data_out; when IOI_DQ9 => data_out_mux <= data_out; when IOI_DQ10 => data_out_mux <= data_out; when IOI_DQ11 => data_out_mux <= data_out; when IOI_DQ12 => data_out_mux <= data_out; when IOI_DQ13 => data_out_mux <= data_out; when IOI_DQ14 => data_out_mux <= data_out; when IOI_DQ15 => data_out_mux <= data_out; when IOI_UDQS_CLK => data_out_mux <= data_out; when IOI_UDQS_PIN => data_out_mux <= data_out; when IOI_LDQS_CLK => data_out_mux <= data_out; when IOI_LDQS_PIN => data_out_mux <= data_out; when others => data_out_mux <= data_out; end case; end process; data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else ('0' & data_reg); process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then shift_through_reg <= "000000000"; else if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first shift_through_reg <= data_out_mux; else shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1)); end if; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then bit_cnt <= bit_cnt + "001"; else bit_cnt <= "000"; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then read_data <= "00000000"; else if (state = ALMOST_READY3) then read_data <= shift_through_reg(7 downto 0); end if; end if; end if; end process; ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0'; ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0'; BIT_CNT7 <= '1' when bit_cnt = "111" else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then AddressPhase <= '0'; else if (AddressPhase = '1') then -- Keep it set until we finish the cycle AddressPhase <= AddressPhase and (not ALMOST_READY2_ST); else -- set the address phase when ever we finish the address phase AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7); end if; end if; end if; end process; ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0'; DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then DRP_ADD_xilinx0 <= ADDR_PHASE_ST1; -- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE); DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST; MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg; if (state = READY) then DRP_BKST <= use_broadcast; end if; end if; end process; DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance '0'; DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance DRP_SDI_pre; process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7) begin addr_data_sel_n <= '0'; load_shift_n <= '0'; case state is when READY => load_shift_n <= '0'; if (cmd_valid = '1') then nextstate <= DECIDE; else nextstate <= READY; end if; when DECIDE => load_shift_n <= '1'; addr_data_sel_n <= '1'; nextstate <= ADDR_PHASE; -- After the second pass go to end of statemachine -- execute a second address phase for the alternative access method. when ADDR_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then if (('1' and rd_not_write_reg) = '1') then if (AddressPhase = '1') then nextstate <= ALMOST_READY; else nextstate <= DECIDE; end if; else nextstate <= ADDR_TO_DATA_GAP; end if; else nextstate <= ADDR_PHASE; end if; when ADDR_TO_DATA_GAP => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP2; when ADDR_TO_DATA_GAP2 => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP3; when ADDR_TO_DATA_GAP3 => load_shift_n <= '1'; nextstate <= DATA_PHASE; when DATA_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then nextstate <= ALMOST_READY; else nextstate <= DATA_PHASE; end if; when ALMOST_READY => load_shift_n <= '0'; nextstate <= ALMOST_READY2; when ALMOST_READY2 => load_shift_n <= '0'; nextstate <= ALMOST_READY3; when ALMOST_READY3 => load_shift_n <= '0'; nextstate <= READY; when others => load_shift_n <= '0'; nextstate <= READY; end case; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then state <= READY; else state <= nextstate; end if; end if; end process; end architecture trans;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: iodrp_mcb_controller.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for IODRP controller for v0.9 device -- --Reference: -- -- Revision: Date: Comment -- 1.0: 03/19/09: Initial version for IODRP_MCB read operations. -- 1.1: 04/03/09: SLH - Added left shift for certain IOI's -- 1.2: 02/14/11: Change FSM encoding from one-hot to gray to match Verilog version. -- End Revision --******************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity iodrp_mcb_controller is --output to IODRP SDI pin --input from IODRP SDO pin -- Register where memcell_address is captured during the READY state -- Register which stores the write data until it is ready to be shifted out -- The shift register which shifts out SDO and shifts in SDI. -- This register is loaded before the address or data phase, but continues to shift for a writeback of read data -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO -- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg -- The counter for which bit is being shifted during address or data phase -- This is set after the first address phase has executed -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg --added so that DRP_SDI output is only active when DRP_CS is active port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end entity iodrp_mcb_controller; architecture trans of iodrp_mcb_controller is type StType is ( READY, DECIDE , ADDR_PHASE , ADDR_TO_DATA_GAP , ADDR_TO_DATA_GAP2, ADDR_TO_DATA_GAP3, DATA_PHASE , ALMOST_READY , ALMOST_READY2 , ALMOST_READY3 ); constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001"; constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000"; constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011"; constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010"; constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101"; constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100"; constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111"; constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110"; constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001"; constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000"; constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011"; constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010"; constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101"; constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100"; constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111"; constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110"; constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101"; constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100"; constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111"; constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110"; signal memcell_addr_reg : std_logic_vector(7 downto 0); signal data_reg : std_logic_vector(7 downto 0); signal shift_through_reg : std_logic_vector(8 downto 0); signal load_shift_n : std_logic; signal addr_data_sel_n : std_logic; signal bit_cnt : std_logic_vector(2 downto 0); signal rd_not_write_reg : std_logic; signal AddressPhase : std_logic; signal DRP_CS_pre : std_logic; signal extra_cs : std_logic; signal state,nextstate : StType; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "gray"; attribute fsm_encoding of nextstate : signal is "gray"; signal data_out : std_logic_vector(8 downto 0); signal data_out_mux : std_logic_vector(8 downto 0); signal DRP_SDI_pre : std_logic; --synthesis translate_off signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0); -- case(state) --synthesis translate_on -- The changes below are to compensate for an issue with 1.0 silicon. -- It may still be necessary to add a clock cycle to the ADD and CS signals --`define DRP_v1_0_FIX // Uncomment out this line for synthesis procedure shift_n_expand( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(8 downto 0)) is variable data_out_xilinx2 : std_logic_vector(8 downto 0); begin if ((data_in(0)) = '1') then data_out_xilinx2(1 downto 0) := "11"; else data_out_xilinx2(1 downto 0) := "00"; end if; if (data_in(1 downto 0) = "10") then data_out_xilinx2(2 downto 1) := "11"; else data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1)); end if; if (data_in(2 downto 1) = "10") then data_out_xilinx2(3 downto 2) := "11"; else data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2)); end if; if (data_in(3 downto 2) = "10") then data_out_xilinx2(4 downto 3) := "11"; else data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3)); end if; if (data_in(4 downto 3) = "10") then data_out_xilinx2(5 downto 4) := "11"; else data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4)); end if; if (data_in(5 downto 4) = "10") then data_out_xilinx2(6 downto 5) := "11"; else data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5)); end if; if (data_in(6 downto 5) = "10") then data_out_xilinx2(7 downto 6) := "11"; else data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6)); end if; if (data_in(7 downto 6) = "10") then data_out_xilinx2(8 downto 7) := "11"; else data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7)); end if; end shift_n_expand; -- Declare intermediate signals for referenced outputs signal DRP_CS_xilinx1 : std_logic; signal DRP_ADD_xilinx0 : std_logic; signal ALMOST_READY2_ST : std_logic; signal ADDR_PHASE_ST : std_logic; signal BIT_CNT7 : std_logic; signal ADDR_PHASE_ST1 : std_logic; signal DATA_PHASE_ST : std_logic; begin -- Drive referenced outputs DRP_CS <= DRP_CS_xilinx1; DRP_ADD <= DRP_ADD_xilinx0; -- process (state) -- begin -- case state is -- when READY => -- state_ascii <= "READY"; -- when DECIDE => -- state_ascii <= "DECIDE"; -- when ADDR_PHASE => -- state_ascii <= "ADDR_PHASE"; -- when ADDR_TO_DATA_GAP => -- state_ascii <= "ADDR_TO_DATA_GAP"; -- when ADDR_TO_DATA_GAP2 => -- state_ascii <= "ADDR_TO_DATA_GAP2"; -- when ADDR_TO_DATA_GAP3 => -- state_ascii <= "ADDR_TO_DATA_GAP3"; -- when DATA_PHASE => -- state_ascii <= "DATA_PHASE"; -- when ALMOST_READY => -- state_ascii <= "ALMOST_READY"; -- when ALMOST_READY2 => -- state_ascii <= "ALMOST_READY2"; -- when ALMOST_READY3 => -- state_ascii <= "ALMOST_READY3"; -- when others => -- null; -- end case; -- end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (state = READY) then memcell_addr_reg <= memcell_address; data_reg <= write_data; rd_not_write_reg <= rd_not_write; end if; end if; end process; rdy_busy_n <= '1' when state = READY else '0'; process (drp_ioi_addr, data_out) begin case drp_ioi_addr is when IOI_DQ0 => data_out_mux <= data_out; when IOI_DQ1 => data_out_mux <= data_out; when IOI_DQ2 => data_out_mux <= data_out; when IOI_DQ3 => data_out_mux <= data_out; when IOI_DQ4 => data_out_mux <= data_out; when IOI_DQ5 => data_out_mux <= data_out; when IOI_DQ6 => data_out_mux <= data_out; when IOI_DQ7 => data_out_mux <= data_out; when IOI_DQ8 => data_out_mux <= data_out; when IOI_DQ9 => data_out_mux <= data_out; when IOI_DQ10 => data_out_mux <= data_out; when IOI_DQ11 => data_out_mux <= data_out; when IOI_DQ12 => data_out_mux <= data_out; when IOI_DQ13 => data_out_mux <= data_out; when IOI_DQ14 => data_out_mux <= data_out; when IOI_DQ15 => data_out_mux <= data_out; when IOI_UDQS_CLK => data_out_mux <= data_out; when IOI_UDQS_PIN => data_out_mux <= data_out; when IOI_LDQS_CLK => data_out_mux <= data_out; when IOI_LDQS_PIN => data_out_mux <= data_out; when others => data_out_mux <= data_out; end case; end process; data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else ('0' & data_reg); process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then shift_through_reg <= "000000000"; else if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first shift_through_reg <= data_out_mux; else shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1)); end if; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then bit_cnt <= bit_cnt + "001"; else bit_cnt <= "000"; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then read_data <= "00000000"; else if (state = ALMOST_READY3) then read_data <= shift_through_reg(7 downto 0); end if; end if; end if; end process; ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0'; ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0'; BIT_CNT7 <= '1' when bit_cnt = "111" else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then AddressPhase <= '0'; else if (AddressPhase = '1') then -- Keep it set until we finish the cycle AddressPhase <= AddressPhase and (not ALMOST_READY2_ST); else -- set the address phase when ever we finish the address phase AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7); end if; end if; end if; end process; ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0'; DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then DRP_ADD_xilinx0 <= ADDR_PHASE_ST1; -- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE); DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST; MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg; if (state = READY) then DRP_BKST <= use_broadcast; end if; end if; end process; DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance '0'; DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance DRP_SDI_pre; process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7) begin addr_data_sel_n <= '0'; load_shift_n <= '0'; case state is when READY => load_shift_n <= '0'; if (cmd_valid = '1') then nextstate <= DECIDE; else nextstate <= READY; end if; when DECIDE => load_shift_n <= '1'; addr_data_sel_n <= '1'; nextstate <= ADDR_PHASE; -- After the second pass go to end of statemachine -- execute a second address phase for the alternative access method. when ADDR_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then if (('1' and rd_not_write_reg) = '1') then if (AddressPhase = '1') then nextstate <= ALMOST_READY; else nextstate <= DECIDE; end if; else nextstate <= ADDR_TO_DATA_GAP; end if; else nextstate <= ADDR_PHASE; end if; when ADDR_TO_DATA_GAP => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP2; when ADDR_TO_DATA_GAP2 => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP3; when ADDR_TO_DATA_GAP3 => load_shift_n <= '1'; nextstate <= DATA_PHASE; when DATA_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then nextstate <= ALMOST_READY; else nextstate <= DATA_PHASE; end if; when ALMOST_READY => load_shift_n <= '0'; nextstate <= ALMOST_READY2; when ALMOST_READY2 => load_shift_n <= '0'; nextstate <= ALMOST_READY3; when ALMOST_READY3 => load_shift_n <= '0'; nextstate <= READY; when others => load_shift_n <= '0'; nextstate <= READY; end case; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then state <= READY; else state <= nextstate; end if; end if; end process; end architecture trans;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: iodrp_mcb_controller.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for IODRP controller for v0.9 device -- --Reference: -- -- Revision: Date: Comment -- 1.0: 03/19/09: Initial version for IODRP_MCB read operations. -- 1.1: 04/03/09: SLH - Added left shift for certain IOI's -- 1.2: 02/14/11: Change FSM encoding from one-hot to gray to match Verilog version. -- End Revision --******************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity iodrp_mcb_controller is --output to IODRP SDI pin --input from IODRP SDO pin -- Register where memcell_address is captured during the READY state -- Register which stores the write data until it is ready to be shifted out -- The shift register which shifts out SDO and shifts in SDI. -- This register is loaded before the address or data phase, but continues to shift for a writeback of read data -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO -- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg -- The counter for which bit is being shifted during address or data phase -- This is set after the first address phase has executed -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg --added so that DRP_SDI output is only active when DRP_CS is active port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end entity iodrp_mcb_controller; architecture trans of iodrp_mcb_controller is type StType is ( READY, DECIDE , ADDR_PHASE , ADDR_TO_DATA_GAP , ADDR_TO_DATA_GAP2, ADDR_TO_DATA_GAP3, DATA_PHASE , ALMOST_READY , ALMOST_READY2 , ALMOST_READY3 ); constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001"; constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000"; constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011"; constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010"; constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101"; constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100"; constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111"; constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110"; constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001"; constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000"; constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011"; constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010"; constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101"; constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100"; constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111"; constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110"; constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101"; constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100"; constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111"; constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110"; signal memcell_addr_reg : std_logic_vector(7 downto 0); signal data_reg : std_logic_vector(7 downto 0); signal shift_through_reg : std_logic_vector(8 downto 0); signal load_shift_n : std_logic; signal addr_data_sel_n : std_logic; signal bit_cnt : std_logic_vector(2 downto 0); signal rd_not_write_reg : std_logic; signal AddressPhase : std_logic; signal DRP_CS_pre : std_logic; signal extra_cs : std_logic; signal state,nextstate : StType; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "gray"; attribute fsm_encoding of nextstate : signal is "gray"; signal data_out : std_logic_vector(8 downto 0); signal data_out_mux : std_logic_vector(8 downto 0); signal DRP_SDI_pre : std_logic; --synthesis translate_off signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0); -- case(state) --synthesis translate_on -- The changes below are to compensate for an issue with 1.0 silicon. -- It may still be necessary to add a clock cycle to the ADD and CS signals --`define DRP_v1_0_FIX // Uncomment out this line for synthesis procedure shift_n_expand( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(8 downto 0)) is variable data_out_xilinx2 : std_logic_vector(8 downto 0); begin if ((data_in(0)) = '1') then data_out_xilinx2(1 downto 0) := "11"; else data_out_xilinx2(1 downto 0) := "00"; end if; if (data_in(1 downto 0) = "10") then data_out_xilinx2(2 downto 1) := "11"; else data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1)); end if; if (data_in(2 downto 1) = "10") then data_out_xilinx2(3 downto 2) := "11"; else data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2)); end if; if (data_in(3 downto 2) = "10") then data_out_xilinx2(4 downto 3) := "11"; else data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3)); end if; if (data_in(4 downto 3) = "10") then data_out_xilinx2(5 downto 4) := "11"; else data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4)); end if; if (data_in(5 downto 4) = "10") then data_out_xilinx2(6 downto 5) := "11"; else data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5)); end if; if (data_in(6 downto 5) = "10") then data_out_xilinx2(7 downto 6) := "11"; else data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6)); end if; if (data_in(7 downto 6) = "10") then data_out_xilinx2(8 downto 7) := "11"; else data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7)); end if; end shift_n_expand; -- Declare intermediate signals for referenced outputs signal DRP_CS_xilinx1 : std_logic; signal DRP_ADD_xilinx0 : std_logic; signal ALMOST_READY2_ST : std_logic; signal ADDR_PHASE_ST : std_logic; signal BIT_CNT7 : std_logic; signal ADDR_PHASE_ST1 : std_logic; signal DATA_PHASE_ST : std_logic; begin -- Drive referenced outputs DRP_CS <= DRP_CS_xilinx1; DRP_ADD <= DRP_ADD_xilinx0; -- process (state) -- begin -- case state is -- when READY => -- state_ascii <= "READY"; -- when DECIDE => -- state_ascii <= "DECIDE"; -- when ADDR_PHASE => -- state_ascii <= "ADDR_PHASE"; -- when ADDR_TO_DATA_GAP => -- state_ascii <= "ADDR_TO_DATA_GAP"; -- when ADDR_TO_DATA_GAP2 => -- state_ascii <= "ADDR_TO_DATA_GAP2"; -- when ADDR_TO_DATA_GAP3 => -- state_ascii <= "ADDR_TO_DATA_GAP3"; -- when DATA_PHASE => -- state_ascii <= "DATA_PHASE"; -- when ALMOST_READY => -- state_ascii <= "ALMOST_READY"; -- when ALMOST_READY2 => -- state_ascii <= "ALMOST_READY2"; -- when ALMOST_READY3 => -- state_ascii <= "ALMOST_READY3"; -- when others => -- null; -- end case; -- end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (state = READY) then memcell_addr_reg <= memcell_address; data_reg <= write_data; rd_not_write_reg <= rd_not_write; end if; end if; end process; rdy_busy_n <= '1' when state = READY else '0'; process (drp_ioi_addr, data_out) begin case drp_ioi_addr is when IOI_DQ0 => data_out_mux <= data_out; when IOI_DQ1 => data_out_mux <= data_out; when IOI_DQ2 => data_out_mux <= data_out; when IOI_DQ3 => data_out_mux <= data_out; when IOI_DQ4 => data_out_mux <= data_out; when IOI_DQ5 => data_out_mux <= data_out; when IOI_DQ6 => data_out_mux <= data_out; when IOI_DQ7 => data_out_mux <= data_out; when IOI_DQ8 => data_out_mux <= data_out; when IOI_DQ9 => data_out_mux <= data_out; when IOI_DQ10 => data_out_mux <= data_out; when IOI_DQ11 => data_out_mux <= data_out; when IOI_DQ12 => data_out_mux <= data_out; when IOI_DQ13 => data_out_mux <= data_out; when IOI_DQ14 => data_out_mux <= data_out; when IOI_DQ15 => data_out_mux <= data_out; when IOI_UDQS_CLK => data_out_mux <= data_out; when IOI_UDQS_PIN => data_out_mux <= data_out; when IOI_LDQS_CLK => data_out_mux <= data_out; when IOI_LDQS_PIN => data_out_mux <= data_out; when others => data_out_mux <= data_out; end case; end process; data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else ('0' & data_reg); process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then shift_through_reg <= "000000000"; else if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first shift_through_reg <= data_out_mux; else shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1)); end if; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then bit_cnt <= bit_cnt + "001"; else bit_cnt <= "000"; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then read_data <= "00000000"; else if (state = ALMOST_READY3) then read_data <= shift_through_reg(7 downto 0); end if; end if; end if; end process; ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0'; ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0'; BIT_CNT7 <= '1' when bit_cnt = "111" else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then AddressPhase <= '0'; else if (AddressPhase = '1') then -- Keep it set until we finish the cycle AddressPhase <= AddressPhase and (not ALMOST_READY2_ST); else -- set the address phase when ever we finish the address phase AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7); end if; end if; end if; end process; ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0'; DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then DRP_ADD_xilinx0 <= ADDR_PHASE_ST1; -- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE); DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST; MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg; if (state = READY) then DRP_BKST <= use_broadcast; end if; end if; end process; DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance '0'; DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance DRP_SDI_pre; process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7) begin addr_data_sel_n <= '0'; load_shift_n <= '0'; case state is when READY => load_shift_n <= '0'; if (cmd_valid = '1') then nextstate <= DECIDE; else nextstate <= READY; end if; when DECIDE => load_shift_n <= '1'; addr_data_sel_n <= '1'; nextstate <= ADDR_PHASE; -- After the second pass go to end of statemachine -- execute a second address phase for the alternative access method. when ADDR_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then if (('1' and rd_not_write_reg) = '1') then if (AddressPhase = '1') then nextstate <= ALMOST_READY; else nextstate <= DECIDE; end if; else nextstate <= ADDR_TO_DATA_GAP; end if; else nextstate <= ADDR_PHASE; end if; when ADDR_TO_DATA_GAP => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP2; when ADDR_TO_DATA_GAP2 => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP3; when ADDR_TO_DATA_GAP3 => load_shift_n <= '1'; nextstate <= DATA_PHASE; when DATA_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then nextstate <= ALMOST_READY; else nextstate <= DATA_PHASE; end if; when ALMOST_READY => load_shift_n <= '0'; nextstate <= ALMOST_READY2; when ALMOST_READY2 => load_shift_n <= '0'; nextstate <= ALMOST_READY3; when ALMOST_READY3 => load_shift_n <= '0'; nextstate <= READY; when others => load_shift_n <= '0'; nextstate <= READY; end case; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then state <= READY; else state <= nextstate; end if; end if; end process; end architecture trans;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: iodrp_mcb_controller.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for IODRP controller for v0.9 device -- --Reference: -- -- Revision: Date: Comment -- 1.0: 03/19/09: Initial version for IODRP_MCB read operations. -- 1.1: 04/03/09: SLH - Added left shift for certain IOI's -- 1.2: 02/14/11: Change FSM encoding from one-hot to gray to match Verilog version. -- End Revision --******************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity iodrp_mcb_controller is --output to IODRP SDI pin --input from IODRP SDO pin -- Register where memcell_address is captured during the READY state -- Register which stores the write data until it is ready to be shifted out -- The shift register which shifts out SDO and shifts in SDI. -- This register is loaded before the address or data phase, but continues to shift for a writeback of read data -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO -- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg -- The counter for which bit is being shifted during address or data phase -- This is set after the first address phase has executed -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg --added so that DRP_SDI output is only active when DRP_CS is active port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end entity iodrp_mcb_controller; architecture trans of iodrp_mcb_controller is type StType is ( READY, DECIDE , ADDR_PHASE , ADDR_TO_DATA_GAP , ADDR_TO_DATA_GAP2, ADDR_TO_DATA_GAP3, DATA_PHASE , ALMOST_READY , ALMOST_READY2 , ALMOST_READY3 ); constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001"; constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000"; constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011"; constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010"; constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101"; constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100"; constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111"; constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110"; constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001"; constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000"; constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011"; constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010"; constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101"; constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100"; constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111"; constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110"; constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101"; constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100"; constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111"; constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110"; signal memcell_addr_reg : std_logic_vector(7 downto 0); signal data_reg : std_logic_vector(7 downto 0); signal shift_through_reg : std_logic_vector(8 downto 0); signal load_shift_n : std_logic; signal addr_data_sel_n : std_logic; signal bit_cnt : std_logic_vector(2 downto 0); signal rd_not_write_reg : std_logic; signal AddressPhase : std_logic; signal DRP_CS_pre : std_logic; signal extra_cs : std_logic; signal state,nextstate : StType; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "gray"; attribute fsm_encoding of nextstate : signal is "gray"; signal data_out : std_logic_vector(8 downto 0); signal data_out_mux : std_logic_vector(8 downto 0); signal DRP_SDI_pre : std_logic; --synthesis translate_off signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0); -- case(state) --synthesis translate_on -- The changes below are to compensate for an issue with 1.0 silicon. -- It may still be necessary to add a clock cycle to the ADD and CS signals --`define DRP_v1_0_FIX // Uncomment out this line for synthesis procedure shift_n_expand( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(8 downto 0)) is variable data_out_xilinx2 : std_logic_vector(8 downto 0); begin if ((data_in(0)) = '1') then data_out_xilinx2(1 downto 0) := "11"; else data_out_xilinx2(1 downto 0) := "00"; end if; if (data_in(1 downto 0) = "10") then data_out_xilinx2(2 downto 1) := "11"; else data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1)); end if; if (data_in(2 downto 1) = "10") then data_out_xilinx2(3 downto 2) := "11"; else data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2)); end if; if (data_in(3 downto 2) = "10") then data_out_xilinx2(4 downto 3) := "11"; else data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3)); end if; if (data_in(4 downto 3) = "10") then data_out_xilinx2(5 downto 4) := "11"; else data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4)); end if; if (data_in(5 downto 4) = "10") then data_out_xilinx2(6 downto 5) := "11"; else data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5)); end if; if (data_in(6 downto 5) = "10") then data_out_xilinx2(7 downto 6) := "11"; else data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6)); end if; if (data_in(7 downto 6) = "10") then data_out_xilinx2(8 downto 7) := "11"; else data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7)); end if; end shift_n_expand; -- Declare intermediate signals for referenced outputs signal DRP_CS_xilinx1 : std_logic; signal DRP_ADD_xilinx0 : std_logic; signal ALMOST_READY2_ST : std_logic; signal ADDR_PHASE_ST : std_logic; signal BIT_CNT7 : std_logic; signal ADDR_PHASE_ST1 : std_logic; signal DATA_PHASE_ST : std_logic; begin -- Drive referenced outputs DRP_CS <= DRP_CS_xilinx1; DRP_ADD <= DRP_ADD_xilinx0; -- process (state) -- begin -- case state is -- when READY => -- state_ascii <= "READY"; -- when DECIDE => -- state_ascii <= "DECIDE"; -- when ADDR_PHASE => -- state_ascii <= "ADDR_PHASE"; -- when ADDR_TO_DATA_GAP => -- state_ascii <= "ADDR_TO_DATA_GAP"; -- when ADDR_TO_DATA_GAP2 => -- state_ascii <= "ADDR_TO_DATA_GAP2"; -- when ADDR_TO_DATA_GAP3 => -- state_ascii <= "ADDR_TO_DATA_GAP3"; -- when DATA_PHASE => -- state_ascii <= "DATA_PHASE"; -- when ALMOST_READY => -- state_ascii <= "ALMOST_READY"; -- when ALMOST_READY2 => -- state_ascii <= "ALMOST_READY2"; -- when ALMOST_READY3 => -- state_ascii <= "ALMOST_READY3"; -- when others => -- null; -- end case; -- end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (state = READY) then memcell_addr_reg <= memcell_address; data_reg <= write_data; rd_not_write_reg <= rd_not_write; end if; end if; end process; rdy_busy_n <= '1' when state = READY else '0'; process (drp_ioi_addr, data_out) begin case drp_ioi_addr is when IOI_DQ0 => data_out_mux <= data_out; when IOI_DQ1 => data_out_mux <= data_out; when IOI_DQ2 => data_out_mux <= data_out; when IOI_DQ3 => data_out_mux <= data_out; when IOI_DQ4 => data_out_mux <= data_out; when IOI_DQ5 => data_out_mux <= data_out; when IOI_DQ6 => data_out_mux <= data_out; when IOI_DQ7 => data_out_mux <= data_out; when IOI_DQ8 => data_out_mux <= data_out; when IOI_DQ9 => data_out_mux <= data_out; when IOI_DQ10 => data_out_mux <= data_out; when IOI_DQ11 => data_out_mux <= data_out; when IOI_DQ12 => data_out_mux <= data_out; when IOI_DQ13 => data_out_mux <= data_out; when IOI_DQ14 => data_out_mux <= data_out; when IOI_DQ15 => data_out_mux <= data_out; when IOI_UDQS_CLK => data_out_mux <= data_out; when IOI_UDQS_PIN => data_out_mux <= data_out; when IOI_LDQS_CLK => data_out_mux <= data_out; when IOI_LDQS_PIN => data_out_mux <= data_out; when others => data_out_mux <= data_out; end case; end process; data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else ('0' & data_reg); process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then shift_through_reg <= "000000000"; else if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first shift_through_reg <= data_out_mux; else shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1)); end if; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then bit_cnt <= bit_cnt + "001"; else bit_cnt <= "000"; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then read_data <= "00000000"; else if (state = ALMOST_READY3) then read_data <= shift_through_reg(7 downto 0); end if; end if; end if; end process; ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0'; ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0'; BIT_CNT7 <= '1' when bit_cnt = "111" else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then AddressPhase <= '0'; else if (AddressPhase = '1') then -- Keep it set until we finish the cycle AddressPhase <= AddressPhase and (not ALMOST_READY2_ST); else -- set the address phase when ever we finish the address phase AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7); end if; end if; end if; end process; ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0'; DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then DRP_ADD_xilinx0 <= ADDR_PHASE_ST1; -- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE); DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST; MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg; if (state = READY) then DRP_BKST <= use_broadcast; end if; end if; end process; DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance '0'; DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance DRP_SDI_pre; process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7) begin addr_data_sel_n <= '0'; load_shift_n <= '0'; case state is when READY => load_shift_n <= '0'; if (cmd_valid = '1') then nextstate <= DECIDE; else nextstate <= READY; end if; when DECIDE => load_shift_n <= '1'; addr_data_sel_n <= '1'; nextstate <= ADDR_PHASE; -- After the second pass go to end of statemachine -- execute a second address phase for the alternative access method. when ADDR_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then if (('1' and rd_not_write_reg) = '1') then if (AddressPhase = '1') then nextstate <= ALMOST_READY; else nextstate <= DECIDE; end if; else nextstate <= ADDR_TO_DATA_GAP; end if; else nextstate <= ADDR_PHASE; end if; when ADDR_TO_DATA_GAP => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP2; when ADDR_TO_DATA_GAP2 => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP3; when ADDR_TO_DATA_GAP3 => load_shift_n <= '1'; nextstate <= DATA_PHASE; when DATA_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then nextstate <= ALMOST_READY; else nextstate <= DATA_PHASE; end if; when ALMOST_READY => load_shift_n <= '0'; nextstate <= ALMOST_READY2; when ALMOST_READY2 => load_shift_n <= '0'; nextstate <= ALMOST_READY3; when ALMOST_READY3 => load_shift_n <= '0'; nextstate <= READY; when others => load_shift_n <= '0'; nextstate <= READY; end case; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then state <= READY; else state <= nextstate; end if; end if; end process; end architecture trans;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: iodrp_mcb_controller.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for IODRP controller for v0.9 device -- --Reference: -- -- Revision: Date: Comment -- 1.0: 03/19/09: Initial version for IODRP_MCB read operations. -- 1.1: 04/03/09: SLH - Added left shift for certain IOI's -- 1.2: 02/14/11: Change FSM encoding from one-hot to gray to match Verilog version. -- End Revision --******************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity iodrp_mcb_controller is --output to IODRP SDI pin --input from IODRP SDO pin -- Register where memcell_address is captured during the READY state -- Register which stores the write data until it is ready to be shifted out -- The shift register which shifts out SDO and shifts in SDI. -- This register is loaded before the address or data phase, but continues to shift for a writeback of read data -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO -- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg -- The counter for which bit is being shifted during address or data phase -- This is set after the first address phase has executed -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg --added so that DRP_SDI output is only active when DRP_CS is active port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end entity iodrp_mcb_controller; architecture trans of iodrp_mcb_controller is type StType is ( READY, DECIDE , ADDR_PHASE , ADDR_TO_DATA_GAP , ADDR_TO_DATA_GAP2, ADDR_TO_DATA_GAP3, DATA_PHASE , ALMOST_READY , ALMOST_READY2 , ALMOST_READY3 ); constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001"; constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000"; constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011"; constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010"; constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101"; constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100"; constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111"; constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110"; constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001"; constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000"; constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011"; constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010"; constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101"; constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100"; constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111"; constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110"; constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101"; constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100"; constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111"; constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110"; signal memcell_addr_reg : std_logic_vector(7 downto 0); signal data_reg : std_logic_vector(7 downto 0); signal shift_through_reg : std_logic_vector(8 downto 0); signal load_shift_n : std_logic; signal addr_data_sel_n : std_logic; signal bit_cnt : std_logic_vector(2 downto 0); signal rd_not_write_reg : std_logic; signal AddressPhase : std_logic; signal DRP_CS_pre : std_logic; signal extra_cs : std_logic; signal state,nextstate : StType; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "gray"; attribute fsm_encoding of nextstate : signal is "gray"; signal data_out : std_logic_vector(8 downto 0); signal data_out_mux : std_logic_vector(8 downto 0); signal DRP_SDI_pre : std_logic; --synthesis translate_off signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0); -- case(state) --synthesis translate_on -- The changes below are to compensate for an issue with 1.0 silicon. -- It may still be necessary to add a clock cycle to the ADD and CS signals --`define DRP_v1_0_FIX // Uncomment out this line for synthesis procedure shift_n_expand( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(8 downto 0)) is variable data_out_xilinx2 : std_logic_vector(8 downto 0); begin if ((data_in(0)) = '1') then data_out_xilinx2(1 downto 0) := "11"; else data_out_xilinx2(1 downto 0) := "00"; end if; if (data_in(1 downto 0) = "10") then data_out_xilinx2(2 downto 1) := "11"; else data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1)); end if; if (data_in(2 downto 1) = "10") then data_out_xilinx2(3 downto 2) := "11"; else data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2)); end if; if (data_in(3 downto 2) = "10") then data_out_xilinx2(4 downto 3) := "11"; else data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3)); end if; if (data_in(4 downto 3) = "10") then data_out_xilinx2(5 downto 4) := "11"; else data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4)); end if; if (data_in(5 downto 4) = "10") then data_out_xilinx2(6 downto 5) := "11"; else data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5)); end if; if (data_in(6 downto 5) = "10") then data_out_xilinx2(7 downto 6) := "11"; else data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6)); end if; if (data_in(7 downto 6) = "10") then data_out_xilinx2(8 downto 7) := "11"; else data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7)); end if; end shift_n_expand; -- Declare intermediate signals for referenced outputs signal DRP_CS_xilinx1 : std_logic; signal DRP_ADD_xilinx0 : std_logic; signal ALMOST_READY2_ST : std_logic; signal ADDR_PHASE_ST : std_logic; signal BIT_CNT7 : std_logic; signal ADDR_PHASE_ST1 : std_logic; signal DATA_PHASE_ST : std_logic; begin -- Drive referenced outputs DRP_CS <= DRP_CS_xilinx1; DRP_ADD <= DRP_ADD_xilinx0; -- process (state) -- begin -- case state is -- when READY => -- state_ascii <= "READY"; -- when DECIDE => -- state_ascii <= "DECIDE"; -- when ADDR_PHASE => -- state_ascii <= "ADDR_PHASE"; -- when ADDR_TO_DATA_GAP => -- state_ascii <= "ADDR_TO_DATA_GAP"; -- when ADDR_TO_DATA_GAP2 => -- state_ascii <= "ADDR_TO_DATA_GAP2"; -- when ADDR_TO_DATA_GAP3 => -- state_ascii <= "ADDR_TO_DATA_GAP3"; -- when DATA_PHASE => -- state_ascii <= "DATA_PHASE"; -- when ALMOST_READY => -- state_ascii <= "ALMOST_READY"; -- when ALMOST_READY2 => -- state_ascii <= "ALMOST_READY2"; -- when ALMOST_READY3 => -- state_ascii <= "ALMOST_READY3"; -- when others => -- null; -- end case; -- end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (state = READY) then memcell_addr_reg <= memcell_address; data_reg <= write_data; rd_not_write_reg <= rd_not_write; end if; end if; end process; rdy_busy_n <= '1' when state = READY else '0'; process (drp_ioi_addr, data_out) begin case drp_ioi_addr is when IOI_DQ0 => data_out_mux <= data_out; when IOI_DQ1 => data_out_mux <= data_out; when IOI_DQ2 => data_out_mux <= data_out; when IOI_DQ3 => data_out_mux <= data_out; when IOI_DQ4 => data_out_mux <= data_out; when IOI_DQ5 => data_out_mux <= data_out; when IOI_DQ6 => data_out_mux <= data_out; when IOI_DQ7 => data_out_mux <= data_out; when IOI_DQ8 => data_out_mux <= data_out; when IOI_DQ9 => data_out_mux <= data_out; when IOI_DQ10 => data_out_mux <= data_out; when IOI_DQ11 => data_out_mux <= data_out; when IOI_DQ12 => data_out_mux <= data_out; when IOI_DQ13 => data_out_mux <= data_out; when IOI_DQ14 => data_out_mux <= data_out; when IOI_DQ15 => data_out_mux <= data_out; when IOI_UDQS_CLK => data_out_mux <= data_out; when IOI_UDQS_PIN => data_out_mux <= data_out; when IOI_LDQS_CLK => data_out_mux <= data_out; when IOI_LDQS_PIN => data_out_mux <= data_out; when others => data_out_mux <= data_out; end case; end process; data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else ('0' & data_reg); process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then shift_through_reg <= "000000000"; else if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first shift_through_reg <= data_out_mux; else shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1)); end if; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then bit_cnt <= bit_cnt + "001"; else bit_cnt <= "000"; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then read_data <= "00000000"; else if (state = ALMOST_READY3) then read_data <= shift_through_reg(7 downto 0); end if; end if; end if; end process; ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0'; ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0'; BIT_CNT7 <= '1' when bit_cnt = "111" else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then AddressPhase <= '0'; else if (AddressPhase = '1') then -- Keep it set until we finish the cycle AddressPhase <= AddressPhase and (not ALMOST_READY2_ST); else -- set the address phase when ever we finish the address phase AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7); end if; end if; end if; end process; ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0'; DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then DRP_ADD_xilinx0 <= ADDR_PHASE_ST1; -- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE); DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST; MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg; if (state = READY) then DRP_BKST <= use_broadcast; end if; end if; end process; DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance '0'; DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance DRP_SDI_pre; process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7) begin addr_data_sel_n <= '0'; load_shift_n <= '0'; case state is when READY => load_shift_n <= '0'; if (cmd_valid = '1') then nextstate <= DECIDE; else nextstate <= READY; end if; when DECIDE => load_shift_n <= '1'; addr_data_sel_n <= '1'; nextstate <= ADDR_PHASE; -- After the second pass go to end of statemachine -- execute a second address phase for the alternative access method. when ADDR_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then if (('1' and rd_not_write_reg) = '1') then if (AddressPhase = '1') then nextstate <= ALMOST_READY; else nextstate <= DECIDE; end if; else nextstate <= ADDR_TO_DATA_GAP; end if; else nextstate <= ADDR_PHASE; end if; when ADDR_TO_DATA_GAP => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP2; when ADDR_TO_DATA_GAP2 => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP3; when ADDR_TO_DATA_GAP3 => load_shift_n <= '1'; nextstate <= DATA_PHASE; when DATA_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then nextstate <= ALMOST_READY; else nextstate <= DATA_PHASE; end if; when ALMOST_READY => load_shift_n <= '0'; nextstate <= ALMOST_READY2; when ALMOST_READY2 => load_shift_n <= '0'; nextstate <= ALMOST_READY3; when ALMOST_READY3 => load_shift_n <= '0'; nextstate <= READY; when others => load_shift_n <= '0'; nextstate <= READY; end case; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then state <= READY; else state <= nextstate; end if; end if; end process; end architecture trans;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: iodrp_mcb_controller.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for IODRP controller for v0.9 device -- --Reference: -- -- Revision: Date: Comment -- 1.0: 03/19/09: Initial version for IODRP_MCB read operations. -- 1.1: 04/03/09: SLH - Added left shift for certain IOI's -- 1.2: 02/14/11: Change FSM encoding from one-hot to gray to match Verilog version. -- End Revision --******************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity iodrp_mcb_controller is --output to IODRP SDI pin --input from IODRP SDO pin -- Register where memcell_address is captured during the READY state -- Register which stores the write data until it is ready to be shifted out -- The shift register which shifts out SDO and shifts in SDI. -- This register is loaded before the address or data phase, but continues to shift for a writeback of read data -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO -- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg -- The counter for which bit is being shifted during address or data phase -- This is set after the first address phase has executed -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg --added so that DRP_SDI output is only active when DRP_CS is active port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end entity iodrp_mcb_controller; architecture trans of iodrp_mcb_controller is type StType is ( READY, DECIDE , ADDR_PHASE , ADDR_TO_DATA_GAP , ADDR_TO_DATA_GAP2, ADDR_TO_DATA_GAP3, DATA_PHASE , ALMOST_READY , ALMOST_READY2 , ALMOST_READY3 ); constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001"; constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000"; constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011"; constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010"; constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101"; constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100"; constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111"; constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110"; constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001"; constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000"; constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011"; constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010"; constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101"; constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100"; constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111"; constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110"; constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101"; constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100"; constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111"; constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110"; signal memcell_addr_reg : std_logic_vector(7 downto 0); signal data_reg : std_logic_vector(7 downto 0); signal shift_through_reg : std_logic_vector(8 downto 0); signal load_shift_n : std_logic; signal addr_data_sel_n : std_logic; signal bit_cnt : std_logic_vector(2 downto 0); signal rd_not_write_reg : std_logic; signal AddressPhase : std_logic; signal DRP_CS_pre : std_logic; signal extra_cs : std_logic; signal state,nextstate : StType; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "gray"; attribute fsm_encoding of nextstate : signal is "gray"; signal data_out : std_logic_vector(8 downto 0); signal data_out_mux : std_logic_vector(8 downto 0); signal DRP_SDI_pre : std_logic; --synthesis translate_off signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0); -- case(state) --synthesis translate_on -- The changes below are to compensate for an issue with 1.0 silicon. -- It may still be necessary to add a clock cycle to the ADD and CS signals --`define DRP_v1_0_FIX // Uncomment out this line for synthesis procedure shift_n_expand( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(8 downto 0)) is variable data_out_xilinx2 : std_logic_vector(8 downto 0); begin if ((data_in(0)) = '1') then data_out_xilinx2(1 downto 0) := "11"; else data_out_xilinx2(1 downto 0) := "00"; end if; if (data_in(1 downto 0) = "10") then data_out_xilinx2(2 downto 1) := "11"; else data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1)); end if; if (data_in(2 downto 1) = "10") then data_out_xilinx2(3 downto 2) := "11"; else data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2)); end if; if (data_in(3 downto 2) = "10") then data_out_xilinx2(4 downto 3) := "11"; else data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3)); end if; if (data_in(4 downto 3) = "10") then data_out_xilinx2(5 downto 4) := "11"; else data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4)); end if; if (data_in(5 downto 4) = "10") then data_out_xilinx2(6 downto 5) := "11"; else data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5)); end if; if (data_in(6 downto 5) = "10") then data_out_xilinx2(7 downto 6) := "11"; else data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6)); end if; if (data_in(7 downto 6) = "10") then data_out_xilinx2(8 downto 7) := "11"; else data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7)); end if; end shift_n_expand; -- Declare intermediate signals for referenced outputs signal DRP_CS_xilinx1 : std_logic; signal DRP_ADD_xilinx0 : std_logic; signal ALMOST_READY2_ST : std_logic; signal ADDR_PHASE_ST : std_logic; signal BIT_CNT7 : std_logic; signal ADDR_PHASE_ST1 : std_logic; signal DATA_PHASE_ST : std_logic; begin -- Drive referenced outputs DRP_CS <= DRP_CS_xilinx1; DRP_ADD <= DRP_ADD_xilinx0; -- process (state) -- begin -- case state is -- when READY => -- state_ascii <= "READY"; -- when DECIDE => -- state_ascii <= "DECIDE"; -- when ADDR_PHASE => -- state_ascii <= "ADDR_PHASE"; -- when ADDR_TO_DATA_GAP => -- state_ascii <= "ADDR_TO_DATA_GAP"; -- when ADDR_TO_DATA_GAP2 => -- state_ascii <= "ADDR_TO_DATA_GAP2"; -- when ADDR_TO_DATA_GAP3 => -- state_ascii <= "ADDR_TO_DATA_GAP3"; -- when DATA_PHASE => -- state_ascii <= "DATA_PHASE"; -- when ALMOST_READY => -- state_ascii <= "ALMOST_READY"; -- when ALMOST_READY2 => -- state_ascii <= "ALMOST_READY2"; -- when ALMOST_READY3 => -- state_ascii <= "ALMOST_READY3"; -- when others => -- null; -- end case; -- end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (state = READY) then memcell_addr_reg <= memcell_address; data_reg <= write_data; rd_not_write_reg <= rd_not_write; end if; end if; end process; rdy_busy_n <= '1' when state = READY else '0'; process (drp_ioi_addr, data_out) begin case drp_ioi_addr is when IOI_DQ0 => data_out_mux <= data_out; when IOI_DQ1 => data_out_mux <= data_out; when IOI_DQ2 => data_out_mux <= data_out; when IOI_DQ3 => data_out_mux <= data_out; when IOI_DQ4 => data_out_mux <= data_out; when IOI_DQ5 => data_out_mux <= data_out; when IOI_DQ6 => data_out_mux <= data_out; when IOI_DQ7 => data_out_mux <= data_out; when IOI_DQ8 => data_out_mux <= data_out; when IOI_DQ9 => data_out_mux <= data_out; when IOI_DQ10 => data_out_mux <= data_out; when IOI_DQ11 => data_out_mux <= data_out; when IOI_DQ12 => data_out_mux <= data_out; when IOI_DQ13 => data_out_mux <= data_out; when IOI_DQ14 => data_out_mux <= data_out; when IOI_DQ15 => data_out_mux <= data_out; when IOI_UDQS_CLK => data_out_mux <= data_out; when IOI_UDQS_PIN => data_out_mux <= data_out; when IOI_LDQS_CLK => data_out_mux <= data_out; when IOI_LDQS_PIN => data_out_mux <= data_out; when others => data_out_mux <= data_out; end case; end process; data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else ('0' & data_reg); process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then shift_through_reg <= "000000000"; else if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first shift_through_reg <= data_out_mux; else shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1)); end if; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then bit_cnt <= bit_cnt + "001"; else bit_cnt <= "000"; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then read_data <= "00000000"; else if (state = ALMOST_READY3) then read_data <= shift_through_reg(7 downto 0); end if; end if; end if; end process; ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0'; ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0'; BIT_CNT7 <= '1' when bit_cnt = "111" else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then AddressPhase <= '0'; else if (AddressPhase = '1') then -- Keep it set until we finish the cycle AddressPhase <= AddressPhase and (not ALMOST_READY2_ST); else -- set the address phase when ever we finish the address phase AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7); end if; end if; end if; end process; ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0'; DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then DRP_ADD_xilinx0 <= ADDR_PHASE_ST1; -- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE); DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST; MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg; if (state = READY) then DRP_BKST <= use_broadcast; end if; end if; end process; DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance '0'; DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance DRP_SDI_pre; process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7) begin addr_data_sel_n <= '0'; load_shift_n <= '0'; case state is when READY => load_shift_n <= '0'; if (cmd_valid = '1') then nextstate <= DECIDE; else nextstate <= READY; end if; when DECIDE => load_shift_n <= '1'; addr_data_sel_n <= '1'; nextstate <= ADDR_PHASE; -- After the second pass go to end of statemachine -- execute a second address phase for the alternative access method. when ADDR_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then if (('1' and rd_not_write_reg) = '1') then if (AddressPhase = '1') then nextstate <= ALMOST_READY; else nextstate <= DECIDE; end if; else nextstate <= ADDR_TO_DATA_GAP; end if; else nextstate <= ADDR_PHASE; end if; when ADDR_TO_DATA_GAP => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP2; when ADDR_TO_DATA_GAP2 => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP3; when ADDR_TO_DATA_GAP3 => load_shift_n <= '1'; nextstate <= DATA_PHASE; when DATA_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then nextstate <= ALMOST_READY; else nextstate <= DATA_PHASE; end if; when ALMOST_READY => load_shift_n <= '0'; nextstate <= ALMOST_READY2; when ALMOST_READY2 => load_shift_n <= '0'; nextstate <= ALMOST_READY3; when ALMOST_READY3 => load_shift_n <= '0'; nextstate <= READY; when others => load_shift_n <= '0'; nextstate <= READY; end case; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then state <= READY; else state <= nextstate; end if; end if; end process; end architecture trans;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: iodrp_mcb_controller.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for IODRP controller for v0.9 device -- --Reference: -- -- Revision: Date: Comment -- 1.0: 03/19/09: Initial version for IODRP_MCB read operations. -- 1.1: 04/03/09: SLH - Added left shift for certain IOI's -- 1.2: 02/14/11: Change FSM encoding from one-hot to gray to match Verilog version. -- End Revision --******************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity iodrp_mcb_controller is --output to IODRP SDI pin --input from IODRP SDO pin -- Register where memcell_address is captured during the READY state -- Register which stores the write data until it is ready to be shifted out -- The shift register which shifts out SDO and shifts in SDI. -- This register is loaded before the address or data phase, but continues to shift for a writeback of read data -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO -- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg -- The counter for which bit is being shifted during address or data phase -- This is set after the first address phase has executed -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg --added so that DRP_SDI output is only active when DRP_CS is active port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end entity iodrp_mcb_controller; architecture trans of iodrp_mcb_controller is type StType is ( READY, DECIDE , ADDR_PHASE , ADDR_TO_DATA_GAP , ADDR_TO_DATA_GAP2, ADDR_TO_DATA_GAP3, DATA_PHASE , ALMOST_READY , ALMOST_READY2 , ALMOST_READY3 ); constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001"; constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000"; constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011"; constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010"; constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101"; constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100"; constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111"; constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110"; constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001"; constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000"; constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011"; constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010"; constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101"; constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100"; constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111"; constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110"; constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101"; constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100"; constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111"; constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110"; signal memcell_addr_reg : std_logic_vector(7 downto 0); signal data_reg : std_logic_vector(7 downto 0); signal shift_through_reg : std_logic_vector(8 downto 0); signal load_shift_n : std_logic; signal addr_data_sel_n : std_logic; signal bit_cnt : std_logic_vector(2 downto 0); signal rd_not_write_reg : std_logic; signal AddressPhase : std_logic; signal DRP_CS_pre : std_logic; signal extra_cs : std_logic; signal state,nextstate : StType; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "gray"; attribute fsm_encoding of nextstate : signal is "gray"; signal data_out : std_logic_vector(8 downto 0); signal data_out_mux : std_logic_vector(8 downto 0); signal DRP_SDI_pre : std_logic; --synthesis translate_off signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0); -- case(state) --synthesis translate_on -- The changes below are to compensate for an issue with 1.0 silicon. -- It may still be necessary to add a clock cycle to the ADD and CS signals --`define DRP_v1_0_FIX // Uncomment out this line for synthesis procedure shift_n_expand( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(8 downto 0)) is variable data_out_xilinx2 : std_logic_vector(8 downto 0); begin if ((data_in(0)) = '1') then data_out_xilinx2(1 downto 0) := "11"; else data_out_xilinx2(1 downto 0) := "00"; end if; if (data_in(1 downto 0) = "10") then data_out_xilinx2(2 downto 1) := "11"; else data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1)); end if; if (data_in(2 downto 1) = "10") then data_out_xilinx2(3 downto 2) := "11"; else data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2)); end if; if (data_in(3 downto 2) = "10") then data_out_xilinx2(4 downto 3) := "11"; else data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3)); end if; if (data_in(4 downto 3) = "10") then data_out_xilinx2(5 downto 4) := "11"; else data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4)); end if; if (data_in(5 downto 4) = "10") then data_out_xilinx2(6 downto 5) := "11"; else data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5)); end if; if (data_in(6 downto 5) = "10") then data_out_xilinx2(7 downto 6) := "11"; else data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6)); end if; if (data_in(7 downto 6) = "10") then data_out_xilinx2(8 downto 7) := "11"; else data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7)); end if; end shift_n_expand; -- Declare intermediate signals for referenced outputs signal DRP_CS_xilinx1 : std_logic; signal DRP_ADD_xilinx0 : std_logic; signal ALMOST_READY2_ST : std_logic; signal ADDR_PHASE_ST : std_logic; signal BIT_CNT7 : std_logic; signal ADDR_PHASE_ST1 : std_logic; signal DATA_PHASE_ST : std_logic; begin -- Drive referenced outputs DRP_CS <= DRP_CS_xilinx1; DRP_ADD <= DRP_ADD_xilinx0; -- process (state) -- begin -- case state is -- when READY => -- state_ascii <= "READY"; -- when DECIDE => -- state_ascii <= "DECIDE"; -- when ADDR_PHASE => -- state_ascii <= "ADDR_PHASE"; -- when ADDR_TO_DATA_GAP => -- state_ascii <= "ADDR_TO_DATA_GAP"; -- when ADDR_TO_DATA_GAP2 => -- state_ascii <= "ADDR_TO_DATA_GAP2"; -- when ADDR_TO_DATA_GAP3 => -- state_ascii <= "ADDR_TO_DATA_GAP3"; -- when DATA_PHASE => -- state_ascii <= "DATA_PHASE"; -- when ALMOST_READY => -- state_ascii <= "ALMOST_READY"; -- when ALMOST_READY2 => -- state_ascii <= "ALMOST_READY2"; -- when ALMOST_READY3 => -- state_ascii <= "ALMOST_READY3"; -- when others => -- null; -- end case; -- end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (state = READY) then memcell_addr_reg <= memcell_address; data_reg <= write_data; rd_not_write_reg <= rd_not_write; end if; end if; end process; rdy_busy_n <= '1' when state = READY else '0'; process (drp_ioi_addr, data_out) begin case drp_ioi_addr is when IOI_DQ0 => data_out_mux <= data_out; when IOI_DQ1 => data_out_mux <= data_out; when IOI_DQ2 => data_out_mux <= data_out; when IOI_DQ3 => data_out_mux <= data_out; when IOI_DQ4 => data_out_mux <= data_out; when IOI_DQ5 => data_out_mux <= data_out; when IOI_DQ6 => data_out_mux <= data_out; when IOI_DQ7 => data_out_mux <= data_out; when IOI_DQ8 => data_out_mux <= data_out; when IOI_DQ9 => data_out_mux <= data_out; when IOI_DQ10 => data_out_mux <= data_out; when IOI_DQ11 => data_out_mux <= data_out; when IOI_DQ12 => data_out_mux <= data_out; when IOI_DQ13 => data_out_mux <= data_out; when IOI_DQ14 => data_out_mux <= data_out; when IOI_DQ15 => data_out_mux <= data_out; when IOI_UDQS_CLK => data_out_mux <= data_out; when IOI_UDQS_PIN => data_out_mux <= data_out; when IOI_LDQS_CLK => data_out_mux <= data_out; when IOI_LDQS_PIN => data_out_mux <= data_out; when others => data_out_mux <= data_out; end case; end process; data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else ('0' & data_reg); process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then shift_through_reg <= "000000000"; else if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first shift_through_reg <= data_out_mux; else shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1)); end if; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then bit_cnt <= bit_cnt + "001"; else bit_cnt <= "000"; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then read_data <= "00000000"; else if (state = ALMOST_READY3) then read_data <= shift_through_reg(7 downto 0); end if; end if; end if; end process; ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0'; ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0'; BIT_CNT7 <= '1' when bit_cnt = "111" else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then AddressPhase <= '0'; else if (AddressPhase = '1') then -- Keep it set until we finish the cycle AddressPhase <= AddressPhase and (not ALMOST_READY2_ST); else -- set the address phase when ever we finish the address phase AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7); end if; end if; end if; end process; ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0'; DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then DRP_ADD_xilinx0 <= ADDR_PHASE_ST1; -- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE); DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST; MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg; if (state = READY) then DRP_BKST <= use_broadcast; end if; end if; end process; DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance '0'; DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance DRP_SDI_pre; process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7) begin addr_data_sel_n <= '0'; load_shift_n <= '0'; case state is when READY => load_shift_n <= '0'; if (cmd_valid = '1') then nextstate <= DECIDE; else nextstate <= READY; end if; when DECIDE => load_shift_n <= '1'; addr_data_sel_n <= '1'; nextstate <= ADDR_PHASE; -- After the second pass go to end of statemachine -- execute a second address phase for the alternative access method. when ADDR_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then if (('1' and rd_not_write_reg) = '1') then if (AddressPhase = '1') then nextstate <= ALMOST_READY; else nextstate <= DECIDE; end if; else nextstate <= ADDR_TO_DATA_GAP; end if; else nextstate <= ADDR_PHASE; end if; when ADDR_TO_DATA_GAP => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP2; when ADDR_TO_DATA_GAP2 => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP3; when ADDR_TO_DATA_GAP3 => load_shift_n <= '1'; nextstate <= DATA_PHASE; when DATA_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then nextstate <= ALMOST_READY; else nextstate <= DATA_PHASE; end if; when ALMOST_READY => load_shift_n <= '0'; nextstate <= ALMOST_READY2; when ALMOST_READY2 => load_shift_n <= '0'; nextstate <= ALMOST_READY3; when ALMOST_READY3 => load_shift_n <= '0'; nextstate <= READY; when others => load_shift_n <= '0'; nextstate <= READY; end case; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then state <= READY; else state <= nextstate; end if; end if; end process; end architecture trans;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: iodrp_mcb_controller.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for IODRP controller for v0.9 device -- --Reference: -- -- Revision: Date: Comment -- 1.0: 03/19/09: Initial version for IODRP_MCB read operations. -- 1.1: 04/03/09: SLH - Added left shift for certain IOI's -- 1.2: 02/14/11: Change FSM encoding from one-hot to gray to match Verilog version. -- End Revision --******************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity iodrp_mcb_controller is --output to IODRP SDI pin --input from IODRP SDO pin -- Register where memcell_address is captured during the READY state -- Register which stores the write data until it is ready to be shifted out -- The shift register which shifts out SDO and shifts in SDI. -- This register is loaded before the address or data phase, but continues to shift for a writeback of read data -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO -- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg -- The counter for which bit is being shifted during address or data phase -- This is set after the first address phase has executed -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg --added so that DRP_SDI output is only active when DRP_CS is active port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end entity iodrp_mcb_controller; architecture trans of iodrp_mcb_controller is type StType is ( READY, DECIDE , ADDR_PHASE , ADDR_TO_DATA_GAP , ADDR_TO_DATA_GAP2, ADDR_TO_DATA_GAP3, DATA_PHASE , ALMOST_READY , ALMOST_READY2 , ALMOST_READY3 ); constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001"; constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000"; constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011"; constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010"; constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101"; constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100"; constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111"; constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110"; constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001"; constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000"; constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011"; constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010"; constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101"; constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100"; constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111"; constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110"; constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101"; constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100"; constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111"; constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110"; signal memcell_addr_reg : std_logic_vector(7 downto 0); signal data_reg : std_logic_vector(7 downto 0); signal shift_through_reg : std_logic_vector(8 downto 0); signal load_shift_n : std_logic; signal addr_data_sel_n : std_logic; signal bit_cnt : std_logic_vector(2 downto 0); signal rd_not_write_reg : std_logic; signal AddressPhase : std_logic; signal DRP_CS_pre : std_logic; signal extra_cs : std_logic; signal state,nextstate : StType; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "gray"; attribute fsm_encoding of nextstate : signal is "gray"; signal data_out : std_logic_vector(8 downto 0); signal data_out_mux : std_logic_vector(8 downto 0); signal DRP_SDI_pre : std_logic; --synthesis translate_off signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0); -- case(state) --synthesis translate_on -- The changes below are to compensate for an issue with 1.0 silicon. -- It may still be necessary to add a clock cycle to the ADD and CS signals --`define DRP_v1_0_FIX // Uncomment out this line for synthesis procedure shift_n_expand( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(8 downto 0)) is variable data_out_xilinx2 : std_logic_vector(8 downto 0); begin if ((data_in(0)) = '1') then data_out_xilinx2(1 downto 0) := "11"; else data_out_xilinx2(1 downto 0) := "00"; end if; if (data_in(1 downto 0) = "10") then data_out_xilinx2(2 downto 1) := "11"; else data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1)); end if; if (data_in(2 downto 1) = "10") then data_out_xilinx2(3 downto 2) := "11"; else data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2)); end if; if (data_in(3 downto 2) = "10") then data_out_xilinx2(4 downto 3) := "11"; else data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3)); end if; if (data_in(4 downto 3) = "10") then data_out_xilinx2(5 downto 4) := "11"; else data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4)); end if; if (data_in(5 downto 4) = "10") then data_out_xilinx2(6 downto 5) := "11"; else data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5)); end if; if (data_in(6 downto 5) = "10") then data_out_xilinx2(7 downto 6) := "11"; else data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6)); end if; if (data_in(7 downto 6) = "10") then data_out_xilinx2(8 downto 7) := "11"; else data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7)); end if; end shift_n_expand; -- Declare intermediate signals for referenced outputs signal DRP_CS_xilinx1 : std_logic; signal DRP_ADD_xilinx0 : std_logic; signal ALMOST_READY2_ST : std_logic; signal ADDR_PHASE_ST : std_logic; signal BIT_CNT7 : std_logic; signal ADDR_PHASE_ST1 : std_logic; signal DATA_PHASE_ST : std_logic; begin -- Drive referenced outputs DRP_CS <= DRP_CS_xilinx1; DRP_ADD <= DRP_ADD_xilinx0; -- process (state) -- begin -- case state is -- when READY => -- state_ascii <= "READY"; -- when DECIDE => -- state_ascii <= "DECIDE"; -- when ADDR_PHASE => -- state_ascii <= "ADDR_PHASE"; -- when ADDR_TO_DATA_GAP => -- state_ascii <= "ADDR_TO_DATA_GAP"; -- when ADDR_TO_DATA_GAP2 => -- state_ascii <= "ADDR_TO_DATA_GAP2"; -- when ADDR_TO_DATA_GAP3 => -- state_ascii <= "ADDR_TO_DATA_GAP3"; -- when DATA_PHASE => -- state_ascii <= "DATA_PHASE"; -- when ALMOST_READY => -- state_ascii <= "ALMOST_READY"; -- when ALMOST_READY2 => -- state_ascii <= "ALMOST_READY2"; -- when ALMOST_READY3 => -- state_ascii <= "ALMOST_READY3"; -- when others => -- null; -- end case; -- end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (state = READY) then memcell_addr_reg <= memcell_address; data_reg <= write_data; rd_not_write_reg <= rd_not_write; end if; end if; end process; rdy_busy_n <= '1' when state = READY else '0'; process (drp_ioi_addr, data_out) begin case drp_ioi_addr is when IOI_DQ0 => data_out_mux <= data_out; when IOI_DQ1 => data_out_mux <= data_out; when IOI_DQ2 => data_out_mux <= data_out; when IOI_DQ3 => data_out_mux <= data_out; when IOI_DQ4 => data_out_mux <= data_out; when IOI_DQ5 => data_out_mux <= data_out; when IOI_DQ6 => data_out_mux <= data_out; when IOI_DQ7 => data_out_mux <= data_out; when IOI_DQ8 => data_out_mux <= data_out; when IOI_DQ9 => data_out_mux <= data_out; when IOI_DQ10 => data_out_mux <= data_out; when IOI_DQ11 => data_out_mux <= data_out; when IOI_DQ12 => data_out_mux <= data_out; when IOI_DQ13 => data_out_mux <= data_out; when IOI_DQ14 => data_out_mux <= data_out; when IOI_DQ15 => data_out_mux <= data_out; when IOI_UDQS_CLK => data_out_mux <= data_out; when IOI_UDQS_PIN => data_out_mux <= data_out; when IOI_LDQS_CLK => data_out_mux <= data_out; when IOI_LDQS_PIN => data_out_mux <= data_out; when others => data_out_mux <= data_out; end case; end process; data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else ('0' & data_reg); process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then shift_through_reg <= "000000000"; else if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first shift_through_reg <= data_out_mux; else shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1)); end if; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then bit_cnt <= bit_cnt + "001"; else bit_cnt <= "000"; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then read_data <= "00000000"; else if (state = ALMOST_READY3) then read_data <= shift_through_reg(7 downto 0); end if; end if; end if; end process; ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0'; ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0'; BIT_CNT7 <= '1' when bit_cnt = "111" else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then AddressPhase <= '0'; else if (AddressPhase = '1') then -- Keep it set until we finish the cycle AddressPhase <= AddressPhase and (not ALMOST_READY2_ST); else -- set the address phase when ever we finish the address phase AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7); end if; end if; end if; end process; ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0'; DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then DRP_ADD_xilinx0 <= ADDR_PHASE_ST1; -- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE); DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST; MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg; if (state = READY) then DRP_BKST <= use_broadcast; end if; end if; end process; DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance '0'; DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance DRP_SDI_pre; process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7) begin addr_data_sel_n <= '0'; load_shift_n <= '0'; case state is when READY => load_shift_n <= '0'; if (cmd_valid = '1') then nextstate <= DECIDE; else nextstate <= READY; end if; when DECIDE => load_shift_n <= '1'; addr_data_sel_n <= '1'; nextstate <= ADDR_PHASE; -- After the second pass go to end of statemachine -- execute a second address phase for the alternative access method. when ADDR_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then if (('1' and rd_not_write_reg) = '1') then if (AddressPhase = '1') then nextstate <= ALMOST_READY; else nextstate <= DECIDE; end if; else nextstate <= ADDR_TO_DATA_GAP; end if; else nextstate <= ADDR_PHASE; end if; when ADDR_TO_DATA_GAP => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP2; when ADDR_TO_DATA_GAP2 => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP3; when ADDR_TO_DATA_GAP3 => load_shift_n <= '1'; nextstate <= DATA_PHASE; when DATA_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then nextstate <= ALMOST_READY; else nextstate <= DATA_PHASE; end if; when ALMOST_READY => load_shift_n <= '0'; nextstate <= ALMOST_READY2; when ALMOST_READY2 => load_shift_n <= '0'; nextstate <= ALMOST_READY3; when ALMOST_READY3 => load_shift_n <= '0'; nextstate <= READY; when others => load_shift_n <= '0'; nextstate <= READY; end case; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then state <= READY; else state <= nextstate; end if; end if; end process; end architecture trans;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: iodrp_mcb_controller.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for IODRP controller for v0.9 device -- --Reference: -- -- Revision: Date: Comment -- 1.0: 03/19/09: Initial version for IODRP_MCB read operations. -- 1.1: 04/03/09: SLH - Added left shift for certain IOI's -- 1.2: 02/14/11: Change FSM encoding from one-hot to gray to match Verilog version. -- End Revision --******************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity iodrp_mcb_controller is --output to IODRP SDI pin --input from IODRP SDO pin -- Register where memcell_address is captured during the READY state -- Register which stores the write data until it is ready to be shifted out -- The shift register which shifts out SDO and shifts in SDI. -- This register is loaded before the address or data phase, but continues to shift for a writeback of read data -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO -- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg -- The counter for which bit is being shifted during address or data phase -- This is set after the first address phase has executed -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg --added so that DRP_SDI output is only active when DRP_CS is active port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end entity iodrp_mcb_controller; architecture trans of iodrp_mcb_controller is type StType is ( READY, DECIDE , ADDR_PHASE , ADDR_TO_DATA_GAP , ADDR_TO_DATA_GAP2, ADDR_TO_DATA_GAP3, DATA_PHASE , ALMOST_READY , ALMOST_READY2 , ALMOST_READY3 ); constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001"; constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000"; constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011"; constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010"; constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101"; constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100"; constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111"; constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110"; constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001"; constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000"; constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011"; constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010"; constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101"; constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100"; constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111"; constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110"; constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101"; constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100"; constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111"; constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110"; signal memcell_addr_reg : std_logic_vector(7 downto 0); signal data_reg : std_logic_vector(7 downto 0); signal shift_through_reg : std_logic_vector(8 downto 0); signal load_shift_n : std_logic; signal addr_data_sel_n : std_logic; signal bit_cnt : std_logic_vector(2 downto 0); signal rd_not_write_reg : std_logic; signal AddressPhase : std_logic; signal DRP_CS_pre : std_logic; signal extra_cs : std_logic; signal state,nextstate : StType; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "gray"; attribute fsm_encoding of nextstate : signal is "gray"; signal data_out : std_logic_vector(8 downto 0); signal data_out_mux : std_logic_vector(8 downto 0); signal DRP_SDI_pre : std_logic; --synthesis translate_off signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0); -- case(state) --synthesis translate_on -- The changes below are to compensate for an issue with 1.0 silicon. -- It may still be necessary to add a clock cycle to the ADD and CS signals --`define DRP_v1_0_FIX // Uncomment out this line for synthesis procedure shift_n_expand( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(8 downto 0)) is variable data_out_xilinx2 : std_logic_vector(8 downto 0); begin if ((data_in(0)) = '1') then data_out_xilinx2(1 downto 0) := "11"; else data_out_xilinx2(1 downto 0) := "00"; end if; if (data_in(1 downto 0) = "10") then data_out_xilinx2(2 downto 1) := "11"; else data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1)); end if; if (data_in(2 downto 1) = "10") then data_out_xilinx2(3 downto 2) := "11"; else data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2)); end if; if (data_in(3 downto 2) = "10") then data_out_xilinx2(4 downto 3) := "11"; else data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3)); end if; if (data_in(4 downto 3) = "10") then data_out_xilinx2(5 downto 4) := "11"; else data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4)); end if; if (data_in(5 downto 4) = "10") then data_out_xilinx2(6 downto 5) := "11"; else data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5)); end if; if (data_in(6 downto 5) = "10") then data_out_xilinx2(7 downto 6) := "11"; else data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6)); end if; if (data_in(7 downto 6) = "10") then data_out_xilinx2(8 downto 7) := "11"; else data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7)); end if; end shift_n_expand; -- Declare intermediate signals for referenced outputs signal DRP_CS_xilinx1 : std_logic; signal DRP_ADD_xilinx0 : std_logic; signal ALMOST_READY2_ST : std_logic; signal ADDR_PHASE_ST : std_logic; signal BIT_CNT7 : std_logic; signal ADDR_PHASE_ST1 : std_logic; signal DATA_PHASE_ST : std_logic; begin -- Drive referenced outputs DRP_CS <= DRP_CS_xilinx1; DRP_ADD <= DRP_ADD_xilinx0; -- process (state) -- begin -- case state is -- when READY => -- state_ascii <= "READY"; -- when DECIDE => -- state_ascii <= "DECIDE"; -- when ADDR_PHASE => -- state_ascii <= "ADDR_PHASE"; -- when ADDR_TO_DATA_GAP => -- state_ascii <= "ADDR_TO_DATA_GAP"; -- when ADDR_TO_DATA_GAP2 => -- state_ascii <= "ADDR_TO_DATA_GAP2"; -- when ADDR_TO_DATA_GAP3 => -- state_ascii <= "ADDR_TO_DATA_GAP3"; -- when DATA_PHASE => -- state_ascii <= "DATA_PHASE"; -- when ALMOST_READY => -- state_ascii <= "ALMOST_READY"; -- when ALMOST_READY2 => -- state_ascii <= "ALMOST_READY2"; -- when ALMOST_READY3 => -- state_ascii <= "ALMOST_READY3"; -- when others => -- null; -- end case; -- end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (state = READY) then memcell_addr_reg <= memcell_address; data_reg <= write_data; rd_not_write_reg <= rd_not_write; end if; end if; end process; rdy_busy_n <= '1' when state = READY else '0'; process (drp_ioi_addr, data_out) begin case drp_ioi_addr is when IOI_DQ0 => data_out_mux <= data_out; when IOI_DQ1 => data_out_mux <= data_out; when IOI_DQ2 => data_out_mux <= data_out; when IOI_DQ3 => data_out_mux <= data_out; when IOI_DQ4 => data_out_mux <= data_out; when IOI_DQ5 => data_out_mux <= data_out; when IOI_DQ6 => data_out_mux <= data_out; when IOI_DQ7 => data_out_mux <= data_out; when IOI_DQ8 => data_out_mux <= data_out; when IOI_DQ9 => data_out_mux <= data_out; when IOI_DQ10 => data_out_mux <= data_out; when IOI_DQ11 => data_out_mux <= data_out; when IOI_DQ12 => data_out_mux <= data_out; when IOI_DQ13 => data_out_mux <= data_out; when IOI_DQ14 => data_out_mux <= data_out; when IOI_DQ15 => data_out_mux <= data_out; when IOI_UDQS_CLK => data_out_mux <= data_out; when IOI_UDQS_PIN => data_out_mux <= data_out; when IOI_LDQS_CLK => data_out_mux <= data_out; when IOI_LDQS_PIN => data_out_mux <= data_out; when others => data_out_mux <= data_out; end case; end process; data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else ('0' & data_reg); process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then shift_through_reg <= "000000000"; else if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first shift_through_reg <= data_out_mux; else shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1)); end if; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then bit_cnt <= bit_cnt + "001"; else bit_cnt <= "000"; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then read_data <= "00000000"; else if (state = ALMOST_READY3) then read_data <= shift_through_reg(7 downto 0); end if; end if; end if; end process; ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0'; ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0'; BIT_CNT7 <= '1' when bit_cnt = "111" else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then AddressPhase <= '0'; else if (AddressPhase = '1') then -- Keep it set until we finish the cycle AddressPhase <= AddressPhase and (not ALMOST_READY2_ST); else -- set the address phase when ever we finish the address phase AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7); end if; end if; end if; end process; ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0'; DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then DRP_ADD_xilinx0 <= ADDR_PHASE_ST1; -- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE); DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST; MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg; if (state = READY) then DRP_BKST <= use_broadcast; end if; end if; end process; DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance '0'; DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance DRP_SDI_pre; process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7) begin addr_data_sel_n <= '0'; load_shift_n <= '0'; case state is when READY => load_shift_n <= '0'; if (cmd_valid = '1') then nextstate <= DECIDE; else nextstate <= READY; end if; when DECIDE => load_shift_n <= '1'; addr_data_sel_n <= '1'; nextstate <= ADDR_PHASE; -- After the second pass go to end of statemachine -- execute a second address phase for the alternative access method. when ADDR_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then if (('1' and rd_not_write_reg) = '1') then if (AddressPhase = '1') then nextstate <= ALMOST_READY; else nextstate <= DECIDE; end if; else nextstate <= ADDR_TO_DATA_GAP; end if; else nextstate <= ADDR_PHASE; end if; when ADDR_TO_DATA_GAP => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP2; when ADDR_TO_DATA_GAP2 => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP3; when ADDR_TO_DATA_GAP3 => load_shift_n <= '1'; nextstate <= DATA_PHASE; when DATA_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then nextstate <= ALMOST_READY; else nextstate <= DATA_PHASE; end if; when ALMOST_READY => load_shift_n <= '0'; nextstate <= ALMOST_READY2; when ALMOST_READY2 => load_shift_n <= '0'; nextstate <= ALMOST_READY3; when ALMOST_READY3 => load_shift_n <= '0'; nextstate <= READY; when others => load_shift_n <= '0'; nextstate <= READY; end case; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then state <= READY; else state <= nextstate; end if; end if; end process; end architecture trans;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: iodrp_mcb_controller.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for IODRP controller for v0.9 device -- --Reference: -- -- Revision: Date: Comment -- 1.0: 03/19/09: Initial version for IODRP_MCB read operations. -- 1.1: 04/03/09: SLH - Added left shift for certain IOI's -- 1.2: 02/14/11: Change FSM encoding from one-hot to gray to match Verilog version. -- End Revision --******************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity iodrp_mcb_controller is --output to IODRP SDI pin --input from IODRP SDO pin -- Register where memcell_address is captured during the READY state -- Register which stores the write data until it is ready to be shifted out -- The shift register which shifts out SDO and shifts in SDI. -- This register is loaded before the address or data phase, but continues to shift for a writeback of read data -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO -- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg -- The counter for which bit is being shifted during address or data phase -- This is set after the first address phase has executed -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg --added so that DRP_SDI output is only active when DRP_CS is active port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end entity iodrp_mcb_controller; architecture trans of iodrp_mcb_controller is type StType is ( READY, DECIDE , ADDR_PHASE , ADDR_TO_DATA_GAP , ADDR_TO_DATA_GAP2, ADDR_TO_DATA_GAP3, DATA_PHASE , ALMOST_READY , ALMOST_READY2 , ALMOST_READY3 ); constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001"; constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000"; constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011"; constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010"; constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101"; constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100"; constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111"; constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110"; constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001"; constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000"; constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011"; constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010"; constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101"; constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100"; constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111"; constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110"; constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101"; constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100"; constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111"; constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110"; signal memcell_addr_reg : std_logic_vector(7 downto 0); signal data_reg : std_logic_vector(7 downto 0); signal shift_through_reg : std_logic_vector(8 downto 0); signal load_shift_n : std_logic; signal addr_data_sel_n : std_logic; signal bit_cnt : std_logic_vector(2 downto 0); signal rd_not_write_reg : std_logic; signal AddressPhase : std_logic; signal DRP_CS_pre : std_logic; signal extra_cs : std_logic; signal state,nextstate : StType; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "gray"; attribute fsm_encoding of nextstate : signal is "gray"; signal data_out : std_logic_vector(8 downto 0); signal data_out_mux : std_logic_vector(8 downto 0); signal DRP_SDI_pre : std_logic; --synthesis translate_off signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0); -- case(state) --synthesis translate_on -- The changes below are to compensate for an issue with 1.0 silicon. -- It may still be necessary to add a clock cycle to the ADD and CS signals --`define DRP_v1_0_FIX // Uncomment out this line for synthesis procedure shift_n_expand( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(8 downto 0)) is variable data_out_xilinx2 : std_logic_vector(8 downto 0); begin if ((data_in(0)) = '1') then data_out_xilinx2(1 downto 0) := "11"; else data_out_xilinx2(1 downto 0) := "00"; end if; if (data_in(1 downto 0) = "10") then data_out_xilinx2(2 downto 1) := "11"; else data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1)); end if; if (data_in(2 downto 1) = "10") then data_out_xilinx2(3 downto 2) := "11"; else data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2)); end if; if (data_in(3 downto 2) = "10") then data_out_xilinx2(4 downto 3) := "11"; else data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3)); end if; if (data_in(4 downto 3) = "10") then data_out_xilinx2(5 downto 4) := "11"; else data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4)); end if; if (data_in(5 downto 4) = "10") then data_out_xilinx2(6 downto 5) := "11"; else data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5)); end if; if (data_in(6 downto 5) = "10") then data_out_xilinx2(7 downto 6) := "11"; else data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6)); end if; if (data_in(7 downto 6) = "10") then data_out_xilinx2(8 downto 7) := "11"; else data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7)); end if; end shift_n_expand; -- Declare intermediate signals for referenced outputs signal DRP_CS_xilinx1 : std_logic; signal DRP_ADD_xilinx0 : std_logic; signal ALMOST_READY2_ST : std_logic; signal ADDR_PHASE_ST : std_logic; signal BIT_CNT7 : std_logic; signal ADDR_PHASE_ST1 : std_logic; signal DATA_PHASE_ST : std_logic; begin -- Drive referenced outputs DRP_CS <= DRP_CS_xilinx1; DRP_ADD <= DRP_ADD_xilinx0; -- process (state) -- begin -- case state is -- when READY => -- state_ascii <= "READY"; -- when DECIDE => -- state_ascii <= "DECIDE"; -- when ADDR_PHASE => -- state_ascii <= "ADDR_PHASE"; -- when ADDR_TO_DATA_GAP => -- state_ascii <= "ADDR_TO_DATA_GAP"; -- when ADDR_TO_DATA_GAP2 => -- state_ascii <= "ADDR_TO_DATA_GAP2"; -- when ADDR_TO_DATA_GAP3 => -- state_ascii <= "ADDR_TO_DATA_GAP3"; -- when DATA_PHASE => -- state_ascii <= "DATA_PHASE"; -- when ALMOST_READY => -- state_ascii <= "ALMOST_READY"; -- when ALMOST_READY2 => -- state_ascii <= "ALMOST_READY2"; -- when ALMOST_READY3 => -- state_ascii <= "ALMOST_READY3"; -- when others => -- null; -- end case; -- end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (state = READY) then memcell_addr_reg <= memcell_address; data_reg <= write_data; rd_not_write_reg <= rd_not_write; end if; end if; end process; rdy_busy_n <= '1' when state = READY else '0'; process (drp_ioi_addr, data_out) begin case drp_ioi_addr is when IOI_DQ0 => data_out_mux <= data_out; when IOI_DQ1 => data_out_mux <= data_out; when IOI_DQ2 => data_out_mux <= data_out; when IOI_DQ3 => data_out_mux <= data_out; when IOI_DQ4 => data_out_mux <= data_out; when IOI_DQ5 => data_out_mux <= data_out; when IOI_DQ6 => data_out_mux <= data_out; when IOI_DQ7 => data_out_mux <= data_out; when IOI_DQ8 => data_out_mux <= data_out; when IOI_DQ9 => data_out_mux <= data_out; when IOI_DQ10 => data_out_mux <= data_out; when IOI_DQ11 => data_out_mux <= data_out; when IOI_DQ12 => data_out_mux <= data_out; when IOI_DQ13 => data_out_mux <= data_out; when IOI_DQ14 => data_out_mux <= data_out; when IOI_DQ15 => data_out_mux <= data_out; when IOI_UDQS_CLK => data_out_mux <= data_out; when IOI_UDQS_PIN => data_out_mux <= data_out; when IOI_LDQS_CLK => data_out_mux <= data_out; when IOI_LDQS_PIN => data_out_mux <= data_out; when others => data_out_mux <= data_out; end case; end process; data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else ('0' & data_reg); process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then shift_through_reg <= "000000000"; else if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first shift_through_reg <= data_out_mux; else shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1)); end if; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then bit_cnt <= bit_cnt + "001"; else bit_cnt <= "000"; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then read_data <= "00000000"; else if (state = ALMOST_READY3) then read_data <= shift_through_reg(7 downto 0); end if; end if; end if; end process; ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0'; ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0'; BIT_CNT7 <= '1' when bit_cnt = "111" else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then AddressPhase <= '0'; else if (AddressPhase = '1') then -- Keep it set until we finish the cycle AddressPhase <= AddressPhase and (not ALMOST_READY2_ST); else -- set the address phase when ever we finish the address phase AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7); end if; end if; end if; end process; ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0'; DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then DRP_ADD_xilinx0 <= ADDR_PHASE_ST1; -- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE); DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST; MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg; if (state = READY) then DRP_BKST <= use_broadcast; end if; end if; end process; DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance '0'; DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance DRP_SDI_pre; process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7) begin addr_data_sel_n <= '0'; load_shift_n <= '0'; case state is when READY => load_shift_n <= '0'; if (cmd_valid = '1') then nextstate <= DECIDE; else nextstate <= READY; end if; when DECIDE => load_shift_n <= '1'; addr_data_sel_n <= '1'; nextstate <= ADDR_PHASE; -- After the second pass go to end of statemachine -- execute a second address phase for the alternative access method. when ADDR_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then if (('1' and rd_not_write_reg) = '1') then if (AddressPhase = '1') then nextstate <= ALMOST_READY; else nextstate <= DECIDE; end if; else nextstate <= ADDR_TO_DATA_GAP; end if; else nextstate <= ADDR_PHASE; end if; when ADDR_TO_DATA_GAP => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP2; when ADDR_TO_DATA_GAP2 => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP3; when ADDR_TO_DATA_GAP3 => load_shift_n <= '1'; nextstate <= DATA_PHASE; when DATA_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then nextstate <= ALMOST_READY; else nextstate <= DATA_PHASE; end if; when ALMOST_READY => load_shift_n <= '0'; nextstate <= ALMOST_READY2; when ALMOST_READY2 => load_shift_n <= '0'; nextstate <= ALMOST_READY3; when ALMOST_READY3 => load_shift_n <= '0'; nextstate <= READY; when others => load_shift_n <= '0'; nextstate <= READY; end case; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then state <= READY; else state <= nextstate; end if; end if; end process; end architecture trans;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: iodrp_mcb_controller.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for IODRP controller for v0.9 device -- --Reference: -- -- Revision: Date: Comment -- 1.0: 03/19/09: Initial version for IODRP_MCB read operations. -- 1.1: 04/03/09: SLH - Added left shift for certain IOI's -- 1.2: 02/14/11: Change FSM encoding from one-hot to gray to match Verilog version. -- End Revision --******************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity iodrp_mcb_controller is --output to IODRP SDI pin --input from IODRP SDO pin -- Register where memcell_address is captured during the READY state -- Register which stores the write data until it is ready to be shifted out -- The shift register which shifts out SDO and shifts in SDI. -- This register is loaded before the address or data phase, but continues to shift for a writeback of read data -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO -- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg -- The counter for which bit is being shifted during address or data phase -- This is set after the first address phase has executed -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg --added so that DRP_SDI output is only active when DRP_CS is active port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end entity iodrp_mcb_controller; architecture trans of iodrp_mcb_controller is type StType is ( READY, DECIDE , ADDR_PHASE , ADDR_TO_DATA_GAP , ADDR_TO_DATA_GAP2, ADDR_TO_DATA_GAP3, DATA_PHASE , ALMOST_READY , ALMOST_READY2 , ALMOST_READY3 ); constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001"; constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000"; constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011"; constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010"; constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101"; constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100"; constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111"; constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110"; constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001"; constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000"; constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011"; constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010"; constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101"; constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100"; constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111"; constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110"; constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101"; constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100"; constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111"; constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110"; signal memcell_addr_reg : std_logic_vector(7 downto 0); signal data_reg : std_logic_vector(7 downto 0); signal shift_through_reg : std_logic_vector(8 downto 0); signal load_shift_n : std_logic; signal addr_data_sel_n : std_logic; signal bit_cnt : std_logic_vector(2 downto 0); signal rd_not_write_reg : std_logic; signal AddressPhase : std_logic; signal DRP_CS_pre : std_logic; signal extra_cs : std_logic; signal state,nextstate : StType; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "gray"; attribute fsm_encoding of nextstate : signal is "gray"; signal data_out : std_logic_vector(8 downto 0); signal data_out_mux : std_logic_vector(8 downto 0); signal DRP_SDI_pre : std_logic; --synthesis translate_off signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0); -- case(state) --synthesis translate_on -- The changes below are to compensate for an issue with 1.0 silicon. -- It may still be necessary to add a clock cycle to the ADD and CS signals --`define DRP_v1_0_FIX // Uncomment out this line for synthesis procedure shift_n_expand( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(8 downto 0)) is variable data_out_xilinx2 : std_logic_vector(8 downto 0); begin if ((data_in(0)) = '1') then data_out_xilinx2(1 downto 0) := "11"; else data_out_xilinx2(1 downto 0) := "00"; end if; if (data_in(1 downto 0) = "10") then data_out_xilinx2(2 downto 1) := "11"; else data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1)); end if; if (data_in(2 downto 1) = "10") then data_out_xilinx2(3 downto 2) := "11"; else data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2)); end if; if (data_in(3 downto 2) = "10") then data_out_xilinx2(4 downto 3) := "11"; else data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3)); end if; if (data_in(4 downto 3) = "10") then data_out_xilinx2(5 downto 4) := "11"; else data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4)); end if; if (data_in(5 downto 4) = "10") then data_out_xilinx2(6 downto 5) := "11"; else data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5)); end if; if (data_in(6 downto 5) = "10") then data_out_xilinx2(7 downto 6) := "11"; else data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6)); end if; if (data_in(7 downto 6) = "10") then data_out_xilinx2(8 downto 7) := "11"; else data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7)); end if; end shift_n_expand; -- Declare intermediate signals for referenced outputs signal DRP_CS_xilinx1 : std_logic; signal DRP_ADD_xilinx0 : std_logic; signal ALMOST_READY2_ST : std_logic; signal ADDR_PHASE_ST : std_logic; signal BIT_CNT7 : std_logic; signal ADDR_PHASE_ST1 : std_logic; signal DATA_PHASE_ST : std_logic; begin -- Drive referenced outputs DRP_CS <= DRP_CS_xilinx1; DRP_ADD <= DRP_ADD_xilinx0; -- process (state) -- begin -- case state is -- when READY => -- state_ascii <= "READY"; -- when DECIDE => -- state_ascii <= "DECIDE"; -- when ADDR_PHASE => -- state_ascii <= "ADDR_PHASE"; -- when ADDR_TO_DATA_GAP => -- state_ascii <= "ADDR_TO_DATA_GAP"; -- when ADDR_TO_DATA_GAP2 => -- state_ascii <= "ADDR_TO_DATA_GAP2"; -- when ADDR_TO_DATA_GAP3 => -- state_ascii <= "ADDR_TO_DATA_GAP3"; -- when DATA_PHASE => -- state_ascii <= "DATA_PHASE"; -- when ALMOST_READY => -- state_ascii <= "ALMOST_READY"; -- when ALMOST_READY2 => -- state_ascii <= "ALMOST_READY2"; -- when ALMOST_READY3 => -- state_ascii <= "ALMOST_READY3"; -- when others => -- null; -- end case; -- end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (state = READY) then memcell_addr_reg <= memcell_address; data_reg <= write_data; rd_not_write_reg <= rd_not_write; end if; end if; end process; rdy_busy_n <= '1' when state = READY else '0'; process (drp_ioi_addr, data_out) begin case drp_ioi_addr is when IOI_DQ0 => data_out_mux <= data_out; when IOI_DQ1 => data_out_mux <= data_out; when IOI_DQ2 => data_out_mux <= data_out; when IOI_DQ3 => data_out_mux <= data_out; when IOI_DQ4 => data_out_mux <= data_out; when IOI_DQ5 => data_out_mux <= data_out; when IOI_DQ6 => data_out_mux <= data_out; when IOI_DQ7 => data_out_mux <= data_out; when IOI_DQ8 => data_out_mux <= data_out; when IOI_DQ9 => data_out_mux <= data_out; when IOI_DQ10 => data_out_mux <= data_out; when IOI_DQ11 => data_out_mux <= data_out; when IOI_DQ12 => data_out_mux <= data_out; when IOI_DQ13 => data_out_mux <= data_out; when IOI_DQ14 => data_out_mux <= data_out; when IOI_DQ15 => data_out_mux <= data_out; when IOI_UDQS_CLK => data_out_mux <= data_out; when IOI_UDQS_PIN => data_out_mux <= data_out; when IOI_LDQS_CLK => data_out_mux <= data_out; when IOI_LDQS_PIN => data_out_mux <= data_out; when others => data_out_mux <= data_out; end case; end process; data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else ('0' & data_reg); process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then shift_through_reg <= "000000000"; else if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first shift_through_reg <= data_out_mux; else shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1)); end if; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then bit_cnt <= bit_cnt + "001"; else bit_cnt <= "000"; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then read_data <= "00000000"; else if (state = ALMOST_READY3) then read_data <= shift_through_reg(7 downto 0); end if; end if; end if; end process; ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0'; ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0'; BIT_CNT7 <= '1' when bit_cnt = "111" else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then AddressPhase <= '0'; else if (AddressPhase = '1') then -- Keep it set until we finish the cycle AddressPhase <= AddressPhase and (not ALMOST_READY2_ST); else -- set the address phase when ever we finish the address phase AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7); end if; end if; end if; end process; ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0'; DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then DRP_ADD_xilinx0 <= ADDR_PHASE_ST1; -- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE); DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST; MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg; if (state = READY) then DRP_BKST <= use_broadcast; end if; end if; end process; DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance '0'; DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance DRP_SDI_pre; process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7) begin addr_data_sel_n <= '0'; load_shift_n <= '0'; case state is when READY => load_shift_n <= '0'; if (cmd_valid = '1') then nextstate <= DECIDE; else nextstate <= READY; end if; when DECIDE => load_shift_n <= '1'; addr_data_sel_n <= '1'; nextstate <= ADDR_PHASE; -- After the second pass go to end of statemachine -- execute a second address phase for the alternative access method. when ADDR_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then if (('1' and rd_not_write_reg) = '1') then if (AddressPhase = '1') then nextstate <= ALMOST_READY; else nextstate <= DECIDE; end if; else nextstate <= ADDR_TO_DATA_GAP; end if; else nextstate <= ADDR_PHASE; end if; when ADDR_TO_DATA_GAP => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP2; when ADDR_TO_DATA_GAP2 => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP3; when ADDR_TO_DATA_GAP3 => load_shift_n <= '1'; nextstate <= DATA_PHASE; when DATA_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then nextstate <= ALMOST_READY; else nextstate <= DATA_PHASE; end if; when ALMOST_READY => load_shift_n <= '0'; nextstate <= ALMOST_READY2; when ALMOST_READY2 => load_shift_n <= '0'; nextstate <= ALMOST_READY3; when ALMOST_READY3 => load_shift_n <= '0'; nextstate <= READY; when others => load_shift_n <= '0'; nextstate <= READY; end case; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then state <= READY; else state <= nextstate; end if; end if; end process; end architecture trans;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: iodrp_mcb_controller.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for IODRP controller for v0.9 device -- --Reference: -- -- Revision: Date: Comment -- 1.0: 03/19/09: Initial version for IODRP_MCB read operations. -- 1.1: 04/03/09: SLH - Added left shift for certain IOI's -- 1.2: 02/14/11: Change FSM encoding from one-hot to gray to match Verilog version. -- End Revision --******************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity iodrp_mcb_controller is --output to IODRP SDI pin --input from IODRP SDO pin -- Register where memcell_address is captured during the READY state -- Register which stores the write data until it is ready to be shifted out -- The shift register which shifts out SDO and shifts in SDI. -- This register is loaded before the address or data phase, but continues to shift for a writeback of read data -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO -- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg -- The counter for which bit is being shifted during address or data phase -- This is set after the first address phase has executed -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg --added so that DRP_SDI output is only active when DRP_CS is active port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end entity iodrp_mcb_controller; architecture trans of iodrp_mcb_controller is type StType is ( READY, DECIDE , ADDR_PHASE , ADDR_TO_DATA_GAP , ADDR_TO_DATA_GAP2, ADDR_TO_DATA_GAP3, DATA_PHASE , ALMOST_READY , ALMOST_READY2 , ALMOST_READY3 ); constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001"; constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000"; constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011"; constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010"; constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101"; constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100"; constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111"; constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110"; constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001"; constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000"; constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011"; constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010"; constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101"; constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100"; constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111"; constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110"; constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101"; constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100"; constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111"; constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110"; signal memcell_addr_reg : std_logic_vector(7 downto 0); signal data_reg : std_logic_vector(7 downto 0); signal shift_through_reg : std_logic_vector(8 downto 0); signal load_shift_n : std_logic; signal addr_data_sel_n : std_logic; signal bit_cnt : std_logic_vector(2 downto 0); signal rd_not_write_reg : std_logic; signal AddressPhase : std_logic; signal DRP_CS_pre : std_logic; signal extra_cs : std_logic; signal state,nextstate : StType; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "gray"; attribute fsm_encoding of nextstate : signal is "gray"; signal data_out : std_logic_vector(8 downto 0); signal data_out_mux : std_logic_vector(8 downto 0); signal DRP_SDI_pre : std_logic; --synthesis translate_off signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0); -- case(state) --synthesis translate_on -- The changes below are to compensate for an issue with 1.0 silicon. -- It may still be necessary to add a clock cycle to the ADD and CS signals --`define DRP_v1_0_FIX // Uncomment out this line for synthesis procedure shift_n_expand( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(8 downto 0)) is variable data_out_xilinx2 : std_logic_vector(8 downto 0); begin if ((data_in(0)) = '1') then data_out_xilinx2(1 downto 0) := "11"; else data_out_xilinx2(1 downto 0) := "00"; end if; if (data_in(1 downto 0) = "10") then data_out_xilinx2(2 downto 1) := "11"; else data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1)); end if; if (data_in(2 downto 1) = "10") then data_out_xilinx2(3 downto 2) := "11"; else data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2)); end if; if (data_in(3 downto 2) = "10") then data_out_xilinx2(4 downto 3) := "11"; else data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3)); end if; if (data_in(4 downto 3) = "10") then data_out_xilinx2(5 downto 4) := "11"; else data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4)); end if; if (data_in(5 downto 4) = "10") then data_out_xilinx2(6 downto 5) := "11"; else data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5)); end if; if (data_in(6 downto 5) = "10") then data_out_xilinx2(7 downto 6) := "11"; else data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6)); end if; if (data_in(7 downto 6) = "10") then data_out_xilinx2(8 downto 7) := "11"; else data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7)); end if; end shift_n_expand; -- Declare intermediate signals for referenced outputs signal DRP_CS_xilinx1 : std_logic; signal DRP_ADD_xilinx0 : std_logic; signal ALMOST_READY2_ST : std_logic; signal ADDR_PHASE_ST : std_logic; signal BIT_CNT7 : std_logic; signal ADDR_PHASE_ST1 : std_logic; signal DATA_PHASE_ST : std_logic; begin -- Drive referenced outputs DRP_CS <= DRP_CS_xilinx1; DRP_ADD <= DRP_ADD_xilinx0; -- process (state) -- begin -- case state is -- when READY => -- state_ascii <= "READY"; -- when DECIDE => -- state_ascii <= "DECIDE"; -- when ADDR_PHASE => -- state_ascii <= "ADDR_PHASE"; -- when ADDR_TO_DATA_GAP => -- state_ascii <= "ADDR_TO_DATA_GAP"; -- when ADDR_TO_DATA_GAP2 => -- state_ascii <= "ADDR_TO_DATA_GAP2"; -- when ADDR_TO_DATA_GAP3 => -- state_ascii <= "ADDR_TO_DATA_GAP3"; -- when DATA_PHASE => -- state_ascii <= "DATA_PHASE"; -- when ALMOST_READY => -- state_ascii <= "ALMOST_READY"; -- when ALMOST_READY2 => -- state_ascii <= "ALMOST_READY2"; -- when ALMOST_READY3 => -- state_ascii <= "ALMOST_READY3"; -- when others => -- null; -- end case; -- end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (state = READY) then memcell_addr_reg <= memcell_address; data_reg <= write_data; rd_not_write_reg <= rd_not_write; end if; end if; end process; rdy_busy_n <= '1' when state = READY else '0'; process (drp_ioi_addr, data_out) begin case drp_ioi_addr is when IOI_DQ0 => data_out_mux <= data_out; when IOI_DQ1 => data_out_mux <= data_out; when IOI_DQ2 => data_out_mux <= data_out; when IOI_DQ3 => data_out_mux <= data_out; when IOI_DQ4 => data_out_mux <= data_out; when IOI_DQ5 => data_out_mux <= data_out; when IOI_DQ6 => data_out_mux <= data_out; when IOI_DQ7 => data_out_mux <= data_out; when IOI_DQ8 => data_out_mux <= data_out; when IOI_DQ9 => data_out_mux <= data_out; when IOI_DQ10 => data_out_mux <= data_out; when IOI_DQ11 => data_out_mux <= data_out; when IOI_DQ12 => data_out_mux <= data_out; when IOI_DQ13 => data_out_mux <= data_out; when IOI_DQ14 => data_out_mux <= data_out; when IOI_DQ15 => data_out_mux <= data_out; when IOI_UDQS_CLK => data_out_mux <= data_out; when IOI_UDQS_PIN => data_out_mux <= data_out; when IOI_LDQS_CLK => data_out_mux <= data_out; when IOI_LDQS_PIN => data_out_mux <= data_out; when others => data_out_mux <= data_out; end case; end process; data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else ('0' & data_reg); process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then shift_through_reg <= "000000000"; else if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first shift_through_reg <= data_out_mux; else shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1)); end if; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then bit_cnt <= bit_cnt + "001"; else bit_cnt <= "000"; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then read_data <= "00000000"; else if (state = ALMOST_READY3) then read_data <= shift_through_reg(7 downto 0); end if; end if; end if; end process; ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0'; ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0'; BIT_CNT7 <= '1' when bit_cnt = "111" else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then AddressPhase <= '0'; else if (AddressPhase = '1') then -- Keep it set until we finish the cycle AddressPhase <= AddressPhase and (not ALMOST_READY2_ST); else -- set the address phase when ever we finish the address phase AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7); end if; end if; end if; end process; ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0'; DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then DRP_ADD_xilinx0 <= ADDR_PHASE_ST1; -- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE); DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST; MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg; if (state = READY) then DRP_BKST <= use_broadcast; end if; end if; end process; DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance '0'; DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance DRP_SDI_pre; process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7) begin addr_data_sel_n <= '0'; load_shift_n <= '0'; case state is when READY => load_shift_n <= '0'; if (cmd_valid = '1') then nextstate <= DECIDE; else nextstate <= READY; end if; when DECIDE => load_shift_n <= '1'; addr_data_sel_n <= '1'; nextstate <= ADDR_PHASE; -- After the second pass go to end of statemachine -- execute a second address phase for the alternative access method. when ADDR_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then if (('1' and rd_not_write_reg) = '1') then if (AddressPhase = '1') then nextstate <= ALMOST_READY; else nextstate <= DECIDE; end if; else nextstate <= ADDR_TO_DATA_GAP; end if; else nextstate <= ADDR_PHASE; end if; when ADDR_TO_DATA_GAP => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP2; when ADDR_TO_DATA_GAP2 => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP3; when ADDR_TO_DATA_GAP3 => load_shift_n <= '1'; nextstate <= DATA_PHASE; when DATA_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then nextstate <= ALMOST_READY; else nextstate <= DATA_PHASE; end if; when ALMOST_READY => load_shift_n <= '0'; nextstate <= ALMOST_READY2; when ALMOST_READY2 => load_shift_n <= '0'; nextstate <= ALMOST_READY3; when ALMOST_READY3 => load_shift_n <= '0'; nextstate <= READY; when others => load_shift_n <= '0'; nextstate <= READY; end case; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then state <= READY; else state <= nextstate; end if; end if; end process; end architecture trans;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: iodrp_mcb_controller.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for IODRP controller for v0.9 device -- --Reference: -- -- Revision: Date: Comment -- 1.0: 03/19/09: Initial version for IODRP_MCB read operations. -- 1.1: 04/03/09: SLH - Added left shift for certain IOI's -- 1.2: 02/14/11: Change FSM encoding from one-hot to gray to match Verilog version. -- End Revision --******************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity iodrp_mcb_controller is --output to IODRP SDI pin --input from IODRP SDO pin -- Register where memcell_address is captured during the READY state -- Register which stores the write data until it is ready to be shifted out -- The shift register which shifts out SDO and shifts in SDI. -- This register is loaded before the address or data phase, but continues to shift for a writeback of read data -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO -- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg -- The counter for which bit is being shifted during address or data phase -- This is set after the first address phase has executed -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg --added so that DRP_SDI output is only active when DRP_CS is active port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end entity iodrp_mcb_controller; architecture trans of iodrp_mcb_controller is type StType is ( READY, DECIDE , ADDR_PHASE , ADDR_TO_DATA_GAP , ADDR_TO_DATA_GAP2, ADDR_TO_DATA_GAP3, DATA_PHASE , ALMOST_READY , ALMOST_READY2 , ALMOST_READY3 ); constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001"; constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000"; constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011"; constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010"; constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101"; constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100"; constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111"; constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110"; constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001"; constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000"; constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011"; constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010"; constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101"; constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100"; constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111"; constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110"; constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101"; constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100"; constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111"; constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110"; signal memcell_addr_reg : std_logic_vector(7 downto 0); signal data_reg : std_logic_vector(7 downto 0); signal shift_through_reg : std_logic_vector(8 downto 0); signal load_shift_n : std_logic; signal addr_data_sel_n : std_logic; signal bit_cnt : std_logic_vector(2 downto 0); signal rd_not_write_reg : std_logic; signal AddressPhase : std_logic; signal DRP_CS_pre : std_logic; signal extra_cs : std_logic; signal state,nextstate : StType; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "gray"; attribute fsm_encoding of nextstate : signal is "gray"; signal data_out : std_logic_vector(8 downto 0); signal data_out_mux : std_logic_vector(8 downto 0); signal DRP_SDI_pre : std_logic; --synthesis translate_off signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0); -- case(state) --synthesis translate_on -- The changes below are to compensate for an issue with 1.0 silicon. -- It may still be necessary to add a clock cycle to the ADD and CS signals --`define DRP_v1_0_FIX // Uncomment out this line for synthesis procedure shift_n_expand( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(8 downto 0)) is variable data_out_xilinx2 : std_logic_vector(8 downto 0); begin if ((data_in(0)) = '1') then data_out_xilinx2(1 downto 0) := "11"; else data_out_xilinx2(1 downto 0) := "00"; end if; if (data_in(1 downto 0) = "10") then data_out_xilinx2(2 downto 1) := "11"; else data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1)); end if; if (data_in(2 downto 1) = "10") then data_out_xilinx2(3 downto 2) := "11"; else data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2)); end if; if (data_in(3 downto 2) = "10") then data_out_xilinx2(4 downto 3) := "11"; else data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3)); end if; if (data_in(4 downto 3) = "10") then data_out_xilinx2(5 downto 4) := "11"; else data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4)); end if; if (data_in(5 downto 4) = "10") then data_out_xilinx2(6 downto 5) := "11"; else data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5)); end if; if (data_in(6 downto 5) = "10") then data_out_xilinx2(7 downto 6) := "11"; else data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6)); end if; if (data_in(7 downto 6) = "10") then data_out_xilinx2(8 downto 7) := "11"; else data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7)); end if; end shift_n_expand; -- Declare intermediate signals for referenced outputs signal DRP_CS_xilinx1 : std_logic; signal DRP_ADD_xilinx0 : std_logic; signal ALMOST_READY2_ST : std_logic; signal ADDR_PHASE_ST : std_logic; signal BIT_CNT7 : std_logic; signal ADDR_PHASE_ST1 : std_logic; signal DATA_PHASE_ST : std_logic; begin -- Drive referenced outputs DRP_CS <= DRP_CS_xilinx1; DRP_ADD <= DRP_ADD_xilinx0; -- process (state) -- begin -- case state is -- when READY => -- state_ascii <= "READY"; -- when DECIDE => -- state_ascii <= "DECIDE"; -- when ADDR_PHASE => -- state_ascii <= "ADDR_PHASE"; -- when ADDR_TO_DATA_GAP => -- state_ascii <= "ADDR_TO_DATA_GAP"; -- when ADDR_TO_DATA_GAP2 => -- state_ascii <= "ADDR_TO_DATA_GAP2"; -- when ADDR_TO_DATA_GAP3 => -- state_ascii <= "ADDR_TO_DATA_GAP3"; -- when DATA_PHASE => -- state_ascii <= "DATA_PHASE"; -- when ALMOST_READY => -- state_ascii <= "ALMOST_READY"; -- when ALMOST_READY2 => -- state_ascii <= "ALMOST_READY2"; -- when ALMOST_READY3 => -- state_ascii <= "ALMOST_READY3"; -- when others => -- null; -- end case; -- end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (state = READY) then memcell_addr_reg <= memcell_address; data_reg <= write_data; rd_not_write_reg <= rd_not_write; end if; end if; end process; rdy_busy_n <= '1' when state = READY else '0'; process (drp_ioi_addr, data_out) begin case drp_ioi_addr is when IOI_DQ0 => data_out_mux <= data_out; when IOI_DQ1 => data_out_mux <= data_out; when IOI_DQ2 => data_out_mux <= data_out; when IOI_DQ3 => data_out_mux <= data_out; when IOI_DQ4 => data_out_mux <= data_out; when IOI_DQ5 => data_out_mux <= data_out; when IOI_DQ6 => data_out_mux <= data_out; when IOI_DQ7 => data_out_mux <= data_out; when IOI_DQ8 => data_out_mux <= data_out; when IOI_DQ9 => data_out_mux <= data_out; when IOI_DQ10 => data_out_mux <= data_out; when IOI_DQ11 => data_out_mux <= data_out; when IOI_DQ12 => data_out_mux <= data_out; when IOI_DQ13 => data_out_mux <= data_out; when IOI_DQ14 => data_out_mux <= data_out; when IOI_DQ15 => data_out_mux <= data_out; when IOI_UDQS_CLK => data_out_mux <= data_out; when IOI_UDQS_PIN => data_out_mux <= data_out; when IOI_LDQS_CLK => data_out_mux <= data_out; when IOI_LDQS_PIN => data_out_mux <= data_out; when others => data_out_mux <= data_out; end case; end process; data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else ('0' & data_reg); process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then shift_through_reg <= "000000000"; else if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first shift_through_reg <= data_out_mux; else shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1)); end if; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then bit_cnt <= bit_cnt + "001"; else bit_cnt <= "000"; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then read_data <= "00000000"; else if (state = ALMOST_READY3) then read_data <= shift_through_reg(7 downto 0); end if; end if; end if; end process; ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0'; ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0'; BIT_CNT7 <= '1' when bit_cnt = "111" else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then AddressPhase <= '0'; else if (AddressPhase = '1') then -- Keep it set until we finish the cycle AddressPhase <= AddressPhase and (not ALMOST_READY2_ST); else -- set the address phase when ever we finish the address phase AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7); end if; end if; end if; end process; ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0'; DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then DRP_ADD_xilinx0 <= ADDR_PHASE_ST1; -- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE); DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST; MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg; if (state = READY) then DRP_BKST <= use_broadcast; end if; end if; end process; DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance '0'; DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance DRP_SDI_pre; process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7) begin addr_data_sel_n <= '0'; load_shift_n <= '0'; case state is when READY => load_shift_n <= '0'; if (cmd_valid = '1') then nextstate <= DECIDE; else nextstate <= READY; end if; when DECIDE => load_shift_n <= '1'; addr_data_sel_n <= '1'; nextstate <= ADDR_PHASE; -- After the second pass go to end of statemachine -- execute a second address phase for the alternative access method. when ADDR_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then if (('1' and rd_not_write_reg) = '1') then if (AddressPhase = '1') then nextstate <= ALMOST_READY; else nextstate <= DECIDE; end if; else nextstate <= ADDR_TO_DATA_GAP; end if; else nextstate <= ADDR_PHASE; end if; when ADDR_TO_DATA_GAP => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP2; when ADDR_TO_DATA_GAP2 => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP3; when ADDR_TO_DATA_GAP3 => load_shift_n <= '1'; nextstate <= DATA_PHASE; when DATA_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then nextstate <= ALMOST_READY; else nextstate <= DATA_PHASE; end if; when ALMOST_READY => load_shift_n <= '0'; nextstate <= ALMOST_READY2; when ALMOST_READY2 => load_shift_n <= '0'; nextstate <= ALMOST_READY3; when ALMOST_READY3 => load_shift_n <= '0'; nextstate <= READY; when others => load_shift_n <= '0'; nextstate <= READY; end case; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then state <= READY; else state <= nextstate; end if; end if; end process; end architecture trans;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: iodrp_mcb_controller.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for IODRP controller for v0.9 device -- --Reference: -- -- Revision: Date: Comment -- 1.0: 03/19/09: Initial version for IODRP_MCB read operations. -- 1.1: 04/03/09: SLH - Added left shift for certain IOI's -- 1.2: 02/14/11: Change FSM encoding from one-hot to gray to match Verilog version. -- End Revision --******************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity iodrp_mcb_controller is --output to IODRP SDI pin --input from IODRP SDO pin -- Register where memcell_address is captured during the READY state -- Register which stores the write data until it is ready to be shifted out -- The shift register which shifts out SDO and shifts in SDI. -- This register is loaded before the address or data phase, but continues to shift for a writeback of read data -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO -- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg -- The counter for which bit is being shifted during address or data phase -- This is set after the first address phase has executed -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg --added so that DRP_SDI output is only active when DRP_CS is active port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end entity iodrp_mcb_controller; architecture trans of iodrp_mcb_controller is type StType is ( READY, DECIDE , ADDR_PHASE , ADDR_TO_DATA_GAP , ADDR_TO_DATA_GAP2, ADDR_TO_DATA_GAP3, DATA_PHASE , ALMOST_READY , ALMOST_READY2 , ALMOST_READY3 ); constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001"; constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000"; constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011"; constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010"; constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101"; constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100"; constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111"; constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110"; constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001"; constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000"; constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011"; constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010"; constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101"; constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100"; constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111"; constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110"; constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101"; constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100"; constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111"; constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110"; signal memcell_addr_reg : std_logic_vector(7 downto 0); signal data_reg : std_logic_vector(7 downto 0); signal shift_through_reg : std_logic_vector(8 downto 0); signal load_shift_n : std_logic; signal addr_data_sel_n : std_logic; signal bit_cnt : std_logic_vector(2 downto 0); signal rd_not_write_reg : std_logic; signal AddressPhase : std_logic; signal DRP_CS_pre : std_logic; signal extra_cs : std_logic; signal state,nextstate : StType; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "gray"; attribute fsm_encoding of nextstate : signal is "gray"; signal data_out : std_logic_vector(8 downto 0); signal data_out_mux : std_logic_vector(8 downto 0); signal DRP_SDI_pre : std_logic; --synthesis translate_off signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0); -- case(state) --synthesis translate_on -- The changes below are to compensate for an issue with 1.0 silicon. -- It may still be necessary to add a clock cycle to the ADD and CS signals --`define DRP_v1_0_FIX // Uncomment out this line for synthesis procedure shift_n_expand( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(8 downto 0)) is variable data_out_xilinx2 : std_logic_vector(8 downto 0); begin if ((data_in(0)) = '1') then data_out_xilinx2(1 downto 0) := "11"; else data_out_xilinx2(1 downto 0) := "00"; end if; if (data_in(1 downto 0) = "10") then data_out_xilinx2(2 downto 1) := "11"; else data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1)); end if; if (data_in(2 downto 1) = "10") then data_out_xilinx2(3 downto 2) := "11"; else data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2)); end if; if (data_in(3 downto 2) = "10") then data_out_xilinx2(4 downto 3) := "11"; else data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3)); end if; if (data_in(4 downto 3) = "10") then data_out_xilinx2(5 downto 4) := "11"; else data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4)); end if; if (data_in(5 downto 4) = "10") then data_out_xilinx2(6 downto 5) := "11"; else data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5)); end if; if (data_in(6 downto 5) = "10") then data_out_xilinx2(7 downto 6) := "11"; else data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6)); end if; if (data_in(7 downto 6) = "10") then data_out_xilinx2(8 downto 7) := "11"; else data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7)); end if; end shift_n_expand; -- Declare intermediate signals for referenced outputs signal DRP_CS_xilinx1 : std_logic; signal DRP_ADD_xilinx0 : std_logic; signal ALMOST_READY2_ST : std_logic; signal ADDR_PHASE_ST : std_logic; signal BIT_CNT7 : std_logic; signal ADDR_PHASE_ST1 : std_logic; signal DATA_PHASE_ST : std_logic; begin -- Drive referenced outputs DRP_CS <= DRP_CS_xilinx1; DRP_ADD <= DRP_ADD_xilinx0; -- process (state) -- begin -- case state is -- when READY => -- state_ascii <= "READY"; -- when DECIDE => -- state_ascii <= "DECIDE"; -- when ADDR_PHASE => -- state_ascii <= "ADDR_PHASE"; -- when ADDR_TO_DATA_GAP => -- state_ascii <= "ADDR_TO_DATA_GAP"; -- when ADDR_TO_DATA_GAP2 => -- state_ascii <= "ADDR_TO_DATA_GAP2"; -- when ADDR_TO_DATA_GAP3 => -- state_ascii <= "ADDR_TO_DATA_GAP3"; -- when DATA_PHASE => -- state_ascii <= "DATA_PHASE"; -- when ALMOST_READY => -- state_ascii <= "ALMOST_READY"; -- when ALMOST_READY2 => -- state_ascii <= "ALMOST_READY2"; -- when ALMOST_READY3 => -- state_ascii <= "ALMOST_READY3"; -- when others => -- null; -- end case; -- end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (state = READY) then memcell_addr_reg <= memcell_address; data_reg <= write_data; rd_not_write_reg <= rd_not_write; end if; end if; end process; rdy_busy_n <= '1' when state = READY else '0'; process (drp_ioi_addr, data_out) begin case drp_ioi_addr is when IOI_DQ0 => data_out_mux <= data_out; when IOI_DQ1 => data_out_mux <= data_out; when IOI_DQ2 => data_out_mux <= data_out; when IOI_DQ3 => data_out_mux <= data_out; when IOI_DQ4 => data_out_mux <= data_out; when IOI_DQ5 => data_out_mux <= data_out; when IOI_DQ6 => data_out_mux <= data_out; when IOI_DQ7 => data_out_mux <= data_out; when IOI_DQ8 => data_out_mux <= data_out; when IOI_DQ9 => data_out_mux <= data_out; when IOI_DQ10 => data_out_mux <= data_out; when IOI_DQ11 => data_out_mux <= data_out; when IOI_DQ12 => data_out_mux <= data_out; when IOI_DQ13 => data_out_mux <= data_out; when IOI_DQ14 => data_out_mux <= data_out; when IOI_DQ15 => data_out_mux <= data_out; when IOI_UDQS_CLK => data_out_mux <= data_out; when IOI_UDQS_PIN => data_out_mux <= data_out; when IOI_LDQS_CLK => data_out_mux <= data_out; when IOI_LDQS_PIN => data_out_mux <= data_out; when others => data_out_mux <= data_out; end case; end process; data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else ('0' & data_reg); process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then shift_through_reg <= "000000000"; else if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first shift_through_reg <= data_out_mux; else shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1)); end if; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then bit_cnt <= bit_cnt + "001"; else bit_cnt <= "000"; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then read_data <= "00000000"; else if (state = ALMOST_READY3) then read_data <= shift_through_reg(7 downto 0); end if; end if; end if; end process; ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0'; ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0'; BIT_CNT7 <= '1' when bit_cnt = "111" else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then AddressPhase <= '0'; else if (AddressPhase = '1') then -- Keep it set until we finish the cycle AddressPhase <= AddressPhase and (not ALMOST_READY2_ST); else -- set the address phase when ever we finish the address phase AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7); end if; end if; end if; end process; ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0'; DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then DRP_ADD_xilinx0 <= ADDR_PHASE_ST1; -- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE); DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST; MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg; if (state = READY) then DRP_BKST <= use_broadcast; end if; end if; end process; DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance '0'; DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance DRP_SDI_pre; process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7) begin addr_data_sel_n <= '0'; load_shift_n <= '0'; case state is when READY => load_shift_n <= '0'; if (cmd_valid = '1') then nextstate <= DECIDE; else nextstate <= READY; end if; when DECIDE => load_shift_n <= '1'; addr_data_sel_n <= '1'; nextstate <= ADDR_PHASE; -- After the second pass go to end of statemachine -- execute a second address phase for the alternative access method. when ADDR_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then if (('1' and rd_not_write_reg) = '1') then if (AddressPhase = '1') then nextstate <= ALMOST_READY; else nextstate <= DECIDE; end if; else nextstate <= ADDR_TO_DATA_GAP; end if; else nextstate <= ADDR_PHASE; end if; when ADDR_TO_DATA_GAP => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP2; when ADDR_TO_DATA_GAP2 => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP3; when ADDR_TO_DATA_GAP3 => load_shift_n <= '1'; nextstate <= DATA_PHASE; when DATA_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then nextstate <= ALMOST_READY; else nextstate <= DATA_PHASE; end if; when ALMOST_READY => load_shift_n <= '0'; nextstate <= ALMOST_READY2; when ALMOST_READY2 => load_shift_n <= '0'; nextstate <= ALMOST_READY3; when ALMOST_READY3 => load_shift_n <= '0'; nextstate <= READY; when others => load_shift_n <= '0'; nextstate <= READY; end case; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then state <= READY; else state <= nextstate; end if; end if; end process; end architecture trans;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: iodrp_mcb_controller.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for IODRP controller for v0.9 device -- --Reference: -- -- Revision: Date: Comment -- 1.0: 03/19/09: Initial version for IODRP_MCB read operations. -- 1.1: 04/03/09: SLH - Added left shift for certain IOI's -- 1.2: 02/14/11: Change FSM encoding from one-hot to gray to match Verilog version. -- End Revision --******************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity iodrp_mcb_controller is --output to IODRP SDI pin --input from IODRP SDO pin -- Register where memcell_address is captured during the READY state -- Register which stores the write data until it is ready to be shifted out -- The shift register which shifts out SDO and shifts in SDI. -- This register is loaded before the address or data phase, but continues to shift for a writeback of read data -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO -- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg -- The counter for which bit is being shifted during address or data phase -- This is set after the first address phase has executed -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg --added so that DRP_SDI output is only active when DRP_CS is active port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end entity iodrp_mcb_controller; architecture trans of iodrp_mcb_controller is type StType is ( READY, DECIDE , ADDR_PHASE , ADDR_TO_DATA_GAP , ADDR_TO_DATA_GAP2, ADDR_TO_DATA_GAP3, DATA_PHASE , ALMOST_READY , ALMOST_READY2 , ALMOST_READY3 ); constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001"; constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000"; constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011"; constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010"; constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101"; constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100"; constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111"; constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110"; constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001"; constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000"; constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011"; constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010"; constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101"; constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100"; constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111"; constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110"; constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101"; constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100"; constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111"; constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110"; signal memcell_addr_reg : std_logic_vector(7 downto 0); signal data_reg : std_logic_vector(7 downto 0); signal shift_through_reg : std_logic_vector(8 downto 0); signal load_shift_n : std_logic; signal addr_data_sel_n : std_logic; signal bit_cnt : std_logic_vector(2 downto 0); signal rd_not_write_reg : std_logic; signal AddressPhase : std_logic; signal DRP_CS_pre : std_logic; signal extra_cs : std_logic; signal state,nextstate : StType; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "gray"; attribute fsm_encoding of nextstate : signal is "gray"; signal data_out : std_logic_vector(8 downto 0); signal data_out_mux : std_logic_vector(8 downto 0); signal DRP_SDI_pre : std_logic; --synthesis translate_off signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0); -- case(state) --synthesis translate_on -- The changes below are to compensate for an issue with 1.0 silicon. -- It may still be necessary to add a clock cycle to the ADD and CS signals --`define DRP_v1_0_FIX // Uncomment out this line for synthesis procedure shift_n_expand( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(8 downto 0)) is variable data_out_xilinx2 : std_logic_vector(8 downto 0); begin if ((data_in(0)) = '1') then data_out_xilinx2(1 downto 0) := "11"; else data_out_xilinx2(1 downto 0) := "00"; end if; if (data_in(1 downto 0) = "10") then data_out_xilinx2(2 downto 1) := "11"; else data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1)); end if; if (data_in(2 downto 1) = "10") then data_out_xilinx2(3 downto 2) := "11"; else data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2)); end if; if (data_in(3 downto 2) = "10") then data_out_xilinx2(4 downto 3) := "11"; else data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3)); end if; if (data_in(4 downto 3) = "10") then data_out_xilinx2(5 downto 4) := "11"; else data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4)); end if; if (data_in(5 downto 4) = "10") then data_out_xilinx2(6 downto 5) := "11"; else data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5)); end if; if (data_in(6 downto 5) = "10") then data_out_xilinx2(7 downto 6) := "11"; else data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6)); end if; if (data_in(7 downto 6) = "10") then data_out_xilinx2(8 downto 7) := "11"; else data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7)); end if; end shift_n_expand; -- Declare intermediate signals for referenced outputs signal DRP_CS_xilinx1 : std_logic; signal DRP_ADD_xilinx0 : std_logic; signal ALMOST_READY2_ST : std_logic; signal ADDR_PHASE_ST : std_logic; signal BIT_CNT7 : std_logic; signal ADDR_PHASE_ST1 : std_logic; signal DATA_PHASE_ST : std_logic; begin -- Drive referenced outputs DRP_CS <= DRP_CS_xilinx1; DRP_ADD <= DRP_ADD_xilinx0; -- process (state) -- begin -- case state is -- when READY => -- state_ascii <= "READY"; -- when DECIDE => -- state_ascii <= "DECIDE"; -- when ADDR_PHASE => -- state_ascii <= "ADDR_PHASE"; -- when ADDR_TO_DATA_GAP => -- state_ascii <= "ADDR_TO_DATA_GAP"; -- when ADDR_TO_DATA_GAP2 => -- state_ascii <= "ADDR_TO_DATA_GAP2"; -- when ADDR_TO_DATA_GAP3 => -- state_ascii <= "ADDR_TO_DATA_GAP3"; -- when DATA_PHASE => -- state_ascii <= "DATA_PHASE"; -- when ALMOST_READY => -- state_ascii <= "ALMOST_READY"; -- when ALMOST_READY2 => -- state_ascii <= "ALMOST_READY2"; -- when ALMOST_READY3 => -- state_ascii <= "ALMOST_READY3"; -- when others => -- null; -- end case; -- end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (state = READY) then memcell_addr_reg <= memcell_address; data_reg <= write_data; rd_not_write_reg <= rd_not_write; end if; end if; end process; rdy_busy_n <= '1' when state = READY else '0'; process (drp_ioi_addr, data_out) begin case drp_ioi_addr is when IOI_DQ0 => data_out_mux <= data_out; when IOI_DQ1 => data_out_mux <= data_out; when IOI_DQ2 => data_out_mux <= data_out; when IOI_DQ3 => data_out_mux <= data_out; when IOI_DQ4 => data_out_mux <= data_out; when IOI_DQ5 => data_out_mux <= data_out; when IOI_DQ6 => data_out_mux <= data_out; when IOI_DQ7 => data_out_mux <= data_out; when IOI_DQ8 => data_out_mux <= data_out; when IOI_DQ9 => data_out_mux <= data_out; when IOI_DQ10 => data_out_mux <= data_out; when IOI_DQ11 => data_out_mux <= data_out; when IOI_DQ12 => data_out_mux <= data_out; when IOI_DQ13 => data_out_mux <= data_out; when IOI_DQ14 => data_out_mux <= data_out; when IOI_DQ15 => data_out_mux <= data_out; when IOI_UDQS_CLK => data_out_mux <= data_out; when IOI_UDQS_PIN => data_out_mux <= data_out; when IOI_LDQS_CLK => data_out_mux <= data_out; when IOI_LDQS_PIN => data_out_mux <= data_out; when others => data_out_mux <= data_out; end case; end process; data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else ('0' & data_reg); process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then shift_through_reg <= "000000000"; else if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first shift_through_reg <= data_out_mux; else shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1)); end if; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then bit_cnt <= bit_cnt + "001"; else bit_cnt <= "000"; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then read_data <= "00000000"; else if (state = ALMOST_READY3) then read_data <= shift_through_reg(7 downto 0); end if; end if; end if; end process; ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0'; ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0'; BIT_CNT7 <= '1' when bit_cnt = "111" else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then AddressPhase <= '0'; else if (AddressPhase = '1') then -- Keep it set until we finish the cycle AddressPhase <= AddressPhase and (not ALMOST_READY2_ST); else -- set the address phase when ever we finish the address phase AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7); end if; end if; end if; end process; ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0'; DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then DRP_ADD_xilinx0 <= ADDR_PHASE_ST1; -- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE); DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST; MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg; if (state = READY) then DRP_BKST <= use_broadcast; end if; end if; end process; DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance '0'; DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance DRP_SDI_pre; process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7) begin addr_data_sel_n <= '0'; load_shift_n <= '0'; case state is when READY => load_shift_n <= '0'; if (cmd_valid = '1') then nextstate <= DECIDE; else nextstate <= READY; end if; when DECIDE => load_shift_n <= '1'; addr_data_sel_n <= '1'; nextstate <= ADDR_PHASE; -- After the second pass go to end of statemachine -- execute a second address phase for the alternative access method. when ADDR_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then if (('1' and rd_not_write_reg) = '1') then if (AddressPhase = '1') then nextstate <= ALMOST_READY; else nextstate <= DECIDE; end if; else nextstate <= ADDR_TO_DATA_GAP; end if; else nextstate <= ADDR_PHASE; end if; when ADDR_TO_DATA_GAP => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP2; when ADDR_TO_DATA_GAP2 => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP3; when ADDR_TO_DATA_GAP3 => load_shift_n <= '1'; nextstate <= DATA_PHASE; when DATA_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then nextstate <= ALMOST_READY; else nextstate <= DATA_PHASE; end if; when ALMOST_READY => load_shift_n <= '0'; nextstate <= ALMOST_READY2; when ALMOST_READY2 => load_shift_n <= '0'; nextstate <= ALMOST_READY3; when ALMOST_READY3 => load_shift_n <= '0'; nextstate <= READY; when others => load_shift_n <= '0'; nextstate <= READY; end case; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then state <= READY; else state <= nextstate; end if; end if; end process; end architecture trans;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: iodrp_mcb_controller.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for IODRP controller for v0.9 device -- --Reference: -- -- Revision: Date: Comment -- 1.0: 03/19/09: Initial version for IODRP_MCB read operations. -- 1.1: 04/03/09: SLH - Added left shift for certain IOI's -- 1.2: 02/14/11: Change FSM encoding from one-hot to gray to match Verilog version. -- End Revision --******************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity iodrp_mcb_controller is --output to IODRP SDI pin --input from IODRP SDO pin -- Register where memcell_address is captured during the READY state -- Register which stores the write data until it is ready to be shifted out -- The shift register which shifts out SDO and shifts in SDI. -- This register is loaded before the address or data phase, but continues to shift for a writeback of read data -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO -- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg -- The counter for which bit is being shifted during address or data phase -- This is set after the first address phase has executed -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg --added so that DRP_SDI output is only active when DRP_CS is active port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end entity iodrp_mcb_controller; architecture trans of iodrp_mcb_controller is type StType is ( READY, DECIDE , ADDR_PHASE , ADDR_TO_DATA_GAP , ADDR_TO_DATA_GAP2, ADDR_TO_DATA_GAP3, DATA_PHASE , ALMOST_READY , ALMOST_READY2 , ALMOST_READY3 ); constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001"; constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000"; constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011"; constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010"; constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101"; constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100"; constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111"; constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110"; constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001"; constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000"; constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011"; constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010"; constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101"; constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100"; constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111"; constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110"; constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101"; constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100"; constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111"; constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110"; signal memcell_addr_reg : std_logic_vector(7 downto 0); signal data_reg : std_logic_vector(7 downto 0); signal shift_through_reg : std_logic_vector(8 downto 0); signal load_shift_n : std_logic; signal addr_data_sel_n : std_logic; signal bit_cnt : std_logic_vector(2 downto 0); signal rd_not_write_reg : std_logic; signal AddressPhase : std_logic; signal DRP_CS_pre : std_logic; signal extra_cs : std_logic; signal state,nextstate : StType; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "gray"; attribute fsm_encoding of nextstate : signal is "gray"; signal data_out : std_logic_vector(8 downto 0); signal data_out_mux : std_logic_vector(8 downto 0); signal DRP_SDI_pre : std_logic; --synthesis translate_off signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0); -- case(state) --synthesis translate_on -- The changes below are to compensate for an issue with 1.0 silicon. -- It may still be necessary to add a clock cycle to the ADD and CS signals --`define DRP_v1_0_FIX // Uncomment out this line for synthesis procedure shift_n_expand( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(8 downto 0)) is variable data_out_xilinx2 : std_logic_vector(8 downto 0); begin if ((data_in(0)) = '1') then data_out_xilinx2(1 downto 0) := "11"; else data_out_xilinx2(1 downto 0) := "00"; end if; if (data_in(1 downto 0) = "10") then data_out_xilinx2(2 downto 1) := "11"; else data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1)); end if; if (data_in(2 downto 1) = "10") then data_out_xilinx2(3 downto 2) := "11"; else data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2)); end if; if (data_in(3 downto 2) = "10") then data_out_xilinx2(4 downto 3) := "11"; else data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3)); end if; if (data_in(4 downto 3) = "10") then data_out_xilinx2(5 downto 4) := "11"; else data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4)); end if; if (data_in(5 downto 4) = "10") then data_out_xilinx2(6 downto 5) := "11"; else data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5)); end if; if (data_in(6 downto 5) = "10") then data_out_xilinx2(7 downto 6) := "11"; else data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6)); end if; if (data_in(7 downto 6) = "10") then data_out_xilinx2(8 downto 7) := "11"; else data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7)); end if; end shift_n_expand; -- Declare intermediate signals for referenced outputs signal DRP_CS_xilinx1 : std_logic; signal DRP_ADD_xilinx0 : std_logic; signal ALMOST_READY2_ST : std_logic; signal ADDR_PHASE_ST : std_logic; signal BIT_CNT7 : std_logic; signal ADDR_PHASE_ST1 : std_logic; signal DATA_PHASE_ST : std_logic; begin -- Drive referenced outputs DRP_CS <= DRP_CS_xilinx1; DRP_ADD <= DRP_ADD_xilinx0; -- process (state) -- begin -- case state is -- when READY => -- state_ascii <= "READY"; -- when DECIDE => -- state_ascii <= "DECIDE"; -- when ADDR_PHASE => -- state_ascii <= "ADDR_PHASE"; -- when ADDR_TO_DATA_GAP => -- state_ascii <= "ADDR_TO_DATA_GAP"; -- when ADDR_TO_DATA_GAP2 => -- state_ascii <= "ADDR_TO_DATA_GAP2"; -- when ADDR_TO_DATA_GAP3 => -- state_ascii <= "ADDR_TO_DATA_GAP3"; -- when DATA_PHASE => -- state_ascii <= "DATA_PHASE"; -- when ALMOST_READY => -- state_ascii <= "ALMOST_READY"; -- when ALMOST_READY2 => -- state_ascii <= "ALMOST_READY2"; -- when ALMOST_READY3 => -- state_ascii <= "ALMOST_READY3"; -- when others => -- null; -- end case; -- end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (state = READY) then memcell_addr_reg <= memcell_address; data_reg <= write_data; rd_not_write_reg <= rd_not_write; end if; end if; end process; rdy_busy_n <= '1' when state = READY else '0'; process (drp_ioi_addr, data_out) begin case drp_ioi_addr is when IOI_DQ0 => data_out_mux <= data_out; when IOI_DQ1 => data_out_mux <= data_out; when IOI_DQ2 => data_out_mux <= data_out; when IOI_DQ3 => data_out_mux <= data_out; when IOI_DQ4 => data_out_mux <= data_out; when IOI_DQ5 => data_out_mux <= data_out; when IOI_DQ6 => data_out_mux <= data_out; when IOI_DQ7 => data_out_mux <= data_out; when IOI_DQ8 => data_out_mux <= data_out; when IOI_DQ9 => data_out_mux <= data_out; when IOI_DQ10 => data_out_mux <= data_out; when IOI_DQ11 => data_out_mux <= data_out; when IOI_DQ12 => data_out_mux <= data_out; when IOI_DQ13 => data_out_mux <= data_out; when IOI_DQ14 => data_out_mux <= data_out; when IOI_DQ15 => data_out_mux <= data_out; when IOI_UDQS_CLK => data_out_mux <= data_out; when IOI_UDQS_PIN => data_out_mux <= data_out; when IOI_LDQS_CLK => data_out_mux <= data_out; when IOI_LDQS_PIN => data_out_mux <= data_out; when others => data_out_mux <= data_out; end case; end process; data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else ('0' & data_reg); process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then shift_through_reg <= "000000000"; else if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first shift_through_reg <= data_out_mux; else shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1)); end if; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then bit_cnt <= bit_cnt + "001"; else bit_cnt <= "000"; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then read_data <= "00000000"; else if (state = ALMOST_READY3) then read_data <= shift_through_reg(7 downto 0); end if; end if; end if; end process; ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0'; ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0'; BIT_CNT7 <= '1' when bit_cnt = "111" else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then AddressPhase <= '0'; else if (AddressPhase = '1') then -- Keep it set until we finish the cycle AddressPhase <= AddressPhase and (not ALMOST_READY2_ST); else -- set the address phase when ever we finish the address phase AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7); end if; end if; end if; end process; ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0'; DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then DRP_ADD_xilinx0 <= ADDR_PHASE_ST1; -- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE); DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST; MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg; if (state = READY) then DRP_BKST <= use_broadcast; end if; end if; end process; DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance '0'; DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance DRP_SDI_pre; process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7) begin addr_data_sel_n <= '0'; load_shift_n <= '0'; case state is when READY => load_shift_n <= '0'; if (cmd_valid = '1') then nextstate <= DECIDE; else nextstate <= READY; end if; when DECIDE => load_shift_n <= '1'; addr_data_sel_n <= '1'; nextstate <= ADDR_PHASE; -- After the second pass go to end of statemachine -- execute a second address phase for the alternative access method. when ADDR_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then if (('1' and rd_not_write_reg) = '1') then if (AddressPhase = '1') then nextstate <= ALMOST_READY; else nextstate <= DECIDE; end if; else nextstate <= ADDR_TO_DATA_GAP; end if; else nextstate <= ADDR_PHASE; end if; when ADDR_TO_DATA_GAP => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP2; when ADDR_TO_DATA_GAP2 => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP3; when ADDR_TO_DATA_GAP3 => load_shift_n <= '1'; nextstate <= DATA_PHASE; when DATA_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then nextstate <= ALMOST_READY; else nextstate <= DATA_PHASE; end if; when ALMOST_READY => load_shift_n <= '0'; nextstate <= ALMOST_READY2; when ALMOST_READY2 => load_shift_n <= '0'; nextstate <= ALMOST_READY3; when ALMOST_READY3 => load_shift_n <= '0'; nextstate <= READY; when others => load_shift_n <= '0'; nextstate <= READY; end case; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then state <= READY; else state <= nextstate; end if; end if; end process; end architecture trans;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: iodrp_mcb_controller.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for IODRP controller for v0.9 device -- --Reference: -- -- Revision: Date: Comment -- 1.0: 03/19/09: Initial version for IODRP_MCB read operations. -- 1.1: 04/03/09: SLH - Added left shift for certain IOI's -- 1.2: 02/14/11: Change FSM encoding from one-hot to gray to match Verilog version. -- End Revision --******************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity iodrp_mcb_controller is --output to IODRP SDI pin --input from IODRP SDO pin -- Register where memcell_address is captured during the READY state -- Register which stores the write data until it is ready to be shifted out -- The shift register which shifts out SDO and shifts in SDI. -- This register is loaded before the address or data phase, but continues to shift for a writeback of read data -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO -- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg -- The counter for which bit is being shifted during address or data phase -- This is set after the first address phase has executed -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg --added so that DRP_SDI output is only active when DRP_CS is active port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end entity iodrp_mcb_controller; architecture trans of iodrp_mcb_controller is type StType is ( READY, DECIDE , ADDR_PHASE , ADDR_TO_DATA_GAP , ADDR_TO_DATA_GAP2, ADDR_TO_DATA_GAP3, DATA_PHASE , ALMOST_READY , ALMOST_READY2 , ALMOST_READY3 ); constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001"; constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000"; constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011"; constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010"; constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101"; constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100"; constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111"; constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110"; constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001"; constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000"; constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011"; constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010"; constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101"; constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100"; constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111"; constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110"; constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101"; constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100"; constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111"; constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110"; signal memcell_addr_reg : std_logic_vector(7 downto 0); signal data_reg : std_logic_vector(7 downto 0); signal shift_through_reg : std_logic_vector(8 downto 0); signal load_shift_n : std_logic; signal addr_data_sel_n : std_logic; signal bit_cnt : std_logic_vector(2 downto 0); signal rd_not_write_reg : std_logic; signal AddressPhase : std_logic; signal DRP_CS_pre : std_logic; signal extra_cs : std_logic; signal state,nextstate : StType; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "gray"; attribute fsm_encoding of nextstate : signal is "gray"; signal data_out : std_logic_vector(8 downto 0); signal data_out_mux : std_logic_vector(8 downto 0); signal DRP_SDI_pre : std_logic; --synthesis translate_off signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0); -- case(state) --synthesis translate_on -- The changes below are to compensate for an issue with 1.0 silicon. -- It may still be necessary to add a clock cycle to the ADD and CS signals --`define DRP_v1_0_FIX // Uncomment out this line for synthesis procedure shift_n_expand( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(8 downto 0)) is variable data_out_xilinx2 : std_logic_vector(8 downto 0); begin if ((data_in(0)) = '1') then data_out_xilinx2(1 downto 0) := "11"; else data_out_xilinx2(1 downto 0) := "00"; end if; if (data_in(1 downto 0) = "10") then data_out_xilinx2(2 downto 1) := "11"; else data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1)); end if; if (data_in(2 downto 1) = "10") then data_out_xilinx2(3 downto 2) := "11"; else data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2)); end if; if (data_in(3 downto 2) = "10") then data_out_xilinx2(4 downto 3) := "11"; else data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3)); end if; if (data_in(4 downto 3) = "10") then data_out_xilinx2(5 downto 4) := "11"; else data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4)); end if; if (data_in(5 downto 4) = "10") then data_out_xilinx2(6 downto 5) := "11"; else data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5)); end if; if (data_in(6 downto 5) = "10") then data_out_xilinx2(7 downto 6) := "11"; else data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6)); end if; if (data_in(7 downto 6) = "10") then data_out_xilinx2(8 downto 7) := "11"; else data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7)); end if; end shift_n_expand; -- Declare intermediate signals for referenced outputs signal DRP_CS_xilinx1 : std_logic; signal DRP_ADD_xilinx0 : std_logic; signal ALMOST_READY2_ST : std_logic; signal ADDR_PHASE_ST : std_logic; signal BIT_CNT7 : std_logic; signal ADDR_PHASE_ST1 : std_logic; signal DATA_PHASE_ST : std_logic; begin -- Drive referenced outputs DRP_CS <= DRP_CS_xilinx1; DRP_ADD <= DRP_ADD_xilinx0; -- process (state) -- begin -- case state is -- when READY => -- state_ascii <= "READY"; -- when DECIDE => -- state_ascii <= "DECIDE"; -- when ADDR_PHASE => -- state_ascii <= "ADDR_PHASE"; -- when ADDR_TO_DATA_GAP => -- state_ascii <= "ADDR_TO_DATA_GAP"; -- when ADDR_TO_DATA_GAP2 => -- state_ascii <= "ADDR_TO_DATA_GAP2"; -- when ADDR_TO_DATA_GAP3 => -- state_ascii <= "ADDR_TO_DATA_GAP3"; -- when DATA_PHASE => -- state_ascii <= "DATA_PHASE"; -- when ALMOST_READY => -- state_ascii <= "ALMOST_READY"; -- when ALMOST_READY2 => -- state_ascii <= "ALMOST_READY2"; -- when ALMOST_READY3 => -- state_ascii <= "ALMOST_READY3"; -- when others => -- null; -- end case; -- end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (state = READY) then memcell_addr_reg <= memcell_address; data_reg <= write_data; rd_not_write_reg <= rd_not_write; end if; end if; end process; rdy_busy_n <= '1' when state = READY else '0'; process (drp_ioi_addr, data_out) begin case drp_ioi_addr is when IOI_DQ0 => data_out_mux <= data_out; when IOI_DQ1 => data_out_mux <= data_out; when IOI_DQ2 => data_out_mux <= data_out; when IOI_DQ3 => data_out_mux <= data_out; when IOI_DQ4 => data_out_mux <= data_out; when IOI_DQ5 => data_out_mux <= data_out; when IOI_DQ6 => data_out_mux <= data_out; when IOI_DQ7 => data_out_mux <= data_out; when IOI_DQ8 => data_out_mux <= data_out; when IOI_DQ9 => data_out_mux <= data_out; when IOI_DQ10 => data_out_mux <= data_out; when IOI_DQ11 => data_out_mux <= data_out; when IOI_DQ12 => data_out_mux <= data_out; when IOI_DQ13 => data_out_mux <= data_out; when IOI_DQ14 => data_out_mux <= data_out; when IOI_DQ15 => data_out_mux <= data_out; when IOI_UDQS_CLK => data_out_mux <= data_out; when IOI_UDQS_PIN => data_out_mux <= data_out; when IOI_LDQS_CLK => data_out_mux <= data_out; when IOI_LDQS_PIN => data_out_mux <= data_out; when others => data_out_mux <= data_out; end case; end process; data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else ('0' & data_reg); process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then shift_through_reg <= "000000000"; else if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first shift_through_reg <= data_out_mux; else shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1)); end if; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then bit_cnt <= bit_cnt + "001"; else bit_cnt <= "000"; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then read_data <= "00000000"; else if (state = ALMOST_READY3) then read_data <= shift_through_reg(7 downto 0); end if; end if; end if; end process; ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0'; ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0'; BIT_CNT7 <= '1' when bit_cnt = "111" else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then AddressPhase <= '0'; else if (AddressPhase = '1') then -- Keep it set until we finish the cycle AddressPhase <= AddressPhase and (not ALMOST_READY2_ST); else -- set the address phase when ever we finish the address phase AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7); end if; end if; end if; end process; ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0'; DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then DRP_ADD_xilinx0 <= ADDR_PHASE_ST1; -- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE); DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST; MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg; if (state = READY) then DRP_BKST <= use_broadcast; end if; end if; end process; DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance '0'; DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance DRP_SDI_pre; process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7) begin addr_data_sel_n <= '0'; load_shift_n <= '0'; case state is when READY => load_shift_n <= '0'; if (cmd_valid = '1') then nextstate <= DECIDE; else nextstate <= READY; end if; when DECIDE => load_shift_n <= '1'; addr_data_sel_n <= '1'; nextstate <= ADDR_PHASE; -- After the second pass go to end of statemachine -- execute a second address phase for the alternative access method. when ADDR_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then if (('1' and rd_not_write_reg) = '1') then if (AddressPhase = '1') then nextstate <= ALMOST_READY; else nextstate <= DECIDE; end if; else nextstate <= ADDR_TO_DATA_GAP; end if; else nextstate <= ADDR_PHASE; end if; when ADDR_TO_DATA_GAP => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP2; when ADDR_TO_DATA_GAP2 => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP3; when ADDR_TO_DATA_GAP3 => load_shift_n <= '1'; nextstate <= DATA_PHASE; when DATA_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then nextstate <= ALMOST_READY; else nextstate <= DATA_PHASE; end if; when ALMOST_READY => load_shift_n <= '0'; nextstate <= ALMOST_READY2; when ALMOST_READY2 => load_shift_n <= '0'; nextstate <= ALMOST_READY3; when ALMOST_READY3 => load_shift_n <= '0'; nextstate <= READY; when others => load_shift_n <= '0'; nextstate <= READY; end case; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then state <= READY; else state <= nextstate; end if; end if; end process; end architecture trans;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: iodrp_mcb_controller.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for IODRP controller for v0.9 device -- --Reference: -- -- Revision: Date: Comment -- 1.0: 03/19/09: Initial version for IODRP_MCB read operations. -- 1.1: 04/03/09: SLH - Added left shift for certain IOI's -- 1.2: 02/14/11: Change FSM encoding from one-hot to gray to match Verilog version. -- End Revision --******************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity iodrp_mcb_controller is --output to IODRP SDI pin --input from IODRP SDO pin -- Register where memcell_address is captured during the READY state -- Register which stores the write data until it is ready to be shifted out -- The shift register which shifts out SDO and shifts in SDI. -- This register is loaded before the address or data phase, but continues to shift for a writeback of read data -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO -- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg -- The counter for which bit is being shifted during address or data phase -- This is set after the first address phase has executed -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg --added so that DRP_SDI output is only active when DRP_CS is active port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end entity iodrp_mcb_controller; architecture trans of iodrp_mcb_controller is type StType is ( READY, DECIDE , ADDR_PHASE , ADDR_TO_DATA_GAP , ADDR_TO_DATA_GAP2, ADDR_TO_DATA_GAP3, DATA_PHASE , ALMOST_READY , ALMOST_READY2 , ALMOST_READY3 ); constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001"; constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000"; constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011"; constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010"; constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101"; constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100"; constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111"; constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110"; constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001"; constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000"; constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011"; constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010"; constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101"; constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100"; constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111"; constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110"; constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101"; constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100"; constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111"; constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110"; signal memcell_addr_reg : std_logic_vector(7 downto 0); signal data_reg : std_logic_vector(7 downto 0); signal shift_through_reg : std_logic_vector(8 downto 0); signal load_shift_n : std_logic; signal addr_data_sel_n : std_logic; signal bit_cnt : std_logic_vector(2 downto 0); signal rd_not_write_reg : std_logic; signal AddressPhase : std_logic; signal DRP_CS_pre : std_logic; signal extra_cs : std_logic; signal state,nextstate : StType; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "gray"; attribute fsm_encoding of nextstate : signal is "gray"; signal data_out : std_logic_vector(8 downto 0); signal data_out_mux : std_logic_vector(8 downto 0); signal DRP_SDI_pre : std_logic; --synthesis translate_off signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0); -- case(state) --synthesis translate_on -- The changes below are to compensate for an issue with 1.0 silicon. -- It may still be necessary to add a clock cycle to the ADD and CS signals --`define DRP_v1_0_FIX // Uncomment out this line for synthesis procedure shift_n_expand( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(8 downto 0)) is variable data_out_xilinx2 : std_logic_vector(8 downto 0); begin if ((data_in(0)) = '1') then data_out_xilinx2(1 downto 0) := "11"; else data_out_xilinx2(1 downto 0) := "00"; end if; if (data_in(1 downto 0) = "10") then data_out_xilinx2(2 downto 1) := "11"; else data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1)); end if; if (data_in(2 downto 1) = "10") then data_out_xilinx2(3 downto 2) := "11"; else data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2)); end if; if (data_in(3 downto 2) = "10") then data_out_xilinx2(4 downto 3) := "11"; else data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3)); end if; if (data_in(4 downto 3) = "10") then data_out_xilinx2(5 downto 4) := "11"; else data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4)); end if; if (data_in(5 downto 4) = "10") then data_out_xilinx2(6 downto 5) := "11"; else data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5)); end if; if (data_in(6 downto 5) = "10") then data_out_xilinx2(7 downto 6) := "11"; else data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6)); end if; if (data_in(7 downto 6) = "10") then data_out_xilinx2(8 downto 7) := "11"; else data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7)); end if; end shift_n_expand; -- Declare intermediate signals for referenced outputs signal DRP_CS_xilinx1 : std_logic; signal DRP_ADD_xilinx0 : std_logic; signal ALMOST_READY2_ST : std_logic; signal ADDR_PHASE_ST : std_logic; signal BIT_CNT7 : std_logic; signal ADDR_PHASE_ST1 : std_logic; signal DATA_PHASE_ST : std_logic; begin -- Drive referenced outputs DRP_CS <= DRP_CS_xilinx1; DRP_ADD <= DRP_ADD_xilinx0; -- process (state) -- begin -- case state is -- when READY => -- state_ascii <= "READY"; -- when DECIDE => -- state_ascii <= "DECIDE"; -- when ADDR_PHASE => -- state_ascii <= "ADDR_PHASE"; -- when ADDR_TO_DATA_GAP => -- state_ascii <= "ADDR_TO_DATA_GAP"; -- when ADDR_TO_DATA_GAP2 => -- state_ascii <= "ADDR_TO_DATA_GAP2"; -- when ADDR_TO_DATA_GAP3 => -- state_ascii <= "ADDR_TO_DATA_GAP3"; -- when DATA_PHASE => -- state_ascii <= "DATA_PHASE"; -- when ALMOST_READY => -- state_ascii <= "ALMOST_READY"; -- when ALMOST_READY2 => -- state_ascii <= "ALMOST_READY2"; -- when ALMOST_READY3 => -- state_ascii <= "ALMOST_READY3"; -- when others => -- null; -- end case; -- end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (state = READY) then memcell_addr_reg <= memcell_address; data_reg <= write_data; rd_not_write_reg <= rd_not_write; end if; end if; end process; rdy_busy_n <= '1' when state = READY else '0'; process (drp_ioi_addr, data_out) begin case drp_ioi_addr is when IOI_DQ0 => data_out_mux <= data_out; when IOI_DQ1 => data_out_mux <= data_out; when IOI_DQ2 => data_out_mux <= data_out; when IOI_DQ3 => data_out_mux <= data_out; when IOI_DQ4 => data_out_mux <= data_out; when IOI_DQ5 => data_out_mux <= data_out; when IOI_DQ6 => data_out_mux <= data_out; when IOI_DQ7 => data_out_mux <= data_out; when IOI_DQ8 => data_out_mux <= data_out; when IOI_DQ9 => data_out_mux <= data_out; when IOI_DQ10 => data_out_mux <= data_out; when IOI_DQ11 => data_out_mux <= data_out; when IOI_DQ12 => data_out_mux <= data_out; when IOI_DQ13 => data_out_mux <= data_out; when IOI_DQ14 => data_out_mux <= data_out; when IOI_DQ15 => data_out_mux <= data_out; when IOI_UDQS_CLK => data_out_mux <= data_out; when IOI_UDQS_PIN => data_out_mux <= data_out; when IOI_LDQS_CLK => data_out_mux <= data_out; when IOI_LDQS_PIN => data_out_mux <= data_out; when others => data_out_mux <= data_out; end case; end process; data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else ('0' & data_reg); process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then shift_through_reg <= "000000000"; else if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first shift_through_reg <= data_out_mux; else shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1)); end if; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then bit_cnt <= bit_cnt + "001"; else bit_cnt <= "000"; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then read_data <= "00000000"; else if (state = ALMOST_READY3) then read_data <= shift_through_reg(7 downto 0); end if; end if; end if; end process; ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0'; ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0'; BIT_CNT7 <= '1' when bit_cnt = "111" else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then AddressPhase <= '0'; else if (AddressPhase = '1') then -- Keep it set until we finish the cycle AddressPhase <= AddressPhase and (not ALMOST_READY2_ST); else -- set the address phase when ever we finish the address phase AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7); end if; end if; end if; end process; ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0'; DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then DRP_ADD_xilinx0 <= ADDR_PHASE_ST1; -- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE); DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST; MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg; if (state = READY) then DRP_BKST <= use_broadcast; end if; end if; end process; DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance '0'; DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance DRP_SDI_pre; process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7) begin addr_data_sel_n <= '0'; load_shift_n <= '0'; case state is when READY => load_shift_n <= '0'; if (cmd_valid = '1') then nextstate <= DECIDE; else nextstate <= READY; end if; when DECIDE => load_shift_n <= '1'; addr_data_sel_n <= '1'; nextstate <= ADDR_PHASE; -- After the second pass go to end of statemachine -- execute a second address phase for the alternative access method. when ADDR_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then if (('1' and rd_not_write_reg) = '1') then if (AddressPhase = '1') then nextstate <= ALMOST_READY; else nextstate <= DECIDE; end if; else nextstate <= ADDR_TO_DATA_GAP; end if; else nextstate <= ADDR_PHASE; end if; when ADDR_TO_DATA_GAP => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP2; when ADDR_TO_DATA_GAP2 => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP3; when ADDR_TO_DATA_GAP3 => load_shift_n <= '1'; nextstate <= DATA_PHASE; when DATA_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then nextstate <= ALMOST_READY; else nextstate <= DATA_PHASE; end if; when ALMOST_READY => load_shift_n <= '0'; nextstate <= ALMOST_READY2; when ALMOST_READY2 => load_shift_n <= '0'; nextstate <= ALMOST_READY3; when ALMOST_READY3 => load_shift_n <= '0'; nextstate <= READY; when others => load_shift_n <= '0'; nextstate <= READY; end case; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then state <= READY; else state <= nextstate; end if; end if; end process; end architecture trans;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: iodrp_mcb_controller.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for IODRP controller for v0.9 device -- --Reference: -- -- Revision: Date: Comment -- 1.0: 03/19/09: Initial version for IODRP_MCB read operations. -- 1.1: 04/03/09: SLH - Added left shift for certain IOI's -- 1.2: 02/14/11: Change FSM encoding from one-hot to gray to match Verilog version. -- End Revision --******************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity iodrp_mcb_controller is --output to IODRP SDI pin --input from IODRP SDO pin -- Register where memcell_address is captured during the READY state -- Register which stores the write data until it is ready to be shifted out -- The shift register which shifts out SDO and shifts in SDI. -- This register is loaded before the address or data phase, but continues to shift for a writeback of read data -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO -- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg -- The counter for which bit is being shifted during address or data phase -- This is set after the first address phase has executed -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg --added so that DRP_SDI output is only active when DRP_CS is active port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end entity iodrp_mcb_controller; architecture trans of iodrp_mcb_controller is type StType is ( READY, DECIDE , ADDR_PHASE , ADDR_TO_DATA_GAP , ADDR_TO_DATA_GAP2, ADDR_TO_DATA_GAP3, DATA_PHASE , ALMOST_READY , ALMOST_READY2 , ALMOST_READY3 ); constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001"; constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000"; constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011"; constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010"; constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101"; constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100"; constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111"; constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110"; constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001"; constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000"; constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011"; constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010"; constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101"; constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100"; constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111"; constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110"; constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101"; constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100"; constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111"; constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110"; signal memcell_addr_reg : std_logic_vector(7 downto 0); signal data_reg : std_logic_vector(7 downto 0); signal shift_through_reg : std_logic_vector(8 downto 0); signal load_shift_n : std_logic; signal addr_data_sel_n : std_logic; signal bit_cnt : std_logic_vector(2 downto 0); signal rd_not_write_reg : std_logic; signal AddressPhase : std_logic; signal DRP_CS_pre : std_logic; signal extra_cs : std_logic; signal state,nextstate : StType; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "gray"; attribute fsm_encoding of nextstate : signal is "gray"; signal data_out : std_logic_vector(8 downto 0); signal data_out_mux : std_logic_vector(8 downto 0); signal DRP_SDI_pre : std_logic; --synthesis translate_off signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0); -- case(state) --synthesis translate_on -- The changes below are to compensate for an issue with 1.0 silicon. -- It may still be necessary to add a clock cycle to the ADD and CS signals --`define DRP_v1_0_FIX // Uncomment out this line for synthesis procedure shift_n_expand( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(8 downto 0)) is variable data_out_xilinx2 : std_logic_vector(8 downto 0); begin if ((data_in(0)) = '1') then data_out_xilinx2(1 downto 0) := "11"; else data_out_xilinx2(1 downto 0) := "00"; end if; if (data_in(1 downto 0) = "10") then data_out_xilinx2(2 downto 1) := "11"; else data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1)); end if; if (data_in(2 downto 1) = "10") then data_out_xilinx2(3 downto 2) := "11"; else data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2)); end if; if (data_in(3 downto 2) = "10") then data_out_xilinx2(4 downto 3) := "11"; else data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3)); end if; if (data_in(4 downto 3) = "10") then data_out_xilinx2(5 downto 4) := "11"; else data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4)); end if; if (data_in(5 downto 4) = "10") then data_out_xilinx2(6 downto 5) := "11"; else data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5)); end if; if (data_in(6 downto 5) = "10") then data_out_xilinx2(7 downto 6) := "11"; else data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6)); end if; if (data_in(7 downto 6) = "10") then data_out_xilinx2(8 downto 7) := "11"; else data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7)); end if; end shift_n_expand; -- Declare intermediate signals for referenced outputs signal DRP_CS_xilinx1 : std_logic; signal DRP_ADD_xilinx0 : std_logic; signal ALMOST_READY2_ST : std_logic; signal ADDR_PHASE_ST : std_logic; signal BIT_CNT7 : std_logic; signal ADDR_PHASE_ST1 : std_logic; signal DATA_PHASE_ST : std_logic; begin -- Drive referenced outputs DRP_CS <= DRP_CS_xilinx1; DRP_ADD <= DRP_ADD_xilinx0; -- process (state) -- begin -- case state is -- when READY => -- state_ascii <= "READY"; -- when DECIDE => -- state_ascii <= "DECIDE"; -- when ADDR_PHASE => -- state_ascii <= "ADDR_PHASE"; -- when ADDR_TO_DATA_GAP => -- state_ascii <= "ADDR_TO_DATA_GAP"; -- when ADDR_TO_DATA_GAP2 => -- state_ascii <= "ADDR_TO_DATA_GAP2"; -- when ADDR_TO_DATA_GAP3 => -- state_ascii <= "ADDR_TO_DATA_GAP3"; -- when DATA_PHASE => -- state_ascii <= "DATA_PHASE"; -- when ALMOST_READY => -- state_ascii <= "ALMOST_READY"; -- when ALMOST_READY2 => -- state_ascii <= "ALMOST_READY2"; -- when ALMOST_READY3 => -- state_ascii <= "ALMOST_READY3"; -- when others => -- null; -- end case; -- end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (state = READY) then memcell_addr_reg <= memcell_address; data_reg <= write_data; rd_not_write_reg <= rd_not_write; end if; end if; end process; rdy_busy_n <= '1' when state = READY else '0'; process (drp_ioi_addr, data_out) begin case drp_ioi_addr is when IOI_DQ0 => data_out_mux <= data_out; when IOI_DQ1 => data_out_mux <= data_out; when IOI_DQ2 => data_out_mux <= data_out; when IOI_DQ3 => data_out_mux <= data_out; when IOI_DQ4 => data_out_mux <= data_out; when IOI_DQ5 => data_out_mux <= data_out; when IOI_DQ6 => data_out_mux <= data_out; when IOI_DQ7 => data_out_mux <= data_out; when IOI_DQ8 => data_out_mux <= data_out; when IOI_DQ9 => data_out_mux <= data_out; when IOI_DQ10 => data_out_mux <= data_out; when IOI_DQ11 => data_out_mux <= data_out; when IOI_DQ12 => data_out_mux <= data_out; when IOI_DQ13 => data_out_mux <= data_out; when IOI_DQ14 => data_out_mux <= data_out; when IOI_DQ15 => data_out_mux <= data_out; when IOI_UDQS_CLK => data_out_mux <= data_out; when IOI_UDQS_PIN => data_out_mux <= data_out; when IOI_LDQS_CLK => data_out_mux <= data_out; when IOI_LDQS_PIN => data_out_mux <= data_out; when others => data_out_mux <= data_out; end case; end process; data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else ('0' & data_reg); process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then shift_through_reg <= "000000000"; else if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first shift_through_reg <= data_out_mux; else shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1)); end if; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then bit_cnt <= bit_cnt + "001"; else bit_cnt <= "000"; end if; end if; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then read_data <= "00000000"; else if (state = ALMOST_READY3) then read_data <= shift_through_reg(7 downto 0); end if; end if; end if; end process; ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0'; ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0'; BIT_CNT7 <= '1' when bit_cnt = "111" else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then AddressPhase <= '0'; else if (AddressPhase = '1') then -- Keep it set until we finish the cycle AddressPhase <= AddressPhase and (not ALMOST_READY2_ST); else -- set the address phase when ever we finish the address phase AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7); end if; end if; end if; end process; ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0'; DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0'; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then DRP_ADD_xilinx0 <= ADDR_PHASE_ST1; -- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE); DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST; MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg; if (state = READY) then DRP_BKST <= use_broadcast; end if; end if; end process; DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance '0'; DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance DRP_SDI_pre; process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7) begin addr_data_sel_n <= '0'; load_shift_n <= '0'; case state is when READY => load_shift_n <= '0'; if (cmd_valid = '1') then nextstate <= DECIDE; else nextstate <= READY; end if; when DECIDE => load_shift_n <= '1'; addr_data_sel_n <= '1'; nextstate <= ADDR_PHASE; -- After the second pass go to end of statemachine -- execute a second address phase for the alternative access method. when ADDR_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then if (('1' and rd_not_write_reg) = '1') then if (AddressPhase = '1') then nextstate <= ALMOST_READY; else nextstate <= DECIDE; end if; else nextstate <= ADDR_TO_DATA_GAP; end if; else nextstate <= ADDR_PHASE; end if; when ADDR_TO_DATA_GAP => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP2; when ADDR_TO_DATA_GAP2 => load_shift_n <= '1'; nextstate <= ADDR_TO_DATA_GAP3; when ADDR_TO_DATA_GAP3 => load_shift_n <= '1'; nextstate <= DATA_PHASE; when DATA_PHASE => load_shift_n <= '0'; if (BIT_CNT7 = '1') then nextstate <= ALMOST_READY; else nextstate <= DATA_PHASE; end if; when ALMOST_READY => load_shift_n <= '0'; nextstate <= ALMOST_READY2; when ALMOST_READY2 => load_shift_n <= '0'; nextstate <= ALMOST_READY3; when ALMOST_READY3 => load_shift_n <= '0'; nextstate <= READY; when others => load_shift_n <= '0'; nextstate <= READY; end case; end process; process (DRP_CLK) begin if (DRP_CLK'event and DRP_CLK = '1') then if (sync_rst = '1') then state <= READY; else state <= nextstate; end if; end if; end process; end architecture trans;
-- ------------------------------------------------------------------------------------------- -- Copyright © 2010-2011, Xilinx, Inc. -- This file contains confidential and proprietary information of Xilinx, Inc. and is -- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------- -- -- Disclaimer: -- This disclaimer is not a license and does not grant any rights to the materials -- distributed herewith. Except as otherwise provided in a valid license issued to -- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE -- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY -- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, -- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, -- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable -- (whether in contract or tort, including negligence, or under any other theory -- of liability) for any loss or damage of any kind or nature related to, arising -- under or in connection with these materials, including for any direct, or any -- indirect, special, incidental, or consequential loss or damage (including loss -- of data, profits, goodwill, or any type of loss or damage suffered as a result -- of any action brought by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail-safe, or for use in any -- application requiring fail-safe performance, such as life-support or safety -- devices or systems, Class III medical devices, nuclear facilities, applications -- related to the deployment of airbags, or any other applications that could lead -- to death, personal injury, or severe property or environmental damage -- (individually and collectively, "Critical Applications"). Customer assumes the -- sole risk and liability of any use of Xilinx products in Critical Applications, -- subject only to applicable laws and regulations governing limitations on product -- liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------------------- -- -- KCPSM6 - PicoBlaze for Spartan-6 and Virtex-6 devices. -- -- Start of design entry - 14th May 2010. -- Version 1.0 - 30th September 2010. -- Version 1.1 - 9th February 2011. -- Correction to parity computation logic. -- -- Ken Chapman -- Xilinx Ltd -- Benchmark House -- 203 Brooklands Road -- Weybridge -- Surrey KT13 ORH -- United Kingdom -- -- [email protected] -- ------------------------------------------------------------------------------------------- -- -- Format of this file. -- -- The module defines the implementation of the logic using Xilinx primitives. -- These ensure predictable synthesis results and maximise the density of the implementation. -- The Unisim Library is used to define Xilinx primitives. It is also used during -- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd -- ------------------------------------------------------------------------------------------- -- -- Library declarations -- -- Standard IEEE libraries -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library unisim; use unisim.vcomponents.all; -- ------------------------------------------------------------------------------------------- -- -- Main Entity for kcpsm6 -- entity kcpsm6 is generic( hwbuild : std_logic_vector(7 downto 0) := X"00"; interrupt_vector : std_logic_vector(11 downto 0) := X"3FF"; scratch_pad_memory_size : integer := 64); port ( address : out std_logic_vector(11 downto 0); instruction : in std_logic_vector(17 downto 0); bram_enable : out std_logic; in_port : in std_logic_vector(7 downto 0); out_port : out std_logic_vector(7 downto 0); port_id : out std_logic_vector(7 downto 0); write_strobe : out std_logic; k_write_strobe : out std_logic; read_strobe : out std_logic; interrupt : in std_logic; interrupt_ack : out std_logic; sleep : in std_logic; reset : in std_logic; clk : in std_logic); end kcpsm6; -- ------------------------------------------------------------------------------------------- -- -- Start of Main Architecture for kcpsm6 -- architecture low_level_definition of kcpsm6 is -- ------------------------------------------------------------------------------------------- -- -- Signals used in kcpsm6 -- ------------------------------------------------------------------------------------------- -- -- State Machine and Interrupt -- signal t_state_value : std_logic_vector(2 downto 1); signal t_state : std_logic_vector(2 downto 1); signal run_value : std_logic; signal run : std_logic; signal internal_reset_value : std_logic; signal internal_reset : std_logic; signal sync_sleep : std_logic; signal int_enable_type : std_logic; signal interrupt_enable_value : std_logic; signal interrupt_enable : std_logic; signal sync_interrupt : std_logic; signal active_interrupt_value : std_logic; signal active_interrupt : std_logic; -- -- Arithmetic and Logical Functions -- signal arith_logical_sel : std_logic_vector(2 downto 0); signal arith_carry_in : std_logic; signal arith_carry_value : std_logic; signal arith_carry : std_logic; signal half_arith_logical : std_logic_vector(7 downto 0); signal logical_carry_mask : std_logic_vector(7 downto 0); signal carry_arith_logical : std_logic_vector(7 downto 0); signal arith_logical_value : std_logic_vector(7 downto 0); signal arith_logical_result : std_logic_vector(7 downto 0); -- -- Shift and Rotate Functions -- signal shift_rotate_value : std_logic_vector(7 downto 0); signal shift_rotate_result : std_logic_vector(7 downto 0); signal shift_in_bit : std_logic; -- -- ALU structure -- signal alu_result : std_logic_vector(7 downto 0); signal alu_mux_sel_value : std_logic_vector(1 downto 0); signal alu_mux_sel : std_logic_vector(1 downto 0); -- -- Strobes -- signal strobe_type : std_logic; signal write_strobe_value : std_logic; signal k_write_strobe_value : std_logic; signal read_strobe_value : std_logic; -- -- Flags -- signal flag_enable_type : std_logic; signal flag_enable_value : std_logic; signal flag_enable : std_logic; signal lower_parity : std_logic; signal lower_parity_sel : std_logic; signal carry_lower_parity : std_logic; signal upper_parity : std_logic; signal parity : std_logic; signal shift_carry_value : std_logic; signal shift_carry : std_logic; signal carry_flag_value : std_logic; signal carry_flag : std_logic; signal use_zero_flag_value : std_logic; signal use_zero_flag : std_logic; signal drive_carry_in_zero : std_logic; signal carry_in_zero : std_logic; signal lower_zero : std_logic; signal lower_zero_sel : std_logic; signal carry_lower_zero : std_logic; signal middle_zero : std_logic; signal middle_zero_sel : std_logic; signal carry_middle_zero : std_logic; signal upper_zero_sel : std_logic; signal zero_flag_value : std_logic; signal zero_flag : std_logic; -- -- Scratch Pad Memory -- signal spm_enable_value : std_logic; signal spm_enable : std_logic; signal spm_ram_data : std_logic_vector(7 downto 0); signal spm_data : std_logic_vector(7 downto 0); -- -- Registers -- signal regbank_type : std_logic; signal bank_value : std_logic; signal bank : std_logic; signal loadstar_type : std_logic; signal sx_addr4_value : std_logic; signal register_enable_type : std_logic; signal register_enable_value : std_logic; signal register_enable : std_logic; signal sx_addr : std_logic_vector(4 downto 0); signal sy_addr : std_logic_vector(4 downto 0); signal sx : std_logic_vector(7 downto 0); signal sy : std_logic_vector(7 downto 0); -- -- Second Operand -- signal sy_or_kk : std_logic_vector(7 downto 0); -- -- Program Counter -- signal pc_move_is_valid : std_logic; signal move_type : std_logic; signal returni_type : std_logic; signal pc_mode : std_logic_vector(2 downto 0); signal register_vector : std_logic_vector(11 downto 0); signal half_pc : std_logic_vector(11 downto 0); signal carry_pc : std_logic_vector(10 downto 0); signal pc_value : std_logic_vector(11 downto 0); signal pc : std_logic_vector(11 downto 0); signal pc_vector : std_logic_vector(11 downto 0); -- -- Program Counter Stack -- signal push_stack : std_logic; signal pop_stack : std_logic; signal stack_memory : std_logic_vector(11 downto 0); signal return_vector : std_logic_vector(11 downto 0); signal stack_carry_flag : std_logic; signal shadow_carry_flag : std_logic; signal stack_zero_flag : std_logic; signal shadow_zero_value : std_logic; signal shadow_zero_flag : std_logic; signal stack_bank : std_logic; signal shadow_bank : std_logic; signal stack_bit : std_logic; signal special_bit : std_logic; signal half_pointer_value : std_logic_vector(4 downto 0); signal feed_pointer_value : std_logic_vector(4 downto 0); signal stack_pointer_carry : std_logic_vector(4 downto 0); signal stack_pointer_value : std_logic_vector(4 downto 0); signal stack_pointer : std_logic_vector(4 downto 0); -- -- -- --********************************************************************************** -- -- Signals between these *** lines are only made visible during simulation -- --synthesis translate off -- signal kcpsm6_opcode : string(1 to 19):= "LOAD s0, s0 "; signal kcpsm6_status : string(1 to 16):= "A,NZ,NC,ID,Reset"; signal sim_s0 : std_logic_vector(7 downto 0); signal sim_s1 : std_logic_vector(7 downto 0); signal sim_s2 : std_logic_vector(7 downto 0); signal sim_s3 : std_logic_vector(7 downto 0); signal sim_s4 : std_logic_vector(7 downto 0); signal sim_s5 : std_logic_vector(7 downto 0); signal sim_s6 : std_logic_vector(7 downto 0); signal sim_s7 : std_logic_vector(7 downto 0); signal sim_s8 : std_logic_vector(7 downto 0); signal sim_s9 : std_logic_vector(7 downto 0); signal sim_sA : std_logic_vector(7 downto 0); signal sim_sB : std_logic_vector(7 downto 0); signal sim_sC : std_logic_vector(7 downto 0); signal sim_sD : std_logic_vector(7 downto 0); signal sim_sE : std_logic_vector(7 downto 0); signal sim_sF : std_logic_vector(7 downto 0); signal sim_spm00 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm01 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm02 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm03 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm04 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm05 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm06 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm07 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm08 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm09 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm0A : std_logic_vector(7 downto 0) := X"00"; signal sim_spm0B : std_logic_vector(7 downto 0) := X"00"; signal sim_spm0C : std_logic_vector(7 downto 0) := X"00"; signal sim_spm0D : std_logic_vector(7 downto 0) := X"00"; signal sim_spm0E : std_logic_vector(7 downto 0) := X"00"; signal sim_spm0F : std_logic_vector(7 downto 0) := X"00"; signal sim_spm10 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm11 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm12 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm13 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm14 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm15 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm16 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm17 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm18 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm19 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm1A : std_logic_vector(7 downto 0) := X"00"; signal sim_spm1B : std_logic_vector(7 downto 0) := X"00"; signal sim_spm1C : std_logic_vector(7 downto 0) := X"00"; signal sim_spm1D : std_logic_vector(7 downto 0) := X"00"; signal sim_spm1E : std_logic_vector(7 downto 0) := X"00"; signal sim_spm1F : std_logic_vector(7 downto 0) := X"00"; signal sim_spm20 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm21 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm22 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm23 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm24 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm25 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm26 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm27 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm28 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm29 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm2A : std_logic_vector(7 downto 0) := X"00"; signal sim_spm2B : std_logic_vector(7 downto 0) := X"00"; signal sim_spm2C : std_logic_vector(7 downto 0) := X"00"; signal sim_spm2D : std_logic_vector(7 downto 0) := X"00"; signal sim_spm2E : std_logic_vector(7 downto 0) := X"00"; signal sim_spm2F : std_logic_vector(7 downto 0) := X"00"; signal sim_spm30 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm31 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm32 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm33 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm34 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm35 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm36 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm37 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm38 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm39 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm3A : std_logic_vector(7 downto 0) := X"00"; signal sim_spm3B : std_logic_vector(7 downto 0) := X"00"; signal sim_spm3C : std_logic_vector(7 downto 0) := X"00"; signal sim_spm3D : std_logic_vector(7 downto 0) := X"00"; signal sim_spm3E : std_logic_vector(7 downto 0) := X"00"; signal sim_spm3F : std_logic_vector(7 downto 0) := X"00"; signal sim_spm40 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm41 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm42 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm43 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm44 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm45 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm46 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm47 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm48 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm49 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm4A : std_logic_vector(7 downto 0) := X"00"; signal sim_spm4B : std_logic_vector(7 downto 0) := X"00"; signal sim_spm4C : std_logic_vector(7 downto 0) := X"00"; signal sim_spm4D : std_logic_vector(7 downto 0) := X"00"; signal sim_spm4E : std_logic_vector(7 downto 0) := X"00"; signal sim_spm4F : std_logic_vector(7 downto 0) := X"00"; signal sim_spm50 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm51 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm52 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm53 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm54 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm55 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm56 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm57 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm58 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm59 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm5A : std_logic_vector(7 downto 0) := X"00"; signal sim_spm5B : std_logic_vector(7 downto 0) := X"00"; signal sim_spm5C : std_logic_vector(7 downto 0) := X"00"; signal sim_spm5D : std_logic_vector(7 downto 0) := X"00"; signal sim_spm5E : std_logic_vector(7 downto 0) := X"00"; signal sim_spm5F : std_logic_vector(7 downto 0) := X"00"; signal sim_spm60 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm61 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm62 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm63 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm64 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm65 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm66 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm67 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm68 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm69 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm6A : std_logic_vector(7 downto 0) := X"00"; signal sim_spm6B : std_logic_vector(7 downto 0) := X"00"; signal sim_spm6C : std_logic_vector(7 downto 0) := X"00"; signal sim_spm6D : std_logic_vector(7 downto 0) := X"00"; signal sim_spm6E : std_logic_vector(7 downto 0) := X"00"; signal sim_spm6F : std_logic_vector(7 downto 0) := X"00"; signal sim_spm70 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm71 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm72 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm73 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm74 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm75 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm76 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm77 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm78 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm79 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm7A : std_logic_vector(7 downto 0) := X"00"; signal sim_spm7B : std_logic_vector(7 downto 0) := X"00"; signal sim_spm7C : std_logic_vector(7 downto 0) := X"00"; signal sim_spm7D : std_logic_vector(7 downto 0) := X"00"; signal sim_spm7E : std_logic_vector(7 downto 0) := X"00"; signal sim_spm7F : std_logic_vector(7 downto 0) := X"00"; signal sim_spm80 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm81 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm82 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm83 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm84 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm85 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm86 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm87 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm88 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm89 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm8A : std_logic_vector(7 downto 0) := X"00"; signal sim_spm8B : std_logic_vector(7 downto 0) := X"00"; signal sim_spm8C : std_logic_vector(7 downto 0) := X"00"; signal sim_spm8D : std_logic_vector(7 downto 0) := X"00"; signal sim_spm8E : std_logic_vector(7 downto 0) := X"00"; signal sim_spm8F : std_logic_vector(7 downto 0) := X"00"; signal sim_spm90 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm91 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm92 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm93 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm94 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm95 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm96 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm97 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm98 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm99 : std_logic_vector(7 downto 0) := X"00"; signal sim_spm9A : std_logic_vector(7 downto 0) := X"00"; signal sim_spm9B : std_logic_vector(7 downto 0) := X"00"; signal sim_spm9C : std_logic_vector(7 downto 0) := X"00"; signal sim_spm9D : std_logic_vector(7 downto 0) := X"00"; signal sim_spm9E : std_logic_vector(7 downto 0) := X"00"; signal sim_spm9F : std_logic_vector(7 downto 0) := X"00"; signal sim_spmA0 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmA1 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmA2 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmA3 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmA4 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmA5 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmA6 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmA7 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmA8 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmA9 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmAA : std_logic_vector(7 downto 0) := X"00"; signal sim_spmAB : std_logic_vector(7 downto 0) := X"00"; signal sim_spmAC : std_logic_vector(7 downto 0) := X"00"; signal sim_spmAD : std_logic_vector(7 downto 0) := X"00"; signal sim_spmAE : std_logic_vector(7 downto 0) := X"00"; signal sim_spmAF : std_logic_vector(7 downto 0) := X"00"; signal sim_spmB0 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmB1 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmB2 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmB3 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmB4 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmB5 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmB6 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmB7 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmB8 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmB9 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmBA : std_logic_vector(7 downto 0) := X"00"; signal sim_spmBB : std_logic_vector(7 downto 0) := X"00"; signal sim_spmBC : std_logic_vector(7 downto 0) := X"00"; signal sim_spmBD : std_logic_vector(7 downto 0) := X"00"; signal sim_spmBE : std_logic_vector(7 downto 0) := X"00"; signal sim_spmBF : std_logic_vector(7 downto 0) := X"00"; signal sim_spmC0 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmC1 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmC2 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmC3 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmC4 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmC5 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmC6 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmC7 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmC8 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmC9 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmCA : std_logic_vector(7 downto 0) := X"00"; signal sim_spmCB : std_logic_vector(7 downto 0) := X"00"; signal sim_spmCC : std_logic_vector(7 downto 0) := X"00"; signal sim_spmCD : std_logic_vector(7 downto 0) := X"00"; signal sim_spmCE : std_logic_vector(7 downto 0) := X"00"; signal sim_spmCF : std_logic_vector(7 downto 0) := X"00"; signal sim_spmD0 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmD1 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmD2 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmD3 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmD4 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmD5 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmD6 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmD7 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmD8 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmD9 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmDA : std_logic_vector(7 downto 0) := X"00"; signal sim_spmDB : std_logic_vector(7 downto 0) := X"00"; signal sim_spmDC : std_logic_vector(7 downto 0) := X"00"; signal sim_spmDD : std_logic_vector(7 downto 0) := X"00"; signal sim_spmDE : std_logic_vector(7 downto 0) := X"00"; signal sim_spmDF : std_logic_vector(7 downto 0) := X"00"; signal sim_spmE0 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmE1 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmE2 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmE3 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmE4 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmE5 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmE6 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmE7 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmE8 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmE9 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmEA : std_logic_vector(7 downto 0) := X"00"; signal sim_spmEB : std_logic_vector(7 downto 0) := X"00"; signal sim_spmEC : std_logic_vector(7 downto 0) := X"00"; signal sim_spmED : std_logic_vector(7 downto 0) := X"00"; signal sim_spmEE : std_logic_vector(7 downto 0) := X"00"; signal sim_spmEF : std_logic_vector(7 downto 0) := X"00"; signal sim_spmF0 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmF1 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmF2 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmF3 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmF4 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmF5 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmF6 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmF7 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmF8 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmF9 : std_logic_vector(7 downto 0) := X"00"; signal sim_spmFA : std_logic_vector(7 downto 0) := X"00"; signal sim_spmFB : std_logic_vector(7 downto 0) := X"00"; signal sim_spmFC : std_logic_vector(7 downto 0) := X"00"; signal sim_spmFD : std_logic_vector(7 downto 0) := X"00"; signal sim_spmFE : std_logic_vector(7 downto 0) := X"00"; signal sim_spmFF : std_logic_vector(7 downto 0) := X"00"; -- --synthesis translate on -- --********************************************************************************** -- -- ------------------------------------------------------------------------------------------- -- -- Attributes to guide mapping of logic into Slices. -- attribute hblknm : string; attribute hblknm of reset_lut : label is "kcpsm6_control"; attribute hblknm of run_flop : label is "kcpsm6_control"; attribute hblknm of internal_reset_flop : label is "kcpsm6_control"; attribute hblknm of t_state_lut : label is "kcpsm6_control"; attribute hblknm of t_state1_flop : label is "kcpsm6_control"; attribute hblknm of t_state2_flop : label is "kcpsm6_control"; attribute hblknm of active_interrupt_lut : label is "kcpsm6_control"; attribute hblknm of active_interrupt_flop : label is "kcpsm6_control"; attribute hblknm of sx_addr4_flop : label is "kcpsm6_control"; attribute hblknm of arith_carry_xorcy : label is "kcpsm6_control"; attribute hblknm of arith_carry_flop : label is "kcpsm6_control"; attribute hblknm of zero_flag_flop : label is "kcpsm6_flags"; attribute hblknm of carry_flag_flop : label is "kcpsm6_flags"; attribute hblknm of carry_flag_lut : label is "kcpsm6_flags"; attribute hblknm of lower_zero_lut : label is "kcpsm6_flags"; attribute hblknm of middle_zero_lut : label is "kcpsm6_flags"; attribute hblknm of upper_zero_lut : label is "kcpsm6_flags"; attribute hblknm of init_zero_muxcy : label is "kcpsm6_flags"; attribute hblknm of lower_zero_muxcy : label is "kcpsm6_flags"; attribute hblknm of middle_zero_muxcy : label is "kcpsm6_flags"; attribute hblknm of upper_zero_muxcy : label is "kcpsm6_flags"; attribute hblknm of int_enable_type_lut : label is "kcpsm6_decode0"; attribute hblknm of move_type_lut : label is "kcpsm6_decode0"; attribute hblknm of pc_move_is_valid_lut : label is "kcpsm6_decode0"; attribute hblknm of interrupt_enable_lut : label is "kcpsm6_decode0"; attribute hblknm of interrupt_enable_flop : label is "kcpsm6_decode0"; attribute hblknm of alu_decode1_lut : label is "kcpsm6_decode1"; attribute hblknm of alu_mux_sel1_flop : label is "kcpsm6_decode1"; attribute hblknm of shift_carry_lut : label is "kcpsm6_decode1"; attribute hblknm of shift_carry_flop : label is "kcpsm6_decode1"; attribute hblknm of use_zero_flag_lut : label is "kcpsm6_decode1"; attribute hblknm of use_zero_flag_flop : label is "kcpsm6_decode1"; attribute hblknm of interrupt_ack_flop : label is "kcpsm6_decode1"; attribute hblknm of shadow_zero_flag_flop : label is "kcpsm6_decode1"; attribute hblknm of alu_decode0_lut : label is "kcpsm6_decode2"; attribute hblknm of alu_mux_sel0_flop : label is "kcpsm6_decode2"; attribute hblknm of alu_decode2_lut : label is "kcpsm6_decode2"; attribute hblknm of lower_parity_lut : label is "kcpsm6_decode2"; attribute hblknm of parity_muxcy : label is "kcpsm6_decode2"; attribute hblknm of upper_parity_lut : label is "kcpsm6_decode2"; attribute hblknm of parity_xorcy : label is "kcpsm6_decode2"; attribute hblknm of sync_sleep_flop : label is "kcpsm6_decode2"; attribute hblknm of sync_interrupt_flop : label is "kcpsm6_decode2"; attribute hblknm of push_pop_lut : label is "kcpsm6_stack1"; attribute hblknm of regbank_type_lut : label is "kcpsm6_stack1"; attribute hblknm of bank_lut : label is "kcpsm6_stack1"; attribute hblknm of bank_flop : label is "kcpsm6_stack1"; attribute hblknm of register_enable_type_lut : label is "kcpsm6_strobes"; attribute hblknm of register_enable_lut : label is "kcpsm6_strobes"; attribute hblknm of flag_enable_flop : label is "kcpsm6_strobes"; attribute hblknm of register_enable_flop : label is "kcpsm6_strobes"; attribute hblknm of spm_enable_lut : label is "kcpsm6_strobes"; attribute hblknm of k_write_strobe_flop : label is "kcpsm6_strobes"; attribute hblknm of spm_enable_flop : label is "kcpsm6_strobes"; attribute hblknm of read_strobe_lut : label is "kcpsm6_strobes"; attribute hblknm of write_strobe_flop : label is "kcpsm6_strobes"; attribute hblknm of read_strobe_flop : label is "kcpsm6_strobes"; attribute hblknm of stack_ram_low : label is "kcpsm6_stack_ram0"; attribute hblknm of shadow_carry_flag_flop : label is "kcpsm6_stack_ram0"; attribute hblknm of stack_zero_flop : label is "kcpsm6_stack_ram0"; attribute hblknm of shadow_bank_flop : label is "kcpsm6_stack_ram0"; attribute hblknm of stack_bit_flop : label is "kcpsm6_stack_ram0"; attribute hblknm of stack_ram_high : label is "kcpsm6_stack_ram1"; attribute hblknm of lower_reg_banks : label is "kcpsm6_reg0"; attribute hblknm of upper_reg_banks : label is "kcpsm6_reg1"; attribute hblknm of pc_mode1_lut : label is "kcpsm6_vector1"; attribute hblknm of pc_mode2_lut : label is "kcpsm6_vector1"; -- ------------------------------------------------------------------------------------------- -- -- Start of kcpsm6 circuit description -- -- Summary of all primitives defined. -- -- 29 x LUT6 79 LUTs (plus 1 LUT will be required to form a GND signal) -- 50 x LUT6_2 -- 48 x FD 82 flip-flops -- 20 x FDR (Depending on the value of 'hwbuild' up) -- 0 x FDS (to eight FDR will be replaced by FDS ) -- 14 x FDRE -- 29 x MUXCY -- 27 x XORCY -- 4 x RAM32M (16 LUTs) -- -- 2 x RAM64M or 8 x RAM128X1S or 8 x RAM256X1S -- (8 LUTs) (16 LUTs) (32 LUTs) -- ------------------------------------------------------------------------------------------- -- begin -- ------------------------------------------------------------------------------------------- -- -- Perform check of generic to report error as soon as possible. -- ------------------------------------------------------------------------------------------- -- assert ((scratch_pad_memory_size = 64) or (scratch_pad_memory_size = 128) or (scratch_pad_memory_size = 256)) report "Invalid 'scratch_pad_memory_size'. Please set to 64, 128 or 256." severity FAILURE; -- ------------------------------------------------------------------------------------------- -- -- State Machine and Control -- -- -- 1 x LUT6 -- 4 x LUT6_2 -- 9 x FD -- ------------------------------------------------------------------------------------------- -- reset_lut: LUT6_2 generic map (INIT => X"FFFFF55500000EEE") port map( I0 => run, I1 => internal_reset, I2 => stack_pointer_carry(4), I3 => t_state(2), I4 => reset, I5 => '1', O5 => run_value, O6 => internal_reset_value); run_flop: FD port map ( D => run_value, Q => run, C => clk); internal_reset_flop: FD port map ( D => internal_reset_value, Q => internal_reset, C => clk); sync_sleep_flop: FD port map ( D => sleep, Q => sync_sleep, C => clk); t_state_lut: LUT6_2 generic map (INIT => X"0083000B00C4004C") port map( I0 => t_state(1), I1 => t_state(2), I2 => sync_sleep, I3 => internal_reset, I4 => special_bit, I5 => '1', O5 => t_state_value(1), O6 => t_state_value(2)); t_state1_flop: FD port map ( D => t_state_value(1), Q => t_state(1), C => clk); t_state2_flop: FD port map ( D => t_state_value(2), Q => t_state(2), C => clk); int_enable_type_lut: LUT6_2 generic map (INIT => X"0010000000000800") port map( I0 => instruction(13), I1 => instruction(14), I2 => instruction(15), I3 => instruction(16), I4 => instruction(17), I5 => '1', O5 => loadstar_type, O6 => int_enable_type); interrupt_enable_lut: LUT6 generic map (INIT => X"000000000000CAAA") port map( I0 => interrupt_enable, I1 => instruction(0), I2 => int_enable_type, I3 => t_state(1), I4 => active_interrupt, I5 => internal_reset, O => interrupt_enable_value); interrupt_enable_flop: FD port map ( D => interrupt_enable_value, Q => interrupt_enable, C => clk); sync_interrupt_flop: FD port map ( D => interrupt, Q => sync_interrupt, C => clk); active_interrupt_lut: LUT6_2 generic map (INIT => X"CC33FF0080808080") port map( I0 => interrupt_enable, I1 => t_state(2), I2 => sync_interrupt, I3 => bank, I4 => loadstar_type, I5 => '1', O5 => active_interrupt_value, O6 => sx_addr4_value); active_interrupt_flop: FD port map ( D => active_interrupt_value, Q => active_interrupt, C => clk); interrupt_ack_flop: FD port map ( D => active_interrupt, Q => interrupt_ack, C => clk); -- ------------------------------------------------------------------------------------------- -- -- Decoders -- -- -- 2 x LUT6 -- 10 x LUT6_2 -- 2 x FD -- 6 x FDR -- ------------------------------------------------------------------------------------------- -- -- -- Decoding for Program Counter and Stack -- pc_move_is_valid_lut: LUT6 generic map (INIT => X"5A3CFFFF00000000") port map( I0 => carry_flag, I1 => zero_flag, I2 => instruction(14), I3 => instruction(15), I4 => instruction(16), I5 => instruction(17), O => pc_move_is_valid); move_type_lut: LUT6_2 generic map (INIT => X"7777027700000200") port map( I0 => instruction(12), I1 => instruction(13), I2 => instruction(14), I3 => instruction(15), I4 => instruction(16), I5 => '1', O5 => returni_type, O6 => move_type); pc_mode1_lut: LUT6_2 generic map (INIT => X"0000F000000023FF") port map( I0 => instruction(12), I1 => returni_type, I2 => move_type, I3 => pc_move_is_valid, I4 => active_interrupt, I5 => '1', O5 => pc_mode(0), O6 => pc_mode(1)); pc_mode2_lut: LUT6 generic map (INIT => X"FFFFFFFF00040000") port map( I0 => instruction(12), I1 => instruction(14), I2 => instruction(15), I3 => instruction(16), I4 => instruction(17), I5 => active_interrupt, O => pc_mode(2)); push_pop_lut: LUT6_2 generic map (INIT => X"FFFF100000002000") port map( I0 => instruction(12), I1 => instruction(13), I2 => move_type, I3 => pc_move_is_valid, I4 => active_interrupt, I5 => '1', O5 => pop_stack, O6 => push_stack); -- -- Decoding for ALU -- alu_decode0_lut: LUT6_2 generic map (INIT => X"03CA000004200000") port map( I0 => instruction(13), I1 => instruction(14), I2 => instruction(15), I3 => instruction(16), I4 => '1', I5 => '1', O5 => alu_mux_sel_value(0), O6 => arith_logical_sel(0)); alu_mux_sel0_flop: FD port map ( D => alu_mux_sel_value(0), Q => alu_mux_sel(0), C => clk); alu_decode1_lut: LUT6_2 generic map (INIT => X"7708000000000F00") port map( I0 => carry_flag, I1 => instruction(13), I2 => instruction(14), I3 => instruction(15), I4 => instruction(16), I5 => '1', O5 => alu_mux_sel_value(1), O6 => arith_carry_in); alu_mux_sel1_flop: FD port map ( D => alu_mux_sel_value(1), Q => alu_mux_sel(1), C => clk); alu_decode2_lut: LUT6_2 generic map (INIT => X"D000000002000000") port map( I0 => instruction(14), I1 => instruction(15), I2 => instruction(16), I3 => '1', I4 => '1', I5 => '1', O5 => arith_logical_sel(1), O6 => arith_logical_sel(2)); -- -- Decoding for strobes and enables -- register_enable_type_lut: LUT6_2 generic map (INIT => X"00013F3F0010F7CE") port map( I0 => instruction(13), I1 => instruction(14), I2 => instruction(15), I3 => instruction(16), I4 => instruction(17), I5 => '1', O5 => flag_enable_type, O6 => register_enable_type); register_enable_lut: LUT6_2 generic map (INIT => X"C0CC0000A0AA0000") port map( I0 => flag_enable_type, I1 => register_enable_type, I2 => instruction(12), I3 => instruction(17), I4 => t_state(1), I5 => '1', O5 => flag_enable_value, O6 => register_enable_value); flag_enable_flop: FDR port map ( D => flag_enable_value, Q => flag_enable, R => active_interrupt, C => clk); register_enable_flop: FDR port map ( D => register_enable_value, Q => register_enable, R => active_interrupt, C => clk); spm_enable_lut: LUT6_2 generic map (INIT => X"8000000020000000") port map( I0 => instruction(13), I1 => instruction(14), I2 => instruction(17), I3 => strobe_type, I4 => t_state(1), I5 => '1', O5 => k_write_strobe_value, O6 => spm_enable_value); k_write_strobe_flop: FDR port map ( D => k_write_strobe_value, Q => k_write_strobe, R => active_interrupt, C => clk); spm_enable_flop: FDR port map ( D => spm_enable_value, Q => spm_enable, R => active_interrupt, C => clk); read_strobe_lut: LUT6_2 generic map (INIT => X"4000000001000000") port map( I0 => instruction(13), I1 => instruction(14), I2 => instruction(17), I3 => strobe_type, I4 => t_state(1), I5 => '1', O5 => read_strobe_value, O6 => write_strobe_value); write_strobe_flop: FDR port map ( D => write_strobe_value, Q => write_strobe, R => active_interrupt, C => clk); read_strobe_flop: FDR port map ( D => read_strobe_value, Q => read_strobe, R => active_interrupt, C => clk); -- ------------------------------------------------------------------------------------------- -- -- Register bank control -- -- -- 2 x LUT6 -- 1 x FDR -- 1 x FD -- ------------------------------------------------------------------------------------------- -- regbank_type_lut: LUT6 generic map (INIT => X"0080020000000000") port map( I0 => instruction(12), I1 => instruction(13), I2 => instruction(14), I3 => instruction(15), I4 => instruction(16), I5 => instruction(17), O => regbank_type); bank_lut: LUT6 generic map (INIT => X"ACACFF00FF00FF00") port map( I0 => instruction(0), I1 => shadow_bank, I2 => instruction(16), I3 => bank, I4 => regbank_type, I5 => t_state(1), O => bank_value); bank_flop: FDR port map ( D => bank_value, Q => bank, R => internal_reset, C => clk); sx_addr4_flop: FD port map ( D => sx_addr4_value, Q => sx_addr(4), C => clk); sx_addr(3 downto 0) <= instruction(11 downto 8); sy_addr <= bank & instruction(7 downto 4); -- ------------------------------------------------------------------------------------------- -- -- Flags -- -- -- 3 x LUT6 -- 5 x LUT6_2 -- 3 x FD -- 2 x FDRE -- 2 x XORCY -- 5 x MUXCY -- ------------------------------------------------------------------------------------------- -- arith_carry_xorcy: XORCY port map( LI => '0', CI => carry_arith_logical(7), O => arith_carry_value); arith_carry_flop: FD port map ( D => arith_carry_value, Q => arith_carry, C => clk); lower_parity_lut: LUT6_2 generic map (INIT => X"0000000087780000") port map( I0 => instruction(13), I1 => carry_flag, I2 => arith_logical_result(0), I3 => arith_logical_result(1), I4 => '1', I5 => '1', O5 => lower_parity, O6 => lower_parity_sel); parity_muxcy: MUXCY port map( DI => lower_parity, CI => '0', S => lower_parity_sel, O => carry_lower_parity); upper_parity_lut: LUT6 generic map (INIT => X"6996966996696996") port map( I0 => arith_logical_result(2), I1 => arith_logical_result(3), I2 => arith_logical_result(4), I3 => arith_logical_result(5), I4 => arith_logical_result(6), I5 => arith_logical_result(7), O => upper_parity); parity_xorcy: XORCY port map( LI => upper_parity, CI => carry_lower_parity, O => parity); shift_carry_lut: LUT6 generic map (INIT => X"FFFFAACCF0F0F0F0") port map( I0 => sx(0), I1 => sx(7), I2 => shadow_carry_flag, I3 => instruction(3), I4 => instruction(7), I5 => instruction(16), O => shift_carry_value); shift_carry_flop: FD port map ( D => shift_carry_value, Q => shift_carry, C => clk); carry_flag_lut: LUT6_2 generic map (INIT => X"3333AACCF0AA0000") port map( I0 => shift_carry, I1 => arith_carry, I2 => parity, I3 => instruction(14), I4 => instruction(15), I5 => instruction(16), O5 => drive_carry_in_zero, O6 => carry_flag_value); carry_flag_flop: FDRE port map ( D => carry_flag_value, Q => carry_flag, CE => flag_enable, R => internal_reset, C => clk); init_zero_muxcy: MUXCY port map( DI => drive_carry_in_zero, CI => '0', S => carry_flag_value, O => carry_in_zero); use_zero_flag_lut: LUT6_2 generic map (INIT => X"A280000000F000F0") port map( I0 => instruction(13), I1 => instruction(14), I2 => instruction(15), I3 => instruction(16), I4 => '1', I5 => '1', O5 => strobe_type, O6 => use_zero_flag_value); use_zero_flag_flop: FD port map ( D => use_zero_flag_value, Q => use_zero_flag, C => clk); lower_zero_lut: LUT6_2 generic map (INIT => X"0000000000000001") port map( I0 => alu_result(0), I1 => alu_result(1), I2 => alu_result(2), I3 => alu_result(3), I4 => alu_result(4), I5 => '1', O5 => lower_zero, O6 => lower_zero_sel); lower_zero_muxcy: MUXCY port map( DI => lower_zero, CI => carry_in_zero, S => lower_zero_sel, O => carry_lower_zero); middle_zero_lut: LUT6_2 generic map (INIT => X"0000000D00000000") port map( I0 => use_zero_flag, I1 => zero_flag, I2 => alu_result(5), I3 => alu_result(6), I4 => alu_result(7), I5 => '1', O5 => middle_zero, O6 => middle_zero_sel); middle_zero_muxcy: MUXCY port map( DI => middle_zero, CI => carry_lower_zero, S => middle_zero_sel, O => carry_middle_zero); upper_zero_lut: LUT6 generic map (INIT => X"FBFF000000000000") port map( I0 => instruction(14), I1 => instruction(15), I2 => instruction(16), I3 => '1', I4 => '1', I5 => '1', O => upper_zero_sel); upper_zero_muxcy: MUXCY port map( DI => shadow_zero_flag, CI => carry_middle_zero, S => upper_zero_sel, O => zero_flag_value); zero_flag_flop: FDRE port map ( D => zero_flag_value, Q => zero_flag, CE => flag_enable, R => internal_reset, C => clk); -- ------------------------------------------------------------------------------------------- -- -- 12-bit Program Address Generation -- ------------------------------------------------------------------------------------------- -- -- -- Prepare 12-bit vector from the sX and sY register outputs. -- register_vector <= sx(3 downto 0) & sy; address_loop: for i in 0 to 11 generate attribute hblknm : string; attribute hblknm of pc_flop : label is "kcpsm6_pc" & integer'image(i/4); attribute hblknm of return_vector_flop : label is "kcpsm6_stack_ram" & integer'image((i+4)/8); begin -- ------------------------------------------------------------------------------------------- -- -- Selection of vector to load program counter -- -- instruction(12) -- 0 Constant aaa from instruction(11:0) -- 1 Return vector from stack -- -- 'aaa' is used during 'JUMP aaa', 'JUMP c, aaa', 'CALL aaa' and 'CALL c, aaa'. -- Return vector is used during 'RETURN', 'RETURN c', 'RETURN&LOAD' and 'RETURNI'. -- -- 6 x LUT6_2 -- 12 x FD -- ------------------------------------------------------------------------------------------- -- -- -- Pipeline output of the stack memory -- return_vector_flop: FD port map ( D => stack_memory(i), Q => return_vector(i), C => clk); -- -- Multiplex instruction constant address and output from stack. -- 2 bits per LUT so only generate when 'i' is even. -- output_data: if (i rem 2)=0 generate attribute hblknm : string; attribute hblknm of pc_vector_mux_lut : label is "kcpsm6_vector" & integer'image(i/8); begin pc_vector_mux_lut: LUT6_2 generic map (INIT => X"FF00F0F0CCCCAAAA") port map( I0 => instruction(i), I1 => return_vector(i), I2 => instruction(i+1), I3 => return_vector(i+1), I4 => instruction(12), I5 => '1', O5 => pc_vector(i), O6 => pc_vector(i+1)); end generate output_data; -- ------------------------------------------------------------------------------------------- -- -- Program Counter -- -- Reset by internal_reset has highest priority. -- Enabled by t_state(1) has second priority. -- -- The function performed is defined by pc_mode(2:0). -- -- pc_mode (2) (1) (0) -- 0 0 1 pc+1 for normal program flow. -- 1 0 0 Forces interrupt vector value (+0) during active interrupt. -- The vector is defined by a generic with default value FF0 hex. -- 1 1 0 register_vector (+0) for 'JUMP (sX, sY)' and 'CALL (sX, sY)'. -- 0 1 0 pc_vector (+0) for 'JUMP/CALL aaa' and 'RETURNI'. -- 0 1 1 pc_vector+1 for 'RETURN'. -- -- Note that pc_mode(0) is High during operations that require an increment to occur. -- The LUT6 associated with the LSB must invert pc or pc_vector in these cases and -- pc_mode(0) also has to be connected to the start of the carry chain. -- -- 3 Slices -- 12 x LUT6 -- 11 x MUXCY -- 12 x XORCY -- 12 x FDRE -- ------------------------------------------------------------------------------------------- -- pc_flop: FDRE port map ( D => pc_value(i), Q => pc(i), R => internal_reset, CE => t_state(1), C => clk); lsb_pc: if i=0 generate attribute hblknm : string; attribute hblknm of pc_xorcy : label is "kcpsm6_pc" & integer'image(i/4); attribute hblknm of pc_muxcy : label is "kcpsm6_pc" & integer'image(i/4); begin -- -- Logic of LSB must invert selected value when pc_mode(0) is High. -- The interrupt vector is defined by a generic. -- low_int_vector: if interrupt_vector(i)='0' generate attribute hblknm : string; attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4); begin pc_lut: LUT6 generic map (INIT => X"00AA000033CC0F00") port map( I0 => register_vector(i), I1 => pc_vector(i), I2 => pc(i), I3 => pc_mode(0), I4 => pc_mode(1), I5 => pc_mode(2), O => half_pc(i)); end generate low_int_vector; high_int_vector: if interrupt_vector(i)='1' generate attribute hblknm : string; attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4); begin pc_lut: LUT6 generic map (INIT => X"00AA00FF33CC0F00") port map( I0 => register_vector(i), I1 => pc_vector(i), I2 => pc(i), I3 => pc_mode(0), I4 => pc_mode(1), I5 => pc_mode(2), O => half_pc(i)); end generate high_int_vector; -- -- pc_mode(0) connected to first MUXCY and carry input is '0' -- pc_xorcy: XORCY port map( LI => half_pc(i), CI => '0', O => pc_value(i)); pc_muxcy: MUXCY port map( DI => pc_mode(0), CI => '0', S => half_pc(i), O => carry_pc(i)); end generate lsb_pc; upper_pc: if i>0 generate attribute hblknm : string; attribute hblknm of pc_xorcy : label is "kcpsm6_pc" & integer'image(i/4); begin -- -- Logic of upper section selects required value. -- The interrupt vector is defined by a generic. -- low_int_vector: if interrupt_vector(i)='0' generate attribute hblknm : string; attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4); begin pc_lut: LUT6 generic map (INIT => X"00AA0000CCCCF000") port map( I0 => register_vector(i), I1 => pc_vector(i), I2 => pc(i), I3 => pc_mode(0), I4 => pc_mode(1), I5 => pc_mode(2), O => half_pc(i)); end generate low_int_vector; high_int_vector: if interrupt_vector(i)='1' generate attribute hblknm : string; attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4); begin pc_lut: LUT6 generic map (INIT => X"00AA00FFCCCCF000") port map( I0 => register_vector(i), I1 => pc_vector(i), I2 => pc(i), I3 => pc_mode(0), I4 => pc_mode(1), I5 => pc_mode(2), O => half_pc(i)); end generate high_int_vector; -- -- Carry chain implementing remainder of increment function -- pc_xorcy: XORCY port map( LI => half_pc(i), CI => carry_pc(i-1), O => pc_value(i)); -- -- No MUXCY required at the top of the chain -- mid_pc: if i<11 generate attribute hblknm : string; attribute hblknm of pc_muxcy : label is "kcpsm6_pc" & integer'image(i/4); begin pc_muxcy: MUXCY port map( DI => '0', CI => carry_pc(i-1), S => half_pc(i), O => carry_pc(i)); end generate mid_pc; end generate upper_pc; -- ------------------------------------------------------------------------------------------- -- end generate address_loop; -- ------------------------------------------------------------------------------------------- -- -- Stack -- Preserves upto 31 nested values of the Program Counter during CALL and RETURN. -- Also preserves flags and bank selection during interrupt. -- -- 2 x RAM32M -- 4 x FD -- 5 x FDR -- 1 x LUT6 -- 4 x LUT6_2 -- 5 x XORCY -- 5 x MUXCY -- ------------------------------------------------------------------------------------------- -- shadow_carry_flag_flop: FD port map ( D => stack_carry_flag, Q => shadow_carry_flag, C => clk); stack_zero_flop: FD port map ( D => stack_zero_flag, Q => shadow_zero_value, C => clk); shadow_zero_flag_flop: FD port map ( D => shadow_zero_value, Q => shadow_zero_flag, C => clk); shadow_bank_flop: FD port map ( D => stack_bank, Q => shadow_bank, C => clk); stack_bit_flop: FD port map ( D => stack_bit, Q => special_bit, C => clk); stack_ram_low : RAM32M generic map (INIT_A => X"0000000000000000", INIT_B => X"0000000000000000", INIT_C => X"0000000000000000", INIT_D => X"0000000000000000") port map ( DOA(0) => stack_carry_flag, DOA(1) => stack_zero_flag, DOB(0) => stack_bank, DOB(1) => stack_bit, DOC => stack_memory(1 downto 0), DOD => stack_memory(3 downto 2), ADDRA => stack_pointer(4 downto 0), ADDRB => stack_pointer(4 downto 0), ADDRC => stack_pointer(4 downto 0), ADDRD => stack_pointer(4 downto 0), DIA(0) => carry_flag, DIA(1) => zero_flag, DIB(0) => bank, DIB(1) => run, DIC => pc(1 downto 0), DID => pc(3 downto 2), WE => t_state(1), WCLK => clk ); stack_ram_high : RAM32M generic map (INIT_A => X"0000000000000000", INIT_B => X"0000000000000000", INIT_C => X"0000000000000000", INIT_D => X"0000000000000000") port map ( DOA => stack_memory(5 downto 4), DOB => stack_memory(7 downto 6), DOC => stack_memory(9 downto 8), DOD => stack_memory(11 downto 10), ADDRA => stack_pointer(4 downto 0), ADDRB => stack_pointer(4 downto 0), ADDRC => stack_pointer(4 downto 0), ADDRD => stack_pointer(4 downto 0), DIA => pc(5 downto 4), DIB => pc(7 downto 6), DIC => pc(9 downto 8), DID => pc(11 downto 10), WE => t_state(1), WCLK => clk ); stack_loop: for i in 0 to 4 generate begin lsb_stack: if i=0 generate attribute hblknm : string; attribute hblknm of pointer_flop : label is "kcpsm6_stack" & integer'image(i/4); attribute hblknm of stack_pointer_lut : label is "kcpsm6_stack" & integer'image(i/4); attribute hblknm of stack_xorcy : label is "kcpsm6_stack" & integer'image(i/4); attribute hblknm of stack_muxcy : label is "kcpsm6_stack" & integer'image(i/4); begin pointer_flop: FDR port map ( D => stack_pointer_value(i), Q => stack_pointer(i), R => internal_reset, C => clk); stack_pointer_lut: LUT6_2 generic map (INIT => X"001529AAAAAAAAAA") port map( I0 => stack_pointer(i), I1 => pop_stack, I2 => push_stack, I3 => t_state(1), I4 => t_state(2), I5 => '1', O5 => feed_pointer_value(i), O6 => half_pointer_value(i)); stack_xorcy: XORCY port map( LI => half_pointer_value(i), CI => '0', O => stack_pointer_value(i)); stack_muxcy: MUXCY port map( DI => feed_pointer_value(i), CI => '0', S => half_pointer_value(i), O => stack_pointer_carry(i)); end generate lsb_stack; upper_stack: if i>0 generate attribute hblknm : string; attribute hblknm of pointer_flop : label is "kcpsm6_stack" & integer'image(i/4); attribute hblknm of stack_pointer_lut : label is "kcpsm6_stack" & integer'image(i/4); attribute hblknm of stack_xorcy : label is "kcpsm6_stack" & integer'image(i/4); attribute hblknm of stack_muxcy : label is "kcpsm6_stack" & integer'image(i/4); begin pointer_flop: FDR port map ( D => stack_pointer_value(i), Q => stack_pointer(i), R => internal_reset, C => clk); stack_pointer_lut: LUT6_2 generic map (INIT => X"002A252AAAAAAAAA") port map( I0 => stack_pointer(i), I1 => pop_stack, I2 => push_stack, I3 => t_state(1), I4 => t_state(2), I5 => '1', O5 => feed_pointer_value(i), O6 => half_pointer_value(i)); stack_xorcy: XORCY port map( LI => half_pointer_value(i), CI => stack_pointer_carry(i-1), O => stack_pointer_value(i)); stack_muxcy: MUXCY port map( DI => feed_pointer_value(i), CI => stack_pointer_carry(i-1), S => half_pointer_value(i), O => stack_pointer_carry(i)); end generate upper_stack; end generate stack_loop; -- ------------------------------------------------------------------------------------------- -- -- 8-bit Data Path -- ------------------------------------------------------------------------------------------- -- data_path_loop: for i in 0 to 7 generate attribute hblknm : string; attribute hblknm of arith_logical_lut : label is "kcpsm6_add" & integer'image(i/4); attribute hblknm of arith_logical_flop : label is "kcpsm6_add" & integer'image(i/4); attribute hblknm of alu_mux_lut : label is "kcpsm6_alu" & integer'image(i/4); begin -- ------------------------------------------------------------------------------------------- -- -- Selection of second operand to ALU and port_id -- -- instruction(12) -- 0 Register sY -- 1 Constant kk -- -- 4 x LUT6_2 -- ------------------------------------------------------------------------------------------- -- -- -- 2 bits per LUT so only generate when 'i' is even -- output_data: if (i rem 2)=0 generate attribute hblknm : string; attribute hblknm of sy_kk_mux_lut : label is "kcpsm6_port_id"; begin sy_kk_mux_lut: LUT6_2 generic map (INIT => X"FF00F0F0CCCCAAAA") port map( I0 => sy(i), I1 => instruction(i), I2 => sy(i+1), I3 => instruction(i+1), I4 => instruction(12), I5 => '1', O5 => sy_or_kk(i), O6 => sy_or_kk(i+1)); end generate output_data; -- ------------------------------------------------------------------------------------------- -- -- Selection of out_port value -- -- instruction(13) -- 0 Register sX -- 1 Constant kk from instruction(11:4) -- -- 4 x LUT6_2 -- ------------------------------------------------------------------------------------------- -- -- -- 2 bits per LUT so only generate when 'i' is even -- second_operand: if (i rem 2)=0 generate attribute hblknm : string; attribute hblknm of out_port_lut : label is "kcpsm6_out_port"; begin out_port_lut: LUT6_2 generic map (INIT => X"FF00F0F0CCCCAAAA") port map( I0 => sx(i), I1 => instruction(i+4), I2 => sx(i+1), I3 => instruction(i+5), I4 => instruction(13), I5 => '1', O5 => out_port(i), O6 => out_port(i+1)); end generate second_operand; -- ------------------------------------------------------------------------------------------- -- -- Arithmetic and Logical operations -- -- Definition of.... -- ADD and SUB also used for ADDCY, SUBCY, COMPARE and COMPARECY. -- LOAD, AND, OR and XOR also used for LOAD*, RETURN&LOAD, TEST and TESTCY. -- -- arith_logical_sel (2) (1) (0) -- 0 0 0 - LOAD -- 0 0 1 - AND -- 0 1 0 - OR -- 0 1 1 - XOR -- 1 X 0 - SUB -- 1 X 1 - ADD -- -- Includes pipeline stage. -- -- 2 Slices -- 8 x LUT6_2 -- 8 x MUXCY -- 8 x XORCY -- 8 x FD -- ------------------------------------------------------------------------------------------- -- arith_logical_lut: LUT6_2 generic map (INIT => X"69696E8ACCCC0000") port map( I0 => sy_or_kk(i), I1 => sx(i), I2 => arith_logical_sel(0), I3 => arith_logical_sel(1), I4 => arith_logical_sel(2), I5 => '1', O5 => logical_carry_mask(i), O6 => half_arith_logical(i)); arith_logical_flop: FD port map ( D => arith_logical_value(i), Q => arith_logical_result(i), C => clk); lsb_arith_logical: if i=0 generate attribute hblknm : string; attribute hblknm of arith_logical_muxcy : label is "kcpsm6_add" & integer'image(i/4); attribute hblknm of arith_logical_xorcy : label is "kcpsm6_add" & integer'image(i/4); begin -- -- Carry input to first MUXCY and XORCY -- arith_logical_muxcy: MUXCY port map( DI => logical_carry_mask(i), CI => arith_carry_in, S => half_arith_logical(i), O => carry_arith_logical(i)); arith_logical_xorcy: XORCY port map( LI => half_arith_logical(i), CI => arith_carry_in, O => arith_logical_value(i)); end generate lsb_arith_logical; upper_arith_logical: if i>0 generate attribute hblknm : string; attribute hblknm of arith_logical_muxcy : label is "kcpsm6_add" & integer'image(i/4); attribute hblknm of arith_logical_xorcy : label is "kcpsm6_add" & integer'image(i/4); begin -- -- Main carry chain -- arith_logical_muxcy: MUXCY port map( DI => logical_carry_mask(i), CI => carry_arith_logical(i-1), S => half_arith_logical(i), O => carry_arith_logical(i)); arith_logical_xorcy: XORCY port map( LI => half_arith_logical(i), CI => carry_arith_logical(i-1), O => arith_logical_value(i)); end generate upper_arith_logical; -- ------------------------------------------------------------------------------------------- -- -- Shift and Rotate operations -- -- Definition of SL0, SL1, SLX, SLA, RL, SR0, SR1, SRX, SRA, and RR -- -- instruction (3) (2) (1) (0) -- 0 1 1 0 - SL0 -- 0 1 1 1 - SL1 -- 0 1 0 0 - SLX -- 0 0 0 0 - SLA -- 0 0 1 0 - RL -- 1 1 1 0 - SR0 -- 1 1 1 1 - SR1 -- 1 0 1 0 - SRX -- 1 0 0 0 - SRA -- 1 1 0 0 - RR -- -- instruction(3) -- 0 - Left -- 1 - Right -- -- instruction (2) (1) Bit shifted in -- 0 0 Carry_flag -- 0 1 sX(7) -- 1 0 sX(0) -- 1 1 instruction(0) -- -- Includes pipeline stage. -- -- 4 x LUT6_2 -- 1 x LUT6 -- 8 x FD -- ------------------------------------------------------------------------------------------- -- low_hwbuild: if hwbuild(i)='0' generate attribute hblknm : string; attribute hblknm of shift_rotate_flop : label is "kcpsm6_sandr"; begin -- -- Reset Flip-flop to form '0' for this bit of HWBUILD -- shift_rotate_flop: FDR port map ( D => shift_rotate_value(i), Q => shift_rotate_result(i), R => instruction(7), C => clk); end generate low_hwbuild; high_hwbuild: if hwbuild(i)='1' generate attribute hblknm : string; attribute hblknm of shift_rotate_flop : label is "kcpsm6_sandr"; begin -- -- Set Flip-flop to form '1' for this bit of HWBUILD -- shift_rotate_flop: FDS port map ( D => shift_rotate_value(i), Q => shift_rotate_result(i), S => instruction(7), C => clk); end generate high_hwbuild; lsb_shift_rotate: if i=0 generate attribute hblknm : string; attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr"; attribute hblknm of shift_bit_lut : label is "kcpsm6_decode1"; begin -- -- Select bit to be shifted or rotated into result -- shift_bit_lut: LUT6 generic map (INIT => X"BFBC8F8CB3B08380") port map( I0 => instruction(0), I1 => instruction(1), I2 => instruction(2), I3 => carry_flag, I4 => sx(0), I5 => sx(7), O => shift_in_bit); -- -- Define lower bits of result -- shift_rotate_lut: LUT6_2 generic map (INIT => X"FF00F0F0CCCCAAAA") port map( I0 => shift_in_bit, I1 => sx(i+1), I2 => sx(i), I3 => sx(i+2), I4 => instruction(3), I5 => '1', O5 => shift_rotate_value(i), O6 => shift_rotate_value(i+1)); end generate lsb_shift_rotate; mid_shift_rotate: if i=2 or i=4 generate attribute hblknm : string; attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr"; begin -- -- Define middle bits of result -- shift_rotate_lut: LUT6_2 generic map (INIT => X"FF00F0F0CCCCAAAA") port map( I0 => sx(i-1), I1 => sx(i+1), I2 => sx(i), I3 => sx(i+2), I4 => instruction(3), I5 => '1', O5 => shift_rotate_value(i), O6 => shift_rotate_value(i+1)); end generate mid_shift_rotate; msb_shift_rotate: if i=6 generate attribute hblknm : string; attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr"; begin -- -- Define upper bits of result -- shift_rotate_lut: LUT6_2 generic map (INIT => X"FF00F0F0CCCCAAAA") port map( I0 => sx(i-1), I1 => sx(i+1), I2 => sx(i), I3 => shift_in_bit, I4 => instruction(3), I5 => '1', O5 => shift_rotate_value(i), O6 => shift_rotate_value(i+1)); end generate msb_shift_rotate; -- ------------------------------------------------------------------------------------------- -- -- Multiplex outputs from ALU functions, scratch pad memory and input port. -- -- alu_mux_sel (1) (0) -- 0 0 Arithmetic and Logical Instructions -- 0 1 Shift and Rotate Instructions -- 1 0 Input Port -- 1 1 Scratch Pad Memory -- -- 8 x LUT6 -- ------------------------------------------------------------------------------------------- -- alu_mux_lut: LUT6 generic map (INIT => X"FF00F0F0CCCCAAAA") port map( I0 => arith_logical_result(i), I1 => shift_rotate_result(i), I2 => in_port(i), I3 => spm_data(i), I4 => alu_mux_sel(0), I5 => alu_mux_sel(1), O => alu_result(i)); -- ------------------------------------------------------------------------------------------- -- -- Scratchpad Memory with output register. -- -- The size of the scratch pad memory is defined by the 'scratch_pad_memory_size' generic. -- The default size is 64 bytes the same as KCPSM3 but this can be increased to 128 or 256 -- bytes at an additional cost of 2 and 6 Slices. -- -- -- 8 x RAM256X1S (256 bytes). -- 8 x RAM128X1S (128 bytes). -- 2 x RAM64M (64 bytes). -- -- 8 x FD. -- ------------------------------------------------------------------------------------------- -- small_spm: if scratch_pad_memory_size = 64 generate attribute hblknm : string; attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i/4); begin spm_flop: FD port map ( D => spm_ram_data(i), Q => spm_data(i), C => clk); small_spm_ram: if (i=0 or i=4) generate attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i/4); begin spm_ram: RAM64M generic map ( INIT_A => X"0000000000000000", INIT_B => X"0000000000000000", INIT_C => X"0000000000000000", INIT_D => X"0000000000000000") port map ( DOA => spm_ram_data(i), DOB => spm_ram_data(i+1), DOC => spm_ram_data(i+2), DOD => spm_ram_data(i+3), ADDRA => sy_or_kk(5 downto 0), ADDRB => sy_or_kk(5 downto 0), ADDRC => sy_or_kk(5 downto 0), ADDRD => sy_or_kk(5 downto 0), DIA => sx(i), DIB => sx(i+1), DIC => sx(i+2), DID => sx(i+3), WE => spm_enable, WCLK => clk ); end generate small_spm_ram; end generate small_spm; medium_spm: if scratch_pad_memory_size = 128 generate attribute hblknm : string; attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i/2); attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i/2); begin spm_ram: RAM128X1S generic map(INIT => X"00000000000000000000000000000000") port map ( D => sx(i), WE => spm_enable, WCLK => clk, A0 => sy_or_kk(0), A1 => sy_or_kk(1), A2 => sy_or_kk(2), A3 => sy_or_kk(3), A4 => sy_or_kk(4), A5 => sy_or_kk(5), A6 => sy_or_kk(6), O => spm_ram_data(i)); spm_flop: FD port map ( D => spm_ram_data(i), Q => spm_data(i), C => clk); end generate medium_spm; large_spm: if scratch_pad_memory_size = 256 generate attribute hblknm : string; attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i); attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i); begin spm_ram: RAM256X1S generic map(INIT => X"0000000000000000000000000000000000000000000000000000000000000000") port map ( D => sx(i), WE => spm_enable, WCLK => clk, A => sy_or_kk, O => spm_ram_data(i)); spm_flop: FD port map ( D => spm_ram_data(i), Q => spm_data(i), C => clk); end generate large_spm; -- ------------------------------------------------------------------------------------------- -- end generate data_path_loop; -- ------------------------------------------------------------------------------------------- -- -- Two Banks of 16 General Purpose Registers. -- -- sx_addr - Address for sX is formed by bank select and instruction[11:8] -- sy_addr - Address for sY is formed by bank select and instruction[7:4] -- -- 2 Slices -- 2 x RAM32M -- ------------------------------------------------------------------------------------------- -- lower_reg_banks : RAM32M generic map (INIT_A => X"0000000000000000", INIT_B => X"0000000000000000", INIT_C => X"0000000000000000", INIT_D => X"0000000000000000") port map ( DOA => sy(1 downto 0), DOB => sx(1 downto 0), DOC => sy(3 downto 2), DOD => sx(3 downto 2), ADDRA => sy_addr, ADDRB => sx_addr, ADDRC => sy_addr, ADDRD => sx_addr, DIA => alu_result(1 downto 0), DIB => alu_result(1 downto 0), DIC => alu_result(3 downto 2), DID => alu_result(3 downto 2), WE => register_enable, WCLK => clk ); upper_reg_banks : RAM32M generic map (INIT_A => X"0000000000000000", INIT_B => X"0000000000000000", INIT_C => X"0000000000000000", INIT_D => X"0000000000000000") port map ( DOA => sy(5 downto 4), DOB => sx(5 downto 4), DOC => sy(7 downto 6), DOD => sx(7 downto 6), ADDRA => sy_addr, ADDRB => sx_addr, ADDRC => sy_addr, ADDRD => sx_addr, DIA => alu_result(5 downto 4), DIB => alu_result(5 downto 4), DIC => alu_result(7 downto 6), DID => alu_result(7 downto 6), WE => register_enable, WCLK => clk ); -- ------------------------------------------------------------------------------------------- -- -- Connections to KCPSM6 outputs. -- ------------------------------------------------------------------------------------------- -- address <= pc; bram_enable <= t_state(2); -- ------------------------------------------------------------------------------------------- -- -- Connections KCPSM6 Outputs. -- ------------------------------------------------------------------------------------------- -- port_id <= sy_or_kk; -- ------------------------------------------------------------------------------------------- -- -- End of description for kcpsm6 macro. -- ------------------------------------------------------------------------------------------- -- -- ***************************************************** -- * Code for simulation purposes only after this line * -- ***************************************************** -- -- -- Disassemble the instruction codes to form a text string for display. -- Determine status of reset and flags and present in the form of a text string. -- Provide signals to simulate the contents of each register and scratch pad memory -- location. -- ------------------------------------------------------------------------------------------- -- --All of this section is ignored during synthesis. --synthesis translate off simulation: process (clk, instruction, carry_flag, zero_flag, bank, interrupt_enable) -- -- Variables for contents of each register in each bank -- variable bank_a_s0 : std_logic_vector(7 downto 0) := X"00"; variable bank_a_s1 : std_logic_vector(7 downto 0) := X"00"; variable bank_a_s2 : std_logic_vector(7 downto 0) := X"00"; variable bank_a_s3 : std_logic_vector(7 downto 0) := X"00"; variable bank_a_s4 : std_logic_vector(7 downto 0) := X"00"; variable bank_a_s5 : std_logic_vector(7 downto 0) := X"00"; variable bank_a_s6 : std_logic_vector(7 downto 0) := X"00"; variable bank_a_s7 : std_logic_vector(7 downto 0) := X"00"; variable bank_a_s8 : std_logic_vector(7 downto 0) := X"00"; variable bank_a_s9 : std_logic_vector(7 downto 0) := X"00"; variable bank_a_sa : std_logic_vector(7 downto 0) := X"00"; variable bank_a_sb : std_logic_vector(7 downto 0) := X"00"; variable bank_a_sc : std_logic_vector(7 downto 0) := X"00"; variable bank_a_sd : std_logic_vector(7 downto 0) := X"00"; variable bank_a_se : std_logic_vector(7 downto 0) := X"00"; variable bank_a_sf : std_logic_vector(7 downto 0) := X"00"; variable bank_b_s0 : std_logic_vector(7 downto 0) := X"00"; variable bank_b_s1 : std_logic_vector(7 downto 0) := X"00"; variable bank_b_s2 : std_logic_vector(7 downto 0) := X"00"; variable bank_b_s3 : std_logic_vector(7 downto 0) := X"00"; variable bank_b_s4 : std_logic_vector(7 downto 0) := X"00"; variable bank_b_s5 : std_logic_vector(7 downto 0) := X"00"; variable bank_b_s6 : std_logic_vector(7 downto 0) := X"00"; variable bank_b_s7 : std_logic_vector(7 downto 0) := X"00"; variable bank_b_s8 : std_logic_vector(7 downto 0) := X"00"; variable bank_b_s9 : std_logic_vector(7 downto 0) := X"00"; variable bank_b_sa : std_logic_vector(7 downto 0) := X"00"; variable bank_b_sb : std_logic_vector(7 downto 0) := X"00"; variable bank_b_sc : std_logic_vector(7 downto 0) := X"00"; variable bank_b_sd : std_logic_vector(7 downto 0) := X"00"; variable bank_b_se : std_logic_vector(7 downto 0) := X"00"; variable bank_b_sf : std_logic_vector(7 downto 0) := X"00"; -- -- Temporary variables for instruction decoding -- variable sx_decode : string(1 to 2); -- sX register specification variable sy_decode : string(1 to 2); -- sY register specification variable kk_decode : string(1 to 2); -- constant value kk, pp or ss variable aaa_decode : string(1 to 3); -- address value aaa -- ----------------------------------------------------------------------------------------- -- -- Function to convert 4-bit binary nibble to hexadecimal character -- ----------------------------------------------------------------------------------------- -- function hexcharacter (nibble: std_logic_vector(3 downto 0)) return character is variable hex: character; begin case nibble is when "0000" => hex := '0'; when "0001" => hex := '1'; when "0010" => hex := '2'; when "0011" => hex := '3'; when "0100" => hex := '4'; when "0101" => hex := '5'; when "0110" => hex := '6'; when "0111" => hex := '7'; when "1000" => hex := '8'; when "1001" => hex := '9'; when "1010" => hex := 'A'; when "1011" => hex := 'B'; when "1100" => hex := 'C'; when "1101" => hex := 'D'; when "1110" => hex := 'E'; when "1111" => hex := 'F'; when others => hex := 'x'; end case; return hex; end hexcharacter; -- ----------------------------------------------------------------------------------------- -- begin -- decode first register sX sx_decode(1) := 's'; sx_decode(2) := hexcharacter(instruction(11 downto 8)); -- decode second register sY sy_decode(1) := 's'; sy_decode(2) := hexcharacter(instruction(7 downto 4)); -- decode constant value kk_decode(1) := hexcharacter(instruction(7 downto 4)); kk_decode(2) := hexcharacter(instruction(3 downto 0)); -- address value aaa_decode(1) := hexcharacter(instruction(11 downto 8)); aaa_decode(2) := hexcharacter(instruction(7 downto 4)); aaa_decode(3) := hexcharacter(instruction(3 downto 0)); -- decode instruction case instruction(17 downto 12) is when "000000" => kcpsm6_opcode <= "LOAD " & sx_decode & ", " & sy_decode & " "; when "000001" => kcpsm6_opcode <= "LOAD " & sx_decode & ", " & kk_decode & " "; when "010110" => kcpsm6_opcode <= "STAR " & sx_decode & ", " & sy_decode & " "; when "000010" => kcpsm6_opcode <= "AND " & sx_decode & ", " & sy_decode & " "; when "000011" => kcpsm6_opcode <= "AND " & sx_decode & ", " & kk_decode & " "; when "000100" => kcpsm6_opcode <= "OR " & sx_decode & ", " & sy_decode & " "; when "000101" => kcpsm6_opcode <= "OR " & sx_decode & ", " & kk_decode & " "; when "000110" => kcpsm6_opcode <= "XOR " & sx_decode & ", " & sy_decode & " "; when "000111" => kcpsm6_opcode <= "XOR " & sx_decode & ", " & kk_decode & " "; when "001100" => kcpsm6_opcode <= "TEST " & sx_decode & ", " & sy_decode & " "; when "001101" => kcpsm6_opcode <= "TEST " & sx_decode & ", " & kk_decode & " "; when "001110" => kcpsm6_opcode <= "TESTCY " & sx_decode & ", " & sy_decode & " "; when "001111" => kcpsm6_opcode <= "TESTCY " & sx_decode & ", " & kk_decode & " "; when "010000" => kcpsm6_opcode <= "ADD " & sx_decode & ", " & sy_decode & " "; when "010001" => kcpsm6_opcode <= "ADD " & sx_decode & ", " & kk_decode & " "; when "010010" => kcpsm6_opcode <= "ADDCY " & sx_decode & ", " & sy_decode & " "; when "010011" => kcpsm6_opcode <= "ADDCY " & sx_decode & ", " & kk_decode & " "; when "011000" => kcpsm6_opcode <= "SUB " & sx_decode & ", " & sy_decode & " "; when "011001" => kcpsm6_opcode <= "SUB " & sx_decode & ", " & kk_decode & " "; when "011010" => kcpsm6_opcode <= "SUBCY " & sx_decode & ", " & sy_decode & " "; when "011011" => kcpsm6_opcode <= "SUBCY " & sx_decode & ", " & kk_decode & " "; when "011100" => kcpsm6_opcode <= "COMPARE " & sx_decode & ", " & sy_decode & " "; when "011101" => kcpsm6_opcode <= "COMPARE " & sx_decode & ", " & kk_decode & " "; when "011110" => kcpsm6_opcode <= "COMPARECY " & sx_decode & ", " & sy_decode & " "; when "011111" => kcpsm6_opcode <= "COMPARECY " & sx_decode & ", " & kk_decode & " "; when "010100" => if instruction(7) = '1' then kcpsm6_opcode <= "HWBUILD " & sx_decode & " "; else case instruction(3 downto 0) is when "0110" => kcpsm6_opcode <= "SL0 " & sx_decode & " "; when "0111" => kcpsm6_opcode <= "SL1 " & sx_decode & " "; when "0100" => kcpsm6_opcode <= "SLX " & sx_decode & " "; when "0000" => kcpsm6_opcode <= "SLA " & sx_decode & " "; when "0010" => kcpsm6_opcode <= "RL " & sx_decode & " "; when "1110" => kcpsm6_opcode <= "SR0 " & sx_decode & " "; when "1111" => kcpsm6_opcode <= "SR1 " & sx_decode & " "; when "1010" => kcpsm6_opcode <= "SRX " & sx_decode & " "; when "1000" => kcpsm6_opcode <= "SRA " & sx_decode & " "; when "1100" => kcpsm6_opcode <= "RR " & sx_decode & " "; when others => kcpsm6_opcode <= "Invalid Instruction"; end case; end if; when "101100" => kcpsm6_opcode <= "OUTPUT " & sx_decode & ", (" & sy_decode & ") "; when "101101" => kcpsm6_opcode <= "OUTPUT " & sx_decode & ", " & kk_decode & " "; when "101011" => kcpsm6_opcode <= "OUTPUTK " & aaa_decode(1) & aaa_decode(2) & ", " & aaa_decode(3) & " "; when "001000" => kcpsm6_opcode <= "INPUT " & sx_decode & ", (" & sy_decode & ") "; when "001001" => kcpsm6_opcode <= "INPUT " & sx_decode & ", " & kk_decode & " "; when "101110" => kcpsm6_opcode <= "STORE " & sx_decode & ", (" & sy_decode & ") "; when "101111" => kcpsm6_opcode <= "STORE " & sx_decode & ", " & kk_decode & " "; when "001010" => kcpsm6_opcode <= "FETCH " & sx_decode & ", (" & sy_decode & ") "; when "001011" => kcpsm6_opcode <= "FETCH " & sx_decode & ", " & kk_decode & " "; when "100010" => kcpsm6_opcode <= "JUMP " & aaa_decode & " "; when "110010" => kcpsm6_opcode <= "JUMP Z, " & aaa_decode & " "; when "110110" => kcpsm6_opcode <= "JUMP NZ, " & aaa_decode & " "; when "111010" => kcpsm6_opcode <= "JUMP C, " & aaa_decode & " "; when "111110" => kcpsm6_opcode <= "JUMP NC, " & aaa_decode & " "; when "100110" => kcpsm6_opcode <= "JUMP@ (" & sx_decode & ", " & sy_decode & ") "; when "100000" => kcpsm6_opcode <= "CALL " & aaa_decode & " "; when "110000" => kcpsm6_opcode <= "CALL Z, " & aaa_decode & " "; when "110100" => kcpsm6_opcode <= "CALL NZ, " & aaa_decode & " "; when "111000" => kcpsm6_opcode <= "CALL C, " & aaa_decode & " "; when "111100" => kcpsm6_opcode <= "CALL NC, " & aaa_decode & " "; when "100100" => kcpsm6_opcode <= "CALL@ (" & sx_decode & ", " & sy_decode & ") "; when "100101" => kcpsm6_opcode <= "RETURN "; when "110001" => kcpsm6_opcode <= "RETURN Z "; when "110101" => kcpsm6_opcode <= "RETURN NZ "; when "111001" => kcpsm6_opcode <= "RETURN C "; when "111101" => kcpsm6_opcode <= "RETURN NC "; when "100001" => kcpsm6_opcode <= "LOAD&RETURN " & sx_decode & ", " & kk_decode & " "; when "101001" => case instruction(0) is when '0' => kcpsm6_opcode <= "RETURNI DISABLE "; when '1' => kcpsm6_opcode <= "RETURNI ENABLE "; when others => kcpsm6_opcode <= "Invalid Instruction"; end case; when "101000" => case instruction(0) is when '0' => kcpsm6_opcode <= "DISABLE INTERRUPT "; when '1' => kcpsm6_opcode <= "ENABLE INTERRUPT "; when others => kcpsm6_opcode <= "Invalid Instruction"; end case; when "110111" => case instruction(0) is when '0' => kcpsm6_opcode <= "REGBANK A "; when '1' => kcpsm6_opcode <= "REGBANK B "; when others => kcpsm6_opcode <= "Invalid Instruction"; end case; when others => kcpsm6_opcode <= "Invalid Instruction"; end case; -- Flag status information if zero_flag = '0' then kcpsm6_status(3 to 5) <= "NZ,"; else kcpsm6_status(3 to 5) <= " Z,"; end if; if carry_flag = '0' then kcpsm6_status(6 to 8) <= "NC,"; else kcpsm6_status(6 to 8) <= " C,"; end if; if interrupt_enable = '0' then kcpsm6_status(9 to 10) <= "ID"; else kcpsm6_status(9 to 10) <= "IE"; end if; -- Operational status if clk'event and clk = '1' then if internal_reset = '1' then kcpsm6_status(11 to 16) <= ",Reset"; else if sync_sleep = '1' and t_state = "00" then kcpsm6_status(11 to 16) <= ",Sleep"; else kcpsm6_status(11 to 16) <= " "; end if; end if; end if; -- Simulation of register contents if clk'event and clk = '1' then if register_enable = '1' then case sx_addr is when "00000" => bank_a_s0 := alu_result; when "00001" => bank_a_s1 := alu_result; when "00010" => bank_a_s2 := alu_result; when "00011" => bank_a_s3 := alu_result; when "00100" => bank_a_s4 := alu_result; when "00101" => bank_a_s5 := alu_result; when "00110" => bank_a_s6 := alu_result; when "00111" => bank_a_s7 := alu_result; when "01000" => bank_a_s8 := alu_result; when "01001" => bank_a_s9 := alu_result; when "01010" => bank_a_sa := alu_result; when "01011" => bank_a_sb := alu_result; when "01100" => bank_a_sc := alu_result; when "01101" => bank_a_sd := alu_result; when "01110" => bank_a_se := alu_result; when "01111" => bank_a_sf := alu_result; when "10000" => bank_b_s0 := alu_result; when "10001" => bank_b_s1 := alu_result; when "10010" => bank_b_s2 := alu_result; when "10011" => bank_b_s3 := alu_result; when "10100" => bank_b_s4 := alu_result; when "10101" => bank_b_s5 := alu_result; when "10110" => bank_b_s6 := alu_result; when "10111" => bank_b_s7 := alu_result; when "11000" => bank_b_s8 := alu_result; when "11001" => bank_b_s9 := alu_result; when "11010" => bank_b_sa := alu_result; when "11011" => bank_b_sb := alu_result; when "11100" => bank_b_sc := alu_result; when "11101" => bank_b_sd := alu_result; when "11110" => bank_b_se := alu_result; when "11111" => bank_b_sf := alu_result; when others => null; end case; end if; --simulation of scratch pad memory contents if spm_enable = '1' then case sy_or_kk is when "00000000" => sim_spm00 <= sx; when "00000001" => sim_spm01 <= sx; when "00000010" => sim_spm02 <= sx; when "00000011" => sim_spm03 <= sx; when "00000100" => sim_spm04 <= sx; when "00000101" => sim_spm05 <= sx; when "00000110" => sim_spm06 <= sx; when "00000111" => sim_spm07 <= sx; when "00001000" => sim_spm08 <= sx; when "00001001" => sim_spm09 <= sx; when "00001010" => sim_spm0A <= sx; when "00001011" => sim_spm0B <= sx; when "00001100" => sim_spm0C <= sx; when "00001101" => sim_spm0D <= sx; when "00001110" => sim_spm0E <= sx; when "00001111" => sim_spm0F <= sx; when "00010000" => sim_spm10 <= sx; when "00010001" => sim_spm11 <= sx; when "00010010" => sim_spm12 <= sx; when "00010011" => sim_spm13 <= sx; when "00010100" => sim_spm14 <= sx; when "00010101" => sim_spm15 <= sx; when "00010110" => sim_spm16 <= sx; when "00010111" => sim_spm17 <= sx; when "00011000" => sim_spm18 <= sx; when "00011001" => sim_spm19 <= sx; when "00011010" => sim_spm1A <= sx; when "00011011" => sim_spm1B <= sx; when "00011100" => sim_spm1C <= sx; when "00011101" => sim_spm1D <= sx; when "00011110" => sim_spm1E <= sx; when "00011111" => sim_spm1F <= sx; when "00100000" => sim_spm20 <= sx; when "00100001" => sim_spm21 <= sx; when "00100010" => sim_spm22 <= sx; when "00100011" => sim_spm23 <= sx; when "00100100" => sim_spm24 <= sx; when "00100101" => sim_spm25 <= sx; when "00100110" => sim_spm26 <= sx; when "00100111" => sim_spm27 <= sx; when "00101000" => sim_spm28 <= sx; when "00101001" => sim_spm29 <= sx; when "00101010" => sim_spm2A <= sx; when "00101011" => sim_spm2B <= sx; when "00101100" => sim_spm2C <= sx; when "00101101" => sim_spm2D <= sx; when "00101110" => sim_spm2E <= sx; when "00101111" => sim_spm2F <= sx; when "00110000" => sim_spm30 <= sx; when "00110001" => sim_spm31 <= sx; when "00110010" => sim_spm32 <= sx; when "00110011" => sim_spm33 <= sx; when "00110100" => sim_spm34 <= sx; when "00110101" => sim_spm35 <= sx; when "00110110" => sim_spm36 <= sx; when "00110111" => sim_spm37 <= sx; when "00111000" => sim_spm38 <= sx; when "00111001" => sim_spm39 <= sx; when "00111010" => sim_spm3A <= sx; when "00111011" => sim_spm3B <= sx; when "00111100" => sim_spm3C <= sx; when "00111101" => sim_spm3D <= sx; when "00111110" => sim_spm3E <= sx; when "00111111" => sim_spm3F <= sx; when "01000000" => sim_spm40 <= sx; when "01000001" => sim_spm41 <= sx; when "01000010" => sim_spm42 <= sx; when "01000011" => sim_spm43 <= sx; when "01000100" => sim_spm44 <= sx; when "01000101" => sim_spm45 <= sx; when "01000110" => sim_spm46 <= sx; when "01000111" => sim_spm47 <= sx; when "01001000" => sim_spm48 <= sx; when "01001001" => sim_spm49 <= sx; when "01001010" => sim_spm4A <= sx; when "01001011" => sim_spm4B <= sx; when "01001100" => sim_spm4C <= sx; when "01001101" => sim_spm4D <= sx; when "01001110" => sim_spm4E <= sx; when "01001111" => sim_spm4F <= sx; when "01010000" => sim_spm50 <= sx; when "01010001" => sim_spm51 <= sx; when "01010010" => sim_spm52 <= sx; when "01010011" => sim_spm53 <= sx; when "01010100" => sim_spm54 <= sx; when "01010101" => sim_spm55 <= sx; when "01010110" => sim_spm56 <= sx; when "01010111" => sim_spm57 <= sx; when "01011000" => sim_spm58 <= sx; when "01011001" => sim_spm59 <= sx; when "01011010" => sim_spm5A <= sx; when "01011011" => sim_spm5B <= sx; when "01011100" => sim_spm5C <= sx; when "01011101" => sim_spm5D <= sx; when "01011110" => sim_spm5E <= sx; when "01011111" => sim_spm5F <= sx; when "01100000" => sim_spm60 <= sx; when "01100001" => sim_spm61 <= sx; when "01100010" => sim_spm62 <= sx; when "01100011" => sim_spm63 <= sx; when "01100100" => sim_spm64 <= sx; when "01100101" => sim_spm65 <= sx; when "01100110" => sim_spm66 <= sx; when "01100111" => sim_spm67 <= sx; when "01101000" => sim_spm68 <= sx; when "01101001" => sim_spm69 <= sx; when "01101010" => sim_spm6A <= sx; when "01101011" => sim_spm6B <= sx; when "01101100" => sim_spm6C <= sx; when "01101101" => sim_spm6D <= sx; when "01101110" => sim_spm6E <= sx; when "01101111" => sim_spm6F <= sx; when "01110000" => sim_spm70 <= sx; when "01110001" => sim_spm71 <= sx; when "01110010" => sim_spm72 <= sx; when "01110011" => sim_spm73 <= sx; when "01110100" => sim_spm74 <= sx; when "01110101" => sim_spm75 <= sx; when "01110110" => sim_spm76 <= sx; when "01110111" => sim_spm77 <= sx; when "01111000" => sim_spm78 <= sx; when "01111001" => sim_spm79 <= sx; when "01111010" => sim_spm7A <= sx; when "01111011" => sim_spm7B <= sx; when "01111100" => sim_spm7C <= sx; when "01111101" => sim_spm7D <= sx; when "01111110" => sim_spm7E <= sx; when "01111111" => sim_spm7F <= sx; when "10000000" => sim_spm80 <= sx; when "10000001" => sim_spm81 <= sx; when "10000010" => sim_spm82 <= sx; when "10000011" => sim_spm83 <= sx; when "10000100" => sim_spm84 <= sx; when "10000101" => sim_spm85 <= sx; when "10000110" => sim_spm86 <= sx; when "10000111" => sim_spm87 <= sx; when "10001000" => sim_spm88 <= sx; when "10001001" => sim_spm89 <= sx; when "10001010" => sim_spm8A <= sx; when "10001011" => sim_spm8B <= sx; when "10001100" => sim_spm8C <= sx; when "10001101" => sim_spm8D <= sx; when "10001110" => sim_spm8E <= sx; when "10001111" => sim_spm8F <= sx; when "10010000" => sim_spm90 <= sx; when "10010001" => sim_spm91 <= sx; when "10010010" => sim_spm92 <= sx; when "10010011" => sim_spm93 <= sx; when "10010100" => sim_spm94 <= sx; when "10010101" => sim_spm95 <= sx; when "10010110" => sim_spm96 <= sx; when "10010111" => sim_spm97 <= sx; when "10011000" => sim_spm98 <= sx; when "10011001" => sim_spm99 <= sx; when "10011010" => sim_spm9A <= sx; when "10011011" => sim_spm9B <= sx; when "10011100" => sim_spm9C <= sx; when "10011101" => sim_spm9D <= sx; when "10011110" => sim_spm9E <= sx; when "10011111" => sim_spm9F <= sx; when "10100000" => sim_spma0 <= sx; when "10100001" => sim_spmA1 <= sx; when "10100010" => sim_spmA2 <= sx; when "10100011" => sim_spmA3 <= sx; when "10100100" => sim_spmA4 <= sx; when "10100101" => sim_spmA5 <= sx; when "10100110" => sim_spmA6 <= sx; when "10100111" => sim_spmA7 <= sx; when "10101000" => sim_spmA8 <= sx; when "10101001" => sim_spmA9 <= sx; when "10101010" => sim_spmAA <= sx; when "10101011" => sim_spmAB <= sx; when "10101100" => sim_spmAC <= sx; when "10101101" => sim_spmAD <= sx; when "10101110" => sim_spmAE <= sx; when "10101111" => sim_spmAF <= sx; when "10110000" => sim_spmB0 <= sx; when "10110001" => sim_spmB1 <= sx; when "10110010" => sim_spmB2 <= sx; when "10110011" => sim_spmB3 <= sx; when "10110100" => sim_spmB4 <= sx; when "10110101" => sim_spmB5 <= sx; when "10110110" => sim_spmB6 <= sx; when "10110111" => sim_spmB7 <= sx; when "10111000" => sim_spmB8 <= sx; when "10111001" => sim_spmB9 <= sx; when "10111010" => sim_spmBA <= sx; when "10111011" => sim_spmBB <= sx; when "10111100" => sim_spmBC <= sx; when "10111101" => sim_spmBD <= sx; when "10111110" => sim_spmBE <= sx; when "10111111" => sim_spmBF <= sx; when "11000000" => sim_spmC0 <= sx; when "11000001" => sim_spmC1 <= sx; when "11000010" => sim_spmC2 <= sx; when "11000011" => sim_spmC3 <= sx; when "11000100" => sim_spmC4 <= sx; when "11000101" => sim_spmC5 <= sx; when "11000110" => sim_spmC6 <= sx; when "11000111" => sim_spmC7 <= sx; when "11001000" => sim_spmC8 <= sx; when "11001001" => sim_spmC9 <= sx; when "11001010" => sim_spmCA <= sx; when "11001011" => sim_spmCB <= sx; when "11001100" => sim_spmCC <= sx; when "11001101" => sim_spmCD <= sx; when "11001110" => sim_spmCE <= sx; when "11001111" => sim_spmCF <= sx; when "11010000" => sim_spmD0 <= sx; when "11010001" => sim_spmD1 <= sx; when "11010010" => sim_spmD2 <= sx; when "11010011" => sim_spmD3 <= sx; when "11010100" => sim_spmD4 <= sx; when "11010101" => sim_spmD5 <= sx; when "11010110" => sim_spmD6 <= sx; when "11010111" => sim_spmD7 <= sx; when "11011000" => sim_spmD8 <= sx; when "11011001" => sim_spmD9 <= sx; when "11011010" => sim_spmDA <= sx; when "11011011" => sim_spmDB <= sx; when "11011100" => sim_spmDC <= sx; when "11011101" => sim_spmDD <= sx; when "11011110" => sim_spmDE <= sx; when "11011111" => sim_spmDF <= sx; when "11100000" => sim_spmE0 <= sx; when "11100001" => sim_spmE1 <= sx; when "11100010" => sim_spmE2 <= sx; when "11100011" => sim_spmE3 <= sx; when "11100100" => sim_spmE4 <= sx; when "11100101" => sim_spmE5 <= sx; when "11100110" => sim_spmE6 <= sx; when "11100111" => sim_spmE7 <= sx; when "11101000" => sim_spmE8 <= sx; when "11101001" => sim_spmE9 <= sx; when "11101010" => sim_spmEA <= sx; when "11101011" => sim_spmEB <= sx; when "11101100" => sim_spmEC <= sx; when "11101101" => sim_spmED <= sx; when "11101110" => sim_spmEE <= sx; when "11101111" => sim_spmEF <= sx; when "11110000" => sim_spmF0 <= sx; when "11110001" => sim_spmF1 <= sx; when "11110010" => sim_spmF2 <= sx; when "11110011" => sim_spmF3 <= sx; when "11110100" => sim_spmF4 <= sx; when "11110101" => sim_spmF5 <= sx; when "11110110" => sim_spmF6 <= sx; when "11110111" => sim_spmF7 <= sx; when "11111000" => sim_spmF8 <= sx; when "11111001" => sim_spmF9 <= sx; when "11111010" => sim_spmFA <= sx; when "11111011" => sim_spmFB <= sx; when "11111100" => sim_spmFC <= sx; when "11111101" => sim_spmFD <= sx; when "11111110" => sim_spmFE <= sx; when "11111111" => sim_spmFF <= sx; when others => null; end case; end if; end if; -- -- Assignment of internal register variables to active registers -- if bank = '0' then kcpsm6_status(1 to 2) <= "A,"; sim_s0 <= bank_a_s0; sim_s1 <= bank_a_s1; sim_s2 <= bank_a_s2; sim_s3 <= bank_a_s3; sim_s4 <= bank_a_s4; sim_s5 <= bank_a_s5; sim_s6 <= bank_a_s6; sim_s7 <= bank_a_s7; sim_s8 <= bank_a_s8; sim_s9 <= bank_a_s9; sim_sA <= bank_a_sA; sim_sB <= bank_a_sB; sim_sC <= bank_a_sC; sim_sD <= bank_a_sD; sim_sE <= bank_a_sE; sim_sF <= bank_a_sF; else kcpsm6_status(1 to 2) <= "B,"; sim_s0 <= bank_b_s0; sim_s1 <= bank_b_s1; sim_s2 <= bank_b_s2; sim_s3 <= bank_b_s3; sim_s4 <= bank_b_s4; sim_s5 <= bank_b_s5; sim_s6 <= bank_b_s6; sim_s7 <= bank_b_s7; sim_s8 <= bank_b_s8; sim_s9 <= bank_b_s9; sim_sA <= bank_b_sA; sim_sB <= bank_b_sB; sim_sC <= bank_b_sC; sim_sD <= bank_b_sD; sim_sE <= bank_b_sE; sim_sF <= bank_b_sF; end if; -- end process simulation; --synthesis translate on -- -- ************************** -- * End of simulation code * -- ************************** -- -- ------------------------------------------------------------------------------------------- -- end low_level_definition; -- ------------------------------------------------------------------------------------------- -- -- END OF FILE kcpsm6.vhd -- -------------------------------------------------------------------------------------------
------------------------------------------------------------------------------- --! @file axiLiteSlaveWrapper-rtl-ea.vhd -- --! @brief AXI lite slave wrapper on avalon slave interface signals -- --! @details AXI lite slave will convert AXI slave interface singal to Avalon --! interface signals. -- ------------------------------------------------------------------------------- -- -- Copyright (c) 2014, Bernecker+Rainer Industrie-Elektronik Ges.m.b.H. (B&R) -- Copyright (c) 2014, Kalycito Infotech Private Limited. -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- --! Use standard ieee library library ieee; --! Use logic elements use ieee.std_logic_1164.all; --! Use libcommon library library libcommon; --! Use Global Library use libcommon.global.all; ------------------------------------------------------------------------------- --! @brief --! @details AXI-lite slave wrapper will receive signals from AXI bus and --! provide proper inputs for a Avlon interface to perform the same action --! initiated by AXI master ------------------------------------------------------------------------------- entity axiLiteSlaveWrapper is generic ( --! Base Lower address for the AXI-lite slave interface gBaseAddr : std_logic_vector(31 downto 0) := x"00000000"; --! Base Higher address for the AXI-lite slave interface gHighAddr : std_logic_vector(31 downto 0) := x"0000ffff"; --! Address width for AXI bus interface gAddrWidth : integer := 32; --! Data width for AXI bus interface gDataWidth : integer := 32 ); port ( --! Global Clock for AXI iAclk : in std_logic; --! Global Reset for AXI inAReset : in std_logic; --! Address for Write Address Channel iAwaddr : in std_logic_vector(gAddrWidth-1 downto 0); --! Protection for Write Address Channel iAwprot : in std_logic_vector(2 downto 0); --unused input --! AddressValid for Write Address Channel iAwvalid : in std_logic; --! AddressReady for Write Address Channel oAwready : out std_logic; --! WriteData for Write Data Channel iWdata : in std_logic_vector(gDataWidth-1 downto 0); --! WriteStrobe for Write Data Channel iWstrb : in std_logic_vector(gDataWidth/8-1 downto 0); --! WriteValid for Write Data Channel iWvalid : in std_logic; --! WriteReady for Write Data Channel oWready : out std_logic; --! WriteResponse for Write Response Channel oBresp : out std_logic_vector (1 downto 0); --! ResponseValid for Write Response Channel oBvalid : out std_logic; --! ResponaseReady for Write Response Channel iBready : in std_logic; --! ReadAddress for Read Address Channel iAraddr : in std_logic_vector(gAddrWidth-1 downto 0); --! ReadAddressProtection for Read Address Channel iArprot : in std_logic_vector(2 downto 0); --unused input --! ReadAddressValid for Read Address Channel iArvalid : in std_logic; --! ReadAddressReady for Read Address Channel oArready : out std_logic; --! ReadData for Read Data Channel oRdata : out std_logic_vector(gDataWidth-1 downto 0); --! ReadResponse for Read Data Channel oRresp : out std_logic_vector(1 downto 0); --! ReadValid for Read Data Channel oRvalid : out std_logic; --! ReadReady for Read Data Channel iRready : in std_logic; --! Address to Avalon Slave Interface oAvsAddress : out std_logic_vector(gAddrWidth-1 downto 0); --! Byte Enable for Avalon Slave interface oAvsByteenable : out std_logic_vector(gDataWidth/8-1 downto 0); --! Write Data for Avalon Slave interface oAvsWritedata : out std_logic_vector(gDataWidth-1 downto 0); --! Read Data for Avalon Slave interface iAvsReaddata : in std_logic_vector(gDataWidth-1 downto 0); --! Read signal for Avalon Slave interface oAvsRead : out std_logic; --! Write signal for Avalon Slave interface oAvsWrite : out std_logic; --! WaitRequest for Avalon slave interface iAvsWaitrequest : in std_logic ); end axiLiteSlaveWrapper; architecture rtl of axiLiteSlaveWrapper is --! Control signal FSM type tFsm is ( sIDLE, sREAD, sREAD_DONE, sWRITE, sWRITE_DONE, sWRRES_DONE, sDELAY ); --Avalon Interface designs --! address latch for Avalon Interface signal address : std_logic_vector(gAddrWidth-1 downto 0); --! Muxed address from AXI interface signal mux_address : std_logic_vector(gAddrWidth-1 downto 0); --! Chip select for address decoder signal chip_sel : std_logic; --! Muxed byte enable latch from AXI Interface signal byte_enable : std_logic_vector(gDataWidth/8-1 downto 0); --Signals for FSM --! synchronized fsm state signal fsm : tFsm; --! fsm state for combinational logic signal fsm_next : tFsm; --Internal Signals --! control for Avalon read signal with fsm signal avalonRead : std_logic; --! Read Data latch for Avalon interface signal avalonReadDataLatch : std_logic_vector(31 downto 0); --! control for Avalon write signal with fsm signal avalonWrite : std_logic; --! write data from AXI for Avalon interface signal axiWriteData : std_logic_vector(31 downto 0); --! valid data from AXI to Avalon signal axiDataValid : std_logic; --! Write start fsm operations signal writeStart : std_logic; --! Write select for control write operations signal write_sel : std_logic; --! Read Start for fsm operations signal readStart : std_logic; --! Read select for control read operations signal read_sel : std_logic; begin --Avalon Slave Interface Signals oAvsAddress <= address; oAvsByteenable <= byte_enable; oAvsRead <= avalonRead; oAvsWrite <= avalonWrite; oAvsWritedata <= axiWriteData; avalonRead <= cActivated when readStart = cActivated and fsm = sIDLE else cActivated when fsm = sREAD else cInactivated when fsm = sREAD_DONE else cInactivated; avalonWrite <= cActivated when fsm = sWRITE and iWvalid = cActivated else cActivated when fsm = sIDLE and axiDataValid = cActivated else cActivated when fsm = sWRITE_DONE else cInactivated; axiWriteData <= iWdata when axiDataValid = cActivated else axiWriteData; -- AXI-Lite Write Data Signals oBvalid <= cActivated when fsm = sWRITE_DONE and iAvsWaitrequest = cInactivated else cActivated when fsm = sWRRES_DONE else cInactivated; oAwready <= cActivated when fsm = sIDLE and writeStart = cActivated else cInactivated; oWready <= cActivated when fsm = sWRITE else cActivated when fsm = sIDLE and axiDataValid = cActivated else cInactivated; -- AXI-lite Read Data Signals oArready <= cActivated when fsm = sIDLE and readStart = cActivated else cInactivated; oRvalid <= cActivated when iAvsWaitrequest = cInactivated and fsm = sREAD else cActivated when fsm = sREAD_DONE else cInactivated; oRdata <= avalonReadDataLatch; avalonReadDataLatch <= iAvsReaddata when iAvsWaitrequest = cInactivated else avalonReadDataLatch; --TODO: Check the possibility of Error Response signals oBresp <= "00"; oRresp <= "00"; -- Address Decoder chip_sel <= read_sel or write_sel; -- 64Kbyte address range only supported so MSB 16 bits enough for Decoding write_sel <= cActivated when iAwaddr(31 downto 16) = gBaseAddr(31 downto 16) else cInactivated; read_sel <= cActivated when iAraddr(31 downto 16) = gBaseAddr(31 downto 16) else cInactivated; -- TODO: Check possibilities of reduce the no of bits in MUX/latch design -- and avoid combinational feedback on MUX -- Mux the address first and latch it with FSM address <= mux_address when fsm = sIDLE else address ; mux_address <= iAraddr when readStart = cActivated else iAwaddr when writeStart = cActivated else x"00000000" ; writeStart <= chip_sel and iAwvalid; readStart <= chip_sel and iArvalid; axiDataValid <= iWvalid; byte_enable <= x"F" when readStart = cActivated and fsm = sIDLE else iWstrb when writeStart = cActivated and fsm = sIDLE else byte_enable; -- Main Control FSM for converting AXI-lite signals to Avalon --! Clock Based Process for state changes SEQ_LOGIC_FSM : process(iAclk) begin if rising_edge(iAclk) then if inAReset = cnActivated then fsm <= sIDLE; else fsm <= fsm_next; end if; end if; end process SEQ_LOGIC_FSM; --! Control State machine COM_LOGIC_FSM : process ( fsm, chip_sel, iAwvalid, iArvalid, iRready, iWvalid, iBready, iAvsWaitrequest ) begin --Default to avoid latches fsm_next <= fsm; case fsm is when sIDLE => if chip_sel = cActivated then --Write Operations if iAwvalid = cActivated then if iWvalid = cActivated then if iAvsWaitrequest = cInactivated then fsm_next <= sWRRES_DONE; else fsm_next <= sWRITE_DONE; end if; else fsm_next <= sWRITE; end if; --Read Operations elsif iArvalid = cActivated then if iAvsWaitrequest = cInactivated then fsm_next <= sREAD_DONE; else fsm_next <= sREAD; end if; else fsm_next <= sIDLE; end if; else fsm_next <= sIDLE; end if; when sREAD => -- Read Valid gets assert Here if iAvsWaitrequest = cInactivated then if iRready = cActivated then fsm_next <= sIDLE; else fsm_next <= sREAD_DONE; end if; else fsm_next <= sREAD; end if; when sREAD_DONE => if iRready = cActivated then fsm_next <= sIDLE; else fsm_next <= sREAD_DONE; end if; when sWRITE => if iWvalid = cActivated then if iAvsWaitrequest = cInactivated then if iBready = cActivated then fsm_next <= sIDLE; else fsm_next <= sWRRES_DONE; end if; else fsm_next <= sWRITE_DONE; end if; else fsm_next <= sWRITE; end if; when sWRITE_DONE => if iAvsWaitrequest = cInactivated then if iBready = cActivated then fsm_next <= sIDLE; else fsm_next <= sWRRES_DONE; end if; else fsm_next <= sWRITE_DONE; end if; when sWRRES_DONE => if iBready = cActivated then fsm_next <= sIDLE; else fsm_next <= sWRRES_DONE; end if; when sDELAY => fsm_next <= sIDLE; when others => null; end case; end process COM_LOGIC_FSM; end rtl;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.types.all; entity DataPath is port ( clk : in std_logic; u232c_in : out u232c_in_t; u232c_out : in u232c_out_t; sramLoad : out boolean := true; sramAddr : out sram_addr := (others => '0'); sramData : inout value_t := (others => '0')); end DataPath; architecture behavioral of DataPath is component Fetch is port ( clk : in std_logic; d : in fetch_in_t; q : out fetch_out_t); end component; component ALU is port ( clk : in std_logic; code : in std_logic_vector(3 downto 0); tagD : in tag_t; valA : in value_t; valB : in value_t; emitTag : out tag_t; emitVal : out value_t); end component; component FPU is port ( clk : in std_logic; code : in std_logic_vector(5 downto 0); tagD : in tag_t; valA : in value_t; valB : in value_t; tag1 : buffer tag_t; tag2 : buffer tag_t; emitTag : out tag_t; emitVal : out value_t); end component; component Branch is port ( clk : in std_logic; d : in branch_in_t; q : out branch_out_t); end component; component IO is port ( clk : in std_logic; enable : in boolean; code : in std_logic_vector(2 downto 0); getTag : in tag_t; putVal : in value_t; blocking : out boolean; emitTag : out tag_t; emitVal : out value_t; u232c_in : out u232c_in_t; u232c_out : in u232c_out_t; emit_instw : out blkram_write_t); end component; type reg_file_t is array(31 downto 0) of value_t; signal gpr_file : reg_file_t := (others => (others => '0')); signal fpr_file : reg_file_t := (others => (others => '0')); attribute RAM_STYLE : string; attribute RAM_STYLE of gpr_file : signal is "distributed"; attribute RAM_STYLE of fpr_file : signal is "distributed"; signal inst : instruction_t := (others => '0'); signal pc : blkram_addr := (others => '0'); signal d_fet : fetch_in_t; signal q_fet : fetch_out_t; signal code_alu : std_logic_vector(3 downto 0) := (others => '0'); signal tag_alu_d : tag_t := (others => '0'); signal emit_tag_alu : tag_t; signal emit_val_alu : value_t; signal code_fpu : std_logic_vector(5 downto 0) := (others => '0'); signal tag_fpu_d : tag_t := (others => '0'); signal pipe1_tag_fpu, pipe2_tag_fpu, emit_tag_fpu : tag_t; signal emit_val_fpu : value_t; signal val_alu_fpu_a, val_alu_fpu_b : value_t := (others => '0'); signal d_bra : branch_in_t := ( code => "000", -- jmp to addr 0 once tag_l => (others => '0'), val_a => (others => '0'), val_b => (others => '0'), val_l => (others => '0'), val_t => (others => '0')); signal q_bra : branch_out_t; signal code_io : std_logic_vector(2 downto 0) := "000"; signal enable_io : boolean := false; signal tag_spc_y : tag_t := (others => '0'); signal val_spc_x : value_t := (others => '0'); signal emit_tag_spc : tag_t; signal emit_val_spc : value_t; signal blocking : boolean; signal jump1 : boolean; signal jump2 : boolean := false; signal ignore : boolean; signal stall : boolean; signal stall_lat : boolean := false; signal addr0 : sram_addr := (others => '0'); signal load0, load1, load2, load3 : boolean := true; signal tagM0, tagM1, tagM2, tagM3, emitTagLoad : tag_t := (others => '0'); signal tagFM0, tagFM1, tagFM2, tagFM3, emitTagFLoad : tag_t := (others => '0'); signal valM0, valM1, valM2, emitValM : value_t := (others => '0'); signal fwdM_1, fwdM_2 : boolean := false; signal tag_gpr_w_sig : tag_t; signal val_gpr_w_sig : value_t; signal tag_fpr_w_sig : tag_t; signal val_fpr_w_sig : value_t; begin -- fetch fetch_map : Fetch port map (clk => clk, d => d_fet, q => q_fet); sequential : process(clk) begin if rising_edge(clk) then if ignore or not stall then inst <= q_fet.inst; pc <= q_fet.pc; end if; gpr_file(to_integer(unsigned(tag_gpr_w_sig))) <= val_gpr_w_sig; fpr_file(to_integer(unsigned(tag_fpr_w_sig))) <= val_fpr_w_sig; d_fet.enable_addr <= not (ignore or stall); jump2 <= jump1; stall_lat <= stall; end if; end process; combinatorial : process(inst, pc, gpr_file, fpr_file, stall_lat, emit_tag_alu, emit_val_alu, pipe1_tag_fpu, pipe2_tag_fpu, emit_tag_fpu, emit_val_fpu, q_bra, q_fet, jump1, jump2, stall, ignore, blocking, emit_tag_spc, emit_val_spc, load1, load2, load3, tagM1, tagM2, tagM3, emitTagLoad, tagFM1, tagFM2, tagFM3, emitTagFLoad, emitValM) variable tag_gpr_w : tag_t; variable val_gpr_w : value_t; variable tag_fpr_w : tag_t; variable val_fpr_w : value_t; variable opcode : std_logic_vector(5 downto 0); variable tag_x, tag_y, tag_z : tag_t; variable imm : unsigned(15 downto 0); variable is_alu_imm, is_alu_gpr, is_alu_fpr : boolean; variable is_fpu_gpr, is_fpu_fpr : boolean; variable is_mem_gpr_ld, is_mem_gpr_st, is_mem_fpr_ld, is_mem_fpr_st : boolean; variable is_spc, is_jmp, is_bra_gpr, is_bra_fpr : boolean; variable val_gpr_x, val_gpr_y, imm_signed, val_gpr_fwd_x, val_gpr_fwd_y : value_t; variable val_fpr_x, val_fpr_y, val_fpr_fwd_x, val_fpr_fwd_y : value_t; variable stall_raw_gpr_x, stall_raw_gpr_y, stall_waw_gpr_y, stall_waw_gpr_z : boolean; variable stall_raw_fpr_x, stall_raw_fpr_y, stall_mst_fpr_y, stall_waw_fpr_z : boolean; begin tag_gpr_w := emit_tag_alu or q_bra.emit_tag or emit_tag_spc or emitTagLoad; if emit_tag_alu /= "00000" then val_gpr_w := emit_val_alu; elsif q_bra.emit_tag /= "00000" then val_gpr_w := value_t(x"0000" & q_bra.emit_link); elsif emit_tag_spc /= "00000" then val_gpr_w := emit_val_spc; elsif emitTagLoad /= "00000" then val_gpr_w := emitValM; else val_gpr_w := (others => '0'); end if; tag_fpr_w := emit_tag_fpu or emitTagFLoad; if emit_tag_fpu /= "00000" then val_fpr_w := emit_val_fpu; elsif emitTagFLoad /= "00000" then val_fpr_w := emitValM; else val_fpr_w := (others => '0'); end if; if not stall_lat then d_fet.addr <= q_bra.emit_target; end if; tag_gpr_w_sig <= tag_gpr_w; tag_fpr_w_sig <= tag_fpr_w; val_gpr_w_sig <= val_gpr_w; val_fpr_w_sig <= val_fpr_w; opcode := inst(31 downto 26); tag_x := tag_t(inst(25 downto 21)); tag_y := tag_t(inst(20 downto 16)); tag_z := tag_t(inst(15 downto 11)); imm := unsigned(inst(15 downto 0)); is_alu_imm := opcode(5 downto 4) = "00"; is_alu_gpr := opcode = "010000"; is_alu_fpr := opcode = "010001"; is_fpu_gpr := opcode = "011000"; is_fpu_fpr := opcode = "011001"; is_mem_gpr_ld := opcode = "010010"; is_mem_gpr_st := opcode = "010011"; is_mem_fpr_ld := opcode = "011010"; is_mem_fpr_st := opcode = "011011"; is_spc := opcode(5 downto 2) = "0101" and opcode(1 downto 0) = "11"; is_jmp := opcode(5 downto 2) = "0101" and opcode(1 downto 0) /= "11"; is_bra_gpr := opcode(5 downto 4) = "10"; is_bra_fpr := opcode(5 downto 4) = "11"; val_gpr_x := gpr_file(to_integer(unsigned(tag_x))); val_gpr_y := gpr_file(to_integer(unsigned(tag_y))); imm_signed := value_t(resize(signed(imm), 32)); if tag_x = tag_gpr_w then val_gpr_fwd_x := val_gpr_w; else val_gpr_fwd_x := val_gpr_x; end if; if tag_y = tag_gpr_w then val_gpr_fwd_y := val_gpr_w; else val_gpr_fwd_y := val_gpr_y; end if; val_fpr_x := fpr_file(to_integer(unsigned(tag_x))); val_fpr_y := fpr_file(to_integer(unsigned(tag_y))); if tag_x = tag_fpr_w then val_fpr_fwd_x := val_fpr_w; else val_fpr_fwd_x := val_fpr_x; end if; if tag_y = tag_fpr_w then val_fpr_fwd_y := val_fpr_w; else val_fpr_fwd_y := val_fpr_y; end if; stall_raw_gpr_x := tag_x /= "00000" and not (is_alu_fpr or is_fpu_fpr or is_bra_fpr) and ( (load1 and tag_x = tagM1) or (load2 and tag_x = tagM2) or (load3 and tag_x = tagM3)); stall_raw_gpr_y := tag_y /= "00000" and (is_alu_gpr or is_fpu_gpr or is_bra_gpr) and ( (load1 and tag_y = tagM1) or (load2 and tag_y = tagM2) or (load3 and tag_y = tagM3)); stall_waw_gpr_y := tag_y /= "00000" and (is_alu_imm or is_spc or is_jmp) and ( (load1 and tag_y = tagM1) or (load2 and tag_y = tagM2) or (load3 and tagM3 /= "00000")); stall_waw_gpr_z := tag_z /= "00000" and is_alu_gpr and ( (load1 and tag_z = tagM1) or (load2 and tag_z = tagM2) or (load3 and tagM3 /= "00000")); stall_raw_fpr_x := tag_x /= "00000" and (is_alu_fpr or is_fpu_fpr or is_bra_fpr) and ( (tag_x = pipe1_tag_fpu) or (tag_x = pipe2_tag_fpu) or (load1 and tag_x = tagFM1) or (load2 and tag_x = tagFM2) or (load3 and tag_x = tagFM3)); stall_raw_fpr_y := tag_y /= "00000" and (is_alu_fpr or is_fpu_fpr or is_bra_fpr) and ( (tag_y = pipe1_tag_fpu) or (tag_y = pipe2_tag_fpu) or (load1 and tag_y = tagFM1) or (load2 and tag_y = tagFM2) or (load3 and tag_y = tagFM3)); stall_mst_fpr_y := tag_y /= "00000" and (is_mem_fpr_st) and ( (tag_y = pipe1_tag_fpu) or (tag_y = pipe2_tag_fpu)); stall_waw_fpr_z := tag_z /= "00000" and (is_fpu_gpr or is_fpu_fpr) and ( (load1 and tagFM1 /= "00000")); stall <= stall_raw_gpr_x or stall_raw_gpr_y or stall_waw_gpr_y or stall_waw_gpr_z or stall_raw_fpr_x or stall_raw_fpr_y or stall_mst_fpr_y or stall_waw_fpr_z or blocking; jump1 <= q_fet.jump; ignore <= jump2 or jump1; d_fet.enable_fetch <= ignore or not stall; if is_alu_imm then code_alu <= opcode(3 downto 0); else code_alu <= inst(3 downto 0); end if; if ignore or stall then tag_alu_d <= "00000"; elsif is_alu_imm then tag_alu_d <= tag_y; elsif is_alu_gpr or is_alu_fpr then tag_alu_d <= tag_z; else tag_alu_d <= "00000"; end if; code_fpu <= inst(5 downto 0); if ignore or stall then tag_fpu_d <= "00000"; elsif is_fpu_gpr or is_fpu_fpr then tag_fpu_d <= tag_z; else tag_fpu_d <= "00000"; end if; if is_alu_imm then val_alu_fpu_a <= val_gpr_fwd_x; val_alu_fpu_b <= imm_signed; elsif opcode(0) = '0' then val_alu_fpu_a <= val_gpr_fwd_x; val_alu_fpu_b <= val_gpr_fwd_y; else val_alu_fpu_a <= val_fpr_fwd_x; val_alu_fpu_b <= val_fpr_fwd_y; end if; if ignore or stall then d_bra.code <= "000"; d_bra.tag_l <= "00000"; if opcode(4) = '0' then d_bra.val_a <= '1' & val_gpr_fwd_x(30 downto 0); d_bra.val_b <= '0' & val_gpr_fwd_y(30 downto 0); else d_bra.val_a <= '1' & val_fpr_fwd_x(30 downto 0); d_bra.val_b <= '0' & val_fpr_fwd_y(30 downto 0); end if; d_bra.val_t <= blkram_addr(imm); else if is_bra_gpr or is_bra_fpr then d_bra.code <= opcode(4) & opcode(1 downto 0); d_bra.tag_l <= "00000"; if opcode(4) = '0' then d_bra.val_a <= val_gpr_fwd_x; d_bra.val_b <= val_gpr_fwd_y; else d_bra.val_a <= val_fpr_fwd_x; d_bra.val_b <= val_fpr_fwd_y; end if; d_bra.val_t <= blkram_addr(imm); else if is_jmp then d_bra.code <= "010"; d_bra.tag_l <= tag_y; else d_bra.code <= "000"; d_bra.tag_l <= "00000"; end if; if opcode(4) = '0' then d_bra.val_a <= '1' & val_gpr_fwd_x(30 downto 0); d_bra.val_b <= '0' & val_gpr_fwd_y(30 downto 0); else d_bra.val_a <= '1' & val_fpr_fwd_x(30 downto 0); d_bra.val_b <= '0' & val_fpr_fwd_y(30 downto 0); end if; d_bra.val_t <= blkram_addr(imm or unsigned(val_gpr_fwd_x(15 downto 0))); end if; end if; d_bra.val_l <= pc; code_io <= inst(2 downto 0); enable_io <= not (ignore or stall) and is_spc; tag_spc_y <= tag_y; val_spc_x <= val_gpr_fwd_x; if ignore or stall then load0 <= true; tagM0 <= "00000"; tagFM0 <= "00000"; else load0 <= not (is_mem_gpr_st or is_mem_fpr_st); if is_mem_gpr_st or is_mem_gpr_ld then tagM0 <= tag_y; else tagM0 <= "00000"; end if; if is_mem_fpr_st or is_mem_fpr_ld then tagFM0 <= tag_y; else tagFM0 <= "00000"; end if; end if; if opcode(3) = '0' then valM0 <= val_gpr_fwd_y; else valM0 <= val_fpr_fwd_y; end if; addr0 <= sram_addr(unsigned(val_gpr_fwd_x(19 downto 0)) + unsigned(imm_signed(19 downto 0))); end process; alu_map : ALU port map ( clk => clk, code => code_alu, tagD => tag_alu_d, valA => val_alu_fpu_a, valB => val_alu_fpu_b, emitTag => emit_tag_alu, emitVal => emit_val_alu); fpu_map : FPU port map ( clk => clk, code => code_fpu, tagD => tag_fpu_d, valA => val_alu_fpu_a, valB => val_alu_fpu_b, tag1 => pipe1_tag_fpu, tag2 => pipe2_tag_fpu, emitTag => emit_tag_fpu, emitVal => emit_val_fpu); branch_map : Branch port map (clk => clk, d => d_bra, q => q_bra); io_map : IO port map ( clk => clk, enable => enable_io, code => code_io, getTag => tag_spc_y, putVal => val_spc_x, blocking => blocking, emitTag => emit_tag_spc, emitVal => emit_val_spc, u232c_in => u232c_in, u232c_out => u232c_out, emit_instw => d_fet.w); -- TODO: separate sram into another component do_sram : process(clk) begin if rising_edge(clk) then -- phase 1 load1 <= load0; tagM1 <= tagM0; tagFM1 <= tagFM0; valM1 <= valM0; sramLoad <= load0; sramAddr <= addr0; -- phase 2 load2 <= load1; tagM2 <= tagM1; tagFM2 <= tagFM1; if (tagM1 /= "00000" and tagM1 = emitTagLoad) or (tagFM1 /= "00000" and tagFM1 = emitTagFLoad) then valM2 <= emitValM; else valM2 <= valM1; end if; fwdM_2 <= load3 and ((tagM1 /= "00000" and tagM1 = tagM3) or (tagFM1 /= "00000" and tagFM1 = tagFM3)); fwdM_1 <= load2 and ((tagM1 /= "00000" and tagM1 = tagM2) or (tagFM1 /= "00000" and tagFM1 = tagFM2)); -- phase 3 load3 <= load2; tagM3 <= tagM2; tagFM3 <= tagFM2; if load2 then sramData <= (others => 'Z'); else if fwdM_1 then sramData <= sramData; elsif fwdM_2 then sramData <= emitValM; else sramData <= valM2; end if; end if; -- phase 4 if load3 then emitTagLoad <= tagM3; emitTagFLoad <= tagFM3; else emitTagLoad <= "00000"; emitTagFLoad <= "00000"; end if; emitValM <= sramData; end if; end process; end behavioral;
entity assert7 is end entity; architecture test of assert7 is impure function func (x : integer) return integer is begin assert x > 0; return -x; end function; function resolved (x : bit_vector) return bit is begin return '1'; end function; subtype rbit is resolved bit; -- Disables init side effects temporarily signal s : rbit; -- Asserts during initialisation constant c : integer := func(-1); begin end architecture;
library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity mul_195 is port ( result : out std_logic_vector(31 downto 0); in_a : in std_logic_vector(31 downto 0); in_b : in std_logic_vector(14 downto 0) ); end mul_195; architecture augh of mul_195 is signal tmp_res : signed(46 downto 0); begin -- The actual multiplication tmp_res <= signed(in_a) * signed(in_b); -- Set the output result <= std_logic_vector(tmp_res(31 downto 0)); end architecture;
library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity mul_195 is port ( result : out std_logic_vector(31 downto 0); in_a : in std_logic_vector(31 downto 0); in_b : in std_logic_vector(14 downto 0) ); end mul_195; architecture augh of mul_195 is signal tmp_res : signed(46 downto 0); begin -- The actual multiplication tmp_res <= signed(in_a) * signed(in_b); -- Set the output result <= std_logic_vector(tmp_res(31 downto 0)); end architecture;
library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; entity s832_hot is port( clock: in std_logic; input: in std_logic_vector(17 downto 0); output: out std_logic_vector(18 downto 0) ); end s832_hot; architecture behaviour of s832_hot is constant s00000: std_logic_vector(24 downto 0) := "1000000000000000000000000"; constant s10000: std_logic_vector(24 downto 0) := "0100000000000000000000000"; constant s01110: std_logic_vector(24 downto 0) := "0010000000000000000000000"; constant s10001: std_logic_vector(24 downto 0) := "0001000000000000000000000"; constant s01111: std_logic_vector(24 downto 0) := "0000100000000000000000000"; constant s00010: std_logic_vector(24 downto 0) := "0000010000000000000000000"; constant s00001: std_logic_vector(24 downto 0) := "0000001000000000000000000"; constant s00100: std_logic_vector(24 downto 0) := "0000000100000000000000000"; constant s00011: std_logic_vector(24 downto 0) := "0000000010000000000000000"; constant s00101: std_logic_vector(24 downto 0) := "0000000001000000000000000"; constant s00110: std_logic_vector(24 downto 0) := "0000000000100000000000000"; constant s11111: std_logic_vector(24 downto 0) := "0000000000010000000000000"; constant s00111: std_logic_vector(24 downto 0) := "0000000000001000000000000"; constant s10111: std_logic_vector(24 downto 0) := "0000000000000100000000000"; constant s01011: std_logic_vector(24 downto 0) := "0000000000000010000000000"; constant s01000: std_logic_vector(24 downto 0) := "0000000000000001000000000"; constant s01100: std_logic_vector(24 downto 0) := "0000000000000000100000000"; constant s01101: std_logic_vector(24 downto 0) := "0000000000000000010000000"; constant s01001: std_logic_vector(24 downto 0) := "0000000000000000001000000"; constant s01010: std_logic_vector(24 downto 0) := "0000000000000000000100000"; constant s11000: std_logic_vector(24 downto 0) := "0000000000000000000010000"; constant s11011: std_logic_vector(24 downto 0) := "0000000000000000000001000"; constant s11001: std_logic_vector(24 downto 0) := "0000000000000000000000100"; constant s11010: std_logic_vector(24 downto 0) := "0000000000000000000000010"; constant s11100: std_logic_vector(24 downto 0) := "0000000000000000000000001"; signal current_state, next_state: std_logic_vector(24 downto 0); begin process(clock) begin if rising_edge(clock) then current_state <= next_state; end if; end process; process(input, current_state) begin next_state <= "-------------------------"; output <= "-------------------"; case current_state is when s00000 => if std_match(input, "-1---------------1") then next_state <= s00000; output <= "0001000000000010000"; elsif std_match(input, "-0-0------------11") then next_state <= s00000; output <= "0000000000000010001"; elsif std_match(input, "-0-0------------01") then next_state <= s00000; output <= "0000000000000010000"; elsif std_match(input, "-0-1------------11") then next_state <= s00000; output <= "0000000000000010001"; elsif std_match(input, "-0-1------------01") then next_state <= s00000; output <= "0010000000000010000"; elsif std_match(input, "-1---------------0") then next_state <= s10000; output <= "0001000000000010000"; elsif std_match(input, "-001------------00") then next_state <= s00000; output <= "0010000000000010000"; elsif std_match(input, "-000------------00") then next_state <= s00000; output <= "0000000000000010000"; elsif std_match(input, "-011------------00") then next_state <= s00000; output <= "0010000000000010000"; elsif std_match(input, "-010------------00") then next_state <= s01110; output <= "0000000000000010000"; elsif std_match(input, "-0--------------10") then next_state <= s10001; output <= "0000000000000010001"; end if; when s10000 => if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000000000000000"; elsif std_match(input, "1----------------0") then next_state <= s00000; output <= "0000000000000000000"; elsif std_match(input, "0----------------0") then next_state <= s10000; output <= "0000000000000000000"; end if; when s01110 => if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000001000000000"; elsif std_match(input, "-----------------0") then next_state <= s01111; output <= "0000000001000000000"; end if; when s01111 => if std_match(input, "----------------00") then next_state <= s00010; output <= "0000000000000010000"; elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000010000"; elsif std_match(input, "----------------11") then next_state <= s00000; output <= "0000010000000010000"; elsif std_match(input, "----------------10") then next_state <= s00001; output <= "0000010000000010000"; end if; when s00010 => if std_match(input, "--------------01-1") then next_state <= s00000; output <= "0000001000000000100"; elsif std_match(input, "--------------11-1") then next_state <= s00000; output <= "0000001000001000100"; elsif std_match(input, "--------------01-0") then next_state <= s00100; output <= "0000001000000000100"; elsif std_match(input, "--------------11-0") then next_state <= s00011; output <= "0000001000001000100"; elsif std_match(input, "---------------0-0") then next_state <= s00010; output <= "0000001000000000000"; elsif std_match(input, "---------------0-1") then next_state <= s00000; output <= "0000001000000000000"; end if; when s00100 => if std_match(input, "----0-1001-----110") then next_state <= s00101; output <= "0000000100000000000"; elsif std_match(input, "----0-0001-----110") then next_state <= s00100; output <= "0000000100000000000"; elsif std_match(input, "----0--101-----110") then next_state <= s00100; output <= "0000000100000000000"; elsif std_match(input, "----0---11-----110") then next_state <= s00100; output <= "0000000100000000000"; elsif std_match(input, "----0----0-----110") then next_state <= s00100; output <= "0000000100000000000"; elsif std_match(input, "----0----------010") then next_state <= s00100; output <= "0000000100000000000"; elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000"; elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001"; elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001"; elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001"; end if; when s00101 => if std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000"; elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000100000000001"; elsif std_match(input, "----0----------010") then next_state <= s00101; output <= "0000000100000000000"; elsif std_match(input, "----0----------110") then next_state <= s00110; output <= "0000000100000000000"; elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001"; end if; when s00001 => if std_match(input, "------0--------0-1") then next_state <= s00000; output <= "0000000000000000000"; elsif std_match(input, "------0--------010") then next_state <= s00001; output <= "0000000000000000000"; elsif std_match(input, "------0--------000") then next_state <= s00010; output <= "0000000000000000000"; elsif std_match(input, "------0--------101") then next_state <= s00000; output <= "0000000000000000000"; elsif std_match(input, "------0--------100") then next_state <= s00010; output <= "0000000000000000000"; elsif std_match(input, "------0--------111") then next_state <= s00000; output <= "0000000000000000000"; elsif std_match(input, "------0--------110") then next_state <= s00001; output <= "0000000000000000000"; elsif std_match(input, "------10---------1") then next_state <= s00000; output <= "0000000000000000000"; elsif std_match(input, "----1-10--------10") then next_state <= s00001; output <= "0000000000000000000"; elsif std_match(input, "----0-10-------010") then next_state <= s00001; output <= "0000000000000000000"; elsif std_match(input, "----0-10-------110") then next_state <= s00001; output <= "0000000000000000000"; elsif std_match(input, "------10--------00") then next_state <= s00010; output <= "0000000000000000000"; elsif std_match(input, "------110--------1") then next_state <= s00000; output <= "0000000000000000000"; elsif std_match(input, "----1-110-------10") then next_state <= s00001; output <= "0000000000000000000"; elsif std_match(input, "----0-110------010") then next_state <= s00001; output <= "0000000000000000000"; elsif std_match(input, "----0-110------110") then next_state <= s00001; output <= "0000000000000000000"; elsif std_match(input, "------110-------00") then next_state <= s00010; output <= "0000000000000000000"; elsif std_match(input, "------111--------1") then next_state <= s00000; output <= "0000000000000000000"; elsif std_match(input, "------1110-----010") then next_state <= s00001; output <= "0000000000000000000"; elsif std_match(input, "------1110-----000") then next_state <= s00010; output <= "0000000000000000000"; elsif std_match(input, "------1110-----110") then next_state <= s00001; output <= "0000000000000000000"; elsif std_match(input, "------1110-----100") then next_state <= s00010; output <= "0000000000000000000"; elsif std_match(input, "------1111------00") then next_state <= s00010; output <= "0000000000000000000"; elsif std_match(input, "------1111------10") then next_state <= s00001; output <= "0000000000000000000"; end if; when s00110 => if std_match(input, "----------------01") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000"; elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----1----------111") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----0-----110--111") then next_state <= s00000; output <= "0000100100000000000"; elsif std_match(input, "----0-----100--111") then next_state <= s00000; output <= "0000000100000000000"; elsif std_match(input, "----0-----0-0--111") then next_state <= s00000; output <= "0000000100000000000"; elsif std_match(input, "----0-----001--111") then next_state <= s00000; output <= "0000000100000000000"; elsif std_match(input, "----0-----101--111") then next_state <= s00000; output <= "0000100100000000000"; elsif std_match(input, "----0------11--111") then next_state <= s00000; output <= "0000100100000000000"; elsif std_match(input, "----1-----1------0") then next_state <= s00001; output <= "0000000100000000001"; elsif std_match(input, "----0-----1----000") then next_state <= s00010; output <= "0000000100000000001"; elsif std_match(input, "----0-----1----010") then next_state <= s00110; output <= "0000000100000000000"; elsif std_match(input, "----0-----11---110") then next_state <= s11111; output <= "0000100100000000000"; elsif std_match(input, "----0-----11---100") then next_state <= s00010; output <= "0000000100000000001"; elsif std_match(input, "----0-----10---100") then next_state <= s00010; output <= "0000000100000000001"; elsif std_match(input, "----0-----101--110") then next_state <= s11111; output <= "0000100100000000000"; elsif std_match(input, "----0-----100--110") then next_state <= s00111; output <= "0000000100000000000"; elsif std_match(input, "----1-----0------0") then next_state <= s00001; output <= "0000000100000000001"; elsif std_match(input, "----0-----0----010") then next_state <= s00110; output <= "0000000100000000000"; elsif std_match(input, "----0-----0----000") then next_state <= s00010; output <= "0000000100000000001"; elsif std_match(input, "----0-----011--110") then next_state <= s11111; output <= "0000100100000000000"; elsif std_match(input, "----0-----010--110") then next_state <= s10111; output <= "0000000100000000000"; elsif std_match(input, "----0-----01---100") then next_state <= s00010; output <= "0000000100000000001"; elsif std_match(input, "----0-----00---100") then next_state <= s00010; output <= "0000000100000000001"; elsif std_match(input, "----0-----00---110") then next_state <= s01011; output <= "0000000100000000000"; end if; when s11111 => if std_match(input, "0----------------1") then next_state <= s00000; output <= "0000000000000000000"; elsif std_match(input, "0----------------0") then next_state <= s11111; output <= "0000000000000000000"; elsif std_match(input, "1-----------------") then next_state <= s00000; output <= "0000000000000000000"; end if; when s00111 => if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000"; elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "0000000100000000001"; elsif std_match(input, "----0--------0-110") then next_state <= s01011; output <= "0000000100000000000"; elsif std_match(input, "----0--------1-110") then next_state <= s01000; output <= "0000000100000000000"; elsif std_match(input, "----0----------010") then next_state <= s00111; output <= "0000000100000000000"; elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001"; elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001"; elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001"; end if; when s01011 => if std_match(input, "----0----------010") then next_state <= s01011; output <= "0000000100000000000"; elsif std_match(input, "----0----------110") then next_state <= s01011; output <= "0000000100000000000"; elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000100010000000"; elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000"; elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100010000000"; elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000100000000001"; elsif std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000100000000001"; end if; when s01100 => if std_match(input, "-----0-----------1") then next_state <= s00000; output <= "0000000010000100000"; elsif std_match(input, "-----0-----------0") then next_state <= s01101; output <= "0000000010000100000"; elsif std_match(input, "-----1-----------1") then next_state <= s00000; output <= "0000000000000101000"; elsif std_match(input, "-----1-----------0") then next_state <= s00010; output <= "0000000000000101000"; end if; when s01101 => if std_match(input, "-1---------------1") then next_state <= s00000; output <= "0101000000000000010"; elsif std_match(input, "-1---------------0") then next_state <= s10000; output <= "0101000000000000010"; elsif std_match(input, "-0---------------1") then next_state <= s00000; output <= "0100000000000000010"; elsif std_match(input, "-010-------------0") then next_state <= s01110; output <= "0100000000000000010"; elsif std_match(input, "-000-------------0") then next_state <= s01101; output <= "0100000000000000010"; elsif std_match(input, "-0-1-------------0") then next_state <= s00000; output <= "0100000000000000010"; end if; when s01000 => if std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000"; elsif std_match(input, "----1----------111") then next_state <= s00000; output <= "0000000100100000001"; elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0000000100100000000"; elsif std_match(input, "----0----------010") then next_state <= s01000; output <= "0000000100000000000"; elsif std_match(input, "----0----------110") then next_state <= s01001; output <= "0000000100100000000"; elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "0000000100100000001"; elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001"; elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "---------------101") then next_state <= s00000; output <= "0000000100100000001"; elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0000000100100000001"; elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001"; elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000100000000001"; elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "0000000100100000001"; end if; when s01001 => if std_match(input, "----0----------010") then next_state <= s01001; output <= "0000000100000000000"; elsif std_match(input, "----0----------110") then next_state <= s01010; output <= "1000000100000000000"; elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000"; elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "1000000100000000000"; elsif std_match(input, "----1----------111") then next_state <= s00000; output <= "1000000100000000001"; elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001"; elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "1000000100000000001"; elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "---------------101") then next_state <= s00000; output <= "1000000100000000001"; elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000100000000001"; elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "1000000100000000001"; elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001"; elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "1000000100000000001"; end if; when s01010 => if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000"; elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001"; elsif std_match(input, "----0----------110") then next_state <= s01011; output <= "0000000100000000000"; elsif std_match(input, "----0----------010") then next_state <= s01010; output <= "0000000100000000000"; elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001"; elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001"; end if; when s10111 => if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000"; elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001"; elsif std_match(input, "----0----------010") then next_state <= s10111; output <= "0000000100000000000"; elsif std_match(input, "----0--------1-110") then next_state <= s11000; output <= "0000000100000000000"; elsif std_match(input, "----0--------0-110") then next_state <= s11011; output <= "0000000100000000000"; elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001"; elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001"; end if; when s11000 => if std_match(input, "---------------101") then next_state <= s00000; output <= "0000000100100000001"; elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0000000100100000000"; elsif std_match(input, "----1----------111") then next_state <= s00000; output <= "0000000100100000001"; elsif std_match(input, "----0----------001") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000"; elsif std_match(input, "----1----------0-1") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----1----------1-0") then next_state <= s00001; output <= "0000000100100000001"; elsif std_match(input, "----1----------0-0") then next_state <= s00001; output <= "0000000100000000001"; elsif std_match(input, "----0----------110") then next_state <= s11001; output <= "0000000100100000000"; elsif std_match(input, "----0----------010") then next_state <= s11000; output <= "0000000100000000000"; elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001"; elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0000000100100000001"; end if; when s11001 => if std_match(input, "----1----------111") then next_state <= s00000; output <= "1000000100000000001"; elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "1000000100000000000"; elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000"; elsif std_match(input, "----0----------110") then next_state <= s11010; output <= "1000000100000000000"; elsif std_match(input, "----0----------010") then next_state <= s11001; output <= "0000000100000000000"; elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "1000000100000000001"; elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001"; elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "---------------101") then next_state <= s00000; output <= "1000000100000000001"; elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000100000000001"; elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "1000000100000000001"; elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "1000000100000000001"; elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001"; end if; when s11010 => if std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000"; elsif std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000100000000001"; elsif std_match(input, "----0----------110") then next_state <= s11011; output <= "0000000100000000000"; elsif std_match(input, "----0----------010") then next_state <= s11010; output <= "0000000100000000000"; elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001"; end if; when s11011 => if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----0-0--------111") then next_state <= s00000; output <= "0000000100000000000"; elsif std_match(input, "----0-1011-----111") then next_state <= s00000; output <= "0000000100000000000"; elsif std_match(input, "----0-1111-----111") then next_state <= s00000; output <= "0000000100010000000"; elsif std_match(input, "----0-1-01-----111") then next_state <= s00000; output <= "0000000100000000000"; elsif std_match(input, "----0-1--0-----111") then next_state <= s00000; output <= "0000000100000000000"; elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000"; elsif std_match(input, "----0-0--1-----110") then next_state <= s11011; output <= "0000000100000000000"; elsif std_match(input, "----0-1011-----110") then next_state <= s11011; output <= "0000000100000000000"; elsif std_match(input, "----0-1111-----110") then next_state <= s11100; output <= "0000000100010000000"; elsif std_match(input, "----0-1-01-----110") then next_state <= s11011; output <= "0000000100000000000"; elsif std_match(input, "----0----0-----110") then next_state <= s11011; output <= "0000000100000000000"; elsif std_match(input, "----0----------010") then next_state <= s11011; output <= "0000000100000000000"; elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001"; elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100010000000"; elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001"; elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000100010000000"; end if; when s11100 => if std_match(input, "----0------------1") then next_state <= s00000; output <= "0000000100000000000"; elsif std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----0-----------10") then next_state <= s11100; output <= "0000000100000000000"; elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001"; elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000100000000000"; elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001"; end if; when s00011 => if std_match(input, "----1----------1-1") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0000000100000000000"; elsif std_match(input, "----0----------101") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----1----------1-0") then next_state <= s00001; output <= "0000000100000000001"; elsif std_match(input, "----0----------110") then next_state <= s00100; output <= "0000000100000000000"; elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0000000100000000001"; elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000"; elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001"; elsif std_match(input, "----0----------010") then next_state <= s00011; output <= "0000000100000000000"; elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000100000000001"; elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001"; elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000100000000001"; end if; when s10001 => if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000000000000000"; elsif std_match(input, "----------------00") then next_state <= s00000; output <= "0000000000000000000"; elsif std_match(input, "----------------10") then next_state <= s10001; output <= "0000000000000000000"; end if; when others => next_state <= "-------------------------"; output <= "-------------------"; end case; end process; end behaviour;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Register32X32 is Port( i_Clk : in std_logic; i_Data : in std_logic_vector(31 downto 0); i_Rst : in std_logic; i_w_en : in std_logic_vector(31 downto 0); i_rA_sel : in std_logic_vector(31 downto 0); i_rB_sel : in std_logic_vector(31 downto 0); o_Data_A : out std_logic_vector(31 downto 0); o_Data_B : out std_logic_vector(31 downto 0) ); end Register32X32; architecture Behavioral of Register32X32 is component Reg_Depth is Port ( i_Clk : in std_logic; i_Data : in std_logic_vector(31 downto 0); i_Rst : in std_logic; i_w_en : in std_logic; i_rA_sel : in std_logic; i_rB_sel : in std_logic; o_Data_A : out std_logic_vector(31 downto 0); o_Data_B : out std_logic_vector(31 downto 0) ); end component; begin Inst_Reg_Depth31: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(31), i_rA_sel => i_rA_sel(31), i_rB_sel => i_rB_sel(31), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth30: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(30), i_rA_sel => i_rA_sel(30), i_rB_sel => i_rB_sel(30), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth29: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(29), i_rA_sel => i_rA_sel(29), i_rB_sel => i_rB_sel(29), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth28: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(28), i_rA_sel => i_rA_sel(28), i_rB_sel => i_rB_sel(28), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth27: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(27), i_rA_sel => i_rA_sel(27), i_rB_sel => i_rB_sel(27), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth26: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(26), i_rA_sel => i_rA_sel(26), i_rB_sel => i_rB_sel(26), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth25: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(25), i_rA_sel => i_rA_sel(25), i_rB_sel => i_rB_sel(25), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth24: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(24), i_rA_sel => i_rA_sel(24), i_rB_sel => i_rB_sel(24), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth23: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(23), i_rA_sel => i_rA_sel(23), i_rB_sel => i_rB_sel(23), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth22: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(22), i_rA_sel => i_rA_sel(22), i_rB_sel => i_rB_sel(22), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth21: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(21), i_rA_sel => i_rA_sel(21), i_rB_sel => i_rB_sel(21), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth20: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(20), i_rA_sel => i_rA_sel(20), i_rB_sel => i_rB_sel(20), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth19: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(19), i_rA_sel => i_rA_sel(19), i_rB_sel => i_rB_sel(19), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth18: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(18), i_rA_sel => i_rA_sel(18), i_rB_sel => i_rB_sel(18), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth17: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(17), i_rA_sel => i_rA_sel(17), i_rB_sel => i_rB_sel(17), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth16: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(16), i_rA_sel => i_rA_sel(16), i_rB_sel => i_rB_sel(16), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth15: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(15), i_rA_sel => i_rA_sel(15), i_rB_sel => i_rB_sel(15), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth14: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(14), i_rA_sel => i_rA_sel(14), i_rB_sel => i_rB_sel(14), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth13: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(13), i_rA_sel => i_rA_sel(13), i_rB_sel => i_rB_sel(13), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth12: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(12), i_rA_sel => i_rA_sel(12), i_rB_sel => i_rB_sel(12), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth11: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(11), i_rA_sel => i_rA_sel(11), i_rB_sel => i_rB_sel(11), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth10: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(10), i_rA_sel => i_rA_sel(10), i_rB_sel => i_rB_sel(10), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth9: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(9), i_rA_sel => i_rA_sel(9), i_rB_sel => i_rB_sel(9), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth8: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(8), i_rA_sel => i_rA_sel(8), i_rB_sel => i_rB_sel(8), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth7: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(7), i_rA_sel => i_rA_sel(7), i_rB_sel => i_rB_sel(7), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth6: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(6), i_rA_sel => i_rA_sel(6), i_rB_sel => i_rB_sel(6), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth5: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(5), i_rA_sel => i_rA_sel(5), i_rB_sel => i_rB_sel(5), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth4: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(4), i_rA_sel => i_rA_sel(4), i_rB_sel => i_rB_sel(4), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth3: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(3), i_rA_sel => i_rA_sel(3), i_rB_sel => i_rB_sel(3), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth2: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(2), i_rA_sel => i_rA_sel(2), i_rB_sel => i_rB_sel(2), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth1: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(1), i_rA_sel => i_rA_sel(1), i_rB_sel => i_rB_sel(1), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth0: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(0), i_rA_sel => i_rA_sel(0), i_rB_sel => i_rB_sel(0), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Register32X32 is Port( i_Clk : in std_logic; i_Data : in std_logic_vector(31 downto 0); i_Rst : in std_logic; i_w_en : in std_logic_vector(31 downto 0); i_rA_sel : in std_logic_vector(31 downto 0); i_rB_sel : in std_logic_vector(31 downto 0); o_Data_A : out std_logic_vector(31 downto 0); o_Data_B : out std_logic_vector(31 downto 0) ); end Register32X32; architecture Behavioral of Register32X32 is component Reg_Depth is Port ( i_Clk : in std_logic; i_Data : in std_logic_vector(31 downto 0); i_Rst : in std_logic; i_w_en : in std_logic; i_rA_sel : in std_logic; i_rB_sel : in std_logic; o_Data_A : out std_logic_vector(31 downto 0); o_Data_B : out std_logic_vector(31 downto 0) ); end component; begin Inst_Reg_Depth31: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(31), i_rA_sel => i_rA_sel(31), i_rB_sel => i_rB_sel(31), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth30: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(30), i_rA_sel => i_rA_sel(30), i_rB_sel => i_rB_sel(30), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth29: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(29), i_rA_sel => i_rA_sel(29), i_rB_sel => i_rB_sel(29), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth28: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(28), i_rA_sel => i_rA_sel(28), i_rB_sel => i_rB_sel(28), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth27: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(27), i_rA_sel => i_rA_sel(27), i_rB_sel => i_rB_sel(27), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth26: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(26), i_rA_sel => i_rA_sel(26), i_rB_sel => i_rB_sel(26), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth25: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(25), i_rA_sel => i_rA_sel(25), i_rB_sel => i_rB_sel(25), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth24: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(24), i_rA_sel => i_rA_sel(24), i_rB_sel => i_rB_sel(24), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth23: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(23), i_rA_sel => i_rA_sel(23), i_rB_sel => i_rB_sel(23), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth22: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(22), i_rA_sel => i_rA_sel(22), i_rB_sel => i_rB_sel(22), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth21: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(21), i_rA_sel => i_rA_sel(21), i_rB_sel => i_rB_sel(21), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth20: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(20), i_rA_sel => i_rA_sel(20), i_rB_sel => i_rB_sel(20), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth19: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(19), i_rA_sel => i_rA_sel(19), i_rB_sel => i_rB_sel(19), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth18: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(18), i_rA_sel => i_rA_sel(18), i_rB_sel => i_rB_sel(18), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth17: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(17), i_rA_sel => i_rA_sel(17), i_rB_sel => i_rB_sel(17), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth16: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(16), i_rA_sel => i_rA_sel(16), i_rB_sel => i_rB_sel(16), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth15: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(15), i_rA_sel => i_rA_sel(15), i_rB_sel => i_rB_sel(15), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth14: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(14), i_rA_sel => i_rA_sel(14), i_rB_sel => i_rB_sel(14), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth13: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(13), i_rA_sel => i_rA_sel(13), i_rB_sel => i_rB_sel(13), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth12: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(12), i_rA_sel => i_rA_sel(12), i_rB_sel => i_rB_sel(12), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth11: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(11), i_rA_sel => i_rA_sel(11), i_rB_sel => i_rB_sel(11), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth10: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(10), i_rA_sel => i_rA_sel(10), i_rB_sel => i_rB_sel(10), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth9: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(9), i_rA_sel => i_rA_sel(9), i_rB_sel => i_rB_sel(9), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth8: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(8), i_rA_sel => i_rA_sel(8), i_rB_sel => i_rB_sel(8), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth7: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(7), i_rA_sel => i_rA_sel(7), i_rB_sel => i_rB_sel(7), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth6: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(6), i_rA_sel => i_rA_sel(6), i_rB_sel => i_rB_sel(6), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth5: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(5), i_rA_sel => i_rA_sel(5), i_rB_sel => i_rB_sel(5), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth4: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(4), i_rA_sel => i_rA_sel(4), i_rB_sel => i_rB_sel(4), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth3: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(3), i_rA_sel => i_rA_sel(3), i_rB_sel => i_rB_sel(3), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth2: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(2), i_rA_sel => i_rA_sel(2), i_rB_sel => i_rB_sel(2), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth1: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(1), i_rA_sel => i_rA_sel(1), i_rB_sel => i_rB_sel(1), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); Inst_Reg_Depth0: Reg_Depth port map( i_Clk => i_Clk, i_Data => i_Data, i_Rst => i_Rst, i_w_en => i_w_en(0), i_rA_sel => i_rA_sel(0), i_rB_sel => i_rB_sel(0), o_Data_A => o_Data_A, o_Data_B => o_Data_B ); end Behavioral;
-------------------------------------------------------------------------------- -- -- FIFO Generator Core Demo Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: cdcfifo_synth.vhd -- -- Description: -- This is the demo testbench for fifo_generator core. -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.STD_LOGIC_1164.ALL; USE ieee.STD_LOGIC_unsigned.ALL; USE IEEE.STD_LOGIC_arith.ALL; USE ieee.numeric_std.ALL; USE ieee.STD_LOGIC_misc.ALL; LIBRARY std; USE std.textio.ALL; LIBRARY work; USE work.cdcfifo_pkg.ALL; -------------------------------------------------------------------------------- -- Entity Declaration -------------------------------------------------------------------------------- ENTITY cdcfifo_synth IS GENERIC( FREEZEON_ERROR : INTEGER := 0; TB_STOP_CNT : INTEGER := 0; TB_SEED : INTEGER := 1 ); PORT( WR_CLK : IN STD_LOGIC; RD_CLK : IN STD_LOGIC; RESET : IN STD_LOGIC; SIM_DONE : OUT STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END ENTITY; ARCHITECTURE simulation_arch OF cdcfifo_synth IS -- FIFO interface signal declarations SIGNAL wr_clk_i : STD_LOGIC; SIGNAL rd_clk_i : STD_LOGIC; SIGNAL almost_full : STD_LOGIC; SIGNAL almost_empty : STD_LOGIC; SIGNAL rst : STD_LOGIC; SIGNAL wr_en : STD_LOGIC; SIGNAL rd_en : STD_LOGIC; SIGNAL din : STD_LOGIC_VECTOR(8-1 DOWNTO 0); SIGNAL dout : STD_LOGIC_VECTOR(8-1 DOWNTO 0); SIGNAL full : STD_LOGIC; SIGNAL empty : STD_LOGIC; -- TB Signals SIGNAL wr_data : STD_LOGIC_VECTOR(8-1 DOWNTO 0); SIGNAL dout_i : STD_LOGIC_VECTOR(8-1 DOWNTO 0); SIGNAL wr_en_i : STD_LOGIC := '0'; SIGNAL rd_en_i : STD_LOGIC := '0'; SIGNAL full_i : STD_LOGIC := '0'; SIGNAL empty_i : STD_LOGIC := '0'; SIGNAL almost_full_i : STD_LOGIC := '0'; SIGNAL almost_empty_i : STD_LOGIC := '0'; SIGNAL prc_we_i : STD_LOGIC := '0'; SIGNAL prc_re_i : STD_LOGIC := '0'; SIGNAL dout_chk_i : STD_LOGIC := '0'; SIGNAL rst_int_rd : STD_LOGIC := '0'; SIGNAL rst_int_wr : STD_LOGIC := '0'; SIGNAL rst_s_wr1 : STD_LOGIC := '0'; SIGNAL rst_s_wr2 : STD_LOGIC := '0'; SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL rst_s_wr3 : STD_LOGIC := '0'; SIGNAL rst_s_rd : STD_LOGIC := '0'; SIGNAL reset_en : STD_LOGIC := '0'; SIGNAL rst_async_wr1 : STD_LOGIC := '0'; SIGNAL rst_async_wr2 : STD_LOGIC := '0'; SIGNAL rst_async_wr3 : STD_LOGIC := '0'; SIGNAL rst_async_rd1 : STD_LOGIC := '0'; SIGNAL rst_async_rd2 : STD_LOGIC := '0'; SIGNAL rst_async_rd3 : STD_LOGIC := '0'; BEGIN ---- Reset generation logic ----- rst_int_wr <= rst_async_wr3 OR rst_s_wr3; rst_int_rd <= rst_async_rd3 OR rst_s_rd; --Testbench reset synchronization PROCESS(rd_clk_i,RESET) BEGIN IF(RESET = '1') THEN rst_async_rd1 <= '1'; rst_async_rd2 <= '1'; rst_async_rd3 <= '1'; ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN rst_async_rd1 <= RESET; rst_async_rd2 <= rst_async_rd1; rst_async_rd3 <= rst_async_rd2; END IF; END PROCESS; PROCESS(wr_clk_i,RESET) BEGIN IF(RESET = '1') THEN rst_async_wr1 <= '1'; rst_async_wr2 <= '1'; rst_async_wr3 <= '1'; ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN rst_async_wr1 <= RESET; rst_async_wr2 <= rst_async_wr1; rst_async_wr3 <= rst_async_wr2; END IF; END PROCESS; --Soft reset for core and testbench PROCESS(rd_clk_i) BEGIN IF(rd_clk_i'event AND rd_clk_i='1') THEN rst_gen_rd <= rst_gen_rd + "1"; IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN rst_s_rd <= '1'; assert false report "Reset applied..Memory Collision checks are not valid" severity note; ELSE IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN rst_s_rd <= '0'; END IF; END IF; END IF; END PROCESS; PROCESS(wr_clk_i) BEGIN IF(wr_clk_i'event AND wr_clk_i='1') THEN rst_s_wr1 <= rst_s_rd; rst_s_wr2 <= rst_s_wr1; rst_s_wr3 <= rst_s_wr2; IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN assert false report "Reset removed..Memory Collision checks are valid" severity note; END IF; END IF; END PROCESS; ------------------ ---- Clock buffers for testbench ---- wr_clk_i <= WR_CLK; rd_clk_i <= RD_CLK; ------------------ rst <= RESET OR rst_s_rd AFTER 12 ns; din <= wr_data; dout_i <= dout; wr_en <= wr_en_i; rd_en <= rd_en_i; full_i <= full; empty_i <= empty; almost_empty_i <= almost_empty; almost_full_i <= almost_full; fg_dg_nv: cdcfifo_dgen GENERIC MAP ( C_DIN_WIDTH => 8, C_DOUT_WIDTH => 8, TB_SEED => TB_SEED, C_CH_TYPE => 0 ) PORT MAP ( -- Write Port RESET => rst_int_wr, WR_CLK => wr_clk_i, PRC_WR_EN => prc_we_i, FULL => full_i, WR_EN => wr_en_i, WR_DATA => wr_data ); fg_dv_nv: cdcfifo_dverif GENERIC MAP ( C_DOUT_WIDTH => 8, C_DIN_WIDTH => 8, C_USE_EMBEDDED_REG => 0, TB_SEED => TB_SEED, C_CH_TYPE => 0 ) PORT MAP( RESET => rst_int_rd, RD_CLK => rd_clk_i, PRC_RD_EN => prc_re_i, RD_EN => rd_en_i, EMPTY => empty_i, DATA_OUT => dout_i, DOUT_CHK => dout_chk_i ); fg_pc_nv: cdcfifo_pctrl GENERIC MAP ( AXI_CHANNEL => "Native", C_APPLICATION_TYPE => 0, C_DOUT_WIDTH => 8, C_DIN_WIDTH => 8, C_WR_PNTR_WIDTH => 11, C_RD_PNTR_WIDTH => 11, C_CH_TYPE => 0, FREEZEON_ERROR => FREEZEON_ERROR, TB_SEED => TB_SEED, TB_STOP_CNT => TB_STOP_CNT ) PORT MAP( RESET_WR => rst_int_wr, RESET_RD => rst_int_rd, RESET_EN => reset_en, WR_CLK => wr_clk_i, RD_CLK => rd_clk_i, PRC_WR_EN => prc_we_i, PRC_RD_EN => prc_re_i, FULL => full_i, ALMOST_FULL => almost_full_i, ALMOST_EMPTY => almost_empty_i, DOUT_CHK => dout_chk_i, EMPTY => empty_i, DATA_IN => wr_data, DATA_OUT => dout, SIM_DONE => SIM_DONE, STATUS => STATUS ); cdcfifo_inst : cdcfifo_exdes PORT MAP ( WR_CLK => wr_clk_i, RD_CLK => rd_clk_i, ALMOST_FULL => almost_full, ALMOST_EMPTY => almost_empty, RST => rst, WR_EN => wr_en, RD_EN => rd_en, DIN => din, DOUT => dout, FULL => full, EMPTY => empty); END ARCHITECTURE;